blob: 5c11ae66b5d8ed872aee750230a026e86059fd52 [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +00001// SPDX-License-Identifier: GPL-2.0-only
Andrew Scullb4b6d4a2019-01-02 15:54:55 +00002/*
3 * Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and
4 * initial domain support. We also handle the DSDT _PRT callbacks for GSI's
5 * used in HVM and initial domain mode (PV does not parse ACPI, so it has no
6 * concept of GSIs). Under PV we hook under the pnbbios API for IRQs and
7 * 0xcf8 PCI configuration read/write.
8 *
9 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
10 * Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
11 * Stefano Stabellini <stefano.stabellini@eu.citrix.com>
12 */
13#include <linux/export.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/acpi.h>
17
18#include <linux/io.h>
19#include <asm/io_apic.h>
20#include <asm/pci_x86.h>
21
22#include <asm/xen/hypervisor.h>
23
24#include <xen/features.h>
25#include <xen/events.h>
26#include <asm/xen/pci.h>
27#include <asm/xen/cpuid.h>
28#include <asm/apic.h>
Olivier Deprez0e641232021-09-23 10:07:05 +020029#include <asm/acpi.h>
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000030#include <asm/i8259.h>
31
32static int xen_pcifront_enable_irq(struct pci_dev *dev)
33{
34 int rc;
35 int share = 1;
36 int pirq;
37 u8 gsi;
38
39 rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
40 if (rc < 0) {
41 dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
42 rc);
43 return rc;
44 }
45 /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
46 pirq = gsi;
47
48 if (gsi < nr_legacy_irqs())
49 share = 0;
50
51 rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
52 if (rc < 0) {
53 dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
54 gsi, pirq, rc);
55 return rc;
56 }
57
58 dev->irq = rc;
59 dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
60 return 0;
61}
62
63#ifdef CONFIG_ACPI
64static int xen_register_pirq(u32 gsi, int gsi_override, int triggering,
65 bool set_pirq)
66{
67 int rc, pirq = -1, irq = -1;
68 struct physdev_map_pirq map_irq;
69 int shareable = 0;
70 char *name;
71
72 irq = xen_irq_from_gsi(gsi);
73 if (irq > 0)
74 return irq;
75
76 if (set_pirq)
77 pirq = gsi;
78
79 map_irq.domid = DOMID_SELF;
80 map_irq.type = MAP_PIRQ_TYPE_GSI;
81 map_irq.index = gsi;
82 map_irq.pirq = pirq;
83
84 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
85 if (rc) {
86 printk(KERN_WARNING "xen map irq failed %d\n", rc);
87 return -1;
88 }
89
90 if (triggering == ACPI_EDGE_SENSITIVE) {
91 shareable = 0;
92 name = "ioapic-edge";
93 } else {
94 shareable = 1;
95 name = "ioapic-level";
96 }
97
98 if (gsi_override >= 0)
99 gsi = gsi_override;
100
101 irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);
102 if (irq < 0)
103 goto out;
104
105 printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi);
106out:
107 return irq;
108}
109
110static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
111 int trigger, int polarity)
112{
113 if (!xen_hvm_domain())
114 return -1;
115
116 return xen_register_pirq(gsi, -1 /* no GSI override */, trigger,
117 false /* no mapping of GSI to PIRQ */);
118}
119
120#ifdef CONFIG_XEN_DOM0
121static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polarity)
122{
123 int rc, irq;
124 struct physdev_setup_gsi setup_gsi;
125
126 if (!xen_pv_domain())
127 return -1;
128
129 printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
130 gsi, triggering, polarity);
131
132 irq = xen_register_pirq(gsi, gsi_override, triggering, true);
133
134 setup_gsi.gsi = gsi;
135 setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
136 setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
137
138 rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
139 if (rc == -EEXIST)
140 printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
141 else if (rc) {
142 printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
143 gsi, rc);
144 }
145
146 return irq;
147}
148
149static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
150 int trigger, int polarity)
151{
152 return xen_register_gsi(gsi, -1 /* no GSI override */, trigger, polarity);
153}
154#endif
155#endif
156
157#if defined(CONFIG_PCI_MSI)
158#include <linux/msi.h>
159#include <asm/msidef.h>
160
161struct xen_pci_frontend_ops *xen_pci_frontend;
162EXPORT_SYMBOL_GPL(xen_pci_frontend);
163
164static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
165{
166 int irq, ret, i;
167 struct msi_desc *msidesc;
168 int *v;
169
170 if (type == PCI_CAP_ID_MSI && nvec > 1)
171 return 1;
172
173 v = kcalloc(max(1, nvec), sizeof(int), GFP_KERNEL);
174 if (!v)
175 return -ENOMEM;
176
177 if (type == PCI_CAP_ID_MSIX)
178 ret = xen_pci_frontend_enable_msix(dev, v, nvec);
179 else
180 ret = xen_pci_frontend_enable_msi(dev, v);
181 if (ret)
182 goto error;
183 i = 0;
184 for_each_pci_msi_entry(msidesc, dev) {
185 irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
186 (type == PCI_CAP_ID_MSI) ? nvec : 1,
187 (type == PCI_CAP_ID_MSIX) ?
188 "pcifront-msi-x" :
189 "pcifront-msi",
190 DOMID_SELF);
191 if (irq < 0) {
192 ret = irq;
193 goto free;
194 }
195 i++;
196 }
197 kfree(v);
198 return 0;
199
200error:
201 if (ret == -ENOSYS)
202 dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
203 else if (ret)
204 dev_err(&dev->dev, "Xen PCI frontend error: %d!\n", ret);
205free:
206 kfree(v);
207 return ret;
208}
209
210#define XEN_PIRQ_MSI_DATA (MSI_DATA_TRIGGER_EDGE | \
211 MSI_DATA_LEVEL_ASSERT | (3 << 8) | MSI_DATA_VECTOR(0))
212
213static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
214 struct msi_msg *msg)
215{
216 /* We set vector == 0 to tell the hypervisor we don't care about it,
217 * but we want a pirq setup instead.
218 * We use the dest_id field to pass the pirq that we want. */
219 msg->address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(pirq);
220 msg->address_lo =
221 MSI_ADDR_BASE_LO |
222 MSI_ADDR_DEST_MODE_PHYSICAL |
223 MSI_ADDR_REDIRECTION_CPU |
224 MSI_ADDR_DEST_ID(pirq);
225
226 msg->data = XEN_PIRQ_MSI_DATA;
227}
228
229static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
230{
231 int irq, pirq;
232 struct msi_desc *msidesc;
233 struct msi_msg msg;
234
235 if (type == PCI_CAP_ID_MSI && nvec > 1)
236 return 1;
237
238 for_each_pci_msi_entry(msidesc, dev) {
239 pirq = xen_allocate_pirq_msi(dev, msidesc);
240 if (pirq < 0) {
241 irq = -ENODEV;
242 goto error;
243 }
244 xen_msi_compose_msg(dev, pirq, &msg);
245 __pci_write_msi_msg(msidesc, &msg);
246 dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq);
247 irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
248 (type == PCI_CAP_ID_MSI) ? nvec : 1,
249 (type == PCI_CAP_ID_MSIX) ?
250 "msi-x" : "msi",
251 DOMID_SELF);
252 if (irq < 0)
253 goto error;
254 dev_dbg(&dev->dev,
255 "xen: msi --> pirq=%d --> irq=%d\n", pirq, irq);
256 }
257 return 0;
258
259error:
260 dev_err(&dev->dev, "Failed to create MSI%s! ret=%d!\n",
261 type == PCI_CAP_ID_MSI ? "" : "-X", irq);
262 return irq;
263}
264
265#ifdef CONFIG_XEN_DOM0
266static bool __read_mostly pci_seg_supported = true;
267
268static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
269{
270 int ret = 0;
271 struct msi_desc *msidesc;
272
273 for_each_pci_msi_entry(msidesc, dev) {
274 struct physdev_map_pirq map_irq;
275 domid_t domid;
276
277 domid = ret = xen_find_device_domain_owner(dev);
278 /* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED,
279 * hence check ret value for < 0. */
280 if (ret < 0)
281 domid = DOMID_SELF;
282
283 memset(&map_irq, 0, sizeof(map_irq));
284 map_irq.domid = domid;
285 map_irq.type = MAP_PIRQ_TYPE_MSI_SEG;
286 map_irq.index = -1;
287 map_irq.pirq = -1;
288 map_irq.bus = dev->bus->number |
289 (pci_domain_nr(dev->bus) << 16);
290 map_irq.devfn = dev->devfn;
291
292 if (type == PCI_CAP_ID_MSI && nvec > 1) {
293 map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
294 map_irq.entry_nr = nvec;
295 } else if (type == PCI_CAP_ID_MSIX) {
296 int pos;
297 unsigned long flags;
298 u32 table_offset, bir;
299
300 pos = dev->msix_cap;
301 pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
302 &table_offset);
303 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
304 flags = pci_resource_flags(dev, bir);
305 if (!flags || (flags & IORESOURCE_UNSET))
306 return -EINVAL;
307
308 map_irq.table_base = pci_resource_start(dev, bir);
309 map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
310 }
311
312 ret = -EINVAL;
313 if (pci_seg_supported)
314 ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
315 &map_irq);
316 if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) {
317 /*
318 * If MAP_PIRQ_TYPE_MULTI_MSI is not available
319 * there's nothing else we can do in this case.
320 * Just set ret > 0 so driver can retry with
321 * single MSI.
322 */
323 ret = 1;
324 goto out;
325 }
326 if (ret == -EINVAL && !pci_domain_nr(dev->bus)) {
327 map_irq.type = MAP_PIRQ_TYPE_MSI;
328 map_irq.index = -1;
329 map_irq.pirq = -1;
330 map_irq.bus = dev->bus->number;
331 ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
332 &map_irq);
333 if (ret != -EINVAL)
334 pci_seg_supported = false;
335 }
336 if (ret) {
337 dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n",
338 ret, domid);
339 goto out;
340 }
341
342 ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq,
343 (type == PCI_CAP_ID_MSI) ? nvec : 1,
344 (type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi",
345 domid);
346 if (ret < 0)
347 goto out;
348 }
349 ret = 0;
350out:
351 return ret;
352}
353
354static void xen_initdom_restore_msi_irqs(struct pci_dev *dev)
355{
356 int ret = 0;
357
358 if (pci_seg_supported) {
359 struct physdev_pci_device restore_ext;
360
361 restore_ext.seg = pci_domain_nr(dev->bus);
362 restore_ext.bus = dev->bus->number;
363 restore_ext.devfn = dev->devfn;
364 ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
365 &restore_ext);
366 if (ret == -ENOSYS)
367 pci_seg_supported = false;
368 WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
369 }
370 if (!pci_seg_supported) {
371 struct physdev_restore_msi restore;
372
373 restore.bus = dev->bus->number;
374 restore.devfn = dev->devfn;
375 ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
376 WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
377 }
378}
379#endif
380
381static void xen_teardown_msi_irqs(struct pci_dev *dev)
382{
383 struct msi_desc *msidesc;
384
385 msidesc = first_pci_msi_entry(dev);
386 if (msidesc->msi_attrib.is_msix)
387 xen_pci_frontend_disable_msix(dev);
388 else
389 xen_pci_frontend_disable_msi(dev);
390
391 /* Free the IRQ's and the msidesc using the generic code. */
392 default_teardown_msi_irqs(dev);
393}
394
395static void xen_teardown_msi_irq(unsigned int irq)
396{
397 xen_destroy_irq(irq);
398}
399
400#endif
401
402int __init pci_xen_init(void)
403{
404 if (!xen_pv_domain() || xen_initial_domain())
405 return -ENODEV;
406
407 printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");
408
409 pcibios_set_cache_line_size();
410
411 pcibios_enable_irq = xen_pcifront_enable_irq;
412 pcibios_disable_irq = NULL;
413
414 /* Keep ACPI out of the picture */
415 acpi_noirq_set();
416
417#ifdef CONFIG_PCI_MSI
418 x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
419 x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
420 x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs;
421 pci_msi_ignore_mask = 1;
422#endif
423 return 0;
424}
425
426#ifdef CONFIG_PCI_MSI
427void __init xen_msi_init(void)
428{
429 if (!disable_apic) {
430 /*
431 * If hardware supports (x2)APIC virtualization (as indicated
432 * by hypervisor's leaf 4) then we don't need to use pirqs/
433 * event channels for MSI handling and instead use regular
434 * APIC processing
435 */
436 uint32_t eax = cpuid_eax(xen_cpuid_base() + 4);
437
438 if (((eax & XEN_HVM_CPUID_X2APIC_VIRT) && x2apic_mode) ||
439 ((eax & XEN_HVM_CPUID_APIC_ACCESS_VIRT) && boot_cpu_has(X86_FEATURE_APIC)))
440 return;
441 }
442
443 x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs;
444 x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
445}
446#endif
447
448int __init pci_xen_hvm_init(void)
449{
450 if (!xen_have_vector_callback || !xen_feature(XENFEAT_hvm_pirqs))
451 return 0;
452
453#ifdef CONFIG_ACPI
454 /*
455 * We don't want to change the actual ACPI delivery model,
456 * just how GSIs get registered.
457 */
458 __acpi_register_gsi = acpi_register_gsi_xen_hvm;
459 __acpi_unregister_gsi = NULL;
460#endif
461
462#ifdef CONFIG_PCI_MSI
463 /*
464 * We need to wait until after x2apic is initialized
465 * before we can set MSI IRQ ops.
466 */
467 x86_platform.apic_post_init = xen_msi_init;
468#endif
469 return 0;
470}
471
472#ifdef CONFIG_XEN_DOM0
473int __init pci_xen_initial_domain(void)
474{
475 int irq;
476
477#ifdef CONFIG_PCI_MSI
478 x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
479 x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
480 x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
481 pci_msi_ignore_mask = 1;
482#endif
483 __acpi_register_gsi = acpi_register_gsi_xen;
484 __acpi_unregister_gsi = NULL;
485 /*
486 * Pre-allocate the legacy IRQs. Use NR_LEGACY_IRQS here
487 * because we don't have a PIC and thus nr_legacy_irqs() is zero.
488 */
489 for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
490 int trigger, polarity;
491
492 if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
493 continue;
494
495 xen_register_pirq(irq, -1 /* no GSI override */,
496 trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,
497 true /* Map GSI to PIRQ */);
498 }
499 if (0 == nr_ioapics) {
500 for (irq = 0; irq < nr_legacy_irqs(); irq++)
501 xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
502 }
503 return 0;
504}
505
506struct xen_device_domain_owner {
507 domid_t domain;
508 struct pci_dev *dev;
509 struct list_head list;
510};
511
512static DEFINE_SPINLOCK(dev_domain_list_spinlock);
513static struct list_head dev_domain_list = LIST_HEAD_INIT(dev_domain_list);
514
515static struct xen_device_domain_owner *find_device(struct pci_dev *dev)
516{
517 struct xen_device_domain_owner *owner;
518
519 list_for_each_entry(owner, &dev_domain_list, list) {
520 if (owner->dev == dev)
521 return owner;
522 }
523 return NULL;
524}
525
526int xen_find_device_domain_owner(struct pci_dev *dev)
527{
528 struct xen_device_domain_owner *owner;
529 int domain = -ENODEV;
530
531 spin_lock(&dev_domain_list_spinlock);
532 owner = find_device(dev);
533 if (owner)
534 domain = owner->domain;
535 spin_unlock(&dev_domain_list_spinlock);
536 return domain;
537}
538EXPORT_SYMBOL_GPL(xen_find_device_domain_owner);
539
540int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain)
541{
542 struct xen_device_domain_owner *owner;
543
544 owner = kzalloc(sizeof(struct xen_device_domain_owner), GFP_KERNEL);
545 if (!owner)
546 return -ENODEV;
547
548 spin_lock(&dev_domain_list_spinlock);
549 if (find_device(dev)) {
550 spin_unlock(&dev_domain_list_spinlock);
551 kfree(owner);
552 return -EEXIST;
553 }
554 owner->domain = domain;
555 owner->dev = dev;
556 list_add_tail(&owner->list, &dev_domain_list);
557 spin_unlock(&dev_domain_list_spinlock);
558 return 0;
559}
560EXPORT_SYMBOL_GPL(xen_register_device_domain_owner);
561
562int xen_unregister_device_domain_owner(struct pci_dev *dev)
563{
564 struct xen_device_domain_owner *owner;
565
566 spin_lock(&dev_domain_list_spinlock);
567 owner = find_device(dev);
568 if (!owner) {
569 spin_unlock(&dev_domain_list_spinlock);
570 return -ENODEV;
571 }
572 list_del(&owner->list);
573 spin_unlock(&dev_domain_list_spinlock);
574 kfree(owner);
575 return 0;
576}
577EXPORT_SYMBOL_GPL(xen_unregister_device_domain_owner);
578#endif