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review.trustedfirmware.org / hafnium / third_party / linux / 0e64123141f3854e695eb4924d82b52856691466 / . / arch / powerpc / include / asm / pnv-pci.h
blob: edcb1fc50aebc5adef08352390b94a295ff80c0c [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-or-later */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]2/*
3 * Copyright 2014 IBM Corp.
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]4 */
5
6#ifndef _ASM_PNV_PCI_H
7#define _ASM_PNV_PCI_H
8
9#include <linux/pci.h>
10#include <linux/pci_hotplug.h>
11#include <linux/irq.h>
12#include <misc/cxl-base.h>
13#include <asm/opal-api.h>
14
15#define PCI_SLOT_ID_PREFIX (1UL << 63)
16#define PCI_SLOT_ID(phb_id, bdfn) \
17 (PCI_SLOT_ID_PREFIX | ((uint64_t)(bdfn) << 16) | (phb_id))
18
19extern int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id);
20extern int pnv_pci_get_device_tree(uint32_t phandle, void *buf, uint64_t len);
21extern int pnv_pci_get_presence_state(uint64_t id, uint8_t *state);
22extern int pnv_pci_get_power_state(uint64_t id, uint8_t *state);
23extern int pnv_pci_set_power_state(uint64_t id, uint8_t state,
24 struct opal_msg *msg);
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]25
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]26extern int pnv_pci_set_tunnel_bar(struct pci_dev *dev, uint64_t addr,
27 int enable);
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]28int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode);
29int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
30 unsigned int virq);
31int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num);
32void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num);
33int pnv_cxl_get_irq_count(struct pci_dev *dev);
34struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev);
35int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq);
36bool is_pnv_opal_msi(struct irq_chip *chip);
37
38#ifdef CONFIG_CXL_BASE
39int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
40 struct pci_dev *dev, int num);
41void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
42 struct pci_dev *dev);
43#endif
44
45struct pnv_php_slot {
46 struct hotplug_slot slot;
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]47 uint64_t id;
48 char *name;
49 int slot_no;
50 unsigned int flags;
51#define PNV_PHP_FLAG_BROKEN_PDC 0x1
52 struct kref kref;
53#define PNV_PHP_STATE_INITIALIZED 0
54#define PNV_PHP_STATE_REGISTERED 1
55#define PNV_PHP_STATE_POPULATED 2
56#define PNV_PHP_STATE_OFFLINE 3
57 int state;
58 int irq;
59 struct workqueue_struct *wq;
60 struct device_node *dn;
61 struct pci_dev *pdev;
62 struct pci_bus *bus;
63 bool power_state_check;
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]64 u8 attention_state;
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]65 void *fdt;
66 void *dt;
67 struct of_changeset ocs;
68 struct pnv_php_slot *parent;
69 struct list_head children;
70 struct list_head link;
71};
72extern struct pnv_php_slot *pnv_php_find_slot(struct device_node *dn);
73extern int pnv_php_set_slot_power_state(struct hotplug_slot *slot,
74 uint8_t state);
75
76#endif