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review.trustedfirmware.org / hafnium / third_party / linux / 0e64123141f3854e695eb4924d82b52856691466 / . / arch / arm / boot / dts / imx6dl-yapp4-common.dtsi
blob: ce4a5a807442236093b269d6bba1dce553a1d2f9 [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (C) 2015-2018 Y Soft Corporation, a.s.
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/pwm/pwm.h>
8
9/ {
10 backlight: backlight {
11 compatible = "pwm-backlight";
12 pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
13 brightness-levels = <0 32 64 128 255>;
14 default-brightness-level = <32>;
15 num-interpolated-steps = <8>;
16 power-supply = <&sw2_reg>;
17 status = "disabled";
18 };
19
20 lcd_display: display {
21 compatible = "fsl,imx-parallel-display";
22 #address-cells = <1>;
23 #size-cells = <0>;
24 interface-pix-fmt = "rgb24";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_ipu1>;
27 status = "disabled";
28
29 port@0 {
30 reg = <0>;
31
32 lcd_display_in: endpoint {
33 remote-endpoint = <&ipu1_di0_disp0>;
34 };
35 };
36
37 port@1 {
38 reg = <1>;
39
40 lcd_display_out: endpoint {
41 remote-endpoint = <&lcd_panel_in>;
42 };
43 };
44 };
45
46 panel: panel {
47 compatible = "dataimage,scf0700c48ggu18";
48 power-supply = <&sw2_reg>;
49 status = "disabled";
50
51 port {
52 lcd_panel_in: endpoint {
53 remote-endpoint = <&lcd_display_out>;
54 };
55 };
56 };
57
58 reg_pcie: regulator-pcie {
59 compatible = "regulator-fixed";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_pcie_reg>;
62 regulator-name = "MPCIE_3V3";
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
66 enable-active-high;
67 status = "disabled";
68 };
69
70 reg_usb_h1_vbus: regulator-usb-h1-vbus {
71 compatible = "regulator-fixed";
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_usbh1_vbus>;
74 regulator-name = "usb_h1_vbus";
75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <5000000>;
77 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
78 enable-active-high;
79 status = "disabled";
80 };
81
82 reg_usb_otg_vbus: regulator-usb-otg-vbus {
83 compatible = "regulator-fixed";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_usbotg_vbus>;
86 regulator-name = "usb_otg_vbus";
87 regulator-min-microvolt = <5000000>;
88 regulator-max-microvolt = <5000000>;
89 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
90 enable-active-high;
91 status = "okay";
92 };
93};
94
95&fec {
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_enet>;
98 phy-mode = "rgmii-id";
99 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
100 phy-reset-duration = <20>;
101 phy-supply = <&sw2_reg>;
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]102 status = "okay";
103
Olivier Deprez0e641232021-09-23 10:07:05 +0200[diff] [blame^]104 fixed-link {
105 speed = <1000>;
106 full-duplex;
107 };
108
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]109 mdio {
110 #address-cells = <1>;
111 #size-cells = <0>;
112
113 phy_port2: phy@1 {
114 reg = <1>;
115 };
116
117 phy_port3: phy@2 {
118 reg = <2>;
119 };
120
121 switch@10 {
122 compatible = "qca,qca8334";
123 reg = <10>;
124
125 switch_ports: ports {
126 #address-cells = <1>;
127 #size-cells = <0>;
128
129 ethphy0: port@0 {
130 reg = <0>;
131 label = "cpu";
132 phy-mode = "rgmii-id";
133 ethernet = <&fec>;
134
135 fixed-link {
136 speed = <1000>;
137 full-duplex;
138 };
139 };
140
141 port@2 {
142 reg = <2>;
143 label = "eth2";
144 phy-handle = <&phy_port2>;
145 };
146
147 port@3 {
148 reg = <3>;
149 label = "eth1";
150 phy-handle = <&phy_port3>;
151 };
152 };
153 };
154 };
155};
156
157&hdmi {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_hdmi_cec>;
160 ddc-i2c-bus = <&i2c2>;
161 status = "disabled";
162};
163
164&i2c2 {
165 clock-frequency = <100000>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_i2c2>;
168 status = "okay";
169
170 pmic@8 {
171 compatible = "fsl,pfuze200";
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_pmic>;
174 reg = <0x8>;
175
176 regulators {
177 sw1a_reg: sw1ab {
178 regulator-min-microvolt = <300000>;
179 regulator-max-microvolt = <1875000>;
180 regulator-boot-on;
181 regulator-always-on;
182 regulator-ramp-delay = <6250>;
183 };
184
185 sw2_reg: sw2 {
186 regulator-min-microvolt = <800000>;
187 regulator-max-microvolt = <3300000>;
188 regulator-boot-on;
189 regulator-always-on;
190 };
191
192 sw3a_reg: sw3a {
193 regulator-min-microvolt = <400000>;
194 regulator-max-microvolt = <1975000>;
195 regulator-boot-on;
196 regulator-always-on;
197 };
198
199 sw3b_reg: sw3b {
200 regulator-min-microvolt = <400000>;
201 regulator-max-microvolt = <1975000>;
202 regulator-boot-on;
203 regulator-always-on;
204 };
205
206 swbst_reg: swbst {
207 regulator-min-microvolt = <5000000>;
208 regulator-max-microvolt = <5150000>;
209 };
210
211 vgen1_reg: vgen1 {
212 regulator-min-microvolt = <800000>;
213 regulator-max-microvolt = <1550000>;
214 };
215
216 vgen2_reg: vgen2 {
217 regulator-min-microvolt = <800000>;
218 regulator-max-microvolt = <1550000>;
219 };
220
221 vgen3_reg: vgen3 {
222 regulator-min-microvolt = <1800000>;
223 regulator-max-microvolt = <3300000>;
224 regulator-always-on;
225 };
226
227 vgen4_reg: vgen4 {
228 regulator-min-microvolt = <1800000>;
229 regulator-max-microvolt = <3300000>;
230 regulator-always-on;
231 };
232
233 vgen5_reg: vgen5 {
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <3300000>;
236 regulator-always-on;
237 };
238
239 vgen6_reg: vgen6 {
240 regulator-min-microvolt = <1800000>;
241 regulator-max-microvolt = <3300000>;
242 regulator-always-on;
243 };
244
245 vref_reg: vrefddr {
246 regulator-boot-on;
247 regulator-always-on;
248 };
249
250 vsnvs_reg: vsnvs {
251 regulator-min-microvolt = <1000000>;
252 regulator-max-microvolt = <3000000>;
253 regulator-boot-on;
254 regulator-always-on;
255 };
256 };
257 };
258
259 leds: led-controller@30 {
260 compatible = "ti,lp5562";
261 reg = <0x30>;
262 clock-mode = /bits/ 8 <1>;
263 status = "disabled";
264
265 chan0 {
266 chan-name = "R";
267 led-cur = /bits/ 8 <0x20>;
268 max-cur = /bits/ 8 <0x60>;
269 };
270
271 chan1 {
272 chan-name = "G";
273 led-cur = /bits/ 8 <0x20>;
274 max-cur = /bits/ 8 <0x60>;
275 };
276
277 chan2 {
278 chan-name = "B";
279 led-cur = /bits/ 8 <0x20>;
280 max-cur = /bits/ 8 <0x60>;
281 };
282
283 chan3 {
284 chan-name = "W";
285 led-cur = /bits/ 8 <0x0>;
286 max-cur = /bits/ 8 <0x0>;
287 };
288 };
289
290 eeprom@57 {
291 compatible = "atmel,24c128";
292 reg = <0x57>;
293 pagesize = <64>;
294 status = "okay";
295 };
296
297 touchscreen: touchscreen@5c {
298 compatible = "pixcir,pixcir_tangoc";
299 reg = <0x5c>;
300 pinctrl-0 = <&pinctrl_touch>;
301 interrupt-parent = <&gpio4>;
302 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
303 attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
304 reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
305 touchscreen-size-x = <800>;
306 touchscreen-size-y = <480>;
307 status = "disabled";
308 };
309};
310
311&i2c3 {
312 clock-frequency = <100000>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_i2c3>;
315 status = "disabled";
316
317 oled: oled@3d {
318 compatible = "solomon,ssd1305fb-i2c";
319 reg = <0x3d>;
320 solomon,height = <64>;
321 solomon,width = <128>;
322 solomon,page-offset = <0>;
323 solomon,prechargep2 = <15>;
324 reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
325 vbat-supply = <&sw2_reg>;
326 status = "disabled";
327 };
328
329 gpio_oled: gpio@41 {
330 compatible = "nxp,pca9536";
331 gpio-controller;
332 #gpio-cells = <2>;
333 reg = <0x41>;
334 vcc-supply = <&sw2_reg>;
335 status = "disabled";
336 };
337};
338
339&iomuxc {
340 pinctrl_enet: enetgrp {
341 fsl,pins = <
342 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020
343 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020
344 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020
345 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020
346 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020
347 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020
348 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020
349 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020
350 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020
351 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020
352 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020
353 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020
354 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020
355 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020
356 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010
357 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010
358 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098
359 >;
360 };
361
362 pinctrl_hdmi_cec: hdmicecgrp {
363 fsl,pins = <
364 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1b898
365 >;
366 };
367
368 pinctrl_i2c2: i2c2grp {
369 fsl,pins = <
370 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899
371 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899
372 >;
373 };
374
375 pinctrl_i2c3: i2c3grp {
376 fsl,pins = <
377 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899
378 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
379 >;
380 };
381
382 pinctrl_ipu1: ipu1grp {
383 fsl,pins = <
384 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
385 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
386 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
387 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
388 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
389 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
390 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
391 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
392 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
393 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
394 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
395 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
396 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
397 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
398 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
399 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
400 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
401 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
402 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
403 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
404 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
405 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
406 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
407 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
408 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
409 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
410 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
411 >;
412 };
413
414 pinctrl_pcie: pciegrp {
415 fsl,pins = <
416 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098
417 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b098
418 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b098
419 >;
420 };
421
422 pinctrl_pcie_reg: pciereggrp {
423 fsl,pins = <
424 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b098
425 >;
426 };
427
428 pinctrl_pmic: pmicgrp {
429 fsl,pins = <
430 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098
431 >;
432 };
433
434 pinctrl_pwm1: pwm1grp {
435 fsl,pins = <
436 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8
437 >;
438 };
439
440 pinctrl_touch: touchgrp {
441 fsl,pins = <
442 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098
443 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098
444 >;
445 };
446
447 pinctrl_uart1: uart1grp {
448 fsl,pins = <
449 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8
450 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8
451 >;
452 };
453
454 pinctrl_usbh1: usbh1grp {
455 fsl,pins = <
456 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098
457 >;
458 };
459
460 pinctrl_usbh1_vbus: usbh1-vbus {
461 fsl,pins = <
462 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98
463 >;
464 };
465
466 pinctrl_usbotg: usbotggrp {
467 fsl,pins = <
468 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098
469 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098
470 >;
471 };
472
473 pinctrl_usbotg_vbus: usbotg-vbus {
474 fsl,pins = <
475 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98
476 >;
477 };
478
479 pinctrl_usdhc3: usdhc3grp {
480 fsl,pins = <
481 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b018
482 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b018
483 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
484 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
485 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
486 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
487 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
488 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
489 >;
490 };
491
492 pinctrl_usdhc4: usdhc4grp {
493 fsl,pins = <
494 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069
495 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069
496 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069
497 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069
498 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069
499 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069
500 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069
501 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069
502 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069
503 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069
504 >;
505 };
506
507 pinctrl_wdog: wdoggrp {
508 fsl,pins = <
509 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
510 >;
511 };
512};
513
514&ipu1_di0_disp0 {
515 remote-endpoint = <&lcd_display_in>;
516};
517
518&pcie {
519 pinctrl-names = "default";
520 pinctrl-0 = <&pinctrl_pcie>;
521 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
522 vpcie-supply = <&reg_pcie>;
523 status = "disabled";
524};
525
526&pwm1 {
527 #pwm-cells = <3>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&pinctrl_pwm1>;
530 status = "disabled";
531};
532
533&uart1 {
534 pinctrl-names = "default";
535 pinctrl-0 = <&pinctrl_uart1>;
536 status = "okay";
537};
538
539&usbh1 {
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_usbh1>;
542 vbus-supply = <&reg_usb_h1_vbus>;
543 status = "disabled";
544};
545
546&usbotg {
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_usbotg>;
549 vbus-supply = <&reg_usb_otg_vbus>;
550 srp-disable;
551 hnp-disable;
552 adp-disable;
553 status = "okay";
554};
555
556&usbphy1 {
557 fsl,tx-d-cal = <106>;
558 status = "okay";
559};
560
561&usbphy2 {
562 fsl,tx-d-cal = <109>;
563 status = "disabled";
564};
565
566&usdhc3 {
567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_usdhc3>;
569 bus-width = <4>;
570 cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
571 wp-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
572 no-1-8-v;
573 keep-power-in-suspend;
574 wakeup-source;
575 vmmc-supply = <&sw2_reg>;
576 status = "disabled";
577};
578
579&usdhc4 {
580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_usdhc4>;
582 bus-width = <8>;
583 non-removable;
584 no-1-8-v;
585 keep-power-in-suspend;
586 vmmc-supply = <&sw2_reg>;
587 status = "okay";
588};
589
590&wdog1 {
591 status = "disabled";
592};
593
594&wdog2 {
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_wdog>;
597 fsl,ext-reset-output;
598 status = "okay";
599};