Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | # |
| 3 | # Makefile for the fpga framework and fpga manager drivers. |
| 4 | # |
| 5 | |
| 6 | # Core FPGA Manager Framework |
| 7 | obj-$(CONFIG_FPGA) += fpga-mgr.o |
| 8 | |
| 9 | # FPGA Manager Drivers |
| 10 | obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o |
| 11 | obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o |
| 12 | obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o |
| 13 | obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o |
| 14 | obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o |
| 15 | obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 16 | obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 17 | obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o |
| 18 | obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o |
| 19 | obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 20 | obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 21 | obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o |
| 22 | obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o |
| 23 | |
| 24 | # FPGA Bridge Drivers |
| 25 | obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o |
| 26 | obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o |
| 27 | obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o |
| 28 | obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o |
| 29 | |
| 30 | # High Level Interfaces |
| 31 | obj-$(CONFIG_FPGA_REGION) += fpga-region.o |
| 32 | obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o |
| 33 | |
| 34 | # FPGA Device Feature List Support |
| 35 | obj-$(CONFIG_FPGA_DFL) += dfl.o |
| 36 | obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o |
| 37 | obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o |
| 38 | obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o |
| 39 | obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o |
| 40 | obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o |
| 41 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 42 | dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 43 | dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 44 | dfl-afu-objs += dfl-afu-error.o |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 45 | |
| 46 | # Drivers for FPGAs which implement DFL |
| 47 | obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o |