| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Common address map definitions |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __ASM_MACH_ADDR_MAP_H |
| 7 | #define __ASM_MACH_ADDR_MAP_H |
| 8 | |
| 9 | /* APB - Application Subsystem Peripheral Bus |
| 10 | * |
| 11 | * NOTE: the DMA controller registers are actually on the AXI fabric #1 |
| 12 | * slave port to AHB/APB bridge, due to its close relationship to those |
| 13 | * peripherals on APB, let's count it into the ABP mapping area. |
| 14 | */ |
| 15 | #define APB_PHYS_BASE 0xd4000000 |
| 16 | #define APB_VIRT_BASE IOMEM(0xfe000000) |
| 17 | #define APB_PHYS_SIZE 0x00200000 |
| 18 | |
| 19 | #define AXI_PHYS_BASE 0xd4200000 |
| 20 | #define AXI_VIRT_BASE IOMEM(0xfe200000) |
| 21 | #define AXI_PHYS_SIZE 0x00200000 |
| 22 | |
| 23 | /* Static Memory Controller - Chip Select 0 and 1 */ |
| 24 | #define SMC_CS0_PHYS_BASE 0x80000000 |
| 25 | #define SMC_CS0_PHYS_SIZE 0x10000000 |
| 26 | #define SMC_CS1_PHYS_BASE 0x90000000 |
| 27 | #define SMC_CS1_PHYS_SIZE 0x10000000 |
| 28 | |
| 29 | #define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) |
| 30 | #define APMU_REG(x) (APMU_VIRT_BASE + (x)) |
| 31 | |
| 32 | #define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) |
| 33 | #define APBC_REG(x) (APBC_VIRT_BASE + (x)) |
| 34 | |
| 35 | #define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000) |
| 36 | #define MPMU_REG(x) (MPMU_VIRT_BASE + (x)) |
| 37 | |
| 38 | #define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00) |
| 39 | #define CIU_REG(x) (CIU_VIRT_BASE + (x)) |
| 40 | |
| 41 | #endif /* __ASM_MACH_ADDR_MAP_H */ |