| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* Common header for intel-gtt.ko and i915.ko */ |
| 3 | |
| 4 | #ifndef _DRM_INTEL_GTT_H |
| 5 | #define _DRM_INTEL_GTT_H |
| 6 | |
| 7 | void intel_gtt_get(u64 *gtt_total, |
| 8 | phys_addr_t *mappable_base, |
| 9 | resource_size_t *mappable_end); |
| 10 | |
| 11 | int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
| 12 | struct agp_bridge_data *bridge); |
| 13 | void intel_gmch_remove(void); |
| 14 | |
| 15 | bool intel_enable_gtt(void); |
| 16 | |
| 17 | void intel_gtt_chipset_flush(void); |
| 18 | void intel_gtt_insert_page(dma_addr_t addr, |
| 19 | unsigned int pg, |
| 20 | unsigned int flags); |
| 21 | void intel_gtt_insert_sg_entries(struct sg_table *st, |
| 22 | unsigned int pg_start, |
| 23 | unsigned int flags); |
| 24 | void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); |
| 25 | |
| 26 | /* Special gtt memory types */ |
| 27 | #define AGP_DCACHE_MEMORY 1 |
| 28 | #define AGP_PHYS_MEMORY 2 |
| 29 | |
| 30 | /* flag for GFDT type */ |
| 31 | #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) |
| 32 | |
| 33 | #ifdef CONFIG_INTEL_IOMMU |
| 34 | extern int intel_iommu_gfx_mapped; |
| 35 | #endif |
| 36 | |
| 37 | #endif |