| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | menu "DesignWare PCI Core Support" |
| 4 | depends on PCI |
| 5 | |
| 6 | config PCIE_DW |
| 7 | bool |
| 8 | |
| 9 | config PCIE_DW_HOST |
| 10 | bool |
| 11 | depends on PCI_MSI_IRQ_DOMAIN |
| 12 | select PCIE_DW |
| 13 | |
| 14 | config PCIE_DW_EP |
| 15 | bool |
| 16 | depends on PCI_ENDPOINT |
| 17 | select PCIE_DW |
| 18 | |
| 19 | config PCI_DRA7XX |
| 20 | bool |
| 21 | |
| 22 | config PCI_DRA7XX_HOST |
| 23 | bool "TI DRA7xx PCIe controller Host Mode" |
| 24 | depends on SOC_DRA7XX || COMPILE_TEST |
| 25 | depends on PCI_MSI_IRQ_DOMAIN |
| 26 | depends on OF && HAS_IOMEM && TI_PIPE3 |
| 27 | select PCIE_DW_HOST |
| 28 | select PCI_DRA7XX |
| 29 | default y |
| 30 | help |
| 31 | Enables support for the PCIe controller in the DRA7xx SoC to work in |
| 32 | host mode. There are two instances of PCIe controller in DRA7xx. |
| 33 | This controller can work either as EP or RC. In order to enable |
| 34 | host-specific features PCI_DRA7XX_HOST must be selected and in order |
| 35 | to enable device-specific features PCI_DRA7XX_EP must be selected. |
| 36 | This uses the DesignWare core. |
| 37 | |
| 38 | config PCI_DRA7XX_EP |
| 39 | bool "TI DRA7xx PCIe controller Endpoint Mode" |
| 40 | depends on SOC_DRA7XX || COMPILE_TEST |
| 41 | depends on PCI_ENDPOINT |
| 42 | depends on OF && HAS_IOMEM && TI_PIPE3 |
| 43 | select PCIE_DW_EP |
| 44 | select PCI_DRA7XX |
| 45 | help |
| 46 | Enables support for the PCIe controller in the DRA7xx SoC to work in |
| 47 | endpoint mode. There are two instances of PCIe controller in DRA7xx. |
| 48 | This controller can work either as EP or RC. In order to enable |
| 49 | host-specific features PCI_DRA7XX_HOST must be selected and in order |
| 50 | to enable device-specific features PCI_DRA7XX_EP must be selected. |
| 51 | This uses the DesignWare core. |
| 52 | |
| 53 | config PCIE_DW_PLAT |
| 54 | bool |
| 55 | |
| 56 | config PCIE_DW_PLAT_HOST |
| 57 | bool "Platform bus based DesignWare PCIe Controller - Host mode" |
| 58 | depends on PCI && PCI_MSI_IRQ_DOMAIN |
| 59 | select PCIE_DW_HOST |
| 60 | select PCIE_DW_PLAT |
| 61 | help |
| 62 | Enables support for the PCIe controller in the Designware IP to |
| 63 | work in host mode. There are two instances of PCIe controller in |
| 64 | Designware IP. |
| 65 | This controller can work either as EP or RC. In order to enable |
| 66 | host-specific features PCIE_DW_PLAT_HOST must be selected and in |
| 67 | order to enable device-specific features PCI_DW_PLAT_EP must be |
| 68 | selected. |
| 69 | |
| 70 | config PCIE_DW_PLAT_EP |
| 71 | bool "Platform bus based DesignWare PCIe Controller - Endpoint mode" |
| 72 | depends on PCI && PCI_MSI_IRQ_DOMAIN |
| 73 | depends on PCI_ENDPOINT |
| 74 | select PCIE_DW_EP |
| 75 | select PCIE_DW_PLAT |
| 76 | help |
| 77 | Enables support for the PCIe controller in the Designware IP to |
| 78 | work in endpoint mode. There are two instances of PCIe controller |
| 79 | in Designware IP. |
| 80 | This controller can work either as EP or RC. In order to enable |
| 81 | host-specific features PCIE_DW_PLAT_HOST must be selected and in |
| 82 | order to enable device-specific features PCI_DW_PLAT_EP must be |
| 83 | selected. |
| 84 | |
| 85 | config PCI_EXYNOS |
| 86 | bool "Samsung Exynos PCIe controller" |
| 87 | depends on SOC_EXYNOS5440 || COMPILE_TEST |
| 88 | depends on PCI_MSI_IRQ_DOMAIN |
| 89 | select PCIE_DW_HOST |
| 90 | |
| 91 | config PCI_IMX6 |
| 92 | bool "Freescale i.MX6 PCIe controller" |
| 93 | depends on SOC_IMX6Q || (ARM && COMPILE_TEST) |
| 94 | depends on PCI_MSI_IRQ_DOMAIN |
| 95 | select PCIE_DW_HOST |
| 96 | |
| 97 | config PCIE_SPEAR13XX |
| 98 | bool "STMicroelectronics SPEAr PCIe controller" |
| 99 | depends on ARCH_SPEAR13XX || COMPILE_TEST |
| 100 | depends on PCI_MSI_IRQ_DOMAIN |
| 101 | select PCIE_DW_HOST |
| 102 | help |
| 103 | Say Y here if you want PCIe support on SPEAr13XX SoCs. |
| 104 | |
| 105 | config PCI_KEYSTONE |
| 106 | bool "TI Keystone PCIe controller" |
| 107 | depends on ARCH_KEYSTONE || (ARM && COMPILE_TEST) |
| 108 | depends on PCI_MSI_IRQ_DOMAIN |
| 109 | select PCIE_DW_HOST |
| 110 | help |
| 111 | Say Y here if you want to enable PCI controller support on Keystone |
| 112 | SoCs. The PCI controller on Keystone is based on DesignWare hardware |
| 113 | and therefore the driver re-uses the DesignWare core functions to |
| 114 | implement the driver. |
| 115 | |
| 116 | config PCI_LAYERSCAPE |
| 117 | bool "Freescale Layerscape PCIe controller" |
| 118 | depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) |
| 119 | depends on PCI_MSI_IRQ_DOMAIN |
| 120 | select MFD_SYSCON |
| 121 | select PCIE_DW_HOST |
| 122 | help |
| 123 | Say Y here if you want PCIe controller support on Layerscape SoCs. |
| 124 | |
| 125 | config PCI_HISI |
| 126 | depends on OF && (ARM64 || COMPILE_TEST) |
| 127 | bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers" |
| 128 | depends on PCI_MSI_IRQ_DOMAIN |
| 129 | select PCIE_DW_HOST |
| 130 | select PCI_HOST_COMMON |
| 131 | help |
| 132 | Say Y here if you want PCIe controller support on HiSilicon |
| 133 | Hip05 and Hip06 SoCs |
| 134 | |
| 135 | config PCIE_QCOM |
| 136 | bool "Qualcomm PCIe controller" |
| 137 | depends on OF && (ARCH_QCOM || COMPILE_TEST) |
| 138 | depends on PCI_MSI_IRQ_DOMAIN |
| 139 | select PCIE_DW_HOST |
| 140 | help |
| 141 | Say Y here to enable PCIe controller support on Qualcomm SoCs. The |
| 142 | PCIe controller uses the DesignWare core plus Qualcomm-specific |
| 143 | hardware wrappers. |
| 144 | |
| 145 | config PCIE_ARMADA_8K |
| 146 | bool "Marvell Armada-8K PCIe controller" |
| 147 | depends on ARCH_MVEBU || COMPILE_TEST |
| 148 | depends on PCI_MSI_IRQ_DOMAIN |
| 149 | select PCIE_DW_HOST |
| 150 | help |
| 151 | Say Y here if you want to enable PCIe controller support on |
| 152 | Armada-8K SoCs. The PCIe controller on Armada-8K is based on |
| 153 | DesignWare hardware and therefore the driver re-uses the |
| 154 | DesignWare core functions to implement the driver. |
| 155 | |
| 156 | config PCIE_ARTPEC6 |
| 157 | bool |
| 158 | |
| 159 | config PCIE_ARTPEC6_HOST |
| 160 | bool "Axis ARTPEC-6 PCIe controller Host Mode" |
| 161 | depends on MACH_ARTPEC6 || COMPILE_TEST |
| 162 | depends on PCI_MSI_IRQ_DOMAIN |
| 163 | select PCIE_DW_HOST |
| 164 | select PCIE_ARTPEC6 |
| 165 | help |
| 166 | Enables support for the PCIe controller in the ARTPEC-6 SoC to work in |
| 167 | host mode. This uses the DesignWare core. |
| 168 | |
| 169 | config PCIE_ARTPEC6_EP |
| 170 | bool "Axis ARTPEC-6 PCIe controller Endpoint Mode" |
| 171 | depends on MACH_ARTPEC6 || COMPILE_TEST |
| 172 | depends on PCI_ENDPOINT |
| 173 | select PCIE_DW_EP |
| 174 | select PCIE_ARTPEC6 |
| 175 | help |
| 176 | Enables support for the PCIe controller in the ARTPEC-6 SoC to work in |
| 177 | endpoint mode. This uses the DesignWare core. |
| 178 | |
| 179 | config PCIE_KIRIN |
| 180 | depends on OF && (ARM64 || COMPILE_TEST) |
| 181 | bool "HiSilicon Kirin series SoCs PCIe controllers" |
| 182 | depends on PCI_MSI_IRQ_DOMAIN |
| 183 | select PCIE_DW_HOST |
| 184 | help |
| 185 | Say Y here if you want PCIe controller support |
| 186 | on HiSilicon Kirin series SoCs. |
| 187 | |
| 188 | config PCIE_HISI_STB |
| 189 | bool "HiSilicon STB SoCs PCIe controllers" |
| 190 | depends on ARCH_HISI || COMPILE_TEST |
| 191 | depends on PCI_MSI_IRQ_DOMAIN |
| 192 | select PCIE_DW_HOST |
| 193 | help |
| 194 | Say Y here if you want PCIe controller support on HiSilicon STB SoCs |
| 195 | |
| 196 | endmenu |