| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify |
| 3 | * it under the terms of the GNU General Public License, version 2, as |
| 4 | * published by the Free Software Foundation. |
| 5 | * |
| 6 | * This program is distributed in the hope that it will be useful, |
| 7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 9 | * GNU General Public License for more details. |
| 10 | * |
| 11 | * You should have received a copy of the GNU General Public License |
| 12 | * along with this program; if not, write to the Free Software |
| 13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
| 14 | * |
| 15 | * Copyright IBM Corp. 2008 |
| 16 | * |
| 17 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> |
| 18 | */ |
| 19 | |
| 20 | #ifndef __ASM_PPC_DISASSEMBLE_H__ |
| 21 | #define __ASM_PPC_DISASSEMBLE_H__ |
| 22 | |
| 23 | #include <linux/types.h> |
| 24 | |
| 25 | static inline unsigned int get_op(u32 inst) |
| 26 | { |
| 27 | return inst >> 26; |
| 28 | } |
| 29 | |
| 30 | static inline unsigned int get_xop(u32 inst) |
| 31 | { |
| 32 | return (inst >> 1) & 0x3ff; |
| 33 | } |
| 34 | |
| 35 | static inline unsigned int get_sprn(u32 inst) |
| 36 | { |
| 37 | return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); |
| 38 | } |
| 39 | |
| 40 | static inline unsigned int get_dcrn(u32 inst) |
| 41 | { |
| 42 | return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); |
| 43 | } |
| 44 | |
| 45 | static inline unsigned int get_tmrn(u32 inst) |
| 46 | { |
| 47 | return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); |
| 48 | } |
| 49 | |
| 50 | static inline unsigned int get_rt(u32 inst) |
| 51 | { |
| 52 | return (inst >> 21) & 0x1f; |
| 53 | } |
| 54 | |
| 55 | static inline unsigned int get_rs(u32 inst) |
| 56 | { |
| 57 | return (inst >> 21) & 0x1f; |
| 58 | } |
| 59 | |
| 60 | static inline unsigned int get_ra(u32 inst) |
| 61 | { |
| 62 | return (inst >> 16) & 0x1f; |
| 63 | } |
| 64 | |
| 65 | static inline unsigned int get_rb(u32 inst) |
| 66 | { |
| 67 | return (inst >> 11) & 0x1f; |
| 68 | } |
| 69 | |
| 70 | static inline unsigned int get_rc(u32 inst) |
| 71 | { |
| 72 | return inst & 0x1; |
| 73 | } |
| 74 | |
| 75 | static inline unsigned int get_ws(u32 inst) |
| 76 | { |
| 77 | return (inst >> 11) & 0x1f; |
| 78 | } |
| 79 | |
| 80 | static inline unsigned int get_d(u32 inst) |
| 81 | { |
| 82 | return inst & 0xffff; |
| 83 | } |
| 84 | |
| 85 | static inline unsigned int get_oc(u32 inst) |
| 86 | { |
| 87 | return (inst >> 11) & 0x7fff; |
| 88 | } |
| 89 | |
| 90 | static inline unsigned int get_tx_or_sx(u32 inst) |
| 91 | { |
| 92 | return (inst) & 0x1; |
| 93 | } |
| 94 | |
| 95 | #define IS_XFORM(inst) (get_op(inst) == 31) |
| 96 | #define IS_DSFORM(inst) (get_op(inst) >= 56) |
| 97 | |
| 98 | /* |
| 99 | * Create a DSISR value from the instruction |
| 100 | */ |
| 101 | static inline unsigned make_dsisr(unsigned instr) |
| 102 | { |
| 103 | unsigned dsisr; |
| 104 | |
| 105 | |
| 106 | /* bits 6:15 --> 22:31 */ |
| 107 | dsisr = (instr & 0x03ff0000) >> 16; |
| 108 | |
| 109 | if (IS_XFORM(instr)) { |
| 110 | /* bits 29:30 --> 15:16 */ |
| 111 | dsisr |= (instr & 0x00000006) << 14; |
| 112 | /* bit 25 --> 17 */ |
| 113 | dsisr |= (instr & 0x00000040) << 8; |
| 114 | /* bits 21:24 --> 18:21 */ |
| 115 | dsisr |= (instr & 0x00000780) << 3; |
| 116 | } else { |
| 117 | /* bit 5 --> 17 */ |
| 118 | dsisr |= (instr & 0x04000000) >> 12; |
| 119 | /* bits 1: 4 --> 18:21 */ |
| 120 | dsisr |= (instr & 0x78000000) >> 17; |
| 121 | /* bits 30:31 --> 12:13 */ |
| 122 | if (IS_DSFORM(instr)) |
| 123 | dsisr |= (instr & 0x00000003) << 18; |
| 124 | } |
| 125 | |
| 126 | return dsisr; |
| 127 | } |
| 128 | #endif /* __ASM_PPC_DISASSEMBLE_H__ */ |