Update Linux to v5.10.109
Sourced from [1]
[1] https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.10.109.tar.xz
Change-Id: I19bca9fc6762d4e63bcf3e4cba88bbe560d9c76c
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
diff --git a/arch/arm/Kbuild b/arch/arm/Kbuild
new file mode 100644
index 0000000..5208f70
--- /dev/null
+++ b/arch/arm/Kbuild
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_FPE_NWFPE) += nwfpe/
+# Put arch/arm/fastfpe/ to use this.
+obj-$(CONFIG_FPE_FASTFPE) += $(patsubst $(srctree)/$(src)/%,%,$(wildcard $(srctree)/$(src)/fastfpe/))
+obj-$(CONFIG_VFP) += vfp/
+obj-$(CONFIG_XEN) += xen/
+obj-$(CONFIG_VDSO) += vdso/
+obj-y += kernel/ mm/ common/
+obj-y += probes/
+obj-y += net/
+obj-y += crypto/
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9aa8871..a0eac00 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -3,17 +3,16 @@
bool
default y
select ARCH_32BIT_OFF_T
- select ARCH_CLOCKSOURCE_DATA
select ARCH_HAS_BINFMT_FLAT
select ARCH_HAS_DEBUG_VIRTUAL if MMU
select ARCH_HAS_DEVMEM_IS_ALLOWED
- select ARCH_HAS_DMA_COHERENT_TO_PFN if SWIOTLB
select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
select ARCH_HAS_ELF_RANDOMIZE
select ARCH_HAS_FORTIFY_SOURCE
select ARCH_HAS_KEEPINITRD
select ARCH_HAS_KCOV
select ARCH_HAS_MEMBARRIER_SYNC_CORE
+ select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
select ARCH_HAS_PHYS_TO_DMA
select ARCH_HAS_SETUP_DMA_OPS
@@ -36,12 +35,14 @@
select ARCH_USE_CMPXCHG_LOCKREF
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_IPC_PARSE_VERSION
+ select ARCH_WANT_LD_ORPHAN_WARN
select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
- select BUILDTIME_EXTABLE_SORT if MMU
+ select BUILDTIME_TABLE_SORT if MMU
select CLONE_BACKWARDS
select CPU_PM if SUSPEND || CPU_IDLE
select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
select DMA_DECLARE_COHERENT
+ select DMA_OPS
select DMA_REMAP if MMU
select EDAC_SUPPORT
select EDAC_ATOMIC_SCRUB
@@ -49,6 +50,7 @@
select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+ select GENERIC_IRQ_IPI if SMP
select GENERIC_CPU_AUTOPROBE
select GENERIC_EARLY_IOREMAP
select GENERIC_IDLE_POLL_SETUP
@@ -67,13 +69,13 @@
select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
select HAVE_ARCH_MMAP_RND_BITS if MMU
+ select HAVE_ARCH_SECCOMP
select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
select HAVE_ARCH_THREAD_STRUCT_WHITELIST
select HAVE_ARCH_TRACEHOOK
select HAVE_ARM_SMCCC if CPU_V7
select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
select HAVE_CONTEXT_TRACKING
- select HAVE_COPY_THREAD_TLS
select HAVE_C_RECORDMCOUNT
select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
select HAVE_DMA_CONTIGUOUS if MMU
@@ -84,7 +86,8 @@
select HAVE_FAST_GUP if ARM_LPAE
select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
- select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000)
+ select HAVE_FUNCTION_TRACER if !XIP_KERNEL
+ select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_GCC_PLUGINS
select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
select HAVE_IDE if PCI || ISA || PCMCIA
@@ -103,7 +106,7 @@
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
select HAVE_PERF_USER_STACK_DUMP
- select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
+ select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_RSEQ
select HAVE_STACKPROTECTOR
@@ -118,8 +121,8 @@
select OLD_SIGSUSPEND3
select PCI_SYSCALL if PCI
select PERF_USE_VMALLOC
- select REFCOUNT_FULL
select RTC_LIB
+ select SET_FS
select SYS_SUPPORTS_APM_EMULATION
# Above selects are sorted alphabetically; please add new ones
# according to that. Thanks.
@@ -267,9 +270,7 @@
depends on !ARM_PATCH_PHYS_VIRT
default DRAM_BASE if !MMU
default 0x00000000 if ARCH_EBSA110 || \
- ARCH_FOOTBRIDGE || \
- ARCH_INTEGRATOR || \
- ARCH_REALVIEW
+ ARCH_FOOTBRIDGE
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
default 0x20000000 if ARCH_S5PV210
default 0xc0000000 if ARCH_SA1100
@@ -315,6 +316,9 @@
config ARCH_MULTIPLATFORM
bool "Allow multiple platforms to be selected"
depends on MMU
+ select ARCH_FLATMEM_ENABLE
+ select ARCH_SPARSEMEM_ENABLE
+ select ARCH_SELECT_MEMORY_MODEL
select ARM_HAS_SG_CHAIN
select ARM_PATCH_PHYS_VIRT
select AUTO_ZRELADDR
@@ -366,6 +370,7 @@
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select GPIOLIB
+ select HAVE_LEGACY_CLK
help
This enables support for the Cirrus EP93xx series of CPUs.
@@ -437,7 +442,6 @@
select ARM_CPU_SUSPEND if PM
select AUTO_ZRELADDR
select COMMON_CLK
- select CLKDEV_LOOKUP
select CLKSRC_PXA
select CLKSRC_MMIO
select TIMER_OF
@@ -476,7 +480,6 @@
bool "SA1100-based"
select ARCH_MTD_XIP
select ARCH_SPARSEMEM_ENABLE
- select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_PXA
select TIMER_OF if OF
@@ -497,14 +500,12 @@
config ARCH_S3C24XX
bool "Samsung S3C24XX SoCs"
select ATAGS
- select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
select GPIOLIB
select GENERIC_IRQ_MULTI_HANDLER
select HAVE_S3C2410_I2C if I2C
- select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_IO_H
select S3C2410_WATCHDOG
@@ -529,6 +530,7 @@
select GENERIC_IRQ_MULTI_HANDLER
select GPIOLIB
select HAVE_IDE
+ select HAVE_LEGACY_CLK
select IRQ_DOMAIN
select NEED_MACH_IO_H if PCCARD
select NEED_MACH_MEMORY_H
@@ -638,7 +640,6 @@
source "arch/arm/mach-ep93xx/Kconfig"
source "arch/arm/mach-exynos/Kconfig"
-source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/mach-footbridge/Kconfig"
@@ -670,6 +671,8 @@
source "arch/arm/mach-moxart/Kconfig"
+source "arch/arm/mach-mstar/Kconfig"
+
source "arch/arm/mach-mv78xx0/Kconfig"
source "arch/arm/mach-mvebu/Kconfig"
@@ -703,13 +706,13 @@
source "arch/arm/mach-rda/Kconfig"
+source "arch/arm/mach-realtek/Kconfig"
+
source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
-source "arch/arm/mach-s3c24xx/Kconfig"
-
-source "arch/arm/mach-s3c64xx/Kconfig"
+source "arch/arm/mach-s3c/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig"
@@ -740,7 +743,6 @@
source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vexpress/Kconfig"
-source "arch/arm/plat-versatile/Kconfig"
source "arch/arm/mach-vt8500/Kconfig"
@@ -1023,7 +1025,7 @@
depends on CPU_V7
help
This option enables the workaround for the 775420 Cortex-A9 (r2p2,
- r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
+ r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
operation aborts with MMU exception, it might cause the processor
to deadlock. This workaround puts DSB before executing ISB if
an abort may occur on cache maintenance.
@@ -1149,12 +1151,6 @@
help
Enable PCI on the BSE nanoEngine board.
-config PCI_HOST_ITE8152
- bool
- depends on PCI && MACH_ARMCORE
- default y
- select DMABOUNCE
-
config ARM_ERRATA_814220
bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
depends on CPU_V7
@@ -1250,7 +1246,6 @@
bool "Architected timer support"
depends on CPU_V7
select ARM_ARCH_TIMER
- select GENERIC_CLOCKEVENTS
help
This option enables support for the ARM architected timer
@@ -1362,7 +1357,7 @@
int
default 2048 if ARCH_SOCFPGA
default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
- ARCH_ZYNQ
+ ARCH_ZYNQ || ARCH_ASPEED
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
default 416 if ARCH_SUNXI
@@ -1430,37 +1425,6 @@
If unsure, say N.
-config THUMB2_AVOID_R_ARM_THM_JUMP11
- bool "Work around buggy Thumb-2 short branch relocations in gas"
- depends on THUMB2_KERNEL && MODULES
- default y
- help
- Various binutils versions can resolve Thumb-2 branches to
- locally-defined, preemptible global symbols as short-range "b.n"
- branch instructions.
-
- This is a problem, because there's no guarantee the final
- destination of the symbol, or any candidate locations for a
- trampoline, are within range of the branch. For this reason, the
- kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
- relocation in modules at all, and it makes little sense to add
- support.
-
- The symptom is that the kernel fails with an "unsupported
- relocation" error when loading some modules.
-
- Until fixed tools are available, passing
- -fno-optimize-sibling-calls to gcc should prevent gcc generating
- code which hits this problem, at the cost of a bit of extra runtime
- stack usage in some cases.
-
- The problem is described in more detail at:
- https://bugs.launchpad.net/binutils-linaro/+bug/725126
-
- Only Thumb-2 kernels are affected.
-
- Unless you are sure your tools don't have this problem, say Y.
-
config ARM_PATCH_IDIV
bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
depends on CPU_32v7 && !XIP_KERNEL
@@ -1520,11 +1484,15 @@
config ARCH_HAS_HOLES_MEMORYMODEL
bool
-config ARCH_SPARSEMEM_ENABLE
+config ARCH_SELECT_MEMORY_MODEL
bool
-config ARCH_SPARSEMEM_DEFAULT
- def_bool ARCH_SPARSEMEM_ENABLE
+config ARCH_FLATMEM_ENABLE
+ bool
+
+config ARCH_SPARSEMEM_ENABLE
+ bool
+ select SPARSEMEM_STATIC if SPARSEMEM
config HAVE_ARCH_PFN_VALID
def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
@@ -1650,20 +1618,6 @@
However, if the CPU data cache is using a write-allocate mode,
this option is unlikely to provide any performance gain.
-config SECCOMP
- bool
- prompt "Enable seccomp to safely compute untrusted bytecode"
- ---help---
- This kernel feature is useful for number crunching applications
- that may need to compute untrusted bytecode during their
- execution. By using pipes or other transports made available to
- the process as file descriptors supporting the read/write
- syscalls, it's possible to isolate those applications in
- their own address space using seccomp. Once seccomp is
- enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
- and the task is only allowed to execute a few safe syscalls
- defined by each seccomp mode.
-
config PARAVIRT
bool "Enable paravirtualization code"
help
@@ -1747,7 +1701,7 @@
# TEXT and BSS so we preserve their values in the config files.
config ZBOOT_ROM_TEXT
hex "Compressed ROM boot loader base address"
- default "0"
+ default 0x0
help
The physical address at which the ROM-able zImage is to be
placed in the target. Platforms which normally make use of
@@ -1758,7 +1712,7 @@
config ZBOOT_ROM_BSS
hex "Compressed ROM boot loader BSS address"
- default "0"
+ default 0x0
help
The base address of an area of read/write memory in the target
for the ROM-able zImage which must be available while the
@@ -1959,9 +1913,9 @@
select UCS2_STRING
select EFI_PARAMS_FROM_FDT
select EFI_STUB
- select EFI_ARMSTUB
+ select EFI_GENERIC_STUB
select EFI_RUNTIME_WRAPPERS
- ---help---
+ help
This option provides support for runtime services provided
by UEFI firmware (such as non-volatile variables, realtime
clock, and platform reset). A UEFI stub is also provided to
@@ -2003,7 +1957,7 @@
config FPE_NWFPE
bool "NWFPE math emulation"
depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
- ---help---
+ help
Say Y to include the NWFPE floating point emulator in the kernel.
This is necessary to run most binaries. Linux does not currently
support floating point hardware so you need to say Y here even if
@@ -2027,7 +1981,7 @@
config FPE_FASTFPE
bool "FastFPE math emulation (EXPERIMENTAL)"
depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
- ---help---
+ help
Say Y here to include the FAST floating point emulator in the kernel.
This is an experimental much faster emulator which now also has full
precision for the mantissa. It does not support any exceptions.
@@ -2096,4 +2050,4 @@
source "arch/arm/crypto/Kconfig"
endif
-source "arch/arm/kvm/Kconfig"
+source "arch/arm/Kconfig.assembler"
diff --git a/arch/arm/Kconfig.assembler b/arch/arm/Kconfig.assembler
new file mode 100644
index 0000000..5cb31aa
--- /dev/null
+++ b/arch/arm/Kconfig.assembler
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config AS_VFP_VMRS_FPINST
+ def_bool $(as-instr,.fpu vfpv2\nvmrs r0$(comma)FPINST)
+ help
+ Supported by binutils >= 2.24 and LLVM integrated assembler.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 8bcbd0c..dd1cf70 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -9,7 +9,7 @@
depends on MMU
select ARM_PTDUMP_CORE
select DEBUG_FS
- ---help---
+ help
Say Y here if you want to show the kernel pagetable layout in a
debugfs file. This information is only useful for kernel developers
who are working in architecture specific areas of the kernel.
@@ -21,7 +21,7 @@
bool "Warn on W+X mappings at boot"
depends on MMU
select ARM_PTDUMP_CORE
- ---help---
+ help
Generate a warning if any W+X mappings are found at boot.
This is useful for discovering cases where the kernel is leaving
@@ -147,14 +147,14 @@
0x80024000 | 0xf0024000 | UART9
config DEBUG_AT91_RM9200_DBGU
- bool "Kernel low-level debugging on AT91RM9200, AT91SAM9 DBGU"
+ bool "Kernel low-level debugging on AT91RM9200, AT91SAM9, SAM9X60 DBGU"
select DEBUG_AT91_UART
- depends on SOC_AT91RM9200 || SOC_AT91SAM9
+ depends on SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60
help
Say Y here if you want kernel low-level debugging support
on the DBGU port of:
at91rm9200, at91sam9260, at91sam9g20, at91sam9261,
- at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5
+ at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5, sam9x60
config DEBUG_AT91_SAM9263_DBGU
bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU"
@@ -400,12 +400,12 @@
Say Y here if you want kernel low-level debugging support
on i.MX25.
- config DEBUG_IMX21_IMX27_UART
- bool "i.MX21 and i.MX27 Debug UART"
- depends on SOC_IMX21 || SOC_IMX27
+ config DEBUG_IMX27_UART
+ bool "i.MX27 Debug UART"
+ depends on SOC_IMX27
help
Say Y here if you want kernel low-level debugging support
- on i.MX21 or i.MX27.
+ on i.MX27.
config DEBUG_IMX28_UART
bool "i.MX28 Debug UART"
@@ -976,6 +976,13 @@
Say Y here if you want kernel low-level debugging support
via SCIF4 on Renesas RZ/G1E (R8A7745).
+ config DEBUG_RCAR_GEN2_SCIFA2
+ bool "Kernel low-level debugging messages via SCIFA2 on R8A7742"
+ depends on ARCH_R8A7742
+ help
+ Say Y here if you want kernel low-level debugging support
+ via SCIFA2 on Renesas RZ/G1H (R8A7742).
+
config DEBUG_RMOBILE_SCIFA0
bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
depends on ARCH_R8A73A4
@@ -998,7 +1005,7 @@
via SCIFA4 on Renesas SH-Mobile AG5 (SH73A0).
config DEBUG_S3C_UART0
- depends on PLAT_SAMSUNG
+ depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
@@ -1010,7 +1017,7 @@
by the boot-loader before use.
config DEBUG_S3C_UART1
- depends on PLAT_SAMSUNG
+ depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
@@ -1022,7 +1029,7 @@
by the boot-loader before use.
config DEBUG_S3C_UART2
- depends on PLAT_SAMSUNG
+ depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C24XX_UART if ARCH_S3C24XX
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
@@ -1034,7 +1041,7 @@
by the boot-loader before use.
config DEBUG_S3C_UART3
- depends on PLAT_SAMSUNG && (ARCH_EXYNOS || ARCH_S5PV210)
+ depends on ARCH_EXYNOS || ARCH_S5PV210
select DEBUG_EXYNOS_UART if ARCH_EXYNOS
select DEBUG_S3C64XX_UART if ARCH_S3C64XX
select DEBUG_S5PV210_UART if ARCH_S5PV210
@@ -1079,6 +1086,14 @@
on SA-11x0 UART ports. The kernel will check for the first
enabled UART in a sequence 3-1-2.
+ config DEBUG_SD5203_UART
+ bool "Hisilicon SD5203 Debug UART"
+ depends on ARCH_SD5203
+ select DEBUG_UART_8250
+ help
+ Say Y here if you want kernel low-level debugging support
+ on SD5203 UART.
+
config DEBUG_SOCFPGA_UART0
depends on ARCH_SOCFPGA
bool "Use SOCFPGA UART0 for low-level debug"
@@ -1201,23 +1216,49 @@
config STM32F4_DEBUG_UART
bool "Use STM32F4 UART for low-level debug"
- depends on ARCH_STM32
+ depends on MACH_STM32F429 || MACH_STM32F469
select DEBUG_STM32_UART
help
Say Y here if you want kernel low-level debugging support
on STM32F4 based platforms, which default UART is wired on
- USART1.
+ USART1, but another UART instance can be selected by modifying
+ CONFIG_DEBUG_UART_PHYS.
If unsure, say N.
config STM32F7_DEBUG_UART
bool "Use STM32F7 UART for low-level debug"
- depends on ARCH_STM32
+ depends on MACH_STM32F746 || MACH_STM32F769
select DEBUG_STM32_UART
help
Say Y here if you want kernel low-level debugging support
on STM32F7 based platforms, which default UART is wired on
- USART1.
+ USART1, but another UART instance can be selected by modifying
+ CONFIG_DEBUG_UART_PHYS.
+
+ If unsure, say N.
+
+ config STM32H7_DEBUG_UART
+ bool "Use STM32H7 UART for low-level debug"
+ depends on MACH_STM32H743
+ select DEBUG_STM32_UART
+ help
+ Say Y here if you want kernel low-level debugging support
+ on STM32H7 based platforms, which default UART is wired on
+ USART1, but another UART instance can be selected by modifying
+ CONFIG_DEBUG_UART_PHYS.
+
+ If unsure, say N.
+
+ config STM32MP1_DEBUG_UART
+ bool "Use STM32MP1 UART for low-level debug"
+ depends on MACH_STM32MP157
+ select DEBUG_STM32_UART
+ help
+ Say Y here if you want kernel low-level debugging support
+ on STM32MP1 based platforms, wich default UART is wired on
+ UART4, but another UART instance can be selected by modifying
+ CONFIG_DEBUG_UART_PHYS and CONFIG_DEBUG_UART_VIRT.
If unsure, say N.
@@ -1464,6 +1505,16 @@
config DEBUG_S5PV210_UART
bool
+config DEBUG_S3C_UART
+ depends on DEBUG_S3C2410_UART || DEBUG_S3C24XX_UART || \
+ DEBUG_S3C64XX_UART || DEBUG_S5PV210_UART || \
+ DEBUG_EXYNOS_UART
+ int
+ default "0" if DEBUG_S3C_UART0
+ default "1" if DEBUG_S3C_UART1
+ default "2" if DEBUG_S3C_UART2
+ default "3" if DEBUG_S3C_UART3
+
config DEBUG_OMAP2PLUS_UART
bool
depends on ARCH_OMAP2PLUS
@@ -1472,7 +1523,7 @@
int "i.MX Debug UART Port Selection"
depends on DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
- DEBUG_IMX21_IMX27_UART || \
+ DEBUG_IMX27_UART || \
DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX50_UART || \
@@ -1513,6 +1564,17 @@
bool
depends on ARCH_SIRF
+config DEBUG_UART_FLOW_CONTROL
+ bool "Enable flow control (CTS) for the debug UART"
+ depends on DEBUG_LL
+ default y if ARCH_EBSA110 || DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC
+ help
+ Some UART ports are connected to terminals that will use modem
+ control signals to indicate whether they are ready to receive text.
+ In practice this means that the terminal is asserting the special
+ control signal CTS (Clear To Send). If your debug UART supports
+ this and your debug terminal will require it, enable this option.
+
config DEBUG_LL_INCLUDE
string
default "debug/sa1100.S" if DEBUG_SA1100
@@ -1529,12 +1591,12 @@
default "debug/icedcc.S" if DEBUG_ICEDCC
default "debug/imx.S" if DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
- DEBUG_IMX21_IMX27_UART || \
+ DEBUG_IMX27_UART || \
DEBUG_IMX31_UART || \
DEBUG_IMX35_UART || \
DEBUG_IMX50_UART || \
DEBUG_IMX51_UART || \
- DEBUG_IMX53_UART ||\
+ DEBUG_IMX53_UART || \
DEBUG_IMX6Q_UART || \
DEBUG_IMX6SL_UART || \
DEBUG_IMX6SX_UART || \
@@ -1551,6 +1613,7 @@
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF1
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4
+ default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIFA2
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
@@ -1605,6 +1668,7 @@
default 0x11006000 if DEBUG_MT6589_UART0
default 0x11009000 if DEBUG_MT8135_UART3
default 0x16000000 if DEBUG_INTEGRATOR
+ default 0x1600d000 if DEBUG_SD5203_UART
default 0x18000300 if DEBUG_BCM_5301X
default 0x18000400 if DEBUG_BCM_HR2
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
@@ -1619,6 +1683,9 @@
default 0x3e000000 if DEBUG_BCM_KONA_UART
default 0x3f201000 if DEBUG_BCM2836
default 0x4000e400 if DEBUG_LL_UART_EFM32
+ default 0x40010000 if STM32MP1_DEBUG_UART
+ default 0x40011000 if STM32F4_DEBUG_UART || STM32F7_DEBUG_UART || \
+ STM32H7_DEBUG_UART
default 0x40028000 if DEBUG_AT91_SAMV7_USART1
default 0x40081000 if DEBUG_LPC18XX_UART0
default 0x40090000 if DEBUG_LPC32XX
@@ -1667,6 +1734,7 @@
default 0xe4007000 if DEBUG_HIP04_UART
default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0
default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1
+ default 0xe6c60000 if DEBUG_RCAR_GEN2_SCIFA2
default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4
default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2
default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
@@ -1708,12 +1776,13 @@
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \
DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \
+ DEBUG_RCAR_GEN2_SCIFA2 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
- DEBUG_AT91_UART
+ DEBUG_AT91_UART || DEBUG_STM32_UART
config DEBUG_UART_VIRT
hex "Virtual base address of debug UART"
@@ -1779,6 +1848,7 @@
default 0xfcfe8600 if DEBUG_BCM63XX_UART
default 0xfd000000 if DEBUG_SPEAR3XX || DEBUG_SPEAR13XX
default 0xfd883000 if DEBUG_ALPINE_UART0
+ default 0xfe010000 if STM32MP1_DEBUG_UART
default 0xfe017000 if DEBUG_MMP_UART2
default 0xfe018000 if DEBUG_MMP_UART3
default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART
@@ -1801,7 +1871,7 @@
default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1
default 0xfec90000 if DEBUG_RK32_UART2
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
- default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
+ default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART
default 0xfed60000 if DEBUG_RK29_UART0
default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
@@ -1823,7 +1893,7 @@
DEBUG_S3C64XX_UART || \
DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
- DEBUG_AT91_UART
+ DEBUG_AT91_UART || DEBUG_STM32_UART
config DEBUG_UART_8250_SHIFT
int "Register offset shift for the 8250 debug UART"
@@ -1853,11 +1923,6 @@
except for having a different register layout. Say Y here if
the debug UART is of this type.
-config DEBUG_UART_8250_FLOW_CONTROL
- bool "Enable flow control for 8250 UART"
- depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
- default y if ARCH_EBSA110 || DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC
-
config DEBUG_UNCOMPRESS
bool "Enable decompressor debugging via DEBUG_LL output"
depends on ARCH_MULTIPLATFORM || PLAT_SAMSUNG || ARM_SINGLE_ARMV7M
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1fc32b6..0e5a876 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -16,10 +16,6 @@
KBUILD_LDFLAGS_MODULE += --be8
endif
-ifeq ($(CONFIG_ARM_MODULE_PLTS),y)
-KBUILD_LDS_MODULE += $(srctree)/arch/arm/kernel/module.lds
-endif
-
GZFLAGS :=-9
#KBUILD_CFLAGS +=-pipe
@@ -45,12 +41,10 @@
ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
KBUILD_CPPFLAGS += -mbig-endian
CHECKFLAGS += -D__ARMEB__
-AS += -EB
KBUILD_LDFLAGS += -EB
else
KBUILD_CPPFLAGS += -mlittle-endian
CHECKFLAGS += -D__ARMEL__
-AS += -EL
KBUILD_LDFLAGS += -EL
endif
@@ -66,15 +60,15 @@
# Note that GCC does not numerically define an architecture version
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
-arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
-arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
-arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m
+arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -march=armv7-a
+arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 -march=armv6
# Only override the compiler option if ARMv6. The ARMv6K extensions are
# always available in ARMv7
ifeq ($(CONFIG_CPU_32v6),y)
-arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
+arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 -march=armv6k
endif
-arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
+arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 -march=armv5te
arch-$(CONFIG_CPU_32v4T) =-D__LINUX_ARM_ARCH__=4 -march=armv4t
arch-$(CONFIG_CPU_32v4) =-D__LINUX_ARM_ARCH__=4 -march=armv4
arch-$(CONFIG_CPU_32v3) =-D__LINUX_ARM_ARCH__=3 -march=armv3m
@@ -88,7 +82,7 @@
tune-$(CONFIG_CPU_ARM740T) =-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM9TDMI) =-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM940T) =-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM946E) =$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
+tune-$(CONFIG_CPU_ARM946E) =-mtune=arm9e
tune-$(CONFIG_CPU_ARM920T) =-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM922T) =-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM925T) =-mtune=arm9tdmi
@@ -96,11 +90,11 @@
tune-$(CONFIG_CPU_FA526) =-mtune=arm9tdmi
tune-$(CONFIG_CPU_SA110) =-mtune=strongarm110
tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
-tune-$(CONFIG_CPU_XSCALE) =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
-tune-$(CONFIG_CPU_XSC3) =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
-tune-$(CONFIG_CPU_FEROCEON) =$(call cc-option,-mtune=marvell-f,-mtune=xscale)
-tune-$(CONFIG_CPU_V6) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
-tune-$(CONFIG_CPU_V6K) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+tune-$(CONFIG_CPU_XSCALE) =-mtune=xscale
+tune-$(CONFIG_CPU_XSC3) =-mtune=xscale
+tune-$(CONFIG_CPU_FEROCEON) =-mtune=xscale
+tune-$(CONFIG_CPU_V6) =-mtune=arm1136j-s
+tune-$(CONFIG_CPU_V6K) =-mtune=arm1136j-s
# Evaluate tune cc-option calls now
tune-y := $(tune-y)
@@ -125,10 +119,6 @@
ifeq ($(CONFIG_THUMB2_KERNEL),y)
CFLAGS_ISA :=-mthumb -Wa,-mimplicit-it=always $(AFLAGS_NOWARN)
AFLAGS_ISA :=$(CFLAGS_ISA) -Wa$(comma)-mthumb
-# Work around buggy relocation from gas if requested:
-ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y)
-KBUILD_CFLAGS_MODULE +=-fno-optimize-sibling-calls
-endif
else
CFLAGS_ISA :=$(call cc-option,-marm,) $(AFLAGS_NOWARN)
AFLAGS_ISA :=$(CFLAGS_ISA)
@@ -145,13 +135,19 @@
# Text offset. This list is sorted numerically by address in order to
# provide a means to avoid/resolve conflicts in multi-arch kernels.
+# Note: the 32kB below this value is reserved for use by the kernel
+# during boot, and this offset is critical to the functioning of
+# kexec-tools.
textofs-y := 0x00008000
# We don't want the htc bootloader to corrupt kernel during resume
textofs-$(CONFIG_PM_H1940) := 0x00108000
+# RTD1195 has Boot ROM at start of address space
+textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000
# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
ifeq ($(CONFIG_ARCH_SA1100),y)
textofs-$(CONFIG_SA1111) := 0x00208000
endif
+textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
textofs-$(CONFIG_ARCH_MESON) := 0x00208000
@@ -196,6 +192,7 @@
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut
machine-$(CONFIG_ARCH_MXS) += mxs
+machine-$(CONFIG_ARCH_MSTARV7) += mstar
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_NSPIRE) += nspire
@@ -207,11 +204,11 @@
machine-$(CONFIG_ARCH_PXA) += pxa
machine-$(CONFIG_ARCH_QCOM) += qcom
machine-$(CONFIG_ARCH_RDA) += rda
+machine-$(CONFIG_ARCH_REALTEK) += realtek
machine-$(CONFIG_ARCH_REALVIEW) += realview
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_RPC) += rpc
-machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx
-machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
+machine-$(CONFIG_PLAT_SAMSUNG) += s3c
machine-$(CONFIG_ARCH_S5PV210) += s5pv210
machine-$(CONFIG_ARCH_SA1100) += sa1100
machine-$(CONFIG_ARCH_RENESAS) += shmobile
@@ -233,13 +230,9 @@
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
-plat-$(CONFIG_ARCH_EXYNOS) += samsung
plat-$(CONFIG_ARCH_OMAP) += omap
-plat-$(CONFIG_ARCH_S3C64XX) += samsung
-plat-$(CONFIG_ARCH_S5PV210) += samsung
plat-$(CONFIG_PLAT_ORION) += orion
plat-$(CONFIG_PLAT_PXA) += pxa
-plat-$(CONFIG_PLAT_S3C24XX) += samsung
plat-$(CONFIG_PLAT_VERSATILE) += versatile
ifeq ($(CONFIG_ARCH_EBSA110),y)
@@ -273,19 +266,8 @@
export TEXT_OFFSET GZFLAGS MMUEXT
-core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/
-# Put arch/arm/fastfpe/ to use this.
-core-$(CONFIG_FPE_FASTFPE) += $(patsubst $(srctree)/%,%,$(wildcard $(srctree)/arch/arm/fastfpe/))
-core-$(CONFIG_VFP) += arch/arm/vfp/
-core-$(CONFIG_XEN) += arch/arm/xen/
-core-$(CONFIG_KVM_ARM_HOST) += arch/arm/kvm/
-core-$(CONFIG_VDSO) += arch/arm/vdso/
-
+core-y += arch/arm/
# If we have a machine-specific directory, then include it in the build.
-core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
-core-y += arch/arm/probes/
-core-y += arch/arm/net/
-core-y += arch/arm/crypto/
core-y += $(machdirs) $(platdirs)
# For cleaning
diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore
index ce1c5ff..8c75932 100644
--- a/arch/arm/boot/.gitignore
+++ b/arch/arm/boot/.gitignore
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
Image
zImage
xipImage
diff --git a/arch/arm/boot/bootp/init.S b/arch/arm/boot/bootp/init.S
index 5c476bd..b562da2 100644
--- a/arch/arm/boot/bootp/init.S
+++ b/arch/arm/boot/bootp/init.S
@@ -13,7 +13,7 @@
* size immediately following the kernel, we could build this into
* a binary blob, and concatenate the zImage using the cat command.
*/
- .section .start,#alloc,#execinstr
+ .section .start, "ax"
.type _start, #function
.globl _start
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index 86b2f5d..60606b0 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
ashldi3.S
bswapsdi2.S
font.c
@@ -6,12 +7,3 @@
piggy_data
vmlinux
vmlinux.lds
-
-# borrowed libfdt files
-fdt.c
-fdt.h
-fdt_ro.c
-fdt_rw.c
-fdt_wip.c
-libfdt.h
-libfdt_internal.h
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index fb6cb24..175213d 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -7,11 +7,11 @@
OBJS =
-AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
HEAD = head.o
OBJS += misc.o decompress.o
ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y)
OBJS += debug.o
+AFLAGS_head.o += -DDEBUG
endif
FONTC = $(srctree)/lib/fonts/font_acorn_8x8.c
@@ -68,7 +68,12 @@
ZBSSADDR := ALIGN(8)
endif
+MALLOC_SIZE := 65536
+
+AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) -DMALLOC_SIZE=$(MALLOC_SIZE)
CPPFLAGS_vmlinux.lds := -DTEXT_START="$(ZTEXTADDR)" -DBSS_START="$(ZBSSADDR)"
+CPPFLAGS_vmlinux.lds += -DTEXT_OFFSET="$(TEXT_OFFSET)"
+CPPFLAGS_vmlinux.lds += -DMALLOC_SIZE="$(MALLOC_SIZE)"
compress-$(CONFIG_KERNEL_GZIP) = gzip
compress-$(CONFIG_KERNEL_LZO) = lzo
@@ -76,18 +81,7 @@
compress-$(CONFIG_KERNEL_XZ) = xzkern
compress-$(CONFIG_KERNEL_LZ4) = lz4
-# Borrowed libfdt files for the ATAG compatibility mode
-
-libfdt := fdt_rw.c fdt_ro.c fdt_wip.c fdt.c
-libfdt_hdrs := fdt.h libfdt.h libfdt_internal.h
-
-libfdt_objs := $(addsuffix .o, $(basename $(libfdt)))
-
-$(addprefix $(obj)/,$(libfdt) $(libfdt_hdrs)): $(obj)/%: $(srctree)/scripts/dtc/libfdt/%
- $(call cmd,shipped)
-
-$(addprefix $(obj)/,$(libfdt_objs) atags_to_fdt.o): \
- $(addprefix $(obj)/,$(libfdt_hdrs))
+libfdt_objs := fdt_rw.o fdt_ro.o fdt_wip.o fdt.o
ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y)
CFLAGS_REMOVE_atags_to_fdt.o += -Wframe-larger-than=${CONFIG_FRAME_WARN}
@@ -95,31 +89,29 @@
OBJS += $(libfdt_objs) atags_to_fdt.o
endif
+# -fstack-protector-strong triggers protection checks in this code,
+# but it is being used too early to link to meaningful stack_chk logic.
+$(foreach o, $(libfdt_objs) atags_to_fdt.o, \
+ $(eval CFLAGS_$(o) := -I $(srctree)/scripts/dtc/libfdt -fno-stack-protector))
+
+# These were previously generated C files. When you are building the kernel
+# with O=, make sure to remove the stale files in the output tree. Otherwise,
+# the build system wrongly compiles the stale ones.
+ifdef building_out_of_srctree
+$(shell rm -f $(addprefix $(obj)/, fdt_rw.c fdt_ro.c fdt_wip.c fdt.c))
+endif
+
targets := vmlinux vmlinux.lds piggy_data piggy.o \
lib1funcs.o ashldi3.o bswapsdi2.o \
head.o $(OBJS)
-clean-files += piggy_data lib1funcs.S ashldi3.S bswapsdi2.S \
- $(libfdt) $(libfdt_hdrs) hyp-stub.S
+clean-files += piggy_data lib1funcs.S ashldi3.S bswapsdi2.S hyp-stub.S
KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING
-ifeq ($(CONFIG_FUNCTION_TRACER),y)
-ORIG_CFLAGS := $(KBUILD_CFLAGS)
-KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
-endif
-
-# -fstack-protector-strong triggers protection checks in this code,
-# but it is being used too early to link to meaningful stack_chk logic.
-nossp_flags := $(call cc-option, -fno-stack-protector)
-CFLAGS_atags_to_fdt.o := $(nossp_flags)
-CFLAGS_fdt.o := $(nossp_flags)
-CFLAGS_fdt_ro.o := $(nossp_flags)
-CFLAGS_fdt_rw.o := $(nossp_flags)
-CFLAGS_fdt_wip.o := $(nossp_flags)
-
ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin \
-I$(obj) $(DISABLE_ARM_SSP_PER_TASK_PLUGIN)
+ccflags-remove-$(CONFIG_FUNCTION_TRACER) += -pg
asflags-y := -DZIMAGE
# Supply kernel BSS size to the decompressor via a linker symbol.
@@ -138,6 +130,10 @@
LDFLAGS_vmlinux += --no-undefined
# Delete all temporary local symbols
LDFLAGS_vmlinux += -X
+# Report orphan sections
+ifdef CONFIG_LD_ORPHAN_WARN
+LDFLAGS_vmlinux += --orphan-handling=warn
+endif
# Next argument is a linker script
LDFLAGS_vmlinux += -T
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
index 330cd3c..31927d2 100644
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
+#include <linux/libfdt_env.h>
#include <asm/setup.h>
#include <libfdt.h>
@@ -14,12 +15,13 @@
{
int offset = fdt_path_offset(fdt, node_path);
if (offset == -FDT_ERR_NOTFOUND)
- offset = fdt_add_subnode(fdt, 0, node_path);
+ /* Add the node to root if not found, dropping the leading '/' */
+ offset = fdt_add_subnode(fdt, 0, node_path + 1);
return offset;
}
static int setprop(void *fdt, const char *node_path, const char *property,
- uint32_t *val_array, int size)
+ void *val_array, int size)
{
int offset = node_offset(fdt, node_path);
if (offset < 0)
@@ -60,7 +62,7 @@
{
int len;
uint32_t cell_size = 1;
- const uint32_t *size_len = getprop(fdt, "/", "#size-cells", &len);
+ const __be32 *size_len = getprop(fdt, "/", "#size-cells", &len);
if (size_len)
cell_size = fdt32_to_cpu(*size_len);
@@ -129,7 +131,7 @@
struct tag *atag = atag_list;
/* In the case of 64 bits memory size, need to reserve 2 cells for
* address and size for each bank */
- uint32_t mem_reg_property[2 * 2 * NR_BANKS];
+ __be32 mem_reg_property[2 * 2 * NR_BANKS];
int memcount = 0;
int ret, memsize;
@@ -138,7 +140,7 @@
return 1;
/* if we get a DTB here we're done already */
- if (*(u32 *)atag_list == fdt32_to_cpu(FDT_MAGIC))
+ if (*(__be32 *)atag_list == cpu_to_fdt32(FDT_MAGIC))
return 0;
/* validate the ATAG */
@@ -177,8 +179,8 @@
/* if memsize is 2, that means that
* each data needs 2 cells of 32 bits,
* so the data are 64 bits */
- uint64_t *mem_reg_prop64 =
- (uint64_t *)mem_reg_property;
+ __be64 *mem_reg_prop64 =
+ (__be64 *)mem_reg_property;
mem_reg_prop64[memcount++] =
cpu_to_fdt64(atag->u.mem.start);
mem_reg_prop64[memcount++] =
diff --git a/arch/arm/boot/compressed/big-endian.S b/arch/arm/boot/compressed/big-endian.S
index 88e2a88..0e092c3 100644
--- a/arch/arm/boot/compressed/big-endian.S
+++ b/arch/arm/boot/compressed/big-endian.S
@@ -6,7 +6,7 @@
* Author: Nicolas Pitre
*/
- .section ".start", #alloc, #execinstr
+ .section ".start", "ax"
mrc p15, 0, r0, c1, c0, 0 @ read control reg
orr r0, r0, #(1 << 7) @ enable big endian mode
diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S
index 6bf2917..fac40a7 100644
--- a/arch/arm/boot/compressed/debug.S
+++ b/arch/arm/boot/compressed/debug.S
@@ -8,7 +8,10 @@
ENTRY(putc)
addruart r1, r2, r3
- waituart r3, r1
+#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL
+ waituartcts r3, r1
+#endif
+ waituarttxrdy r3, r1
senduart r0, r1
busyuart r3, r1
mov pc, lr
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index aa075d8..74255e8 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -47,7 +47,10 @@
#endif
#ifdef CONFIG_KERNEL_XZ
+/* Prevent KASAN override of string helpers in decompressor */
+#undef memmove
#define memmove memmove
+#undef memcpy
#define memcpy memcpy
#include "../../../../lib/decompress_unxz.c"
#endif
diff --git a/arch/arm/boot/compressed/efi-header.S b/arch/arm/boot/compressed/efi-header.S
index a598358..230030c 100644
--- a/arch/arm/boot/compressed/efi-header.S
+++ b/arch/arm/boot/compressed/efi-header.S
@@ -9,16 +9,22 @@
#include <linux/sizes.h>
.macro __nop
-#ifdef CONFIG_EFI_STUB
- @ This is almost but not quite a NOP, since it does clobber the
- @ condition flags. But it is the best we can do for EFI, since
- @ PE/COFF expects the magic string "MZ" at offset 0, while the
- @ ARM/Linux boot protocol expects an executable instruction
- @ there.
- .inst MZ_MAGIC | (0x1310 << 16) @ tstne r0, #0x4d000
-#else
AR_CLASS( mov r0, r0 )
M_CLASS( nop.w )
+ .endm
+
+ .macro __initial_nops
+#ifdef CONFIG_EFI_STUB
+ @ This is a two-instruction NOP, which happens to bear the
+ @ PE/COFF signature "MZ" in the first two bytes, so the kernel
+ @ is accepted as an EFI binary. Booting via the UEFI stub
+ @ will not execute those instructions, but the ARM/Linux
+ @ boot protocol does, so we need some NOPs here.
+ .inst MZ_MAGIC | (0xe225 << 16) @ eor r5, r5, 0x4d000
+ eor r5, r5, 0x4d000 @ undo previous insn
+#else
+ __nop
+ __nop
#endif
.endm
@@ -60,7 +66,7 @@
.long __pecoff_code_size @ SizeOfCode
.long __pecoff_data_size @ SizeOfInitializedData
.long 0 @ SizeOfUninitializedData
- .long efi_stub_entry - start @ AddressOfEntryPoint
+ .long efi_pe_entry - start @ AddressOfEntryPoint
.long start_offset @ BaseOfCode
.long __pecoff_data_start - start @ BaseOfData
@@ -70,8 +76,8 @@
.long SZ_512 @ FileAlignment
.short 0 @ MajorOsVersion
.short 0 @ MinorOsVersion
- .short 0 @ MajorImageVersion
- .short 0 @ MinorImageVersion
+ .short LINUX_EFISTUB_MAJOR_VERSION @ MajorImageVersion
+ .short LINUX_EFISTUB_MINOR_VERSION @ MinorImageVersion
.short 0 @ MajorSubsystemVersion
.short 0 @ MinorSubsystemVersion
.long 0 @ Win32VersionValue
diff --git a/arch/arm/boot/compressed/fdt.c b/arch/arm/boot/compressed/fdt.c
new file mode 100644
index 0000000..f8ea7a2
--- /dev/null
+++ b/arch/arm/boot/compressed/fdt.c
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "../../../../lib/fdt.c"
diff --git a/arch/arm/boot/compressed/fdt_ro.c b/arch/arm/boot/compressed/fdt_ro.c
new file mode 100644
index 0000000..93970a4
--- /dev/null
+++ b/arch/arm/boot/compressed/fdt_ro.c
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "../../../../lib/fdt_ro.c"
diff --git a/arch/arm/boot/compressed/fdt_rw.c b/arch/arm/boot/compressed/fdt_rw.c
new file mode 100644
index 0000000..f7c6b8b
--- /dev/null
+++ b/arch/arm/boot/compressed/fdt_rw.c
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "../../../../lib/fdt_rw.c"
diff --git a/arch/arm/boot/compressed/fdt_wip.c b/arch/arm/boot/compressed/fdt_wip.c
new file mode 100644
index 0000000..048d2c7
--- /dev/null
+++ b/arch/arm/boot/compressed/fdt_wip.c
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "../../../../lib/fdt_wip.c"
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index cbe1262..7a38c63 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -28,19 +28,19 @@
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
.macro loadsp, rb, tmp1, tmp2
.endm
- .macro writeb, ch, rb
+ .macro writeb, ch, rb, tmp
mcr p14, 0, \ch, c0, c5, 0
.endm
#elif defined(CONFIG_CPU_XSCALE)
.macro loadsp, rb, tmp1, tmp2
.endm
- .macro writeb, ch, rb
+ .macro writeb, ch, rb, tmp
mcr p14, 0, \ch, c8, c0, 0
.endm
#else
.macro loadsp, rb, tmp1, tmp2
.endm
- .macro writeb, ch, rb
+ .macro writeb, ch, rb, tmp
mcr p14, 0, \ch, c1, c0, 0
.endm
#endif
@@ -49,8 +49,13 @@
#include CONFIG_DEBUG_LL_INCLUDE
- .macro writeb, ch, rb
+ .macro writeb, ch, rb, tmp
+#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL
+ waituartcts \tmp, \rb
+#endif
+ waituarttxrdy \tmp, \rb
senduart \ch, \rb
+ busyuart \tmp, \rb
.endm
#if defined(CONFIG_ARCH_SA1100)
@@ -81,42 +86,11 @@
bl phex
.endm
- .macro debug_reloc_start
-#ifdef DEBUG
- kputc #'\n'
- kphex r6, 8 /* processor id */
- kputc #':'
- kphex r7, 8 /* architecture id */
-#ifdef CONFIG_CPU_CP15
- kputc #':'
- mrc p15, 0, r0, c1, c0
- kphex r0, 8 /* control reg */
-#endif
- kputc #'\n'
- kphex r5, 8 /* decompressed kernel start */
- kputc #'-'
- kphex r9, 8 /* decompressed kernel end */
- kputc #'>'
- kphex r4, 8 /* kernel execution address */
- kputc #'\n'
-#endif
- .endm
-
- .macro debug_reloc_end
-#ifdef DEBUG
- kphex r5, 8 /* end of kernel */
- kputc #'\n'
- mov r0, r4
- bl memdump /* dump 256 bytes at start of kernel */
-#endif
- .endm
-
/*
* Debug kernel copy by printing the memory addresses involved
*/
.macro dbgkc, begin, end, cbegin, cend
#ifdef DEBUG
- kputc #'\n'
kputc #'C'
kputc #':'
kputc #'0'
@@ -136,11 +110,62 @@
kputc #'x'
kphex \cend, 8 /* End of kernel copy */
kputc #'\n'
- kputc #'\r'
#endif
.endm
- .section ".start", #alloc, #execinstr
+ /*
+ * Debug print of the final appended DTB location
+ */
+ .macro dbgadtb, begin, size
+#ifdef DEBUG
+ kputc #'D'
+ kputc #'T'
+ kputc #'B'
+ kputc #':'
+ kputc #'0'
+ kputc #'x'
+ kphex \begin, 8 /* Start of appended DTB */
+ kputc #' '
+ kputc #'('
+ kputc #'0'
+ kputc #'x'
+ kphex \size, 8 /* Size of appended DTB */
+ kputc #')'
+ kputc #'\n'
+#endif
+ .endm
+
+ .macro enable_cp15_barriers, reg
+ mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
+ tst \reg, #(1 << 5) @ CP15BEN bit set?
+ bne .L_\@
+ orr \reg, \reg, #(1 << 5) @ CP15 barrier instructions
+ mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
+ ARM( .inst 0xf57ff06f @ v7+ isb )
+ THUMB( isb )
+.L_\@:
+ .endm
+
+ /*
+ * The kernel build system appends the size of the
+ * decompressed kernel at the end of the compressed data
+ * in little-endian form.
+ */
+ .macro get_inflated_image_size, res:req, tmp1:req, tmp2:req
+ adr \res, .Linflated_image_size_offset
+ ldr \tmp1, [\res]
+ add \tmp1, \tmp1, \res @ address of inflated image size
+
+ ldrb \res, [\tmp1] @ get_unaligned_le32
+ ldrb \tmp2, [\tmp1, #1]
+ orr \res, \res, \tmp2, lsl #8
+ ldrb \tmp2, [\tmp1, #2]
+ ldrb \tmp1, [\tmp1, #3]
+ orr \res, \res, \tmp2, lsl #16
+ orr \res, \res, \tmp1, lsl #24
+ .endm
+
+ .section ".start", "ax"
/*
* sort out different calling conventions
*/
@@ -165,7 +190,8 @@
* were patching the initial instructions of the kernel, i.e
* had started to exploit this "patch area".
*/
- .rept 7
+ __initial_nops
+ .rept 5
__nop
.endr
#ifndef CONFIG_THUMB2_KERNEL
@@ -257,41 +283,23 @@
*/
mov r0, pc
cmp r0, r4
- ldrcc r0, LC0+32
+ ldrcc r0, .Lheadroom
addcc r0, r0, pc
cmpcc r4, r0
orrcc r4, r4, #1 @ remember we skipped cache_on
blcs cache_on
-restart: adr r0, LC0
- ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
- ldr sp, [r0, #28]
+restart: adr r0, LC1
+ ldr sp, [r0]
+ ldr r6, [r0, #4]
+ add sp, sp, r0
+ add r6, r6, r0
- /*
- * We might be running at a different address. We need
- * to fix up various pointers.
- */
- sub r0, r0, r1 @ calculate the delta offset
- add r6, r6, r0 @ _edata
- add r10, r10, r0 @ inflated kernel size location
-
- /*
- * The kernel build system appends the size of the
- * decompressed kernel at the end of the compressed data
- * in little-endian form.
- */
- ldrb r9, [r10, #0]
- ldrb lr, [r10, #1]
- orr r9, r9, lr, lsl #8
- ldrb lr, [r10, #2]
- ldrb r10, [r10, #3]
- orr r9, r9, lr, lsl #16
- orr r9, r9, r10, lsl #24
+ get_inflated_image_size r9, r10, lr
#ifndef CONFIG_ZBOOT_ROM
/* malloc space is above the relocated stack (64k max) */
- add sp, sp, r0
- add r10, sp, #0x10000
+ add r10, sp, #MALLOC_SIZE
#else
/*
* With ZBOOT_ROM the bss/stack is non relocatable,
@@ -304,9 +312,6 @@
mov r5, #0 @ init dtb size to 0
#ifdef CONFIG_ARM_APPENDED_DTB
/*
- * r0 = delta
- * r2 = BSS start
- * r3 = BSS end
* r4 = final kernel address (possibly with LSB set)
* r5 = appended dtb size (still unknown)
* r6 = _edata
@@ -314,8 +319,6 @@
* r8 = atags/device tree pointer
* r9 = size of decompressed image
* r10 = end of this image, including bss/stack/malloc space if non XIP
- * r11 = GOT start
- * r12 = GOT end
* sp = stack pointer
*
* if there are device trees (dtb) appended to zImage, advance r10 so that the
@@ -350,6 +353,7 @@
mov r5, r5, ror #8
eor r5, r5, r1, lsr #8
#endif
+ dbgadtb r6, r5
/* 50% DTB growth should be good enough */
add r5, r5, r5, lsr #1
/* preserve 64-bit alignment */
@@ -363,7 +367,6 @@
/* temporarily relocate the stack past the DTB work space */
add sp, sp, r5
- stmfd sp!, {r0-r3, ip, lr}
mov r0, r8
mov r1, r6
mov r2, r5
@@ -382,7 +385,6 @@
mov r2, r5
bleq atags_to_fdt
- ldmfd sp!, {r0-r3, ip, lr}
sub sp, sp, r5
#endif
@@ -510,11 +512,8 @@
/* Preserve offset to relocated code. */
sub r6, r9, r6
-#ifndef CONFIG_ZBOOT_ROM
- /* cache_clean_flush may use the stack, so relocate it */
- add sp, sp, r6
-#endif
-
+ mov r0, r9 @ start of relocated zImage
+ add r1, sp, r6 @ end of relocated zImage
bl cache_clean_flush
badr r0, restart
@@ -522,6 +521,10 @@
mov pc, r0
wont_overwrite:
+ adr r0, LC0
+ ldmia r0, {r1, r2, r3, r11, r12}
+ sub r0, r0, r1 @ calculate the delta offset
+
/*
* If delta is zero, we are running at the address we were linked at.
* r0 = delta
@@ -608,9 +611,14 @@
*/
mov r0, r4
mov r1, sp @ malloc space above stack
- add r2, sp, #0x10000 @ 64k max
+ add r2, sp, #MALLOC_SIZE @ 64k max
mov r3, r7
bl decompress_kernel
+
+ get_inflated_image_size r1, r2, r3
+
+ mov r0, r4 @ start of inflated image
+ add r1, r1, r0 @ end of inflated image
bl cache_clean_flush
bl cache_off
@@ -640,14 +648,21 @@
LC0: .word LC0 @ r1
.word __bss_start @ r2
.word _end @ r3
- .word _edata @ r6
- .word input_data_end - 4 @ r10 (inflated size location)
.word _got_start @ r11
.word _got_end @ ip
- .word .L_user_stack_end @ sp
- .word _end - restart + 16384 + 1024*1024
.size LC0, . - LC0
+ .type LC1, #object
+LC1: .word .L_user_stack_end - LC1 @ sp
+ .word _edata - LC1 @ r6
+ .size LC1, . - LC1
+
+.Lheadroom:
+ .word _end - restart + 16384 + 1024*1024
+
+.Linflated_image_size_offset:
+ .long (input_data_end - 4) - .
+
#ifdef CONFIG_ARCH_RPC
.globl params
params: ldr r0, =0x10000100 @ params_phys for RPC
@@ -657,6 +672,24 @@
#endif
/*
+ * dcache_line_size - get the minimum D-cache line size from the CTR register
+ * on ARMv7.
+ */
+ .macro dcache_line_size, reg, tmp
+#ifdef CONFIG_CPU_V7M
+ movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
+ movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
+ ldr \tmp, [\tmp]
+#else
+ mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
+#endif
+ lsr \tmp, \tmp, #16
+ and \tmp, \tmp, #0xf @ cache line size encoding
+ mov \reg, #4 @ bytes per word
+ mov \reg, \reg, lsl \tmp @ actual cache line size
+ .endm
+
+/*
* Turn on the cache. We need to setup some page tables so that we
* can have both the I and D caches on.
*
@@ -820,6 +853,7 @@
mov pc, r12
__armv7_mmu_cache_on:
+ enable_cp15_barriers r11
mov r12, lr
#ifdef CONFIG_MMU
mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
@@ -1147,8 +1181,6 @@
bic r0, r0, #0x0004
#endif
mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
- mov r12, lr
- bl __armv7_mmu_cache_flush
mov r0, #0
#ifdef CONFIG_MMU
mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
@@ -1156,11 +1188,14 @@
mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
- mov pc, r12
+ mov pc, lr
/*
* Clean and flush the cache to maintain consistency.
*
+ * On entry,
+ * r0 = start address
+ * r1 = end address (exclusive)
* On exit,
* r1, r2, r3, r9, r10, r11, r12 corrupted
* This routine must preserve:
@@ -1169,6 +1204,7 @@
.align 5
cache_clean_flush:
mov r3, #16
+ mov r11, r1
b call_cache_fn
__armv4_mpu_cache_flush:
@@ -1209,6 +1245,7 @@
mov pc, lr
__armv7_mmu_cache_flush:
+ enable_cp15_barriers r10
tst r4, #1
bne iflush
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
@@ -1218,51 +1255,16 @@
mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
b iflush
hierarchical:
- mcr p15, 0, r10, c7, c10, 5 @ DMB
- stmfd sp!, {r0-r7, r9-r11}
- mrc p15, 1, r0, c0, c0, 1 @ read clidr
- ands r3, r0, #0x7000000 @ extract loc from clidr
- mov r3, r3, lsr #23 @ left align loc bit field
- beq finished @ if loc is 0, then no need to clean
- mov r10, #0 @ start clean at cache level 0
-loop1:
- add r2, r10, r10, lsr #1 @ work out 3x current cache level
- mov r1, r0, lsr r2 @ extract cache type bits from clidr
- and r1, r1, #7 @ mask of the bits for current cache only
- cmp r1, #2 @ see what cache we have at this level
- blt skip @ skip if no cache, or just i-cache
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
- mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
- mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
- and r2, r1, #7 @ extract the length of the cache lines
- add r2, r2, #4 @ add 4 (line length offset)
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 @ find maximum number on the way size
- clz r5, r4 @ find bit position of way size increment
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 @ extract max number of the index size
-loop2:
- mov r9, r4 @ create working copy of max way size
-loop3:
- ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
- ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
- THUMB( lsl r6, r9, r5 )
- THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
- THUMB( lsl r6, r7, r2 )
- THUMB( orr r11, r11, r6 ) @ factor index number into r11
- mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
- subs r9, r9, #1 @ decrement the way
- bge loop3
- subs r7, r7, #1 @ decrement the index
- bge loop2
-skip:
- add r10, r10, #2 @ increment cache number
- cmp r3, r10
- bgt loop1
-finished:
- ldmfd sp!, {r0-r7, r9-r11}
- mov r10, #0 @ switch back to cache level 0
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dcache_line_size r1, r2 @ r1 := dcache min line size
+ sub r2, r1, #1 @ r2 := line size mask
+ bic r0, r0, r2 @ round down start to line size
+ sub r11, r11, #1 @ end address is exclusive
+ bic r11, r11, r2 @ round down end to line size
+0: cmp r0, r11 @ finished?
+ bgt iflush
+ mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
+ add r0, r0, r1
+ b 0b
iflush:
mcr p15, 0, r10, c7, c10, 4 @ DSB
mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
@@ -1273,7 +1275,7 @@
__armv5tej_mmu_cache_flush:
tst r4, #1
movne pc, lr
-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
+1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
mcr p15, 0, r0, c7, c5, 0 @ flush I cache
mcr p15, 0, r0, c7, c10, 4 @ drain WB
@@ -1351,7 +1353,7 @@
1: ldrb r2, [r0], #1
teq r2, #0
moveq pc, lr
-2: writeb r2, r3
+2: writeb r2, r3, r1
mov r1, #0x00020000
3: subs r1, r1, #1
bne 3b
@@ -1405,7 +1407,11 @@
__hyp_reentry_vectors:
W(b) . @ reset
W(b) . @ undef
+#ifdef CONFIG_EFI_STUB
+ W(b) __enter_kernel_from_hyp @ hvc from HYP
+#else
W(b) . @ svc
+#endif
W(b) . @ pabort
W(b) . @ dabort
W(b) __enter_kernel @ hyp
@@ -1424,64 +1430,87 @@
reloc_code_end:
#ifdef CONFIG_EFI_STUB
- .align 2
-_start: .long start - .
+__enter_kernel_from_hyp:
+ mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
+ bic r0, r0, #0x5 @ disable MMU and caches
+ mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
+ isb
+ b __enter_kernel
-ENTRY(efi_stub_entry)
- @ allocate space on stack for passing current zImage address
- @ and for the EFI stub to return of new entry point of
- @ zImage, as EFI stub may copy the kernel. Pointer address
- @ is passed in r2. r0 and r1 are passed through from the
- @ EFI firmware to efi_entry
- adr ip, _start
- ldr r3, [ip]
- add r3, r3, ip
- stmfd sp!, {r3, lr}
- mov r2, sp @ pass zImage address in r2
- bl efi_entry
+ENTRY(efi_enter_kernel)
+ mov r4, r0 @ preserve image base
+ mov r8, r1 @ preserve DT pointer
- @ Check for error return from EFI stub. r0 has FDT address
- @ or error code.
- cmn r0, #1
- beq efi_load_fail
+ adr_l r0, call_cache_fn
+ adr r1, 0f @ clean the region of code we
+ bl cache_clean_flush @ may run with the MMU off
- @ Preserve return value of efi_entry() in r4
- mov r4, r0
+#ifdef CONFIG_ARM_VIRT_EXT
+ @
+ @ The EFI spec does not support booting on ARM in HYP mode,
+ @ since it mandates that the MMU and caches are on, with all
+ @ 32-bit addressable DRAM mapped 1:1 using short descriptors.
+ @
+ @ While the EDK2 reference implementation adheres to this,
+ @ U-Boot might decide to enter the EFI stub in HYP mode
+ @ anyway, with the MMU and caches either on or off.
+ @
+ mrs r0, cpsr @ get the current mode
+ msr spsr_cxsf, r0 @ record boot mode
+ and r0, r0, #MODE_MASK @ are we running in HYP mode?
+ cmp r0, #HYP_MODE
+ bne .Lefi_svc
- @ our cache maintenance code relies on CP15 barrier instructions
- @ but since we arrived here with the MMU and caches configured
- @ by UEFI, we must check that the CP15BEN bit is set in SCTLR.
- @ Note that this bit is RAO/WI on v6 and earlier, so the ISB in
- @ the enable path will be executed on v7+ only.
- mrc p15, 0, r1, c1, c0, 0 @ read SCTLR
- tst r1, #(1 << 5) @ CP15BEN bit set?
- bne 0f
- orr r1, r1, #(1 << 5) @ CP15 barrier instructions
- mcr p15, 0, r1, c1, c0, 0 @ write SCTLR
- ARM( .inst 0xf57ff06f @ v7+ isb )
- THUMB( isb )
+ mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
+ tst r1, #0x1 @ MMU enabled at HYP?
+ beq 1f
-0: bl cache_clean_flush
- bl cache_off
+ @
+ @ When running in HYP mode with the caches on, we're better
+ @ off just carrying on using the cached 1:1 mapping that the
+ @ firmware provided. Set up the HYP vectors so HVC instructions
+ @ issued from HYP mode take us to the correct handler code. We
+ @ will disable the MMU before jumping to the kernel proper.
+ @
+ ARM( bic r1, r1, #(1 << 30) ) @ clear HSCTLR.TE
+ THUMB( orr r1, r1, #(1 << 30) ) @ set HSCTLR.TE
+ mcr p15, 4, r1, c1, c0, 0
+ adr r0, __hyp_reentry_vectors
+ mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
+ isb
+ b .Lefi_hyp
- @ Set parameters for booting zImage according to boot protocol
- @ put FDT address in r2, it was returned by efi_entry()
- @ r1 is the machine type, and r0 needs to be 0
- mov r0, #0
- mov r1, #0xFFFFFFFF
- mov r2, r4
+ @
+ @ When running in HYP mode with the caches off, we need to drop
+ @ into SVC mode now, and let the decompressor set up its cached
+ @ 1:1 mapping as usual.
+ @
+1: mov r9, r4 @ preserve image base
+ bl __hyp_stub_install @ install HYP stub vectors
+ safe_svcmode_maskall r1 @ drop to SVC mode
+ msr spsr_cxsf, r0 @ record boot mode
+ orr r4, r9, #1 @ restore image base and set LSB
+ b .Lefi_hyp
+.Lefi_svc:
+#endif
+ mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
+ tst r0, #0x1 @ MMU enabled?
+ orreq r4, r4, #1 @ set LSB if not
- @ Branch to (possibly) relocated zImage that is in [sp]
- ldr lr, [sp]
- ldr ip, =start_offset
- add lr, lr, ip
- mov pc, lr @ no mode switch
+.Lefi_hyp:
+ mov r0, r8 @ DT start
+ add r1, r8, r2 @ DT end
+ bl cache_clean_flush
-efi_load_fail:
- @ Return EFI_LOAD_ERROR to EFI firmware on error.
- ldr r0, =0x80000001
- ldmfd sp!, {ip, pc}
-ENDPROC(efi_stub_entry)
+ adr r0, 0f @ switch to our stack
+ ldr sp, [r0]
+ add sp, sp, r0
+
+ mov r5, #0 @ appended DTB size
+ mov r7, #0xFFFFFFFF @ machine ID
+ b wont_overwrite
+ENDPROC(efi_enter_kernel)
+0: .long .L_user_stack_end - .
#endif
.align
diff --git a/arch/arm/boot/compressed/libfdt_env.h b/arch/arm/boot/compressed/libfdt_env.h
deleted file mode 100644
index 6a0f1f5..0000000
--- a/arch/arm/boot/compressed/libfdt_env.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ARM_LIBFDT_ENV_H
-#define _ARM_LIBFDT_ENV_H
-
-#include <linux/limits.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <asm/byteorder.h>
-
-#define INT32_MAX S32_MAX
-#define UINT32_MAX U32_MAX
-
-typedef __be16 fdt16_t;
-typedef __be32 fdt32_t;
-typedef __be64 fdt64_t;
-
-#define fdt16_to_cpu(x) be16_to_cpu(x)
-#define cpu_to_fdt16(x) cpu_to_be16(x)
-#define fdt32_to_cpu(x) be32_to_cpu(x)
-#define cpu_to_fdt32(x) cpu_to_be32(x)
-#define fdt64_to_cpu(x) be64_to_cpu(x)
-#define cpu_to_fdt64(x) cpu_to_be64(x)
-
-#endif
diff --git a/arch/arm/boot/compressed/piggy.S b/arch/arm/boot/compressed/piggy.S
index 0284f84..2757764 100644
--- a/arch/arm/boot/compressed/piggy.S
+++ b/arch/arm/boot/compressed/piggy.S
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
- .section .piggydata,#alloc
+ .section .piggydata, "a"
.globl input_data
input_data:
.incbin "arch/arm/boot/compressed/piggy_data"
diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S
index 51b0786..1bcb68a 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
@@ -2,6 +2,7 @@
/*
* Copyright (C) 2000 Russell King
*/
+#include <asm/vmlinux.lds.h>
#ifdef CONFIG_CPU_ENDIAN_BE8
#define ZIMAGE_MAGIC(x) ( (((x) >> 24) & 0x000000ff) | \
@@ -17,8 +18,11 @@
SECTIONS
{
/DISCARD/ : {
+ COMMON_DISCARDS
*(.ARM.exidx*)
*(.ARM.extab*)
+ *(.note.*)
+ *(.rel.*)
/*
* Discard any r/w data - this produces a link error if we have any,
* which is required for PIC decompression. Local data generates
@@ -36,17 +40,16 @@
*(.start)
*(.text)
*(.text.*)
- *(.fixup)
- *(.gnu.warning)
- *(.glue_7t)
- *(.glue_7)
+ ARM_STUBS_TEXT
}
.table : ALIGN(4) {
_table_start = .;
- LONG(ZIMAGE_MAGIC(4))
+ LONG(ZIMAGE_MAGIC(6))
LONG(ZIMAGE_MAGIC(0x5a534c4b))
LONG(ZIMAGE_MAGIC(__piggy_size_addr - _start))
LONG(ZIMAGE_MAGIC(_kernel_bss_size))
+ LONG(ZIMAGE_MAGIC(TEXT_OFFSET))
+ LONG(ZIMAGE_MAGIC(MALLOC_SIZE))
LONG(0)
_table_end = .;
}
@@ -64,9 +67,11 @@
_etext = .;
.got.plt : { *(.got.plt) }
+#ifndef CONFIG_EFI_STUB
_got_start = .;
.got : { *(.got) }
_got_end = .;
+#endif
/* ensure the zImage file size is always a multiple of 64 bits */
/* (without a dummy byte, ld just ignores the empty section) */
@@ -75,11 +80,14 @@
#ifdef CONFIG_EFI_STUB
.data : ALIGN(4096) {
__pecoff_data_start = .;
+ _got_start = .;
+ *(.got)
+ _got_end = .;
/*
* The EFI stub always executes from RAM, and runs strictly before the
* decompressor, so we can make an exception for its r/w data, and keep it
*/
- *(.data.efistub)
+ *(.data.efistub .bss.efistub)
__pecoff_data_end = .;
/*
@@ -124,12 +132,10 @@
PROVIDE(__pecoff_data_size = ALIGN(512) - ADDR(.data));
PROVIDE(__pecoff_end = ALIGN(512));
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
+ STABS_DEBUG
+ DWARF_DEBUG
+ ARM_DETAILS
+
+ ARM_ASSERTS
}
ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b21b3a6..7e81516 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -37,17 +37,26 @@
at91-ariag25.dtb \
at91-ariettag25.dtb \
at91-cosino_mega2560.dtb \
- at91-kizboxmini.dtb \
+ at91-kizboxmini-base.dtb \
+ at91-kizboxmini-mb.dtb \
+ at91-kizboxmini-rd.dtb \
+ at91-smartkiz.dtb \
at91-wb45n.dtb \
at91sam9g15ek.dtb \
+ at91sam9g25-gardena-smart-gateway.dtb \
at91sam9g25ek.dtb \
at91sam9g35ek.dtb \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
+dtb-$(CONFIG_SOC_SAM9X60) += \
+ at91-sam9x60ek.dtb
dtb-$(CONFIG_SOC_SAM_V7) += \
- at91-kizbox2.dtb \
+ at91-kizbox2-2.dtb \
+ at91-kizbox3-hs.dtb \
at91-nattis-2-natte-2.dtb \
at91-sama5d27_som1_ek.dtb \
+ at91-sama5d27_wlsom1_ek.dtb \
+ at91-sama5d2_icp.dtb \
at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
@@ -83,6 +92,7 @@
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
bcm2837-rpi-cm3-io3.dtb \
+ bcm2711-rpi-4-b.dtb \
bcm2835-rpi-zero.dtb \
bcm2835-rpi-zero-w.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += \
@@ -113,10 +123,12 @@
bcm47094-luxul-abr-4500.dtb \
bcm47094-luxul-xap-1610.dtb \
bcm47094-luxul-xbr-4500.dtb \
+ bcm47094-luxul-xwc-2000.dtb \
bcm47094-luxul-xwr-3100.dtb \
bcm47094-luxul-xwr-3150-v1.dtb \
bcm47094-netgear-r8500.dtb \
bcm47094-phicomm-k3.dtb \
+ bcm53016-meraki-mr32.dtb \
bcm94708.dtb \
bcm94709.dtb \
bcm953012er.dtb \
@@ -172,6 +184,7 @@
exynos3250-monk.dtb \
exynos3250-rinato.dtb
dtb-$(CONFIG_ARCH_EXYNOS4) += \
+ exynos4210-i9100.dtb \
exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
@@ -228,6 +241,7 @@
hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += \
integratorap.dtb \
+ integratorap-im-pd1.dtb \
integratorcp.dtb
dtb-$(CONFIG_ARCH_IXP4XX) += \
intel-ixp42x-linksys-nslu2.dtb \
@@ -270,6 +284,7 @@
kirkwood-iomega_ix2_200.dtb \
kirkwood-is2.dtb \
kirkwood-km_kirkwood.dtb \
+ kirkwood-l-50.dtb \
kirkwood-laplug.dtb \
kirkwood-linkstation-lsqvl.dtb \
kirkwood-linkstation-lsvl.dtb \
@@ -337,12 +352,15 @@
pxa168-aspenite.dtb \
pxa910-dkb.dtb \
mmp2-brownstone.dtb \
- mmp2-olpc-xo-1-75.dtb
+ mmp2-olpc-xo-1-75.dtb \
+ mmp3-dell-ariel.dtb
dtb-$(CONFIG_ARCH_MPS2) += \
mps2-an385.dtb \
mps2-an399.dtb
dtb-$(CONFIG_ARCH_MOXART) += \
moxart-uc7112lx.dtb
+dtb-$(CONFIG_ARCH_SD5203) += \
+ sd5203.dtb
dtb-$(CONFIG_SOC_IMX1) += \
imx1-ads.dtb \
imx1-apf9328.dtb
@@ -402,6 +420,7 @@
imx6dl-aristainetos2_4.dtb \
imx6dl-aristainetos2_7.dtb \
imx6dl-colibri-eval-v3.dtb \
+ imx6dl-colibri-v1_1-eval-v3.dtb \
imx6dl-cubox-i.dtb \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
@@ -418,6 +437,10 @@
imx6dl-gw560x.dtb \
imx6dl-gw5903.dtb \
imx6dl-gw5904.dtb \
+ imx6dl-gw5907.dtb \
+ imx6dl-gw5910.dtb \
+ imx6dl-gw5912.dtb \
+ imx6dl-gw5913.dtb \
imx6dl-hummingboard.dtb \
imx6dl-hummingboard-emmc-som-v15.dtb \
imx6dl-hummingboard-som-v15.dtb \
@@ -432,6 +455,12 @@
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-mira-rdk-nand.dtb \
imx6dl-phytec-pbab01.dtb \
+ imx6dl-pico-dwarf.dtb \
+ imx6dl-pico-hobbit.dtb \
+ imx6dl-pico-nymph.dtb \
+ imx6dl-pico-pi.dtb \
+ imx6dl-prtrvt.dtb \
+ imx6dl-prtvt7.dtb \
imx6dl-rex-basic.dtb \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
@@ -457,6 +486,7 @@
imx6dl-wandboard-revd1.dtb \
imx6dl-yapp4-draco.dtb \
imx6dl-yapp4-hydra.dtb \
+ imx6dl-yapp4-orion.dtb \
imx6dl-yapp4-ursa.dtb \
imx6q-apalis-eval.dtb \
imx6q-apalis-ixora.dtb \
@@ -489,6 +519,10 @@
imx6q-gw560x.dtb \
imx6q-gw5903.dtb \
imx6q-gw5904.dtb \
+ imx6q-gw5907.dtb \
+ imx6q-gw5910.dtb \
+ imx6q-gw5912.dtb \
+ imx6q-gw5913.dtb \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
imx6q-hummingboard-emmc-som-v15.dtb \
@@ -502,6 +536,7 @@
imx6q-icore-ofcap12.dtb \
imx6q-icore-rqs.dtb \
imx6q-kp-tpc.dtb \
+ imx6q-logicpd.dtb \
imx6q-marsboard.dtb \
imx6q-mccmon6.dtb \
imx6q-nitrogen6x.dtb \
@@ -511,7 +546,13 @@
imx6q-phytec-mira-rdk-emmc.dtb \
imx6q-phytec-mira-rdk-nand.dtb \
imx6q-phytec-pbab01.dtb \
+ imx6q-pico-dwarf.dtb \
+ imx6q-pico-hobbit.dtb \
+ imx6q-pico-nymph.dtb \
+ imx6q-pico-pi.dtb \
imx6q-pistachio.dtb \
+ imx6q-prti6q.dtb \
+ imx6q-prtwd2.dtb \
imx6q-rex-pro.dtb \
imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \
@@ -550,15 +591,19 @@
imx6qp-zii-rdu2.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
+ imx6sl-tolino-shine2hd.dtb \
+ imx6sl-tolino-shine3.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
- imx6sll-evk.dtb
+ imx6sll-evk.dtb \
+ imx6sll-kobo-clarahd.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-nitrogen6sx.dtb \
imx6sx-sabreauto.dtb \
imx6sx-sdb-reva.dtb \
imx6sx-sdb-sai.dtb \
imx6sx-sdb.dtb \
+ imx6sx-sdb-mqs.dtb \
imx6sx-softing-vining-2000.dtb \
imx6sx-udoo-neo-basic.dtb \
imx6sx-udoo-neo-extended.dtb \
@@ -574,6 +619,7 @@
imx6ul-kontron-n6310-s-43.dtb \
imx6ul-liteboard.dtb \
imx6ul-opos6uldev.dtb \
+ imx6ul-pico-dwarf.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
@@ -583,18 +629,24 @@
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
+ imx6ull-myir-mys-6ulx-eval.dtb \
+ imx6ull-opos6uldev.dtb \
imx6ull-phytec-segin-ff-rdk-nand.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-phytec-segin-lc-rdk-nand.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
+ imx7d-colibri-aster.dtb \
+ imx7d-colibri-emmc-aster.dtb \
imx7d-colibri-emmc-eval-v3.dtb \
imx7d-colibri-eval-v3.dtb \
imx7d-mba7.dtb \
imx7d-meerkat96.dtb \
imx7d-nitrogen7.dtb \
+ imx7d-pico-dwarf.dtb \
imx7d-pico-hobbit.dtb \
+ imx7d-pico-nymph.dtb \
imx7d-pico-pi.dtb \
imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb \
@@ -602,10 +654,12 @@
imx7d-sdb-sht11.dtb \
imx7d-zii-rmu2.dtb \
imx7d-zii-rpu2.dtb \
+ imx7s-colibri-aster.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-mba7.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_IMX7ULP) += \
+ imx7ulp-com.dtb \
imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
@@ -677,6 +731,7 @@
logicpd-som-lv-37xx-devkit.dtb \
omap3430-sdp.dtb \
omap3-beagle.dtb \
+ omap3-beagle-ab4.dtb \
omap3-beagle-xm.dtb \
omap3-beagle-xm-ab.dtb \
omap3-cm-t3517.dtb \
@@ -685,6 +740,7 @@
omap3-devkit8000.dtb \
omap3-devkit8000-lcd43.dtb \
omap3-devkit8000-lcd70.dtb \
+ omap3-echo.dtb \
omap3-evm.dtb \
omap3-evm-37xx.dtb \
omap3-gta04a3.dtb \
@@ -753,6 +809,9 @@
am335x-moxa-uc-2101.dtb \
am335x-moxa-uc-8100-me-t.dtb \
am335x-nano.dtb \
+ am335x-netcan-plus-1xx.dtb \
+ am335x-netcom-plus-2xx.dtb \
+ am335x-netcom-plus-8xx.dtb \
am335x-pdu001.dtb \
am335x-pepper.dtb \
am335x-phycore-rdk.dtb \
@@ -765,6 +824,7 @@
am335x-wega-rdk.dtb \
am335x-osd3358-sm-red.dtb
dtb-$(CONFIG_ARCH_OMAP4) += \
+ omap4-droid-bionic-xt875.dtb \
omap4-droid4-xt894.dtb \
omap4-duovero-parlor.dtb \
omap4-kc1.dtb \
@@ -791,6 +851,7 @@
am57xx-beagle-x15.dtb \
am57xx-beagle-x15-revb1.dtb \
am57xx-beagle-x15-revc.dtb \
+ am5729-beagleboneai.dtb \
am57xx-cl-som-am57x.dtb \
am57xx-sbc-am57x.dtb \
am572x-idk.dtb \
@@ -815,7 +876,12 @@
dtb-$(CONFIG_ARCH_ACTIONS) += \
owl-s500-cubieboard6.dtb \
owl-s500-guitar-bb-rev-b.dtb \
+ owl-s500-labrador-base-m.dtb \
+ owl-s500-roseapplepi.dtb \
owl-s500-sparky.dtb
+dtb-$(CONFIG_ARCH_PICOXCELL) += \
+ picoxcell-pc7302-pc3x2.dtb \
+ picoxcell-pc7302-pc3x3.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += \
prima2-evb.dtb
dtb-$(CONFIG_ARCH_PXA) += \
@@ -843,6 +909,7 @@
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
+ qcom-ipq8064-rb3011.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-fairphone-fp2.dtb \
@@ -855,6 +922,9 @@
dtb-$(CONFIG_ARCH_RDA) += \
rda8810pl-orangepi-2g-iot.dtb \
rda8810pl-orangepi-i96.dtb
+dtb-$(CONFIG_ARCH_REALTEK) += \
+ rtd1195-horseradish.dtb \
+ rtd1195-mele-x1000.dtb
dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb \
arm-realview-pb11mp.dtb \
@@ -876,6 +946,8 @@
r7s9210-rza2mevb.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
+ r8a7742-iwg21d-q7.dtb \
+ r8a7742-iwg21d-q7-dbcm-ca.dtb \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
@@ -923,6 +995,7 @@
rk3288-popmetal.dtb \
rk3288-r89.dtb \
rk3288-rock2-square.dtb \
+ rk3288-rock-pi-n8.dtb \
rk3288-tinker.dtb \
rk3288-tinker-s.dtb \
rk3288-veyron-brain.dtb \
@@ -987,11 +1060,18 @@
stm32746g-eval.dtb \
stm32h743i-eval.dtb \
stm32h743i-disco.dtb \
+ stm32mp153c-dhcom-drc02.dtb \
stm32mp157a-avenger96.dtb \
+ stm32mp157a-dhcor-avenger96.dtb \
stm32mp157a-dk1.dtb \
+ stm32mp157a-iot-box.dtb \
+ stm32mp157a-stinger96.dtb \
+ stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
- stm32mp157c-ev1.dtb
+ stm32mp157c-ev1.dtb \
+ stm32mp157c-lxa-mc1.dtb \
+ stm32mp157c-odyssey.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
@@ -1029,6 +1109,7 @@
sun5i-a13-licheepi-one.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
+ sun5i-a13-pocketbook-touch-lux-3.dtb \
sun5i-a13-q8-tablet.dtb \
sun5i-a13-utoo-p66.dtb \
sun5i-gr8-chip-pro.dtb \
@@ -1059,6 +1140,7 @@
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-icnova-swac.dtb \
sun7i-a20-lamobo-r1.dtb \
+ sun7i-a20-linutronix-testbox-v2.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
@@ -1066,6 +1148,7 @@
sun7i-a20-olimex-som204-evb.dtb \
sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
+ sun7i-a20-olinuxino-lime-emmc.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
sun7i-a20-olinuxino-micro.dtb \
@@ -1105,6 +1188,7 @@
sun8i-h3-beelink-x2.dtb \
sun8i-h3-libretech-all-h3-cc.dtb \
sun8i-h3-mapleboard-mp130.dtb \
+ sun8i-h3-nanopi-duo2.dtb \
sun8i-h3-nanopi-m1.dtb \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
@@ -1118,12 +1202,14 @@
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-orangepi-zero-plus2.dtb \
sun8i-h3-rervision-dvk.dtb \
+ sun8i-h3-emlid-neutis-n5h3-devboard.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic.dtb \
sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-s3-lichee-zero-plus.dtb \
+ sun8i-s3-pinecube.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
@@ -1136,6 +1222,7 @@
dtb-$(CONFIG_ARCH_TANGO) += \
tango4-vantage-1172.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
+ tegra20-acer-a500-picasso.dtb \
tegra20-harmony.dtb \
tegra20-colibri-eval-v3.dtb \
tegra20-colibri-iris.dtb \
@@ -1149,6 +1236,9 @@
dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-apalis-eval.dtb \
tegra30-apalis-v1.1-eval.dtb \
+ tegra30-asus-nexus7-grouper-PM269.dtb \
+ tegra30-asus-nexus7-grouper-E1565.dtb \
+ tegra30-asus-nexus7-tilapia-E1565.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
@@ -1171,7 +1261,10 @@
ste-hrefprev60-stuib.dtb \
ste-hrefprev60-tvk.dtb \
ste-hrefv60plus-stuib.dtb \
- ste-hrefv60plus-tvk.dtb
+ ste-hrefv60plus-tvk.dtb \
+ ste-href520-tvk.dtb \
+ ste-ux500-samsung-golden.dtb \
+ ste-ux500-samsung-skomer.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ld4-ref.dtb \
uniphier-ld6b-ref.dtb \
@@ -1227,6 +1320,8 @@
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
+ armada-385-clearfog-gtr-s4.dtb \
+ armada-385-clearfog-gtr-l8.dtb \
armada-385-db-88f6820-amc.dtb \
armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \
@@ -1276,10 +1371,15 @@
mt8127-moose.dtb \
mt8135-evbp1.dtb
dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
+dtb-$(CONFIG_ARCH_MSTARV7) += \
+ mstar-infinity-msc313-breadbee_crust.dtb \
+ mstar-infinity3-msc313e-breadbee.dtb \
+ mstar-mercury5-ssc8336n-midrived08.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-ast2600-evb.dtb \
+ aspeed-bmc-amd-ethanolx.dtb \
aspeed-bmc-arm-centriq2400-rep.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-facebook-cmm.dtb \
@@ -1287,7 +1387,10 @@
aspeed-bmc-facebook-tiogapass.dtb \
aspeed-bmc-facebook-wedge40.dtb \
aspeed-bmc-facebook-wedge100.dtb \
+ aspeed-bmc-facebook-wedge400.dtb \
aspeed-bmc-facebook-yamp.dtb \
+ aspeed-bmc-facebook-yosemitev2.dtb \
+ aspeed-bmc-ibm-rainier.dtb \
aspeed-bmc-intel-s2600wf.dtb \
aspeed-bmc-inspur-fp5280g2.dtb \
aspeed-bmc-lenovo-hr630.dtb \
@@ -1295,9 +1398,12 @@
aspeed-bmc-microsoft-olympus.dtb \
aspeed-bmc-opp-lanyang.dtb \
aspeed-bmc-opp-mihawk.dtb \
+ aspeed-bmc-opp-mowgli.dtb \
+ aspeed-bmc-opp-nicole.dtb \
aspeed-bmc-opp-palmetto.dtb \
aspeed-bmc-opp-romulus.dtb \
aspeed-bmc-opp-swift.dtb \
+ aspeed-bmc-opp-tacoma.dtb \
aspeed-bmc-opp-vesnin.dtb \
aspeed-bmc-opp-witherspoon.dtb \
aspeed-bmc-opp-zaius.dtb \
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index d3036ea..3b0675a 100644
--- a/arch/arm/boot/dts/alpine.dtsi
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -91,7 +91,7 @@
};
/* Interrupt Controller */
- gic: gic@fb001000 {
+ gic: interrupt-controller@fb001000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
index 386d5f8..56915b6 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
index b0df725..d8d6039 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
index d6aa46e..8096d45 100644
--- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts
+++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/am335x-baltos-leds.dtsi
index 4e11a16..9a79f72 100644
--- a/arch/arm/boot/dts/am335x-baltos-leds.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos-leds.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi
index ed235f2..77e23e7 100644
--- a/arch/arm/boot/dts/am335x-baltos.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
@@ -258,18 +258,6 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&cppi41dma {
- status = "okay";
-};
-
#include "tps65910.dtsi"
&tps {
@@ -381,7 +369,7 @@
&mmc2 {
status = "okay";
vmmc-supply = <&wl12xx_vmmc>;
- ti,non-removable;
+ non-removable;
bus-width = <4>;
cap-power-off-card;
pinctrl-names = "default";
@@ -405,10 +393,10 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
-&gpio3 {
+&gpio3_target {
ti,no-reset-on-init;
};
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 89b4cf2..2d51d4b 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
@@ -191,38 +191,16 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "peripheral";
interrupts-extended = <&intc 18 &tps 0>;
interrupt-names = "mc", "vbus";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 43bfbce..b5d85ef 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
index 91f93bc..64c3e92 100644
--- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi
+++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/display/tda998x.h>
@@ -22,6 +22,7 @@
pinctrl-0 = <&emmc_pins>;
bus-width = <8>;
status = "okay";
+ non-removable;
};
&am33xx_pinmux {
diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
index 3124d94..86cad99 100644
--- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts
+++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -75,7 +75,6 @@
bus-width = <4>;
non-removable;
cap-power-off-card;
- ti,needs-special-hs-handling;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index d392866..b4feb85 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -23,3 +23,147 @@
opp-supported-hw = <0x06 0x0100>;
};
};
+
+&gpio0 {
+ gpio-line-names =
+ "[ethernet]",
+ "[ethernet]",
+ "P9_22 [spi0_sclk]",
+ "P9_21 [spi0_d0]",
+ "P9_18 [spi0_d1]",
+ "P9_17 [spi0_cs0]",
+ "[sd card]",
+ "P9_42A [ecappwm0]",
+ "P8_35 [hdmi]",
+ "P8_33 [hdmi]",
+ "P8_31 [hdmi]",
+ "P8_32 [hdmi]",
+ "P9_20 [i2c2_sda]",
+ "P9_19 [i2c2_scl]",
+ "P9_26 [uart1_rxd]",
+ "P9_24 [uart1_txd]",
+ "[ethernet]",
+ "[ethernet]",
+ "[usb]",
+ "[hdmi]",
+ "P9_41B",
+ "[ethernet]",
+ "P8_19 [ehrpwm2a]",
+ "P8_13 [ehrpwm2b]",
+ "[NC]",
+ "[NC]",
+ "P8_14",
+ "P8_17",
+ "[ethernet]",
+ "[ethernet]",
+ "P9_11 [uart4_rxd]",
+ "P9_13 [uart4_txd]";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "P8_25 [emmc]",
+ "[emmc]",
+ "P8_5 [emmc]",
+ "P8_6 [emmc]",
+ "P8_23 [emmc]",
+ "P8_22 [emmc]",
+ "P8_3 [emmc]",
+ "P8_4 [emmc]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "P8_12",
+ "P8_11",
+ "P8_16",
+ "P8_15",
+ "P9_15A",
+ "P9_23",
+ "P9_14 [ehrpwm1a]",
+ "P9_16 [ehrpwm1b]",
+ "[emmc]",
+ "[usr0 led]",
+ "[usr1 led]",
+ "[usr2 led]",
+ "[usr3 led]",
+ "[hdmi]",
+ "[usb]",
+ "[hdmi audio]",
+ "P9_12",
+ "P8_26",
+ "P8_21 [emmc]",
+ "P8_20 [emmc]";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "P9_15B",
+ "P8_18",
+ "P8_7",
+ "P8_8",
+ "P8_10",
+ "P8_9",
+ "P8_45 [hdmi]",
+ "P8_46 [hdmi]",
+ "P8_43 [hdmi]",
+ "P8_44 [hdmi]",
+ "P8_41 [hdmi]",
+ "P8_42 [hdmi]",
+ "P8_39 [hdmi]",
+ "P8_40 [hdmi]",
+ "P8_37 [hdmi]",
+ "P8_38 [hdmi]",
+ "P8_36 [hdmi]",
+ "P8_34 [hdmi]",
+ "[ethernet]",
+ "[ethernet]",
+ "[ethernet]",
+ "[ethernet]",
+ "P8_27 [hdmi]",
+ "P8_29 [hdmi]",
+ "P8_28 [hdmi]",
+ "P8_30 [hdmi]",
+ "[emmc]",
+ "[emmc]",
+ "[emmc]",
+ "[emmc]",
+ "[emmc]",
+ "[emmc]";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "[ethernet]",
+ "[ethernet]",
+ "[ethernet]",
+ "[ethernet]",
+ "[ethernet]",
+ "[i2c0]",
+ "[i2c0]",
+ "[emu]",
+ "[emu]",
+ "[ethernet]",
+ "[ethernet]",
+ "[NC]",
+ "[NC]",
+ "[usb]",
+ "P9_31 [spi1_sclk]",
+ "P9_29 [spi1_d0]",
+ "P9_30 [spi1_d1]",
+ "P9_28 [spi1_cs0]",
+ "P9_42B [ecappwm0]",
+ "P9_27",
+ "P9_41A",
+ "P9_25",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]";
+};
diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index 2f6652e..c696d57 100644
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -278,38 +278,16 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "peripheral";
interrupts-extended = <&intc 18 &tps 0>;
interrupt-names = "mc", "vbus";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&i2c0 {
baseboard_eeprom: baseboard_eeprom@50 {
compatible = "atmel,24c256";
@@ -389,7 +367,6 @@
bus-width = <4>;
non-removable;
cap-power-off-card;
- ti,needs-special-hs-handling;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
diff --git a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi
index 7a88266..9f7fb63 100644
--- a/arch/arm/boot/dts/am335x-bonegreen-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bonegreen-common.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
&ldo3_reg {
diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
index 4092cd1..7615327 100644
--- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
+++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -75,7 +75,6 @@
bus-width = <4>;
non-removable;
cap-power-off-card;
- ti,needs-special-hs-handling;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
diff --git a/arch/arm/boot/dts/am335x-bonegreen.dts b/arch/arm/boot/dts/am335x-bonegreen.dts
index c12bb07..18cc0f4 100644
--- a/arch/arm/boot/dts/am335x-bonegreen.dts
+++ b/arch/arm/boot/dts/am335x-bonegreen.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts
index 8cd81dc..5660b5f 100644
--- a/arch/arm/boot/dts/am335x-chiliboard.dts
+++ b/arch/arm/boot/dts/am335x-chiliboard.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
* Author: Rostislav Lisovy <lisovy@jablotron.cz>
*/
/dts-v1/;
@@ -153,30 +153,12 @@
};
/* USB */
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_drvvbus>;
-
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
/* microSD */
&mmc1 {
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi
index b31e2f7..43b61e4 100644
--- a/arch/arm/boot/dts/am335x-chilisom.dtsi
+++ b/arch/arm/boot/dts/am335x-chilisom.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
+ * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
* Author: Rostislav Lisovy <lisovy@jablotron.cz>
*/
#include "am33xx.dtsi"
diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts
index 09b36df..08c89f1 100644
--- a/arch/arm/boot/dts/am335x-cm-t335.dts
+++ b/arch/arm/boot/dts/am335x-cm-t335.dts
@@ -330,26 +330,6 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&cppi41dma {
- status = "okay";
-};
-
&epwmss0 {
status = "okay";
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index a001457..12dffcc 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -113,7 +113,7 @@
};
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 0>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
@@ -121,35 +121,15 @@
};
panel {
- compatible = "ti,tilcdc,panel";
- status = "okay";
+ compatible = "tfc,s9700rtwv43tr-01b";
+
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins_s0>;
- panel-info {
- ac-bias = <255>;
- ac-bias-intrpt = <0>;
- dma-burst-sz = <16>;
- bpp = <32>;
- fdd = <0x80>;
- sync-edge = <0>;
- sync-ctrl = <1>;
- raster-order = <0>;
- fifo-th = <0>;
- };
+ backlight = <&backlight>;
- display-timings {
- 800x480p62 {
- clock-frequency = <30000000>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch = <39>;
- hback-porch = <39>;
- hsync-len = <47>;
- vback-porch = <29>;
- vfront-porch = <13>;
- vsync-len = <2>;
- hsync-active = <1>;
- vsync-active = <1>;
+ port {
+ panel_0: endpoint@0 {
+ remote-endpoint = <&lcdc_0>;
};
};
};
@@ -433,35 +413,10 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -525,6 +480,12 @@
status = "okay";
blue-and-red-wiring = "crossed";
+
+ port {
+ lcdc_0: endpoint@0 {
+ remote-endpoint = <&panel_0>;
+ };
+ };
};
&elm {
@@ -782,8 +743,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wlan_pins>;
- ti,non-removable;
- ti,needs-special-hs-handling;
+ non-removable;
cap-power-off-card;
keep-power-in-suspend;
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index e28a5b8..bf05b68 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
@@ -183,36 +183,16 @@
};
panel {
- compatible = "ti,tilcdc,panel";
+ compatible = "newhaven,nhd-4.3-480272ef-atxl";
+
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_pins_default>;
pinctrl-1 = <&lcd_pins_sleep>;
backlight = <&lcd_bl>;
- status = "okay";
- panel-info {
- ac-bias = <255>;
- ac-bias-intrpt = <0>;
- dma-burst-sz = <16>;
- bpp = <32>;
- fdd = <0x80>;
- sync-edge = <0>;
- sync-ctrl = <1>;
- raster-order = <0>;
- fifo-th = <0>;
- };
- display-timings {
- 480x272 {
- hactive = <480>;
- vactive = <272>;
- hback-porch = <43>;
- hfront-porch = <8>;
- hsync-len = <4>;
- vback-porch = <12>;
- vfront-porch = <4>;
- vsync-len = <10>;
- clock-frequency = <9000000>;
- hsync-active = <0>;
- vsync-active = <0>;
+
+ port {
+ panel_0: endpoint@0 {
+ remote-endpoint = <&lcdc_0>;
};
};
};
@@ -523,35 +503,10 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&epwmss2 {
status = "okay";
@@ -693,14 +648,14 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
&mmc2 {
status = "okay";
vmmc-supply = <&wl12xx_vmmc>;
- ti,non-removable;
+ non-removable;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
@@ -750,6 +705,12 @@
status = "okay";
blue-and-red-wiring = "crossed";
+
+ port {
+ lcdc_0: endpoint@0 {
+ remote-endpoint = <&panel_0>;
+ };
+ };
};
&rtc {
diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts
index c9611ea..1918766 100644
--- a/arch/arm/boot/dts/am335x-guardian.dts
+++ b/arch/arm/boot/dts/am335x-guardian.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
/dts-v1/;
@@ -105,6 +105,7 @@
ti,timers = <&timer7>;
pinctrl-names = "default";
pinctrl-0 = <&dmtimer7_pins>;
+ ti,clock-source = <0x01>;
};
vmmcsd_fixed: regulator-3v3 {
@@ -115,10 +116,6 @@
};
};
-&cppi41dma {
- status = "okay";
-};
-
&elm {
status = "okay";
};
@@ -328,30 +325,12 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
&usb0 {
dr_mode = "peripheral";
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
};
&usb1 {
dr_mode = "host";
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
};
&am33xx_pinmux {
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index 204bccf..b958ab5 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
@@ -287,6 +287,19 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ /* osd9616p0899-10 */
+ display@3c {
+ compatible = "solomon,ssd1306fb-i2c";
+ reg = <0x3c>;
+ solomon,height = <16>;
+ solomon,width = <96>;
+ solomon,com-seq;
+ solomon,com-invdir;
+ solomon,page-offset = <0>;
+ solomon,prechargep1 = <2>;
+ solomon,prechargep2 = <13>;
+ };
};
&spi0 {
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index eabcc8b..c9f354f 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -217,35 +217,10 @@
pinctrl-0 = <&uart0_pins>;
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
#include "tps65910.dtsi"
&tps {
diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts
index a8005e9..0f07846 100644
--- a/arch/arm/boot/dts/am335x-lxm.dts
+++ b/arch/arm/boot/dts/am335x-lxm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com
+ * Copyright (C) 2014 NovaTech LLC - https://www.novatechweb.com
*/
/dts-v1/;
@@ -160,11 +160,15 @@
serial_config1: serial_config1@20 {
compatible = "nxp,pca9539";
reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
};
serial_config2: serial_config2@21 {
compatible = "nxp,pca9539";
reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
};
tps: tps@2d {
@@ -283,36 +287,14 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "host";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&cpsw_emac0 {
phy-handle = <ðphy0>;
phy-mode = "rmii";
@@ -361,7 +343,7 @@
pinctrl-0 = <&emmc_pins>;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <8>;
- ti,non-removable;
+ non-removable;
status = "okay";
};
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
index 671d4a5..8121a19 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
+++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
@@ -111,27 +111,10 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
/* Power */
&vbat {
regulator-name = "vbat";
@@ -167,7 +150,7 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
@@ -176,7 +159,7 @@
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <8>;
pinctrl-0 = <&mmc1_pins_default>;
- ti,non-removable;
+ non-removable;
status = "okay";
};
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi
new file mode 100644
index 0000000..39e5d2c
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 MOXA Inc. - https://www.moxa.com/
+ *
+ * Author: Johnson Chen <johnsonch.chen@moxa.com>
+ */
+
+#include "am33xx.dtsi"
+
+/ {
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ vbat: vbat-regulator {
+ compatible = "regulator-fixed";
+ };
+
+ /* Power supply provides a fixed 3.3V @3A */
+ vmmcsd_fixed: vmmcsd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ buttons: push_button {
+ compatible = "gpio-keys";
+ };
+
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&minipcie_pins>;
+
+ minipcie_pins: pinmux_minipcie {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */
+ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */
+ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/
+ >;
+ };
+
+ push_button_pins: pinmux_push_button {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
+ >;
+ };
+
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */
+ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
+ >;
+ };
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
+ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)
+ AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+ AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+ AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
+ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
+ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
+
+ /* Slave 2 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */
+ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */
+
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
+ >;
+ };
+
+ mmc0_pins_default: pinmux_mmc0_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */
+ >;
+ };
+
+ mmc2_pins_default: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ /* eMMC */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */
+ >;
+ };
+
+ spi0_pins: pinmux_spi0 {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
+ >;
+ };
+
+};
+
+&uart0 {
+ /* Console */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+};
+
+&uart1 {
+ /* UART 1 setting */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&uart5 {
+ /* UART 2 setting */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@2d {
+ compatible = "ti,tps65910";
+ reg = <0x2d>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c16";
+ pagesize = <16>;
+ reg = <0x50>;
+ };
+
+ rtc_wdt: rtc_wdt@68 {
+ compatible = "dallas,ds1374";
+ reg = <0x68>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+ gpio_xten: gpio_xten@27 {
+ compatible = "nxp,pca9535";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x27>;
+ };
+};
+
+&usb0 {
+ dr_mode = "host";
+};
+
+&usb1 {
+ dr_mode = "host";
+};
+
+
+#include "tps65910.dtsi"
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc_reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+/* Power */
+&vbat {
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+};
+
+&mac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cpsw_default>;
+ dual_emac = <1>;
+ status = "okay";
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&davinci_mdio_default>;
+ status = "okay";
+
+ ethphy0: ethernet-phy@4 {
+ reg = <4>;
+ };
+
+ ethphy1: ethernet-phy@5 {
+ reg = <5>;
+ };
+};
+
+&cpsw_emac0 {
+ status = "okay";
+ phy-handle = <ðphy0>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+ status = "okay";
+ phy-handle = <ðphy1>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <2>;
+};
+
+&sham {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&gpio0_target {
+ ti,no-reset-on-init;
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <4>;
+ pinctrl-0 = <&mmc0_pins_default>;
+ cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&mmc3 {
+ dmas = <&edma_xbar 12 0 1
+ &edma_xbar 13 0 2>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <8>;
+ pinctrl-0 = <&mmc2_pins_default>;
+ ti,non-removable;
+ status = "okay";
+};
+
+&buttons {
+ pinctrl-names = "default";
+ pinctrl-0 = <&push_button_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@0 {
+ label = "push_button";
+ linux,code = <0x100>;
+ gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+ };
+};
+
+/* SPI Busses */
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+
+ m25p80@0 {
+ compatible = "mx25l6405d";
+ spi-max-frequency = <40000000>;
+
+ reg = <0>;
+ spi-cpol;
+ spi-cpha;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* reg : The partition's offset and size within the mtd bank. */
+ partitions@0 {
+ label = "MLO";
+ reg = <0x0 0x80000>;
+ };
+
+ partitions@1 {
+ label = "U-Boot";
+ reg = <0x80000 0x100000>;
+ };
+
+ partitions@2 {
+ label = "U-Boot Env";
+ reg = <0x180000 0x20000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
index 783d411..0c7949d 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
+++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
@@ -4,39 +4,19 @@
*
* Author: SZ Lin (林上智) <sz.lin@moxa.com>
*/
-
/dts-v1/;
-#include "am33xx.dtsi"
+#include "am335x-moxa-uc-8100-common.dtsi"
/ {
model = "Moxa UC-8100-ME-T";
compatible = "moxa,uc-8100-me-t", "ti,am33xx";
- cpus {
- cpu@0 {
- cpu0-supply = <&vdd1_reg>;
- };
- };
-
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
- vbat: vbat-regulator {
- compatible = "regulator-fixed";
- };
-
- /* Power supply provides a fixed 3.3V @3A */
- vmmcsd_fixed: vmmcsd-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsd_fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
-
leds {
compatible = "gpio-leds";
led1 {
@@ -88,259 +68,17 @@
default-state = "off";
};
};
-
- buttons: push_button {
- compatible = "gpio-keys";
- };
-
-};
-
-&am33xx_pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&minipcie_pins>;
-
- minipcie_pins: pinmux_minipcie {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */
- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */
- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/
- >;
- };
-
- push_button_pins: pinmux_push_button {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */
- >;
- };
-
- i2c0_pins: pinmux_i2c0_pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
- >;
- };
-
-
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */
- AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */
- >;
- };
-
- uart0_pins: pinmux_uart0_pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- >;
- };
-
- uart1_pins: pinmux_uart1_pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
- >;
- };
-
- uart2_pins: pinmux_uart2_pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */
- >;
- };
-
- cpsw_default: cpsw_default {
- pinctrl-single,pins = <
- /* Slave 1 */
- AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)
- AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
- AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
- AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
- AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
- AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
-
- /* Slave 2 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */
- AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */
- AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */
- AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */
- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */
-
- >;
- };
-
- davinci_mdio_default: davinci_mdio_default {
- pinctrl-single,pins = <
- /* MDIO */
- AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
- >;
- };
-
- mmc0_pins_default: pinmux_mmc0_pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */
- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */
- >;
- };
-
- mmc2_pins_default: pinmux_mmc2_pins {
- pinctrl-single,pins = <
- /* eMMC */
- AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */
- AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
- AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */
- >;
- };
-
- spi0_pins: pinmux_spi0 {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
- >;
- };
-
-};
-
-&uart0 {
- /* Console */
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
-
-&uart1 {
- /* UART 1 setting */
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-&uart5 {
- /* UART 2 setting */
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
-
- status = "okay";
- clock-frequency = <400000>;
-
tpm: tpm@20 {
compatible = "infineon,slb9645tt";
reg = <0x20>;
};
-
- tps: tps@2d {
- compatible = "ti,tps65910";
- reg = <0x2d>;
- };
-
- eeprom: eeprom@50 {
- compatible = "atmel,24c16";
- pagesize = <16>;
- reg = <0x50>;
- };
-
- rtc_wdt: rtc_wdt@68 {
- compatible = "dallas,ds1374";
- reg = <0x68>;
- };
};
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
-
- status = "okay";
- clock-frequency = <400000>;
- gpio_xten: gpio_xten@27 {
- compatible = "nxp,pca9535";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x27>;
- };
-};
-
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- dr_mode = "host";
-};
-
-&usb1 {
- status = "okay";
- dr_mode = "host";
-};
-
-&cppi41dma {
- status = "okay";
-};
-
-#include "tps65910.dtsi"
-
&tps {
- vcc1-supply = <&vbat>;
- vcc2-supply = <&vbat>;
- vcc3-supply = <&vbat>;
- vcc4-supply = <&vbat>;
- vcc5-supply = <&vbat>;
- vcc6-supply = <&vbat>;
- vcc7-supply = <&vbat>;
- vccio-supply = <&vbat>;
-
regulators {
- vrtc_reg: regulator@0 {
- regulator-always-on;
- };
-
- vio_reg: regulator@1 {
- regulator-always-on;
- };
-
vdd1_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
@@ -358,168 +96,6 @@
regulator-boot-on;
regulator-always-on;
};
-
- vdd3_reg: regulator@4 {
- regulator-always-on;
- };
-
- vdig1_reg: regulator@5 {
- regulator-always-on;
- };
-
- vdig2_reg: regulator@6 {
- regulator-always-on;
- };
-
- vpll_reg: regulator@7 {
- regulator-always-on;
- };
-
- vdac_reg: regulator@8 {
- regulator-always-on;
- };
-
- vaux1_reg: regulator@9 {
- regulator-always-on;
- };
-
- vaux2_reg: regulator@10 {
- regulator-always-on;
- };
-
- vaux33_reg: regulator@11 {
- regulator-always-on;
- };
-
- vmmc_reg: regulator@12 {
- compatible = "regulator-fixed";
- regulator-name = "vmmc_reg";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
};
};
-/* Power */
-&vbat {
- regulator-name = "vbat";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-};
-
-&mac {
- pinctrl-names = "default";
- pinctrl-0 = <&cpsw_default>;
- dual_emac = <1>;
- status = "okay";
-};
-
-&davinci_mdio {
- pinctrl-names = "default";
- pinctrl-0 = <&davinci_mdio_default>;
- status = "okay";
-
- ethphy0: ethernet-phy@4 {
- reg = <4>;
- };
-
- ethphy1: ethernet-phy@5 {
- reg = <5>;
- };
-};
-
-&cpsw_emac0 {
- status = "okay";
- phy-handle = <ðphy0>;
- phy-mode = "rmii";
- dual_emac_res_vlan = <1>;
-};
-
-&cpsw_emac1 {
- status = "okay";
- phy-handle = <ðphy1>;
- phy-mode = "rmii";
- dual_emac_res_vlan = <2>;
-};
-
-&sham {
- status = "okay";
-};
-
-&aes {
- status = "okay";
-};
-
-&gpio0 {
- ti,no-reset-on-init;
-};
-
-&mmc1 {
- pinctrl-names = "default";
- vmmc-supply = <&vmmcsd_fixed>;
- bus-width = <4>;
- pinctrl-0 = <&mmc0_pins_default>;
- cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
- wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
- status = "okay";
-};
-
-&mmc3 {
- dmas = <&edma_xbar 12 0 1
- &edma_xbar 13 0 2>;
- dma-names = "tx", "rx";
- pinctrl-names = "default";
- vmmc-supply = <&vmmcsd_fixed>;
- bus-width = <8>;
- pinctrl-0 = <&mmc2_pins_default>;
- ti,non-removable;
- status = "okay";
-};
-
-&buttons {
- pinctrl-names = "default";
- pinctrl-0 = <&push_button_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- button@0 {
- label = "push_button";
- linux,code = <0x100>;
- gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
- };
-};
-
-/* SPI Busses */
-&spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins>;
-
- m25p80@0 {
- compatible = "mx25l6405d";
- spi-max-frequency = <40000000>;
-
- reg = <0>;
- spi-cpol;
- spi-cpha;
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* reg : The partition's offset and size within the mtd bank. */
- partitions@0 {
- label = "MLO";
- reg = <0x0 0x80000>;
- };
-
- partitions@1 {
- label = "U-Boot";
- reg = <0x80000 0x100000>;
- };
-
- partitions@2 {
- label = "U-Boot Env";
- reg = <0x180000 0x20000>;
- };
- };
-};
diff --git a/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts
new file mode 100644
index 0000000..8303b83
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-netcan-plus-1xx.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+/dts-v1/;
+
+#include "am335x-baltos.dtsi"
+#include "am335x-baltos-leds.dtsi"
+
+/ {
+ model = "NetCAN";
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds_s0>;
+
+ compatible = "gpio-leds";
+
+ led@1 {
+ label = "can_data";
+ linux,default-trigger = "netdev";
+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ led@2 {
+ label = "can_error";
+ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+};
+
+&am33xx_pinmux {
+ user_leds_s0: user_leds_s0 {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Data LED */
+ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* CAN Error LED */
+ >;
+ };
+
+ dcan1_pins: pinmux_dcan1_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* CAN TX */
+ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* CAN RX */
+ >;
+ };
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+};
+
+&cpsw_emac0 {
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+ phy-handle = <&phy0>;
+};
+
+&cpsw_emac1 {
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
+};
+
+&dcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcan1_pins>;
+
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts
new file mode 100644
index 0000000..f8e0e95
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-netcom-plus-2xx.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+/dts-v1/;
+
+#include "am335x-baltos.dtsi"
+#include "am335x-baltos-leds.dtsi"
+
+/ {
+ model = "NetCom Plus";
+};
+
+&am33xx_pinmux {
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */
+ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */
+ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */
+ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */
+ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */
+ AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */
+ AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */
+ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */
+ >;
+ };
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */
+ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */
+ AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */
+ AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */
+ >;
+ };
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+};
+
+&cpsw_emac0 {
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+ phy-handle = <&phy0>;
+};
+
+&cpsw_emac1 {
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
+};
diff --git a/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts
new file mode 100644
index 0000000..a4e1375
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-netcom-plus-8xx.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/*
+ * VScom OnRISC
+ * http://www.vscom.de
+ */
+
+/dts-v1/;
+
+#include "am335x-baltos.dtsi"
+
+/ {
+ model = "NetCom Plus";
+};
+
+&am33xx_pinmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dip_switches>;
+
+ dip_switches: pinmux_dip_switches {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)
+ >;
+ };
+
+ tca6416_pins: pinmux_tca6416_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE3)
+ AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE3)
+ >;
+ };
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&i2c1 {
+ tca6416a: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <20 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tca6416_pins>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416b: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ tca6416c: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&davinci_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ };
+};
+
+&cpsw_emac0 {
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+ phy-handle = <&phy0>;
+};
+
+&cpsw_emac1 {
+ phy-mode = "rgmii-id";
+ dual_emac_res_vlan = <2>;
+ phy-handle = <&phy1>;
+};
diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
index f47cc9f..f841afb 100644
--- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
+++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
@@ -1,5 +1,5 @@
//SPDX-License-Identifier: GPL-2.0
-/* Copyright (C) 2018 Octavo Systems LLC - http://www.octavosystems.com/
+/* Copyright (C) 2018 Octavo Systems LLC - https://www.octavosystems.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -107,7 +107,7 @@
* below to "crossed" and uncomment the video-ports -property
* in tda19988 node.
* AM335x errata for wiring:
- * http://www.ti.com/lit/er/sprz360i/sprz360i.pdf
+ * https://www.ti.com/lit/er/sprz360i/sprz360i.pdf
*/
blue-and-red-wiring = "straight";
@@ -384,38 +384,16 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "peripheral";
interrupts-extended = <&intc 18 &tps 0>;
interrupt-names = "mc", "vbus";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
diff --git a/arch/arm/boot/dts/am335x-osd335x-common.dtsi b/arch/arm/boot/dts/am335x-osd335x-common.dtsi
index a8b6842..2888b15 100644
--- a/arch/arm/boot/dts/am335x-osd335x-common.dtsi
+++ b/arch/arm/boot/dts/am335x-osd335x-common.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* Author: Robert Nelson <robertcnelson@gmail.com>
*/
diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi
index 9bfa032..6c547c8 100644
--- a/arch/arm/boot/dts/am335x-pcm-953.dtsi
+++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi
@@ -237,31 +237,6 @@
};
/* USB */
-&cppi41dma {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
-
-&usb1_phy {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts
index 3141255..d41a5ff 100644
--- a/arch/arm/boot/dts/am335x-pdu001.dts
+++ b/arch/arm/boot/dts/am335x-pdu001.dts
@@ -5,7 +5,7 @@
*
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -384,34 +384,6 @@
};
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&cppi41dma {
- status = "okay";
-};
-
/*
* Disable soc's rtc as we have no VBAT for it. This makes the board
* rtc (Microchip MCP79400) the default rtc device 'rtc0'.
diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts
index e7764ec..f9a027b 100644
--- a/arch/arm/boot/dts/am335x-pepper.dts
+++ b/arch/arm/boot/dts/am335x-pepper.dts
@@ -341,7 +341,7 @@
pinctrl-0 = <&emmc_pins>;
vmmc-supply = <&ldo3_reg>;
bus-width = <8>;
- ti,non-removable;
+ non-removable;
};
&mmc3 {
@@ -351,7 +351,7 @@
pinctrl-0 = <&wireless_pins>;
vmmmc-supply = <&v3v3c_reg>;
bus-width = <4>;
- ti,non-removable;
+ non-removable;
dmas = <&edma_xbar 12 0 1
&edma_xbar 13 0 2>;
dma-names = "tx", "rx";
@@ -552,38 +552,18 @@
/* USB */
&usb {
- status = "okay";
-
pinctrl-names = "default";
pinctrl-0 = <&usb_pins>;
};
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "host";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&am33xx_pinmux {
usb_pins: pinmux_usb {
pinctrl-single,pins = <
diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi
index 3d0672b..7e46b4c 100644
--- a/arch/arm/boot/dts/am335x-phycore-som.dtsi
+++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi
@@ -69,7 +69,7 @@
pinctrl-0 = <&emmc_pins>;
vmmc-supply = <&vmmc_reg>;
bus-width = <8>;
- ti,non-removable;
+ non-removable;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts b/arch/arm/boot/dts/am335x-pocketbeagle.dts
index abf2bad..d526c59 100644
--- a/arch/arm/boot/dts/am335x-pocketbeagle.dts
+++ b/arch/arm/boot/dts/am335x-pocketbeagle.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* Author: Robert Nelson <robertcnelson@gmail.com>
*/
@@ -59,7 +59,276 @@
};
};
+&gpio0 {
+ gpio-line-names =
+ "[NC]",
+ "[NC]",
+ "P1.08 [SPI0_CLK]",
+ "P1.10 [SPI0_MISO]",
+ "P1.12 [SPI0_MOSI]",
+ "P1.06 [SPI0_CS]",
+ "[MMC0_CD]",
+ "P2.29 [SPI1_CLK]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "P1.26 [I2C2_SDA]",
+ "P1.28 [I2C2_SCL]",
+ "P2.11 [I2C1_SDA]",
+ "P2.09 [I2C1_SCL]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "P2.31 [SPI1_CS]",
+ "P1.20 [PRU0.16]",
+ "[NC]",
+ "[NC]",
+ "P2.03",
+ "[NC]",
+ "[NC]",
+ "P1.34",
+ "P2.19",
+ "[NC]",
+ "[NC]",
+ "P2.05 [UART4_RX]",
+ "P2.07 [UART4_TX]";
+};
+
+&gpio1 {
+ gpio-line-names =
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "P2.25 [SPI1_MOSI]",
+ "P1.32 [UART0_RX]",
+ "P1.30 [UART0_TX]",
+ "P2.24",
+ "P2.33",
+ "P2.22",
+ "P2.18",
+ "[NC]",
+ "[NC]",
+ "P2.01 [PWM1A]",
+ "[NC]",
+ "P2.10",
+ "[USR LED 0]",
+ "[USR LED 1]",
+ "[USR LED 2]",
+ "[USR LED 3]",
+ "P2.06",
+ "P2.04",
+ "P2.02",
+ "P2.08",
+ "[NC]",
+ "[NC]",
+ "[NC]";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "P2.20",
+ "P2.17",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[EEPROM_WP]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[SYSBOOT]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "P2.35 [AIN5]",
+ "P1.02 [AIN6]",
+ "P1.35 [PRU1.10]",
+ "P1.04 [PRU1.11]",
+ "[MMC0_DAT3]",
+ "[MMC0_DAT2]",
+ "[MMC0_DAT1]",
+ "[MMC0_DAT0]",
+ "[MMC0_CLK]",
+ "[MMC0_CMD]";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[I2C0_SDA]",
+ "[I2C0_SCL]",
+ "[JTAG]",
+ "[JTAG]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "P1.03 [USB1]",
+ "P1.36 [PWM0A]",
+ "P1.33 [PRU0.1]",
+ "P2.32 [PRU0.2]",
+ "P2.30 [PRU0.3]",
+ "P1.31 [PRU0.4]",
+ "P2.34 [PRU0.5]",
+ "P2.28 [PRU0.6]",
+ "P1.29 [PRU0.7]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]",
+ "[NC]";
+};
+
&am33xx_pinmux {
+
+ pinctrl-names = "default";
+
+ pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio
+ &P2_33_gpio &P2_22_gpio &P2_18_gpio &P2_10_gpio
+ &P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio
+ &P2_17_gpio >;
+
+ /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */
+ P2_03_gpio: pinmux_P2_03_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */
+ P1_34_gpio: pinmux_P1_34_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */
+ P2_19_gpio: pinmux_P2_19_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P2_24 (ZCZ ball T12) gpio1_12 0x830 PIN 12 */
+ P2_24_gpio: pinmux_P2_24_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P2_33 (ZCZ ball R12) gpio1_13 0x834 PIN 13 */
+ P2_33_gpio: pinmux_P2_33_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P2_22 (ZCZ ball V13) gpio1_14 0x838 PIN 14 */
+ P2_22_gpio: pinmux_P2_22_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */
+ P2_18_gpio: pinmux_P2_18_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P2_10 (ZCZ ball R14) gpio1_20 0x850 PIN 20 */
+ P2_10_gpio: pinmux_P2_10_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P2_06 (ZCZ ball U16) gpio1_25 0x864 PIN 25 */
+ P2_06_gpio: pinmux_P2_06_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P2_04 (ZCZ ball T16) gpio1_26 0x868 PIN 26 */
+ P2_04_gpio: pinmux_P2_04_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P2_02 (ZCZ ball V17) gpio1_27 0x86c PIN 27 */
+ P2_02_gpio: pinmux_P2_02_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
+ /* P2_08 (ZCZ ball U18) gpio1_28 0x878 PIN 30 */
+ P2_08_gpio: pinmux_P2_08_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x00 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x00 0x00 0x10 0x18>;
+ };
+
+ /* P2_17 (ZCZ ball V12) gpio2_1 0x88c PIN 35 */
+ P2_17_gpio: pinmux_P2_17_gpio {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7)
+ >;
+ pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
+ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
+ };
+
i2c2_pins: pinmux-i2c2-pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */
@@ -205,32 +474,10 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "otg";
};
-&usb1_phy {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
-
-&cppi41dma {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/am335x-regor.dtsi b/arch/arm/boot/dts/am335x-regor.dtsi
index 5aff02a..6fbf4ac 100644
--- a/arch/arm/boot/dts/am335x-regor.dtsi
+++ b/arch/arm/boot/dts/am335x-regor.dtsi
@@ -200,24 +200,3 @@
status = "okay";
linux,rs485-enabled-at-boot-time;
};
-
-/* USB */
-&cppi41dma {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
index e5fdb7a..275ba33 100644
--- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts
+++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/am335x-sbc-t335.dts b/arch/arm/boot/dts/am335x-sbc-t335.dts
index a3f6bc4..81e4453 100644
--- a/arch/arm/boot/dts/am335x-sbc-t335.dts
+++ b/arch/arm/boot/dts/am335x-sbc-t335.dts
@@ -155,13 +155,13 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x26>;
- dvi_ena {
+ dvi-ena-hog {
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "dvi-enable";
};
- lcd_ena {
+ lcd-ena-hog {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts
index 5b03685..1eaa265 100644
--- a/arch/arm/boot/dts/am335x-shc.dts
+++ b/arch/arm/boot/dts/am335x-shc.dts
@@ -117,10 +117,6 @@
status = "okay";
};
-&cppi41dma {
- status = "okay";
-};
-
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
@@ -358,20 +354,7 @@
status = "okay";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb1 {
- status = "okay";
dr_mode = "host";
};
diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts
index 2f82095..f4684c8 100644
--- a/arch/arm/boot/dts/am335x-sl50.dts
+++ b/arch/arm/boot/dts/am335x-sl50.dts
@@ -512,36 +512,14 @@
status = "disabled";
};
-&usb {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
&usb0 {
- status = "okay";
dr_mode = "otg";
};
&usb1 {
- status = "okay";
dr_mode = "host";
};
-&cppi41dma {
- status = "okay";
-};
-
&mmc1 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi
index 61fc4cd..1359bf8 100644
--- a/arch/arm/boot/dts/am335x-wega.dtsi
+++ b/arch/arm/boot/dts/am335x-wega.dtsi
@@ -191,32 +191,6 @@
status = "okay";
};
-/* USB */
-&cppi41dma {
- status = "okay";
-};
-
-&usb_ctrl_mod {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
&usb1 {
dr_mode = "host";
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
};
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
index 7a9eb2b..29fafb6 100644
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -129,7 +129,6 @@
gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio1";
reg = <0x7000 0x4>,
<0x7010 0x4>,
<0x7114 0x4>;
@@ -152,6 +151,18 @@
gpio0: gpio@0 {
compatible = "ti,omap4-gpio";
+ gpio-ranges = <&am33xx_pinmux 0 82 8>,
+ <&am33xx_pinmux 8 52 4>,
+ <&am33xx_pinmux 12 94 4>,
+ <&am33xx_pinmux 16 71 2>,
+ <&am33xx_pinmux 18 135 1>,
+ <&am33xx_pinmux 19 108 2>,
+ <&am33xx_pinmux 21 73 1>,
+ <&am33xx_pinmux 22 8 2>,
+ <&am33xx_pinmux 26 10 2>,
+ <&am33xx_pinmux 28 74 1>,
+ <&am33xx_pinmux 29 81 1>,
+ <&am33xx_pinmux 30 28 2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -163,7 +174,6 @@
target-module@9000 { /* 0x44e09000, ap 16 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart1";
reg = <0x9050 0x4>,
<0x9054 0x4>,
<0x9058 0x4>;
@@ -195,7 +205,6 @@
target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c1";
reg = <0xb000 0x8>,
<0xb010 0x8>,
<0xb090 0x8>;
@@ -228,7 +237,6 @@
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
@@ -282,7 +290,7 @@
am33xx_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x238>;
- #pinctrl-cells = <1>;
+ #pinctrl-cells = <2>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
@@ -306,6 +314,13 @@
};
};
+ usb_ctrl_mod: control@620 {
+ compatible = "ti,am335x-usb-ctrl-module";
+ reg = <0x620 0x10>,
+ <0x648 0x4>;
+ reg-names = "phy_ctrl", "wakeup";
+ };
+
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
@@ -327,9 +342,8 @@
};
};
- target-module@31000 { /* 0x44e31000, ap 25 40.0 */
+ timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
- ti,hwmods = "timer1";
reg = <0x31000 0x4>,
<0x31010 0x4>,
<0x31014 0x4>;
@@ -368,7 +382,6 @@
target-module@35000 { /* 0x44e35000, ap 29 50.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "wd_timer2";
reg = <0x35000 0x4>,
<0x35010 0x4>,
<0x35014 0x4>;
@@ -412,7 +425,6 @@
target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "rtc";
reg = <0x3e074 0x4>,
<0x3e078 0x4>;
reg-names = "rev", "sysc";
@@ -757,12 +769,27 @@
ranges = <0x0 0x200000 0x80000>;
};
- target-module@300000 { /* 0x4a300000, ap 9 04.0 */
- compatible = "ti,sysc";
- status = "disabled";
+ pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
+ compatible = "ti,sysc-pruss", "ti,sysc";
+ reg = <0x326000 0x4>,
+ <0x326004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
+ SYSC_PRUSS_SUB_MWAIT)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_per 1>;
+ reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x300000 0x80000>;
+ status = "disabled";
};
};
};
@@ -912,7 +939,6 @@
target-module@22000 { /* 0x48022000, ap 10 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart2";
reg = <0x22050 0x4>,
<0x22054 0x4>,
<0x22058 0x4>;
@@ -944,7 +970,6 @@
target-module@24000 { /* 0x48024000, ap 12 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart3";
reg = <0x24050 0x4>,
<0x24054 0x4>,
<0x24058 0x4>;
@@ -976,7 +1001,6 @@
target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c2";
reg = <0x2a000 0x8>,
<0x2a010 0x8>,
<0x2a090 0x8>;
@@ -1009,7 +1033,6 @@
target-module@30000 { /* 0x48030000, ap 77 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
@@ -1046,7 +1069,6 @@
target-module@38000 { /* 0x48038000, ap 16 02.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "mcasp0";
reg = <0x38000 0x4>,
<0x38004 0x4>;
reg-names = "rev", "sysc";
@@ -1077,7 +1099,6 @@
target-module@3c000 { /* 0x4803c000, ap 20 32.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "mcasp1";
reg = <0x3c000 0x4>,
<0x3c004 0x4>;
reg-names = "rev", "sysc";
@@ -1106,9 +1127,8 @@
};
};
- target-module@40000 { /* 0x48040000, ap 22 1e.0 */
+ timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer2";
reg = <0x40000 0x4>,
<0x40010 0x4>,
<0x40014 0x4>;
@@ -1136,7 +1156,6 @@
target-module@42000 { /* 0x48042000, ap 24 1c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
@@ -1162,7 +1181,6 @@
target-module@44000 { /* 0x48044000, ap 26 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
@@ -1189,7 +1207,6 @@
target-module@46000 { /* 0x48046000, ap 28 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
@@ -1216,7 +1233,6 @@
target-module@48000 { /* 0x48048000, ap 30 22.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
@@ -1243,7 +1259,6 @@
target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
@@ -1270,7 +1285,6 @@
target-module@4c000 { /* 0x4804c000, ap 32 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio2";
reg = <0x4c000 0x4>,
<0x4c010 0x4>,
<0x4c114 0x4>;
@@ -1293,6 +1307,10 @@
gpio1: gpio@0 {
compatible = "ti,omap4-gpio";
+ gpio-ranges = <&am33xx_pinmux 0 0 8>,
+ <&am33xx_pinmux 8 90 4>,
+ <&am33xx_pinmux 12 12 16>,
+ <&am33xx_pinmux 28 30 4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1312,7 +1330,6 @@
target-module@60000 { /* 0x48060000, ap 36 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc1";
reg = <0x602fc 0x4>,
<0x60110 0x4>,
<0x60114 0x4>;
@@ -1333,10 +1350,8 @@
ranges = <0x0 0x60000 0x1000>;
mmc1: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- ti,dual-volt;
+ compatible = "ti,am335-sdhci";
ti,needs-special-reset;
- ti,needs-special-hs-handling;
dmas = <&edma_xbar 24 0 0
&edma_xbar 25 0 0>;
dma-names = "tx", "rx";
@@ -1348,7 +1363,6 @@
target-module@80000 { /* 0x48080000, ap 38 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@@ -1385,7 +1399,6 @@
target-module@c8000 { /* 0x480c8000, ap 87 06.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox";
reg = <0xc8000 0x4>,
<0xc8010 0x4>;
reg-names = "rev", "sysc";
@@ -1417,7 +1430,6 @@
target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
@@ -1506,7 +1518,6 @@
target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c3";
reg = <0x9c000 0x8>,
<0x9c010 0x8>,
<0x9c090 0x8>;
@@ -1539,7 +1550,6 @@
target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
@@ -1592,7 +1602,6 @@
target-module@a6000 { /* 0x481a6000, ap 48 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart4";
reg = <0xa6050 0x4>,
<0xa6054 0x4>,
<0xa6058 0x4>;
@@ -1622,7 +1631,6 @@
target-module@a8000 { /* 0x481a8000, ap 50 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart5";
reg = <0xa8050 0x4>,
<0xa8054 0x4>,
<0xa8058 0x4>;
@@ -1652,7 +1660,6 @@
target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart6";
reg = <0xaa050 0x4>,
<0xaa054 0x4>,
<0xaa058 0x4>;
@@ -1682,7 +1689,6 @@
target-module@ac000 { /* 0x481ac000, ap 54 38.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio3";
reg = <0xac000 0x4>,
<0xac010 0x4>,
<0xac114 0x4>;
@@ -1705,6 +1711,9 @@
gpio2: gpio@0 {
compatible = "ti,omap4-gpio";
+ gpio-ranges = <&am33xx_pinmux 0 34 18>,
+ <&am33xx_pinmux 18 77 4>,
+ <&am33xx_pinmux 22 56 10>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1714,9 +1723,8 @@
};
};
- target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
+ gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio4";
reg = <0xae000 0x4>,
<0xae010 0x4>,
<0xae114 0x4>;
@@ -1739,6 +1747,11 @@
gpio3: gpio@0 {
compatible = "ti,omap4-gpio";
+ gpio-ranges = <&am33xx_pinmux 0 66 5>,
+ <&am33xx_pinmux 5 98 2>,
+ <&am33xx_pinmux 7 75 2>,
+ <&am33xx_pinmux 13 141 1>,
+ <&am33xx_pinmux 14 100 8>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -1760,7 +1773,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
- ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
<&dcan0_fck>;
@@ -1784,7 +1796,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
- ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
<&dcan1_fck>;
@@ -1806,7 +1817,6 @@
target-module@d8000 { /* 0x481d8000, ap 64 66.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc2";
reg = <0xd82fc 0x4>,
<0xd8110 0x4>,
<0xd8114 0x4>;
@@ -1827,7 +1837,7 @@
ranges = <0x0 0xd8000 0x1000>;
mmc2: mmc@0 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,am335-sdhci";
ti,needs-special-reset;
dmas = <&edma 2 0
&edma 3 0>;
@@ -1875,7 +1885,6 @@
target-module@0 { /* 0x48300000, ap 66 48.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
@@ -1928,7 +1937,6 @@
target-module@2000 { /* 0x48302000, ap 68 52.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
@@ -1981,7 +1989,6 @@
target-module@4000 { /* 0x48304000, ap 70 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@@ -2034,7 +2041,6 @@
target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "lcdc";
reg = <0xe000 0x4>,
<0xe054 0x4>;
reg-names = "rev", "sysc";
@@ -2061,7 +2067,6 @@
target-module@10000 { /* 0x48310000, ap 76 4e.1 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "rng";
reg = <0x11fe0 0x4>,
<0x11fe4 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 77fa7c0..f09a61c 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for AM33XX SoC
*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -50,6 +50,7 @@
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a8";
+ enable-method = "ti,am3352";
device_type = "cpu";
reg = <0>;
@@ -59,6 +60,17 @@
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
+ cpu-idle-states = <&mpu_gate>;
+ };
+
+ idle-states {
+ mpu_gate: mpu_gate {
+ compatible = "arm,idle-state";
+ entry-latency-us = <40>;
+ exit-latency-us = <90>;
+ min-residency-us = <300>;
+ ti,idle-wkup-m3;
+ };
};
};
@@ -163,7 +175,7 @@
* for the moment, just use a fake OCP bus entry to represent
* the whole bus hierarchy.
*/
- ocp {
+ ocp: ocp {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -196,50 +208,104 @@
reg = <0x48200000 0x1000>;
};
- edma: edma@49000000 {
- compatible = "ti,edma3-tpcc";
- ti,hwmods = "tpcc";
- reg = <0x49000000 0x10000>;
- reg-names = "edma3_cc";
- interrupts = <12 13 14>;
- interrupt-names = "edma3_ccint", "edma3_mperr",
- "edma3_ccerrint";
- dma-requests = <64>;
- #dma-cells = <2>;
+ target-module@49000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49000000 0x4>;
+ reg-names = "rev";
+ clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49000000 0x10000>;
- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
- <&edma_tptc2 0>;
+ edma: dma@0 {
+ compatible = "ti,edma3-tpcc";
+ reg = <0 0x10000>;
+ reg-names = "edma3_cc";
+ interrupts = <12 13 14>;
+ interrupt-names = "edma3_ccint", "edma3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
- ti,edma-memcpy-channels = <20 21>;
+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
+ <&edma_tptc2 0>;
+
+ ti,edma-memcpy-channels = <20 21>;
+ };
};
- edma_tptc0: tptc@49800000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc0";
- reg = <0x49800000 0x100000>;
- interrupts = <112>;
- interrupt-names = "edma3_tcerrint";
+ target-module@49800000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49800000 0x4>,
+ <0x49800010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49800000 0x100000>;
+
+ edma_tptc0: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <112>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
- edma_tptc1: tptc@49900000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc1";
- reg = <0x49900000 0x100000>;
- interrupts = <113>;
- interrupt-names = "edma3_tcerrint";
+ target-module@49900000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49900000 0x4>,
+ <0x49900010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49900000 0x100000>;
+
+ edma_tptc1: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <113>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
- edma_tptc2: tptc@49a00000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc2";
- reg = <0x49a00000 0x100000>;
- interrupts = <114>;
- interrupt-names = "edma3_tcerrint";
+ target-module@49a00000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49a00000 0x4>,
+ <0x49a00010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49a00000 0x100000>;
+
+ edma_tptc2: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <114>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
target-module@47810000 {
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc3";
reg = <0x478102fc 0x4>,
<0x47810110 0x4>,
<0x47810114 0x4>;
@@ -259,44 +325,46 @@
ranges = <0x0 0x47810000 0x1000>;
mmc3: mmc@0 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,am335-sdhci";
ti,needs-special-reset;
interrupts = <29>;
reg = <0x0 0x1000>;
+ status = "disabled";
};
};
- usb: usb@47400000 {
- compatible = "ti,am33xx-usb";
- reg = <0x47400000 0x1000>;
- ranges;
+ usb: target-module@47400000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x47400000 0x4>,
+ <0x47400010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
- ti,hwmods = "usb_otg_hs";
- status = "disabled";
+ ranges = <0x0 0x47400000 0x8000>;
- usb_ctrl_mod: control@44e10620 {
- compatible = "ti,am335x-usb-ctrl-module";
- reg = <0x44e10620 0x10
- 0x44e10648 0x4>;
- reg-names = "phy_ctrl", "wakeup";
- status = "disabled";
- };
-
- usb0_phy: usb-phy@47401300 {
+ usb0_phy: usb-phy@1300 {
compatible = "ti,am335x-usb-phy";
- reg = <0x47401300 0x100>;
+ reg = <0x1300 0x100>;
reg-names = "phy";
- status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
- usb0: usb@47401000 {
+ usb0: usb@1400 {
compatible = "ti,musb-am33xx";
- status = "disabled";
- reg = <0x47401400 0x400
- 0x47401000 0x200>;
+ reg = <0x1400 0x400>,
+ <0x1000 0x200>;
reg-names = "mc", "control";
interrupts = <18>;
@@ -332,20 +400,18 @@
"tx14", "tx15";
};
- usb1_phy: usb-phy@47401b00 {
+ usb1_phy: usb-phy@1b00 {
compatible = "ti,am335x-usb-phy";
- reg = <0x47401b00 0x100>;
+ reg = <0x1b00 0x100>;
reg-names = "phy";
- status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
- usb1: usb@47401800 {
+ usb1: usb@1800 {
compatible = "ti,musb-am33xx";
- status = "disabled";
- reg = <0x47401c00 0x400
- 0x47401800 0x200>;
+ reg = <0x1c00 0x400>,
+ <0x1800 0x200>;
reg-names = "mc", "control";
interrupts = <19>;
interrupt-names = "mc";
@@ -380,36 +446,35 @@
"tx14", "tx15";
};
- cppi41dma: dma-controller@47402000 {
+ cppi41dma: dma-controller@2000 {
compatible = "ti,am3359-cppi41";
- reg = <0x47400000 0x1000
- 0x47402000 0x1000
- 0x47403000 0x1000
- 0x47404000 0x4000>;
+ reg = <0x0000 0x1000>,
+ <0x2000 0x1000>,
+ <0x3000 0x1000>,
+ <0x4000 0x4000>;
reg-names = "glue", "controller", "scheduler", "queuemgr";
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
#dma-channels = <30>;
#dma-requests = <256>;
- status = "disabled";
};
};
- ocmcram: ocmcram@40300000 {
+ ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x10000>; /* 64k */
ranges = <0x0 0x40300000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
- pm_sram_code: pm-sram-code@0 {
+ pm_sram_code: pm-code-sram@0 {
compatible = "ti,sram";
reg = <0x0 0x1000>;
protect-exec;
};
- pm_sram_data: pm-sram-data@1000 {
+ pm_sram_data: pm-data-sram@1000 {
compatible = "ti,sram";
reg = <0x1000 0x1000>;
pool;
@@ -445,26 +510,138 @@
status = "disabled";
};
- sham: sham@53100000 {
- compatible = "ti,omap4-sham";
- ti,hwmods = "sham";
- reg = <0x53100000 0x200>;
- interrupts = <109>;
- dmas = <&edma 36 0>;
- dma-names = "rx";
+ sham_target: target-module@53100000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x53100100 0x4>,
+ <0x53100110 0x4>,
+ <0x53100114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53100000 0x1000>;
+
+ sham: sham@0 {
+ compatible = "ti,omap4-sham";
+ reg = <0 0x200>;
+ interrupts = <109>;
+ dmas = <&edma 36 0>;
+ dma-names = "rx";
+ };
};
- aes: aes@53500000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes";
- reg = <0x53500000 0xa0>;
- interrupts = <103>;
- dmas = <&edma 6 0>,
- <&edma 5 0>;
- dma-names = "tx", "rx";
+ aes_target: target-module@53500000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x53500080 0x4>,
+ <0x53500084 0x4>,
+ <0x53500088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53500000 0x1000>;
+
+ aes: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <103>;
+ dmas = <&edma 6 0>,
+ <&edma 5 0>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module@56000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5600fe00 0x4>,
+ <0x5600fe10 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
+ clock-names = "fck";
+ power-domains = <&prm_gfx>;
+ resets = <&prm_gfx 0>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x56000000 0x1000000>;
+
+ /*
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
};
};
};
#include "am33xx-l4.dtsi"
#include "am33xx-clocks.dtsi"
+
+&prcm {
+ prm_per: prm@c00 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0xc00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_wkup: prm@d00 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0xd00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm@f00 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0xf00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_gfx: prm@1100 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1100 0x100>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+};
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer1_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer2_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/am3517-craneboard.dts
index eb3517d..3642cfc 100644
--- a/arch/arm/boot/dts/am3517-craneboard.dts
+++ b/arch/arm/boot/dts/am3517-craneboard.dts
@@ -2,7 +2,7 @@
/*
* See craneboard.org for more details
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/am3517-evm-ui.dtsi
index 48631a4..7d8f32b 100644
--- a/arch/arm/boot/dts/am3517-evm-ui.dtsi
+++ b/arch/arm/boot/dts/am3517-evm-ui.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/
+ * Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/
*/
#include <dt-bindings/input/input.h>
@@ -183,14 +183,14 @@
};
&mcbsp1 {
- status = "ok";
+ status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
};
&mcbsp2 {
- status = "ok";
+ status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index a1fd3e6..0d2fac9 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -156,6 +156,7 @@
pinctrl-0 = <&pwm_pins>;
ti,timers = <&timer11>;
#pwm-cells = <3>;
+ ti,clock-source = <0x01>;
};
/* HS USB Host PHY on PORT 1 */
@@ -175,7 +176,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index bf30020..de33c4f 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for am3517 SoC
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -10,12 +10,47 @@
#include "omap3.dtsi"
+/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */
+/delete-node/ &aes1_target;
+/delete-node/ &aes2_target;
+
/ {
aliases {
serial3 = &uart4;
can = &hecc;
};
+ cpus {
+ cpu: cpu@0 {
+ /* Based on OMAP3630 variants OPP50 and OPP100 */
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ clock-latency = <300000>; /* From legacy driver */
+ };
+ };
+
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_conf>;
+ /*
+ * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx
+ * appear to operate at 300MHz as well. Since AM3517 only
+ * lists one operating voltage, it will remain fixed at 1.2V
+ */
+ opp50-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0xffffffff 0xffffffff>;
+ opp-suspend;
+ };
+
+ opp100-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1200000>;
+ opp-supported-hw = <0xffffffff 0xffffffff>;
+ };
+ };
+
ocp@68000000 {
am35x_otg_hs: am35x_otg_hs@5c040000 {
compatible = "ti,omap3-musb";
@@ -43,7 +78,7 @@
clock-names = "ick";
};
- davinci_mdio: ethernet@5c030000 {
+ davinci_mdio: mdio@5c030000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
status = "disabled";
@@ -115,6 +150,12 @@
};
};
+/* Not currently working, probably needs at least different clocks */
+&rng_target {
+ status = "disabled";
+ /delete-property/ clocks;
+};
+
/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
&usb_otg_hs {
status = "disabled";
@@ -132,5 +173,25 @@
status = "disabled";
};
-/include/ "am35xx-clocks.dtsi"
-/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+#include "am35xx-clocks.dtsi"
+#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt1_fck>;
+ assigned-clock-parents = <&sys_ck>;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt2_fck>;
+ assigned-clock-parents = <&sys_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index e507e4a..e7d7124 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -8,7 +8,7 @@
/ {
model = "TeeJet Mt.Ventoux";
- compatible = "teejet,mt_ventoux", "ti,omap3";
+ compatible = "teejet,mt_ventoux", "ti,am3517", "ti,omap3";
memory@80000000 {
device_type = "memory";
diff --git a/arch/arm/boot/dts/am3703.dtsi b/arch/arm/boot/dts/am3703.dtsi
new file mode 100644
index 0000000..2b994ae
--- /dev/null
+++ b/arch/arm/boot/dts/am3703.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
+ */
+
+#include "omap36xx.dtsi"
+
+&iva {
+ status = "disabled";
+};
+
+&sgx_module {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/am3715.dtsi b/arch/arm/boot/dts/am3715.dtsi
new file mode 100644
index 0000000..ab328e8
--- /dev/null
+++ b/arch/arm/boot/dts/am3715.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
+ */
+
+#include "omap36xx.dtsi"
+
+&iva {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts
index 1b4b2b0..9423e9f 100644
--- a/arch/arm/boot/dts/am3874-iceboard.dts
+++ b/arch/arm/boot/dts/am3874-iceboard.dts
@@ -2,8 +2,8 @@
/*
* Device tree for Winterland IceBoard
*
- * http://mcgillcosmology.com
- * http://threespeedlogic.com
+ * https://mcgillcosmology.com
+ * https://threespeedlogic.com
*
* This is an ARM + FPGA instrumentation board used at telescopes in
* Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO
@@ -195,7 +195,7 @@
"FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS",
"FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C",
"FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL";
- reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
u42: pca9575@21 {
@@ -208,7 +208,7 @@
"QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL",
"SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1",
"QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR";
- reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
u48: pca9575@22 {
@@ -227,7 +227,7 @@
"GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8",
"GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5",
"GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1";
- reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
u59: pca9575@23 {
@@ -240,7 +240,7 @@
"GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault",
"BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3",
"BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17";
- reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; };
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 14bbc43..878406b 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for AM4372 SoC
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -35,8 +35,8 @@
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
- ethernet0 = &cpsw_emac0;
- ethernet1 = &cpsw_emac1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
spi0 = &qspi;
};
@@ -45,6 +45,7 @@
#size-cells = <0>;
cpu: cpu@0 {
compatible = "arm,cortex-a9";
+ enable-method = "ti,am4372";
device_type = "cpu";
reg = <0>;
@@ -54,6 +55,17 @@
operating-points-v2 = <&cpu0_opp_table>;
clock-latency = <300000>; /* From omap-cpufreq driver */
+ cpu-idle-states = <&mpu_gate>;
+ };
+
+ idle-states {
+ mpu_gate: mpu_gate {
+ compatible = "arm,idle-state";
+ entry-latency-us = <40>;
+ exit-latency-us = <100>;
+ min-residency-us = <300>;
+ local-timer-stop;
+ };
};
};
@@ -141,7 +153,7 @@
clocks = <&mpu_periphclk>;
};
- l2-cache-controller@48242000 {
+ cache-controller@48242000 {
compatible = "arm,pl310-cache";
reg = <0x48242000 0x1000>;
cache-unified;
@@ -185,52 +197,106 @@
&pm_sram_data>;
};
- edma: edma@49000000 {
- compatible = "ti,edma3-tpcc";
- ti,hwmods = "tpcc";
- reg = <0x49000000 0x10000>;
- reg-names = "edma3_cc";
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma3_ccint", "edma3_mperr",
- "edma3_ccerrint";
- dma-requests = <64>;
- #dma-cells = <2>;
+ target-module@49000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49000000 0x4>;
+ reg-names = "rev";
+ clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49000000 0x10000>;
- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
- <&edma_tptc2 0>;
+ edma: dma@0 {
+ compatible = "ti,edma3-tpcc";
+ reg = <0 0x10000>;
+ reg-names = "edma3_cc";
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_ccint", "edma3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
- ti,edma-memcpy-channels = <58 59>;
+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
+ <&edma_tptc2 0>;
+
+ ti,edma-memcpy-channels = <58 59>;
+ };
};
- edma_tptc0: tptc@49800000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc0";
- reg = <0x49800000 0x100000>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma3_tcerrint";
+ target-module@49800000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49800000 0x4>,
+ <0x49800010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49800000 0x100000>;
+
+ edma_tptc0: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
- edma_tptc1: tptc@49900000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc1";
- reg = <0x49900000 0x100000>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma3_tcerrint";
+ target-module@49900000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49900000 0x4>,
+ <0x49900010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49900000 0x100000>;
+
+ edma_tptc1: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
- edma_tptc2: tptc@49a00000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc2";
- reg = <0x49a00000 0x100000>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma3_tcerrint";
+ target-module@49a00000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49a00000 0x4>,
+ <0x49a00010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49a00000 0x100000>;
+
+ edma_tptc2: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
target-module@47810000 {
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc3";
reg = <0x478102fc 0x4>,
<0x47810110 0x4>,
<0x47810114 0x4>;
@@ -250,40 +316,122 @@
ranges = <0x0 0x47810000 0x1000>;
mmc3: mmc@0 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,am437-sdhci";
ti,needs-special-reset;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x1000>;
+ status = "disabled";
};
};
- sham: sham@53100000 {
- compatible = "ti,omap5-sham";
- ti,hwmods = "sham";
- reg = <0x53100000 0x300>;
- dmas = <&edma 36 0>;
- dma-names = "rx";
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ sham_target: target-module@53100000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x53100100 0x4>,
+ <0x53100110 0x4>,
+ <0x53100114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53100000 0x1000>;
+
+ sham: sham@0 {
+ compatible = "ti,omap5-sham";
+ reg = <0 0x300>;
+ dmas = <&edma 36 0>;
+ dma-names = "rx";
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
- aes: aes@53501000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes";
- reg = <0x53501000 0xa0>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&edma 6 0>,
- <&edma 5 0>;
- dma-names = "tx", "rx";
+ aes_target: target-module@53501000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x53501080 0x4>,
+ <0x53501084 0x4>,
+ <0x53501088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53501000 0x1000>;
+
+ aes: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma 6 0>,
+ <&edma 5 0>;
+ dma-names = "tx", "rx";
+ };
};
- des: des@53701000 {
- compatible = "ti,omap4-des";
- ti,hwmods = "des";
- reg = <0x53701000 0xa0>;
- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&edma 34 0>,
- <&edma 33 0>;
- dma-names = "tx", "rx";
+ des_target: target-module@53701000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x53701030 0x4>,
+ <0x53701034 0x4>,
+ <0x53701038 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x53701000 0x1000>;
+
+ des: des@0 {
+ compatible = "ti,omap4-des";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma 34 0>,
+ <&edma 33 0>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ pruss_tm: target-module@54400000 {
+ compatible = "ti,sysc-pruss", "ti,sysc";
+ reg = <0x54426000 0x4>,
+ <0x54426004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
+ SYSC_PRUSS_SUB_MWAIT)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_per 1>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x54400000 0x80000>;
};
gpmc: gpmc@50000000 {
@@ -306,72 +454,125 @@
status = "disabled";
};
- qspi: spi@47900000 {
- compatible = "ti,am4372-qspi";
- reg = <0x47900000 0x100>,
- <0x30000000 0x4000000>;
- reg-names = "qspi_base", "qspi_mmap";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "qspi";
- interrupts = <0 138 0x4>;
- num-cs = <4>;
- status = "disabled";
- };
-
- dss: dss@4832a000 {
- compatible = "ti,omap3-dss";
- reg = <0x4832a000 0x200>;
- status = "disabled";
- ti,hwmods = "dss_core";
- clocks = <&disp_clk>;
+ target-module@47900000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x47900000 0x4>,
+ <0x47900010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0x0 0x47900000 0x1000>,
+ <0x30000000 0x30000000 0x4000000>;
- dispc: dispc@4832a400 {
- compatible = "ti,omap3-dispc";
- reg = <0x4832a400 0x400>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "dss_dispc";
- clocks = <&disp_clk>;
+ qspi: spi@0 {
+ compatible = "ti,am4372-qspi";
+ reg = <0 0x100>,
+ <0x30000000 0x4000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ clocks = <&dpll_per_m2_div4_ck>;
clock-names = "fck";
-
- max-memory-bandwidth = <230000000>;
- };
-
- rfbi: rfbi@4832a800 {
- compatible = "ti,omap3-rfbi";
- reg = <0x4832a800 0x100>;
- ti,hwmods = "dss_rfbi";
- clocks = <&disp_clk>;
- clock-names = "fck";
- status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 138 0x4>;
+ num-cs = <4>;
};
};
- ocmcram: ocmcram@40300000 {
+ ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x40000>; /* 256k */
ranges = <0x0 0x40300000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
- pm_sram_code: pm-sram-code@0 {
+ pm_sram_code: pm-code-sram@0 {
compatible = "ti,sram";
reg = <0x0 0x1000>;
protect-exec;
};
- pm_sram_data: pm-sram-data@1000 {
+ pm_sram_data: pm-data-sram@1000 {
compatible = "ti,sram";
reg = <0x1000 0x1000>;
pool;
};
};
+
+ target-module@56000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5600fe00 0x4>,
+ <0x5600fe10 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
+ clock-names = "fck";
+ power-domains = <&prm_gfx>;
+ resets = <&prm_gfx 0>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x56000000 0x1000000>;
+ };
};
};
#include "am437x-l4.dtsi"
#include "am43xx-clocks.dtsi"
+
+&prcm {
+ prm_gfx: prm@400 {
+ compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x400 0x100>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ prm_per: prm@800 {
+ compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x800 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_wkup: prm@2000 {
+ compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x2000 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm@4000 {
+ compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x4000 0x100>;
+ #reset-cells = <1>;
+ };
+};
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer1_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer2_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts
index 063113a..a83f46e 100644
--- a/arch/arm/boot/dts/am437x-cm-t43.dts
+++ b/arch/arm/boot/dts/am437x-cm-t43.dts
@@ -291,7 +291,7 @@
pinctrl-0 = <&emmc_pins>;
vmmc-supply = <&vmmc_3v3>;
bus-width = <8>;
- ti,non-removable;
+ non-removable;
};
&spi0 {
@@ -325,17 +325,15 @@
};
};
-&mac {
+&mac_sw {
pinctrl-names = "default";
pinctrl-0 = <&cpsw_default>;
- dual_emac = <1>;
status = "okay";
};
-&davinci_mdio {
+&davinci_mdio_sw {
pinctrl-names = "default";
pinctrl-0 = <&davinci_mdio_default>;
- status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
@@ -346,16 +344,16 @@
};
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <ðphy0>;
phy-mode = "rgmii-txid";
- dual_emac_res_vlan = <1>;
+ ti,dual-emac-pvid = <1>;
};
-&cpsw_emac1 {
+&cpsw_port2 {
phy-handle = <ðphy1>;
phy-mode = "rgmii-txid";
- dual_emac_res_vlan = <2>;
+ ti,dual-emac-pvid = <2>;
};
&dwc3_1 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 126965a..033b984 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/* AM437x GP EVM */
@@ -91,22 +91,6 @@
backlight = <&lcd_bl>;
- panel-timing {
- clock-frequency = <33000000>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch = <210>;
- hback-porch = <16>;
- hsync-len = <30>;
- vback-porch = <10>;
- vfront-porch = <22>;
- vsync-len = <13>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
-
port {
lcd_in: endpoint {
remote-endpoint = <&dpi_out>;
@@ -872,7 +856,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_sleep>;
- ti,non-removable;
+ non-removable;
};
&mmc3 {
@@ -889,7 +873,7 @@
pinctrl-1 = <&mmc3_pins_sleep>;
cap-power-off-card;
keep-power-in-suspend;
- ti,non-removable;
+ non-removable;
#address-cells = <1>;
#size-cells = <0>;
@@ -925,28 +909,31 @@
status = "okay";
};
-&mac {
- slaves = <1>;
+&mac_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
-&davinci_mdio {
+&davinci_mdio_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <ðphy0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-rxid";
+ ti,dual-emac-pvid = <1>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
};
&elm {
@@ -1043,7 +1030,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_pins>;
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index 9f66f96..2dc5255 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -483,28 +483,31 @@
};
};
-&mac {
- slaves = <1>;
+&mac_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
-&davinci_mdio {
+&davinci_mdio_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <ðphy0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-rxid";
+ ti,dual-emac-pvid = <1>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
};
&rtc {
diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi
index 64fdd50..86bf668 100644
--- a/arch/arm/boot/dts/am437x-l4.dtsi
+++ b/arch/arm/boot/dts/am437x-l4.dtsi
@@ -132,7 +132,6 @@
target-module@7000 { /* 0x44e07000, ap 14 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio1";
reg = <0x7000 0x4>,
<0x7010 0x4>,
<0x7114 0x4>;
@@ -167,7 +166,6 @@
target-module@9000 { /* 0x44e09000, ap 16 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart1";
reg = <0x9050 0x4>,
<0x9054 0x4>,
<0x9058 0x4>;
@@ -195,7 +193,6 @@
target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c1";
reg = <0xb000 0x8>,
<0xb010 0x8>,
<0xb090 0x8>;
@@ -228,7 +225,6 @@
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
@@ -332,9 +328,8 @@
};
};
- target-module@31000 { /* 0x44e31000, ap 24 40.0 */
+ timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
- ti,hwmods = "timer1";
reg = <0x31000 0x4>,
<0x31010 0x4>,
<0x31014 0x4>;
@@ -373,7 +368,6 @@
target-module@35000 { /* 0x44e35000, ap 28 50.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "wd_timer2";
reg = <0x35000 0x4>,
<0x35010 0x4>,
<0x35014 0x4>;
@@ -415,9 +409,8 @@
ranges = <0x0 0x39000 0x1000>;
};
- target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */
+ rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "rtc";
reg = <0x3e074 0x4>,
<0x3e078 0x4>;
reg-names = "rev", "sysc";
@@ -455,7 +448,6 @@
target-module@86000 { /* 0x44e86000, ap 40 70.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "counter_32k";
reg = <0x86000 0x4>,
<0x86004 0x4>;
reg-names = "rev", "sysc";
@@ -528,54 +520,57 @@
#size-cells = <1>;
ranges = <0x0 0x100000 0x8000>;
- mac: ethernet@0 {
- compatible = "ti,am4372-cpsw","ti,cpsw";
- reg = <0x0 0x800
- 0x1200 0x100>;
+ mac_sw: switch@0 {
+ compatible = "ti,am4372-cpsw-switch", "ti,cpsw-switch";
+ reg = <0x0 0x4000>;
+ ranges = <0 0 0x4000>;
+ clocks = <&cpsw_125mhz_gclk>, <&dpll_clksel_mac_clk>;
+ clock-names = "fck", "50mclk";
+ assigned-clocks = <&dpll_clksel_mac_clk>;
+ assigned-clock-rates = <50000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscon = <&scm_conf>;
+ status = "disabled";
+
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
- <&dpll_clksel_mac_clk>;
- clock-names = "fck", "cpts", "50mclk";
- assigned-clocks = <&dpll_clksel_mac_clk>;
- assigned-clock-rates = <50000000>;
- status = "disabled";
- cpdma_channels = <8>;
- ale_entries = <1024>;
- bd_ram_size = <0x2000>;
- mac_control = <0x20>;
- slaves = <2>;
- active_slave = <0>;
- cpts_clock_mult = <0x80000000>;
- cpts_clock_shift = <29>;
- ranges = <0 0 0x8000>;
- syscon = <&scm_conf>;
+ interrupt-names = "rx_thresh", "rx", "tx", "misc";
- davinci_mdio: mdio@1000 {
- compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x1000 0x100>;
- clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ label = "port1";
+ mac-address = [ 00 00 00 00 00 00 ];
+ phys = <&phy_gmii_sel 1 0>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ label = "port2";
+ mac-address = [ 00 00 00 00 00 00 ];
+ phys = <&phy_gmii_sel 2 0>;
+ };
+ };
+
+ davinci_mdio_sw: mdio@1000 {
+ compatible = "ti,am4372-mdio", "ti,cpsw-mdio","ti,davinci_mdio";
+ clocks = <&cpsw_125mhz_gclk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
- status = "disabled";
+ reg = <0x1000 0x100>;
};
- cpsw_emac0: slave@200 {
- /* Filled in by U-Boot */
- mac-address = [ 00 00 00 00 00 00 ];
- phys = <&phy_gmii_sel 1 0>;
- };
-
- cpsw_emac1: slave@300 {
- /* Filled in by U-Boot */
- mac-address = [ 00 00 00 00 00 00 ];
- phys = <&phy_gmii_sel 2 0>;
+ cpts {
+ clocks = <&cpsw_cpts_rft_clk>;
+ clock-names = "cpts";
};
};
};
@@ -679,7 +674,6 @@
target-module@22000 { /* 0x48022000, ap 8 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart2";
reg = <0x22050 0x4>,
<0x22054 0x4>,
<0x22058 0x4>;
@@ -708,7 +702,6 @@
target-module@24000 { /* 0x48024000, ap 10 1c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart3";
reg = <0x24050 0x4>,
<0x24054 0x4>,
<0x24058 0x4>;
@@ -737,7 +730,6 @@
target-module@2a000 { /* 0x4802a000, ap 12 22.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c2";
reg = <0x2a000 0x8>,
<0x2a010 0x8>,
<0x2a090 0x8>;
@@ -770,7 +762,6 @@
target-module@30000 { /* 0x48030000, ap 65 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
@@ -817,7 +808,6 @@
target-module@38000 { /* 0x48038000, ap 14 04.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "mcasp0";
reg = <0x38000 0x4>,
<0x38004 0x4>;
reg-names = "rev", "sysc";
@@ -849,7 +839,6 @@
target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "mcasp1";
reg = <0x3c000 0x4>,
<0x3c004 0x4>;
reg-names = "rev", "sysc";
@@ -879,9 +868,8 @@
};
};
- target-module@40000 { /* 0x48040000, ap 18 1e.0 */
+ timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer2";
reg = <0x40000 0x4>,
<0x40010 0x4>,
<0x40014 0x4>;
@@ -909,7 +897,6 @@
target-module@42000 { /* 0x48042000, ap 20 24.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
@@ -936,7 +923,6 @@
target-module@44000 { /* 0x48044000, ap 22 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
@@ -964,7 +950,6 @@
target-module@46000 { /* 0x48046000, ap 24 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
@@ -992,7 +977,6 @@
target-module@48000 { /* 0x48048000, ap 26 1a.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
@@ -1020,7 +1004,6 @@
target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
@@ -1048,7 +1031,6 @@
target-module@4c000 { /* 0x4804c000, ap 28 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio2";
reg = <0x4c000 0x4>,
<0x4c010 0x4>,
<0x4c114 0x4>;
@@ -1083,7 +1065,6 @@
target-module@60000 { /* 0x48060000, ap 30 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc1";
reg = <0x602fc 0x4>,
<0x60110 0x4>,
<0x60114 0x4>;
@@ -1104,9 +1085,8 @@
ranges = <0x0 0x60000 0x1000>;
mmc1: mmc@0 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,am437-sdhci";
reg = <0x0 0x1000>;
- ti,dual-volt;
ti,needs-special-reset;
dmas = <&edma 24 0>,
<&edma 25 0>;
@@ -1118,7 +1098,6 @@
target-module@80000 { /* 0x48080000, ap 32 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@@ -1149,7 +1128,6 @@
target-module@c8000 { /* 0x480c8000, ap 73 06.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox";
reg = <0xc8000 0x4>,
<0xc8010 0x4>;
reg-names = "rev", "sysc";
@@ -1181,7 +1159,6 @@
target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
@@ -1262,7 +1239,6 @@
target-module@9c000 { /* 0x4819c000, ap 38 52.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c3";
reg = <0x9c000 0x8>,
<0x9c010 0x8>,
<0x9c090 0x8>;
@@ -1295,7 +1271,6 @@
target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
@@ -1326,7 +1301,6 @@
target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi2";
reg = <0xa2000 0x4>,
<0xa2110 0x4>,
<0xa2114 0x4>;
@@ -1357,7 +1331,6 @@
target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi3";
reg = <0xa4000 0x4>,
<0xa4110 0x4>,
<0xa4114 0x4>;
@@ -1388,7 +1361,6 @@
target-module@a6000 { /* 0x481a6000, ap 40 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart4";
reg = <0xa6050 0x4>,
<0xa6054 0x4>,
<0xa6058 0x4>;
@@ -1417,7 +1389,6 @@
target-module@a8000 { /* 0x481a8000, ap 42 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart5";
reg = <0xa8050 0x4>,
<0xa8054 0x4>,
<0xa8058 0x4>;
@@ -1446,7 +1417,6 @@
target-module@aa000 { /* 0x481aa000, ap 44 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart6";
reg = <0xaa050 0x4>,
<0xaa054 0x4>,
<0xaa058 0x4>;
@@ -1475,7 +1445,6 @@
target-module@ac000 { /* 0x481ac000, ap 46 30.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio3";
reg = <0xac000 0x4>,
<0xac010 0x4>,
<0xac114 0x4>;
@@ -1510,7 +1479,6 @@
target-module@ae000 { /* 0x481ae000, ap 48 32.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio4";
reg = <0xae000 0x4>,
<0xae010 0x4>,
<0xae114 0x4>;
@@ -1545,7 +1513,6 @@
target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer8";
reg = <0xc1000 0x4>,
<0xc1010 0x4>,
<0xc1014 0x4>;
@@ -1574,7 +1541,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
- ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>,
<&dcan0_fck>;
@@ -1598,7 +1564,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
- ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>,
<&dcan1_fck>;
@@ -1620,7 +1585,6 @@
target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmc2";
reg = <0xd82fc 0x4>,
<0xd8110 0x4>,
<0xd8114 0x4>;
@@ -1641,7 +1605,7 @@
ranges = <0x0 0xd8000 0x1000>;
mmc2: mmc@0 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,am437-sdhci";
reg = <0x0 0x1000>;
ti,needs-special-reset;
dmas = <&edma 2 0>,
@@ -1720,7 +1684,6 @@
target-module@0 { /* 0x48300000, ap 56 40.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
@@ -1773,7 +1736,6 @@
target-module@2000 { /* 0x48302000, ap 58 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
@@ -1826,7 +1788,6 @@
target-module@4000 { /* 0x48304000, ap 60 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@@ -1879,7 +1840,6 @@
target-module@6000 { /* 0x48306000, ap 96 58.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss3";
reg = <0x6000 0x4>,
<0x6004 0x4>;
reg-names = "rev", "sysc";
@@ -1921,7 +1881,6 @@
target-module@8000 { /* 0x48308000, ap 98 54.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss4";
reg = <0x8000 0x4>,
<0x8004 0x4>;
reg-names = "rev", "sysc";
@@ -1963,7 +1922,6 @@
target-module@a000 { /* 0x4830a000, ap 100 60.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss5";
reg = <0xa000 0x4>,
<0xa004 0x4>;
reg-names = "rev", "sysc";
@@ -2005,7 +1963,6 @@
target-module@10000 { /* 0x48310000, ap 64 4e.1 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "rng";
reg = <0x11fe0 0x4>,
<0x11fe4 0x4>;
reg-names = "rev", "sysc";
@@ -2044,7 +2001,6 @@
target-module@20000 { /* 0x48320000, ap 82 34.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio5";
reg = <0x20000 0x4>,
<0x20010 0x4>,
<0x20114 0x4>;
@@ -2079,7 +2035,6 @@
gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio6";
reg = <0x22000 0x4>,
<0x22010 0x4>,
<0x22114 0x4>;
@@ -2114,7 +2069,6 @@
target-module@26000 { /* 0x48326000, ap 86 66.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "vpfe0";
reg = <0x26000 0x4>,
<0x26104 0x4>;
reg-names = "rev", "sysc";
@@ -2141,7 +2095,6 @@
target-module@28000 { /* 0x48328000, ap 75 0e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "vpfe1";
reg = <0x28000 0x4>,
<0x28104 0x4>;
reg-names = "rev", "sysc";
@@ -2168,7 +2121,6 @@
target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "dss_core";
reg = <0x2a000 0x4>,
<0x2a010 0x4>,
<0x2a014 0x4>;
@@ -2186,11 +2138,86 @@
<0x00000800 0x0002a800 0x00000400>,
<0x00000c00 0x0002ac00 0x00000400>,
<0x00001000 0x0002b000 0x00001000>;
+
+ dss: dss@0 {
+ compatible = "ti,omap3-dss";
+ reg = <0 0x200>;
+ status = "disabled";
+ clocks = <&disp_clk>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x00000400>,
+ <0x00000400 0x00000400 0x00000400>,
+ <0x00000800 0x00000800 0x00000400>,
+ <0x00000c00 0x00000c00 0x00000400>,
+ <0x00001000 0x00001000 0x00001000>;
+
+ target-module@400 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x400 0x4>,
+ <0x410 0x4>,
+ <0x414 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x400>;
+
+ dispc: dispc@0 {
+ compatible = "ti,omap3-dispc";
+ reg = <0 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&disp_clk>;
+ clock-names = "fck";
+
+ max-memory-bandwidth = <230000000>;
+ };
+ };
+
+ target-module@800 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x800 0x4>,
+ <0x810 0x4>,
+ <0x814 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x400>;
+
+ rfbi: rfbi@0 {
+ compatible = "ti,omap3-rfbi";
+ reg = <0 0x100>;
+ clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+ };
+ };
};
target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer9";
reg = <0x3d000 0x4>,
<0x3d010 0x4>,
<0x3d014 0x4>;
@@ -2217,7 +2244,6 @@
target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer10";
reg = <0x3f000 0x4>,
<0x3f010 0x4>,
<0x3f014 0x4>;
@@ -2244,7 +2270,6 @@
target-module@41000 { /* 0x48341000, ap 106 76.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer11";
reg = <0x41000 0x4>,
<0x41010 0x4>,
<0x41014 0x4>;
@@ -2271,7 +2296,6 @@
target-module@45000 { /* 0x48345000, ap 108 6a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spi4";
reg = <0x45000 0x4>,
<0x45110 0x4>,
<0x45114 0x4>;
@@ -2302,7 +2326,6 @@
target-module@47000 { /* 0x48347000, ap 110 70.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "hdq1w";
reg = <0x47000 0x4>,
<0x47014 0x4>,
<0x47018 0x4>;
@@ -2336,7 +2359,6 @@
target-module@80000 { /* 0x48380000, ap 123 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_otg_ss0";
reg = <0x80000 0x4>,
<0x80010 0x4>;
reg-names = "rev", "sysc";
@@ -2387,7 +2409,6 @@
target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "ocp2scp0";
reg = <0xa8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
@@ -2418,7 +2439,6 @@
target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_otg_ss1";
reg = <0xc0000 0x4>,
<0xc0010 0x4>;
reg-names = "rev", "sysc";
@@ -2469,7 +2489,6 @@
target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "ocp2scp1";
reg = <0xe8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
diff --git a/arch/arm/boot/dts/am437x-sbc-t43.dts b/arch/arm/boot/dts/am437x-sbc-t43.dts
index 94cf07e..8ea3780 100644
--- a/arch/arm/boot/dts/am437x-sbc-t43.dts
+++ b/arch/arm/boot/dts/am437x-sbc-t43.dts
@@ -136,7 +136,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_pinctrl_default>;
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 74eaa6a..496ed34 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
*/
/* AM437x SK EVM */
@@ -134,22 +134,6 @@
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- panel-timing {
- clock-frequency = <9000000>;
- hactive = <480>;
- vactive = <272>;
- hfront-porch = <2>;
- hback-porch = <2>;
- hsync-len = <41>;
- vfront-porch = <2>;
- vback-porch = <2>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
-
port {
lcd_in: endpoint {
remote-endpoint = <&dpi_out>;
@@ -272,6 +256,12 @@
>;
};
+ clkout1_pin: pinmux_clkout1_pin {
+ pinctrl-single,pins = <
+ 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */
+ >;
+ };
+
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
@@ -593,6 +583,25 @@
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
+ ov2659@30 {
+ compatible = "ovti,ov2659";
+ reg = <0x30>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkout1_pin>;
+
+ clocks = <&clkout1_mux_ck>;
+ clock-names = "xvclk";
+ assigned-clocks = <&clkout1_mux_ck>;
+ assigned-clock-parents = <&clkout1_osc_div_ck>;
+
+ port {
+ ov2659_1: endpoint {
+ remote-endpoint = <&vpfe0_ep>;
+ link-frequencies = /bits/ 64 <70000000>;
+ };
+ };
+ };
+
edt-ft5306@38 {
status = "okay";
compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
@@ -694,7 +703,7 @@
pinctrl-1 = <&mmc3_pins_sleep>;
cap-power-off-card;
keep-power-in-suspend;
- ti,non-removable;
+ non-removable;
#address-cells = <1>;
#size-cells = <0>;
@@ -783,19 +792,17 @@
};
};
-&mac {
+&mac_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
- dual_emac = <1>;
status = "okay";
};
-&davinci_mdio {
+&davinci_mdio_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
ethphy0: ethernet-phy@4 {
reg = <4>;
@@ -806,16 +813,16 @@
};
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <ðphy0>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <1>;
+ phy-mode = "rgmii-rxid";
+ ti,dual-emac-pvid = <1>;
};
-&cpsw_emac1 {
+&cpsw_port2 {
phy-handle = <ðphy1>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <2>;
+ phy-mode = "rgmii-rxid";
+ ti,dual-emac-pvid = <2>;
};
&elm {
@@ -877,7 +884,7 @@
/* Camera port */
port {
vpfe0_ep: endpoint {
- /* remote-endpoint = <&sensor>; add once we have it */
+ remote-endpoint = <&ov2659_1>;
ti,am437x-vpfe-interface = <0>;
bus-width = <8>;
hsync-active = <0>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index d0ea958..d2aebdb 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/* AM43x EPOS EVM */
@@ -47,22 +47,6 @@
backlight = <&lcd_bl>;
- panel-timing {
- clock-frequency = <33000000>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch = <210>;
- hback-porch = <16>;
- hsync-len = <30>;
- vback-porch = <10>;
- vfront-porch = <22>;
- vsync-len = <13>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
-
port {
lcd_in: endpoint {
remote-endpoint = <&dpi_out>;
@@ -145,6 +129,12 @@
system-clock-frequency = <12000000>;
};
};
+
+ audio_mstrclk: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
};
&am43xx_pinmux {
@@ -560,29 +550,32 @@
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
-&mac {
+&mac_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
- slaves = <1>;
};
-&davinci_mdio {
+&davinci_mdio_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
- status = "okay";
ethphy0: ethernet-phy@16 {
reg = <16>;
};
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <ðphy0>;
phy-mode = "rmii";
phys = <&phy_gmii_sel 1 1>;
+ ti,dual-emac-pvid = <1>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
};
&i2c0 {
@@ -696,6 +689,21 @@
IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
};
+
+ ov2659@30 {
+ compatible = "ovti,ov2659";
+ reg = <0x30>;
+
+ clocks = <&audio_mstrclk>;
+ clock-names = "xvclk";
+
+ port {
+ ov2659_1: endpoint {
+ remote-endpoint = <&vpfe1_ep>;
+ link-frequencies = /bits/ 64 <70000000>;
+ };
+ };
+ };
};
&i2c2 {
@@ -828,6 +836,10 @@
status = "okay";
};
+&rtc_target {
+ status = "disabled";
+};
+
&tscadc {
status = "okay";
@@ -943,7 +955,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_pins>;
@@ -964,7 +976,7 @@
port {
vpfe1_ep: endpoint {
- /* remote-endpoint = <&sensor>; add once we have it */
+ remote-endpoint = <&ov2659_1>;
ti,am437x-vpfe-interface = <0>;
bus-width = <8>;
hsync-active = <0>;
diff --git a/arch/arm/boot/dts/am57-pruss.dtsi b/arch/arm/boot/dts/am57-pruss.dtsi
new file mode 100644
index 0000000..032c1ac
--- /dev/null
+++ b/arch/arm/boot/dts/am57-pruss.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * Common PRUSS data for TI AM57xx platforms
+ */
+
+&ocp {
+ pruss1_tm: target-module@4b226000 {
+ compatible = "ti,sysc-pruss", "ti,sysc";
+ reg = <0x4b226000 0x4>,
+ <0x4b226004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
+ SYSC_PRUSS_SUB_MWAIT)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
+ clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4b200000 0x80000>;
+ };
+
+ pruss2_tm: target-module@4b2a6000 {
+ compatible = "ti,sysc-pruss", "ti,sysc";
+ reg = <0x4b2a6000 0x4>,
+ <0x4b2a6004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
+ SYSC_PRUSS_SUB_MWAIT)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
+ clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4b280000 0x80000>;
+ };
+};
diff --git a/arch/arm/boot/dts/am5718.dtsi b/arch/arm/boot/dts/am5718.dtsi
index d51007c..6d7530a 100644
--- a/arch/arm/boot/dts/am5718.dtsi
+++ b/arch/arm/boot/dts/am5718.dtsi
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra72x.dtsi"
+#include "am57-pruss.dtsi"
/ {
compatible = "ti,am5718", "ti,dra7";
@@ -16,17 +17,13 @@
* VCP1, VCP2
* MLB
* ISS
- * USB3, USB4
+ * USB3
*/
&usb3_tm {
status = "disabled";
};
-&usb4_tm {
- status = "disabled";
-};
-
&atl_tm {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
index 10105a4..e81078c 100644
--- a/arch/arm/boot/dts/am571x-idk.dts
+++ b/arch/arm/boot/dts/am571x-idk.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -10,6 +10,7 @@
#include "dra7-mmc-iodelay.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
#include "am57xx-idk-common.dtsi"
+#include "dra7-ipu-dsp-common.dtsi"
/ {
model = "TI AM5718 IDK";
@@ -20,6 +21,33 @@
reg = <0x0 0x80000000 0x0 0x40000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipu2_memory_region: ipu2-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_memory_region: dsp1-memory@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_memory_region: ipu1-memory@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
leds {
compatible = "gpio-leds";
cpu0-led {
@@ -148,21 +176,19 @@
load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
};
-&mailbox5 {
+&ipu2 {
status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- status = "okay";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- status = "okay";
- };
+ memory-region = <&ipu2_memory_region>;
};
-&mailbox6 {
+&ipu1 {
status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- status = "okay";
- };
+ memory-region = <&ipu1_memory_region>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_memory_region>;
};
&pcie1_rc {
diff --git a/arch/arm/boot/dts/am5728.dtsi b/arch/arm/boot/dts/am5728.dtsi
index 82e5427..5e0bdf1 100644
--- a/arch/arm/boot/dts/am5728.dtsi
+++ b/arch/arm/boot/dts/am5728.dtsi
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra74x.dtsi"
+#include "am57-pruss.dtsi"
/ {
compatible = "ti,am5728", "ti,dra7";
diff --git a/arch/arm/boot/dts/am5729-beagleboneai.dts b/arch/arm/boot/dts/am5729-beagleboneai.dts
new file mode 100644
index 0000000..149cfaf
--- /dev/null
+++ b/arch/arm/boot/dts/am5729-beagleboneai.dts
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "dra74x.dtsi"
+#include "am57xx-commercial-grade.dtsi"
+#include "dra74x-mmc-iodelay.dtsi"
+#include "dra74-ipu-dsp-common.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/dra.h>
+
+/ {
+ model = "BeagleBoard.org BeagleBone AI";
+ compatible = "beagle,am5729-beagleboneai", "ti,am5728",
+ "ti,dra742", "ti,dra74", "ti,dra7";
+
+ aliases {
+ rtc0 = &tps659038_rtc;
+ rtc1 = &rtc;
+ display0 = &hdmi_conn;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipu2_memory_region: ipu2-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_memory_region: dsp1-memory@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_memory_region: ipu1-memory@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp2_memory_region: dsp2-memory@9f000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9f000000 0x0 0x800000>;
+ reusable;
+ status = "okay";
+ };
+
+ };
+
+ vdd_adc: gpioregulator-vdd_adc {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd_adc";
+ vin-supply = <&vdd_5v>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0
+ 3300000 1>;
+ };
+
+ vdd_5v: fixedregulator-vdd_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vtt_fixed: fixedregulator-vtt {
+ /* TPS51200 */
+ compatible = "regulator-fixed";
+ regulator-name = "vtt_fixed";
+ vin-supply = <&vdd_ddr>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ label = "beaglebone:green:usr0";
+ gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led1 {
+ label = "beaglebone:green:usr1";
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "beaglebone:green:usr2";
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "cpu";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "beaglebone:green:usr3";
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "beaglebone:green:usr4";
+ gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "netdev";
+ default-state = "off";
+ };
+ };
+
+ hdmi_conn: connector@0 {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_encoder_out>;
+ };
+ };
+ };
+
+ hdmi_enc: encoder@0 {
+ /* "ti,tpd12s016" software compatible with "ti,tpd12s015"
+ * no need for individual driver
+ */
+ compatible = "ti,tpd12s015";
+ gpios = <0>,
+ <0>,
+ <&gpio7 12 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ hdmi_encoder_in: endpoint@0 {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ hdmi_encoder_out: endpoint@0 {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ };
+
+ brcmf_pwrseq: brcmf_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */
+ <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ ti,enable-id-detection;
+ id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps659038: tps659038@58 {
+ compatible = "ti,tps659038";
+ reg = <0x58>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,system-power-controller;
+ ti,palmas-override-powerhold;
+
+ tps659038_pmic {
+ compatible = "ti,tps659038-pmic";
+
+ smps12-in-supply = <&vdd_5v>;
+ smps3-in-supply = <&vdd_5v>;
+ smps45-in-supply = <&vdd_5v>;
+ smps6-in-supply = <&vdd_5v>;
+ smps7-in-supply = <&vdd_5v>;
+ mps3-in-supply = <&vdd_5v>;
+ smps8-in-supply = <&vdd_5v>;
+ smps9-in-supply = <&vdd_5v>;
+ ldo1-in-supply = <&vdd_5v>;
+ ldo2-in-supply = <&vdd_5v>;
+ ldo3-in-supply = <&vdd_5v>;
+ ldo4-in-supply = <&vdd_5v>;
+ ldo9-in-supply = <&vdd_5v>;
+ ldoln-in-supply = <&vdd_5v>;
+ ldousb-in-supply = <&vdd_5v>;
+ ldortc-in-supply = <&vdd_5v>;
+
+ regulators {
+ vdd_mpu: smps12 {
+ /* VDD_MPU */
+ regulator-name = "smps12";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_ddr: smps3 {
+ /* VDD_DDR EMIF1 EMIF2 */
+ regulator-name = "smps3";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_dspeve: smps45 {
+ /* VDD_DSPEVE on AM572 */
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_gpu: smps6 {
+ /* VDD_GPU */
+ regulator-name = "smps6";
+ regulator-min-microvolt = < 850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_core: smps7 {
+ /* VDD_CORE */
+ regulator-name = "smps7";
+ regulator-min-microvolt = < 850000>; /*** 1.15V */
+ regulator-max-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_iva: smps8 {
+ /* VDD_IVAHD */ /*** 1.06V */
+ regulator-name = "smps8";
+ };
+
+ vdd_3v3: smps9 {
+ /* VDD_3V3 */
+ regulator-name = "smps9";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_sd: ldo1 {
+ /* VDDSHV8 - VSDMMC */
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_1v8: ldo2 {
+ /* VDDSH18V */
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_phy_ldo3: ldo3 {
+ /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_phy_ldo4: ldo4 {
+ /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* LDO5-8 unused */
+
+ vdd_rtc: ldo9 {
+ /* VDD_RTC */
+ regulator-name = "ldo9";
+ regulator-min-microvolt = < 840000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v8_pll: ldoln {
+ /* VDDA_1V8_PLL */
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ /* VDDA_3V_USB: VDDA_USBHS33 */
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldortc_reg: ldortc {
+ /* VDDA_RTC */
+ regulator-name = "ldortc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ regen1: regen1 {
+ /* VDD_3V3_ON */
+ regulator-name = "regen1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ regen2: regen2 {
+ /* Needed for PMIC internal resource */
+ regulator-name = "regen2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ tps659038_rtc: tps659038_rtc {
+ compatible = "ti,palmas-rtc";
+ interrupt-parent = <&tps659038>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ };
+
+ tps659038_pwr_button: tps659038_pwr_button {
+ compatible = "ti,palmas-pwrbutton";
+ interrupt-parent = <&tps659038>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
+ ti,palmas-long-press-seconds = <12>;
+ };
+
+ tps659038_gpio: tps659038_gpio {
+ compatible = "ti,palmas-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ /* STMPE811 touch screen controller */
+ stmpe811@41 {
+ compatible = "st,stmpe811";
+ reg = <0x41>;
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio2>;
+ interrupt-controller;
+ id = <0>;
+ blocks = <0x5>;
+ irq-trigger = <0x1>;
+ st,mod-12b = <1>; /* 12-bit ADC */
+ st,ref-sel = <0>; /* internal ADC reference */
+ st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
+ st,sample-time = <4>; /* ADC converstion time: 80 clocks */
+
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ st,norequest-mask = <0x00>; /* mask any channels to be used by touchscreen */
+ adc0: iio-device@0 {
+ #io-channel-cells = <1>;
+ iio-channels = <&adc0 4>, <&adc0 1>, <&adc0 2>, <&adc0 3>, <&adc0 4>, <&adc0 5>, <&adc0 6>;
+ iio-channel-names = "AIN0_P9_39", "AIN1_P9_40", "AIN2_P9_37", "AIN3_P9_38",
+ "AIN4_P9_33", "AIN5_P9_36", "AIN6_P9_35";
+ };
+ };
+
+ stmpe_touchscreen {
+ status = "disabled";
+ compatible = "st,stmpe-ts";
+ /* 8 sample average control */
+ st,ave-ctrl = <3>;
+ /* 7 length fractional part in z */
+ st,fraction-z = <7>;
+ /*
+ * 50 mA typical 80 mA max touchscreen drivers
+ * current limit value
+ */
+ st,i-drive = <1>;
+ /* 1 ms panel driver settling time */
+ st,settling = <3>;
+ /* 5 ms touch detect interrupt delay */
+ st,touch-det-delay = <5>;
+ };
+
+ stmpe_gpio {
+ compatible = "st,stmpe-gpio";
+ };
+
+ stmpe_pwm {
+ compatible = "st,stmpe-pwm";
+ #pwm-cells = <2>;
+ };
+ };
+};
+
+&mcspi3 {
+ status = "okay";
+ ti,pindir-d0-out-d1-in;
+
+ sn65hvs882: sn65hvs882@0 {
+ compatible = "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ };
+};
+
+&cpu0 {
+ vdd-supply = <&vdd_mpu>;
+ voltage-tolerance = <1>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&davinci_mdio_sw {
+ reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy@4 {
+ reg = <4>;
+ eee-broken-100tx;
+ eee-broken-1000t;
+ };
+};
+
+&mac_sw {
+ status = "okay";
+};
+
+&cpsw_port1 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-rxid";
+ ti,dual-emac-pvid = <1>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&ocp {
+ pruss1_shmem: pruss_shmem@4b200000 {
+ status = "okay";
+ compatible = "ti,pruss-shmem";
+ reg = <0x4b200000 0x020000>;
+ };
+
+ pruss2_shmem: pruss_shmem@4b280000 {
+ status = "okay";
+ compatible = "ti,pruss-shmem";
+ reg = <0x4b280000 0x020000>;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&vdd_sd>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+};
+
+&mmc2 {
+ status = "okay";
+ vmmc-supply = <&vdd_1v8>;
+ vqmmc-supply = <&vdd_1v8>;
+ bus-width = <8>;
+ ti,non-removable;
+ non-removable;
+ mmc-pwrseq = <&emmc_pwrseq>;
+
+ ti,needs-special-reset;
+ dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
+ dma-names = "tx", "rx";
+
+};
+
+&mmc4 {
+ /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
+ /* HS: High speed up to 50 MHz (3.3 V signaling). */
+ /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
+ /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
+ /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
+ /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
+ /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
+ status = "okay";
+
+ ti,needs-special-reset;
+ vmmc-supply = <&vdd_3v3>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ ti,non-removable;
+ non-removable;
+ no-1-8-v;
+ max-frequency = <24000000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mmc-pwrseq = <&brcmf_pwrseq>;
+
+ brcmf: wifi@1 {
+ status = "okay";
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+
+ brcm,sd-head-align = <4>;
+ brcm,sd_head_align = <4>;
+ brcm,sd_sgentry_align = <512>;
+
+ interrupt-parent = <&gpio3>;
+ interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&usb2_phy1 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb2_phy2 {
+ phy-supply = <&ldousb_reg>;
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&omap_dwc3_1 {
+ extcon = <&extcon_usb1>;
+};
+
+&usb2 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&dss {
+ status = "okay";
+ vdda_video-supply = <&vdd_1v8_pll>;
+};
+
+&hdmi {
+ status = "okay";
+ vdda-supply = <&vdd_1v8_phy_ldo4>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&hdmi_encoder_in>;
+ };
+ };
+};
+
+&bandgap {
+ status = "okay";
+};
+
+&cpu_alert0 {
+ temperature = <55000>; /* milliCelsius */
+};
+
+&cpu_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&gpu_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&core_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&dspeve_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&iva_crit {
+ temperature = <85000>; /* milliCelsius */
+};
+
+&sata {
+ status = "disabled";
+};
+
+&sata_phy {
+ status = "disabled";
+};
+
+/* bluetooth */
+&uart6 {
+ status = "okay";
+};
+
+/* cape header stuff */
+&i2c4 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cpu0_opp_table {
+ opp_slow-500000000 {
+ opp-shared;
+ };
+};
+
+&ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_memory_region>;
+};
+
+&ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_memory_region>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_memory_region>;
+};
+
+&dsp2 {
+ status = "okay";
+ memory-region = <&dsp2_memory_region>;
+};
diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi
index ddf1236..1d66278 100644
--- a/arch/arm/boot/dts/am572x-idk-common.dtsi
+++ b/arch/arm/boot/dts/am572x-idk-common.dtsi
@@ -1,11 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
+#include "dra74-ipu-dsp-common.dtsi"
/ {
memory@0 {
@@ -13,6 +14,40 @@
reg = <0x0 0x80000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipu2_memory_region: ipu2-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_memory_region: dsp1-memory@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_memory_region: ipu1-memory@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp2_memory_region: dsp2-memory@9f000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9f000000 0x0 0x800000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
status-leds {
compatible = "gpio-leds";
cpu0-led {
@@ -147,22 +182,22 @@
gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
};
-&mailbox5 {
+&ipu2 {
status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- status = "okay";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- status = "okay";
- };
+ memory-region = <&ipu2_memory_region>;
};
-&mailbox6 {
+&ipu1 {
status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- status = "okay";
- };
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
- status = "okay";
- };
+ memory-region = <&ipu1_memory_region>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_memory_region>;
+};
+
+&dsp2 {
+ status = "okay";
+ memory-region = <&dsp2_memory_region>;
};
diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
index ea1c119..6504265 100644
--- a/arch/arm/boot/dts/am572x-idk.dts
+++ b/arch/arm/boot/dts/am572x-idk.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/am5748.dtsi b/arch/arm/boot/dts/am5748.dtsi
index 5e12975..2cb5774 100644
--- a/arch/arm/boot/dts/am5748.dtsi
+++ b/arch/arm/boot/dts/am5748.dtsi
@@ -1,9 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra76x.dtsi"
+#include "am57-pruss.dtsi"
/ {
compatible = "ti,am5748", "ti,dra762", "ti,dra7";
diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts
index 7935d70..3775876 100644
--- a/arch/arm/boot/dts/am574x-idk.dts
+++ b/arch/arm/boot/dts/am574x-idk.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
@@ -35,3 +35,7 @@
pinctrl-1 = <&mmc2_pins_default>;
pinctrl-2 = <&mmc2_pins_default>;
};
+
+&m_can0 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index a813a0c..6b82ecf 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -1,12 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "am5728.dtsi"
#include "am57xx-commercial-grade.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
+#include "dra74-ipu-dsp-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -50,6 +51,40 @@
regulator-boot-on;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipu2_memory_region: ipu2-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_memory_region: dsp1-memory@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_memory_region: ipu1-memory@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp2_memory_region: dsp2-memory@9f000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9f000000 0x0 0x800000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
vdd_3v3: fixedregulator-vdd_3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
@@ -416,7 +451,7 @@
<&dra7_pmx_core 0x3f8>;
};
-&davinci_mdio {
+&davinci_mdio_sw {
phy0: ethernet-phy@1 {
reg = <1>;
};
@@ -426,21 +461,20 @@
};
};
-&mac {
+&mac_sw {
status = "okay";
- dual_emac;
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <&phy0>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <1>;
+ phy-mode = "rgmii-rxid";
+ ti,dual-emac-pvid = <1>;
};
-&cpsw_emac1 {
+&cpsw_port2 {
phy-handle = <&phy1>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <2>;
+ phy-mode = "rgmii-rxid";
+ ti,dual-emac-pvid = <2>;
};
&mmc1 {
@@ -547,13 +581,13 @@
};
&dss {
- status = "ok";
+ status = "okay";
vdda_video-supply = <&ldoln_reg>;
};
&hdmi {
- status = "ok";
+ status = "okay";
vdda-supply = <&ldo4_reg>;
port {
@@ -564,7 +598,7 @@
};
&pcie1_rc {
- status = "ok";
+ status = "okay";
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
@@ -584,22 +618,22 @@
rx-num-evt = <32>;
};
-&mailbox5 {
+&ipu2 {
status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- status = "okay";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- status = "okay";
- };
+ memory-region = <&ipu2_memory_region>;
};
-&mailbox6 {
+&ipu1 {
status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- status = "okay";
- };
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
- status = "okay";
- };
+ memory-region = <&ipu1_memory_region>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_memory_region>;
+};
+
+&dsp2 {
+ status = "okay";
+ memory-region = <&dsp2_memory_region>;
};
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
index 7b113b5..83e174e 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-beagle-x15-common.dtsi"
@@ -24,7 +24,7 @@
};
&mmc2 {
- pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_3_3v_rev11 &mmc2_iodelay_ddr_3_3v_rev11_conf>;
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
index 30c500b..656dd84 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-beagle-x15-common.dtsi"
@@ -24,7 +24,7 @@
};
&mmc2 {
- pinctrl-names = "default", "hs", "ddr_1_8v";
+ pinctrl-names = "default", "hs", "ddr_3_3v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
pinctrl-2 = <&mmc2_pins_ddr_rev20>;
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index a5c24ed..0a8b165 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-beagle-x15-common.dtsi"
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index e86d479..aed8156 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -454,20 +454,20 @@
&mailbox5 {
status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
status = "okay";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
status = "okay";
};
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
status = "okay";
};
};
@@ -546,27 +546,26 @@
};
};
-&mac {
+&mac_sw {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_pins_default>;
pinctrl-1 = <&cpsw_pins_sleep>;
- dual_emac;
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <ðphy0>;
phy-mode = "rgmii-txid";
- dual_emac_res_vlan = <0>;
+ ti,dual-emac-pvid = <1>;
};
-&cpsw_emac1 {
+&cpsw_port2 {
phy-handle = <ðphy1>;
phy-mode = "rgmii-txid";
- dual_emac_res_vlan = <1>;
+ ti,dual-emac-pvid = <2>;
};
-&davinci_mdio {
+&davinci_mdio_sw {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_pins_default>;
pinctrl-1 = <&davinci_mdio_pins_sleep>;
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 423855a..9fcb894 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-industrial-grade.dtsi"
@@ -9,6 +9,7 @@
aliases {
rtc0 = &tps659038_rtc;
rtc1 = &rtc;
+ display0 = &hdmi0;
};
chosen {
@@ -34,6 +35,16 @@
regulator-boot-on;
};
+ v1_2d: fixedregulator-v1_2d {
+ compatible = "regulator-fixed";
+ regulator-name = "V1_2D";
+ vin-supply = <&vmain>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
vtt_fixed: fixedregulator-vtt {
/* TPS51200 */
compatible = "regulator-fixed";
@@ -96,6 +107,54 @@
default-state = "off";
};
};
+
+ hdmi0: connector@0 {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder@0 {
+ compatible = "ti,tpd12s016", "ti,tpd12s015";
+
+ gpios = <0>, /* optional CT_CP_HPD */
+ <0>, /* optional LS_OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint@0 {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint@0 {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
+ src_clk_x1: src_clk_x1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
};
&dra7_pmx_core {
@@ -335,6 +394,32 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ dsi_bridge: tc358778@e {
+ compatible = "toshiba,tc358778", "toshiba,tc358768";
+ reg = <0xe>;
+ status = "disabled";
+
+ clocks = <&src_clk_x1>;
+ clock-names = "refclk";
+
+ vddc-supply = <&v1_2d>;
+ vddmipi-supply = <&v1_2d>;
+ vddio-supply = <&v3_3d>;
+
+ dsi_bridge_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ rgb_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ data-lines = <24>;
+ };
+ };
+ };
+ };
};
&mcspi3 {
@@ -363,24 +448,23 @@
ext-clk-src;
};
-&mac {
+&mac_sw {
status = "okay";
- dual_emac;
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <ðphy0>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <1>;
+ phy-mode = "rgmii-rxid";
+ ti,dual-emac-pvid = <1>;
};
-&cpsw_emac1 {
+&cpsw_port2 {
phy-handle = <ðphy1>;
- phy-mode = "rgmii";
- dual_emac_res_vlan = <2>;
+ phy-mode = "rgmii-rxid";
+ ti,dual-emac-pvid = <2>;
};
-&davinci_mdio {
+&davinci_mdio_sw {
ethphy0: ethernet-phy@0 {
reg = <0>;
};
@@ -490,3 +574,35 @@
&cpu0 {
vdd-supply = <&smps12_reg>;
};
+
+&hdmi {
+ status = "okay";
+
+ vdda-supply = <&ldo4_reg>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
+
+&dss {
+ status = "okay";
+
+ vdda_video-supply = <&ldoln_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpi_out: endpoint {
+ remote-endpoint = <&rgb_in>;
+ data-lines = <24>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
index ce5bf1d..beef63e 100644
--- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
@@ -120,7 +120,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
vdda_video-supply = <&ldoln_reg>;
@@ -148,7 +148,7 @@
};
&hdmi {
- status = "ok";
+ status = "okay";
vdda-supply = <&ldo4_reg>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index c36d28c..7da718a 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -26,7 +26,7 @@
stdout-path = &usart2;
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
@@ -81,6 +81,7 @@
pinctrl-0 = <&pinctrl_mmc0_clk
&pinctrl_mmc0_slot1_cmd_dat0
&pinctrl_mmc0_slot1_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@1 {
diff --git a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi
index 29b636f..26783d0 100644
--- a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi
+++ b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi
@@ -59,7 +59,7 @@
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
};
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,l220-cache";
reg = <0x1f002000 0x1000>;
interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi
index fe0207b..a534a8e 100644
--- a/arch/arm/boot/dts/arm-realview-eb.dtsi
+++ b/arch/arm/boot/dts/arm-realview-eb.dtsi
@@ -390,7 +390,7 @@
compatible = "arm,sp805", "arm,primecell";
reg = <0x10010000 0x1000>;
clocks = <&wdogclk>, <&pclk>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
index 2625ce6..f925782 100644
--- a/arch/arm/boot/dts/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -323,7 +323,7 @@
<0x10120000 0x100>;
};
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,l220-cache";
reg = <0x10110000 0x1000>;
interrupt-parent = <&intc_dc1176>;
diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts
index c69cf7d..0c7dabe 100644
--- a/arch/arm/boot/dts/arm-realview-pb11mp.dts
+++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts
@@ -92,7 +92,7 @@
<0x1f000100 0x100>;
};
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,l220-cache";
reg = <0x1f002000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
@@ -546,7 +546,7 @@
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wdogclk>, <&pclk>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
status = "disabled";
};
@@ -556,7 +556,7 @@
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wdogclk>, <&pclk>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
};
timer01: timer@10011000 {
@@ -568,8 +568,8 @@
clocks = <&sp810_syscon 0>,
<&sp810_syscon 1>,
<&pclk>;
- clock-names = "timerclk0",
- "timerclk1",
+ clock-names = "timer0clk",
+ "timer1clk",
"apb_pclk";
};
@@ -582,8 +582,8 @@
clocks = <&sp810_syscon 2>,
<&sp810_syscon 3>,
<&pclk>;
- clock-names = "timerclk2",
- "timerclk3",
+ clock-names = "timer0clk",
+ "timer1clk",
"apb_pclk";
};
@@ -645,16 +645,16 @@
timer45: timer@10018000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x10018000 0x1000>;
- clocks = <&timclk>, <&pclk>;
- clock-names = "timer", "apb_pclk";
+ clocks = <&timclk>, <&timclk>, <&pclk>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
timer67: timer@10019000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x10019000 0x1000>;
- clocks = <&timclk>, <&pclk>;
- clock-names = "timer", "apb_pclk";
+ clocks = <&timclk>, <&timclk>, <&pclk>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
index 90d00b4..85d3968 100644
--- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts
+++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
@@ -60,7 +60,7 @@
};
};
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0x1f002000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index 09f3f54..ac95667 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -210,7 +210,7 @@
};
};
- soc: soc@0 {
+ soc: soc {
compatible = "arm,realview-pbx-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -381,7 +381,7 @@
compatible = "arm,sp805", "arm,primecell";
reg = <0x1000f000 0x1000>;
clocks = <&wdogclk>, <&pclk>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
status = "disabled";
};
@@ -389,7 +389,7 @@
compatible = "arm,sp805", "arm,primecell";
reg = <0x10010000 0x1000>;
clocks = <&wdogclk>, <&pclk>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
index baa459d..2008c6e 100644
--- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
+++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
@@ -247,9 +247,8 @@
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
- marvell,reg-init = <0x0 0x16 0x0 0x0002>,
- <0x0 0x19 0x0 0x0077>,
- <0x0 0x18 0x0 0x5747>;
+ marvell,reg-init = <0x2 0x19 0x0 0x0077>,
+ <0x2 0x18 0x0 0x5747>;
};
};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index c15f5e9..0b8c2a6 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -114,7 +114,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <31>;
- timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
@@ -124,7 +123,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <32>;
- timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index 2932a29..9805e50 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -236,7 +236,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
@@ -247,7 +246,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts
new file mode 100644
index 0000000..c9ac630
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "armada-385-clearfog-gtr.dtsi"
+
+/ {
+ model = "SolidRun Clearfog GTR L8";
+};
+
+&mdio {
+ switch0: switch0@4 {
+ compatible = "marvell,mv88e6190";
+ reg = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cf_gtr_switch_reset_pins>;
+ reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ label = "lan8";
+ phy-handle = <&switch0phy0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan7";
+ phy-handle = <&switch0phy1>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan6";
+ phy-handle = <&switch0phy2>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan5";
+ phy-handle = <&switch0phy3>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan4";
+ phy-handle = <&switch0phy4>;
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "lan3";
+ phy-handle = <&switch0phy5>;
+ };
+
+ port@7 {
+ reg = <7>;
+ label = "lan2";
+ phy-handle = <&switch0phy6>;
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "lan1";
+ phy-handle = <&switch0phy7>;
+ };
+
+ port@10 {
+ reg = <10>;
+ label = "cpu";
+ ethernet = <ð1>;
+ };
+
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy0: switch0phy0@1 {
+ reg = <0x1>;
+ };
+
+ switch0phy1: switch0phy1@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy2: switch0phy2@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy3: switch0phy3@4 {
+ reg = <0x4>;
+ };
+
+ switch0phy4: switch0phy4@5 {
+ reg = <0x5>;
+ };
+
+ switch0phy5: switch0phy5@6 {
+ reg = <0x6>;
+ };
+
+ switch0phy6: switch0phy6@7 {
+ reg = <0x7>;
+ };
+
+ switch0phy7: switch0phy7@8 {
+ reg = <0x8>;
+ };
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts
new file mode 100644
index 0000000..fa653b3
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "armada-385-clearfog-gtr.dtsi"
+
+/ {
+ model = "SolidRun Clearfog GTR S4";
+};
+
+&sfp0 {
+ tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+};
+
+&mdio {
+ switch0: switch0@4 {
+ compatible = "marvell,mv88e6085";
+ reg = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cf_gtr_switch_reset_pins>;
+ reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-handle = <&switch0phy0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan1";
+ phy-handle = <&switch0phy1>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ phy-handle = <&switch0phy2>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan3";
+ phy-handle = <&switch0phy3>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <ð1>;
+ };
+
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy0: switch0phy0@11 {
+ reg = <0x11>;
+ };
+
+ switch0phy1: switch0phy1@12 {
+ reg = <0x12>;
+ };
+
+ switch0phy2: switch0phy2@13 {
+ reg = <0x13>;
+ };
+
+ switch0phy3: switch0phy3@14 {
+ reg = <0x14>;
+ };
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi
new file mode 100644
index 0000000..624bbca
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi
@@ -0,0 +1,450 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
+ *
+ * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
+ */
+
+/*
+ SERDES mapping -
+ 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
+ 1. 6141 switch (2.5Gbps capable)
+ 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
+ 3. USB 3.0 Host
+ 4. mini PCIe CON2 - PCIe2
+ 5. SFP connector, or optionally SGMII Ethernet 1512 PHY
+
+ USB 2.0 mapping -
+ 0. USB 2.0 - 0 USB pins header CON12
+ 1. USB 2.0 - 1 mini PCIe CON2
+ 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
+
+ Pin mapping -
+ 0,1 - console UART
+ 2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
+ front panel and PSE controller
+ 4,5 - MDC/MDIO
+ 6..17 - RGMII
+ 18 - Topaz switch reset (active low)
+ 19 - 1512 phy reset
+ 20 - 1512 phy reset (eth2, optional)
+ 21,28,37,38,39,40 - SD0
+ 22 - USB 3.0 current limiter enable (active high)
+ 24 - SFP TX fault (input active high)
+ 25 - SFP present (input active low)
+ 26,27 - I2C1 - connected to SFP
+ 29 - Fan PWM
+ 30 - CON4 mini PCIe wifi disable
+ 31 - CON3 mini PCIe wifi disable
+ 32 - Fuse programming power toggle (1.8v)
+ 33 - CON4 mini PCIe reset
+ 34 - CON2 mini PCIe wifi disable
+ 35 - CON3 mini PCIe reset
+ 36 - Rear button (GPIO active low)
+ 41 - CON1 front panel connector
+ 42 - Front LED1, or front panel CON1
+ 43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
+ 44 - CON2 mini PCIe reset
+ 45 - TPM PIRQ signal, or front panel CON1
+ 46 - SFP TX disable
+ 47 - Control isolation of boot sensitive SAR signals
+ 48 - PSE reset
+ 49 - PSE OSS signal
+ 50 - PSE interrupt
+ 52 - Front LED2, or front panel
+ 53 - Front button
+ 54 - SFP LOS (input active high)
+ 55 - Fan sense
+ 56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
+ 59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
+*/
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "armada-385.dtsi"
+
+/ {
+ compatible = "marvell,armada385", "marvell,armada380";
+
+ aliases {
+ /* So that mvebu u-boot can update the MAC addresses */
+ ethernet1 = ð0;
+ ethernet2 = ð1;
+ ethernet3 = ð2;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; /* 256 MB */
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "5P0V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ v_usb3_con: regulator-v-usb3-con {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "v_usb3_con";
+ vin-supply = <®_5p0v>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+
+ internal-regs {
+
+ rtc@a3800 {
+ status = "okay";
+ };
+
+ i2c@11000 { /* ROM, temp sensor and front panel */
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ i2c@11100 { /* SFP (CON5/CON6) */
+ pinctrl-0 = <&cf_gtr_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ pinctrl@18000 {
+ cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
+ marvell,pins = "mpp18";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
+ marvell,pins = "mpp22";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_fan_pwm: cf-gtr-fan-pwm {
+ marvell,pins = "mpp23";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_i2c1_pins: i2c1-pins {
+ /* SFP */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+
+ cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
+ marvell,pins = "mpp21", "mpp28",
+ "mpp37", "mpp38",
+ "mpp39", "mpp40";
+ marvell,function = "sd0";
+ };
+
+ cf_gtr_isolation_pins: cf-gtr-isolation-pins {
+ marvell,pins = "mpp47";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
+ marvell,pins = "mpp48";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp59";
+ marvell,function = "spi1";
+ };
+
+ cf_gtr_front_button_pins: cf-gtr-front-button-pins {
+ marvell,pins = "mpp53";
+ marvell,function = "gpio";
+ };
+
+ cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
+ marvell,pins = "mpp36";
+ marvell,function = "gpio";
+ };
+ };
+
+ sdhci@d8000 {
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ pinctrl-0 = <&cf_gtr_sdhci_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc = <®_3p3v>;
+ wp-inverted;
+ };
+
+ usb@58000 {
+ status = "okay";
+ };
+
+ usb3@f0000 {
+ status = "okay";
+ };
+
+ usb3@f8000 {
+ vbus-supply = <&v_usb3_con>;
+ status = "okay";
+ };
+ };
+
+ pcie {
+ status = "okay";
+ /*
+ * The PCIe units are accessible through
+ * the mini-PCIe connectors on the board.
+ */
+ pcie@1,0 {
+ reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+
+ pcie@2,0 {
+ reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+
+ pcie@3,0 {
+ reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ };
+ };
+
+ sfp0: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
+ pinctrl-names = "default";
+
+ button_0 {
+ label = "Rear Button";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_0>;
+ };
+
+ button_1 {
+ label = "Front Button";
+ gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ linux,can-disable;
+ linux,code = <BTN_1>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ function = LED_FUNCTION_CPU;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ led2 {
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&bm {
+ status = "okay";
+};
+
+&bm_bppi {
+ status = "okay";
+};
+
+ð0 {
+ /* ethernet@70000 */
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ phy = <&phy_dedicated>;
+ phy-mode = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+ status = "okay";
+};
+
+ð1 {
+ /* ethernet@30000 */
+ bm,pool-long = <2>;
+ bm,pool-short = <1>;
+ buffer-manager = <&bm>;
+ phys = <&comphy1 1>;
+ phy-mode = "2500base-x";
+ status = "okay";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+};
+
+ð2 {
+ /* ethernet@34000 */
+ bm,pool-long = <3>;
+ bm,pool-short = <1>;
+ buffer-manager = <&bm>;
+ managed = "in-band-status";
+ phys = <&comphy5 1>;
+ phy-mode = "sgmii";
+ sfp = <&sfp0>;
+ status = "okay";
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ phy_dedicated: ethernet-phy@0 {
+ /*
+ * Annoyingly, the marvell phy driver configures the LED
+ * register, rather than preserving reset-loaded setting.
+ * We undo that rubbish here.
+ */
+ marvell,reg-init = <3 16 0 0x1017>;
+ reg = <0>;
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&spi1 {
+ /*
+ * CS0: W25Q32 flash
+ */
+ pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "w25q32", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <3000000>;
+ status = "okay";
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* U26 temperature sensor placed near SoC */
+ temp1: nct75@4c {
+ compatible = "lm75";
+ reg = <0x4c>;
+ };
+
+ /* U27 temperature sensor placed near RTC battery */
+ temp2: nct75@4d {
+ compatible = "lm75";
+ reg = <0x4d>;
+ };
+
+ /* 2Kb eeprom */
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
+};
+
+&ahci0 {
+ status = "okay";
+};
+
+&ahci1 {
+ status = "okay";
+};
+
+&gpio0 {
+ pinctrl-0 = <&cf_gtr_fan_pwm>;
+ pinctrl-names = "default";
+
+ wifi-disable {
+ gpio-hog;
+ gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "wifi-disable";
+ };
+};
+
+&gpio1 {
+ pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
+ pinctrl-names = "default";
+
+ lte-disable {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "lte-disable";
+ };
+
+ /*
+ * This signal, when asserted, isolates Armada 38x sample at reset pins
+ * from control of external devices. Should be de-asserted after reset.
+ */
+ sar-isolation {
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "sar-isolation";
+ };
+
+ poe-reset {
+ gpio-hog;
+ gpios = <16 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "poe-reset";
+ };
+};
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 0d81600..a0aa1d1 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -111,11 +111,6 @@
};
&i2c0 {
- clock-frequency = <400000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
@@ -183,6 +178,12 @@
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
};
&i2c1 {
diff --git a/arch/arm/boot/dts/armada-388-helios4.dts b/arch/arm/boot/dts/armada-388-helios4.dts
index a947580..a7ff774 100644
--- a/arch/arm/boot/dts/armada-388-helios4.dts
+++ b/arch/arm/boot/dts/armada-388-helios4.dts
@@ -150,11 +150,6 @@
soc {
internal-regs {
i2c@11000 {
- clock-frequency = <400000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-Board Revision bit 0 #
diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
index 3a7f9c1..363ac42 100644
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -71,6 +71,19 @@
};
};
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+};
+
&pinctrl {
microsom_phy_clk_pins: microsom-phy-clk-pins {
marvell,pins = "mpp45";
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 669da3a..df3c8d1 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -103,6 +103,11 @@
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+ sdramc: sdramc@1400 {
+ compatible = "marvell,armada-xp-sdram-controller";
+ reg = <0x1400 0x500>;
+ };
+
L2: cache-controller@8000 {
compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;
@@ -148,7 +153,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
@@ -159,13 +163,12 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
uart0: serial@12000 {
- compatible = "marvell,armada-38x-uart";
+ compatible = "marvell,armada-38x-uart", "ns16550a";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@@ -175,7 +178,7 @@
};
uart1: serial@12100 {
- compatible = "marvell,armada-38x-uart";
+ compatible = "marvell,armada-38x-uart", "ns16550a";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
index b1b8693..e0b7c20 100644
--- a/arch/arm/boot/dts/armada-39x.dtsi
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -108,7 +108,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
@@ -119,7 +118,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
@@ -130,7 +128,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
@@ -141,7 +138,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index 30abb4b..aeccedd 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -90,7 +90,7 @@
};
internal-regs {
- sdramc@1400 {
+ sdramc: sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index df04805..4ec0ae0 100644
--- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
+++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
@@ -33,6 +33,11 @@
};
};
+&L2 {
+ arm,parity-enable;
+ marvell,ecc-enable;
+};
+
&devbus_bootcs {
status = "okay";
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index ee15c77..6c19984 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -36,7 +36,7 @@
};
internal-regs {
- sdramc@1400 {
+ sdramc: sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index c9d88c9..8bec21e 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -40,6 +40,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+ spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
};
};
@@ -50,6 +51,7 @@
status = "okay";
m25p,fast-read;
label = "pnor";
+ spi-max-frequency = <100000000>;
};
};
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index 9870553..8d0f465 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -55,6 +55,9 @@
phy-mode = "rgmii";
phy-handle = <ðphy1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default>;
};
&mac2 {
@@ -62,6 +65,9 @@
phy-mode = "rgmii";
phy-handle = <ðphy2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii3_default>;
};
&mac3 {
@@ -69,12 +75,145 @@
phy-mode = "rgmii";
phy-handle = <ðphy3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii4_default>;
};
-&emmc {
+&emmc_controller {
status = "okay";
};
+&emmc {
+ non-removable;
+ bus-width = <4>;
+ max-frequency = <52000000>;
+};
+
&rtc {
status = "okay";
};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0xe0000>; // 896KB
+ label = "u-boot";
+ };
+
+ u-boot-env@e0000 {
+ reg = <0xe0000 0x20000>; // 128KB
+ label = "u-boot-env";
+ };
+
+ kernel@100000 {
+ reg = <0x100000 0x900000>; // 9MB
+ label = "kernel";
+ };
+
+ rofs@a00000 {
+ reg = <0xa00000 0x2000000>; // 32MB
+ label = "rofs";
+ };
+
+ rwfs@6000000 {
+ reg = <0x2a00000 0x1600000>; // 22MB
+ label = "rwfs";
+ };
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&uart5 {
+ // Workaround for A0
+ compatible = "snps,dw-apb-uart";
+};
+
+&i2c0 {
+ status = "okay";
+
+ temp@2e {
+ compatible = "adi,adt7490";
+ reg = <0x2e>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&fsim0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
new file mode 100644
index 0000000..60ba86f
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 AMD Inc.
+// Author: Supreeth Venkatesh <supreeth.venkatesh@amd.com>
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "AMD EthanolX BMC";
+ compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+ aliases {
+ serial0 = &uart1;
+ serial4 = &uart5;
+ };
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+ leds {
+ compatible = "gpio-leds";
+
+ fault {
+ gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ identify {
+ gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
+ };
+ };
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ #include "openbmc-flash-layout.dtsi"
+ };
+};
+
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
+};
+
+&uart1 {
+ //Host Console
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&uart5 {
+ //BMC Console
+ status = "okay";
+};
+
+&adc {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default
+ &pinctrl_adc1_default
+ &pinctrl_adc2_default
+ &pinctrl_adc3_default
+ &pinctrl_adc4_default>;
+};
+
+//APML for P0
+&i2c0 {
+ status = "okay";
+};
+
+//APML for P1
+&i2c1 {
+ status = "okay";
+};
+
+// Thermal Sensors
+&i2c7 {
+ status = "okay";
+
+ lm75a@48 {
+ compatible = "national,lm75a";
+ reg = <0x48>;
+ };
+
+ lm75a@49 {
+ compatible = "national,lm75a";
+ reg = <0x49>;
+ };
+
+ lm75a@4a {
+ compatible = "national,lm75a";
+ reg = <0x4a>;
+ };
+
+ lm75a@4b {
+ compatible = "national,lm75a";
+ reg = <0x4b>;
+ };
+
+ lm75a@4c {
+ compatible = "national,lm75a";
+ reg = <0x4c>;
+ };
+
+ lm75a@4d {
+ compatible = "national,lm75a";
+ reg = <0x4d>;
+ };
+
+ lm75a@4e {
+ compatible = "national,lm75a";
+ reg = <0x4e>;
+ };
+
+ lm75a@4f {
+ compatible = "national,lm75a";
+ reg = <0x4f>;
+ };
+};
+
+&kcs1 {
+ status = "okay";
+ kcs_addr = <0x60>;
+};
+
+&kcs2 {
+ status = "okay";
+ kcs_addr = <0x62>;
+};
+
+&kcs4 {
+ status = "okay";
+ kcs_addr = <0x97DE>;
+};
+
+&lpc_snoop {
+ status = "okay";
+ snoop-ports = <0x80>;
+};
+
+&lpc_ctrl {
+ //Enable lpc clock
+ status = "okay";
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm2_default
+ &pinctrl_pwm3_default
+ &pinctrl_pwm4_default
+ &pinctrl_pwm5_default
+ &pinctrl_pwm6_default
+ &pinctrl_pwm7_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan@2 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan@3 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan@4 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan@5 {
+ reg = <0x05>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan@6 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan@7 {
+ reg = <0x07>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+};
+
+
+
diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
index 521afbe..2c29ac0 100644
--- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
@@ -92,6 +92,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii2_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>,
+ <&syscon ASPEED_CLK_MAC2RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
index d519d30..2fb8b14 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts
@@ -2,7 +2,7 @@
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
-#include "aspeed-g5.dtsi"
+#include "ast2500-facebook-netbmc-common.dtsi"
/ {
model = "Facebook Backpack CMM BMC";
@@ -19,8 +19,8 @@
serial3 = &uart4;
/*
- * Hardcode the bus number of i2c switches' channels to
- * avoid breaking the legacy applications.
+ * PCA9548 (1-0077) provides 8 channels for connecting to
+ * 4 Line Cards and 4 Fabric Cards.
*/
i2c16 = &imux16;
i2c17 = &imux17;
@@ -30,6 +30,11 @@
i2c21 = &imux21;
i2c22 = &imux22;
i2c23 = &imux23;
+
+ /*
+ * PCA9548 (2-0071) provides 8 channels for connecting to
+ * Power Distribution Board.
+ */
i2c24 = &imux24;
i2c25 = &imux25;
i2c26 = &imux26;
@@ -38,6 +43,11 @@
i2c29 = &imux29;
i2c30 = &imux30;
i2c31 = &imux31;
+
+ /*
+ * PCA9548 (8-0077) provides 8 channels and the first 4
+ * channels are connecting to 4 Fan Control Boards.
+ */
i2c32 = &imux32;
i2c33 = &imux33;
i2c34 = &imux34;
@@ -46,6 +56,226 @@
i2c37 = &imux37;
i2c38 = &imux38;
i2c39 = &imux39;
+
+ /*
+ * 2 PCA9548 (18-0070 & 18-0073), 16 channels connecting
+ * to Line Card #1.
+ */
+ i2c40 = &imux40;
+ i2c41 = &imux41;
+ i2c42 = &imux42;
+ i2c43 = &imux43;
+ i2c44 = &imux44;
+ i2c45 = &imux45;
+ i2c46 = &imux46;
+ i2c47 = &imux47;
+ i2c48 = &imux48;
+ i2c49 = &imux49;
+ i2c50 = &imux50;
+ i2c51 = &imux51;
+ i2c52 = &imux52;
+ i2c53 = &imux53;
+ i2c54 = &imux54;
+ i2c55 = &imux55;
+
+ /*
+ * 2 PCA9548 (19-0070 & 19-0073), 16 channels connecting
+ * to Line Card #2.
+ */
+ i2c56 = &imux56;
+ i2c57 = &imux57;
+ i2c58 = &imux58;
+ i2c59 = &imux59;
+ i2c60 = &imux60;
+ i2c61 = &imux61;
+ i2c62 = &imux62;
+ i2c63 = &imux63;
+ i2c64 = &imux64;
+ i2c65 = &imux65;
+ i2c66 = &imux66;
+ i2c67 = &imux67;
+ i2c68 = &imux68;
+ i2c69 = &imux69;
+ i2c70 = &imux70;
+ i2c71 = &imux71;
+
+ /*
+ * 2 PCA9548 (20-0070 & 20-0073), 16 channels connecting
+ * to Line Card #3.
+ */
+ i2c72 = &imux72;
+ i2c73 = &imux73;
+ i2c74 = &imux74;
+ i2c75 = &imux75;
+ i2c76 = &imux76;
+ i2c77 = &imux77;
+ i2c78 = &imux78;
+ i2c79 = &imux79;
+ i2c80 = &imux80;
+ i2c81 = &imux81;
+ i2c82 = &imux82;
+ i2c83 = &imux83;
+ i2c84 = &imux84;
+ i2c85 = &imux85;
+ i2c86 = &imux86;
+ i2c87 = &imux87;
+
+ /*
+ * 2 PCA9548 (21-0070 & 21-0073), 16 channels connecting
+ * to Line Card #4.
+ */
+ i2c88 = &imux88;
+ i2c89 = &imux89;
+ i2c90 = &imux90;
+ i2c91 = &imux91;
+ i2c92 = &imux92;
+ i2c93 = &imux93;
+ i2c94 = &imux94;
+ i2c95 = &imux95;
+ i2c96 = &imux96;
+ i2c97 = &imux97;
+ i2c98 = &imux98;
+ i2c99 = &imux99;
+ i2c100 = &imux100;
+ i2c101 = &imux101;
+ i2c102 = &imux102;
+ i2c103 = &imux103;
+
+ /*
+ * 2 PCA9548 (16-0070 & 16-0073), 16 channels connecting
+ * to Fabric Card #1.
+ */
+ i2c104 = &imux104;
+ i2c105 = &imux105;
+ i2c106 = &imux106;
+ i2c107 = &imux107;
+ i2c108 = &imux108;
+ i2c109 = &imux109;
+ i2c110 = &imux110;
+ i2c111 = &imux111;
+ i2c112 = &imux112;
+ i2c113 = &imux113;
+ i2c114 = &imux114;
+ i2c115 = &imux115;
+ i2c116 = &imux116;
+ i2c117 = &imux117;
+ i2c118 = &imux118;
+ i2c119 = &imux119;
+
+ /*
+ * 2 PCA9548 (17-0070 & 17-0073), 16 channels connecting
+ * to Fabric Card #2.
+ */
+ i2c120 = &imux120;
+ i2c121 = &imux121;
+ i2c122 = &imux122;
+ i2c123 = &imux123;
+ i2c124 = &imux124;
+ i2c125 = &imux125;
+ i2c126 = &imux126;
+ i2c127 = &imux127;
+ i2c128 = &imux128;
+ i2c129 = &imux129;
+ i2c130 = &imux130;
+ i2c131 = &imux131;
+ i2c132 = &imux132;
+ i2c133 = &imux133;
+ i2c134 = &imux134;
+ i2c135 = &imux135;
+
+ /*
+ * 2 PCA9548 (22-0070 & 22-0073), 16 channels connecting
+ * to Fabric Card #3.
+ */
+ i2c136 = &imux136;
+ i2c137 = &imux137;
+ i2c138 = &imux138;
+ i2c139 = &imux139;
+ i2c140 = &imux140;
+ i2c141 = &imux141;
+ i2c142 = &imux142;
+ i2c143 = &imux143;
+ i2c144 = &imux144;
+ i2c145 = &imux145;
+ i2c146 = &imux146;
+ i2c147 = &imux147;
+ i2c148 = &imux148;
+ i2c149 = &imux149;
+ i2c150 = &imux150;
+ i2c151 = &imux151;
+
+ /*
+ * 2 PCA9548 (23-0070 & 23-0073), 16 channels connecting
+ * to Fabric Card #4.
+ */
+ i2c152 = &imux152;
+ i2c153 = &imux153;
+ i2c154 = &imux154;
+ i2c155 = &imux155;
+ i2c156 = &imux156;
+ i2c157 = &imux157;
+ i2c158 = &imux158;
+ i2c159 = &imux159;
+ i2c160 = &imux160;
+ i2c161 = &imux161;
+ i2c162 = &imux162;
+ i2c163 = &imux163;
+ i2c164 = &imux164;
+ i2c165 = &imux165;
+ i2c166 = &imux166;
+ i2c167 = &imux167;
+
+ /*
+ * PCA9548 (32-0070), 8 channels connecting to Fan Control
+ # Board #1.
+ */
+ i2c168 = &imux168;
+ i2c169 = &imux169;
+ i2c170 = &imux170;
+ i2c171 = &imux171;
+ i2c172 = &imux172;
+ i2c173 = &imux173;
+ i2c174 = &imux174;
+ i2c175 = &imux175;
+
+ /*
+ * PCA9548 (33-0070), 8 channels connecting to Fan Control
+ # Board #2.
+ */
+ i2c176 = &imux176;
+ i2c177 = &imux177;
+ i2c178 = &imux178;
+ i2c179 = &imux179;
+ i2c180 = &imux180;
+ i2c181 = &imux181;
+ i2c182 = &imux182;
+ i2c183 = &imux183;
+
+ /*
+ * PCA9548 (34-0070), 8 channels connecting to Fan Control
+ # Board #3.
+ */
+ i2c184 = &imux184;
+ i2c185 = &imux185;
+ i2c186 = &imux186;
+ i2c187 = &imux187;
+ i2c188 = &imux188;
+ i2c189 = &imux189;
+ i2c190 = &imux190;
+ i2c191 = &imux191;
+
+ /*
+ * PCA9548 (35-0070), 8 channels connecting to Fan Control
+ # Board #4.
+ */
+ i2c192 = &imux192;
+ i2c193 = &imux193;
+ i2c194 = &imux194;
+ i2c195 = &imux195;
+ i2c196 = &imux196;
+ i2c197 = &imux197;
+ i2c198 = &imux198;
+ i2c199 = &imux199;
};
chosen {
@@ -53,10 +283,6 @@
bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk";
};
- memory@80000000 {
- reg = <0x80000000 0x20000000>;
- };
-
ast-adc-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
@@ -64,39 +290,7 @@
};
};
-&pinctrl {
- aspeed,external-nodes = <&gfx &lhc>;
-};
-
-/*
- * Update reset type to "system" (full chip) to fix warm reboot hang issue
- * when reset type is set to default ("soc", gated by reset mask registers).
- */
-&wdt1 {
- status = "okay";
- aspeed,reset-type = "system";
-};
-
-/*
- * wdt2 is not used by Backpack CMM.
- */
-&wdt2 {
- status = "disabled";
-};
-
-&fmc {
- status = "okay";
- flash@0 {
- status = "okay";
- m25p,fast-read;
- label = "bmc";
-#include "facebook-bmc-flash-layout.dtsi"
- };
-};
-
&uart1 {
- status = "okay";
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_ncts1_default
@@ -107,8 +301,6 @@
};
&uart3 {
- status = "okay";
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default
&pinctrl_rxd3_default
&pinctrl_ncts3_default
@@ -123,17 +315,6 @@
&pinctrl_rxd4_default>;
};
-&uart5 {
- status = "okay";
-};
-
-&mac1 {
- status = "okay";
- no-hw-checksum;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
-};
-
/*
* I2C bus reserved for communication with COM-E.
*/
@@ -152,53 +333,846 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x77>;
+ i2c-mux-idle-disconnect;
+ /* To Fabric Card #1 */
imux16: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux104: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux105: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux106: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux107: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux108: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux109: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux110: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux111: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+
+ i2c-switch@73 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x73>;
+ i2c-mux-idle-disconnect;
+
+ imux112: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux113: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux114: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux115: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux116: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux117: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux118: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux119: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
+ /* To Fabric Card #2 */
imux17: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux120: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux121: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux122: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux123: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux124: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux125: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux126: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux127: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+
+ i2c-switch@73 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x73>;
+ i2c-mux-idle-disconnect;
+
+ imux128: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux129: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux130: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux131: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux132: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux133: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux134: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux135: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
+ /* To Line Card #1 */
imux18: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux40: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux41: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux42: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux43: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux44: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux45: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux46: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux47: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+
+ i2c-switch@73 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x73>;
+ i2c-mux-idle-disconnect;
+
+ imux48: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux49: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux50: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux51: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux52: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux53: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux54: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux55: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
+ /* To Line Card #2 */
imux19: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux56: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux57: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux58: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux59: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux60: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux61: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux62: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux63: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+
+ i2c-switch@73 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x73>;
+ i2c-mux-idle-disconnect;
+
+ imux64: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux65: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux66: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux67: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux68: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux69: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux70: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux71: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
+ /* To LC3 SCM */
imux20: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux72: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux73: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux74: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux75: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux76: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux77: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux78: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux79: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+
+ i2c-switch@73 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x73>;
+ i2c-mux-idle-disconnect;
+
+ imux80: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux81: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux82: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux83: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux84: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux85: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux86: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux87: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
+ /* To Line Card #4 */
imux21: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux88: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux89: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux90: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux91: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux92: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux93: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux94: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux95: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+
+ i2c-switch@73 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x73>;
+ i2c-mux-idle-disconnect;
+
+ imux96: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux97: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux98: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux99: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux100: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux101: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux102: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux103: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
+ /* To Fabric Card #3 */
imux22: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux136: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux137: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux138: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux139: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux140: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux141: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux142: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux143: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+
+ i2c-switch@73 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x73>;
+ i2c-mux-idle-disconnect;
+
+ imux144: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux145: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux146: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux147: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux148: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux149: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux150: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux151: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
+ /* To Fabric Card #4 */
imux23: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux152: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux153: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux154: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux155: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux156: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux157: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux158: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux159: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+
+ i2c-switch@73 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x73>;
+ i2c-mux-idle-disconnect;
+
+ imux160: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux161: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux162: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux163: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux164: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux165: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux166: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux167: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
};
};
@@ -214,6 +1188,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
+ i2c-mux-idle-disconnect;
imux24: i2c@0 {
#address-cells = <1>;
@@ -301,7 +1276,7 @@
};
/*
- * I2C bus to Fan Control Board.
+ * I2C bus to Fan Control Boards.
*/
&i2c8 {
status = "okay";
@@ -311,29 +1286,230 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x77>;
+ i2c-mux-idle-disconnect;
+ /* To Fan Control Board #1 */
imux32: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux168: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux169: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux170: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux171: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux172: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux173: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux174: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux175: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
+ /* To Fan Control Board #2 */
imux33: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux176: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux177: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux178: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux179: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux180: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux181: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux182: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux183: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
+ /* To Fan Control Board #3 */
imux34: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux184: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux185: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux186: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux187: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux188: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux189: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux190: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux191: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
+ /* To Fan Control Board #4 */
imux35: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux192: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ imux193: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ imux194: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ imux195: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ imux196: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ imux197: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ imux198: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ imux199: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
};
imux36: i2c@4 {
@@ -380,3 +1556,35 @@
&ehci1 {
status = "okay";
};
+
+&vhub {
+ status = "disabled";
+};
+
+&sdhci0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd1_default>;
+};
+
+&sdhci1 {
+ status = "disabled";
+};
+
+&fmc_flash0 {
+#include "facebook-bmc-flash-layout.dtsi"
+};
+
+&fmc_flash1 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash1@0 {
+ reg = <0x0 0x2000000>;
+ label = "flash1";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts
index c054782..c34741d 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts
@@ -2,7 +2,7 @@
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
-#include "aspeed-g5.dtsi"
+#include "ast2500-facebook-netbmc-common.dtsi"
/ {
model = "Facebook Minipack 100 BMC";
@@ -76,15 +76,6 @@
stdout-path = &uart1;
bootargs = "debug console=ttyS1,9600n8 root=/dev/ram rw";
};
-
- memory@80000000 {
- reg = <0x80000000 0x20000000>;
- };
-};
-
-&wdt1 {
- status = "okay";
- aspeed,reset-type = "system";
};
&wdt2 {
@@ -92,19 +83,72 @@
aspeed,reset-type = "system";
};
-&fmc {
- status = "okay";
- flash@0 {
- status = "okay";
- m25p,fast-read;
- label = "bmc";
-#include "facebook-bmc-flash-layout.dtsi"
+/*
+ * Both firmware flashes are 64MB on Minipack BMC.
+ */
+&fmc_flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * u-boot partition: 384KB.
+ */
+ u-boot@0 {
+ reg = <0x0 0x60000>;
+ label = "u-boot";
+ };
+
+ /*
+ * u-boot environment variables: 128KB.
+ */
+ u-boot-env@60000 {
+ reg = <0x60000 0x20000>;
+ label = "env";
+ };
+
+ /*
+ * FIT image: 59.5 MB.
+ */
+ fit@80000 {
+ reg = <0x80000 0x3b80000>;
+ label = "fit";
+ };
+
+ /*
+ * "data0" partition (4MB) is reserved for persistent
+ * data store.
+ */
+ data0@3800000 {
+ reg = <0x3c00000 0x400000>;
+ label = "data0";
+ };
+
+ /*
+ * "flash0" partition (covering the entire flash) is
+ * explicitly created to avoid breaking legacy applications.
+ */
+ flash0@0 {
+ reg = <0x0 0x4000000>;
+ label = "flash0";
+ };
+ };
+};
+
+&fmc_flash1 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash1@0 {
+ reg = <0x0 0x4000000>;
+ };
};
};
&uart1 {
- status = "okay";
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_ncts1_default
@@ -120,13 +164,6 @@
&pinctrl_rxd2_default>;
};
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_txd3_default
- &pinctrl_rxd3_default>;
-};
-
&uart4 {
status = "okay";
pinctrl-names = "default";
@@ -134,17 +171,6 @@
&pinctrl_rxd4_default>;
};
-&uart5 {
- status = "okay";
-};
-
-&mac1 {
- status = "okay";
- no-hw-checksum;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
-};
-
&i2c0 {
status = "okay";
bus-frequency = <400000>;
@@ -423,7 +449,3 @@
&i2c13 {
status = "okay";
};
-
-&vhub {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
index c58230f..e6ad821 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
@@ -5,6 +5,7 @@
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
/ {
model = "Facebook TiogaPass BMC";
@@ -107,13 +108,76 @@
&kcs2 {
// BMC KCS channel 2
status = "okay";
- kcs_addr = <0xca8>;
+ aspeed,lpc-io-reg = <0xca8>;
};
&kcs3 {
// BMC KCS channel 3
status = "okay";
- kcs_addr = <0xca2>;
+ aspeed,lpc-io-reg = <0xca2>;
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names =
+ /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","",
+ /*B0-B7*/ "","BMC_DEBUG_EN","","","","BMC_PPIN","PS_PWROK",
+ "IRQ_PVDDQ_GHJ_VRHOT_LVT3",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "BIOS_MRC_DEBUG_MSG_DIS","BOARD_REV_ID0","",
+ "BOARD_REV_ID1","IRQ_DIMM_SAVE_LVT3","BOARD_REV_ID2",
+ "CPU_ERR0_LVT3_BMC","CPU_ERR1_LVT3_BMC",
+ /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON",
+ "POWER_OUT","NMI_BUTTON","","CPU0_PROCHOT_LVT3_ BMC",
+ "CPU1_PROCHOT_LVT3_ BMC",
+ /*F0-F7*/ "IRQ_PVDDQ_ABC_VRHOT_LVT3","",
+ "IRQ_PVCCIN_CPU0_VRHOT_LVC3",
+ "IRQ_PVCCIN_CPU1_VRHOT_LVC3",
+ "IRQ_PVDDQ_KLM_VRHOT_LVT3","","P3VBAT_BRIDGE_EN","",
+ /*G0-G7*/ "CPU_ERR2_LVT3","CPU_CATERR_LVT3","PCH_BMC_THERMTRIP",
+ "CPU0_SKTOCC_LVT3","","","","BIOS_SMI_ACTIVE",
+ /*H0-H7*/ "LED_POST_CODE_0","LED_POST_CODE_1","LED_POST_CODE_2",
+ "LED_POST_CODE_3","LED_POST_CODE_4","LED_POST_CODE_5",
+ "LED_POST_CODE_6","LED_POST_CODE_7",
+ /*I0-I7*/ "CPU0_FIVR_FAULT_LVT3","CPU1_FIVR_FAULT_LVT3",
+ "FORCE_ADR","UV_ADR_TRIGGER_EN","","","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "IRQ_UV_DETECT","IRQ_OC_DETECT","HSC_TIMER_EXP","",
+ "MEM_THERM_EVENT_PCH","PMBUS_ALERT_BUF_EN","","",
+ /*M0-M7*/ "CPU0_RC_ERROR","CPU1_RC_ERROR","","OC_DETECT_EN",
+ "CPU0_THERMTRIP_LATCH_LVT3",
+ "CPU1_THERMTRIP_LATCH_LVT3","","",
+ /*N0-N7*/ "","","","CPU_MSMI_LVT3","","BIOS_SPI_BMC_CTRL","","",
+ /*O0-O7*/ "","","","","","","","",
+ /*P0-P7*/ "BOARD_SKU_ID0","BOARD_SKU_ID1","BOARD_SKU_ID2",
+ "BOARD_SKU_ID3","BOARD_SKU_ID4","BMC_PREQ",
+ "BMC_PWR_DEBUG","RST_RSMRST",
+ /*Q0-Q7*/ "","","","","UARTSW_LSB","UARTSW_MSB",
+ "POST_CARD_PRES_BMC","PE_BMC_WAKE",
+ /*R0-R7*/ "","","BMC_TCK_MUX_SEL","BMC_PRDY",
+ "BMC_XDP_PRSNT_IN","RST_BMC_PLTRST_BUF","SLT_CFG0",
+ "SLT_CFG1",
+ /*S0-S7*/ "THROTTLE","BMC_READY","","HSC_SMBUS_SWITCH_EN","",
+ "","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","BMC_FAULT","","",
+ /*V0-V7*/ "","","","FAST_PROCHOT_EN","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","GLOBAL_RST_WARN",
+ "CPU0_MEMABC_MEMHOT_LVT3_BMC",
+ "CPU0_MEMDEF_MEMHOT_LVT3_BMC",
+ "CPU1_MEMGHJ_MEMHOT_LVT3_BMC",
+ "CPU1_MEMKLM_MEMHOT_LVT3_BMC",
+ /*Y0-Y7*/ "SIO_S3","SIO_S5","BMC_JTAG_SEL","SIO_ONCONTROL","",
+ "","","",
+ /*Z0-Z7*/ "","SIO_POWER_GOOD","IRQ_PVDDQ_DEF_VRHOT_LVT3","",
+ "","","","",
+ /*AA0-AA7*/ "CPU1_SKTOCC_LVT3","IRQ_SML1_PMBUS_ALERT",
+ "SERVER_POWER_LED","","PECI_MUX_SELECT","UV_HIGH_SET",
+ "","POST_COMPLETE",
+ /*AB0-AB7*/ "IRQ_HSC_FAULT","OCP_MEZZA_PRES","","","","","","",
+ /*AC0-AC7*/ "","","","","","","","";
};
&mac0 {
@@ -121,6 +185,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
@@ -360,6 +427,11 @@
&i2c4 {
status = "okay";
// BMC Debug Header
+ ipmb0@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
};
&i2c5 {
@@ -441,6 +513,11 @@
&i2c9 {
status = "okay";
//USB Debug Connector
+ ipmb0@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
};
&pwm_tacho {
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts
index b1e10f0..322587b 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts
@@ -76,7 +76,6 @@
&mac1 {
status = "okay";
- no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
index aaa77a5..8c426ba 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
@@ -27,6 +27,11 @@
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
+
+ ast-adc-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>;
+ };
};
&wdt1 {
@@ -43,7 +48,7 @@
flash@0 {
status = "okay";
m25p,fast-read;
- label = "fmc0";
+ label = "spi0.0";
#include "facebook-bmc-flash-layout.dtsi"
};
};
@@ -66,7 +71,8 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd4_default
- &pinctrl_rxd4_default>;
+ &pinctrl_rxd4_default
+ &pinctrl_ndts4_default>;
};
&uart5 {
@@ -75,7 +81,6 @@
&mac1 {
status = "okay";
- no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
@@ -116,14 +121,6 @@
status = "okay";
};
-&i2c9 {
- status = "okay";
-};
-
-&i2c10 {
- status = "okay";
-};
-
&i2c11 {
status = "okay";
};
@@ -132,10 +129,39 @@
status = "okay";
};
-&i2c13 {
+&vhub {
status = "okay";
};
-&vhub {
+&adc {
status = "okay";
};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default
+ &pinctrl_pwm1_default
+ &pinctrl_pwm6_default
+ &pinctrl_pwm7_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>;
+ };
+
+ fan@6 {
+ reg = <0x06>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>;
+ };
+
+ fan@7 {
+ reg = <0x07>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>;
+ };
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts
new file mode 100644
index 0000000..ad1fcad
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2019 Facebook Inc.
+/dts-v1/;
+
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include "ast2500-facebook-netbmc-common.dtsi"
+
+/ {
+ model = "Facebook Wedge 400 BMC";
+ compatible = "facebook,wedge400-bmc", "aspeed,ast2500";
+
+ aliases {
+ /*
+ * PCA9548 (2-0070) provides 8 channels connecting to
+ * SCM (System Controller Module).
+ */
+ i2c16 = &imux16;
+ i2c17 = &imux17;
+ i2c18 = &imux18;
+ i2c19 = &imux19;
+ i2c20 = &imux20;
+ i2c21 = &imux21;
+ i2c22 = &imux22;
+ i2c23 = &imux23;
+
+ /*
+ * PCA9548 (8-0070) provides 8 channels connecting to
+ * SMB (Switch Main Board).
+ */
+ i2c24 = &imux24;
+ i2c25 = &imux25;
+ i2c26 = &imux26;
+ i2c27 = &imux27;
+ i2c28 = &imux28;
+ i2c29 = &imux29;
+ i2c30 = &imux30;
+ i2c31 = &imux31;
+
+ /*
+ * PCA9548 (11-0076) provides 8 channels connecting to
+ * FCM (Fan Controller Module).
+ */
+ i2c32 = &imux32;
+ i2c33 = &imux33;
+ i2c34 = &imux34;
+ i2c35 = &imux35;
+ i2c36 = &imux36;
+ i2c37 = &imux37;
+ i2c38 = &imux38;
+ i2c39 = &imux39;
+
+ spi2 = &spi_gpio;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ bootargs = "console=ttyS0,9600n8 root=/dev/ram rw";
+ };
+
+ ast-adc-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
+ };
+
+ /*
+ * GPIO-based SPI Master is required to access SPI TPM, because
+ * full-duplex SPI transactions are not supported by ASPEED SPI
+ * Controllers.
+ */
+ spi_gpio: spi-gpio {
+ status = "okay";
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>;
+ gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
+ gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>;
+ gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
+ num-chipselects = <1>;
+
+ tpmdev@0 {
+ compatible = "tcg,tpm_tis-spi";
+ spi-max-frequency = <33000000>;
+ reg = <0>;
+ };
+ };
+};
+
+/*
+ * Both firmware flashes are 128MB on Wedge400 BMC.
+ */
+&fmc_flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * u-boot partition: 384KB.
+ */
+ u-boot@0 {
+ reg = <0x0 0x60000>;
+ label = "u-boot";
+ };
+
+ /*
+ * u-boot environment variables: 128KB.
+ */
+ u-boot-env@60000 {
+ reg = <0x60000 0x20000>;
+ label = "env";
+ };
+
+ /*
+ * FIT image: 123.5 MB.
+ */
+ fit@80000 {
+ reg = <0x80000 0x7b80000>;
+ label = "fit";
+ };
+
+ /*
+ * "data0" partition (4MB) is reserved for persistent
+ * data store.
+ */
+ data0@3800000 {
+ reg = <0x7c00000 0x800000>;
+ label = "data0";
+ };
+
+ /*
+ * "flash0" partition (covering the entire flash) is
+ * explicitly created to avoid breaking legacy applications.
+ */
+ flash0@0 {
+ reg = <0x0 0x8000000>;
+ label = "flash0";
+ };
+ };
+};
+
+&fmc_flash1 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash1@0 {
+ reg = <0x0 0x8000000>;
+ label = "flash1";
+ };
+ };
+};
+
+&uart2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default
+ &pinctrl_rxd2_default>;
+};
+
+&uart4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd4_default
+ &pinctrl_rxd4_default>;
+};
+
+/*
+ * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC
+ * communication.
+ */
+&i2c0 {
+ status = "okay";
+ multi-master;
+ bus-frequency = <1000000>;
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux16: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ imux17: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ imux18: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ imux19: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ imux20: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ imux21: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ imux22: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ imux23: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+
+ i2c-switch@70 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x70>;
+ i2c-mux-idle-disconnect;
+
+ imux24: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ imux25: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ imux26: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ imux27: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ imux28: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ imux29: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ imux30: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ imux31: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+
+ };
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+
+ i2c-switch@76 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x76>;
+ i2c-mux-idle-disconnect;
+
+ imux32: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ imux33: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ imux34: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ imux35: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ imux36: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ imux37: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ imux38: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ imux39: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+
+ };
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&adc {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&sdhci1 {
+ /*
+ * DMA mode needs to be disabled to avoid conflicts with UHCI
+ * Controller in AST2500 SoC.
+ */
+ sdhci-caps-mask = <0x0 0x580000>;
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts
index 4e09a9c..5e61058 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts
@@ -2,7 +2,7 @@
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
-#include "aspeed-g5.dtsi"
+#include "ast2500-facebook-netbmc-common.dtsi"
/ {
model = "Facebook YAMP 100 BMC";
@@ -23,47 +23,6 @@
stdout-path = &uart5;
bootargs = "console=ttyS0,9600n8 root=/dev/ram rw";
};
-
- memory@80000000 {
- reg = <0x80000000 0x20000000>;
- };
-};
-
-&pinctrl {
- aspeed,external-nodes = <&gfx &lhc>;
-};
-
-/*
- * Update reset type to "system" (full chip) to fix warm reboot hang issue
- * when reset type is set to default ("soc", gated by reset mask registers).
- */
-&wdt1 {
- status = "okay";
- aspeed,reset-type = "system";
-};
-
-/*
- * wdt2 is not used by Yamp.
- */
-&wdt2 {
- status = "disabled";
-};
-
-&fmc {
- status = "okay";
- flash@0 {
- status = "okay";
- m25p,fast-read;
- label = "bmc";
-#include "facebook-bmc-flash-layout.dtsi"
- };
-};
-
-&uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_txd1_default
- &pinctrl_rxd1_default>;
};
&uart2 {
@@ -73,23 +32,18 @@
&pinctrl_rxd2_default>;
};
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_txd3_default
- &pinctrl_rxd3_default>;
-};
-
-&uart5 {
- status = "okay";
-};
-
&mac0 {
status = "okay";
use-ncsi;
- no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
+};
+
+&mac1 {
+ status = "disabled";
};
&i2c0 {
@@ -155,6 +109,19 @@
status = "okay";
};
-&vhub {
- status = "okay";
+&fmc_flash0 {
+#include "facebook-bmc-flash-layout.dtsi"
+};
+
+&fmc_flash1 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash1@0 {
+ reg = <0x0 0x2000000>;
+ label = "flash1";
+ };
+ };
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts
new file mode 100644
index 0000000..8864e9c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright (c) 2018 Facebook Inc.
+/dts-v1/;
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/i2c/i2c.h>
+
+/ {
+ model = "Facebook Yosemitev2 BMC";
+ compatible = "facebook,yosemitev2-bmc", "aspeed,ast2500";
+ aliases {
+ serial4 = &uart5;
+ };
+ chosen {
+ stdout-path = &uart5;
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ iio-hwmon {
+ // VOLATAGE SENSOR
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0> , <&adc 1> , <&adc 2> , <&adc 3> ,
+ <&adc 4> , <&adc 5> , <&adc 6> , <&adc 7> ,
+ <&adc 8> , <&adc 9> , <&adc 10>, <&adc 11> ,
+ <&adc 12> , <&adc 13> , <&adc 14> , <&adc 15> ;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ };
+};
+&uart1 {
+ // Host1 Console
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&uart2 {
+ // Host2 Console
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default
+ &pinctrl_rxd2_default>;
+
+};
+
+&uart3 {
+ // Host3 Console
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default
+ &pinctrl_rxd3_default>;
+};
+
+&uart4 {
+ // Host4 Console
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd4_default
+ &pinctrl_rxd4_default>;
+};
+
+&uart5 {
+ // BMC Console
+ status = "okay";
+};
+
+&vuart {
+ // Virtual UART
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ use-ncsi;
+ mlx,multi-host;
+};
+
+&adc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default
+ &pinctrl_adc1_default
+ &pinctrl_adc2_default
+ &pinctrl_adc3_default
+ &pinctrl_adc4_default
+ &pinctrl_adc5_default
+ &pinctrl_adc6_default
+ &pinctrl_adc7_default
+ &pinctrl_adc8_default
+ &pinctrl_adc9_default
+ &pinctrl_adc10_default
+ &pinctrl_adc11_default
+ &pinctrl_adc12_default
+ &pinctrl_adc13_default
+ &pinctrl_adc14_default
+ &pinctrl_adc15_default>;
+};
+
+&i2c1 {
+ //Host1 IPMB bus
+ status = "okay";
+ multi-master;
+ ipmb1@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+};
+
+&i2c3 {
+ //Host2 IPMB bus
+ status = "okay";
+ multi-master;
+ ipmb3@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+};
+
+&i2c5 {
+ //Host3 IPMB bus
+ status = "okay";
+ multi-master;
+ ipmb5@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+};
+
+&i2c7 {
+ //Host4 IPMB bus
+ status = "okay";
+ multi-master;
+ ipmb7@10 {
+ compatible = "ipmb-dev";
+ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+ i2c-protocol;
+ };
+};
+
+&i2c8 {
+ status = "okay";
+ //FRU EEPROM
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+ tmp421@4e {
+ //INLET TEMP
+ compatible = "ti,tmp421";
+ reg = <0x4e>;
+ };
+ //OUTLET TEMP
+ tmp421@4f {
+ compatible = "ti,tmp421";
+ reg = <0x4f>;
+ };
+};
+
+&i2c10 {
+ status = "okay";
+ //HSC
+ adm1278@40 {
+ compatible = "adi,adm1278";
+ reg = <0x40>;
+ };
+};
+
+&i2c11 {
+ status = "okay";
+ //MEZZ_TEMP_SENSOR
+ tmp421@1f {
+ compatible = "ti,tmp421";
+ reg = <0x1f>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+ //MEZZ_FRU
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+};
+
+&pwm_tacho {
+ status = "okay";
+ //FSC
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
new file mode 100644
index 0000000..5a4e137
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
@@ -0,0 +1,1137 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2019 IBM Corp.
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/leds/leds-pca955x.h>
+
+/ {
+ model = "Rainier";
+ compatible = "ibm,rainier-bmc", "aspeed,ast2600";
+
+ aliases {
+ serial4 = &uart5;
+ i2c16 = &i2c2mux0;
+ i2c17 = &i2c2mux1;
+ i2c18 = &i2c2mux2;
+ i2c19 = &i2c2mux3;
+
+ spi10 = &cfam0_spi0;
+ spi11 = &cfam0_spi1;
+ spi12 = &cfam0_spi2;
+ spi13 = &cfam0_spi3;
+ spi20 = &cfam1_spi0;
+ spi21 = &cfam1_spi1;
+ spi22 = &cfam1_spi2;
+ spi23 = &cfam1_spi3;
+ spi30 = &cfam2_spi0;
+ spi31 = &cfam2_spi1;
+ spi32 = &cfam2_spi2;
+ spi33 = &cfam2_spi3;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@B8000000 {
+ no-map;
+ reg = <0xB8000000 0x04000000>; /* 64M */
+ };
+
+ vga_memory: region@bf000000 {
+ no-map;
+ compatible = "shared-dma-pool";
+ reg = <0xbf000000 0x01000000>; /* 16M */
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ ps0-presence {
+ label = "ps0-presence";
+ gpios = <&gpio0 ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(S, 0)>;
+ };
+
+ ps1-presence {
+ label = "ps1-presence";
+ gpios = <&gpio0 ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(S, 1)>;
+ };
+
+ ps2-presence {
+ label = "ps2-presence";
+ gpios = <&gpio0 ASPEED_GPIO(S, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(S, 2)>;
+ };
+
+ ps3-presence {
+ label = "ps3-presence";
+ gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(S, 3)>;
+ };
+ };
+
+ i2c2mux: i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ i2c-parent = <&i2c2>;
+ mux-gpios = <&gpio0 ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>,
+ <&gpio0 ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
+ idle-state = <0>;
+
+ i2c2mux0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c2mux1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c2mux2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c2mux3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gpio0 {
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "","","","","","","checkstop","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "","","","","","","","",
+ /*F0-F7*/ "","","","","","","","",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "","","","","","","","",
+ /*O0-O7*/ "","","","usb-power","","","","",
+ /*P0-P7*/ "","","","","","","","",
+ /*Q0-Q7*/ "cfam-reset","","","","","","","",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3",
+ "","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","";
+
+ pin_mclr_vpp {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(P, 7) GPIO_OPEN_DRAIN>;
+ output-high;
+ line-name = "mclr_vpp";
+ };
+
+ i2c3_mux_oe_n {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(G, 6) GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "I2C3_MUX_OE_N";
+ };
+};
+
+&emmc_controller {
+ status = "okay";
+};
+
+&pinctrl_emmc_default {
+ bias-disable;
+};
+
+&emmc {
+ status = "okay";
+};
+
+&fsim0 {
+ status = "okay";
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /*
+ * CFAM Reset is supposed to be active low but pass1 hardware is wired
+ * active high.
+ */
+ cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
+
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <0>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ fsi2spi@1c00 {
+ compatible = "ibm,fsi2spi";
+ reg = <0x1c00 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam0_spi0: spi@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam0_spi1: spi@20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam0_spi2: spi@40 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam0_spi3: spi@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ0: occ {
+ compatible = "ibm,p10-occ";
+ };
+ };
+
+ fsi_hub0: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ no-scan-on-init;
+ };
+ };
+};
+
+&fsi_hub0 {
+ cfam@1,0 {
+ reg = <1 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <1>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ fsi2spi@1c00 {
+ compatible = "ibm,fsi2spi";
+ reg = <0x1c00 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam1_spi0: spi@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam1_spi1: spi@20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam1_spi2: spi@40 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam1_spi3: spi@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ1: occ {
+ compatible = "ibm,p10-occ";
+ };
+ };
+
+ fsi_hub1: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ no-scan-on-init;
+ };
+ };
+
+ cfam@2,0 {
+ reg = <2 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <2>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ fsi2spi@1c00 {
+ compatible = "ibm,fsi2spi";
+ reg = <0x1c00 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam2_spi0: spi@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam2_spi1: spi@20 {
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam2_spi2: spi@40 {
+ reg = <0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ cfam2_spi3: spi@60 {
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@0 {
+ at25,byte-len = <0x80000>;
+ at25,addr-mode = <4>;
+ at25,page-size = <256>;
+
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ2: occ {
+ compatible = "ibm,p10-occ";
+ };
+ };
+
+ fsi_hub2: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ no-scan-on-init;
+ };
+ };
+};
+
+/* Legacy OCC numbering (to get rid of when userspace is fixed) */
+&fsi_occ0 {
+ reg = <1>;
+};
+
+&fsi_occ1 {
+ reg = <2>;
+};
+
+&fsi_occ2 {
+ reg = <3>;
+};
+
+&ibt {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ tca9554@40 {
+ compatible = "ti,tca9554";
+ reg = <0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ smbus0 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "smbus0";
+ };
+ };
+
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ power-supply@68 {
+ compatible = "ibm,cffps";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps";
+ reg = <0x69>;
+ };
+
+ power-supply@6a {
+ compatible = "ibm,cffps";
+ reg = <0x6a>;
+ };
+
+ power-supply@6b {
+ compatible = "ibm,cffps";
+ reg = <0x6b>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@49 {
+ compatible = "ti,tmp275";
+ reg = <0x49>;
+ };
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c64";
+ reg = <0x52>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@49 {
+ compatible = "ti,tmp275";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+};
+
+&i2c6 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+
+ tmp275@4b {
+ compatible = "ti,tmp275";
+ reg = <0x4b>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c64";
+ reg = <0x52>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c64";
+ reg = <0x53>;
+ };
+};
+
+&i2c7 {
+ multi-master;
+ status = "okay";
+
+ si7021-a20@40 {
+ compatible = "silabs,si7020";
+ reg = <0x40>;
+ };
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan@0 {
+ compatible = "pmbus-fan";
+ reg = <0>;
+ tach-pulses = <2>;
+ };
+
+ fan@1 {
+ compatible = "pmbus-fan";
+ reg = <1>;
+ tach-pulses = <2>;
+ };
+
+ fan@2 {
+ compatible = "pmbus-fan";
+ reg = <2>;
+ tach-pulses = <2>;
+ };
+
+ fan@3 {
+ compatible = "pmbus-fan";
+ reg = <3>;
+ tach-pulses = <2>;
+ };
+ };
+
+ pca0: pca9552@61 {
+ compatible = "nxp,pca9552";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ ibm-panel@62 {
+ compatible = "ibm,op-panel";
+ reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>;
+ };
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+};
+
+&i2c8 {
+ status = "okay";
+
+ ucd90320@11 {
+ compatible = "ti,ucd90320";
+ reg = <0x11>;
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ pca1: pca9552@61 {
+ compatible = "nxp,pca9552";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+};
+
+&i2c9 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ tmp423b@4d {
+ compatible = "ti,tmp423";
+ reg = <0x4d>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+};
+
+&i2c10 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ tmp423b@4d {
+ compatible = "ti,tmp423";
+ reg = <0x4d>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c128";
+ reg = <0x50>;
+ };
+};
+
+&i2c11 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@49 {
+ compatible = "ti,tmp275";
+ reg = <0x49>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+};
+
+&i2c14 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+};
+
+&i2c15 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+};
+
+&vuart1 {
+ status = "okay";
+};
+
+&vuart2 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+};
+
+&mac2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii3_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>,
+ <&syscon ASPEED_CLK_MAC3RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
+&mac3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii4_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>,
+ <&syscon ASPEED_CLK_MAC4RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&xdma {
+ status = "okay";
+ memory-region = <&vga_memory>;
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
index e9d714a..62a3ab4 100644
--- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
@@ -94,8 +94,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <1000>;
fan0-presence {
@@ -148,14 +146,48 @@
};
leds {
- compatible = "gpio-leds";
+ compatible = "gpio-leds";
- power {
- label = "power";
- /* TODO: dummy gpio */
- gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>;
- };
+ power {
+ label = "power";
+ /* TODO: dummy gpio */
+ gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+ };
+ init-ok {
+ label = "init-ok";
+ gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ front-memory {
+ label = "front-memory";
+ gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>;
+ };
+
+ front-syshot {
+ label = "front-syshot";
+ gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ front-syshealth {
+ label = "front-syshealth";
+ gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ front-fan {
+ label = "front-fan";
+ gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>;
+ };
+
+ front-psu {
+ label = "front-psu";
+ gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ identify {
+ label = "identify";
+ gpios = <&gpio ASPEED_GPIO(Z, 7) GPIO_ACTIVE_LOW>;
+ };
};
iio-hwmon-battery {
@@ -239,6 +271,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
@@ -749,15 +784,6 @@
aspeed,external-nodes = <&gfx &lhc>;
};
-&gpio {
- pin_gpio_b7 {
- gpio-hog;
- gpios = <ASPEED_GPIO(B,7) GPIO_ACTIVE_LOW>;
- output-high;
- line-name = "BMC_INIT_OK";
- };
-};
-
&wdt1 {
aspeed,reset-type = "none";
aspeed,external-signal;
diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts
index 2337ee2..80c92e0 100644
--- a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts
@@ -77,6 +77,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
index d1dbe3b..6e9baf3 100644
--- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
@@ -69,6 +69,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
index d3695a3..c29e5f4 100644
--- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts
@@ -133,6 +133,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts
index 118eb8b..084c455 100644
--- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts
@@ -139,6 +139,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts
index de95112..42b37a2 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts
@@ -178,6 +178,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
index e55cc45..cb85168 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts
@@ -8,6 +8,52 @@
model = "Mihawk BMC";
compatible = "ibm,mihawk-bmc", "aspeed,ast2500";
+ aliases {
+ i2c215 = &bus6_mux215;
+ i2c216 = &bus6_mux216;
+ i2c217 = &bus6_mux217;
+ i2c218 = &bus6_mux218;
+ i2c219 = &bus6_mux219;
+ i2c220 = &bus6_mux220;
+ i2c221 = &bus6_mux221;
+ i2c222 = &bus6_mux222;
+ i2c223 = &bus7_mux223;
+ i2c224 = &bus7_mux224;
+ i2c225 = &bus7_mux225;
+ i2c226 = &bus7_mux226;
+ i2c227 = &bus7_mux227;
+ i2c228 = &bus7_mux228;
+ i2c229 = &bus7_mux229;
+ i2c230 = &bus7_mux230;
+ i2c231 = &bus9_mux231;
+ i2c232 = &bus9_mux232;
+ i2c233 = &bus9_mux233;
+ i2c234 = &bus9_mux234;
+ i2c235 = &bus9_mux235;
+ i2c236 = &bus9_mux236;
+ i2c237 = &bus9_mux237;
+ i2c238 = &bus9_mux238;
+ i2c239 = &bus10_mux239;
+ i2c240 = &bus10_mux240;
+ i2c241 = &bus10_mux241;
+ i2c242 = &bus10_mux242;
+ i2c243 = &bus10_mux243;
+ i2c244 = &bus10_mux244;
+ i2c245 = &bus10_mux245;
+ i2c246 = &bus10_mux246;
+ i2c247 = &bus12_mux247;
+ i2c248 = &bus12_mux248;
+ i2c249 = &bus12_mux249;
+ i2c250 = &bus12_mux250;
+ i2c251 = &bus13_mux251;
+ i2c252 = &bus13_mux252;
+ i2c253 = &bus13_mux253;
+ i2c254 = &bus13_mux254;
+ i2c255 = &bus13_mux255;
+ i2c256 = &bus13_mux256;
+ i2c257 = &bus13_mux257;
+ i2c258 = &bus13_mux258;
+ };
chosen {
stdout-path = &uart5;
@@ -120,35 +166,24 @@
leds {
compatible = "gpio-leds";
- fault {
+ front-fault {
retain-state-shutdown;
default-state = "keep";
gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>;
};
- power {
+ power-button {
retain-state-shutdown;
default-state = "keep";
gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>;
};
- rear-id {
+ front-id {
retain-state-shutdown;
default-state = "keep";
gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
};
- rear-g {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>;
- };
-
- rear-ok {
- retain-state-shutdown;
- default-state = "keep";
- gpios = <&gpio ASPEED_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
- };
fan0 {
retain-state-shutdown;
@@ -449,6 +484,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
@@ -627,6 +665,54 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
+
+ bus7_mux223: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ bus7_mux224: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ bus7_mux225: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ bus7_mux226: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ bus7_mux227: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ bus7_mux228: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ bus7_mux229: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ bus7_mux230: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
};
};
@@ -641,6 +727,54 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
+
+ bus6_mux215: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ bus6_mux216: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ bus6_mux217: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ bus6_mux218: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ bus6_mux219: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ bus6_mux220: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ bus6_mux221: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ bus6_mux222: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
};
};
@@ -681,6 +815,68 @@
i2c-mux-idle-disconnect;
interrupt-controller;
#interrupt-cells = <2>;
+
+ bus9_mux231: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tca9554@39 {
+ compatible = "ti,tca9554";
+ reg = <0x39>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ smbus0 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "smbus0";
+ };
+ };
+
+ tmp431@4c {
+ compatible = "ti,tmp401";
+ reg = <0x4c>;
+ };
+ };
+
+ bus9_mux232: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tca9554@39 {
+ compatible = "ti,tca9554";
+ reg = <0x39>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ smbus1 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "smbus1";
+ };
+ };
+
+ tmp431@4c {
+ compatible = "ti,tmp401";
+ reg = <0x4c>;
+ };
+ };
+
+ bus9_mux233: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ bus9_mux234: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
};
pca9545@71 {
@@ -692,6 +888,68 @@
i2c-mux-idle-disconnect;
interrupt-controller;
#interrupt-cells = <2>;
+
+ bus9_mux235: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tca9554@39 {
+ compatible = "ti,tca9554";
+ reg = <0x39>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ smbus2 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "smbus2";
+ };
+ };
+
+ tmp431@4c {
+ compatible = "ti,tmp401";
+ reg = <0x4c>;
+ };
+ };
+
+ bus9_mux236: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tca9554@39 {
+ compatible = "ti,tca9554";
+ reg = <0x39>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ smbus3 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "smbus3";
+ };
+ };
+
+ tmp431@4c {
+ compatible = "ti,tmp401";
+ reg = <0x4c>;
+ };
+ };
+
+ bus9_mux237: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ bus9_mux238: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
};
};
@@ -722,6 +980,68 @@
i2c-mux-idle-disconnect;
interrupt-controller;
#interrupt-cells = <2>;
+
+ bus10_mux239: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tca9554@39 {
+ compatible = "ti,tca9554";
+ reg = <0x39>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ smbus4 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "smbus4";
+ };
+ };
+
+ tmp431@4c {
+ compatible = "ti,tmp401";
+ reg = <0x4c>;
+ };
+ };
+
+ bus10_mux240: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tca9554@39 {
+ compatible = "ti,tca9554";
+ reg = <0x39>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ smbus5 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "smbus5";
+ };
+ };
+
+ tmp431@4c {
+ compatible = "ti,tmp401";
+ reg = <0x4c>;
+ };
+ };
+
+ bus10_mux241: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ bus10_mux242: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
};
pca9545@71 {
@@ -733,6 +1053,68 @@
i2c-mux-idle-disconnect;
interrupt-controller;
#interrupt-cells = <2>;
+
+ bus10_mux243: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tca9554@39 {
+ compatible = "ti,tca9554";
+ reg = <0x39>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ smbus6 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "smbus6";
+ };
+ };
+
+ tmp431@4c {
+ compatible = "ti,tmp401";
+ reg = <0x4c>;
+ };
+ };
+
+ bus10_mux244: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tca9554@39 {
+ compatible = "ti,tca9554";
+ reg = <0x39>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ smbus7 {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "smbus7";
+ };
+ };
+
+ tmp431@4c {
+ compatible = "ti,tmp401";
+ reg = <0x4c>;
+ };
+ };
+
+ bus10_mux245: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ bus10_mux246: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
};
};
@@ -793,7 +1175,7 @@
interrupt-controller;
#interrupt-cells = <2>;
- i2c@0 {
+ bus12_mux247: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -804,7 +1186,7 @@
};
};
- i2c@1 {
+ bus12_mux248: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
@@ -815,7 +1197,7 @@
};
};
- i2c@2 {
+ bus12_mux249: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
@@ -826,7 +1208,7 @@
};
};
- i2c@3 {
+ bus12_mux250: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
@@ -854,6 +1236,53 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
+ bus13_mux251: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ bus13_mux252: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ bus13_mux253: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ bus13_mux254: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+
+ bus13_mux255: i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+
+ bus13_mux256: i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ bus13_mux257: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+
+ bus13_mux258: i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
};
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts
new file mode 100644
index 0000000..b648e46
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts
@@ -0,0 +1,662 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/leds/leds-pca955x.h>
+
+/ {
+ model = "Mowgli BMC";
+ compatible = "ibm,mowgli-bmc", "aspeed,ast2500";
+
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x04000000>; /* 64M */
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ video_engine_memory: jpegbuffer {
+ size = <0x02000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ air-water {
+ label = "air-water";
+ gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(F, 6)>;
+ };
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(J, 2)>;
+ };
+
+ ps0-presence {
+ label = "ps0-presence";
+ gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(Z, 2)>;
+ };
+
+ ps1-presence {
+ label = "ps1-presence";
+ gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(Z, 0)>;
+ };
+
+ id-button {
+ label = "id-button";
+ gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(F, 1)>;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <1000>;
+
+ fan0-presence {
+ label = "fan0-presence";
+ gpios = <&pca9552 9 GPIO_ACTIVE_LOW>;
+ linux,code = <9>;
+ };
+
+ fan1-presence {
+ label = "fan1-presence";
+ gpios = <&pca9552 10 GPIO_ACTIVE_LOW>;
+ linux,code = <10>;
+ };
+
+ fan2-presence {
+ label = "fan2-presence";
+ gpios = <&pca9552 11 GPIO_ACTIVE_LOW>;
+ linux,code = <11>;
+ };
+
+ fan3-presence {
+ label = "fan3-presence";
+ gpios = <&pca9552 12 GPIO_ACTIVE_LOW>;
+ linux,code = <12>;
+ };
+
+ fan4-presence {
+ label = "fan4-presence";
+ gpios = <&pca9552 13 GPIO_ACTIVE_LOW>;
+ linux,code = <13>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ front-fault {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ power-button {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ front-id {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ fan0 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca9552 0 GPIO_ACTIVE_LOW>;
+ };
+
+ fan1 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca9552 1 GPIO_ACTIVE_LOW>;
+ };
+
+ fan2 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca9552 2 GPIO_ACTIVE_LOW>;
+ };
+
+ fan3 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca9552 3 GPIO_ACTIVE_LOW>;
+ };
+
+ fan4 {
+ retain-state-shutdown;
+ default-state = "keep";
+ gpios = <&pca9552 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "fsi-master-gpio", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ no-gpio-delays;
+
+ clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ trans-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>;
+ };
+
+ iio-hwmon-12v {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 0>;
+ };
+
+ iio-hwmon-5v {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 1>;
+ };
+
+ iio-hwmon-3v {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 2>;
+ };
+
+ iio-hwmon-vdd {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 3>;
+ };
+
+ iio-hwmon-vcs {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 5>;
+ };
+
+ iio-hwmon-vdn {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 7>;
+ };
+
+ iio-hwmon-vio {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 9>;
+ };
+
+ iio-hwmon-vddra {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 11>;
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 12>;
+ };
+
+ iio-hwmon-vddrb {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 13>;
+ };
+};
+
+&pwm_tacho {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
+ &pinctrl_pwm2_default &pinctrl_pwm3_default
+ &pinctrl_pwm4_default>;
+
+ fan@0 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+ };
+
+ fan@1 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+ };
+
+ fan@2 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x02>;
+ };
+
+ fan@3 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x03>;
+ };
+
+ fan@4 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x04>;
+ };
+
+ fan@5 {
+ reg = <0x00>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x05>;
+ };
+
+ fan@6 {
+ reg = <0x01>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x06>;
+ };
+
+ fan@7 {
+ reg = <0x02>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x07>;
+ };
+
+ fan@8 {
+ reg = <0x03>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x08>;
+ };
+
+ fan@9 {
+ reg = <0x04>;
+ aspeed,fan-tach-ch = /bits/ 8 <0x09>;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ label = "bmc";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ partitions {
+ #address-cells = < 1 >;
+ #size-cells = < 1 >;
+ compatible = "fixed-partitions";
+ u-boot@0 {
+ reg = < 0 0x60000 >;
+ label = "u-boot";
+ };
+ u-boot-env@60000 {
+ reg = < 0x60000 0x20000 >;
+ label = "u-boot-env";
+ };
+ obmc-ubi@80000 {
+ reg = < 0x80000 0x1F80000 >;
+ label = "obmc-ubi";
+ };
+ };
+ };
+ flash@1 {
+ status = "okay";
+ label = "alt-bmc";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ partitions {
+ #address-cells = < 1 >;
+ #size-cells = < 1 >;
+ compatible = "fixed-partitions";
+ u-boot@0 {
+ reg = < 0 0x60000 >;
+ label = "alt-u-boot";
+ };
+ u-boot-env@60000 {
+ reg = < 0x60000 0x20000 >;
+ label = "alt-u-boot-env";
+ };
+ obmc-ubi@80000 {
+ reg = < 0x80000 0x1F80000 >;
+ label = "alt-obmc-ubi";
+ };
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ label = "pnor";
+ m25p,fast-read;
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&uart1 {
+ /* Rear RS-232 connector */
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_nri1_default>;
+};
+
+&uart2 {
+ /* APSS */
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
+&mac1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+};
+
+&i2c1 {
+ status = "disabled";
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* CPU MFG CONN */
+
+};
+
+&i2c3 {
+ status = "okay";
+
+ /* APSS */
+ /* CPLD */
+
+ /* PCA9516 (repeater) ->
+ * CLK Buffer 9FGS9092
+ * Power Supply 0
+ * Power Supply 1
+ * PCA 9552 LED
+ */
+
+ pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps1";
+ reg = <0x69>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ /* CP0 VDD & VCS : IR35221 */
+ /* CP0 VDN & VIO : IR35221 */
+ /* CP0 VDDR : IR35221 */
+
+ ir35221@28 {
+ compatible = "infineon,ir35221";
+ reg = <0x28>;
+ };
+
+ ir35221@29 {
+ compatible = "infineon,ir35221";
+ reg = <0x29>;
+ };
+
+ ir35221@2d {
+ compatible = "infineon,ir35221";
+ reg = <0x2d>;
+ };
+
+};
+
+&i2c5 {
+ status = "disabled";
+};
+
+&i2c6 {
+ status = "disabled";
+};
+
+&i2c7 {
+ status = "disabled";
+};
+
+&i2c8 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+};
+
+&i2c9 {
+ status = "okay";
+
+ /* PCIe G3 x16 slot */
+};
+
+&i2c10 {
+ status = "disabled";
+};
+
+&i2c11 {
+ status = "okay";
+
+ /* CPLD */
+ /* TPM */
+ /* RTC RX8900CE */
+ /* TMP275A */
+ /* TMP275A */
+
+ tmp275@48 {
+ compatible = "ti,tmp275";
+ reg = <0x48>;
+ };
+
+ tmp275@49 {
+ compatible = "ti,tmp275";
+ reg = <0x49>;
+ };
+
+};
+
+&i2c12 {
+ status = "disabled";
+};
+
+&i2c13 {
+ status = "disabled";
+};
+
+&vuart {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&adc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default
+ &pinctrl_adc1_default
+ &pinctrl_adc2_default
+ &pinctrl_adc3_default
+ &pinctrl_adc4_default
+ &pinctrl_adc5_default
+ &pinctrl_adc6_default
+ &pinctrl_adc7_default
+ &pinctrl_adc8_default
+ &pinctrl_adc9_default
+ &pinctrl_adc10_default
+ &pinctrl_adc11_default
+ &pinctrl_adc12_default
+ &pinctrl_adc13_default
+ &pinctrl_adc14_default
+ &pinctrl_adc15_default>;
+};
+
+&wdt1 {
+ aspeed,reset-type = "none";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+};
+
+&wdt2 {
+ aspeed,alt-boot;
+};
+
+&ibt {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+#include "ibm-power9-dual.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts
new file mode 100644
index 0000000..91dced7
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-nicole.dts
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2019 YADRO
+/dts-v1/;
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Nicole BMC";
+ compatible = "yadro,nicole-bmc", "aspeed,ast2500";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200 earlyprintk";
+ };
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vga_memory: framebuffer@9f000000 {
+ no-map;
+ reg = <0x9f000000 0x01000000>; /* 16M */
+ };
+
+ flash_memory: region@98000000 {
+ no-map;
+ reg = <0x98000000 0x04000000>; /* 64M */
+ };
+
+ coldfire_memory: codefire_memory@9ef00000 {
+ reg = <0x9ef00000 0x00100000>;
+ no-map;
+ };
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+
+ video_engine_memory: jpegbuffer {
+ size = <0x02000000>; /* 32M */
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "platform:green:power";
+ gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>;
+ };
+
+ identify {
+ label = "platform:blue:indicator";
+ gpios = <&gpio ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>;
+ };
+
+ fault {
+ label = "platform:red:fault";
+ gpios = <&gpio ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>;
+ };
+
+ attention {
+ label = "platform:yellow:alarm";
+ gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ fsi: gpio-fsi {
+ compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ no-gpio-delays;
+
+ memory-region = <&coldfire_memory>;
+ aspeed,sram = <&sram>;
+ aspeed,cvic = <&cvic>;
+
+ clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
+ data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>;
+ mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ trans-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ checkstop {
+ label = "checkstop";
+ gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(J, 2)>;
+ };
+ };
+
+ iio-hwmon-battery {
+ compatible = "iio-hwmon";
+ io-channels = <&adc 12>;
+ };
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&uart1 {
+ /* Rear RS-232 connector */
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_nri1_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&mac0 {
+ status = "okay";
+
+ use-ncsi;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ /* CPU0 characterization connector */
+};
+
+&i2c3 {
+ status = "okay";
+ /* CLK GEN SI5338 */
+};
+
+&i2c4 {
+ status = "okay";
+ /* Voltage regulators for CPU0 */
+};
+
+&i2c5 {
+ status = "okay";
+ /* Voltage regulators for CPU1 */
+};
+
+&i2c6 {
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ /* CPLD */
+};
+
+&gpio {
+ gpio-line-names =
+ /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","",
+ /*B0-B7*/ "","","","","","","","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "fsi-enable","bmc_power_up","sys_pwrok_buf",
+ "func_mode0","func_mode1","func_mode2","","",
+ /*E0-E7*/ "","ncsi_cfg","","","","","","",
+ /*F0-F7*/ "","","","","","","","",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "","","checkstop","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "","","","","","","","",
+ /*O0-O7*/ "","","power-button","","","","","",
+ /*P0-P7*/ "","fsi-trans","pm_rtc_adc_en","","","","","",
+ /*Q0-Q7*/ "","","","","","","","id-button",
+ /*R0-R7*/ "","software_pwrgood","","","","","","",
+ /*S0-S7*/ "","","","","","","","seq_cont",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","",
+ /*AA0-AA7*/ "fsi-clock","led-attention","fsi-data","led-fault",
+ "led-power","","","led-identify",
+ /*AB0-AB7*/ "","","","","","","","",
+ /*AC0-AC7*/ "","","","","","","","";
+
+ func_mode0 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ func_mode1 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ func_mode2 {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(D, 5) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ seq_cont {
+ gpio-hog;
+ gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ ncsi_cfg {
+ gpio-hog;
+ input;
+ gpios = <ASPEED_GPIO(E, 1) GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&vuart {
+ status = "okay";
+};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
+
+&pinctrl {
+ aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&ibt {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+};
+
+&adc {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_default
+ &pinctrl_adc1_default
+ &pinctrl_adc2_default
+ &pinctrl_adc3_default
+ &pinctrl_adc4_default
+ &pinctrl_adc5_default
+ &pinctrl_adc6_default
+ &pinctrl_adc7_default
+ &pinctrl_adc8_default
+ &pinctrl_adc9_default
+ &pinctrl_adc10_default
+ &pinctrl_adc11_default
+ &pinctrl_adc12_default
+ &pinctrl_adc13_default
+ &pinctrl_adc14_default
+ &pinctrl_adc15_default>;
+};
+
+&video {
+ status = "okay";
+ memory-region = <&video_engine_memory>;
+};
+
+#include "ibm-power9-dual.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index b0cb34c..eb4e93a 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -87,6 +87,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+ spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
};
};
@@ -99,6 +100,7 @@
flash@0 {
status = "okay";
m25p,fast-read;
+ spi-max-frequency = <50000000>;
label = "pnor";
};
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 9628ecb..fd2e014 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -112,6 +112,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
+ spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
};
};
@@ -125,6 +126,7 @@
status = "okay";
m25p,fast-read;
label = "pnor";
+ spi-max-frequency = <100000000>;
};
};
@@ -160,6 +162,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
};
&i2c1 {
@@ -226,23 +231,52 @@
};
&gpio {
+ gpio-line-names =
+ /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","",
+ /*B0-B7*/ "","","","","","","","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "fsi-enable","","","nic_func_mode0","nic_func_mode1","","","",
+ /*E0-E7*/ "","","","","","","","",
+ /*F0-F7*/ "","","","","","","","",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","power-button","","","","",
+ /*J0-J7*/ "","","checkstop","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "","","led-fault","",
+ "led-identify","","","",
+ /*O0-O7*/ "","","","","","","","",
+ /*P0-P7*/ "","","","","","","","",
+ /*Q0-Q7*/ "","","","","","","","id-button",
+ /*R0-R7*/ "","","fsi-trans","","","led-power","","",
+ /*S0-S7*/ "","","","","","","","seq_cont",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","",
+ /*AA0-AA7*/ "fsi-clock","","fsi-data","","","","","",
+ /*AB0-AB7*/ "","","","","","","","",
+ /*AC0-AC7*/ "","","","","","","","";
+
nic_func_mode0 {
gpio-hog;
gpios = <ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
output-low;
- line-name = "nic_func_mode0";
};
nic_func_mode1 {
gpio-hog;
gpios = <ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
output-low;
- line-name = "nic_func_mode1";
};
seq_cont {
gpio-hog;
gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
output-low;
- line-name = "seq_cont";
};
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
index f67fef1..d56b5ed 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts
@@ -82,8 +82,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <1000>;
scm0-presence {
@@ -322,6 +320,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
use-ncsi;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
};
&i2c2 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
new file mode 100644
index 0000000..0e8851c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
@@ -0,0 +1,870 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2019 IBM Corp.
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/leds/leds-pca955x.h>
+
+/ {
+ model = "Tacoma";
+ compatible = "ibm,tacoma-bmc", "aspeed,ast2600";
+
+ chosen {
+ stdout-path = &uart5;
+ bootargs = "console=ttyS4,115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flash_memory: region@b8000000 {
+ no-map;
+ reg = <0xb8000000 0x4000000>; /* 64M */
+ };
+
+ vga_memory: region@bf000000 {
+ no-map;
+ compatible = "shared-dma-pool";
+ reg = <0xbf000000 0x01000000>; /* 16M */
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ ps0-presence {
+ label = "ps0-presence";
+ gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 3)>;
+ };
+
+ ps1-presence {
+ label = "ps1-presence";
+ gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(E, 5)>;
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <1000>;
+
+ fan0-presence {
+ label = "fan0-presence";
+ gpios = <&pca0 4 GPIO_ACTIVE_LOW>;
+ linux,code = <4>;
+ };
+
+ fan1-presence {
+ label = "fan1-presence";
+ gpios = <&pca0 5 GPIO_ACTIVE_LOW>;
+ linux,code = <5>;
+ };
+
+ fan2-presence {
+ label = "fan2-presence";
+ gpios = <&pca0 6 GPIO_ACTIVE_LOW>;
+ linux,code = <6>;
+ };
+
+ fan3-presence {
+ label = "fan3-presence";
+ gpios = <&pca0 7 GPIO_ACTIVE_LOW>;
+ linux,code = <7>;
+ };
+ };
+
+ iio-hwmon-dps310 {
+ compatible = "iio-hwmon";
+ io-channels = <&dps 0>;
+ };
+
+ iio-hwmon-bmp280 {
+ compatible = "iio-hwmon";
+ io-channels = <&bmp 1>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gpio0 {
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "fsi-mux","","","","","","","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "power-button","","","checkstop","","presence-ps1","","led-rear-fault",
+ /*F0-F7*/ "","","","","","","","",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","presence-ps0","","","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "","","","","","","","",
+ /*O0-O7*/ "led-rear-power","led-rear-id","","usb-power","","","","",
+ /*P0-P7*/ "","","","","","","","",
+ /*Q0-Q7*/ "cfam-reset","","","","","","","fsi-routing",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","";
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+
+ flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "alt-bmc";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&mac2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii3_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>,
+ <&syscon ASPEED_CLK_MAC3RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
+&emmc_controller {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+ clk-phase-mmc-hs200 = <36>, <270>;
+};
+
+&fsim0 {
+ status = "okay";
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+ fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>;
+ cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+
+ cfam@0,0 {
+ reg = <0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <0>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ };
+
+ cfam0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ };
+
+ cfam0_i2c2: i2c-bus@2 {
+ reg = <2>;
+ };
+
+ cfam0_i2c3: i2c-bus@3 {
+ reg = <3>;
+ };
+
+ cfam0_i2c4: i2c-bus@4 {
+ reg = <4>;
+ };
+
+ cfam0_i2c5: i2c-bus@5 {
+ reg = <5>;
+ };
+
+ cfam0_i2c6: i2c-bus@6 {
+ reg = <6>;
+ };
+
+ cfam0_i2c7: i2c-bus@7 {
+ reg = <7>;
+ };
+
+ cfam0_i2c8: i2c-bus@8 {
+ reg = <8>;
+ };
+
+ cfam0_i2c9: i2c-bus@9 {
+ reg = <9>;
+ };
+
+ cfam0_i2c10: i2c-bus@a {
+ reg = <10>;
+ };
+
+ cfam0_i2c11: i2c-bus@b {
+ reg = <11>;
+ };
+
+ cfam0_i2c12: i2c-bus@c {
+ reg = <12>;
+ };
+
+ cfam0_i2c13: i2c-bus@d {
+ reg = <13>;
+ };
+
+ cfam0_i2c14: i2c-bus@e {
+ reg = <14>;
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ0: occ {
+ compatible = "ibm,p9-occ";
+ };
+ };
+
+ fsi_hub0: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ no-scan-on-init;
+ };
+ };
+};
+
+&fsi_hub0 {
+ cfam@1,0 {
+ reg = <1 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chip-id = <1>;
+
+ scom@1000 {
+ compatible = "ibm,fsi2pib";
+ reg = <0x1000 0x400>;
+ };
+
+ i2c@1800 {
+ compatible = "ibm,fsi-i2c-master";
+ reg = <0x1800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cfam1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ };
+
+ cfam1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ };
+
+ cfam1_i2c2: i2c-bus@2 {
+ reg = <2>;
+ };
+
+ cfam1_i2c3: i2c-bus@3 {
+ reg = <3>;
+ };
+
+ cfam1_i2c4: i2c-bus@4 {
+ reg = <4>;
+ };
+
+ cfam1_i2c5: i2c-bus@5 {
+ reg = <5>;
+ };
+
+ cfam1_i2c6: i2c-bus@6 {
+ reg = <6>;
+ };
+
+ cfam1_i2c7: i2c-bus@7 {
+ reg = <7>;
+ };
+
+ cfam1_i2c8: i2c-bus@8 {
+ reg = <8>;
+ };
+
+ cfam1_i2c9: i2c-bus@9 {
+ reg = <9>;
+ };
+
+ cfam1_i2c10: i2c-bus@a {
+ reg = <10>;
+ };
+
+ cfam1_i2c11: i2c-bus@b {
+ reg = <11>;
+ };
+
+ cfam1_i2c12: i2c-bus@c {
+ reg = <12>;
+ };
+
+ cfam1_i2c13: i2c-bus@d {
+ reg = <13>;
+ };
+
+ cfam1_i2c14: i2c-bus@e {
+ reg = <14>;
+ };
+ };
+
+ sbefifo@2400 {
+ compatible = "ibm,p9-sbefifo";
+ reg = <0x2400 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fsi_occ1: occ {
+ compatible = "ibm,p9-occ";
+ };
+ };
+
+ fsi_hub1: hub@3400 {
+ compatible = "fsi-master-hub";
+ reg = <0x3400 0x400>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ no-scan-on-init;
+ };
+ };
+};
+
+/* Legacy OCC numbering (to get rid of when userspace is fixed) */
+&fsi_occ0 {
+ reg = <1>;
+};
+
+&fsi_occ1 {
+ reg = <2>;
+};
+
+/ {
+ aliases {
+ i2c100 = &cfam0_i2c0;
+ i2c101 = &cfam0_i2c1;
+ i2c102 = &cfam0_i2c2;
+ i2c103 = &cfam0_i2c3;
+ i2c104 = &cfam0_i2c4;
+ i2c105 = &cfam0_i2c5;
+ i2c106 = &cfam0_i2c6;
+ i2c107 = &cfam0_i2c7;
+ i2c108 = &cfam0_i2c8;
+ i2c109 = &cfam0_i2c9;
+ i2c110 = &cfam0_i2c10;
+ i2c111 = &cfam0_i2c11;
+ i2c112 = &cfam0_i2c12;
+ i2c113 = &cfam0_i2c13;
+ i2c114 = &cfam0_i2c14;
+ i2c200 = &cfam1_i2c0;
+ i2c201 = &cfam1_i2c1;
+ i2c202 = &cfam1_i2c2;
+ i2c203 = &cfam1_i2c3;
+ i2c204 = &cfam1_i2c4;
+ i2c205 = &cfam1_i2c5;
+ i2c206 = &cfam1_i2c6;
+ i2c207 = &cfam1_i2c7;
+ i2c208 = &cfam1_i2c8;
+ i2c209 = &cfam1_i2c9;
+ i2c210 = &cfam1_i2c10;
+ i2c211 = &cfam1_i2c11;
+ i2c212 = &cfam1_i2c12;
+ i2c213 = &cfam1_i2c13;
+ i2c214 = &cfam1_i2c14;
+ };
+
+};
+
+&i2c0 {
+ multi-master;
+ status = "okay";
+
+ ibm-panel@62 {
+ compatible = "ibm,op-panel";
+ reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ tpm: tpm@2e {
+ compatible = "tcg,tpm-tis-i2c";
+ reg = <0x2e>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ bmp: bmp280@77 {
+ compatible = "bosch,bmp280";
+ reg = <0x77>;
+ #io-channel-cells = <1>;
+ };
+
+ max31785@52 {
+ compatible = "maxim,max31785a";
+ reg = <0x52>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fan@0 {
+ compatible = "pmbus-fan";
+ reg = <0>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@1 {
+ compatible = "pmbus-fan";
+ reg = <1>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@2 {
+ compatible = "pmbus-fan";
+ reg = <2>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+
+ fan@3 {
+ compatible = "pmbus-fan";
+ reg = <3>;
+ tach-pulses = <2>;
+ maxim,fan-rotor-input = "tach";
+ maxim,fan-pwm-freq = <25000>;
+ maxim,fan-dual-tach;
+ maxim,fan-no-watchdog;
+ maxim,fan-no-fault-ramp;
+ maxim,fan-ramp = <2>;
+ maxim,fan-fault-pin-mon;
+ };
+ };
+
+ dps: dps310@76 {
+ compatible = "infineon,dps310";
+ reg = <0x76>;
+ #io-channel-cells = <0>;
+ };
+
+ pca0: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps1";
+ reg = <0x69>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ tmp423a@4c {
+ compatible = "ti,tmp423";
+ reg = <0x4c>;
+ };
+
+ ir35221@70 {
+ compatible = "infineon,ir35221";
+ reg = <0x70>;
+ };
+
+ ir35221@71 {
+ compatible = "infineon,ir35221";
+ reg = <0x71>;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+
+ tmp275@4a {
+ compatible = "ti,tmp275";
+ reg = <0x4a>;
+ };
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+
+ pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N",
+ "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF",
+ "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF",
+ "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF",
+ "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF",
+ "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF",
+ "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF",
+ "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N";
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@1 {
+ reg = <1>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@8 {
+ reg = <8>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@9 {
+ reg = <9>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@10 {
+ reg = <10>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@11 {
+ reg = <11>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ ucd90160@64 {
+ compatible = "ti,ucd90160";
+ reg = <0x64>;
+ };
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&ibt {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+ // Workaround for A0
+ compatible = "snps,dw-apb-uart";
+};
+
+&uart5 {
+ // Workaround for A0
+ compatible = "snps,dw-apb-uart";
+};
+
+&vuart1 {
+ status = "okay";
+};
+
+&vuart2 {
+ status = "okay";
+};
+
+&lpc_ctrl {
+ status = "okay";
+ memory-region = <&flash_memory>;
+ flash = <&spi1>;
+};
+
+&wdt1 {
+ aspeed,reset-type = "none";
+ aspeed,external-signal;
+ aspeed,ext-push-pull;
+ aspeed,ext-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdtrst1_default>;
+};
+
+&wdt2 {
+ status = "okay";
+};
+
+&pinctrl {
+ /* Hog these as no driver is probed for the entire LPC block */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpc_default>,
+ <&pinctrl_lsirq_default>;
+};
+
+&xdma {
+ status = "okay";
+ memory-region = <&vga_memory>;
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index a27c88d..01074b6 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -14,7 +14,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
- memory {
+ memory@40000000 {
reg = <0x40000000 0x20000000>;
};
@@ -43,6 +43,10 @@
gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>;
};
+ power_green {
+ gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+ };
+
id_blue {
gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>;
};
@@ -103,10 +107,7 @@
&mac0 {
status = "okay";
-
use-ncsi;
- no-hw-checksum;
-
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
};
@@ -232,3 +233,16 @@
&wdt2 {
aspeed,alt-boot;
};
+
+&sdmmc {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd2_default>;
+ cd-inverted;
+ disable-wp;
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index 31ea34e..85d58a6 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -27,6 +27,12 @@
reg = <0x98000000 0x04000000>; /* 64M */
};
+ vga_memory: region@9f000000 {
+ no-map;
+ compatible = "shared-dma-pool";
+ reg = <0x9f000000 0x01000000>; /* 16M */
+ };
+
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
@@ -77,8 +83,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <1000>;
fan0-presence {
@@ -193,6 +197,40 @@
};
+&gpio {
+ gpio-line-names =
+ /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","",
+ /*B0-B7*/ "","","","","","air-water","","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "fsi-enable","","","","","","","",
+ /*E0-E7*/ "fsi-data","","","","","","","",
+ /*F0-F7*/ "","","","","","","","",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","","","",
+ /*J0-J7*/ "","","checkstop","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "presence-ps1","","led-rear-fault","led-rear-power",
+ "led-rear-id","","","",
+ /*O0-O7*/ "","","","","","","","",
+ /*P0-P7*/ "","","","","","","","presence-ps0",
+ /*Q0-Q7*/ "","","","","","","","",
+ /*R0-R7*/ "","","fsi-trans","","","power-button","","",
+ /*S0-S7*/ "","","","","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","",
+ /*AA0-AA7*/ "fsi-clock","","","","","","","",
+ /*AB0-AB7*/ "","","","","","","","",
+ /*AC0-AC7*/ "","","","","","","","";
+};
+
&fmc {
status = "okay";
@@ -200,6 +238,7 @@
status = "okay";
label = "bmc";
m25p,fast-read;
+ spi-max-frequency = <50000000>;
partitions {
#address-cells = < 1 >;
@@ -224,6 +263,7 @@
status = "okay";
label = "alt-bmc";
m25p,fast-read;
+ spi-max-frequency = <50000000>;
partitions {
#address-cells = < 1 >;
@@ -242,7 +282,6 @@
label = "alt-obmc-ubi";
};
};
-
};
};
@@ -255,6 +294,7 @@
status = "okay";
label = "pnor";
m25p,fast-read;
+ spi-max-frequency = <100000000>;
};
};
@@ -293,6 +333,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
@@ -653,4 +696,9 @@
memory-region = <&video_engine_memory>;
};
+&xdma {
+ status = "okay";
+ memory-region = <&vga_memory>;
+};
+
#include "ibm-power9-dual.dtsi"
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
index 3062437..4bcc820 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -130,6 +130,7 @@
status = "okay";
label = "bmc";
m25p,fast-read;
+ spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
};
};
@@ -143,6 +144,7 @@
status = "okay";
label = "pnor";
m25p,fast-read;
+ spi-max-frequency = <100000000>;
};
};
@@ -187,6 +189,9 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
@@ -473,32 +478,61 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpioh_unbiased>;
+ gpio-line-names =
+ /*A0-A7*/ "","cfam-reset","","","","","","",
+ /*B0-B7*/ "","","","","","","","",
+ /*C0-C7*/ "","","","","","","","",
+ /*D0-D7*/ "fsi-enable","","","","","led-sys-boot-status","led-attention",
+ "led-fault",
+ /*E0-E7*/ "","","","","","","","presence-pcie-e2b",
+ /*F0-F7*/ "","","","","","","","checkstop",
+ /*G0-G7*/ "fsi-clock","fsi-data","","","","","","",
+ /*H0-H7*/ "onewire0","onewire1","onewire2","onewire3","","","","",
+ /*I0-I7*/ "","","","power-button","","","","",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","","",
+ /*M0-M7*/ "","","","","","","","",
+ /*N0-N7*/ "","","","","","","","",
+ /*O0-O7*/ "","","","","iso_u164_en","","fsi-trans","",
+ /*P0-P7*/ "ncsi_mux_en_n","bmc_i2c2_sw_rst_n","","bmc_i2c5_sw_rst_n","",
+ "","fsi-mux","",
+ /*Q0-Q7*/ "","","","","","","","",
+ /*R0-R7*/ "","","","","","","","",
+ /*S0-S7*/ "","","","","","","","",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","","","","","","",
+ /*V0-V7*/ "","","","","","","","",
+ /*W0-W7*/ "","","","","","","","",
+ /*X0-X7*/ "","","","","","","","",
+ /*Y0-Y7*/ "","","","","","","","",
+ /*Z0-Z7*/ "","","","","","","","",
+ /*AA0-AA7*/ "","","led-hdd-fault","","","","","",
+ /*AB0-AB7*/ "","","","","","","","",
+ /*AC0-AC7*/ "","","","","","","","";
+
line_iso_u146_en {
gpio-hog;
gpios = <ASPEED_GPIO(O, 4) GPIO_ACTIVE_HIGH>;
output-high;
- line-name = "iso_u164_en";
};
ncsi_mux_en_n {
gpio-hog;
gpios = <ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
output-low;
- line-name = "ncsi_mux_en_n";
};
line_bmc_i2c2_sw_rst_n {
gpio-hog;
gpios = <ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>;
output-high;
- line-name = "bmc_i2c2_sw_rst_n";
};
line_bmc_i2c5_sw_rst_n {
gpio-hog;
gpios = <ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
output-high;
- line-name = "bmc_i2c5_sw_rst_n";
};
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
index 33d7045..4a1ca8f 100644
--- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts
@@ -80,12 +80,18 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default
&pinctrl_mdio1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii2_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>,
+ <&syscon ASPEED_CLK_MAC2RCLK>;
+ clock-names = "MACCLK", "RCLK";
use-ncsi;
};
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 679d04d..f81a540 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -65,6 +65,7 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
@@ -100,6 +101,7 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
@@ -162,6 +164,8 @@
reg = <0x1e6a0000 0x300>;
interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
+ aspeed,vhub-downstream-ports = <5>;
+ aspeed,vhub-generic-endpoints = <15>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2d_default>;
status = "disabled";
@@ -177,18 +181,21 @@
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges = <0 0x1e6e2000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
- pinctrl: pinctrl {
- compatible = "aspeed,g4-pinctrl";
- };
-
- p2a: p2a-control {
+ p2a: p2a-control@2c {
+ reg = <0x2c 0x4>;
compatible = "aspeed,ast2400-p2a-ctrl";
status = "disabled";
};
+
+ pinctrl: pinctrl@80 {
+ reg = <0x80 0x18>, <0xa0 0x10>;
+ compatible = "aspeed,ast2400-pinctrl";
+ };
};
rng: hwrng@1e6e2078 {
@@ -212,6 +219,16 @@
reg = <0x1e720000 0x8000>; // 32K
};
+ video: video@1e700000 {
+ compatible = "aspeed,ast2400-video-engine";
+ reg = <0x1e700000 0x1000>;
+ clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
+ <&syscon ASPEED_CLK_GATE_ECLK>;
+ clock-names = "vclk", "eclk";
+ interrupts = <7>;
+ status = "disabled";
+ };
+
sdmmc: sd-controller@1e740000 {
compatible = "aspeed,ast2400-sd-controller";
reg = <0x1e740000 0x100>;
@@ -344,15 +361,16 @@
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2400-lpc-ctrl";
- reg = <0x0 0x80>;
+ reg = <0x0 0x10>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
- lpc_snoop: lpc-snoop@0 {
+ lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2400-lpc-snoop";
- reg = <0x0 0x80>;
+ reg = <0x10 0x8>;
interrupts = <8>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
@@ -371,7 +389,6 @@
compatible = "aspeed,ast2400-ibt-bmc";
reg = <0xc0 0x18>;
interrupts = <8>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 412c96b..39e690b 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/clock/aspeed-clock.h>
+#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
/ {
model = "Aspeed BMC";
@@ -47,13 +48,6 @@
reg = <0x80000000 0>;
};
- edac: sdram@1e6e0000 {
- compatible = "aspeed,ast2500-sdram-edac";
- reg = <0x1e6e0000 0x174>;
- interrupts = <0>;
- status = "disabled";
- };
-
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -72,16 +66,19 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
@@ -97,11 +94,13 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
@@ -117,11 +116,13 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
@@ -195,6 +196,8 @@
reg = <0x1e6a0000 0x300>;
interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
+ aspeed,vhub-downstream-ports = <5>;
+ aspeed,vhub-generic-endpoints = <15>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ad_default>;
status = "disabled";
@@ -206,24 +209,41 @@
#size-cells = <1>;
ranges;
+ edac: memory-controller@1e6e0000 {
+ compatible = "aspeed,ast2500-sdram-edac";
+ reg = <0x1e6e0000 0x174>;
+ interrupts = <0>;
+ status = "disabled";
+ };
+
syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+ ranges = <0 0x1e6e2000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
- pinctrl: pinctrl {
- compatible = "aspeed,g5-pinctrl";
- aspeed,external-nodes = <&gfx &lhc>;
-
+ scu_ic: interrupt-controller@18 {
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2500-scu-ic";
+ reg = <0x18 0x4>;
+ interrupts = <21>;
+ interrupt-controller;
};
- p2a: p2a-control {
+ p2a: p2a-control@2c {
compatible = "aspeed,ast2500-p2a-ctrl";
+ reg = <0x2c 0x4>;
status = "disabled";
};
+
+ pinctrl: pinctrl@80 {
+ compatible = "aspeed,ast2500-pinctrl";
+ reg = <0x80 0x18>, <0xa0 0x10>;
+ aspeed,external-nodes = <&gfx>, <&lhc>;
+ };
};
rng: hwrng@1e6e2078 {
@@ -243,6 +263,17 @@
interrupts = <0x19>;
};
+ xdma: xdma@1e6e7000 {
+ compatible = "aspeed,ast2500-xdma";
+ reg = <0x1e6e7000 0x100>;
+ clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
+ resets = <&syscon ASPEED_RESET_XDMA>;
+ interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
+ aspeed,pcie-device = "bmc";
+ aspeed,scu = <&syscon>;
+ status = "disabled";
+ };
+
adc: adc@1e6e9000 {
compatible = "aspeed,ast2500-adc";
reg = <0x1e6e9000 0xb0>;
@@ -299,7 +330,7 @@
#gpio-cells = <2>;
gpio-controller;
compatible = "aspeed,ast2500-gpio";
- reg = <0x1e780000 0x1000>;
+ reg = <0x1e780000 0x200>;
interrupts = <20>;
gpio-ranges = <&pinctrl 0 0 232>;
clocks = <&syscon ASPEED_CLK_APB>;
@@ -307,6 +338,21 @@
#interrupt-cells = <2>;
};
+ sgpio: sgpio@1e780200 {
+ #gpio-cells = <2>;
+ compatible = "aspeed,ast2500-sgpio";
+ gpio-controller;
+ interrupts = <40>;
+ reg = <0x1e780200 0x0100>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ interrupt-controller;
+ ngpios = <8>;
+ bus-frequency = <12000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm_default>;
+ status = "disabled";
+ };
+
rtc: rtc@1e781000 {
compatible = "aspeed,ast2500-rtc";
reg = <0x1e781000 0x18>;
@@ -399,22 +445,22 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x80>;
- kcs1: kcs1@0 {
- compatible = "aspeed,ast2500-kcs-bmc";
+ kcs1: kcs@24 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
interrupts = <8>;
- kcs_chan = <1>;
status = "disabled";
};
- kcs2: kcs2@0 {
- compatible = "aspeed,ast2500-kcs-bmc";
+ kcs2: kcs@28 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
interrupts = <8>;
- kcs_chan = <2>;
status = "disabled";
};
- kcs3: kcs3@0 {
- compatible = "aspeed,ast2500-kcs-bmc";
+ kcs3: kcs@2c {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
interrupts = <8>;
- kcs_chan = <3>;
status = "disabled";
};
};
@@ -428,43 +474,44 @@
#size-cells = <1>;
ranges = <0x0 0x80 0x1e0>;
- kcs4: kcs4@0 {
- compatible = "aspeed,ast2500-kcs-bmc";
+ kcs4: kcs@94 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
interrupts = <8>;
- kcs_chan = <4>;
status = "disabled";
};
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x0 0x80>;
+ reg = <0x0 0x10>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
- lpc_snoop: lpc-snoop@0 {
+ lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2500-lpc-snoop";
- reg = <0x0 0x80>;
+ reg = <0x10 0x8>;
interrupts = <8>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
- lhc: lhc@20 {
- compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
lpc_reset: reset-controller@18 {
compatible = "aspeed,ast2500-lpc-reset";
reg = <0x18 0x4>;
#reset-cells = <1>;
};
+ lhc: lhc@20 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+ };
+
+
ibt: ibt@c0 {
compatible = "aspeed,ast2500-ibt-bmc";
reg = <0xc0 0x18>;
interrupts = <8>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
index 996e006..a362714 100644
--- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi
@@ -118,7 +118,7 @@
};
pinctrl_fwqspid_default: fwqspid_default {
- function = "FWQSPID";
+ function = "FWSPID";
groups = "FWQSPID";
};
@@ -852,14 +852,9 @@
groups = "SD2";
};
- pinctrl_sd3_default: sd3_default {
- function = "SD3";
- groups = "SD3";
- };
-
pinctrl_emmc_default: emmc_default {
- function = "SD3";
- groups = "EMMC";
+ function = "EMMC";
+ groups = "EMMCG4";
};
pinctrl_sgpm1_default: sgpm1_default {
@@ -1117,6 +1112,31 @@
groups = "UART9";
};
+ pinctrl_usb2ah_default: usb2ah_default {
+ function = "USB2AH";
+ groups = "USBA";
+ };
+
+ pinctrl_usb2ad_default: usb2ad_default {
+ function = "USB2AD";
+ groups = "USBA";
+ };
+
+ pinctrl_usb2bh_default: usb2bh_default {
+ function = "USB2BH";
+ groups = "USBB";
+ };
+
+ pinctrl_usb2bd_default: usb2bd_default {
+ function = "USB2BD";
+ groups = "USBB";
+ };
+
+ pinctrl_usb11bhid_default: usb11bhid_default {
+ function = "USB11BHID";
+ groups = "USBB";
+ };
+
pinctrl_vb_default: vb_default {
function = "VB";
groups = "VB";
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 3a1422f..1cf71bd 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -2,6 +2,7 @@
// Copyright 2019 IBM Corp.
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
#include <dt-bindings/clock/ast2600-clock.h>
/ {
@@ -12,7 +13,29 @@
interrupt-parent = <&gic>;
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
serial4 = &uart5;
+ serial5 = &vuart1;
+ serial6 = &vuart2;
};
@@ -43,6 +66,7 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
clocks = <&syscon ASPEED_CLK_HPLL>;
arm,cpu-registers-not-fw-configured;
+ always-on;
};
ahb {
@@ -64,12 +88,93 @@
<0x40466000 0x2000>;
};
+ fmc: spi@1e620000 {
+ reg = < 0x1e620000 0xc4
+ 0x20000000 0x10000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2600-fmc";
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ status = "disabled";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ flash@2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ };
+
+ spi1: spi@1e630000 {
+ reg = < 0x1e630000 0xc4
+ 0x30000000 0x10000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2600-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ status = "disabled";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ };
+
+ spi2: spi@1e631000 {
+ reg = < 0x1e631000 0xc4
+ 0x50000000 0x10000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2600-spi";
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ status = "disabled";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ flash@1 {
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ flash@2 {
+ reg = < 2 >;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ status = "disabled";
+ };
+ };
+
mdio0: mdio@1e650000 {
compatible = "aspeed,ast2600-mdio";
reg = <0x1e650000 0x8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mdio1_default>;
};
mdio1: mdio@1e650008 {
@@ -78,6 +183,8 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mdio2_default>;
};
mdio2: mdio@1e650010 {
@@ -86,6 +193,8 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mdio3_default>;
};
mdio3: mdio@1e650018 {
@@ -94,6 +203,8 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mdio4_default>;
};
mac0: ftgmac@1e660000 {
@@ -136,6 +247,51 @@
status = "disabled";
};
+ ehci0: usb@1e6a1000 {
+ compatible = "aspeed,ast2600-ehci", "generic-ehci";
+ reg = <0x1e6a1000 0x100>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2ah_default>;
+ status = "disabled";
+ };
+
+ ehci1: usb@1e6a3000 {
+ compatible = "aspeed,ast2600-ehci", "generic-ehci";
+ reg = <0x1e6a3000 0x100>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2bh_default>;
+ status = "disabled";
+ };
+
+ uhci: usb@1e6b0000 {
+ compatible = "aspeed,ast2600-uhci", "generic-uhci";
+ reg = <0x1e6b0000 0x100>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #ports = <2>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
+ status = "disabled";
+ /*
+ * No default pinmux, it will follow EHCI, use an
+ * explicit pinmux override if EHCI is not enabled.
+ */
+ };
+
+ vhub: usb-vhub@1e6a0000 {
+ compatible = "aspeed,ast2600-usb-vhub";
+ reg = <0x1e6a0000 0x350>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
+ aspeed,vhub-downstream-ports = <7>;
+ aspeed,vhub-generic-endpoints = <21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2ad_default>;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -159,6 +315,22 @@
compatible = "aspeed,ast2600-smpmem";
reg = <0x180 0x40>;
};
+
+ scu_ic0: interrupt-controller@560 {
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2600-scu-ic0";
+ reg = <0x560 0x4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ };
+
+ scu_ic1: interrupt-controller@570 {
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2600-scu-ic1";
+ reg = <0x570 0x4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ };
};
rng: hwrng@1e6e2524 {
@@ -168,6 +340,45 @@
quality = <100>;
};
+ xdma: xdma@1e6e7000 {
+ compatible = "aspeed,ast2600-xdma";
+ reg = <0x1e6e7000 0x100>;
+ clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
+ resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>;
+ reset-names = "device", "root-complex";
+ interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>;
+ aspeed,pcie-device = "bmc";
+ aspeed,scu = <&syscon>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@1e780000 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2600-gpio";
+ reg = <0x1e780000 0x400>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 0 208>;
+ ngpios = <208>;
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@1e780800 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2600-gpio";
+ reg = <0x1e780800 0x800>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&pinctrl 0 208 36>;
+ ngpios = <36>;
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
rtc: rtc@1e781000 {
compatible = "aspeed,ast2600-rtc";
reg = <0x1e781000 0x18>;
@@ -175,6 +386,36 @@
status = "disabled";
};
+ timer: timer@1e782000 {
+ compatible = "aspeed,ast2600-timer";
+ reg = <0x1e782000 0x90>;
+ interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ clock-names = "PCLK";
+ status = "disabled";
+ };
+
+ uart1: serial@1e783000 {
+ compatible = "ns16550a";
+ reg = <0x1e783000 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
+ resets = <&lpc_reset 4>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>;
+ status = "disabled";
+ };
+
uart5: serial@1e784000 {
compatible = "ns16550a";
reg = <0x1e784000 0x1000>;
@@ -201,12 +442,101 @@
status = "disabled";
};
- wdt4: watchdog@1e7850C0 {
+ wdt4: watchdog@1e7850c0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
status = "disabled";
};
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2600-lpc", "simple-mfd";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ lpc_bmc: lpc-bmc@0 {
+ compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon";
+ reg = <0x0 0x80>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x80>;
+
+ kcs1: kcs@24 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <1>;
+ status = "disabled";
+ };
+ kcs2: kcs@28 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ kcs3: kcs@2c {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ lpc_host: lpc-host@80 {
+ compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon";
+ reg = <0x80 0x1e0>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80 0x1e0>;
+
+ kcs4: kcs@94 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible = "aspeed,ast2600-lpc-ctrl";
+ reg = <0x0 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
+ };
+
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2600-lpc-snoop";
+ reg = <0x0 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
+ };
+
+ lhc: lhc@20 {
+ compatible = "aspeed,ast2600-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+ };
+
+ lpc_reset: reset-controller@18 {
+ compatible = "aspeed,ast2600-lpc-reset";
+ reg = <0x18 0x4>;
+ #reset-cells = <1>;
+ };
+
+ ibt: ibt@c0 {
+ compatible = "aspeed,ast2600-ibt-bmc";
+ reg = <0xc0 0x18>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+ };
+
sdc: sdc@1e740000 {
compatible = "aspeed,ast2600-sd-controller";
reg = <0x1e740000 0x100>;
@@ -235,7 +565,7 @@
};
};
- emmc: sdc@1e750000 {
+ emmc_controller: sdc@1e750000 {
compatible = "aspeed,ast2600-sd-controller";
reg = <0x1e750000 0x100>;
#address-cells = <1>;
@@ -244,7 +574,7 @@
clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
status = "disabled";
- sdhci@1e750100 {
+ emmc: sdhci@1e750100 {
compatible = "aspeed,ast2600-sdhci";
reg = <0x100 0x100>;
sdhci,auto-cmd12;
@@ -254,8 +584,339 @@
pinctrl-0 = <&pinctrl_emmc_default>;
};
};
+
+ vuart1: serial@1e787000 {
+ compatible = "aspeed,ast2500-vuart";
+ reg = <0x1e787000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ vuart2: serial@1e788000 {
+ compatible = "aspeed,ast2500-vuart";
+ reg = <0x1e788000 0x40>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_APB1>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ uart2: serial@1e78d000 {
+ compatible = "ns16550a";
+ reg = <0x1e78d000 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
+ resets = <&lpc_reset 5>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
+ status = "disabled";
+ };
+
+ uart3: serial@1e78e000 {
+ compatible = "ns16550a";
+ reg = <0x1e78e000 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
+ resets = <&lpc_reset 6>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
+ status = "disabled";
+ };
+
+ uart4: serial@1e78f000 {
+ compatible = "ns16550a";
+ reg = <0x1e78f000 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
+ resets = <&lpc_reset 7>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>;
+ status = "disabled";
+ };
+
+ i2c: bus@1e78a000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1e78a000 0x1000>;
+ };
+
+ fsim0: fsi@1e79b000 {
+ compatible = "aspeed,ast2600-fsi-master", "fsi-master";
+ reg = <0x1e79b000 0x94>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fsi1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
+ status = "disabled";
+ };
+
+ fsim1: fsi@1e79b100 {
+ compatible = "aspeed,ast2600-fsi-master", "fsi-master";
+ reg = <0x1e79b100 0x94>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fsi2_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
+ status = "disabled";
+ };
};
};
};
#include "aspeed-g6-pinctrl.dtsi"
+
+&i2c {
+ i2c0: i2c-bus@80 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x80 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "disabled";
+ };
+
+ i2c1: i2c-bus@100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x100 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_default>;
+ status = "disabled";
+ };
+
+ i2c2: i2c-bus@180 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x180 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_default>;
+ status = "disabled";
+ };
+
+ i2c3: i2c-bus@200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x200 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_default>;
+ status = "disabled";
+ };
+
+ i2c4: i2c-bus@280 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x280 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c5_default>;
+ status = "disabled";
+ };
+
+ i2c5: i2c-bus@300 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x300 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c6_default>;
+ status = "disabled";
+ };
+
+ i2c6: i2c-bus@380 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x380 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c7_default>;
+ status = "disabled";
+ };
+
+ i2c7: i2c-bus@400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x400 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c8_default>;
+ status = "disabled";
+ };
+
+ i2c8: i2c-bus@480 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x480 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c9_default>;
+ status = "disabled";
+ };
+
+ i2c9: i2c-bus@500 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x500 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c10_default>;
+ status = "disabled";
+ };
+
+ i2c10: i2c-bus@580 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x580 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c11_default>;
+ status = "disabled";
+ };
+
+ i2c11: i2c-bus@600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x600 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c12_default>;
+ status = "disabled";
+ };
+
+ i2c12: i2c-bus@680 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x680 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c13_default>;
+ status = "disabled";
+ };
+
+ i2c13: i2c-bus@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x700 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c14_default>;
+ status = "disabled";
+ };
+
+ i2c14: i2c-bus@780 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x780 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c15_default>;
+ status = "disabled";
+ };
+
+ i2c15: i2c-bus@800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x800 0x80>;
+ compatible = "aspeed,ast2600-i2c-bus";
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ bus-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c16_default>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi
new file mode 100644
index 0000000..c0c43b8
--- /dev/null
+++ b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2019 Facebook Inc.
+
+#include "aspeed-g5.dtsi"
+
+/ {
+ memory@80000000 {
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+/*
+ * Update reset type to "system" (full chip) to fix warm reboot hang issue
+ * when reset type is set to default ("soc", gated by reset mask registers).
+ */
+&wdt1 {
+ status = "okay";
+ aspeed,reset-type = "system";
+};
+
+&wdt2 {
+ status = "disabled";
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default>;
+};
+
+&uart3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_txd3_default
+ &pinctrl_rxd3_default>;
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+
+ fmc_flash0: flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "spi0.0";
+ };
+
+ fmc_flash1: flash@1 {
+ status = "okay";
+ m25p,fast-read;
+ label = "spi0.1";
+ };
+};
+
+&mac1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&vhub {
+ status = "okay";
+};
+
+&sdmmc {
+ status = "okay";
+};
+
+&sdhci1 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd2_default>;
+};
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index dbfefef..713d18f 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -22,7 +22,7 @@
bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
};
- memory {
+ memory@20000000 {
/* 128 MB, change this for 256 MB revision */
reg = <0x20000000 0x8000000>;
};
@@ -93,6 +93,7 @@
pinctrl-0 = <
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
diff --git a/arch/arm/boot/dts/at91-ariettag25.dts b/arch/arm/boot/dts/at91-ariettag25.dts
index 0267e72..2c52a71 100644
--- a/arch/arm/boot/dts/at91-ariettag25.dts
+++ b/arch/arm/boot/dts/at91-ariettag25.dts
@@ -15,7 +15,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x8000000>;
};
@@ -48,6 +48,7 @@
pinctrl-0 = <
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi
index feebd54..ee0f5da 100644
--- a/arch/arm/boot/dts/at91-cosino.dtsi
+++ b/arch/arm/boot/dts/at91-cosino.dtsi
@@ -20,7 +20,7 @@
bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x8000000>;
};
@@ -112,6 +112,7 @@
&pinctrl_board_mmc0
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts
index 73e88d1..04cb7be 100644
--- a/arch/arm/boot/dts/at91-cosino_mega2560.dts
+++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts
@@ -34,6 +34,7 @@
pinctrl-0 = <
&pinctrl_mmc1_slot0_clk_cmd_dat0
&pinctrl_mmc1_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
index 21876da..c1c8650 100644
--- a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
+++ b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
@@ -62,7 +62,7 @@
wm8904: wm8904@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
- clocks = <&pck2>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 10>;
clock-names = "mclk";
};
};
diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi
index df0f0cc..bea920b 100644
--- a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi
+++ b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi
@@ -17,7 +17,7 @@
};
panel: panel {
- compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92", "simple-panel";
+ compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92";
backlight = <&backlight>;
power-supply = <&vcc_lcd_reg>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts
index 683b9e3..7edf057 100644
--- a/arch/arm/boot/dts/at91-foxg20.dts
+++ b/arch/arm/boot/dts/at91-foxg20.dts
@@ -17,7 +17,7 @@
bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
@@ -55,6 +55,7 @@
&pinctrl_mmc0_clk
&pinctrl_mmc0_slot1_cmd_dat0
&pinctrl_mmc0_slot1_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@1 {
diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts
index 90996ea..7add151 100644
--- a/arch/arm/boot/dts/at91-kizbox.dts
+++ b/arch/arm/boot/dts/at91-kizbox.dts
@@ -18,7 +18,7 @@
stdout-path = &dbgu;
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x2000000>;
};
@@ -28,85 +28,6 @@
};
};
- ahb {
- apb {
- tcb0: timer@fffa0000 {
- timer@0 {
- compatible = "atmel,tcb-timer";
- reg = <0>, <1>;
- };
-
- timer@2 {
- compatible = "atmel,tcb-timer";
- reg = <2>;
- };
- };
-
- macb0: ethernet@fffc4000 {
- phy-mode = "mii";
- pinctrl-0 = <&pinctrl_macb_rmii
- &pinctrl_macb_rmii_mii_alt>;
- status = "okay";
- };
-
- usart3: serial@fffd0000 {
- status = "okay";
- };
-
- dbgu: serial@fffff200 {
- status = "okay";
- };
-
- watchdog@fffffd40 {
- timeout-sec = <15>;
- atmel,max-heartbeat-sec = <16>;
- atmel,min-heartbeat-sec = <0>;
- status = "okay";
- };
- };
-
- usb0: ohci@500000 {
- num-ports = <1>;
- status = "okay";
- };
-
- ebi: ebi@10000000 {
- status = "okay";
-
- nand_controller: nand-controller {
- status = "okay";
- pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
- pinctrl-names = "default";
-
- nand@3 {
- reg = <0x3 0x0 0x800000>;
- rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
- nand-bus-width = <8>;
- nand-ecc-mode = "soft";
- nand-on-flash-bbt;
- label = "atmel_nand";
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootstrap@0 {
- label = "bootstrap";
- reg = <0x0 0x20000>;
- };
-
- ubi@20000 {
- label = "ubi";
- reg = <0x20000 0x7fe0000>;
- };
- };
- };
- };
- };
- };
-
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
@@ -127,15 +48,6 @@
};
};
- i2c-gpio-0 {
- status = "okay";
-
- rtc: pcf8563@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
-
pwm_leds {
compatible = "pwm-leds";
@@ -179,3 +91,87 @@
&pinctrl_tcb1_tiob0>;
};
};
+
+&tcb0 {
+ timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>, <1>;
+ };
+
+ timer@2 {
+ compatible = "atmel,tcb-timer";
+ reg = <2>;
+ };
+};
+
+&ebi {
+ status = "okay";
+};
+
+&nand_controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "soft";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ ubi@20000 {
+ label = "ubi";
+ reg = <0x20000 0x7fe0000>;
+ };
+ };
+ };
+};
+
+&macb0 {
+ phy-mode = "mii";
+ pinctrl-0 = <&pinctrl_macb_rmii
+ &pinctrl_macb_rmii_mii_alt>;
+ status = "okay";
+};
+
+&usart3 {
+ status = "okay";
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&watchdog {
+ timeout-sec = <15>;
+ atmel,max-heartbeat-sec = <16>;
+ atmel,min-heartbeat-sec = <0>;
+ status = "okay";
+};
+
+&usb0 {
+ num-ports = <1>;
+ status = "okay";
+};
+
+&i2c_gpio0 {
+ status = "okay";
+
+ rtc: pcf8563@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
diff --git a/arch/arm/boot/dts/at91-kizbox2-2.dts b/arch/arm/boot/dts/at91-kizbox2-2.dts
new file mode 100644
index 0000000..cab8b35
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizbox2-2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * at91-kizbox2-2.dts - Device Tree file for the Kizbox2 with
+ * two head board
+ *
+ * Copyright (C) 2015 Overkiz SAS
+ *
+ * Authors: Antoine Aubert <a.aubert@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizbox2-common.dtsi"
+
+/ {
+ model = "Overkiz Kizbox 2 with two heads";
+ compatible = "overkiz,kizbox2-2", "atmel,sama5d31",
+ "atmel,sama5d3", "atmel,sama5";
+};
+
+&usart1 {
+ status = "okay";
+};
+
+&usart2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/at91-kizbox2-common.dtsi
new file mode 100644
index 0000000..25f7610
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizbox2-common.dtsi
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * at91-kizbox2_common.dtsi - Device Tree Include file for
+ * Overkiz Kizbox 2 family SoC
+ *
+ * Copyright (C) 2014-2018 Overkiz SAS
+ *
+ * Authors: Antoine Aubert <a.aubert@overkiz.com>
+ * Gaël Portay <g.portay@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ */
+#include "sama5d31.dtsi"
+
+/ {
+ chosen {
+ bootargs = "ubi.mtd=ubi";
+ stdout-path = &dbgu;
+ };
+
+ memory@20000000 {
+ reg = <0x20000000 0x10000000>;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ prog {
+ label = "PB_PROG";
+ gpios = <&pioE 27 GPIO_ACTIVE_LOW>;
+ linux,code = <0x102>;
+ wakeup-source;
+ };
+
+ reset {
+ label = "PB_RST";
+ gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
+ linux,code = <0x100>;
+ wakeup-source;
+ };
+
+ user {
+ label = "PB_USER";
+ gpios = <&pioE 31 GPIO_ACTIVE_HIGH>;
+ linux,code = <0x101>;
+ wakeup-source;
+ };
+ };
+
+ pwm_leds {
+ compatible = "pwm-leds";
+
+ blue {
+ label = "pwm:blue:user";
+ pwms = <&pwm0 2 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "none";
+ };
+
+ green {
+ label = "pwm:green:user";
+ pwms = <&pwm0 1 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ };
+
+ red {
+ label = "pwm:red:user";
+ pwms = <&pwm0 0 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ pmic: act8865@5b {
+ compatible = "active-semi,act8865";
+ reg = <0x5b>;
+ status = "okay";
+
+ regulators {
+ vcc_1v8_reg: DCDC_REG1 {
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcc_1v2_reg: DCDC_REG2 {
+ regulator-name = "VCC_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vcc_3v3_reg: DCDC_REG3 {
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vddfuse_reg: LDO_REG1 {
+ regulator-name = "FUSE_2V5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ vddana_reg: LDO_REG2 {
+ regulator-name = "VDDANA";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vled_reg: LDO_REG3 {
+ regulator-name = "VLED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ v3v8_rf_reg: LDO_REG4 {
+ regulator-name = "V3V8_RF";
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&usart0 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&usart1 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&usart2 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_pwmh0_1
+ &pinctrl_pwm0_pwmh1_1
+ &pinctrl_pwm0_pwmh2_0>;
+ status = "okay";
+};
+
+&adc0 {
+ atmel,adc-vref = <3333>;
+ status = "okay";
+};
+
+&macb1 {
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&ebi {
+ pinctrl-0 = <&pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&nand_controller {
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ ubi@20000 {
+ label = "ubi";
+ reg = <0x20000 0x7fe0000>;
+ };
+ };
+ };
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+/* WMBUS (inverted with IO in the latest schematic) */
+&pinctrl_usart0 {
+ atmel,pins =
+ <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOE 2 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+};
+
+/* RTS */
+&pinctrl_usart1 {
+ atmel,pins =
+ <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOE 7 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+};
+
+/* IO (inverted with WMBUS in the latest schematic) */
+&pinctrl_usart2 {
+ atmel,pins =
+ <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP
+ AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+};
diff --git a/arch/arm/boot/dts/at91-kizbox2.dts b/arch/arm/boot/dts/at91-kizbox2.dts
deleted file mode 100644
index 86d8218..0000000
--- a/arch/arm/boot/dts/at91-kizbox2.dts
+++ /dev/null
@@ -1,244 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * at91-kizbox2.dts - Device Tree file for Overkiz Kizbox 2 board
- *
- * Copyright (C) 2014 Gaël PORTAY <g.portay@overkiz.com>
- */
-/dts-v1/;
-#include "sama5d31.dtsi"
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
- model = "Overkiz Kizbox 2";
- compatible = "overkiz,kizbox2", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
-
- chosen {
- bootargs = "ubi.mtd=ubi";
- stdout-path = &dbgu;
- };
-
- memory {
- reg = <0x20000000 0x10000000>;
- };
-
- clocks {
- slow_xtal {
- clock-frequency = <32768>;
- };
-
- main_xtal {
- clock-frequency = <12000000>;
- };
- };
-
- ahb {
- apb {
- i2c1: i2c@f0018000 {
- status = "okay";
-
- pmic: act8865@5b {
- compatible = "active-semi,act8865";
- reg = <0x5b>;
- status = "okay";
-
- regulators {
- vcc_1v8_reg: DCDC_REG1 {
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- vcc_1v2_reg: DCDC_REG2 {
- regulator-name = "VCC_1V2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- vcc_3v3_reg: DCDC_REG3 {
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vddfuse_reg: LDO_REG1 {
- regulator-name = "FUSE_2V5";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- };
-
- vddana_reg: LDO_REG2 {
- regulator-name = "VDDANA";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vled_reg: LDO_REG3 {
- regulator-name = "VLED";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- v3v8_rf_reg: LDO_REG4 {
- regulator-name = "V3V8_RF";
- regulator-min-microvolt = <3800000>;
- regulator-max-microvolt = <3800000>;
- regulator-always-on;
- };
- };
- };
- };
-
- tcb0: timer@f0010000 {
- timer@0 {
- compatible = "atmel,tcb-timer";
- reg = <0>;
- };
-
- timer@1 {
- compatible = "atmel,tcb-timer";
- reg = <1>;
- };
- };
-
- usart0: serial@f001c000 {
- status = "okay";
- };
-
- usart1: serial@f0020000 {
- status = "okay";
- };
-
- pwm0: pwm@f002c000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_pwmh0_1
- &pinctrl_pwm0_pwmh1_1
- &pinctrl_pwm0_pwmh2_0>;
- status = "okay";
- };
-
- adc0: adc@f8018000 {
- atmel,adc-vref = <3333>;
- status = "okay";
- };
-
- usart2: serial@f8020000 {
- status = "okay";
- };
-
- macb1: ethernet@f802c000 {
- phy-mode = "rmii";
- status = "okay";
- };
-
- dbgu: serial@ffffee00 {
- status = "okay";
- };
-
- watchdog@fffffe40 {
- status = "okay";
- };
- };
-
- usb1: ohci@600000 {
- status = "okay";
- };
-
- usb2: ehci@700000 {
- status = "okay";
- };
-
- ebi: ebi@10000000 {
- pinctrl-0 = <&pinctrl_ebi_nand_addr>;
- pinctrl-names = "default";
- status = "okay";
-
- nand_controller: nand-controller {
- status = "okay";
-
- nand@3 {
- reg = <0x3 0x0 0x2>;
- atmel,rb = <0>;
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- nand-on-flash-bbt;
- label = "atmel_nand";
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootstrap@0 {
- label = "bootstrap";
- reg = <0x0 0x20000>;
- };
-
- ubi@20000 {
- label = "ubi";
- reg = <0x20000 0x7fe0000>;
- };
- };
- };
- };
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-
- prog {
- label = "PB_PROG";
- gpios = <&pioE 27 GPIO_ACTIVE_LOW>;
- linux,code = <0x102>;
- wakeup-source;
- };
-
- reset {
- label = "PB_RST";
- gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
- linux,code = <0x100>;
- wakeup-source;
- };
-
- user {
- label = "PB_USER";
- gpios = <&pioE 31 GPIO_ACTIVE_HIGH>;
- linux,code = <0x101>;
- wakeup-source;
- };
- };
-
- pwm_leds {
- compatible = "pwm-leds";
-
- blue {
- label = "pwm:blue:user";
- pwms = <&pwm0 2 10000000 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- };
-
- green {
- label = "pwm:green:user";
- pwms = <&pwm0 1 10000000 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- };
-
- red {
- label = "pwm:red:user";
- pwms = <&pwm0 0 10000000 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- };
- };
-};
diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts
new file mode 100644
index 0000000..0da1f05
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizbox3-hs.dts
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * at91-kizbox3-hs.dts - Device Tree file for Overkiz KIZBOX3-HS board
+ *
+ * Copyright (C) 2018 Overkiz SAS
+ *
+ * Authors: Dorian Rocipon <d.rocipon@overkiz.com>
+ * Kevin Carli <k.carli@overkiz.com>
+ * Mickael Gardet <m.gardet@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizbox3_common.dtsi"
+
+/ {
+ model = "Overkiz KIZBOX3-HS";
+ compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5";
+
+ pwm_leds {
+ status = "okay";
+
+ red {
+ status = "okay";
+ };
+
+ green {
+ status = "okay";
+ };
+
+ blue {
+ status = "okay";
+ };
+
+ white {
+ status = "okay";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led_red
+ &pinctrl_led_white>;
+ status = "okay";
+
+ red {
+ label = "pio:red:user";
+ gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ white {
+ label = "pio:white:user";
+ gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default" , "default", "default",
+ "default", "default" ;
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+ pinctrl-1 = <&pinctrl_pio_rf &pinctrl_pio_wifi>;
+ pinctrl-2 = <&pinctrl_pio_io_boot
+ &pinctrl_pio_io_reset
+ &pinctrl_pio_io_test_radio>;
+ pinctrl-3 = <&pinctrl_pio_zbe_test_radio
+ &pinctrl_pio_zbe_rst>;
+ pinctrl-4 = <&pinctrl_pio_input>;
+
+ SW1 {
+ label = "SW1";
+ gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>;
+ linux,code = <0x101>;
+ wakeup-source;
+ };
+
+ SW2 {
+ label = "SW2";
+ gpios = <&pioA PIN_PA18 GPIO_ACTIVE_LOW>;
+ linux,code = <0x102>;
+ wakeup-source;
+ };
+
+ SW3 {
+ label = "SW3";
+ gpios = <&pioA PIN_PA22 GPIO_ACTIVE_LOW>;
+ linux,code = <0x103>;
+ wakeup-source;
+ };
+
+ SW7 {
+ label = "SW7";
+ gpios = <&pioA PIN_PA26 GPIO_ACTIVE_LOW>;
+ linux,code = <0x107>;
+ wakeup-source;
+ };
+
+ SW8 {
+ label = "SW8";
+ gpios = <&pioA PIN_PA24 GPIO_ACTIVE_LOW>;
+ linux,code = <0x108>;
+ wakeup-source;
+ };
+ };
+
+ gpios {
+ compatible = "gpio";
+ status = "okay";
+
+ rf_on {
+ label = "rf on";
+ gpio = <&pioA PIN_PC19 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ wifi_on {
+ label = "wifi on";
+ gpio = <&pioA PIN_PC20 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ zbe_test_radio {
+ label = "zbe test radio";
+ gpio = <&pioA PIN_PB21 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ zbe_rst {
+ label = "zbe rst";
+ gpio = <&pioA PIN_PB25 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ io_reset {
+ label = "io reset";
+ gpio = <&pioA PIN_PB30 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ io_test_radio {
+ label = "io test radio";
+ gpio = <&pioA PIN_PC9 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ io_boot_0 {
+ label = "io boot 0";
+ gpio = <&pioA PIN_PC11 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ io_boot_1 {
+ label = "io boot 1";
+ gpio = <&pioA PIN_PC17 GPIO_ACTIVE_HIGH>;
+ output;
+ init-low;
+ };
+
+ verbose_bootloader {
+ label = "verbose bootloader";
+ gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+
+ nail_bed_detection {
+ label = "nail bed detection";
+ gpio = <&pioA PIN_PB12 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+
+ id_usba {
+ label = "id usba";
+ gpio = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>;
+ input;
+ };
+ };
+};
+
+&pioA {
+ pinctrl_key_gpio_default: key_gpio_default {
+ pinmux= <PIN_PA22__GPIO>,
+ <PIN_PA24__GPIO>,
+ <PIN_PA26__GPIO>,
+ <PIN_PA29__GPIO>,
+ <PIN_PA18__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_gpio {
+ pinctrl_pio_rf: gpio_rf {
+ pinmux = <PIN_PC19__GPIO>;
+ bias-disable;
+ };
+ pinctrl_pio_wifi: gpio_wifi {
+ pinmux = <PIN_PC20__GPIO>;
+ bias-disable;
+ };
+ pinctrl_pio_io_boot: gpio_io_boot {
+ pinmux =
+ <PIN_PC11__GPIO>,
+ <PIN_PC17__GPIO>;
+ bias-disable;
+ };
+ pinctrl_pio_io_test_radio: gpio_io_test_radio {
+ pinmux = <PIN_PC9__GPIO>;
+ bias-disable;
+ };
+ pinctrl_pio_zbe_test_radio: gpio_zbe_test_radio {
+ pinmux = <PIN_PB21__GPIO>;
+ bias-disable;
+ };
+ pinctrl_pio_zbe_rst: gpio_zbe_rst {
+ pinmux = <PIN_PB25__GPIO>;
+ bias-disable;
+ };
+ /* stm32 reset must be open drain (internal pull up) */
+ pinctrl_pio_io_reset: gpio_io_reset {
+ pinmux = <PIN_PB30__GPIO>;
+ bias-disable;
+ drive-open-drain = <1>;
+ output-low;
+ };
+ pinctrl_pio_input: gpio_input {
+ pinmux =
+ <PIN_PB11__GPIO>,
+ <PIN_PB12__GPIO>,
+ <PIN_PC0__GPIO>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_leds {
+ pinctrl_led_red: led_red {
+ pinmux = <PIN_PB1__GPIO>;
+ bias-disable;
+ };
+ pinctrl_led_white: led_white {
+ pinmux = <PIN_PB8__GPIO>;
+ bias-disable;
+ };
+ };
+};
+
+&adc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&flx0 {
+ status = "okay";
+
+ uart5: serial@200 {
+ status = "okay";
+ };
+};
+
+&flx3 {
+ status = "okay";
+ uart8: serial@200 {
+ status = "okay";
+ };
+};
+
+&flx4 {
+ status = "okay";
+
+ i2c6: i2c@600 {
+ status = "okay";
+ };
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi
new file mode 100644
index 0000000..dc77d8e
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizbox3_common.dtsi
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * at91-kizbox3.dts - Device Tree Include file for Overkiz Kizbox 3
+ * family SoC boards
+ *
+ * Copyright (C) 2018 Overkiz SAS
+ *
+ * Authors: Dorian Rocipon <d.rocipon@overkiz.com>
+ * Kevin Carli <k.carli@overkiz.com>
+ * Mickael Gardet <m.gardet@overkiz.com>
+ */
+/dts-v1/;
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Overkiz Kizbox3";
+ compatible = "overkiz,kizbox3", "atmel,sama5d2", "atmel,sama5";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart8;
+ };
+
+ chosen {
+ bootargs = "ubi.mtd=ubi";
+ stdout-path = "serial1:115200n8";
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ vdd_adc_vddana: supply_3v3_ana {
+ compatible = "regulator-fixed";
+ regulator-name = "adc-vddana";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_adc_vref: supply_3v3_ref {
+ compatible = "regulator-fixed";
+ regulator-name = "adc-vref";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ pwm_leds {
+ compatible = "pwm-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_pwm_h0
+ &pinctrl_pwm0_pwm_h1
+ &pinctrl_pwm0_pwm_h2
+ &pinctrl_pwm0_pwm_h3>;
+ status = "disabled";
+
+ red {
+ label = "pwm:red:user";
+ pwms = <&pwm0 0 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ status = "disabled";
+ };
+
+ green {
+ label = "pwm:green:user";
+ pwms = <&pwm0 1 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ status = "disabled";
+ };
+
+ blue {
+ label = "pwm:blue:user";
+ pwms = <&pwm0 2 10000000 0>;
+ max-brightness = <255>;
+ status = "disabled";
+ };
+
+ white {
+ label = "pwm:white:user";
+ pwms = <&pwm0 3 10000000 0>;
+ max-brightness = <255>;
+ status = "disabled";
+ };
+ };
+};
+
+&ebi {
+ status = "okay";
+};
+
+&nand_controller {
+ status = "okay";
+
+ nand@3 {
+ pinctrl-0 = <&pinctrl_ebi_nand_addr>;
+ pinctrl-names = "default";
+ reg = <0x3 0x0 0x800000>;
+
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ u-boot@20000 {
+ label = "u-boot";
+ reg = <0x20000 0x140000>;
+ };
+
+ u-boot-factory@160000 {
+ label = "u-boot-factory";
+ reg = <0x160000 0x140000>;
+ };
+
+ ubi@2A0000 {
+ label = "ubi";
+ reg = <0x2A0000 0x7D60000>;
+ };
+ };
+
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&pioA {
+ pinctrl_ebi_nand_addr: ebi-addr-1 {
+ pinmux = <PIN_PA0__D0>,
+ <PIN_PA1__D1>,
+ <PIN_PA2__D2>,
+ <PIN_PA3__D3>,
+ <PIN_PA4__D4>,
+ <PIN_PA5__D5>,
+ <PIN_PA6__D6>,
+ <PIN_PA7__D7>,
+ <PIN_PA8__NWE_NANDWE>,
+ <PIN_PA9__NCS3>,
+ <PIN_PA10__A21_NANDALE>,
+ <PIN_PA11__A22_NANDCLE>,
+ <PIN_PA21__NANDRDY>;
+ bias-disable;
+ };
+
+ pinctrl_usart {
+ pinctrl_usart_0: usart0-0 {
+ pinmux = < PIN_PB26__URXD0>, <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+ pinctrl_usart_1: usart1-0 {
+ pinmux = < PIN_PD2__URXD1>, <PIN_PD3__UTXD1>;
+ bias-disable;
+ };
+ pinctrl_usart_2: usart2-0 {
+ pinmux = < PIN_PD4__URXD2>, <PIN_PD5__UTXD2>;
+ bias-disable;
+ };
+ pinctrl_usart_3: usart3-0 {
+ pinmux = < PIN_PC12__URXD3>, <PIN_PC13__UTXD3>;
+ bias-disable;
+ };
+ pinctrl_usart_4: usart4-0 {
+ pinmux = < PIN_PB3__URXD4>, <PIN_PB4__UTXD4>;
+ bias-disable;
+ };
+ pinctrl_flx0_default: flx0_usart_default {
+ pinmux = <PIN_PB28__FLEXCOM0_IO0>, //TX
+ <PIN_PB29__FLEXCOM0_IO1>; //RX
+ bias-disable;
+ };
+ pinctrl_flx3_default: flx3_usart_default {
+ pinmux = <PIN_PB22__FLEXCOM3_IO1>, //RX
+ <PIN_PB23__FLEXCOM3_IO0>; //TX
+ bias-disable;
+ };
+ };
+
+ pinctrl_flx4_default: flx4_i2c6_default {
+ pinmux = <PIN_PD12__FLEXCOM4_IO0>, //DATA
+ <PIN_PD13__FLEXCOM4_IO1>; //CLK
+ bias-disable;
+ drive-open-drain = <1>;
+ };
+
+ pinctrl_pwm0 {
+ pinctrl_pwm0_pwm_h0: pwm0_pwm_h0 {
+ pinmux = <PIN_PA30__PWMH0>;
+ bias-disable;
+ };
+ pinctrl_pwm0_pwm_h1: pwm0_pwmh1 {
+ pinmux = <PIN_PB0__PWMH1>;
+ bias-disable;
+ };
+ pinctrl_pwm0_pwm_h2: pwm0_pwm_h2 {
+ pinmux = <PIN_PB5__PWMH2>;
+ bias-disable;
+ };
+ pinctrl_pwm0_pwm_h3: pwm0_pwm_h3 {
+ pinmux = <PIN_PB7__PWMH3>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_adc {
+ pinctrl_adc2: adc2 {
+ pinmux = <PIN_PD21__GPIO>;
+ bias-disable;
+ };
+ pinctrl_adc3: adc3 {
+ pinmux = <PIN_PD22__GPIO>;
+ bias-disable;
+ };
+ pinctrl_adc4: adc4 {
+ pinmux = <PIN_PD23__GPIO>;
+ bias-disable;
+ };
+ pinctrl_adc5: adc5 {
+ pinmux = <PIN_PD24__GPIO>;
+ bias-disable;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart_0>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+/* debug uart */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart_1>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart_2>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart_3>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart_4>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "disabled";
+
+ uart5: serial@200 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+ };
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "disabled";
+
+ uart8: serial@200 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx3_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "disabled";
+ };
+};
+
+&flx4 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "disabled";
+
+ i2c6: i2c@600 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx4_default>;
+ status = "disabled";
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&shutdown_controller {
+ debounce-delay-us = <976>;
+ atmel,wakeup-rtc-timer;
+
+ input@0 {
+ reg = <0>;
+ atmel,wakeup-type = "low";
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&adc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc2
+ &pinctrl_adc3
+ &pinctrl_adc4
+ &pinctrl_adc5>;
+
+ vddana-supply = <&vdd_adc_vddana>;
+ vref-supply = <&vdd_adc_vref>;
+ status = "disabled";
+};
+
+&securam {
+ export;
+
+ /* export overkiz u-boot mode/version and factory */
+ uboot@1400 {
+ reg = <0x1400 0x20>;
+ export;
+ };
+};
diff --git a/arch/arm/boot/dts/at91-kizboxmini-base.dts b/arch/arm/boot/dts/at91-kizboxmini-base.dts
new file mode 100644
index 0000000..81c29ca
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizboxmini-base.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * at91-kizboxmini-base.dts - Device Tree file for Overkiz Kizbox mini
+ * base board
+ *
+ * Copyright (C) 2015 Overkiz SAS
+ * Author: Antoine Aubert <a.aubert@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizboxmini-common.dtsi"
+
+/ {
+ model = "Overkiz Kizbox Mini";
+ compatible = "overkiz,kizboxmini-base", "atmel,at91sam9g25",
+ "atmel,at91sam9x5", "atmel,at91sam9";
+};
+
+&pinctrl_usart0 {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+};
diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi
new file mode 100644
index 0000000..d37724c
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
+ *
+ * Copyright (C) 2014-2018 Overkiz SAS
+ * Author: Antoine Aubert <a.aubert@overkiz.com>
+ * Gaël Portay <g.portay@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ * Dorian Rocipon <d.rocipon@overkiz.com>
+ */
+#include "at91sam9g25.dtsi"
+
+/ {
+ chosen {
+ bootargs = "ubi.mtd=ubi";
+ stdout-path = &dbgu;
+ };
+
+ memory@20000000 {
+ reg = <0x20000000 0x8000000>;
+ };
+
+ clocks {
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ adc_op_clk {
+ status = "disabled";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ prog {
+ label = "PB_PROG";
+ gpios = <&pioC 17 GPIO_ACTIVE_LOW>;
+ linux,code = <0x102>;
+ wakeup-source;
+ };
+
+ reset {
+ label = "PB_RST";
+ gpios = <&pioC 16 GPIO_ACTIVE_LOW>;
+ linux,code = <0x100>;
+ wakeup-source;
+ };
+ };
+
+ leds: pwm_leds {
+ compatible = "pwm-leds";
+
+ led_blue: pwm_blue {
+ label = "pwm:blue:user";
+ pwms = <&pwm0 2 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "none";
+ status = "disabled";
+ };
+
+ led_green: pwm_green {
+ label = "pwm:green:user";
+ pwms = <&pwm0 0 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ };
+
+ led_red: pwm_red {
+ label = "pwm:red:user";
+ pwms = <&pwm0 1 10000000 0>;
+ max-brightness = <255>;
+ linux,default-trigger = "default-on";
+ };
+ };
+};
+
+&usart0 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+};
+
+&macb0 {
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_pwm0_1
+ &pinctrl_pwm0_pwm1_1
+ &pinctrl_pwm0_pwm2_1>;
+ status = "okay";
+};
+
+&dbgu {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&adc0 {
+ status = "disabled";
+};
+
+&rtc {
+ status = "disabled";
+};
+
+&ebi {
+ pinctrl-0 = <&pinctrl_ebi_addr_nand
+ &pinctrl_ebi_data_0_7>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&nand_controller {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_nand_oe_we
+ &pinctrl_nand_cs
+ &pinctrl_nand_rb>;
+ pinctrl-names = "default";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootstrap@0 {
+ label = "bootstrap";
+ reg = <0x0 0x20000>;
+ };
+
+ ubi@20000 {
+ label = "ubi";
+ reg = <0x20000 0x7fe0000>;
+ };
+ };
+ };
+};
+
+&usb0 {
+ num-ports = <1>;
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/at91-kizboxmini-mb.dts b/arch/arm/boot/dts/at91-kizboxmini-mb.dts
new file mode 100644
index 0000000..c07d307
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizboxmini-mb.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015-2018 Overkiz SAS
+ * Author: Mickael Gardet <m.gardet@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizboxmini-common.dtsi"
+
+/ {
+ model = "Overkiz Kizbox Mini Mother Board";
+ compatible = "overkiz,kizboxmini-mb", "atmel,at91sam9g25",
+ "atmel,at91sam9x5", "atmel,at91sam9";
+};
+
+&usb0 {
+ num-ports = <2>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&led_blue {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/at91-kizboxmini-rd.dts b/arch/arm/boot/dts/at91-kizboxmini-rd.dts
new file mode 100644
index 0000000..ab50f4d
--- /dev/null
+++ b/arch/arm/boot/dts/at91-kizboxmini-rd.dts
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015-2018 Overkiz SAS
+ * Author: Mickael Gardet <m.gardet@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizboxmini-common.dtsi"
+
+/ {
+ model = "Overkiz Kizbox Mini RailDIN";
+ compatible = "overkiz,kizboxmini-rd", "atmel,at91sam9g25",
+ "atmel,at91sam9x5", "atmel,at91sam9";
+
+ clocks {
+ adc_op_clk {
+ status = "okay";
+ };
+ };
+};
+
+&pinctrl {
+ adc0 {
+ pinctrl_adc0_ad5: adc0_ad5-0 {
+ /* pull-up disable */
+ atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+};
+
+&usart0 {
+ status = "disabled";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&led_blue {
+ status = "okay";
+};
+
+&adc0 {
+ atmel,adc-vref = <2500>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc0_ad5>;
+ atmel,adc-channels-used = <0x0020>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/at91-kizboxmini.dts b/arch/arm/boot/dts/at91-kizboxmini.dts
deleted file mode 100644
index cb22f5f..0000000
--- a/arch/arm/boot/dts/at91-kizboxmini.dts
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
- *
- * Copyright (C) 2014 Gaël PORTAY <g.portay@overkiz.com>
- */
-/dts-v1/;
-#include "at91sam9g25.dtsi"
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
- model = "Overkiz Kizbox mini";
- compatible = "overkiz,kizboxmini", "atmel,at91sam9g25", "atmel,at91sam9x5", "atmel,at91sam9";
-
- chosen {
- bootargs = "ubi.mtd=ubi";
- stdout-path = &dbgu;
- };
-
- memory {
- reg = <0x20000000 0x8000000>;
- };
-
- clocks {
- slow_xtal {
- clock-frequency = <32768>;
- };
-
- main_xtal {
- clock-frequency = <12000000>;
- };
- };
-
- ahb {
- nand0: nand@40000000 {
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- atmel,has-pmecc;
- atmel,pmecc-cap = <4>;
- atmel,pmecc-sector-size = <512>;
- nand-on-flash-bbt;
- status = "okay";
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-
- prog {
- label = "PB_PROG";
- gpios = <&pioC 17 GPIO_ACTIVE_LOW>;
- linux,code = <0x102>;
- wakeup-source;
- };
-
- reset {
- label = "PB_RST";
- gpios = <&pioC 16 GPIO_ACTIVE_LOW>;
- linux,code = <0x100>;
- wakeup-source;
- };
- };
-
- pwm_leds {
- compatible = "pwm-leds";
-
- green {
- label = "pwm:green:user";
- pwms = <&pwm0 0 10000000 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- };
-
- red {
- label = "pwm:red:user";
- pwms = <&pwm0 1 10000000 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- };
- };
-};
-
-&dbgu {
- status = "okay";
-};
-
-&ebi {
- pinctrl-0 = <&pinctrl_ebi_addr_nand
- &pinctrl_ebi_data_0_7>;
- pinctrl-names = "default";
- status = "okay";
-
- nand-controller {
- pinctrl-0 = <&pinctrl_nand_oe_we
- &pinctrl_nand_cs
- &pinctrl_nand_rb>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@3 {
- reg = <0x3 0x0 0x800000>;
- rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
- nand-bus-width = <8>;
- nand-ecc-mode = "hw";
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- nand-on-flash-bbt;
- label = "atmel_nand";
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- bootstrap@0 {
- label = "bootstrap";
- reg = <0x0 0x20000>;
- };
-
- ubi@20000 {
- label = "ubi";
- reg = <0x20000 0x7fe0000>;
- };
- };
- };
- };
-};
-
-&macb0 {
- phy-mode = "rmii";
- status = "okay";
-};
-
-&pwm0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm0_pwm0_1
- &pinctrl_pwm0_pwm1_1>;
- status = "okay";
-};
-
-&tcb0 {
- timer@0 {
- compatible = "atmel,tcb-timer";
- reg = <0>;
- };
-
- timer@1 {
- compatible = "atmel,tcb-timer";
- reg = <1>;
- };
-};
-
-&usart0 {
- status = "okay";
-};
-
-&usb0 {
- num-ports = <1>;
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/at91-linea.dtsi
index 41f1639..533a440 100644
--- a/arch/arm/boot/dts/at91-linea.dtsi
+++ b/arch/arm/boot/dts/at91-linea.dtsi
@@ -13,7 +13,7 @@
compatible = "axentia,linea",
"atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
};
diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
index f245944..4f12347 100644
--- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
+++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
@@ -8,7 +8,6 @@
*/
/dts-v1/;
#include "at91-linea.dtsi"
-#include "sama5d3_lcd.dtsi"
#include "at91-natte.dtsi"
/ {
diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts
index a50b7fd..969d990 100644
--- a/arch/arm/boot/dts/at91-qil_a9260.dts
+++ b/arch/arm/boot/dts/at91-qil_a9260.dts
@@ -14,7 +14,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
@@ -52,6 +52,7 @@
&pinctrl_mmc0_clk
&pinctrl_mmc0_slot0_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
reg = <0>;
diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts
index 954404e..1e2a28c 100644
--- a/arch/arm/boot/dts/at91-sam9_l9260.dts
+++ b/arch/arm/boot/dts/at91-sam9_l9260.dts
@@ -15,7 +15,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
@@ -49,6 +49,7 @@
&pinctrl_mmc0_clk
&pinctrl_mmc0_slot1_cmd_dat0
&pinctrl_mmc0_slot1_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@1 {
diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
new file mode 100644
index 0000000..b1068cc
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x60.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Microchip SAM9X60-EK";
+ compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+
+ regulators: regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_1v8: fixed-regulator-vdd_1v8@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ status = "okay";
+ };
+
+ vdd_1v5: fixed-regulator-vdd_1v5@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_1V5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ status = "okay";
+ };
+
+ vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD1_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ status = "okay";
+ };
+
+ vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD2_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ status = "okay";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+ status = "okay";
+
+ sw1 {
+ label = "SW1";
+ gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
+ linux,code=<KEY_PROG1>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+ status = "okay"; /* Conflict with pwm0. */
+
+ red {
+ label = "red";
+ gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "green";
+ gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "blue";
+ gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&adc {
+ vddana-supply = <&vdd1_3v3>;
+ vref-supply = <&vdd1_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+ status = "okay";
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_rx_tx>;
+ status = "disabled"; /* Conflict with dbgu. */
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_rx_tx>;
+ status = "okay";
+};
+
+&classd {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_classd_default>;
+ atmel,pwm-type = "diff";
+ atmel,non-overlap-time = <10>;
+ status = "okay";
+};
+
+&dbgu {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ status = "okay"; /* Conflict with can0. */
+};
+
+&ebi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
+ status = "okay";
+
+ nand_controller: nand-controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ uboot@40000 {
+ label = "u-boot";
+ reg = <0x40000 0xc0000>;
+ };
+
+ ubootenvred@100000 {
+ label = "U-Boot Env Redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ ubootenv@140000 {
+ label = "U-Boot Env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x1f800000>;
+ };
+ };
+ };
+ };
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c0: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ atmel,fifo-size = <16>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ status = "okay";
+
+ eeprom@53 {
+ compatible = "atmel,24c32";
+ reg = <0x53>;
+ pagesize = <16>;
+ size = <128>;
+ status = "okay";
+ };
+ };
+};
+
+&flx4 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+ status = "disabled";
+
+ spi0: spi@400 {
+ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+ clock-names = "spi_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx4_default>;
+ atmel,fifo-size = <16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+};
+
+&flx5 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ uart1: serial@200 {
+ compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(10))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+ clock-names = "usart";
+ pinctrl-0 = <&pinctrl_flx5_default>;
+ pinctrl-names = "default";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+};
+
+&flx6 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c1: i2c@600 {
+ compatible = "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx6_default>;
+ atmel,fifo-size = <16>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ status = "okay";
+
+ gpio_exp: mcp23008@20 {
+ compatible = "microchip,mcp23008";
+ reg = <0x20>;
+ };
+ };
+};
+
+&gpbr {
+ status = "okay";
+};
+
+&i2s {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2s_default>;
+ #sound-dai-cells = <0>;
+ status = "disabled"; /* Conflict with QSPI. */
+};
+
+&macb0 {
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ status = "okay";
+
+ ethernet-phy@0 {
+ reg = <0x0>;
+ };
+};
+
+&pinctrl {
+ adc {
+ pinctrl_adc_default: adc_default {
+ atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_adtrg_default: adtrg_default {
+ atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ i2s {
+ pinctrl_i2s_default: i2s {
+ atmel,pins =
+ <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SCK */
+ AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SWS */
+ AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SDIN */
+ AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SDOUT */
+ AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* I2SMCK */
+ };
+ };
+
+ qspi {
+ pinctrl_qspi: qspi {
+ atmel,pins =
+ <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+ AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
+ AT91_PIOB 21 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOB 22 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOB 23 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOB 24 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+ };
+
+ nand {
+ pinctrl_nand_oe_we: nand-oe-we-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_nand_rb: nand-rb-0 {
+ atmel,pins =
+ <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
+ atmel,pins =
+ <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ ebi {
+ pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_ebi_data_0_15: ebi-data-msb-0 {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_addr_nand: ebi-addr-0 {
+ atmel,pins =
+ <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+ };
+
+ flexcom {
+ pinctrl_flx0_default: flx0_twi {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_flx4_default: flx4_spi {
+ atmel,pins =
+ <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_flx5_default: flx_uart {
+ atmel,pins =
+ <AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
+ AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
+ AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_flx6_default: flx6_twi {
+ atmel,pins =
+ <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ classd {
+ pinctrl_classd_default: classd {
+ atmel,pins =
+ <AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+ AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN
+ AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+ AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
+ };
+ };
+
+ can0 {
+ pinctrl_can0_rx_tx: can0_rx_tx {
+ atmel,pins =
+ <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0 */
+ AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX0 */
+ AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN0 mux */
+ AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
+ };
+ };
+
+ can1 {
+ pinctrl_can1_rx_tx: can1_rx_tx {
+ atmel,pins =
+ <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1 RXD1 */
+ AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX1 TXD1 */
+ AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN1 mux */
+ AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
+ };
+ };
+
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+ };
+ };
+
+ pwm0 {
+ pinctrl_pwm0_0: pwm0_0 {
+ atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_1: pwm0_1 {
+ atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_2: pwm0_2 {
+ atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_pwm0_3: pwm0_3 {
+ atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+ };
+
+ sdmmc0 {
+ pinctrl_sdmmc0_default: sdmmc0 {
+ atmel,pins =
+ <AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA17 CK periph A with pullup */
+ AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA16 CMD periph A with pullup */
+ AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA15 DAT0 periph A */
+ AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA18 DAT1 periph A with pullup */
+ AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA19 DAT2 periph A with pullup */
+ AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA20 DAT3 periph A with pullup */
+ };
+ pinctrl_sdmmc0_cd: sdmmc0_cd {
+ atmel,pins =
+ <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ sdmmc1 {
+ pinctrl_sdmmc1_default: sdmmc1 {
+ atmel,pins =
+ <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
+ AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
+ AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
+ AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
+ AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
+ AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
+ };
+ };
+
+ gpio_keys {
+ pinctrl_key_gpio_default: pinctrl_key_gpio {
+ atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ usb0 {
+ pinctrl_usba_vbus: usba_vbus {
+ atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ usb1 {
+ pinctrl_usb_default: usb_default {
+ atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ leds {
+ pinctrl_gpio_leds: gpio_leds {
+ atmel,pins = <AT91_PIOB 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOB 12 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOB 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+}; /* pinctrl */
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
+ status = "disabled"; /* Conflict with leds. */
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default &pinctrl_sdmmc0_cd>;
+ status = "okay";
+ cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+ disable-wp;
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_default>;
+ no-1-8-v;
+ non-removable;
+ status = "disabled"; /* Conflict with flx4. */
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay"; /* Conflict with i2s. */
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+
+ at91bootstrap@0 {
+ label = "qspi: at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "qspi: bootloader";
+ reg = <0x40000 0xc0000>;
+ };
+
+ bootloaderenvred@100000 {
+ label = "qspi: bootloader env redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ bootloaderenv@140000 {
+ label = "qspi: bootloader env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "qspi: device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "qspi: kernel";
+ reg = <0x200000 0x600000>;
+ };
+ };
+};
+
+&rtt {
+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+ status = "okay";
+};
+
+&shutdown_controller {
+ debounce-delay-us = <976>;
+ status = "okay";
+
+ input@0 {
+ reg = <0>;
+ };
+};
+
+&tcb0 {
+ timer0: timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
+&usb0 {
+ atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+};
+
+&usb1 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioD 15 GPIO_ACTIVE_HIGH
+ &pioD 16 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
index ae6d07d..e4824ab 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
@@ -13,6 +13,10 @@
model = "Atmel SAMA5D27 SoM1";
compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
+ aliases {
+ i2c0 = &i2c0;
+ };
+
clocks {
slow_xtal {
clock-frequency = <32768>;
@@ -24,18 +28,54 @@
};
ahb {
+ sdmmc0: sdio-host@a0000000 {
+ microchip,sdcal-inverted;
+ };
+
apb {
qspi1: spi@f0024000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_default>;
flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
+
+ at91bootstrap@00000000 {
+ label = "at91bootstrap";
+ reg = <0x00000000 0x00040000>;
+ };
+
+ bootloader@00040000 {
+ label = "bootloader";
+ reg = <0x00040000 0x000c0000>;
+ };
+
+ bootloaderenvred@00100000 {
+ label = "bootloader env redundant";
+ reg = <0x00100000 0x00040000>;
+ };
+
+ bootloaderenv@00140000 {
+ label = "bootloader env";
+ reg = <0x00140000 0x00040000>;
+ };
+
+ dtb@00180000 {
+ label = "device tree";
+ reg = <0x00180000 0x00080000>;
+ };
+
+ kernel@00200000 {
+ label = "kernel";
+ reg = <0x00200000 0x00600000>;
+ };
};
};
@@ -53,7 +93,25 @@
};
};
+ i2c0: i2c@f8028000 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ status = "okay";
+
+ at24@50 {
+ compatible = "24c02";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+ };
+
pinctrl@fc038000 {
+ pinctrl_i2c0_default: i2c0_default {
+ pinmux = <PIN_PD21__TWD0>,
+ <PIN_PD22__TWCK0>;
+ bias-disable;
+ };
pinctrl_qspi1_default: qspi1_default {
sck_cs {
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index 89f0c99..0a53f21 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -11,6 +11,7 @@
#include "at91-sama5d27_som1.dtsi"
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "Atmel SAMA5D27 SOM1 EK";
@@ -21,7 +22,7 @@
serial1 = &uart4; /* mikro BUS 1 */
serial2 = &uart2; /* mikro BUS 2 */
i2c1 = &i2c1;
- i2c2 = &i2c2;
+ i2c2 = &i2c3;
};
chosen {
@@ -53,6 +54,7 @@
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
+ mmc-ddr-3_3v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
@@ -69,7 +71,6 @@
isc: isc@f0008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>;
- status = "okay";
};
qspi1: spi@f0024000 {
@@ -124,24 +125,19 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
- i2c2: i2c@600 {
- compatible = "atmel,sama5d2-i2c";
- reg = <0x600 0x200>;
- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
+ i2c3: i2c@600 {
dmas = <0>, <0>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
- atmel,fifo-size = <16>;
status = "okay";
};
};
shdwc@f8048010 {
- atmel,shdwc-debouncer = <976>;
+ debounce-delay-us = <976>;
atmel,wakeup-rtc-timer;
input@0 {
@@ -174,27 +170,17 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
status = "disabled";
- uart7: serial@200 {
- compatible = "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
- clock-names = "usart";
+ uart8: serial@200 {
+ dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
- atmel,fifo-size = <32>;
status = "disabled"; /* Conflict with isc. */
};
- spi2: spi@400 {
- compatible = "atmel,at91rm9200-spi";
- reg = <0x400 0x200>;
- interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
- clock-names = "spi_clk";
+ spi5: spi@400 {
+ dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx3_default>;
- atmel,fifo-size = <16>;
status = "disabled"; /* Conflict with isc. */
};
};
@@ -203,48 +189,33 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
status = "okay";
- uart6: serial@200 {
- compatible = "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
- clock-names = "usart";
+ uart9: serial@200 {
+ dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
- atmel,fifo-size = <32>;
- status = "disabled"; /* Conflict with spi3 and i2c3. */
+ status = "disabled"; /* Conflict with spi6 and i2c6. */
};
- spi3: spi@400 {
- compatible = "atmel,at91rm9200-spi";
- reg = <0x400 0x200>;
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
- clock-names = "spi_clk";
+ spi6: spi@400 {
+ dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>;
- atmel,fifo-size = <16>;
- status = "okay"; /* Conflict with uart6 and i2c3. */
+ status = "okay"; /* Conflict with uart5 and i2c6. */
};
- i2c3: i2c@600 {
- compatible = "atmel,sama5d2-i2c";
- reg = <0x600 0x200>;
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
+ i2c6: i2c@600 {
dmas = <0>, <0>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
- atmel,fifo-size = <16>;
- status = "disabled"; /* Conflict with uart6 and spi3. */
+ status = "disabled"; /* Conflict with uart5 and spi6. */
};
};
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
@@ -496,7 +467,7 @@
pb4 {
label = "USER";
gpios = <&pioA PIN_PA29 GPIO_ACTIVE_LOW>;
- linux,code = <0x104>;
+ linux,code = <KEY_PROG1>;
wakeup-source;
};
};
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
new file mode 100644
index 0000000..a06700e
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+ * Author: Eugen Hristev <eugen.hristev@microcihp.com>
+ */
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/pinctrl/at91.h>
+
+/ {
+ model = "Microchip SAMA5D27 WLSOM1";
+ compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+ aliases {
+ i2c0 = &i2c0;
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+};
+
+&flx1 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+
+ uart6: serial@200 {
+ pinctrl-0 = <&pinctrl_flx1_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c1 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+
+ mcp16502@5b {
+ compatible = "microchip,mcp16502";
+ reg = <0x5b>;
+ status = "okay";
+ lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;
+
+ regulators {
+ vdd_3v3: VDD_IO {
+ regulator-name = "VDD_IO";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ vddio_ddr: VDD_DDR {
+ regulator-name = "VDD_DDR";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1200000>;
+ regulator-changeable-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1200000>;
+ regulator-changeable-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ vdd_core: VDD_CORE {
+ regulator-name = "VDD_CORE";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ vdd_ddr: VDD_OTHER {
+ regulator-name = "VDD_OTHER";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ regulator-changeable-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ regulator-changeable-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&macb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_default>;
+ phy-mode = "rmii";
+
+ ethernet-phy@0 {
+ reg = <0x0>;
+ interrupt-parent = <&pioA>;
+ interrupts = <PIN_PB24 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_phy_irq>;
+ };
+};
+
+&pmc {
+ atmel,osc-bypass;
+};
+
+&qspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_default>;
+ status = "disabled";
+
+ qspi1_flash: spi_flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ m25p,fast-read;
+ status = "disabled";
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader@40000 {
+ label = "bootloader";
+ reg = <0x40000 0xc0000>;
+ };
+
+ bootloaderenvred@100000 {
+ label = "bootloader env redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ bootloaderenv@140000 {
+ label = "bootloader env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+ };
+};
+
+&pioA {
+ pinctrl_flx1_default: flx1_usart_default {
+ pinmux = <PIN_PA24__FLEXCOM1_IO0>,
+ <PIN_PA23__FLEXCOM1_IO1>,
+ <PIN_PA25__FLEXCOM1_IO3>,
+ <PIN_PA26__FLEXCOM1_IO4>;
+ bias-disable;
+ };
+
+ pinctrl_i2c0_default: i2c0_default {
+ pinmux = <PIN_PD21__TWD0>,
+ <PIN_PD22__TWCK0>;
+ bias-disable;
+ };
+
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PD19__TWD1>,
+ <PIN_PD20__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_default: macb0_default {
+ pinmux = <PIN_PB14__GTXCK>,
+ <PIN_PB15__GTXEN>,
+ <PIN_PB16__GRXDV>,
+ <PIN_PB17__GRXER>,
+ <PIN_PB18__GRX0>,
+ <PIN_PB19__GRX1>,
+ <PIN_PB20__GTX0>,
+ <PIN_PB21__GTX1>,
+ <PIN_PB22__GMDC>,
+ <PIN_PB23__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PB24__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_qspi1_default: qspi1_default {
+ pinmux = <PIN_PB5__QSPI1_SCK>,
+ <PIN_PB6__QSPI1_CS>,
+ <PIN_PB7__QSPI1_IO0>,
+ <PIN_PB8__QSPI1_IO1>,
+ <PIN_PB9__QSPI1_IO2>,
+ <PIN_PB10__QSPI1_IO3>;
+ bias-pull-up;
+ };
+};
+
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
new file mode 100644
index 0000000..20bcb74
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+ */
+/dts-v1/;
+#include "at91-sama5d27_wlsom1.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Microchip SAMA5D27 WLSOM1 EK";
+ compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+ aliases {
+ serial0 = &uart0; /* DBGU */
+ serial1 = &uart6; /* BT */
+ serial2 = &uart5; /* mikro BUS 2 */
+ serial3 = &uart3; /* mikro BUS 1 */
+ i2c1 = &i2c1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+ status = "okay";
+
+ sw4 {
+ label = "USER BUTTON";
+ gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_PROG1>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led_gpio_default>;
+ status = "okay";
+
+ red {
+ label = "red";
+ gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "green";
+ gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "blue";
+ gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&adc {
+ vddana-supply = <&vdd_3v3>;
+ vref-supply = <&vdd_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc_default>;
+ status = "okay";
+};
+
+&flx0 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ uart5: serial@200 {
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ pinctrl-names = "default";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+};
+
+&flx1 {
+ status = "okay";
+
+ uart6: serial@200 {
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+};
+
+&macb0 {
+ status = "okay";
+};
+
+&pioA {
+ /*
+ * There is no real pinmux for ADC, if the pin
+ * is not requested by another peripheral then
+ * the muxing is done when channel is enabled.
+ * Requesting pins for ADC is GPIO is
+ * encouraged to prevent conflicts and to
+ * disable bias in order to be in the same
+ * state when the pin is not muxed to the adc.
+ */
+ pinctrl_adc_default: adc_default {
+ pinmux = <PIN_PD25__GPIO>,
+ <PIN_PD26__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_flx0_default: flx0_usart_default {
+ pinmux = <PIN_PB28__FLEXCOM0_IO0>,
+ <PIN_PB29__FLEXCOM0_IO1>;
+ bias-disable;
+ };
+
+ pinctrl_key_gpio_default: key_gpio_default {
+ pinmux = <PIN_PB2__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_led_gpio_default: led_gpio_default {
+ pinmux = <PIN_PA6__GPIO>,
+ <PIN_PA7__GPIO>,
+ <PIN_PA8__GPIO>;
+ bias-pull-down;
+ };
+
+ pinctrl_sdmmc0_default: sdmmc0_default {
+ cmd_data {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>;
+ bias-disable;
+ };
+
+ ck_cd_vddsel {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA11__SDMMC0_VDDSEL>,
+ <PIN_PA12__SDMMC0_WP>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart0_default: uart0_default {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+
+ pinctrl_uart3_default: uart3_default {
+ pinmux = <PIN_PB11__URXD3>,
+ <PIN_PB12__UTXD3>;
+ bias-disable;
+ };
+
+ pinctrl_pwm0_default: pwm0_default {
+ pinmux = <PIN_PA31__PWML0>,
+ <PIN_PA30__PWMH0>;
+ bias-disable;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PA10__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PA16__GPIO>;
+ bias-disable;
+ };
+};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default>;
+ status = "okay";
+};
+
+&qspi1 {
+ status = "okay";
+
+ qspi1_flash: spi_flash@0 {
+ status = "okay";
+ };
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ mmc-ddr-3_3v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ status = "okay";
+};
+
+&shutdown_controller {
+ debounce-delay-us = <976>;
+ atmel,wakeup-rtc-timer;
+
+ input@0 {
+ reg = <0>;
+ atmel,wakeup-type = "low";
+ };
+};
+
+&tcb0 {
+ timer0: timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+};
+
+&usb0 {
+ atmel,vbus-gpio = <&pioA PIN_PA16 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+};
+
+&usb1 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioA PIN_PA10 GPIO_ACTIVE_HIGH
+ 0
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+};
+
+&usb2 {
+ phy_type = "hsic";
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
new file mode 100644
index 0000000..308d472
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
@@ -0,0 +1,768 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Radu Pirea & Razvan Stefanescu,
+ * Codrin Ciubotariu <codrin.ciubotariu@microchip.com>,
+ * Cristian Birsan <cristian.birsan@microchip.com>
+ */
+/dts-v1/;
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+/ {
+ model = "Microchip SAMA5D2-ICP";
+ compatible = "microchip,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
+
+ aliases {
+ serial0 = &uart0; /* debug uart0 + mikro BUS 1 */
+ serial1 = &uart1; /* mikro BUS 3 */
+ serial3 = &uart3; /* mikro BUS 2 */
+ serial5 = &uart7; /* flx2 */
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+ status = "okay";
+
+ sw4 {
+ label = "USER_PB1";
+ gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_PROG1>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led_gpio_default>;
+ status = "okay"; /* conflict with pwm0 */
+
+ red {
+ label = "red";
+ gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "green";
+ gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "blue";
+ gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&adc {
+ vddana-supply = <&vdd_io_reg>;
+ vref-supply = <&vdd_io_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
+ status = "okay";
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_default>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
+ status = "okay";
+};
+
+&flx0 { /* mikrobus2 spi */
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+ status = "okay";
+
+ spi2: spi@400 {
+ dmas = <0>, <0>;
+ cs-gpios = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus2_spi &pinctrl_ksz_spi_cs>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0: ksz8563@0 {
+ compatible = "microchip,ksz8563";
+ reg = <0>;
+ reset-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_LOW>;
+
+ spi-max-frequency = <500000>;
+ spi-cpha;
+ spi-cpol;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "cpu";
+ ethernet = <&macb0>;
+ phy-mode = "mii";
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+};
+
+&flx2 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ uart7: serial@200 {
+ pinctrl-0 = <&pinctrl_flx2_default>;
+ pinctrl-names = "default";
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay"; /* Conflict w/ qspi1. */
+ };
+};
+
+&flx3 { /* mikrobus1 spi */
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
+ status = "okay";
+
+ spi5: spi@400 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>;
+ status = "okay";
+ };
+};
+
+&flx4 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c6: i2c@600 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx4_default>;
+ status = "okay";
+
+ mcp16502@5b {
+ compatible = "microchip,mcp16502";
+ reg = <0x5b>;
+ status = "okay";
+ lpm-gpios = <&pioBU 7 GPIO_ACTIVE_LOW>;
+
+ regulators {
+ vdd_io_reg: VDD_IO {
+ regulator-name = "VDD_IO";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ VDD_DDR {
+ regulator-name = "VDD_DDR";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ VDD_CORE {
+ regulator-name = "VDD_CORE";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ VDD_OTHER {
+ regulator-name = "VDD_OTHER";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-initial-mode = <2>;
+ regulator-allowed-modes = <2>, <4>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ regulator-mode = <4>;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-mode = <4>;
+ };
+ };
+
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+
+ regulator-state-standby {
+ regulator-on-in-suspend;
+ };
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ };
+ };
+ };
+};
+
+&i2c0 { /* mikrobus i2c */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus_i2c>;
+ status = "okay";
+};
+
+&i2c1 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <16>;
+ status = "okay";
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c32";
+ reg = <0x52>;
+ pagesize = <16>;
+ status = "disabled";
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c32";
+ reg = <0x53>;
+ pagesize = <16>;
+ status = "disabled";
+ };
+};
+
+&macb0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>;
+ phy-mode = "mii";
+ status = "okay";
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+};
+
+&pioA {
+ pinctrl_adc_default: adc_default {
+ pinmux = <PIN_PD24__GPIO>,
+ <PIN_PD25__GPIO>,
+ <PIN_PD26__GPIO>;
+ bias-disable;
+ };
+
+ /*
+ * The ADTRG pin can work on any edge type.
+ * In here it's being pulled up, so need to
+ * connect it to ground to get an edge e.g.
+ * Trigger can be configured on falling, rise
+ * or any edge, and the pull-up can be changed
+ * to pull-down or left floating according to
+ * needs.
+ */
+ pinctrl_adtrg_default: adtrg_default {
+ pinmux = <PIN_PD31__ADTRG>;
+ bias-pull-up;
+ };
+
+ pinctrl_flx4_default: flx4_default {
+ pinmux = <PIN_PC28__FLEXCOM4_IO0>,
+ <PIN_PC29__FLEXCOM4_IO1>;
+ bias-disable;
+ };
+
+ pinctrl_can0_default: can0_default {
+ pinmux = <PIN_PC10__CANTX0>,
+ <PIN_PC11__CANRX0>;
+ bias-disable;
+ };
+
+ pinctrl_can1_default: can1_default {
+ pinmux = <PIN_PC26__CANTX1>,
+ <PIN_PC27__CANRX1>;
+ bias-disable;
+ };
+
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PD19__TWD1>,
+ <PIN_PD20__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_key_gpio_default: key_gpio_default {
+ pinmux = <PIN_PD0__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_led_gpio_default: led_gpio_default {
+ pinmux = <PIN_PB0__GPIO>,
+ <PIN_PB1__GPIO>,
+ <PIN_PA31__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_qspi1_default: qspi1_default {
+ pinmux = <PIN_PA6__QSPI1_SCK>,
+ <PIN_PA7__QSPI1_IO0>,
+ <PIN_PA8__QSPI1_IO1>,
+ <PIN_PA9__QSPI1_IO2>,
+ <PIN_PA10__QSPI1_IO3>,
+ <PIN_PA11__QSPI1_CS>;
+ bias-disable;
+ };
+
+ pinctrl_sdmmc0_default: sdmmc0_default {
+ cmd_data {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>;
+ bias-disable;
+ };
+
+ ck_cd {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdmmc1_default: sdmmc1_default {
+ cmd_data {
+ pinmux = <PIN_PA18__SDMMC1_DAT0>,
+ <PIN_PA19__SDMMC1_DAT1>,
+ <PIN_PA20__SDMMC1_DAT2>,
+ <PIN_PA21__SDMMC1_DAT3>;
+ bias-disable;
+ };
+
+ ck_cd {
+ pinmux = <PIN_PA22__SDMMC1_CK>,
+ <PIN_PA28__SDMMC1_CMD>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_mikrobus_i2c: mikrobus_i2c {
+ pinmux = <PIN_PD22__TWCK0>,
+ <PIN_PD21__TWD0>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_an: mikrobus1_an {
+ pinmux = <PIN_PD26__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_rst: mikrobus1_rst {
+ pinmux = <PIN_PC5__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs {
+ pinmux = <PIN_PC21__FLEXCOM3_IO3>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_spi: mikrobus1_spi {
+ pinmux = <PIN_PC20__FLEXCOM3_IO0>,
+ <PIN_PC19__FLEXCOM3_IO1>,
+ <PIN_PC18__FLEXCOM3_IO2>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_pwm: mikrobus1_pwm {
+ pinmux = <PIN_PC4__TIOB1>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_int: mikrobus1_int {
+ pinmux = <PIN_PC3__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus1_uart: mikrobus1_uart {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_an: mikrobus2_an {
+ pinmux = <PIN_PD25__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_rst: mikrobus2_rst {
+ pinmux = <PIN_PB24__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs {
+ pinmux = <PIN_PB31__FLEXCOM0_IO3>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_spi: mikrobus2_spi {
+ pinmux = <PIN_PB28__FLEXCOM0_IO0>,
+ <PIN_PB29__FLEXCOM0_IO1>,
+ <PIN_PB30__FLEXCOM0_IO2>;
+ bias-disable;
+ };
+
+ pinctrl_ksz_spi_cs: ksz_spi_cs {
+ pinmux = <PIN_PC0__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_pwm: mikrobus2_pwm {
+ pinmux = <PIN_PB23__TIOB2>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_int: mikrobus2_int {
+ pinmux = <PIN_PB22__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus2_uart: mikrobus2_uart {
+ pinmux = <PIN_PC12__URXD3>,
+ <PIN_PC13__UTXD3>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus3_an: mikrobus3_an {
+ pinmux = <PIN_PD24__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus3_rst: mikrobus3_rst {
+ pinmux = <PIN_PB21__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus3_spi_cs: mikrobus3_spi_cs {
+ pinmux = <PIN_PA17__SPI0_NPCS0>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus3_spi: mikrobus3_spi {
+ pinmux = <PIN_PA14__SPI0_SPCK>,
+ <PIN_PA16__SPI0_MISO>,
+ <PIN_PA15__SPI0_MOSI>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus3_pwm: mikrobus3_pwm {
+ pinmux = <PIN_PB20__TIOB3>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus3_int: mikrobus3_int {
+ pinmux = <PIN_PB18__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_mikrobus3_uart: mikrobus3_uart {
+ pinmux = <PIN_PC7__URXD1>,
+ <PIN_PC8__UTXD1>;
+ bias-disable;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PC17__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PD23__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_pwm0_pwm2_default: pwm0_pwm2_default {
+ pinmux = <PIN_PB5__PWMH2>,
+ <PIN_PB6__PWML2>;
+ bias-pull-up;
+ };
+
+ pinctrl_macb0_default: macb0_default {
+ pinmux = <PIN_PD1__GRXCK>,
+ <PIN_PD2__GTXER>,
+ <PIN_PD5__GRX2>,
+ <PIN_PD6__GRX3>,
+ <PIN_PD7__GTX2>,
+ <PIN_PD8__GTX3>,
+ <PIN_PD9__GTXCK>,
+ <PIN_PD10__GTXEN>,
+ <PIN_PD11__GRXDV>,
+ <PIN_PD12__GRXER>,
+ <PIN_PD13__GRX0>,
+ <PIN_PD14__GRX1>,
+ <PIN_PD15__GTX0>,
+ <PIN_PD16__GTX1>,
+ <PIN_PD17__GMDC>,
+ <PIN_PD18__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PD3__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_rst: macb0_sw_rst {
+ pinmux = <PIN_PD4__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_flx2_default: flx2_default {
+ pinmux = <PIN_PA6__FLEXCOM2_IO0>,
+ <PIN_PA7__FLEXCOM2_IO1>,
+ <PIN_PA9__FLEXCOM2_IO3>,
+ <PIN_PA10__FLEXCOM2_IO4>;
+ bias-disable;
+ };
+};
+
+&pwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_pwm2_default>;
+ status = "disabled"; /* conflict with leds, HSIC */
+};
+
+&qspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_default>;
+ status = "disabled"; /* Conflict with wilc_pwrseq, flx2 */
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+
+ at91bootstrap@0 {
+ label = "qspi: at91bootstrap";
+ reg = <0x00000000 0x00040000>;
+ };
+
+ bootloader@40000 {
+ label = "qspi: bootloader";
+ reg = <0x00040000 0x000c0000>;
+ };
+
+ bootloaderenvred@100000 {
+ label = "qspi: bootloader env redundant";
+ reg = <0x00100000 0x00040000>;
+ };
+
+ bootloaderenv@140000 {
+ label = "qspi: bootloader env";
+ reg = <0x00140000 0x00040000>;
+ };
+
+ dtb@180000 {
+ label = "qspi: device tree";
+ reg = <0x00180000 0x00080000>;
+ };
+
+ kernel@200000 {
+ label = "qspi: kernel";
+ reg = <0x00200000 0x00600000>;
+ };
+ };
+};
+
+&sdmmc0 {
+ no-1-8-v;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ status = "okay";
+};
+
+&shutdown_controller {
+ debounce-delay-us = <976>;
+ atmel,wakeup-rtc-timer;
+
+ input@0 {
+ reg = <0>;
+ atmel,wakeup-type = "low";
+ };
+};
+
+&spi0 { /* mikrobus3 spi */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus3_spi &pinctrl_mikrobus3_spi_cs>;
+ status = "okay";
+};
+
+&tcb0 {
+ timer0: timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer1: timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus1_uart>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus3_uart>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mikrobus2_uart>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+};
+
+&usb0 {
+ atmel,vbus-gpio = <&pioA PIN_PD23 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+};
+
+&usb1 {
+ num-ports = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+};
+
+&usb2 {
+ phy_type = "hsic";
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
index b8db77b..317c6dd 100644
--- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -11,6 +11,7 @@
#include "sama5d2-pinfunc.h"
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/at91.h>
/ {
@@ -18,9 +19,9 @@
compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";
aliases {
- serial0 = &uart0;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
+ serial0 = &uart0; /* DBGU */
+ i2c0 = &i2c0; /* mikroBUS 1 */
+ i2c1 = &i2c1; /* XPRO EXT1 */
i2c2 = &i2c2;
};
@@ -178,8 +179,11 @@
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@@ -188,23 +192,18 @@
status = "okay";
i2c2: i2c@600 {
- compatible = "atmel,sama5d2-i2c";
- reg = <0x600 0x200>;
- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <0>, <0>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_flx0_default>;
- atmel,fifo-size = <16>;
+ pinctrl-1 = <&pinctrl_flx0_gpio>;
+ sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
};
shdwc@f8048010 {
- atmel,shdwc-debouncer = <976>;
+ debounce-delay-us = <976>;
input@0 {
reg = <0>;
@@ -224,8 +223,11 @@
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&pioA PIN_PC6 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PC7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
at24@50 {
@@ -242,18 +244,36 @@
bias-disable;
};
+ pinctrl_flx0_gpio: flx0_gpio {
+ pinmux = <PIN_PB28__GPIO>,
+ <PIN_PB29__GPIO>;
+ bias-disable;
+ };
+
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
+ pinctrl_i2c0_gpio: i2c0_gpio {
+ pinmux = <PIN_PD21__GPIO>,
+ <PIN_PD22__GPIO>;
+ bias-disable;
+ };
+
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PC6__TWD1>,
<PIN_PC7__TWCK1>;
bias-disable;
};
+ pinctrl_i2c1_gpio: i2c1_gpio {
+ pinmux = <PIN_PC6__GPIO>,
+ <PIN_PC7__GPIO>;
+ bias-disable;
+ };
+
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PA10__GPIO>;
bias-pull-up;
@@ -384,7 +404,8 @@
bp1 {
label = "PB_USER";
gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>;
- linux,code = <0x104>;
+ linux,code = <KEY_PROG1>;
+ wakeup-source;
};
};
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index 808e399..08c5182 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -10,12 +10,20 @@
#include "sama5d2-pinfunc.h"
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/regulator/active-semi,8945a-regulator.h>
/ {
model = "Atmel SAMA5D2 Xplained";
compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5";
+ aliases {
+ serial0 = &uart1; /* DBGU */
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2; /* XPRO EXT2 */
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -72,6 +80,58 @@
};
apb {
+ qspi0: spi@f0020000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi0_default>;
+ status = "disabled"; /* conflict with sdmmc1 */
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+
+ at91bootstrap@00000000 {
+ label = "at91bootstrap";
+ reg = <0x00000000 0x00040000>;
+ };
+
+ bootloader@00040000 {
+ label = "bootloader";
+ reg = <0x00040000 0x000c0000>;
+ };
+
+ bootloaderenvred@00100000 {
+ label = "bootloader env redundant";
+ reg = <0x00100000 0x00040000>;
+ };
+
+ bootloaderenv@00140000 {
+ label = "bootloader env";
+ reg = <0x00140000 0x00040000>;
+ };
+
+ dtb@00180000 {
+ label = "device tree";
+ reg = <0x00180000 0x00080000>;
+ };
+
+ kernel@00200000 {
+ label = "kernel";
+ reg = <0x00200000 0x00600000>;
+ };
+
+ misc@00800000 {
+ label = "misc";
+ reg = <0x00800000 0x00000000>;
+ };
+ };
+ };
+
spi0: spi@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
@@ -109,16 +169,6 @@
};
};
- pdmic@f8018000 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pdmic_default>;
- atmel,model = "PDMIC @ sama5d2_xplained";
- atmel,mic-min-freq = <1000000>;
- atmel,mic-max-freq = <3246000>;
- atmel,mic-offset = <0x0>;
- status = "okay";
- };
-
uart1: serial@f8020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
@@ -129,8 +179,11 @@
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-sda-hold-time-ns = <350>;
status = "okay";
@@ -272,20 +325,29 @@
status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */
uart5: serial@200 {
- compatible = "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
- clock-names = "usart";
+ dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
- atmel,fifo-size = <32>;
status = "okay";
};
+
+ i2c2: i2c@600 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-sda-hold-time-ns = <350>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */
+ };
};
shdwc@f8048010 {
- atmel,shdwc-debouncer = <976>;
+ debounce-delay-us = <976>;
atmel,wakeup-rtc-timer;
input@0 {
@@ -322,26 +384,30 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
- i2c2: i2c@600 {
- compatible = "atmel,sama5d2-i2c";
- reg = <0x600 0x200>;
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
+ i2c6: i2c@600 {
dmas = <0>, <0>;
- dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_flx4_default>;
- atmel,fifo-size = <16>;
+ pinctrl-1 = <&pinctrl_flx4_gpio>;
+ sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
status = "okay";
};
};
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
at24@54 {
@@ -415,14 +481,18 @@
bias-pull-up;
};
- pinctrl_classd_default: classd_default {
+ pinctrl_classd_default_pfets: classd_default_pfets {
pinmux = <PIN_PB1__CLASSD_R0>,
- <PIN_PB2__CLASSD_R1>,
- <PIN_PB3__CLASSD_R2>,
- <PIN_PB4__CLASSD_R3>;
+ <PIN_PB3__CLASSD_R2>;
bias-pull-up;
};
+ pinctrl_classd_default_nfets: classd_default_nfets {
+ pinmux = <PIN_PB2__CLASSD_R1>,
+ <PIN_PB4__CLASSD_R3>;
+ bias-pull-down;
+ };
+
pinctrl_flx0_default: flx0_default {
pinmux = <PIN_PB28__FLEXCOM0_IO0>,
<PIN_PB29__FLEXCOM0_IO1>;
@@ -435,18 +505,42 @@
bias-disable;
};
+ pinctrl_flx4_gpio: flx4_gpio {
+ pinmux = <PIN_PD12__GPIO>,
+ <PIN_PD13__GPIO>;
+ bias-disable;
+ };
+
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
+ pinctrl_i2c0_gpio: i2c0_gpio {
+ pinmux = <PIN_PD21__GPIO>,
+ <PIN_PD22__GPIO>;
+ bias-disable;
+ };
+
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
+ pinctrl_i2c1_gpio: i2c1_gpio {
+ pinmux = <PIN_PD4__GPIO>,
+ <PIN_PD5__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_i2c2_gpio: i2c2_gpio {
+ pinmux = <PIN_PB28__GPIO>,
+ <PIN_PB29__GPIO>;
+ bias-disable;
+ };
+
pinctrl_i2s0_default: i2s0_default {
pinmux = <PIN_PC1__I2SC0_CK>,
<PIN_PC2__I2SC0_MCK>,
@@ -496,10 +590,20 @@
bias-disable;
};
- pinctrl_pdmic_default: pdmic_default {
- pinmux = <PIN_PB26__PDMIC_DAT>,
- <PIN_PB27__PDMIC_CLK>;
- bias-disable;
+ pinctrl_qspi0_default: qspi0_default {
+ sck_cs {
+ pinmux = <PIN_PA22__QSPI0_SCK>,
+ <PIN_PA23__QSPI0_CS>;
+ bias-disable;
+ };
+
+ data {
+ pinmux = <PIN_PA24__QSPI0_IO0>,
+ <PIN_PA25__QSPI0_IO1>,
+ <PIN_PA26__QSPI0_IO2>,
+ <PIN_PA27__QSPI0_IO3>;
+ bias-pull-up;
+ };
};
pinctrl_sdmmc0_default: sdmmc0_default {
@@ -581,7 +685,7 @@
classd: classd@fc048000 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_classd_default>;
+ pinctrl-0 = <&pinctrl_classd_default_pfets &pinctrl_classd_default_nfets>;
atmel,pwm-type = "diff";
atmel,non-overlap-time = <10>;
status = "okay";
@@ -610,7 +714,7 @@
bp1 {
label = "PB_USER";
gpios = <&pioA PIN_PB9 GPIO_ACTIVE_LOW>;
- linux,code = <0x104>;
+ linux,code = <KEY_PROG1>;
wakeup-source;
};
};
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index 400eaf6..cc55d16 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -7,6 +7,7 @@
*/
/dts-v1/;
#include "sama5d36.dtsi"
+#include <dt-bindings/input/input.h>
/ {
model = "SAMA5D3 Xplained";
@@ -16,7 +17,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x10000000>;
};
@@ -56,6 +57,8 @@
};
spi0: spi@f0004000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_cs>;
cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
status = "okay";
};
@@ -128,7 +131,7 @@
};
macb0: ethernet@f0028000 {
- phy-mode = "rgmii";
+ phy-mode = "rgmii-rxid";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
@@ -168,6 +171,8 @@
};
spi1: spi@f8008000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_cs>;
cs-gpios = <&pioC 25 0>;
status = "okay";
};
@@ -247,6 +252,26 @@
<AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
+
+ pinctrl_gpio_leds: gpio_leds_default {
+ atmel,pins =
+ <AT91_PIOE 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi0_cs: spi0_cs_default {
+ atmel,pins =
+ <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_spi1_cs: spi1_cs_default {
+ atmel,pins = <AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_vcc_mmc0_reg_gpio: vcc_mmc0_reg_gpio_default {
+ atmel,pins = <AT91_PIOE 2 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
};
};
};
@@ -338,6 +363,8 @@
vcc_mmc0_reg: fixedregulator_mmc0 {
compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>;
gpio = <&pioE 2 GPIO_ACTIVE_LOW>;
regulator-name = "mmc0-card-supply";
regulator-min-microvolt = <3300000>;
@@ -354,13 +381,16 @@
bp3 {
label = "PB_USER";
gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
- linux,code = <0x104>;
+ linux,code = <KEY_PROG1>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+ status = "okay";
d2 {
label = "d2";
diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
index 0be184a..710cb72 100644
--- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
@@ -9,7 +9,7 @@
model = "Aries/DENX MA5D4";
compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5";
- memory {
+ memory@20000000 {
reg = <0x20000000 0x10000000>;
};
diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
index af49694..4d7cee5 100644
--- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
@@ -136,7 +136,7 @@
panel: panel {
/* Actually Ampire 800480R2 */
- compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
+ compatible = "foxlink,fl500wvr00-a0t";
backlight = <&backlight>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
index 1d10106..e42dae0 100644
--- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
@@ -16,7 +16,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x20000000>;
};
@@ -49,6 +49,7 @@
};
i2c0: i2c@f8014000 {
+ i2c-digital-filter;
status = "okay";
};
@@ -89,6 +90,8 @@
};
spi1: spi@fc018000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_cs>;
cs-gpios = <&pioB 21 0>;
status = "okay";
};
@@ -146,6 +149,19 @@
atmel,pins =
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
+ pinctrl_spi0_cs: spi0_cs_default {
+ atmel,pins =
+ <AT91_PIOB 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_gpio_leds: gpio_leds_default {
+ atmel,pins =
+ <AT91_PIOD 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOE 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_vcc_mmc1_reg: vcc_mmc1_reg {
+ atmel,pins =
+ <AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
};
};
};
@@ -251,6 +267,8 @@
leds {
compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
status = "okay";
d8 {
@@ -277,6 +295,8 @@
vcc_mmc1_reg: fixedregulator_mmc1 {
compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vcc_mmc1_reg>;
gpio = <&pioE 4 GPIO_ACTIVE_LOW>;
regulator-name = "VDD MCI1";
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
index 0cc1cff..fe432b6 100644
--- a/arch/arm/boot/dts/at91-sama5d4ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -16,7 +16,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/at91-smartkiz.dts b/arch/arm/boot/dts/at91-smartkiz.dts
new file mode 100644
index 0000000..106f23b
--- /dev/null
+++ b/arch/arm/boot/dts/at91-smartkiz.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017-2018 Overkiz SAS
+ * Author: Mickael Gardet <m.gardet@overkiz.com>
+ * Kévin Raymond <k.raymond@overkiz.com>
+ * Dorian Rocipon <d.rocipon@overkiz.com>
+ */
+/dts-v1/;
+#include "at91-kizboxmini-common.dtsi"
+
+/ {
+ model = "Overkiz SmartKiz";
+ compatible = "overkiz,smartkiz", "atmel,at91sam9g25",
+ "atmel,at91sam9x5", "atmel,at91sam9";
+
+ clocks {
+ adc_op_clk {
+ status = "okay";
+ };
+ };
+
+ aliases {
+ serial5 = &uart0;
+ };
+
+ pio_keys {
+ hk_reset {
+ label = "HK_RESET";
+ gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_rf {
+ label = "POWER_RF";
+ gpios = <&pioA 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_wifi {
+ label = "POWER_WIFI";
+ gpios = <&pioA 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&pinctrl {
+ i2c1 {
+ pinctrl_i2c1: i2c1-0 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
+ AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ adc0 {
+ pinctrl_adc0_ad0: adc0_ad0-0 {
+ /* pull-up disable */
+ atmel,pins = <AT91_PIOB 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad5: adc0_ad5-0 {
+ /* pull-up disable */
+ atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad6: adc0_ad6-0 {
+ /* pull-up disable */
+ atmel,pins = <AT91_PIOB 17 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ pinctrl_adc0_ad11: adc0_ad11-0 {
+ /* pull-up disable */
+ atmel,pins = <AT91_PIOB 10 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+};
+
+&i2c1 {
+ dmas = <0>, <0>;
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "disabled";
+};
+
+&macb0 {
+ status = "disabled";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&leds {
+ blue {
+ status = "okay";
+ };
+};
+
+&adc0 {
+ atmel,adc-vref = <2500>;
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_adc0_ad0
+ &pinctrl_adc0_ad5
+ &pinctrl_adc0_ad6
+ &pinctrl_adc0_ad11
+ >;
+ atmel,adc-channels-used = <0x0861>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/at91-som60.dtsi b/arch/arm/boot/dts/at91-som60.dtsi
index 241682a..39474a1 100644
--- a/arch/arm/boot/dts/at91-som60.dtsi
+++ b/arch/arm/boot/dts/at91-som60.dtsi
@@ -16,7 +16,7 @@
stdout-path = &dbgu;
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x8000000>;
};
diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts
index 3ca97b4..7e5c598 100644
--- a/arch/arm/boot/dts/at91-tse850-3.dts
+++ b/arch/arm/boot/dts/at91-tse850-3.dts
@@ -262,7 +262,7 @@
&macb1 {
status = "okay";
- phy-mode = "rgmii";
+ phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts
index 15050fd..a51a337 100644
--- a/arch/arm/boot/dts/at91-vinco.dts
+++ b/arch/arm/boot/dts/at91-vinco.dts
@@ -17,7 +17,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
diff --git a/arch/arm/boot/dts/at91-wb45n.dtsi b/arch/arm/boot/dts/at91-wb45n.dtsi
index ebe61a2..430c753 100644
--- a/arch/arm/boot/dts/at91-wb45n.dtsi
+++ b/arch/arm/boot/dts/at91-wb45n.dtsi
@@ -17,7 +17,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
@@ -145,6 +145,7 @@
};
&mmc0 {
+ pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/at91-wb50n.dtsi
index 4ed8500..74b249b 100644
--- a/arch/arm/boot/dts/at91-wb50n.dtsi
+++ b/arch/arm/boot/dts/at91-wb50n.dtsi
@@ -17,7 +17,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
};
@@ -46,10 +46,6 @@
atmel,osc-bypass;
};
-&usart1_clk {
- atmel,clk-output-range = <0 132000000>;
-};
-
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 4438571..d1181ea 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -39,16 +39,17 @@
ssc2 = &ssc2;
};
cpus {
- #address-cells = <0>;
+ #address-cells = <1>;
#size-cells = <0>;
- cpu {
+ cpu@0 {
compatible = "arm,arm920t";
device_type = "cpu";
+ reg = <0>;
};
};
- memory {
+ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x04000000>;
};
@@ -70,6 +71,9 @@
sram: sram@200000 {
compatible = "mmio-sram";
reg = <0x00200000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00200000 0x4000>;
};
ahb {
@@ -101,259 +105,9 @@
compatible = "atmel,at91rm9200-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91rm9200-clk-main";
- #clock-cells = <0>;
- clocks = <&main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <3>;
- atmel,pll-clk-output-ranges = <80000000 160000000 0>,
- <150000000 180000000 2>;
- };
-
- pllb: pllbck {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKB>;
- clocks = <&main>;
- reg = <1>;
- atmel,clk-input-range = <1000000 32000000>;
- #atmel,pll-clk-output-range-cells = <3>;
- atmel,pll-clk-output-ranges = <80000000 160000000 0>,
- <150000000 180000000 2>;
- };
-
- mck: masterck {
- compatible = "atmel,at91rm9200-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
- atmel,clk-output-range = <0 80000000>;
- atmel,clk-divisors = <1 2 3 4>;
- };
-
- usb: usbck {
- compatible = "atmel,at91rm9200-clk-usb";
- #clock-cells = <0>;
- atmel,clk-divisors = <1 2 0 0>;
- clocks = <&pllb>;
- };
-
- prog: progck {
- compatible = "atmel,at91rm9200-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
-
- prog2: prog2 {
- #clock-cells = <0>;
- reg = <2>;
- interrupts = <AT91_PMC_PCKRDY(2)>;
- };
-
- prog3: prog3 {
- #clock-cells = <0>;
- reg = <3>;
- interrupts = <AT91_PMC_PCKRDY(3)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <2>;
- clocks = <&usb>;
- };
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <4>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
-
- pck2: pck2 {
- #clock-cells = <0>;
- reg = <10>;
- clocks = <&prog2>;
- };
-
- pck3: pck3 {
- #clock-cells = <0>;
- reg = <11>;
- clocks = <&prog3>;
- };
- };
-
- periphck {
- compatible = "atmel,at91rm9200-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- pioC_clk: pioC_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- pioD_clk: pioD_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- udc_clk: udc_clk {
- #clock-cells = <0>;
- reg = <11>;
- };
-
- twi0_clk: twi0_clk {
- reg = <12>;
- #clock-cells = <0>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- ssc2_clk: ssc2_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- tc0_clk: tc0_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- tc1_clk: tc1_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- tc2_clk: tc2_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- tc3_clk: tc3_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- tc4_clk: tc4_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- tc5_clk: tc5_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- ohci_clk: ohci_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
-
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <24>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&slow_xtal>, <&main_xtal>;
+ clock-names = "slow_xtal", "main_xtal";
};
st: timer@fffffd00 {
@@ -383,7 +137,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -395,7 +149,7 @@
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
21 IRQ_TYPE_LEVEL_HIGH 0
22 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -405,7 +159,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_twi>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -415,11 +169,10 @@
compatible = "atmel,hsmci";
reg = <0xfffb4000 0x4000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default";
status = "disabled";
};
@@ -429,7 +182,7 @@
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "pclk";
status = "disabled";
};
@@ -440,7 +193,7 @@
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
- clocks = <&ssc1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "pclk";
status = "disabled";
};
@@ -451,7 +204,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
- clocks = <&ssc2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "pclk";
status = "disabled";
};
@@ -463,7 +216,7 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
- clocks = <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "ether_clk";
status = "disabled";
};
@@ -803,7 +556,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@@ -814,7 +567,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
@@ -825,7 +578,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioC_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioD: gpio@fffffa00 {
@@ -836,7 +589,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
};
};
@@ -846,7 +599,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -859,7 +612,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -872,7 +625,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -885,7 +638,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -898,7 +651,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "usart";
status = "disabled";
};
@@ -907,7 +660,7 @@
compatible = "atmel,at91rm9200-udc";
reg = <0xfffb0000 0x4000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udc_clk>, <&udpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 2>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -920,7 +673,7 @@
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -947,7 +700,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00300000 0x100000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 4>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index 1e0bf5a..e1ef4e4 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -15,7 +15,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 16c6fd3..82c5d7f 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -36,16 +36,17 @@
ssc0 = &ssc0;
};
cpus {
- #address-cells = <0>;
+ #address-cells = <1>;
#size-cells = <0>;
- cpu {
+ cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
+ reg = <0>;
};
};
- memory {
+ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x04000000>;
};
@@ -73,6 +74,9 @@
sram0: sram@2ff000 {
compatible = "mmio-sram";
reg = <0x002ff000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x002ff000 0x2000>;
};
ahb {
@@ -650,7 +654,6 @@
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
- pinctrl-names = "default";
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "mci_clk";
status = "disabled";
@@ -738,7 +741,7 @@
status = "disabled";
};
- watchdog@fffffd40 {
+ watchdog: watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -793,7 +796,7 @@
};
};
- i2c-gpio-0 {
+ i2c_gpio0: i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
&pioA 24 GPIO_ACTIVE_HIGH /* scl */
diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts
index 81f808a..ce96345 100644
--- a/arch/arm/boot/dts/at91sam9260ek.dts
+++ b/arch/arm/boot/dts/at91sam9260ek.dts
@@ -7,6 +7,7 @@
*/
/dts-v1/;
#include "at91sam9260.dtsi"
+#include <dt-bindings/input/input.h>
/ {
model = "Atmel at91sam9260ek";
@@ -16,7 +17,7 @@
stdout-path = &dbgu;
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
@@ -55,6 +56,7 @@
&pinctrl_mmc0_clk
&pinctrl_mmc0_slot1_cmd_dat0
&pinctrl_mmc0_slot1_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@1 {
reg = <1>;
@@ -155,7 +157,7 @@
btn4 {
label = "Button 4";
gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
- linux,code = <0x104>;
+ linux,code = <KEY_PROG1>;
wakeup-source;
};
};
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 5ed3d74..7adc36c 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -33,16 +33,17 @@
};
cpus {
- #address-cells = <0>;
+ #address-cells = <1>;
#size-cells = <0>;
- cpu {
+ cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
+ reg = <0>;
};
};
- memory {
+ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x08000000>;
};
@@ -64,6 +65,9 @@
sram: sram@300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x28000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00300000 0x28000>;
};
ahb {
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
index c4ef74f..beed819 100644
--- a/arch/arm/boot/dts/at91sam9261ek.dts
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -16,7 +16,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 5c990cf..fe45d96 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -35,16 +35,17 @@
};
cpus {
- #address-cells = <0>;
+ #address-cells = <1>;
#size-cells = <0>;
- cpu {
+ cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
+ reg = <0>;
};
};
- memory {
+ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x08000000>;
};
@@ -66,11 +67,17 @@
sram0: sram@300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x14000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00300000 0x14000>;
};
sram1: sram@500000 {
compatible = "mmio-sram";
reg = <0x00500000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00500000 0x4000>;
};
ahb {
@@ -647,7 +654,6 @@
compatible = "atmel,hsmci";
reg = <0xfff80000 0x600>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
@@ -659,7 +665,6 @@
compatible = "atmel,hsmci";
reg = <0xfff84000 0x600>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 62d2185..71f6057 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -16,7 +16,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
@@ -72,6 +72,7 @@
&pinctrl_mmc0_clk
&pinctrl_mmc0_slot0_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
reg = <0>;
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 4117cf8..708e164 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -11,7 +11,7 @@
model = "Atmel AT91SAM9G20 family SoC";
compatible = "atmel,at91sam9g20";
- memory {
+ memory@20000000 {
reg = <0x20000000 0x08000000>;
};
@@ -22,6 +22,9 @@
sram1: sram@2fc000 {
compatible = "mmio-sram";
reg = <0x002fc000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x002fc000 0x8000>;
};
ahb {
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index bda2270..87bb390 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -5,6 +5,7 @@
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*/
#include "at91sam9g20.dtsi"
+#include <dt-bindings/input/input.h>
/ {
@@ -13,7 +14,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
@@ -93,6 +94,7 @@
&pinctrl_mmc0_clk
&pinctrl_mmc0_slot1_cmd_dat0
&pinctrl_mmc0_slot1_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@1 {
reg = <1>;
@@ -233,7 +235,7 @@
btn4 {
label = "Button 4";
gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
- linux,code = <0x104>;
+ linux,code = <KEY_PROG1>;
wakeup-source;
};
};
diff --git a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts
new file mode 100644
index 0000000..7da70ae
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Device Tree file for the GARDENA smart Gateway (Article No. 19000)
+ *
+ * Copyright (C) 2020 GARDENA GmbH
+ */
+
+/dts-v1/;
+
+#include "at91sam9g25.dtsi"
+#include "at91sam9x5ek.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "GARDENA smart Gateway (Article No. 19000)";
+ compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9g25", "atmel,at91sam9x5",
+ "atmel,at91sam9";
+
+ aliases {
+ serial1 = &usart3;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user_btn1 {
+ label = "USER_BTN1";
+ gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_PROG1>;
+ };
+ };
+
+ 1wire_cm {
+ status = "disabled";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power_blue {
+ label = "smartgw:power:blue";
+ gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ power_green {
+ label = "smartgw:power:green";
+ gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ power_red {
+ label = "smartgw:power:red";
+ gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ radio_blue {
+ label = "smartgw:radio:blue";
+ gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ radio_green {
+ label = "smartgw:radio:green";
+ gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ radio_red {
+ label = "smartgw:radio:red";
+ gpios = <&pioC 16 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ internet_blue {
+ label = "smartgw:internet:blue";
+ gpios = <&pioC 15 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ internet_green {
+ label = "smartgw:internet:green";
+ gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ internet_red {
+ label = "smartgw:internet:red";
+ gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ heartbeat {
+ label = "smartgw:heartbeat";
+ gpios = <&pioB 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ pb18 {
+ status = "disabled";
+ };
+
+ pd21 {
+ status = "disabled";
+ };
+ };
+};
+
+&macb0 {
+ phy-mode = "rmii";
+ status = "okay";
+};
+
+&usart0 {
+ status = "disabled";
+};
+
+&usart2 {
+ status = "disabled";
+};
+
+&usart3 {
+ status = "okay";
+
+ pinctrl-0 = <&pinctrl_usart3
+ &pinctrl_usart3_rts
+ &pinctrl_usart3_cts
+ >;
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&mmc0 {
+ status = "disabled";
+};
+
+&mmc1 {
+ status = "disabled";
+};
+
+&spi0 {
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "disabled";
+};
+
+&adc0 {
+ status = "disabled";
+};
+
+&ssc0 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index fd17909..19fc748 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -41,16 +41,17 @@
pwm0 = &pwm0;
};
cpus {
- #address-cells = <0>;
+ #address-cells = <1>;
#size-cells = <0>;
- cpu {
+ cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
+ reg = <0>;
};
};
- memory {
+ memory@70000000 {
device_type = "memory";
reg = <0x70000000 0x10000000>;
};
@@ -78,6 +79,9 @@
sram: sram@300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00300000 0x10000>;
};
ahb {
@@ -103,14 +107,14 @@
ramc0: ramc@ffffe400 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe400 0x200>;
- clocks = <&ddrck>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>;
clock-names = "ddrck";
};
ramc1: ramc@ffffe600 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe600 0x200>;
- clocks = <&ddrck>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>;
clock-names = "ddrck";
};
@@ -128,271 +132,9 @@
compatible = "atmel,at91sam9g45-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91rm9200-clk-main";
- #clock-cells = <0>;
- clocks = <&main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <2000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <745000000 800000000 0 0
- 695000000 750000000 1 0
- 645000000 700000000 2 0
- 595000000 650000000 3 0
- 545000000 600000000 0 1
- 495000000 555000000 1 1
- 445000000 500000000 2 1
- 400000000 450000000 3 1>;
- };
-
- plladiv: plladivck {
- compatible = "atmel,at91sam9x5-clk-plldiv";
- #clock-cells = <0>;
- clocks = <&plla>;
- };
-
- utmi: utmick {
- compatible = "atmel,at91sam9x5-clk-utmi";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKU>;
- clocks = <&main>;
- };
-
- mck: masterck {
- compatible = "atmel,at91rm9200-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
- atmel,clk-output-range = <0 133333333>;
- atmel,clk-divisors = <1 2 4 3>;
- };
-
- usb: usbck {
- compatible = "atmel,at91sam9x5-clk-usb";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- prog: progck {
- compatible = "atmel,at91sam9g45-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ddrck: ddrck {
- #clock-cells = <0>;
- reg = <2>;
- clocks = <&mck>;
- };
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
- };
-
- periphck {
- compatible = "atmel,at91rm9200-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- pioC_clk: pioC_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- pioDE_clk: pioDE_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- trng_clk: trng_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <11>;
- };
-
- twi0_clk: twi0_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- twi1_clk: twi1_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- tcb0_clk: tcb0_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- dma0_clk: dma0_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- uhphs_clk: uhphs_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- lcd_clk: lcd_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
-
- ac97_clk: ac97_clk {
- #clock-cells = <0>;
- reg = <24>;
- };
-
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
-
- isi_clk: isi_clk {
- #clock-cells = <0>;
- reg = <26>;
- };
-
- udphs_clk: udphs_clk {
- #clock-cells = <0>;
- reg = <27>;
- };
-
- aestdessha_clk: aestdessha_clk {
- #clock-cells = <0>;
- reg = <28>;
- };
-
- mci1_clk: mci1_clk {
- #clock-cells = <0>;
- reg = <29>;
- };
-
- vdec_clk: vdec_clk {
- #clock-cells = <0>;
- reg = <30>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
};
rstc@fffffd00 {
@@ -405,7 +147,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
@@ -421,7 +163,7 @@
#size-cells = <0>;
reg = <0xfff7c000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -431,7 +173,7 @@
#size-cells = <0>;
reg = <0xfffd4000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -440,7 +182,7 @@
reg = <0xffffec00 0x200>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
- clocks = <&dma0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "dma_clk";
};
@@ -883,7 +625,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff400 {
@@ -894,7 +636,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff600 {
@@ -905,7 +647,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioC_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioD: gpio@fffff800 {
@@ -916,7 +658,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioDE_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
};
pioE: gpio@fffffa00 {
@@ -927,7 +669,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioDE_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
};
};
@@ -937,7 +679,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -950,7 +692,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -963,7 +705,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -976,7 +718,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
clock-names = "usart";
status = "disabled";
};
@@ -989,7 +731,7 @@
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
clock-names = "usart";
status = "disabled";
};
@@ -1000,7 +742,7 @@
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
- clocks = <&macb0_clk>, <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_PERIPHERAL 25>;
clock-names = "hclk", "pclk";
status = "disabled";
};
@@ -1009,7 +751,7 @@
compatible = "atmel,at91sam9g45-trng";
reg = <0xfffcc000 0x100>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&trng_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
};
i2c0: i2c@fff84000 {
@@ -1020,7 +762,7 @@
pinctrl-0 = <&pinctrl_i2c0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
status = "disabled";
};
@@ -1032,7 +774,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
status = "disabled";
};
@@ -1042,7 +784,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "pclk";
status = "disabled";
};
@@ -1053,7 +795,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
- clocks = <&ssc1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
clock-names = "pclk";
status = "disabled";
};
@@ -1064,7 +806,7 @@
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ac97>;
- clocks = <&ac97_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "ac97_clk";
status = "disabled";
};
@@ -1075,7 +817,7 @@
compatible = "atmel,at91sam9g45-adc";
reg = <0xfffb0000 0x100>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&adc_clk>, <&adc_op_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-channels-used = <0xff>;
atmel,adc-vref = <3300>;
@@ -1111,7 +853,7 @@
compatible = "atmel,at91sam9g45-isi";
reg = <0xfffb4000 0x4000>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
- clocks = <&isi_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
clock-names = "isi_clk";
status = "disabled";
port {
@@ -1125,7 +867,7 @@
reg = <0xfffb8000 0x300>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
status = "disabled";
};
@@ -1133,12 +875,11 @@
compatible = "atmel,hsmci";
reg = <0xfff80000 0x600>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -1147,12 +888,11 @@
compatible = "atmel,hsmci";
reg = <0xfffd0000 0x600>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
- pinctrl-names = "default";
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
dma-names = "rxtx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
clock-names = "mci_clk";
status = "disabled";
};
@@ -1176,7 +916,7 @@
interrupts = <14 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -1189,73 +929,19 @@
interrupts = <15 4 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "spi_clk";
status = "disabled";
};
usb2: gadget@fff78000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "atmel,at91sam9g45-udc";
reg = <0x00600000 0x80000
0xfff78000 0x400>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&udphs_clk>, <&utmi>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
-
- ep@0 {
- reg = <0>;
- atmel,fifo-size = <64>;
- atmel,nb-banks = <1>;
- };
-
- ep@1 {
- reg = <1>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@2 {
- reg = <2>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@3 {
- reg = <3>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- };
-
- ep@4 {
- reg = <4>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- };
-
- ep@5 {
- reg = <5>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@6 {
- reg = <6>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
};
clk32k: sckc@fffffd50 {
@@ -1294,7 +980,7 @@
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
- clocks = <&lcd_clk>, <&lcd_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "hclk", "lcdc_clk";
status = "disabled";
};
@@ -1303,7 +989,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1312,7 +998,7 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00800000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&utmi>, <&uhphs_clk>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -1330,7 +1016,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 84bed6f..9734667 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -18,7 +18,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@70000000 {
reg = <0x70000000 0x4000000>;
};
@@ -72,9 +72,9 @@
pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>;
- clocks = <&pck1>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 9>;
clock-names = "xvclk";
- assigned-clocks = <&pck1>;
+ assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>;
assigned-clock-rates = <25000000>;
port {
@@ -99,6 +99,7 @@
&pinctrl_board_mmc0
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
reg = <0>;
@@ -112,6 +113,7 @@
&pinctrl_board_mmc1
&pinctrl_mmc1_slot0_clk_cmd_dat0
&pinctrl_mmc1_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
reg = <0>;
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index ea67517..0785389 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -37,16 +37,17 @@
pwm0 = &pwm0;
};
cpus {
- #address-cells = <0>;
+ #address-cells = <1>;
#size-cells = <0>;
- cpu {
+ cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
+ reg = <0>;
};
};
- memory {
+ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x10000000>;
};
@@ -68,6 +69,9 @@
sram: sram@300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00300000 0x8000>;
};
ahb {
@@ -104,7 +108,7 @@
ramc0: ramc@ffffe800 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe800 0x200>;
- clocks = <&ddrck>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>;
clock-names = "ddrck";
};
@@ -116,278 +120,10 @@
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9n12-pmc", "syscon";
reg = <0xfffffc00 0x200>;
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_rc_osc: main_rc_osc {
- compatible = "atmel,at91sam9x5-clk-main-rc-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
- clock-frequency = <12000000>;
- clock-accuracy = <50000000>;
- };
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91sam9x5-clk-main";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
- clocks = <&main_rc_osc>, <&main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <2000000 32000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
- <695000000 750000000 1 0>,
- <645000000 700000000 2 0>,
- <595000000 650000000 3 0>,
- <545000000 600000000 0 1>,
- <495000000 555000000 1 1>,
- <445000000 500000000 2 1>,
- <400000000 450000000 3 1>;
- };
-
- plladiv: plladivck {
- compatible = "atmel,at91sam9x5-clk-plldiv";
- #clock-cells = <0>;
- clocks = <&plla>;
- };
-
- pllb: pllbck {
- compatible = "atmel,at91rm9200-clk-pll";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_LOCKB>;
- clocks = <&main>;
- reg = <1>;
- atmel,clk-input-range = <2000000 32000000>;
- #atmel,pll-clk-output-range-cells = <3>;
- atmel,pll-clk-output-ranges = <30000000 100000000 0>;
- };
-
- mck: masterck {
- compatible = "atmel,at91sam9x5-clk-master";
- #clock-cells = <0>;
- interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
- atmel,clk-output-range = <0 133333333>;
- atmel,clk-divisors = <1 2 4 3>;
- atmel,master-clk-have-div3-pres;
- };
-
- usb: usbck {
- compatible = "atmel,at91sam9n12-clk-usb";
- #clock-cells = <0>;
- clocks = <&pllb>;
- };
-
- prog: progck {
- compatible = "atmel,at91sam9x5-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ddrck: ddrck {
- #clock-cells = <0>;
- reg = <2>;
- clocks = <&mck>;
- };
-
- lcdck: lcdck {
- #clock-cells = <0>;
- reg = <3>;
- clocks = <&mck>;
- };
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
- };
-
- periphck {
- compatible = "atmel,at91sam9x5-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- pioAB_clk: pioAB_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- pioCD_clk: pioCD_clk {
- #clock-cells = <0>;
- reg = <3>;
- };
-
- fuse_clk: fuse_clk {
- #clock-cells = <0>;
- reg = <4>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- twi0_clk: twi0_clk {
- reg = <9>;
- #clock-cells = <0>;
- };
-
- twi1_clk: twi1_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <12>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <13>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <14>;
- };
-
- uart0_clk: uart0_clk {
- #clock-cells = <0>;
- reg = <15>;
- };
-
- uart1_clk: uart1_clk {
- #clock-cells = <0>;
- reg = <16>;
- };
-
- tcb_clk: tcb_clk {
- #clock-cells = <0>;
- reg = <17>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <18>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <19>;
- };
-
- dma0_clk: dma0_clk {
- #clock-cells = <0>;
- reg = <20>;
- };
-
- uhphs_clk: uhphs_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- udphs_clk: udphs_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
-
- lcdc_clk: lcdc_clk {
- #clock-cells = <0>;
- reg = <25>;
- };
-
- sha_clk: sha_clk {
- #clock-cells = <0>;
- reg = <27>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <28>;
- };
-
- aes_clk: aes_clk {
- #clock-cells = <0>;
- reg = <29>;
- };
-
- trng_clk: trng_clk {
- #clock-cells = <0>;
- reg = <30>;
- };
- };
};
rstc@fffffe00 {
@@ -400,7 +136,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
shdwc@fffffe10 {
@@ -439,7 +175,7 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "mci_clk";
#address-cells = <1>;
#size-cells = <0>;
@@ -452,7 +188,7 @@
#size-cells = <0>;
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -462,7 +198,7 @@
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -470,7 +206,7 @@
compatible = "atmel,at91sam9n12-hlcdc";
reg = <0xf8038000 0x2000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
clock-names = "periph_clk", "sys_clk", "slow_clk";
status = "disabled";
@@ -499,7 +235,7 @@
reg = <0xffffec00 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
- clocks = <&dma0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "dma_clk";
};
@@ -817,7 +553,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioAB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
@@ -828,7 +564,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioAB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioC: gpio@fffff800 {
@@ -839,7 +575,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioD: gpio@fffffa00 {
@@ -850,7 +586,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioCD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
};
@@ -860,7 +596,7 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "usart";
status = "disabled";
};
@@ -874,7 +610,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
clock-names = "pclk";
status = "disabled";
};
@@ -885,7 +621,7 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
clock-names = "usart";
status = "disabled";
};
@@ -896,7 +632,7 @@
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
clock-names = "usart";
status = "disabled";
};
@@ -907,7 +643,7 @@
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
clock-names = "usart";
status = "disabled";
};
@@ -918,7 +654,7 @@
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
clock-names = "usart";
status = "disabled";
};
@@ -934,7 +670,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
status = "disabled";
};
@@ -949,7 +685,7 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
- clocks = <&twi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
status = "disabled";
};
@@ -964,7 +700,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -980,7 +716,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -1009,7 +745,7 @@
reg = <0xf8034000 0x300>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
status = "disabled";
};
@@ -1017,7 +753,7 @@
compatible = "atmel,at91sam9260-udc";
reg = <0xf803c000 0x4000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udphs_clk>, <&udpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>;
clock-names = "pclk", "hclk";
status = "disabled";
};
@@ -1027,7 +763,7 @@
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x00100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1045,7 +781,7 @@
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index ea5cef0..2bc4e6e 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -17,7 +17,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x8000000>;
};
@@ -59,7 +59,7 @@
wm8904: codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
- clocks = <&pck0>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "mclk";
};
@@ -238,7 +238,7 @@
};
panel: panel {
- compatible = "qiaodian,qd43003c0-40", "simple-panel";
+ compatible = "qiaodian,qd43003c0-40";
backlight = <&backlight>;
power-supply = <&panel_reg>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 0121bb0..36a42a9 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -38,16 +38,17 @@
};
cpus {
- #address-cells = <0>;
+ #address-cells = <1>;
#size-cells = <0>;
- cpu {
+ cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
+ reg = <0>;
};
};
- memory {
+ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x04000000>;
};
@@ -75,6 +76,9 @@
sram: sram@300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00300000 0x10000>;
};
ahb {
@@ -302,8 +306,6 @@
};
usb0: gadget@fffd4000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "atmel,at91sam9rl-udc";
reg = <0x00600000 0x100000>,
<0xfffd4000 0x4000>;
@@ -311,58 +313,6 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
-
- ep@0 {
- reg = <0>;
- atmel,fifo-size = <64>;
- atmel,nb-banks = <1>;
- };
-
- ep@1 {
- reg = <1>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@2 {
- reg = <2>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@3 {
- reg = <3>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- };
-
- ep@4 {
- reg = <4>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- };
-
- ep@5 {
- reg = <5>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@6 {
- reg = <6>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
};
dma0: dma-controller@ffffe600 {
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts
index 0de75d3..1590862 100644
--- a/arch/arm/boot/dts/at91sam9rlek.dts
+++ b/arch/arm/boot/dts/at91sam9rlek.dts
@@ -17,7 +17,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 7c2eb93..4cdb050 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -39,16 +39,17 @@
pwm0 = &pwm0;
};
cpus {
- #address-cells = <0>;
+ #address-cells = <1>;
#size-cells = <0>;
- cpu {
+ cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
+ reg = <0>;
};
};
- memory {
+ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x10000000>;
};
@@ -76,6 +77,9 @@
sram: sram@300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x8000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00300000 0x8000>;
};
ahb {
@@ -647,7 +651,6 @@
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
- pinctrl-names = "default";
clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "mci_clk";
#address-cells = <1>;
@@ -661,7 +664,6 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
dma-names = "rxtx";
- pinctrl-names = "default";
clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
clock-names = "mci_clk";
#address-cells = <1>;
@@ -867,8 +869,6 @@
};
usb2: gadget@f803c000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "atmel,at91sam9g45-udc";
reg = <0x00500000 0x80000
0xf803c000 0x400>;
@@ -876,58 +876,6 @@
clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "hclk", "pclk";
status = "disabled";
-
- ep@0 {
- reg = <0>;
- atmel,fifo-size = <64>;
- atmel,nb-banks = <1>;
- };
-
- ep@1 {
- reg = <1>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@2 {
- reg = <2>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@3 {
- reg = <3>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- };
-
- ep@4 {
- reg = <4>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- };
-
- ep@5 {
- reg = <5>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@6 {
- reg = <6>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
};
watchdog: watchdog@fffffe40 {
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 75d2f7f..cdd37f6 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -7,7 +7,7 @@
*/
/ {
- memory {
+ memory@20000000 {
reg = <0x20000000 0x8000000>;
};
diff --git a/arch/arm/boot/dts/at91sam9x5dm.dtsi b/arch/arm/boot/dts/at91sam9x5dm.dtsi
index 7f00c1f..a927803 100644
--- a/arch/arm/boot/dts/at91sam9x5dm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5dm.dtsi
@@ -27,7 +27,7 @@
};
panel: panel {
- compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
+ compatible = "foxlink,fl500wvr00-a0t";
backlight = <&backlight>;
power-supply = <&panel_reg>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index c934928..6d1264d 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -56,6 +56,7 @@
&pinctrl_board_mmc0
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
@@ -70,6 +71,7 @@
&pinctrl_board_mmc1
&pinctrl_mmc1_slot0_clk_cmd_dat0
&pinctrl_mmc1_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/at91sam9xe.dtsi
index 3f9d8ca..f571f77 100644
--- a/arch/arm/boot/dts/at91sam9xe.dtsi
+++ b/arch/arm/boot/dts/at91sam9xe.dtsi
@@ -19,5 +19,8 @@
sram1: sram@300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00300000 0x4000>;
};
};
diff --git a/arch/arm/boot/dts/atlas7-evb.dts b/arch/arm/boot/dts/atlas7-evb.dts
index e0c0291..e051504 100644
--- a/arch/arm/boot/dts/atlas7-evb.dts
+++ b/arch/arm/boot/dts/atlas7-evb.dts
@@ -119,7 +119,7 @@
label = "rearview key";
linux,code = <KEY_CAMERA>;
gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>;
- debounce_interval = <100>;
+ debounce-interval = <100>;
};
};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 9ca7b42..ea3dc12 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -91,7 +91,7 @@
<0x20100 0x100>;
};
- L2: l2-cache@22000 {
+ L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
reg = <0x22000 0x1000>;
cache-unified;
@@ -234,8 +234,8 @@
compatible = "arm,sp805" , "arm,primecell";
reg = <0x18009000 0x1000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&axi81_clk>;
- clock-names = "apb_pclk";
+ clocks = <&axi81_clk>, <&axi81_clk>;
+ clock-names = "wdog_clk", "apb_pclk";
};
gpio_ccm: gpio@1800a000 {
diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi
index 3057410..84cda16 100644
--- a/arch/arm/boot/dts/bcm-hr2.dtsi
+++ b/arch/arm/boot/dts/bcm-hr2.dtsi
@@ -104,7 +104,7 @@
<0x20100 0x100>;
};
- L2: l2-cache@22000 {
+ L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
reg = <0x22000 0x1000>;
cache-unified;
@@ -268,7 +268,7 @@
clock-frequency = <100000>;
};
- watchdog@39000 {
+ watchdog: watchdog@39000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x39000 0x1000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 43ff85d..1dae02b 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -77,7 +77,7 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
- mpcore@19000000 {
+ mpcore-bus@19000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x00023000>;
#address-cells = <1>;
@@ -122,7 +122,7 @@
<0x20100 0x100>;
};
- L2: l2-cache@22000 {
+ L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
reg = <0x22000 0x1000>;
cache-unified;
@@ -200,7 +200,7 @@
status = "disabled";
};
- dma@20000 {
+ dma: dma@20000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
@@ -215,9 +215,11 @@
clocks = <&iprocslow>;
clock-names = "apb_pclk";
#dma-cells = <1>;
+ dma-coherent;
+ status = "disabled";
};
- sdio: sdhci@21000 {
+ sdio: mmc@21000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x21000 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
@@ -366,7 +368,7 @@
};
ccbtimer0: timer@34000 {
- compatible = "arm,sp804";
+ compatible = "arm,sp804", "arm,primecell";
reg = <0x34000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
@@ -375,7 +377,7 @@
};
ccbtimer1: timer@35000 {
- compatible = "arm,sp804";
+ compatible = "arm,sp804", "arm,primecell";
reg = <0x35000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
@@ -436,7 +438,7 @@
reg = <0x39000 0x1000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>, <&iprocslow>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
};
lcpll0: lcpll0@3f100 {
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 3cf66fa..58ec1b2 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -90,7 +90,7 @@
reg-io-width = <4>;
};
- L2: l2-cache@3ff20000 {
+ L2: cache-controller@3ff20000 {
compatible = "arm,pl310-cache";
reg = <0x3ff20000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
new file mode 100644
index 0000000..1675385
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2711.dtsi"
+#include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-usb-peripheral.dtsi"
+
+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
+
+/ {
+ compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
+ model = "Raspberry Pi 4 Model B";
+
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
+ /* Will be filled by the bootloader */
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0>;
+ };
+
+ aliases {
+ emmc2bus = &emmc2bus;
+ ethernet0 = &genet;
+ pcie0 = &pcie0;
+ };
+
+ leds {
+ led-act {
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-pwr {
+ label = "PWR";
+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ sd_io_1v8_reg: sd_io_1v8_reg {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-sd-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-settling-time-us = <5000>;
+ gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ status = "okay";
+ };
+
+ sd_vcc_reg: sd_vcc_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ddc0 {
+ status = "okay";
+};
+
+&ddc1 {
+ status = "okay";
+};
+
+&firmware {
+ firmware_clocks: clocks {
+ compatible = "raspberrypi,firmware-clocks";
+ #clock-cells = <1>;
+ };
+
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "PWR_LED_OFF",
+ "GLOBAL_RESET",
+ "VDD_SD_IO_SEL",
+ "CAM_GPIO",
+ "SD_PWR_ON",
+ "";
+ status = "okay";
+ };
+
+ reset: reset {
+ compatible = "raspberrypi,firmware-reset";
+ #reset-cells = <1>;
+ };
+};
+
+&gpio {
+ /*
+ * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
+ * the official GPU firmware DT blob.
+ *
+ * Legend:
+ * "FOO" = GPIO line named "FOO" on the schematic
+ * "FOO_N" = GPIO line named "FOO" on schematic, active low
+ */
+ gpio-line-names = "ID_SDA",
+ "ID_SCL",
+ "SDA1",
+ "SCL1",
+ "GPIO_GCLK",
+ "GPIO5",
+ "GPIO6",
+ "SPI_CE1_N",
+ "SPI_CE0_N",
+ "SPI_MISO",
+ "SPI_MOSI",
+ "SPI_SCLK",
+ "GPIO12",
+ "GPIO13",
+ /* Serial port */
+ "TXD1",
+ "RXD1",
+ "GPIO16",
+ "GPIO17",
+ "GPIO18",
+ "GPIO19",
+ "GPIO20",
+ "GPIO21",
+ "GPIO22",
+ "GPIO23",
+ "GPIO24",
+ "GPIO25",
+ "GPIO26",
+ "GPIO27",
+ "RGMII_MDIO",
+ "RGMIO_MDC",
+ /* Used by BT module */
+ "CTS0",
+ "RTS0",
+ "TXD0",
+ "RXD0",
+ /* Used by Wifi */
+ "SD1_CLK",
+ "SD1_CMD",
+ "SD1_DATA0",
+ "SD1_DATA1",
+ "SD1_DATA2",
+ "SD1_DATA3",
+ /* Shared with SPI flash */
+ "PWM0_MISO",
+ "PWM1_MOSI",
+ "STATUS_LED_G_CLK",
+ "SPIFLASH_CE_N",
+ "SDA0",
+ "SCL0",
+ "RGMII_RXCLK",
+ "RGMII_RXCTL",
+ "RGMII_RXD0",
+ "RGMII_RXD1",
+ "RGMII_RXD2",
+ "RGMII_RXD3",
+ "RGMII_TXCLK",
+ "RGMII_TXCTL",
+ "RGMII_TXD0",
+ "RGMII_TXD1",
+ "RGMII_TXD2",
+ "RGMII_TXD3";
+};
+
+&hdmi0 {
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ status = "okay";
+};
+
+&hdmi1 {
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ status = "okay";
+};
+
+&hvs {
+ clocks = <&firmware_clocks 4>;
+};
+
+&pixelvalve0 {
+ status = "okay";
+};
+
+&pixelvalve1 {
+ status = "okay";
+};
+
+&pixelvalve2 {
+ status = "okay";
+};
+
+&pixelvalve4 {
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
+ status = "okay";
+};
+
+/* SDHCI is used to control the SDIO for wireless */
+&sdhci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_gpio34>;
+ bus-width = <4>;
+ non-removable;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* EMMC2 is used to drive the SD card */
+&emmc2 {
+ vqmmc-supply = <&sd_io_1v8_reg>;
+ vmmc-supply = <&sd_vcc_reg>;
+ broken-cd;
+ status = "okay";
+};
+
+&genet {
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-rxid";
+ status = "okay";
+};
+
+&genet_mdio {
+ phy1: ethernet-phy@1 {
+ /* No PHY interrupt */
+ reg = <0x1>;
+ };
+};
+
+&pcie0 {
+ pci@0,0 {
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ reg = <0 0 0 0 0>;
+
+ usb@0,0 {
+ reg = <0 0 0 0 0>;
+ resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
+ };
+ };
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <2000000>;
+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_gpio14>;
+ status = "okay";
+};
+
+&vchiq {
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&vc4 {
+ status = "okay";
+};
+
+&vec {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
new file mode 100644
index 0000000..e46a3f4
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -0,0 +1,1081 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "bcm283x.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/bcm2835-pm.h>
+
+/ {
+ compatible = "brcm,bcm2711";
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gicv2>;
+
+ vc4: gpu {
+ compatible = "brcm,bcm2711-vc5";
+ status = "disabled";
+ };
+
+ clk_27MHz: clk-27M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ clock-output-names = "27MHz-clock";
+ };
+
+ clk_108MHz: clk-108M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <108000000>;
+ clock-output-names = "108MHz-clock";
+ };
+
+ soc {
+ /*
+ * Defined ranges:
+ * Common BCM283x peripherals
+ * BCM2711-specific peripherals
+ * ARM-local peripherals
+ */
+ ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
+ <0x7c000000 0x0 0xfc000000 0x02000000>,
+ <0x40000000 0x0 0xff800000 0x00800000>;
+ /* Emulate a contiguous 30-bit address range for DMA */
+ dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
+
+ /*
+ * This node is the provider for the enable-method for
+ * bringing up secondary cores.
+ */
+ local_intc: local_intc@40000000 {
+ compatible = "brcm,bcm2836-l1-intc";
+ reg = <0x40000000 0x100>;
+ };
+
+ gicv2: interrupt-controller@40041000 {
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ compatible = "arm,gic-400";
+ reg = <0x40041000 0x1000>,
+ <0x40042000 0x2000>,
+ <0x40044000 0x2000>,
+ <0x40046000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ avs_monitor: avs-monitor@7d5d2000 {
+ compatible = "brcm,bcm2711-avs-monitor",
+ "syscon", "simple-mfd";
+ reg = <0x7d5d2000 0xf00>;
+
+ thermal: thermal {
+ compatible = "brcm,bcm2711-thermal";
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xb00>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ /* DMA lite 7 - 10 */
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "dma8",
+ "dma9",
+ "dma10";
+ #dma-cells = <1>;
+ brcm,dma-channel-mask = <0x07f5>;
+ };
+
+ pm: watchdog@7e100000 {
+ compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ reg = <0x7e100000 0x114>,
+ <0x7e00a000 0x24>,
+ <0x7ec11000 0x20>;
+ clocks = <&clocks BCM2835_CLOCK_V3D>,
+ <&clocks BCM2835_CLOCK_PERI_IMAGE>,
+ <&clocks BCM2835_CLOCK_H264>,
+ <&clocks BCM2835_CLOCK_ISP>;
+ clock-names = "v3d", "peri_image", "h264", "isp";
+ system-power-controller;
+ };
+
+ rng@7e104000 {
+ compatible = "brcm,bcm2711-rng200";
+ reg = <0x7e104000 0x28>;
+ };
+
+ uart2: serial@7e201400 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201400 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ uart3: serial@7e201600 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201600 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ uart4: serial@7e201800 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201800 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ uart5: serial@7e201a00 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x7e201a00 0x200>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_UART>,
+ <&clocks BCM2835_CLOCK_VPU>;
+ clock-names = "uartclk", "apb_pclk";
+ arm,primecell-periphid = <0x00241011>;
+ status = "disabled";
+ };
+
+ spi3: spi@7e204600 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204600 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@7e204800 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204800 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi5: spi@7e204a00 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204a00 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi6: spi@7e204c00 {
+ compatible = "brcm,bcm2835-spi";
+ reg = <0x7e204c00 0x0200>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@7e205600 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205600 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@7e205800 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205800 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@7e205a00 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205a00 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@7e205c00 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ reg = <0x7e205c00 0x200>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pixelvalve0: pixelvalve@7e206000 {
+ compatible = "brcm,bcm2711-pixelvalve0";
+ reg = <0x7e206000 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pixelvalve1: pixelvalve@7e207000 {
+ compatible = "brcm,bcm2711-pixelvalve1";
+ reg = <0x7e207000 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pixelvalve2: pixelvalve@7e20a000 {
+ compatible = "brcm,bcm2711-pixelvalve2";
+ reg = <0x7e20a000 0x100>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@7e20c800 {
+ compatible = "brcm,bcm2835-pwm";
+ reg = <0x7e20c800 0x28>;
+ clocks = <&clocks BCM2835_CLOCK_PWM>;
+ assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
+ assigned-clock-rates = <10000000>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pixelvalve4: pixelvalve@7e216000 {
+ compatible = "brcm,bcm2711-pixelvalve4";
+ reg = <0x7e216000 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ hvs: hvs@7e400000 {
+ compatible = "brcm,bcm2711-hvs";
+ reg = <0x7e400000 0x8000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pixelvalve3: pixelvalve@7ec12000 {
+ compatible = "brcm,bcm2711-pixelvalve3";
+ reg = <0x7ec12000 0x100>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ dvp: clock@7ef00000 {
+ compatible = "brcm,brcm2711-dvp";
+ reg = <0x7ef00000 0x10>;
+ clocks = <&clk_108MHz>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ hdmi0: hdmi@7ef00700 {
+ compatible = "brcm,bcm2711-hdmi0";
+ reg = <0x7ef00700 0x300>,
+ <0x7ef00300 0x200>,
+ <0x7ef00f00 0x80>,
+ <0x7ef00f80 0x80>,
+ <0x7ef01b00 0x200>,
+ <0x7ef01f00 0x400>,
+ <0x7ef00200 0x80>,
+ <0x7ef04300 0x100>,
+ <0x7ef20000 0x100>;
+ reg-names = "hdmi",
+ "dvp",
+ "phy",
+ "rm",
+ "packet",
+ "metadata",
+ "csc",
+ "cec",
+ "hd";
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ resets = <&dvp 0>;
+ ddc = <&ddc0>;
+ dmas = <&dma 10>;
+ dma-names = "audio-rx";
+ status = "disabled";
+ };
+
+ ddc0: i2c@7ef04500 {
+ compatible = "brcm,bcm2711-hdmi-i2c";
+ reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
+ reg-names = "bsc", "auto-i2c";
+ clock-frequency = <97500>;
+ status = "disabled";
+ };
+
+ hdmi1: hdmi@7ef05700 {
+ compatible = "brcm,bcm2711-hdmi1";
+ reg = <0x7ef05700 0x300>,
+ <0x7ef05300 0x200>,
+ <0x7ef05f00 0x80>,
+ <0x7ef05f80 0x80>,
+ <0x7ef06b00 0x200>,
+ <0x7ef06f00 0x400>,
+ <0x7ef00280 0x80>,
+ <0x7ef09300 0x100>,
+ <0x7ef20000 0x100>;
+ reg-names = "hdmi",
+ "dvp",
+ "phy",
+ "rm",
+ "packet",
+ "metadata",
+ "csc",
+ "cec",
+ "hd";
+ ddc = <&ddc1>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ resets = <&dvp 1>;
+ dmas = <&dma 17>;
+ dma-names = "audio-rx";
+ status = "disabled";
+ };
+
+ ddc1: i2c@7ef09500 {
+ compatible = "brcm,bcm2711-hdmi-i2c";
+ reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
+ reg-names = "bsc", "auto-i2c";
+ clock-frequency = <97500>;
+ status = "disabled";
+ };
+ };
+
+ /*
+ * emmc2 has different DMA constraints based on SoC revisions. It was
+ * moved into its own bus, so as for RPi4's firmware to update them.
+ * The firmware will find whether the emmc2bus alias is defined, and if
+ * so, it'll edit the dma-ranges property below accordingly.
+ */
+ emmc2bus: emmc2bus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
+ dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
+
+ emmc2: mmc@7e340000 {
+ compatible = "brcm,bcm2711-emmc2";
+ reg = <0x0 0x7e340000 0x100>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clocks BCM2711_CLOCK_EMMC2>;
+ status = "disabled";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ /* This only applies to the ARMv7 stub */
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000d8>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000e0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000e8>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x000000f0>;
+ };
+ };
+
+ scb {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
+ <0x6 0x00000000 0x6 0x00000000 0x40000000>;
+
+ pcie0: pcie@7d500000 {
+ compatible = "brcm,bcm2711-pcie";
+ reg = <0x0 0x7d500000 0x9310>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gicv2 GIC_SPI 144
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gicv2 GIC_SPI 145
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gicv2 GIC_SPI 146
+ IRQ_TYPE_LEVEL_HIGH>;
+ msi-controller;
+ msi-parent = <&pcie0>;
+
+ ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
+ 0x0 0x04000000>;
+ /*
+ * The wrapper around the PCIe block has a bug
+ * preventing it from accessing beyond the first 3GB of
+ * memory.
+ */
+ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
+ 0x0 0xc0000000>;
+ brcm,enable-ssc;
+ };
+
+ genet: ethernet@7d580000 {
+ compatible = "brcm,bcm2711-genet-v5";
+ reg = <0x0 0x7d580000 0x10000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ genet_mdio: mdio@e14 {
+ compatible = "brcm,genet-mdio-v5";
+ reg = <0xe14 0x8>;
+ reg-names = "mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+ };
+ };
+};
+
+&clk_osc {
+ clock-frequency = <54000000>;
+};
+
+&clocks {
+ compatible = "brcm,bcm2711-cprman";
+};
+
+&cpu_thermal {
+ coefficients = <(-487) 410040>;
+ thermal-sensors = <&thermal>;
+};
+
+&dsi0 {
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&dsi1 {
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio {
+ compatible = "brcm,bcm2711-gpio";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-ranges = <&gpio 0 0 58>;
+
+ gpclk0_gpio49: gpclk0_gpio49 {
+ pin-gpclk {
+ pins = "gpio49";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+ gpclk1_gpio50: gpclk1_gpio50 {
+ pin-gpclk {
+ pins = "gpio50";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+ gpclk2_gpio51: gpclk2_gpio51 {
+ pin-gpclk {
+ pins = "gpio51";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+
+ i2c0_gpio46: i2c0_gpio46 {
+ pin-sda {
+ function = "alt0";
+ pins = "gpio46";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt0";
+ pins = "gpio47";
+ bias-disable;
+ };
+ };
+ i2c1_gpio46: i2c1_gpio46 {
+ pin-sda {
+ function = "alt1";
+ pins = "gpio46";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt1";
+ pins = "gpio47";
+ bias-disable;
+ };
+ };
+ i2c3_gpio2: i2c3_gpio2 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio2";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio3";
+ bias-disable;
+ };
+ };
+ i2c3_gpio4: i2c3_gpio4 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio4";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio5";
+ bias-disable;
+ };
+ };
+ i2c4_gpio6: i2c4_gpio6 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio6";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio7";
+ bias-disable;
+ };
+ };
+ i2c4_gpio8: i2c4_gpio8 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio8";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio9";
+ bias-disable;
+ };
+ };
+ i2c5_gpio10: i2c5_gpio10 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio10";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio11";
+ bias-disable;
+ };
+ };
+ i2c5_gpio12: i2c5_gpio12 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio12";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio13";
+ bias-disable;
+ };
+ };
+ i2c6_gpio0: i2c6_gpio0 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio0";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio1";
+ bias-disable;
+ };
+ };
+ i2c6_gpio22: i2c6_gpio22 {
+ pin-sda {
+ function = "alt5";
+ pins = "gpio22";
+ bias-pull-up;
+ };
+ pin-scl {
+ function = "alt5";
+ pins = "gpio23";
+ bias-disable;
+ };
+ };
+ i2c_slave_gpio8: i2c_slave_gpio8 {
+ pins-i2c-slave {
+ pins = "gpio8",
+ "gpio9",
+ "gpio10",
+ "gpio11";
+ function = "alt3";
+ };
+ };
+
+ jtag_gpio48: jtag_gpio48 {
+ pins-jtag {
+ pins = "gpio48",
+ "gpio49",
+ "gpio50",
+ "gpio51",
+ "gpio52",
+ "gpio53";
+ function = "alt4";
+ };
+ };
+
+ mii_gpio28: mii_gpio28 {
+ pins-mii {
+ pins = "gpio28",
+ "gpio29",
+ "gpio30",
+ "gpio31";
+ function = "alt4";
+ };
+ };
+ mii_gpio36: mii_gpio36 {
+ pins-mii {
+ pins = "gpio36",
+ "gpio37",
+ "gpio38",
+ "gpio39";
+ function = "alt5";
+ };
+ };
+
+ pcm_gpio50: pcm_gpio50 {
+ pins-pcm {
+ pins = "gpio50",
+ "gpio51",
+ "gpio52",
+ "gpio53";
+ function = "alt2";
+ };
+ };
+
+ pwm0_0_gpio12: pwm0_0_gpio12 {
+ pin-pwm {
+ pins = "gpio12";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_0_gpio18: pwm0_0_gpio18 {
+ pin-pwm {
+ pins = "gpio18";
+ function = "alt5";
+ bias-disable;
+ };
+ };
+ pwm1_0_gpio40: pwm1_0_gpio40 {
+ pin-pwm {
+ pins = "gpio40";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio13: pwm0_1_gpio13 {
+ pin-pwm {
+ pins = "gpio13";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio19: pwm0_1_gpio19 {
+ pin-pwm {
+ pins = "gpio19";
+ function = "alt5";
+ bias-disable;
+ };
+ };
+ pwm1_1_gpio41: pwm1_1_gpio41 {
+ pin-pwm {
+ pins = "gpio41";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio45: pwm0_1_gpio45 {
+ pin-pwm {
+ pins = "gpio45";
+ function = "alt0";
+ bias-disable;
+ };
+ };
+ pwm0_0_gpio52: pwm0_0_gpio52 {
+ pin-pwm {
+ pins = "gpio52";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+ pwm0_1_gpio53: pwm0_1_gpio53 {
+ pin-pwm {
+ pins = "gpio53";
+ function = "alt1";
+ bias-disable;
+ };
+ };
+
+ rgmii_gpio35: rgmii_gpio35 {
+ pin-start-stop {
+ pins = "gpio35";
+ function = "alt4";
+ };
+ pin-rx-ok {
+ pins = "gpio36";
+ function = "alt4";
+ };
+ };
+ rgmii_irq_gpio34: rgmii_irq_gpio34 {
+ pin-irq {
+ pins = "gpio34";
+ function = "alt5";
+ };
+ };
+ rgmii_irq_gpio39: rgmii_irq_gpio39 {
+ pin-irq {
+ pins = "gpio39";
+ function = "alt4";
+ };
+ };
+ rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
+ pins-mdio {
+ pins = "gpio28",
+ "gpio29";
+ function = "alt5";
+ };
+ };
+ rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
+ pins-mdio {
+ pins = "gpio37",
+ "gpio38";
+ function = "alt4";
+ };
+ };
+
+ spi0_gpio46: spi0_gpio46 {
+ pins-spi {
+ pins = "gpio46",
+ "gpio47",
+ "gpio48",
+ "gpio49";
+ function = "alt2";
+ };
+ };
+ spi2_gpio46: spi2_gpio46 {
+ pins-spi {
+ pins = "gpio46",
+ "gpio47",
+ "gpio48",
+ "gpio49",
+ "gpio50";
+ function = "alt5";
+ };
+ };
+ spi3_gpio0: spi3_gpio0 {
+ pins-spi {
+ pins = "gpio0",
+ "gpio1",
+ "gpio2",
+ "gpio3";
+ function = "alt3";
+ };
+ };
+ spi4_gpio4: spi4_gpio4 {
+ pins-spi {
+ pins = "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7";
+ function = "alt3";
+ };
+ };
+ spi5_gpio12: spi5_gpio12 {
+ pins-spi {
+ pins = "gpio12",
+ "gpio13",
+ "gpio14",
+ "gpio15";
+ function = "alt3";
+ };
+ };
+ spi6_gpio18: spi6_gpio18 {
+ pins-spi {
+ pins = "gpio18",
+ "gpio19",
+ "gpio20",
+ "gpio21";
+ function = "alt3";
+ };
+ };
+
+ uart2_gpio0: uart2_gpio0 {
+ pin-tx {
+ pins = "gpio0";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio1";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
+ pin-cts {
+ pins = "gpio2";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio3";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+ uart3_gpio4: uart3_gpio4 {
+ pin-tx {
+ pins = "gpio4";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio5";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
+ pin-cts {
+ pins = "gpio6";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio7";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+ uart4_gpio8: uart4_gpio8 {
+ pin-tx {
+ pins = "gpio8";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio9";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
+ pin-cts {
+ pins = "gpio10";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio11";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+ uart5_gpio12: uart5_gpio12 {
+ pin-tx {
+ pins = "gpio12";
+ function = "alt4";
+ bias-disable;
+ };
+ pin-rx {
+ pins = "gpio13";
+ function = "alt4";
+ bias-pull-up;
+ };
+ };
+ uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
+ pin-cts {
+ pins = "gpio14";
+ function = "alt4";
+ bias-pull-up;
+ };
+ pin-rts {
+ pins = "gpio15";
+ function = "alt4";
+ bias-disable;
+ };
+ };
+};
+
+&rmem {
+ #address-cells = <2>;
+};
+
+&cma {
+ /*
+ * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
+ * that's not good enough for the BCM2711 as some devices can
+ * only address the lower 1G of memory (ZONE_DMA).
+ */
+ alloc-ranges = <0x0 0x00000000 0x40000000>;
+};
+
+&i2c0 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&mailbox {
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sdhci {
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sdhost {
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi {
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi1 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi2 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&system_timer {
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&txp {
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart0 {
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart1 {
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usb {
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&vec {
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi
new file mode 100644
index 0000000..4119271
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-common.dtsi
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* This include file covers the common peripherals and configuration between
+ * bcm2835, bcm2836 and bcm2837 implementations.
+ */
+
+/ {
+ interrupt-parent = <&intc>;
+
+ soc {
+ dma: dma@7e007000 {
+ compatible = "brcm,bcm2835-dma";
+ reg = <0x7e007000 0xf00>;
+ interrupts = <1 16>,
+ <1 17>,
+ <1 18>,
+ <1 19>,
+ <1 20>,
+ <1 21>,
+ <1 22>,
+ <1 23>,
+ <1 24>,
+ <1 25>,
+ <1 26>,
+ /* dma channel 11-14 share one irq */
+ <1 27>,
+ <1 27>,
+ <1 27>,
+ <1 27>,
+ /* unused shared irq for all channels */
+ <1 28>;
+ interrupt-names = "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "dma8",
+ "dma9",
+ "dma10",
+ "dma11",
+ "dma12",
+ "dma13",
+ "dma14",
+ "dma-shared-all";
+ #dma-cells = <1>;
+ brcm,dma-channel-mask = <0x7f35>;
+ };
+
+ intc: interrupt-controller@7e00b200 {
+ compatible = "brcm,bcm2835-armctrl-ic";
+ reg = <0x7e00b200 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pm: watchdog@7e100000 {
+ compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ reg = <0x7e100000 0x114>,
+ <0x7e00a000 0x24>;
+ clocks = <&clocks BCM2835_CLOCK_V3D>,
+ <&clocks BCM2835_CLOCK_PERI_IMAGE>,
+ <&clocks BCM2835_CLOCK_H264>,
+ <&clocks BCM2835_CLOCK_ISP>;
+ clock-names = "v3d", "peri_image", "h264", "isp";
+ system-power-controller;
+ };
+
+ rng@7e104000 {
+ compatible = "brcm,bcm2835-rng";
+ reg = <0x7e104000 0x10>;
+ interrupts = <2 29>;
+ };
+
+ pixelvalve@7e206000 {
+ compatible = "brcm,bcm2835-pixelvalve0";
+ reg = <0x7e206000 0x100>;
+ interrupts = <2 13>; /* pwa0 */
+ };
+
+ pixelvalve@7e207000 {
+ compatible = "brcm,bcm2835-pixelvalve1";
+ reg = <0x7e207000 0x100>;
+ interrupts = <2 14>; /* pwa1 */
+ };
+
+ thermal: thermal@7e212000 {
+ compatible = "brcm,bcm2835-thermal";
+ reg = <0x7e212000 0x8>;
+ clocks = <&clocks BCM2835_CLOCK_TSENS>;
+ #thermal-sensor-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@7e805000 {
+ compatible = "brcm,bcm2835-i2c";
+ reg = <0x7e805000 0x1000>;
+ interrupts = <2 21>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ };
+
+ pixelvalve@7e807000 {
+ compatible = "brcm,bcm2835-pixelvalve2";
+ reg = <0x7e807000 0x100>;
+ interrupts = <2 10>; /* pixelvalve */
+ };
+
+ hdmi: hdmi@7e902000 {
+ compatible = "brcm,bcm2835-hdmi";
+ reg = <0x7e902000 0x600>,
+ <0x7e808000 0x100>;
+ interrupts = <2 8>, <2 9>;
+ ddc = <&i2c2>;
+ clocks = <&clocks BCM2835_PLLH_PIX>,
+ <&clocks BCM2835_CLOCK_HSM>;
+ clock-names = "pixel", "hdmi";
+ dmas = <&dma 17>;
+ dma-names = "audio-rx";
+ status = "disabled";
+ };
+
+ v3d: v3d@7ec00000 {
+ compatible = "brcm,bcm2835-v3d";
+ reg = <0x7ec00000 0x1000>;
+ interrupts = <1 10>;
+ };
+
+ vc4: gpu {
+ compatible = "brcm,bcm2835-vc4";
+ };
+ };
+};
+
+&cpu_thermal {
+ thermal-sensors = <&thermal>;
+};
+
+&gpio {
+ i2c_slave_gpio18: i2c_slave_gpio18 {
+ brcm,pins = <18 19 20 21>;
+ brcm,function = <BCM2835_FSEL_ALT3>;
+ };
+
+ jtag_gpio4: jtag_gpio4 {
+ brcm,pins = <4 5 6 12 13>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+
+ pwm0_gpio12: pwm0_gpio12 {
+ brcm,pins = <12>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm0_gpio18: pwm0_gpio18 {
+ brcm,pins = <18>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm0_gpio40: pwm0_gpio40 {
+ brcm,pins = <40>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio13: pwm1_gpio13 {
+ brcm,pins = <13>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio19: pwm1_gpio19 {
+ brcm,pins = <19>;
+ brcm,function = <BCM2835_FSEL_ALT5>;
+ };
+ pwm1_gpio41: pwm1_gpio41 {
+ brcm,pins = <41>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+ pwm1_gpio45: pwm1_gpio45 {
+ brcm,pins = <45>;
+ brcm,function = <BCM2835_FSEL_ALT0>;
+ };
+};
+
+&i2s {
+ dmas = <&dma 2>, <&dma 3>;
+ dma-names = "tx", "rx";
+};
+
+&sdhost {
+ dmas = <&dma 13>;
+ dma-names = "rx-tx";
+};
+
+&spi {
+ dmas = <&dma 6>, <&dma 7>;
+ dma-names = "tx", "rx";
+};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
index 6c8ce39..40b9405 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts
@@ -14,11 +14,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts
index 17fdd48..11edb58 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts
@@ -14,7 +14,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
index b0355c2..1b435c6 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -15,11 +15,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
index 33b3b5c..a23c25c 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
@@ -15,7 +15,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 2b69957..1b63d6b 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -15,7 +15,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
index 58059c2..e4e6b6a 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi
@@ -5,7 +5,7 @@
/ {
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi
new file mode 100644
index 0000000..8a55b6c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This include file covers the common peripherals and configuration between
+ * bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's
+ * firmware interface.
+ */
+
+#include <dt-bindings/power/raspberrypi-power.h>
+
+&v3d {
+ power-domains = <&power RPI_POWER_DOMAIN_V3D>;
+};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
index f65448c..33b2b77 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
@@ -23,7 +23,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
index 6dd93c6..6f9b3a9 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts
@@ -18,7 +18,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index 6c6a7f6..87ddcad 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -4,7 +4,7 @@
leds {
compatible = "gpio-leds";
- act {
+ led-act {
label = "ACT";
default-state = "keep";
linux,default-trigger = "heartbeat";
@@ -13,8 +13,12 @@
soc {
firmware: firmware {
- compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
+ compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
mboxes = <&mailbox>;
+ dma-ranges;
};
power: power {
@@ -59,10 +63,6 @@
clock-frequency = <100000>;
};
-&i2c2 {
- status = "okay";
-};
-
&usb {
power-domains = <&power RPI_POWER_DOMAIN_USB>;
};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index a5c3824..0549686 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
+#include "bcm2835-common.dtsi"
+#include "bcm2835-rpi-common.dtsi"
/ {
compatible = "brcm,bcm2835";
diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
index 0455a68..d8af8ee 100644
--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
@@ -15,11 +15,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi
index c933e84..b390006 100644
--- a/arch/arm/boot/dts/bcm2836.dtsi
+++ b/arch/arm/boot/dts/bcm2836.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
+#include "bcm2835-common.dtsi"
+#include "bcm2835-rpi-common.dtsi"
/ {
compatible = "brcm,bcm2836";
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
index 66ab35e..77099a7 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
@@ -19,13 +19,15 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
};
};
};
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
index 74ed6d0..6101026 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
@@ -20,13 +20,15 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "keep";
+ linux,default-trigger = "default-on";
};
};
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
index 054ecaa..dd4a486 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
@@ -20,7 +20,7 @@
};
leds {
- act {
+ led-act {
gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
index 925cb37..828a205 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
+++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
@@ -14,7 +14,7 @@
* Since there is no upstream GPIO driver yet,
* remove the incomplete node.
*/
- /delete-node/ act;
+ /delete-node/ led-act;
};
reg_3v3: fixed-regulator {
diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index beb6c50..0199ec9 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -1,4 +1,6 @@
#include "bcm283x.dtsi"
+#include "bcm2835-common.dtsi"
+#include "bcm2835-rpi-common.dtsi"
/ {
compatible = "brcm,bcm2837";
diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi
new file mode 100644
index 0000000..0ff0e9e
--- /dev/null
+++ b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+&usb {
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <256>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <256 256 512 512 512 768 768>;
+};
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 50c6414..ffdf7c4 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -18,7 +18,6 @@
/ {
compatible = "brcm,bcm2835";
model = "BCM2835";
- interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
@@ -31,13 +30,24 @@
stdout-path = "serial0:115200n8";
};
+ rmem: reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cma: linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x4000000>; /* 64MB */
+ reusable;
+ linux,cma-default;
+ };
+ };
+
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
- thermal-sensors = <&thermal>;
-
trips {
cpu-crit {
temperature = <90000>;
@@ -56,7 +66,7 @@
#address-cells = <1>;
#size-cells = <1>;
- timer@7e003000 {
+ system_timer: timer@7e003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7e003000 0x1000>;
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
@@ -67,74 +77,12 @@
clock-frequency = <1000000>;
};
- txp@7e004000 {
+ txp: txp@7e004000 {
compatible = "brcm,bcm2835-txp";
reg = <0x7e004000 0x20>;
interrupts = <1 11>;
};
- dma: dma@7e007000 {
- compatible = "brcm,bcm2835-dma";
- reg = <0x7e007000 0xf00>;
- interrupts = <1 16>,
- <1 17>,
- <1 18>,
- <1 19>,
- <1 20>,
- <1 21>,
- <1 22>,
- <1 23>,
- <1 24>,
- <1 25>,
- <1 26>,
- /* dma channel 11-14 share one irq */
- <1 27>,
- <1 27>,
- <1 27>,
- <1 27>,
- /* unused shared irq for all channels */
- <1 28>;
- interrupt-names = "dma0",
- "dma1",
- "dma2",
- "dma3",
- "dma4",
- "dma5",
- "dma6",
- "dma7",
- "dma8",
- "dma9",
- "dma10",
- "dma11",
- "dma12",
- "dma13",
- "dma14",
- "dma-shared-all";
- #dma-cells = <1>;
- brcm,dma-channel-mask = <0x7f35>;
- };
-
- intc: interrupt-controller@7e00b200 {
- compatible = "brcm,bcm2835-armctrl-ic";
- reg = <0x7e00b200 0x200>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pm: watchdog@7e100000 {
- compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
- #power-domain-cells = <1>;
- #reset-cells = <1>;
- reg = <0x7e100000 0x114>,
- <0x7e00a000 0x24>;
- clocks = <&clocks BCM2835_CLOCK_V3D>,
- <&clocks BCM2835_CLOCK_PERI_IMAGE>,
- <&clocks BCM2835_CLOCK_H264>,
- <&clocks BCM2835_CLOCK_ISP>;
- clock-names = "v3d", "peri_image", "h264", "isp";
- system-power-controller;
- };
-
clocks: cprman@7e101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
@@ -149,12 +97,6 @@
<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
};
- rng@7e104000 {
- compatible = "brcm,bcm2835-rng";
- reg = <0x7e104000 0x10>;
- interrupts = <2 29>;
- };
-
mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
@@ -184,8 +126,9 @@
interrupt-controller;
#interrupt-cells = <2>;
- /* Defines pin muxing groups according to
- * BCM2835-ARM-Peripherals.pdf page 102.
+ gpio-ranges = <&gpio 0 0 54>;
+
+ /* Defines common pin muxing groups
*
* While each pin can have its mux selected
* for various functions individually, some
@@ -263,15 +206,7 @@
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
- i2c_slave_gpio18: i2c_slave_gpio18 {
- brcm,pins = <18 19 20 21>;
- brcm,function = <BCM2835_FSEL_ALT3>;
- };
- jtag_gpio4: jtag_gpio4 {
- brcm,pins = <4 5 6 12 13>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
jtag_gpio22: jtag_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT4>;
@@ -286,35 +221,6 @@
brcm,function = <BCM2835_FSEL_ALT2>;
};
- pwm0_gpio12: pwm0_gpio12 {
- brcm,pins = <12>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm0_gpio18: pwm0_gpio18 {
- brcm,pins = <18>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- pwm0_gpio40: pwm0_gpio40 {
- brcm,pins = <40>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio13: pwm1_gpio13 {
- brcm,pins = <13>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio19: pwm1_gpio19 {
- brcm,pins = <19>;
- brcm,function = <BCM2835_FSEL_ALT5>;
- };
- pwm1_gpio41: pwm1_gpio41 {
- brcm,pins = <41>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
- pwm1_gpio45: pwm1_gpio45 {
- brcm,pins = <45>;
- brcm,function = <BCM2835_FSEL_ALT0>;
- };
-
sdhost_gpio48: sdhost_gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT0>;
@@ -396,7 +302,7 @@
};
uart0: serial@7e201000 {
- compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
+ compatible = "arm,pl011", "arm,primecell";
reg = <0x7e201000 0x200>;
interrupts = <2 25>;
clocks = <&clocks BCM2835_CLOCK_UART>,
@@ -410,8 +316,6 @@
reg = <0x7e202000 0x100>;
interrupts = <2 24>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
- dmas = <&dma 13>;
- dma-names = "rx-tx";
status = "disabled";
};
@@ -419,10 +323,6 @@
compatible = "brcm,bcm2835-i2s";
reg = <0x7e203000 0x24>;
clocks = <&clocks BCM2835_CLOCK_PCM>;
-
- dmas = <&dma 2>,
- <&dma 3>;
- dma-names = "tx", "rx";
status = "disabled";
};
@@ -431,8 +331,6 @@
reg = <0x7e204000 0x200>;
interrupts = <2 22>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
- dmas = <&dma 6>, <&dma 7>;
- dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -448,18 +346,6 @@
status = "disabled";
};
- pixelvalve@7e206000 {
- compatible = "brcm,bcm2835-pixelvalve0";
- reg = <0x7e206000 0x100>;
- interrupts = <2 13>; /* pwa0 */
- };
-
- pixelvalve@7e207000 {
- compatible = "brcm,bcm2835-pixelvalve1";
- reg = <0x7e207000 0x100>;
- interrupts = <2 14>; /* pwa1 */
- };
-
dpi: dpi@7e208000 {
compatible = "brcm,bcm2835-dpi";
reg = <0x7e208000 0x8c>;
@@ -491,14 +377,6 @@
status = "disabled";
};
- thermal: thermal@7e212000 {
- compatible = "brcm,bcm2835-thermal";
- reg = <0x7e212000 0x8>;
- clocks = <&clocks BCM2835_CLOCK_TSENS>;
- #thermal-sensor-cells = <0>;
- status = "disabled";
- };
-
aux: aux@7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
@@ -544,7 +422,7 @@
status = "disabled";
};
- sdhci: sdhci@7e300000 {
+ sdhci: mmc@7e300000 {
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
interrupts = <2 30>;
@@ -588,16 +466,6 @@
status = "disabled";
};
- i2c2: i2c@7e805000 {
- compatible = "brcm,bcm2835-i2c";
- reg = <0x7e805000 0x1000>;
- interrupts = <2 21>;
- clocks = <&clocks BCM2835_CLOCK_VPU>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
vec: vec@7e806000 {
compatible = "brcm,bcm2835-vec";
reg = <0x7e806000 0x1000>;
@@ -606,26 +474,6 @@
status = "disabled";
};
- pixelvalve@7e807000 {
- compatible = "brcm,bcm2835-pixelvalve2";
- reg = <0x7e807000 0x100>;
- interrupts = <2 10>; /* pixelvalve */
- };
-
- hdmi: hdmi@7e902000 {
- compatible = "brcm,bcm2835-hdmi";
- reg = <0x7e902000 0x600>,
- <0x7e808000 0x100>;
- interrupts = <2 8>, <2 9>;
- ddc = <&i2c2>;
- clocks = <&clocks BCM2835_PLLH_PIX>,
- <&clocks BCM2835_CLOCK_HSM>;
- clock-names = "pixel", "hdmi";
- dmas = <&dma 17>;
- dma-names = "audio-rx";
- status = "disabled";
- };
-
usb: usb@7e980000 {
compatible = "brcm,bcm2835-usb";
reg = <0x7e980000 0x10000>;
@@ -637,36 +485,19 @@
phys = <&usbphy>;
phy-names = "usb2-phy";
};
-
- v3d: v3d@7ec00000 {
- compatible = "brcm,bcm2835-v3d";
- reg = <0x7ec00000 0x1000>;
- interrupts = <1 10>;
- power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
- };
-
- vc4: gpu {
- compatible = "brcm,bcm2835-vc4";
- };
};
clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
/* The oscillator is the root of the clock tree. */
- clk_osc: clock@3 {
+ clk_osc: clk-osc {
compatible = "fixed-clock";
- reg = <3>;
#clock-cells = <0>;
clock-output-names = "osc";
clock-frequency = <19200000>;
};
- clk_usb: clock@4 {
+ clk_usb: clk-usb {
compatible = "fixed-clock";
- reg = <4>;
#clock-cells = <0>;
clock-output-names = "otg";
clock-frequency = <480000000>;
diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
index 6a96655..8ed4037 100644
--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
@@ -21,8 +21,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
index 3b0029e..667b118 100644
--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
@@ -21,8 +21,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
index 90f57ba..ff31ce4 100644
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -21,8 +21,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x18000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
};
spi {
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
index e58c807..810fc32 100644
--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
@@ -60,3 +60,28 @@
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "poe";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
index 766db61..7604b44 100644
--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
@@ -67,3 +67,23 @@
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+ label = "lan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index fed75e6..7900aac 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -20,10 +20,10 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
index 79542e1..4c60eda 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
@@ -21,8 +21,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
index abd35a5..7d46561 100644
--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
@@ -21,8 +21,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
index c29950b..0e273c5 100644
--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
@@ -21,8 +21,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
index 4dcec68..083ec40 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
@@ -21,8 +21,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
spi {
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
index 0e349e3..8b1a05a 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
@@ -21,8 +21,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
spi {
diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
index b9d9501..1ec6558 100644
--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
@@ -60,3 +60,23 @@
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+ label = "poe";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
index 0052e1b..04bfd58 100644
--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
@@ -108,3 +108,43 @@
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
index 8f1e565..7546c8d 100644
--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
@@ -19,10 +19,10 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
index ce888b1..beae9ea 100644
--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
@@ -19,10 +19,10 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x18000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
index ed8619b..ee94455 100644
--- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
@@ -16,10 +16,10 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
gpio-keys {
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
index 1f87993..56d309d 100644
--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts
@@ -19,10 +19,10 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
index 6c6199a..184e303 100644
--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
@@ -30,10 +30,10 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
index f806be5..c2a266a 100644
--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
@@ -15,7 +15,7 @@
bootargs = "console=ttyS0,115200 earlycon";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
index 911c65f..e635a15 100644
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
@@ -21,8 +21,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
nand: nand@18028000 {
diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
index 0faae89..36d63be 100644
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
@@ -18,8 +18,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
gpio-keys {
diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
index 50f7cd0..a6dc999 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
@@ -18,8 +18,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x18000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
index b47fb07..068e384 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
@@ -54,3 +54,28 @@
&spi_nor {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "poe";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
index bcc420f..ff98837 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
@@ -18,8 +18,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x18000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
new file mode 100644
index 0000000..3d415d8
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2019 Legrand AV Inc.
+ */
+
+/dts-v1/;
+
+#include "bcm47094.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+ compatible = "luxul,xwc-2000-v1", "brcm,bcm47094", "brcm,bcm4708";
+ model = "Luxul XWC-2000 V1";
+
+ chosen {
+ bootargs = "earlycon";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "bcm53xx:green:status";
+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&spi_nor {
+ status = "okay";
+};
+
+&srab {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
index ac75154..9f79802 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
@@ -18,8 +18,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x08000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
};
leds {
@@ -103,3 +103,43 @@
&usb3_phy {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
index 6d28b7d..c8dfa4c 100644
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
@@ -18,8 +18,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x18000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
};
leds {
@@ -74,3 +74,43 @@
&spi_nor {
status = "okay";
};
+
+&srab {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan4";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan1";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
index f42a170..42097a4 100644
--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts
@@ -18,8 +18,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x18000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
};
leds {
diff --git a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
index ac3a448..a2566ad 100644
--- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
+++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts
@@ -15,8 +15,8 @@
memory@0 {
device_type = "memory";
- reg = <0x00000000 0x08000000
- 0x88000000 0x18000000>;
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x18000000>;
};
gpio-keys {
diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
new file mode 100644
index 0000000..577a4dc
--- /dev/null
+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * DTS for Meraki MR32 / Codename: Espresso
+ *
+ * Copyright (C) 2018-2020 Christian Lamparter <chunkeey@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708";
+ model = "Meraki MR32";
+
+ chosen {
+ bootargs = " console=ttyS0,115200n8 earlycon";
+ };
+
+ memory@0 {
+ reg = <0x00000000 0x08000000>;
+ device_type = "memory";
+ };
+
+ aliases {
+ serial1 = &uart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sysled3 {
+ function = LED_FUNCTION_FAULT;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
+ panic-indicator;
+ };
+ sysled2 {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ restart {
+ label = "Reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ red {
+ /* SYS-LED 1 - Tricolor */
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_RED>;
+ pwms = <&pwm 0 50000 0>;
+ max-brightness = <255>;
+ };
+
+ green {
+ /* SYS-LED 1 - Tricolor */
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
+ pwms = <&pwm 1 50000 0>;
+ max-brightness = <255>;
+ };
+
+ blue {
+ /* SYS-LED 1 - Tricolor */
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_BLUE>;
+ pwms = <&pwm 2 50000 0>;
+ max-brightness = <255>;
+ };
+ };
+
+ i2c {
+ /*
+ * The platform provided I2C does not budge.
+ * This is a replacement until I can figure
+ * out what are the missing bits...
+ */
+
+ compatible = "i2c-gpio";
+ sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
+ i2c-gpio,delay-us = <10>; /* close to 100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ current_sense: ina219@45 {
+ compatible = "ti,ina219";
+ reg = <0x45>;
+ shunt-resistor = <60000>; /* = 60 mOhms */
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ read-only;
+ };
+ };
+};
+
+&uart0 {
+ clock-frequency = <62500000>;
+ /delete-property/ clocks;
+};
+
+&uart1 {
+ status = "disabled";
+};
+
+&uart2 {
+ status = "okay";
+ /*
+ * bluetooth-le {
+ * compatible = "brcm,bcm20732";
+ * enable-gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>;
+ *};
+ */
+};
+
+&gmac1 {
+ status = "disabled";
+};
+&gmac2 {
+ status = "disabled";
+};
+&gmac3 {
+ status = "disabled";
+};
+
+&pwm {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_pwm>;
+};
+
+&nandcs {
+ nand-ecc-algo = "hw";
+
+ partitions {
+ /*
+ * The partition autodetection does not work for this device.
+ * It will only detect the "nvram" partition with an incorrect size.
+ * [ 1.721667] 1 bcm47xxpart partitions found on MTD device brcmnand.0
+ * [ 1.727962] Creating 1 MTD partitions on "brcmnand.0":
+ * [ 1.733117] 0x000000400000-0x000008000000 : "nvram"
+ */
+
+ compatible = "fixed-partitions";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ partition0@0 {
+ label = "u-boot";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition1@100000 {
+ label = "bootkernel1";
+ reg = <0x100000 0x300000>;
+ read-only;
+ };
+
+ partition2@400000 {
+ label = "nvram";
+ reg = <0x400000 0x100000>;
+ read-only;
+ };
+
+ partition3@500000 {
+ label = "bootkernel2";
+ reg = <0x500000 0x300000>;
+ read-only;
+ };
+
+ partition4@800000 {
+ label = "ubi";
+ reg = <0x800000 0x7780000>;
+ };
+ };
+};
+
+&srab {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+ label = "poe";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+
+ fixed-link {
+ speed = <1000>;
+ duplex-full;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 9711170..9fdad20 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -242,6 +242,8 @@
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
pcie0: pcie@12000 {
@@ -252,6 +254,10 @@
reg = <0x00013000 0x1000>;
};
+ pcie2: pcie@14000 {
+ reg = <0x00014000 0x1000>;
+ };
+
usb2: usb2@21000 {
reg = <0x00021000 0x1000>;
@@ -350,6 +356,14 @@
};
};
+ pwm: pwm@18002000 {
+ compatible = "brcm,iproc-pwm";
+ reg = <0x18002000 0x28>;
+ clocks = <&osc>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
mdio: mdio@18003000 {
compatible = "brcm,iproc-mdio";
reg = <0x18003000 0x8>;
@@ -384,10 +398,19 @@
reg = <0x18105000 0x1000>;
};
+ uart2: serial@18008000 {
+ compatible = "ns16550a";
+ reg = <0x18008000 0x20>;
+ clocks = <&iprocslow>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
i2c0: i2c@18009000 {
compatible = "brcm,iproc-i2c";
reg = <0x18009000 0x50>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
@@ -417,12 +440,12 @@
function = "spi";
};
- i2c {
+ pinmux_i2c: i2c {
groups = "i2c_grp";
function = "i2c";
};
- pwm {
+ pinmux_pwm: pwm {
groups = "pwm0_grp", "pwm1_grp",
"pwm2_grp", "pwm3_grp";
function = "pwm";
diff --git a/arch/arm/boot/dts/bcm94708.dts b/arch/arm/boot/dts/bcm94708.dts
index 3d13e46..d9eb204 100644
--- a/arch/arm/boot/dts/bcm94708.dts
+++ b/arch/arm/boot/dts/bcm94708.dts
@@ -38,7 +38,7 @@
model = "NorthStar SVK (BCM94708)";
compatible = "brcm,bcm94708", "brcm,bcm4708";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/bcm94709.dts b/arch/arm/boot/dts/bcm94709.dts
index 5017b7b..618c812 100644
--- a/arch/arm/boot/dts/bcm94709.dts
+++ b/arch/arm/boot/dts/bcm94709.dts
@@ -38,7 +38,7 @@
model = "NorthStar SVK (BCM94709)";
compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708";
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
index e9b2d3b..5dd1001 100644
--- a/arch/arm/boot/dts/bcm958522er.dts
+++ b/arch/arm/boot/dts/bcm958522er.dts
@@ -58,6 +58,10 @@
/* USB 3 support needed to be complete */
+&dma {
+ status = "okay";
+};
+
&amac0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
index dfe145a..0e624c5 100644
--- a/arch/arm/boot/dts/bcm958525er.dts
+++ b/arch/arm/boot/dts/bcm958525er.dts
@@ -58,6 +58,10 @@
/* USB 3 support needed to be complete */
+&dma {
+ status = "okay";
+};
+
&amac0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index 17e6a68..2ac6d61 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -58,6 +58,10 @@
/* XHCI support needed to be complete */
+&dma {
+ status = "okay";
+};
+
&amac0 {
status = "okay";
};
@@ -192,7 +196,7 @@
};
&sdio {
- status = "ok";
+ status = "okay";
};
&uart0 {
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index 1d1bc8d..e072fa8 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -58,6 +58,10 @@
/* USB 3 and SLIC support needed to be complete */
+&dma {
+ status = "okay";
+};
+
&amac0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index d5d9a27..835f476 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -58,6 +58,10 @@
/* USB 3 and SLIC support needed to be complete */
+&dma {
+ status = "okay";
+};
+
&amac0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index 670363b..57974b8 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -55,18 +55,9 @@
priority = <200>;
};
- /* Hardware I2C block cannot do more than 63 bytes per transfer,
- * which would prevent reading from a SFP's EEPROM (256 byte).
- */
- i2c1: i2c {
- compatible = "i2c-gpio";
- sda-gpios = <&gpioa 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- };
-
sfp: sfp {
compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
+ i2c-bus = <&i2c0>;
mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
@@ -74,6 +65,14 @@
};
};
+&i2c0 {
+ status = "okay";
+};
+
+&dma {
+ status = "okay";
+};
+
&amac0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index f15cd38..45a043e 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -48,6 +48,10 @@
};
};
+&dma {
+ status = "okay";
+};
+
&amac0 {
status = "okay";
};
@@ -204,7 +208,7 @@
&sdio {
bus-width = <4>;
no-1-8-v;
- status = "ok";
+ status = "okay";
};
&srab {
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index d2f7d98..6194857 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -77,7 +77,7 @@
ranges = <0 0xf7000000 0x1000000>;
- sdhci0: sdhci@ab0000 {
+ sdhci0: mmc@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
@@ -86,7 +86,7 @@
status = "disabled";
};
- sdhci1: sdhci@ab0800 {
+ sdhci1: mmc@ab0800 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>;
clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
@@ -95,7 +95,7 @@
status = "disabled";
};
- sdhci2: sdhci@ab1000 {
+ sdhci2: mmc@ab1000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
@@ -106,7 +106,7 @@
status = "disabled";
};
- l2: l2-cache-controller@ac0000 {
+ l2: cache-controller@ac0000 {
compatible = "marvell,tauros3-cache", "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index e5c1f42..6f30d7e 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -62,7 +62,7 @@
ranges = <0 0xf7000000 0x1000000>;
- sdhci0: sdhci@ab0000 {
+ sdhci0: mmc@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
@@ -71,7 +71,7 @@
status = "disabled";
};
- l2: l2-cache-controller@ac0000 {
+ l2: cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 99d6872..b6a0aca 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -122,7 +122,7 @@
ranges = <0 0xf7000000 0x1000000>;
interrupt-parent = <&gic>;
- sdhci0: sdhci@ab0000 {
+ sdhci0: mmc@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
@@ -131,7 +131,7 @@
status = "disabled";
};
- sdhci1: sdhci@ab0800 {
+ sdhci1: mmc@ab0800 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>;
clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
@@ -140,7 +140,7 @@
status = "disabled";
};
- sdhci2: sdhci@ab1000 {
+ sdhci2: mmc@ab1000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
@@ -149,7 +149,7 @@
status = "disabled";
};
- l2: l2-cache-controller@ac0000 {
+ l2: cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/cros-ec-keyboard.dtsi b/arch/arm/boot/dts/cros-ec-keyboard.dtsi
index 4a0c103..165c5bc 100644
--- a/arch/arm/boot/dts/cros-ec-keyboard.dtsi
+++ b/arch/arm/boot/dts/cros-ec-keyboard.dtsi
@@ -46,6 +46,7 @@
MATRIX_KEY(0x02, 0x09, KEY_F8)
MATRIX_KEY(0x02, 0x0a, KEY_YEN)
+ MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA)
MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
MATRIX_KEY(0x03, 0x02, KEY_F2)
MATRIX_KEY(0x03, 0x03, KEY_5)
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index f2e7609..87c517d 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -2,7 +2,7 @@
/*
* Device Tree for DA850 EVM board
*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "da850.dtsi"
diff --git a/arch/arm/boot/dts/dm3725.dtsi b/arch/arm/boot/dts/dm3725.dtsi
new file mode 100644
index 0000000..d24e906
--- /dev/null
+++ b/arch/arm/boot/dts/dm3725.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
+ */
+
+#include "omap36xx.dtsi"
+
+&sgx_module {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi
index e5e4d0a..f7939f4 100644
--- a/arch/arm/boot/dts/dm814x-clocks.dtsi
+++ b/arch/arm/boot/dts/dm814x-clocks.dtsi
@@ -362,4 +362,18 @@
#clock-cells = <2>;
};
};
+
+ alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
+ compatible = "ti,omap4-cm";
+ reg = <0x15d4 0x4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x15d4 0x4>;
+
+ alwon_ethernet_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0 0x4>;
+ #clock-cells = <2>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index 95de9f2..7702e04 100644
--- a/arch/arm/boot/dts/dm814x.dtsi
+++ b/arch/arm/boot/dts/dm814x.dtsi
@@ -4,6 +4,8 @@
* kind, whether express or implied.
*/
+#include <dt-bindings/bus/ti-sysc.h>
+#include <dt-bindings/clock/dm814.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/dm814x.h>
@@ -306,14 +308,30 @@
ti,hwmods = "mcspi4";
};
- timer1: timer@2e000 {
- compatible = "ti,dm814-timer";
- reg = <0x2e000 0x2000>;
- interrupts = <67>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
+ timer1_target: target-module@2e000 {
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x2e000 0x4>,
+ <0x2e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
clocks = <&timer1_fck>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2e000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,am335x-timer-1ms";
+ reg = <0x0 0x400>;
+ interrupts = <67>;
+ ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
+ };
};
uart1: uart@20000 {
@@ -346,13 +364,29 @@
dma-names = "tx", "rx";
};
- timer2: timer@40000 {
- compatible = "ti,dm814-timer";
- reg = <0x40000 0x2000>;
- interrupts = <68>;
- ti,hwmods = "timer2";
+ timer2_target: target-module@40000 {
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x40000 0x4>,
+ <0x40010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
clocks = <&timer2_fck>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,dm814-timer";
+ reg = <0 0x1000>;
+ interrupts = <68>;
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
+ };
};
timer3: timer@42000 {
@@ -519,53 +553,123 @@
reg = <0x47810000 0x1000>;
};
- edma: edma@49000000 {
- compatible = "ti,edma3-tpcc";
- ti,hwmods = "tpcc";
- reg = <0x49000000 0x10000>;
- reg-names = "edma3_cc";
- interrupts = <12 13 14>;
- interrupt-names = "edma3_ccint", "edma3_mperr",
- "edma3_ccerrint";
- dma-requests = <64>;
- #dma-cells = <2>;
+ target-module@49000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49000000 0x4>;
+ reg-names = "rev";
+ clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49000000 0x10000>;
- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
- <&edma_tptc2 3>, <&edma_tptc3 0>;
+ edma: dma@0 {
+ compatible = "ti,edma3-tpcc";
+ reg = <0 0x10000>;
+ reg-names = "edma3_cc";
+ interrupts = <12 13 14>;
+ interrupt-names = "edma3_ccint", "edma3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
- ti,edma-memcpy-channels = <20 21>;
+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
+ <&edma_tptc2 3>, <&edma_tptc3 0>;
+
+ ti,edma-memcpy-channels = <20 21>;
+ };
};
- edma_tptc0: tptc@49800000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc0";
- reg = <0x49800000 0x100000>;
- interrupts = <112>;
- interrupt-names = "edma3_tcerrint";
+ target-module@49800000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49800000 0x4>,
+ <0x49800010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49800000 0x100000>;
+
+ edma_tptc0: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <112>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
- edma_tptc1: tptc@49900000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc1";
- reg = <0x49900000 0x100000>;
- interrupts = <113>;
- interrupt-names = "edma3_tcerrint";
+ target-module@49900000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49900000 0x4>,
+ <0x49900010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49900000 0x100000>;
+
+ edma_tptc1: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <113>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
- edma_tptc2: tptc@49a00000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc2";
- reg = <0x49a00000 0x100000>;
- interrupts = <114>;
- interrupt-names = "edma3_tcerrint";
+ target-module@49a00000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49a00000 0x4>,
+ <0x49a00010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49a00000 0x100000>;
+
+ edma_tptc2: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <114>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
- edma_tptc3: tptc@49b00000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc3";
- reg = <0x49b00000 0x100000>;
- interrupts = <115>;
- interrupt-names = "edma3_tcerrint";
+ target-module@49b00000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49b00000 0x4>,
+ <0x49b00010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49b00000 0x100000>;
+
+ edma_tptc3: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <115>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
/* See TRM "Table 1-318. L4HS Instance Summary" */
@@ -574,57 +678,73 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a000000 0x1b4040>;
- };
- /* REVISIT: Move to live under l4hs once driver is fixed */
- mac: ethernet@4a100000 {
- compatible = "ti,cpsw";
- ti,hwmods = "cpgmac0";
- clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
- clock-names = "fck", "cpts";
- cpdma_channels = <8>;
- ale_entries = <1024>;
- bd_ram_size = <0x2000>;
- mac_control = <0x20>;
- slaves = <2>;
- active_slave = <0>;
- cpts_clock_mult = <0x80000000>;
- cpts_clock_shift = <29>;
- reg = <0x4a100000 0x800
- 0x4a100900 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- /*
- * c0_rx_thresh_pend
- * c0_rx_pend
- * c0_tx_pend
- * c0_misc_pend
- */
- interrupts = <40 41 42 43>;
- ranges;
- syscon = <&scm_conf>;
-
- davinci_mdio: mdio@4a100800 {
- compatible = "ti,davinci_mdio";
+ target-module@100000 {
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ reg = <0x100900 0x4>,
+ <0x100908 0x4>,
+ <0x100904 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <0>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,syss-mask = <1>;
+ clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "davinci_mdio";
- bus_freq = <1000000>;
- reg = <0x4a100800 0x100>;
- };
+ #size-cells = <1>;
+ ranges = <0 0x100000 0x8000>;
- cpsw_emac0: slave@4a100200 {
- /* Filled in by U-Boot */
- mac-address = [ 00 00 00 00 00 00 ];
- phys = <&phy_gmii_sel 1>;
+ mac: ethernet@0 {
+ compatible = "ti,cpsw";
+ clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
+ clock-names = "fck", "cpts";
+ cpdma_channels = <8>;
+ ale_entries = <1024>;
+ bd_ram_size = <0x2000>;
+ mac_control = <0x20>;
+ slaves = <2>;
+ active_slave = <0>;
+ cpts_clock_mult = <0x80000000>;
+ cpts_clock_shift = <29>;
+ reg = <0 0x800>,
+ <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * c0_rx_thresh_pend
+ * c0_rx_pend
+ * c0_tx_pend
+ * c0_misc_pend
+ */
+ interrupts = <40 41 42 43>;
+ ranges = <0 0 0x8000>;
+ syscon = <&scm_conf>;
- };
+ davinci_mdio: mdio@800 {
+ compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
+ clocks = <&cpsw_125mhz_gclk>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ reg = <0x800 0x100>;
+ };
- cpsw_emac1: slave@4a100300 {
- /* Filled in by U-Boot */
- mac-address = [ 00 00 00 00 00 00 ];
- phys = <&phy_gmii_sel 2>;
+ cpsw_emac0: slave@200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ phys = <&phy_gmii_sel 1>;
+ };
+
+ cpsw_emac1: slave@300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ phys = <&phy_gmii_sel 2>;
+ };
+ };
};
};
@@ -647,3 +767,23 @@
};
#include "dm814x-clocks.dtsi"
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer1_fck>;
+ assigned-clock-parents = <&devosc_ck>;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer2_fck>;
+ assigned-clock-parents = <&devosc_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 1edc2b4..1825d91 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -4,6 +4,8 @@
* kind, whether express or implied.
*/
+#include <dt-bindings/bus/ti-sysc.h>
+#include <dt-bindings/clock/dm816.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/omap.h>
@@ -138,13 +140,123 @@
};
};
- edma: edma@49000000 {
- compatible = "ti,edma3";
- ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
- reg = <0x49000000 0x10000>,
- <0x44e10f90 0x40>;
- interrupts = <12 13 14>;
- #dma-cells = <1>;
+ target-module@49000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49000000 0x4>;
+ reg-names = "rev";
+ clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49000000 0x10000>;
+
+ edma: dma@0 {
+ compatible = "ti,edma3-tpcc";
+ reg = <0 0x10000>;
+ reg-names = "edma3_cc";
+ interrupts = <12 13 14>;
+ interrupt-names = "edma3_ccint", "edma3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
+ <&edma_tptc2 3>, <&edma_tptc3 0>;
+
+ ti,edma-memcpy-channels = <20 21>;
+ };
+ };
+
+ target-module@49800000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49800000 0x4>,
+ <0x49800010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49800000 0x100000>;
+
+ edma_tptc0: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <112>;
+ interrupt-names = "edma3_tcerrint";
+ };
+ };
+
+ target-module@49900000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49900000 0x4>,
+ <0x49900010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49900000 0x100000>;
+
+ edma_tptc1: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <113>;
+ interrupt-names = "edma3_tcerrint";
+ };
+ };
+
+ target-module@49a00000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49a00000 0x4>,
+ <0x49a00010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49a00000 0x100000>;
+
+ edma_tptc2: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <114>;
+ interrupt-names = "edma3_tcerrint";
+ };
+ };
+
+ target-module@49b00000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49b00000 0x4>,
+ <0x49b00010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49b00000 0x100000>;
+
+ edma_tptc3: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <115>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
elm: elm@48080000 {
@@ -185,7 +297,7 @@
#address-cells = <2>;
#size-cells = <1>;
interrupts = <100>;
- dmas = <&edma 52>;
+ dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <6>;
gpmc,num-waitpins = <2>;
@@ -202,7 +314,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <70>;
- dmas = <&edma 58 &edma 59>;
+ dmas = <&edma 58 0 &edma 59 0>;
dma-names = "tx", "rx";
};
@@ -213,7 +325,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <71>;
- dmas = <&edma 60 &edma 61>;
+ dmas = <&edma 60 0 &edma 61 0>;
dma-names = "tx", "rx";
};
@@ -239,7 +351,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
- mbox_dsp: mbox_dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <0 0 0>;
};
@@ -311,10 +423,10 @@
interrupts = <65>;
ti,spi-num-cs = <4>;
ti,hwmods = "mcspi1";
- dmas = <&edma 16 &edma 17
- &edma 18 &edma 19
- &edma 20 &edma 21
- &edma 22 &edma 23>;
+ dmas = <&edma 16 0 &edma 17 0
+ &edma 18 0 &edma 19 0
+ &edma 20 0 &edma 21 0
+ &edma 22 0 &edma 23 0>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
};
@@ -324,27 +436,59 @@
reg = <0x48060000 0x11000>;
ti,hwmods = "mmc1";
interrupts = <64>;
- dmas = <&edma 24 &edma 25>;
+ dmas = <&edma 24 0 &edma 25 0>;
dma-names = "tx", "rx";
};
- timer1: timer@4802e000 {
- compatible = "ti,dm816-timer";
- reg = <0x4802e000 0x2000>;
- interrupts = <67>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
- clocks = <&timer1_fck>;
+ timer1_target: target-module@4802e000 {
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x4802e000 0x4>,
+ <0x4802e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4802e000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,dm816-timer";
+ reg = <0 0x1000>;
+ interrupts = <67>;
+ ti,timer-alwon;
+ clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
+ clock-names = "fck";
+ };
};
- timer2: timer@48040000 {
- compatible = "ti,dm816-timer";
- reg = <0x48040000 0x2000>;
- interrupts = <68>;
- ti,hwmods = "timer2";
- clocks = <&timer2_fck>;
+ timer2_target: target-module@48040000 {
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x48040000 0x4>,
+ <0x48040010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48040000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,dm816-timer";
+ reg = <0 0x1000>;
+ interrupts = <68>;
+ clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ };
};
timer3: timer@48042000 {
@@ -392,7 +536,7 @@
reg = <0x48020000 0x2000>;
clock-frequency = <48000000>;
interrupts = <72>;
- dmas = <&edma 26 &edma 27>;
+ dmas = <&edma 26 0 &edma 27 0>;
dma-names = "tx", "rx";
};
@@ -402,7 +546,7 @@
reg = <0x48022000 0x2000>;
clock-frequency = <48000000>;
interrupts = <73>;
- dmas = <&edma 28 &edma 29>;
+ dmas = <&edma 28 0 &edma 29 0>;
dma-names = "tx", "rx";
};
@@ -412,7 +556,7 @@
reg = <0x48024000 0x2000>;
clock-frequency = <48000000>;
interrupts = <74>;
- dmas = <&edma 30 &edma 31>;
+ dmas = <&edma 30 0 &edma 31 0>;
dma-names = "tx", "rx";
};
@@ -530,3 +674,23 @@
};
#include "dm816x-clocks.dtsi"
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer1_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer2_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 2e8a397..89e0bda 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -175,7 +175,6 @@
#size-cells = <0>;
interrupts = <11>;
clock-frequency = <400000>;
- timeout-ms = <1000>;
clocks = <&core_clk 0>;
status = "okay";
};
@@ -248,7 +247,7 @@
marvell,#interrupts = <5>;
};
- intc: main-interrupt-ctrl@20200 {
+ intc: interrupt-controller@20200 {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
@@ -784,7 +783,7 @@
status = "disabled";
};
- crypto_sram: sa-sram@ffffe000 {
+ crypto_sram: sram@ffffe000 {
compatible = "mmio-sram";
reg = <0xffffe000 0x800>;
clocks = <&gate_clk 15>;
diff --git a/arch/arm/boot/dts/dra62x.dtsi b/arch/arm/boot/dts/dra62x.dtsi
index d3cbb4e..cc4878a 100644
--- a/arch/arm/boot/dts/dra62x.dtsi
+++ b/arch/arm/boot/dts/dra62x.dtsi
@@ -12,12 +12,12 @@
/* Compared to dm814x, dra62x has different offsets for Ethernet */
&mac {
- reg = <0x4a100000 0x800
- 0x4a101200 0x100>;
+ reg = <0 0x800>,
+ <0x1200 0x100>;
};
&davinci_mdio {
- reg = <0x4a101000 0x100>;
+ reg = <0x1000 0x100>;
};
#include "dra62x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
index 1c39a84..e755693 100644
--- a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
+++ b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for DRA7x SoC DSPEVE thermal
*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi
index 82eeba8..0f71a9f 100644
--- a/arch/arm/boot/dts/dra7-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra7-evm-common.dtsi
@@ -1,10 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include "dra74-ipu-dsp-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clk/ti-dra7-atl.h>
+#include <dt-bindings/clock/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>
/ {
@@ -244,26 +245,6 @@
rx-num-evt = <32>;
};
-&mailbox5 {
- status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- status = "okay";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- status = "okay";
- };
-};
-
-&mailbox6 {
- status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- status = "okay";
- };
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
- status = "okay";
- };
-};
-
&pcie1_rc {
status = "okay";
};
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index de7f85e..38530db 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -35,6 +35,40 @@
regulator-max-microvolt = <1800000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipu2_memory_region: ipu2-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_memory_region: dsp1-memory@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_memory_region: ipu1-memory@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp2_memory_region: dsp2-memory@9f000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9f000000 0x0 0x800000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
@@ -61,10 +95,10 @@
regulator-max-microvolt = <1800000>;
};
- evm_3v3: fixedregulator-evm3v3 {
+ vsys_3v3: fixedregulator-vsys3v3 {
/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
compatible = "regulator-fixed";
- regulator-name = "evm_3v3";
+ regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
@@ -503,24 +537,23 @@
ti,no-idle-on-init;
};
-&mac {
+&mac_sw {
status = "okay";
- dual_emac;
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <ðphy0>;
phy-mode = "rgmii";
- dual_emac_res_vlan = <1>;
+ ti,dual-emac-pvid = <1>;
};
-&cpsw_emac1 {
+&cpsw_port2 {
phy-handle = <ðphy1>;
phy-mode = "rgmii";
- dual_emac_res_vlan = <2>;
+ ti,dual-emac-pvid = <2>;
};
-&davinci_mdio {
+&davinci_mdio_sw {
ethphy0: ethernet-phy@2 {
reg = <2>;
};
@@ -531,9 +564,29 @@
};
&dcan1 {
- status = "ok";
+ status = "okay";
pinctrl-names = "default", "sleep", "active";
pinctrl-0 = <&dcan1_pins_sleep>;
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
+
+&ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_memory_region>;
+};
+
+&ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_memory_region>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_memory_region>;
+};
+
+&dsp2 {
+ status = "okay";
+ memory-region = <&dsp2_memory_region>;
+};
diff --git a/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi
new file mode 100644
index 0000000..a5bdc64
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common IPU and DSP data for TI DRA7xx/AM57xx platforms
+ */
+
+&mailbox5 {
+ status = "okay";
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
+ status = "okay";
+ };
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
+ status = "okay";
+ };
+};
+
+&mailbox6 {
+ status = "okay";
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
+ status = "okay";
+ };
+};
+
+&ipu2 {
+ mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
+ ti,timers = <&timer3>;
+ ti,watchdog-timers = <&timer4>, <&timer9>;
+};
+
+&ipu1 {
+ mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
+ ti,timers = <&timer11>;
+ ti,watchdog-timers = <&timer7>, <&timer8>;
+};
+
+&dsp1 {
+ mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
+ ti,timers = <&timer5>;
+ ti,watchdog-timers = <&timer10>;
+};
diff --git a/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/dra7-iva-thermal.dtsi
index dd74a53..a707732 100644
--- a/arch/arm/boot/dts/dra7-iva-thermal.dtsi
+++ b/arch/arm/boot/dts/dra7-iva-thermal.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for DRA7x SoC IVA thermal
*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 3f845a8..30b72f4 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -186,7 +186,6 @@
target-module@56000 { /* 0x4a056000, ap 9 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "dma_system";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
@@ -212,7 +211,7 @@
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
- compatible = "ti,omap4430-sdma";
+ compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
@@ -234,7 +233,6 @@
target-module@80000 { /* 0x4a080000, ap 13 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "ocp2scp1";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@@ -302,7 +300,6 @@
target-module@90000 { /* 0x4a090000, ap 59 42.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "ocp2scp3";
reg = <0x90000 0x4>,
<0x90010 0x4>,
<0x90014 0x4>;
@@ -394,7 +391,6 @@
target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
- ti,hwmods = "smartreflex_mpu";
reg = <0xd9038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@@ -414,7 +410,6 @@
target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
- ti,hwmods = "smartreflex_core";
reg = <0xdd038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@@ -442,7 +437,6 @@
target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox1";
reg = <0xf4000 0x4>,
<0xf4010 0x4>;
reg-names = "rev", "sysc";
@@ -472,7 +466,6 @@
target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spinlock";
reg = <0xf6000 0x4>,
<0xf6010 0x4>,
<0xf6014 0x4>;
@@ -1150,7 +1143,6 @@
target-module@32000 { /* 0x48032000, ap 5 3e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer2";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
@@ -1170,15 +1162,14 @@
timer2: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
};
};
timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer3";
reg = <0x34000 0x4>,
<0x34010 0x4>;
reg-names = "rev", "sysc";
@@ -1198,15 +1189,14 @@
timer3: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
};
timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer4";
reg = <0x36000 0x4>,
<0x36010 0x4>;
reg-names = "rev", "sysc";
@@ -1226,15 +1216,14 @@
timer4: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer9";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -1254,8 +1243,8 @@
timer9: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -1749,7 +1738,6 @@
target-module@78000 { /* 0x48078000, ap 39 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "elm";
reg = <0x78000 0x4>,
<0x78010 0x4>,
<0x78014 0x4>;
@@ -1843,7 +1831,6 @@
target-module@86000 { /* 0x48086000, ap 41 5e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer10";
reg = <0x86000 0x4>,
<0x86010 0x4>;
reg-names = "rev", "sysc";
@@ -1863,15 +1850,14 @@
timer10: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@88000 { /* 0x48088000, ap 43 66.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer11";
reg = <0x88000 0x4>,
<0x88010 0x4>;
reg-names = "rev", "sysc";
@@ -1891,15 +1877,14 @@
timer11: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@90000 { /* 0x48090000, ap 55 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "rng";
reg = <0x91fe0 0x4>,
<0x91fe4 0x4>;
reg-names = "rev", "sysc";
@@ -2046,6 +2031,37 @@
<0x00001000 0x000a5000 0x00001000>;
};
+ des_target: target-module@a5000 { /* 0x480a5000 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xa5030 0x4>,
+ <0xa5034 0x4>,
+ <0xa5038 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa5000 0x00001000>;
+
+ des: des@0 {
+ compatible = "ti,omap4-des";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
+ };
+
target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
compatible = "ti,sysc";
status = "disabled";
@@ -2090,7 +2106,6 @@
target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "hdq1w";
reg = <0xb2000 0x4>,
<0xb2014 0x4>,
<0xb2018 0x4>;
@@ -2493,7 +2508,6 @@
target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss0";
reg = <0x3e000 0x4>,
<0x3e004 0x4>;
reg-names = "rev", "sysc";
@@ -2540,7 +2554,6 @@
target-module@40000 { /* 0x48440000, ap 27 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss1";
reg = <0x40000 0x4>,
<0x40004 0x4>;
reg-names = "rev", "sysc";
@@ -2587,7 +2600,6 @@
target-module@42000 { /* 0x48442000, ap 29 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "epwmss2";
reg = <0x42000 0x4>,
<0x42004 0x4>;
reg-names = "rev", "sysc";
@@ -3026,38 +3038,43 @@
*/
ti,no-idle;
- mac: ethernet@0 {
- compatible = "ti,dra7-cpsw","ti,cpsw";
- clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
- clock-names = "fck", "cpts";
- cpdma_channels = <8>;
- ale_entries = <1024>;
- bd_ram_size = <0x2000>;
- mac_control = <0x20>;
- slaves = <2>;
- active_slave = <0>;
- cpts_clock_mult = <0x784CFE14>;
- cpts_clock_shift = <29>;
- reg = <0x0 0x1000
- 0x1200 0x2e00>;
+ mac_sw: switch@0 {
+ compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
+ reg = <0x0 0x4000>;
+ ranges = <0 0 0x4000>;
+ clocks = <&gmac_main_clk>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
+ syscon = <&scm_conf>;
+ status = "disabled";
- /*
- * rx_thresh_pend
- * rx_pend
- * tx_pend
- * misc_pend
- */
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
- ranges = <0 0 0x4000>;
- syscon = <&scm_conf>;
- status = "disabled";
+ interrupt-names = "rx_thresh", "rx", "tx", "misc";
- davinci_mdio: mdio@1000 {
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ label = "port1";
+ mac-address = [ 00 00 00 00 00 00 ];
+ phys = <&phy_gmii_sel 1>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ label = "port2";
+ mac-address = [ 00 00 00 00 00 00 ];
+ phys = <&phy_gmii_sel 2>;
+ };
+ };
+
+ davinci_mdio_sw: mdio@1000 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
clocks = <&gmac_main_clk>;
clock-names = "fck";
@@ -3067,16 +3084,9 @@
reg = <0x1000 0x100>;
};
- cpsw_emac0: slave@200 {
- /* Filled in by U-Boot */
- mac-address = [ 00 00 00 00 00 00 ];
- phys = <&phy_gmii_sel 1>;
- };
-
- cpsw_emac1: slave@300 {
- /* Filled in by U-Boot */
- mac-address = [ 00 00 00 00 00 00 ];
- phys = <&phy_gmii_sel 2>;
+ cpts {
+ clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
+ clock-names = "cpts";
};
};
};
@@ -3199,7 +3209,6 @@
target-module@2000 { /* 0x48802000, ap 95 7c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox13";
reg = <0x2000 0x4>,
<0x2010 0x4>;
reg-names = "rev", "sysc";
@@ -3278,7 +3287,6 @@
target-module@20000 { /* 0x48820000, ap 5 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer5";
reg = <0x20000 0x4>,
<0x20010 0x4>;
reg-names = "rev", "sysc";
@@ -3298,15 +3306,14 @@
timer5: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@22000 { /* 0x48822000, ap 7 24.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer6";
reg = <0x22000 0x4>,
<0x22010 0x4>;
reg-names = "rev", "sysc";
@@ -3326,15 +3333,14 @@
timer6: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@24000 { /* 0x48824000, ap 9 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer7";
reg = <0x24000 0x4>,
<0x24010 0x4>;
reg-names = "rev", "sysc";
@@ -3354,15 +3360,14 @@
timer7: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@26000 { /* 0x48826000, ap 11 0c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer8";
reg = <0x26000 0x4>,
<0x26010 0x4>;
reg-names = "rev", "sysc";
@@ -3382,15 +3387,14 @@
timer8: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@28000 { /* 0x48828000, ap 13 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer13";
reg = <0x28000 0x4>,
<0x28010 0x4>;
reg-names = "rev", "sysc";
@@ -3410,8 +3414,8 @@
timer13: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
@@ -3419,7 +3423,6 @@
target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer14";
reg = <0x2a000 0x4>,
<0x2a010 0x4>;
reg-names = "rev", "sysc";
@@ -3439,8 +3442,8 @@
timer14: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
@@ -3448,7 +3451,6 @@
target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer15";
reg = <0x2c000 0x4>,
<0x2c010 0x4>;
reg-names = "rev", "sysc";
@@ -3468,8 +3470,8 @@
timer15: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
@@ -3477,7 +3479,6 @@
target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer16";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
@@ -3497,8 +3498,8 @@
timer16: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
@@ -3506,7 +3507,6 @@
rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "rtcss";
reg = <0x38074 0x4>,
<0x38078 0x4>;
reg-names = "rev", "sysc";
@@ -3532,7 +3532,6 @@
target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox2";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
@@ -3563,7 +3562,6 @@
target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox3";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
@@ -3594,7 +3592,6 @@
target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox4";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -3625,7 +3622,6 @@
target-module@40000 { /* 0x48840000, ap 39 64.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox5";
reg = <0x40000 0x4>,
<0x40010 0x4>;
reg-names = "rev", "sysc";
@@ -3656,7 +3652,6 @@
target-module@42000 { /* 0x48842000, ap 41 4e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox6";
reg = <0x42000 0x4>,
<0x42010 0x4>;
reg-names = "rev", "sysc";
@@ -3687,7 +3682,6 @@
target-module@44000 { /* 0x48844000, ap 43 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox7";
reg = <0x44000 0x4>,
<0x44010 0x4>;
reg-names = "rev", "sysc";
@@ -3718,7 +3712,6 @@
target-module@46000 { /* 0x48846000, ap 45 48.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox8";
reg = <0x46000 0x4>,
<0x46010 0x4>;
reg-names = "rev", "sysc";
@@ -3837,7 +3830,6 @@
target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox9";
reg = <0x5e000 0x4>,
<0x5e010 0x4>;
reg-names = "rev", "sysc";
@@ -3868,7 +3860,6 @@
target-module@60000 { /* 0x48860000, ap 71 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox10";
reg = <0x60000 0x4>,
<0x60010 0x4>;
reg-names = "rev", "sysc";
@@ -3899,7 +3890,6 @@
target-module@62000 { /* 0x48862000, ap 73 74.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox11";
reg = <0x62000 0x4>,
<0x62010 0x4>;
reg-names = "rev", "sysc";
@@ -3930,7 +3920,6 @@
target-module@64000 { /* 0x48864000, ap 67 52.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox12";
reg = <0x64000 0x4>,
<0x64010 0x4>;
reg-names = "rev", "sysc";
@@ -3961,7 +3950,6 @@
target-module@80000 { /* 0x48880000, ap 83 0e.1 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_otg_ss1";
reg = <0x80000 0x4>,
<0x80010 0x4>;
reg-names = "rev", "sysc";
@@ -4011,7 +3999,6 @@
target-module@c0000 { /* 0x488c0000, ap 79 06.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_otg_ss2";
reg = <0xc0000 0x4>,
<0xc0010 0x4>;
reg-names = "rev", "sysc";
@@ -4062,7 +4049,6 @@
usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_otg_ss3";
reg = <0x100000 0x4>,
<0x100010 0x4>;
reg-names = "rev", "sysc";
@@ -4109,59 +4095,89 @@
};
};
- usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
+ target-module@170000 { /* 0x48970000, ap 21 0a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_otg_ss4";
- reg = <0x140000 0x4>,
- <0x140010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
+ reg = <0x170010 0x4>;
+ reg-names = "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
+ <SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
+ <SYSC_IDLE_SMART>;
+ clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x140000 0x20000>;
- };
-
- target-module@170000 { /* 0x48970000, ap 21 0a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
ranges = <0x0 0x170000 0x10000>;
+ status = "disabled";
};
target-module@190000 { /* 0x48990000, ap 23 2e.0 */
- compatible = "ti,sysc";
- status = "disabled";
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x190010 0x4>;
+ reg-names = "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x190000 0x10000>;
+ status = "disabled";
};
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
- compatible = "ti,sysc";
- status = "disabled";
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x1b0000 0x4>,
+ <0x1b0010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1b0000 0x10000>;
+ status = "disabled";
};
- target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */
- compatible = "ti,sysc";
- status = "disabled";
+ target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x1d0010 0x4>;
+ reg-names = "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1d0000 0x10000>;
+
+ vpe: vpe@0 {
+ compatible = "ti,dra7-vpe";
+ reg = <0x0000 0x120>,
+ <0x0700 0x80>,
+ <0x5700 0x18>,
+ <0xd000 0x400>;
+ reg-names = "vpe_top",
+ "sc",
+ "csc",
+ "vpdma";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};
};
@@ -4195,7 +4211,6 @@
target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4010 0x4>;
reg-names = "rev", "sysc";
@@ -4305,7 +4320,6 @@
target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "wd_timer2";
reg = <0x4000 0x4>,
<0x4010 0x4>,
<0x4014 0x4>;
@@ -4331,9 +4345,8 @@
};
};
- target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
+ timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>;
reg-names = "rev", "sysc";
@@ -4390,7 +4403,6 @@
target-module@0 { /* 0x4ae20000, ap 19 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer12";
reg = <0x0 0x4>,
<0x10 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f73324c..7ecf8f8 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on "omap4.dtsi"
*/
@@ -37,8 +37,8 @@
serial7 = &uart8;
serial8 = &uart9;
serial9 = &uart10;
- ethernet0 = &cpsw_emac0;
- ethernet1 = &cpsw_emac1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
d_can0 = &dcan1;
d_can1 = &dcan2;
spi0 = &qspi;
@@ -144,7 +144,7 @@
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
- ocp {
+ ocp: ocp {
compatible = "ti,dra7-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -335,43 +335,73 @@
#pinctrl-cells = <2>;
};
- edma: edma@43300000 {
- compatible = "ti,edma3-tpcc";
- ti,hwmods = "tpcc";
- reg = <0x43300000 0x100000>;
- reg-names = "edma3_cc";
- interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma3_ccint", "edma3_mperr",
- "edma3_ccerrint";
- dma-requests = <64>;
- #dma-cells = <2>;
+ target-module@43300000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x43300000 0x4>;
+ reg-names = "rev";
+ clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x43300000 0x100000>;
- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
+ edma: dma@0 {
+ compatible = "ti,edma3-tpcc";
+ reg = <0 0x100000>;
+ reg-names = "edma3_cc";
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_ccint", "edma3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
- /*
- * memcpy is disabled, can be enabled with:
- * ti,edma-memcpy-channels = <20 21>;
- * for example. Note that these channels need to be
- * masked in the xbar as well.
- */
+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
+
+ /*
+ * memcpy is disabled, can be enabled with:
+ * ti,edma-memcpy-channels = <20 21>;
+ * for example. Note that these channels need to be
+ * masked in the xbar as well.
+ */
+ };
};
- edma_tptc0: tptc@43400000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc0";
- reg = <0x43400000 0x100000>;
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma3_tcerrint";
+ target-module@43400000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x43400000 0x4>;
+ reg-names = "rev";
+ clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x43400000 0x100000>;
+
+ edma_tptc0: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
- edma_tptc1: tptc@43500000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc1";
- reg = <0x43500000 0x100000>;
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "edma3_tcerrint";
+ target-module@43500000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x43500000 0x4>;
+ reg-names = "rev";
+ clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x43500000 0x100000>;
+
+ edma_tptc1: dma@0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
dmm@4e000000 {
@@ -381,44 +411,156 @@
ti,hwmods = "dmm";
};
- mmu0_dsp1: mmu@40d01000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x40d01000 0x100>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu0_dsp1";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp1_system 0x0>;
+ ipu1: ipu@58820000 {
+ compatible = "ti,dra7-ipu";
+ reg = <0x58820000 0x10000>;
+ reg-names = "l2ram";
+ iommus = <&mmu_ipu1>;
status = "disabled";
+ resets = <&prm_ipu 0>, <&prm_ipu 1>;
+ clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
+ firmware-name = "dra7-ipu1-fw.xem4";
};
- mmu1_dsp1: mmu@40d02000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x40d02000 0x100>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu1_dsp1";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp1_system 0x1>;
+ ipu2: ipu@55020000 {
+ compatible = "ti,dra7-ipu";
+ reg = <0x55020000 0x10000>;
+ reg-names = "l2ram";
+ iommus = <&mmu_ipu2>;
status = "disabled";
+ resets = <&prm_core 0>, <&prm_core 1>;
+ clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
+ firmware-name = "dra7-ipu2-fw.xem4";
};
- mmu_ipu1: mmu@58882000 {
- compatible = "ti,dra7-iommu";
- reg = <0x58882000 0x100>;
- interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu1";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
+ dsp1: dsp@40800000 {
+ compatible = "ti,dra7-dsp";
+ reg = <0x40800000 0x48000>,
+ <0x40e00000 0x8000>,
+ <0x40f00000 0x8000>;
+ reg-names = "l2ram", "l1pram", "l1dram";
+ ti,bootreg = <&scm_conf 0x55c 10>;
+ iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
status = "disabled";
+ resets = <&prm_dsp1 0>;
+ clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
+ firmware-name = "dra7-dsp1-fw.xe66";
};
- mmu_ipu2: mmu@55082000 {
- compatible = "ti,dra7-iommu";
- reg = <0x55082000 0x100>;
- interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu2";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
- status = "disabled";
+ target-module@40d01000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x40d01000 0x4>,
+ <0x40d01010 0x4>,
+ <0x40d01014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp1 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x40d01000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu0_dsp1: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x0>;
+ };
+ };
+
+ target-module@40d02000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x40d02000 0x4>,
+ <0x40d02010 0x4>,
+ <0x40d02014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp1 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x40d02000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu1_dsp1: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp1_system 0x1>;
+ };
+ };
+
+ target-module@58882000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58882000 0x4>,
+ <0x58882010 0x4>,
+ <0x58882014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_ipu 2>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x58882000 0x100>;
+
+ mmu_ipu1: mmu@0 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
+ };
+
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x55082000 0x100>;
+
+ mmu_ipu2: mmu@0 {
+ compatible = "ti,dra7-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
abb_mpu: regulator-abb-mpu {
@@ -601,6 +743,24 @@
status = "disabled";
};
+ target-module@56000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5600fe00 0x4>,
+ <0x5600fe10 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x56000000 0x2000000>;
+ };
+
crossbar_mpu: crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
@@ -615,89 +775,192 @@
ti,irqs-safe-map = <0>;
};
- dss: dss@58000000 {
- compatible = "ti,dra7-dss";
- /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
- /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
- status = "disabled";
- ti,hwmods = "dss_core";
- /* CTRL_CORE_DSS_PLL_CONTROL */
- syscon-pll-ctrl = <&scm_conf 0x538>;
+ target-module@58000000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58000000 4>,
+ <0x58000014 4>;
+ reg-names = "rev", "syss";
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>;
+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0 0x58000000 0x800000>;
- dispc@58001000 {
- compatible = "ti,dra7-dispc";
- reg = <0x58001000 0x1000>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "dss_dispc";
- clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- /* CTRL_CORE_SMA_SW_1 */
- syscon-pol = <&scm_conf 0x534>;
- };
-
- hdmi: encoder@58060000 {
- compatible = "ti,dra7-hdmi";
- reg = <0x58040000 0x200>,
- <0x58040200 0x80>,
- <0x58040300 0x80>,
- <0x58060000 0x19000>;
- reg-names = "wp", "pll", "phy", "core";
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ dss: dss@0 {
+ compatible = "ti,dra7-dss";
+ /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
+ /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
status = "disabled";
- ti,hwmods = "dss_hdmi";
- clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
- <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
- clock-names = "fck", "sys_clk";
- dmas = <&sdma_xbar 76>;
- dma-names = "audio_tx";
+ /* CTRL_CORE_DSS_PLL_CONTROL */
+ syscon-pll-ctrl = <&scm_conf 0x538>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x800000>;
+
+ target-module@1000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x1000 0x4>,
+ <0x1010 0x4>,
+ <0x1014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x1000>;
+
+ dispc@0 {
+ compatible = "ti,dra7-dispc";
+ reg = <0 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ /* CTRL_CORE_SMA_SW_1 */
+ syscon-pol = <&scm_conf 0x534>;
+ };
+ };
+
+ target-module@40000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x40000 0x4>,
+ <0x40010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck", "dss_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40000 0x40000>;
+
+ hdmi: encoder@0 {
+ compatible = "ti,dra7-hdmi";
+ reg = <0 0x200>,
+ <0x200 0x80>,
+ <0x300 0x80>,
+ <0x20000 0x19000>;
+ reg-names = "wp", "pll", "phy", "core";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ dmas = <&sdma_xbar 76>;
+ dma-names = "audio_tx";
+ };
+ };
};
};
- aes1: aes@4b500000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes1";
- reg = <0x4b500000 0xa0>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
- dma-names = "tx", "rx";
- clocks = <&l3_iclk_div>;
+ aes1_target: target-module@4b500000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b500080 0x4>,
+ <0x4b500084 0x4>,
+ <0x4b500088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b500000 0x1000>;
+
+ aes1: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
};
- aes2: aes@4b700000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes2";
- reg = <0x4b700000 0xa0>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
- dma-names = "tx", "rx";
- clocks = <&l3_iclk_div>;
+ aes2_target: target-module@4b700000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b700080 0x4>,
+ <0x4b700084 0x4>,
+ <0x4b700088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b700000 0x1000>;
+
+ aes2: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
+ dma-names = "tx", "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
};
- des: des@480a5000 {
- compatible = "ti,omap4-des";
- ti,hwmods = "des";
- reg = <0x480a5000 0xa0>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
- dma-names = "tx", "rx";
- clocks = <&l3_iclk_div>;
+ sham_target: target-module@4b101000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x4b101100 0x4>,
+ <0x4b101110 0x4>,
+ <0x4b101114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
clock-names = "fck";
- };
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b101000 0x1000>;
- sham: sham@53100000 {
- compatible = "ti,omap5-sham";
- ti,hwmods = "sham";
- reg = <0x4b101000 0x300>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&edma_xbar 119 0>;
- dma-names = "rx";
- clocks = <&l3_iclk_div>;
- clock-names = "fck";
+ sham: sham@0 {
+ compatible = "ti,omap5-sham";
+ reg = <0 0x300>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&edma_xbar 119 0>;
+ dma-names = "rx";
+ clocks = <&l3_iclk_div>;
+ clock-names = "fck";
+ };
};
opp_supply_mpu: opp-supply@4a003b20 {
@@ -768,6 +1031,67 @@
#include "dra7-l4.dtsi"
#include "dra7xx-clocks.dtsi"
+&prm {
+ prm_dsp1: prm@400 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_ipu: prm@500 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x500 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_iva: prm@f00 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0xf00 0x100>;
+ };
+
+ prm_dsp2: prm@1b00 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1b00 0x40>;
+ #reset-cells = <1>;
+ };
+
+ prm_eve1: prm@1b40 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1b40 0x40>;
+ };
+
+ prm_eve2: prm@1b80 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1b80 0x40>;
+ };
+
+ prm_eve3: prm@1bc0 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1bc0 0x40>;
+ };
+
+ prm_eve4: prm@1c00 {
+ compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1c00 0x60>;
+ };
+};
+
+/* Preferred always-on timer for clockevent */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_32k_ck>;
+ };
+};
+
/* Local timers, see ARM architected timer wrap erratum i940 */
&timer3_target {
ti,no-reset-on-init;
diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
index fabeb77..cad58f7 100644
--- a/arch/arm/boot/dts/dra71-evm.dts
+++ b/arch/arm/boot/dts/dra71-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra71x.dtsi"
@@ -17,6 +17,33 @@
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipu2_memory_region: ipu2-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_memory_region: dsp1-memory@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_memory_region: ipu1-memory@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
vpo_sd_1v8_3v3: gpio-regulator-TPS74801 {
compatible = "regulator-gpio";
@@ -192,26 +219,26 @@
vqmmc-supply = <&evm_1v8_sw>;
};
-&mac {
+&mac_sw {
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
<&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
<&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
- dual_emac;
+ status = "okay";
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <&dp83867_0>;
phy-mode = "rgmii-id";
- dual_emac_res_vlan = <1>;
+ ti,dual-emac-pvid = <1>;
};
-&cpsw_emac1 {
+&cpsw_port2 {
phy-handle = <&dp83867_1>;
phy-mode = "rgmii-id";
- dual_emac_res_vlan = <2>;
+ ti,dual-emac-pvid = <2>;
};
-&davinci_mdio {
+&davinci_mdio_sw {
dp83867_0: ethernet-phy@2 {
reg = <2>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -270,3 +297,18 @@
&extcon_usb2 {
vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>;
};
+
+&ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_memory_region>;
+};
+
+&ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_memory_region>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_memory_region>;
+};
diff --git a/arch/arm/boot/dts/dra71x.dtsi b/arch/arm/boot/dts/dra71x.dtsi
index 695a08e..9c270d8 100644
--- a/arch/arm/boot/dts/dra71x.dtsi
+++ b/arch/arm/boot/dts/dra71x.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -11,7 +11,3 @@
&rtctarget {
status = "disabled";
};
-
-&usb4_tm {
- status = "disabled";
-};
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 8641a3d..b65b2dd 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -1,12 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "dra72x.dtsi"
+#include "dra7-ipu-dsp-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clk/ti-dra7-atl.h>
+#include <dt-bindings/clock/ti-dra7-atl.h>
/ {
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
@@ -187,6 +188,12 @@
gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ clk_ov5640_fixed: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
};
&dra7_pmx_core {
@@ -269,6 +276,23 @@
line-name = "vin6_sel_s0";
};
};
+
+ ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2_phy0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
};
&uart1 {
@@ -438,12 +462,8 @@
};
};
-&mac {
- status = "okay";
-};
-
&dcan1 {
- status = "ok";
+ status = "okay";
pinctrl-names = "default", "sleep", "active";
pinctrl-0 = <&dcan1_pins_sleep>;
pinctrl-1 = <&dcan1_pins_sleep>;
@@ -512,11 +532,11 @@
};
&dss {
- status = "ok";
+ status = "okay";
};
&hdmi {
- status = "ok";
+ status = "okay";
port {
hdmi_out: endpoint {
@@ -560,23 +580,14 @@
rx-num-evt = <32>;
};
-&mailbox5 {
- status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
- status = "okay";
- };
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
- status = "okay";
- };
-};
-
-&mailbox6 {
- status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
- status = "okay";
- };
-};
-
&pcie1_rc {
status = "okay";
};
+
+&csi2_0 {
+ csi2_phy0: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+};
diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts
index 2bb2e8b..f242b93 100644
--- a/arch/arm/boot/dts/dra72-evm-revc.dts
+++ b/arch/arm/boot/dts/dra72-evm-revc.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra72-evm-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
@@ -14,6 +14,33 @@
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipu2_cma_pool: ipu2_cma@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_cma_pool: dsp1_cma@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_cma_pool: ipu1_cma@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
evm_1v8_sw: fixedregulator-evm_1v8 {
compatible = "regulator-fixed";
regulator-name = "evm_1v8";
@@ -50,26 +77,26 @@
interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
};
-&mac {
+&mac_sw {
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
<&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
<&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
- dual_emac;
+ status = "okay";
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <&dp83867_0>;
phy-mode = "rgmii-id";
- dual_emac_res_vlan = <1>;
+ ti,dual-emac-pvid = <1>;
};
-&cpsw_emac1 {
+&cpsw_port2 {
phy-handle = <&dp83867_1>;
phy-mode = "rgmii-id";
- dual_emac_res_vlan = <2>;
+ ti,dual-emac-pvid = <2>;
};
-&davinci_mdio {
+&davinci_mdio_sw {
dp83867_0: ethernet-phy@2 {
reg = <2>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -113,3 +140,18 @@
pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
vmmc-supply = <&evm_1v8_sw>;
};
+
+&ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_cma_pool>;
+};
+
+&ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_cma_pool>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_cma_pool>;
+};
diff --git a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
index 5ff9c43..7b433f5 100644
--- a/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-tps65917.dtsi
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
+ * https://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
*/
&tps65917 {
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 9adb775..5f62f92 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra72-evm-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
@@ -12,6 +12,33 @@
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipu2_memory_region: ipu2-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_memory_region: dsp1-memory@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_memory_region: ipu1-memory@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
evm_1v8_sw: fixedregulator-evm_1v8 {
compatible = "regulator-fixed";
regulator-name = "evm_1v8";
@@ -42,17 +69,22 @@
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
};
-&mac {
- slaves = <1>;
+&mac_sw {
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
+ status = "okay";
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <ðphy0>;
phy-mode = "rgmii";
+ ti,dual-emac-pvid = <1>;
};
-&davinci_mdio {
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&davinci_mdio_sw {
ethphy0: ethernet-phy@3 {
reg = <3>;
};
@@ -78,3 +110,18 @@
pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
vmmc-supply = <&evm_1v8_sw>;
};
+
+&ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_memory_region>;
+};
+
+&ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_memory_region>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_memory_region>;
+};
diff --git a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
index edad87c..a9dce91 100644
--- a/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
+++ b/arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi
@@ -1,7 +1,7 @@
/*
* MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index f576270..9061726 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on "omap4.dtsi"
*/
@@ -10,6 +10,12 @@
/ {
compatible = "ti,dra722", "ti,dra72", "ti,dra7";
+ aliases {
+ rproc0 = &ipu1;
+ rproc1 = &ipu2;
+ rproc2 = &dsp1;
+ };
+
pmu {
compatible = "arm,cortex-a15-pmu";
interrupt-parent = <&wakeupgen>;
@@ -17,10 +23,52 @@
};
};
+&l4_per2 {
+ target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5b000 0x4>,
+ <0x5b010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5b000 0x1000>;
+
+ cal: cal@0 {
+ compatible = "ti,dra72-cal";
+ reg = <0x0000 0x400>,
+ <0x0800 0x40>,
+ <0x0900 0x40>;
+ reg-names = "cal_top",
+ "cal_rx_core0",
+ "cal_rx_core1";
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ ti,camerrx-control = <&scm_conf 0xE94>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi2_0: port@0 {
+ reg = <0>;
+ };
+ csi2_1: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
+};
+
&dss {
- reg = <0x58000000 0x80>,
- <0x58004054 0x4>,
- <0x58004300 0x20>;
+ reg = <0 0x80>,
+ <0x4054 0x4>,
+ <0x4300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1";
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
@@ -29,12 +77,12 @@
};
&mailbox5 {
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
@@ -42,7 +90,7 @@
};
&mailbox6 {
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
@@ -60,7 +108,3 @@
&pcie2_rc {
compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};
-
-&usb4_tm {
- status = "disabled";
-};
diff --git a/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi
new file mode 100644
index 0000000..3256631
--- /dev/null
+++ b/arch/arm/boot/dts/dra74-ipu-dsp-common.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common IPU and DSP data for TI DRA74x/DRA76x/AM572x/AM574x platforms
+ */
+
+#include "dra7-ipu-dsp-common.dtsi"
+
+&mailbox6 {
+ mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
+ status = "okay";
+ };
+};
+
+&dsp2 {
+ mboxes = <&mailbox6 &mbox_dsp2_ipc3x>;
+ ti,timers = <&timer6>;
+ ti,watchdog-timers = <&timer13>;
+};
diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
index 214b9e6..e86da7a 100644
--- a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
+++ b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
@@ -1,7 +1,7 @@
/*
* MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.
*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index d1b5b76..cfb39dd 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on "omap4.dtsi"
*/
@@ -29,6 +29,13 @@
};
};
+ aliases {
+ rproc0 = &ipu1;
+ rproc1 = &ipu2;
+ rproc2 = &dsp1;
+ rproc3 = &dsp2;
+ };
+
pmu {
compatible = "arm,cortex-a15-pmu";
interrupt-parent = <&wakeupgen>;
@@ -42,48 +49,78 @@
reg = <0x41500000 0x100>;
};
- omap_dwc3_4: omap_dwc3_4@48940000 {
- compatible = "ti,dwc3";
- ti,hwmods = "usb_otg_ss4";
- reg = <0x48940000 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
+
+ target-module@41501000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x41501000 0x4>,
+ <0x41501010 0x4>,
+ <0x41501014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp2 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x41501000 0x1000>;
#size-cells = <1>;
- utmi-mode = <2>;
- ranges;
- status = "disabled";
- usb4: usb@48950000 {
- compatible = "snps,dwc3";
- reg = <0x48950000 0x17000>;
- interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- maximum-speed = "high-speed";
- dr_mode = "otg";
+ #address-cells = <1>;
+
+ mmu0_dsp2: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp2_system 0x0>;
};
};
- mmu0_dsp2: mmu@41501000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x41501000 0x100>;
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu0_dsp2";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp2_system 0x0>;
- status = "disabled";
+ target-module@41502000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x41502000 0x4>,
+ <0x41502010 0x4>,
+ <0x41502014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+
+ clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_dsp2 1>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x41502000 0x1000>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu1_dsp2: mmu@0 {
+ compatible = "ti,dra7-dsp-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,syscon-mmuconfig = <&dsp2_system 0x1>;
+ };
};
- mmu1_dsp2: mmu@41502000 {
- compatible = "ti,dra7-dsp-iommu";
- reg = <0x41502000 0x100>;
- interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu1_dsp2";
- #iommu-cells = <0>;
- ti,syscon-mmuconfig = <&dsp2_system 0x1>;
+ dsp2: dsp@41000000 {
+ compatible = "ti,dra7-dsp";
+ reg = <0x41000000 0x48000>,
+ <0x41600000 0x8000>,
+ <0x41700000 0x8000>;
+ reg-names = "l2ram", "l1pram", "l1dram";
+ ti,bootreg = <&scm_conf 0x560 10>;
+ iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
status = "disabled";
+ resets = <&prm_dsp2 0>;
+ clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
+ firmware-name = "dra7-dsp2-fw.xe66";
};
};
};
@@ -93,11 +130,11 @@
};
&dss {
- reg = <0x58000000 0x80>,
- <0x58004054 0x4>,
- <0x58004300 0x20>,
- <0x58009054 0x4>,
- <0x58009300 0x20>;
+ reg = <0 0x80>,
+ <0x4054 0x4>,
+ <0x4300 0x20>,
+ <0x9054 0x4>,
+ <0x9300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2";
@@ -108,12 +145,12 @@
};
&mailbox5 {
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
@@ -121,12 +158,12 @@
};
&mailbox6 {
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
@@ -144,3 +181,52 @@
&pcie2_rc {
compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
};
+
+&l4_per3 {
+ segment@0 {
+ usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x140000 0x4>,
+ <0x140010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x140000 0x20000>;
+
+ omap_dwc3_4: omap_dwc3_4@0 {
+ compatible = "ti,dwc3";
+ reg = <0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ status = "disabled";
+ usb4: usb@10000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000 0x17000>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index 1fb6f13..9bd01ae 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -13,11 +13,52 @@
model = "TI DRA762 EVM";
compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
+ aliases {
+ display0 = &hdmi0;
+
+ sound0 = &sound0;
+ sound1 = &hdmi;
+ };
+
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipu2_cma_pool: ipu2_cma@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x95800000 0x0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp1_cma_pool: dsp1_cma@99000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x99000000 0x0 0x4000000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu1_cma_pool: ipu1_cma@9d000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9d000000 0x0 0x2000000>;
+ reusable;
+ status = "okay";
+ };
+
+ dsp2_cma_pool: dsp2_cma@9f000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x9f000000 0x0 0x800000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
vsys_12v0: fixedregulator-vsys12v0 {
/* main supply */
compatible = "regulator-fixed";
@@ -116,6 +157,54 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
+
+ clk_ov5640_fixed: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+ tpd12s015: encoder {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */
+ <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */
+ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpd12s015_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpd12s015_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
};
&i2c1 {
@@ -317,6 +406,27 @@
};
};
+&i2c5 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ ov5640@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2_phy0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
&cpu0 {
vdd-supply = <&buck10_reg>;
};
@@ -365,25 +475,23 @@
status = "disabled";
};
-&mac {
+&mac_sw {
status = "okay";
-
- dual_emac;
};
-&cpsw_emac0 {
+&cpsw_port1 {
phy-handle = <&dp83867_0>;
phy-mode = "rgmii-id";
- dual_emac_res_vlan = <1>;
+ ti,dual-emac-pvid = <1>;
};
-&cpsw_emac1 {
+&cpsw_port2 {
phy-handle = <&dp83867_1>;
phy-mode = "rgmii-id";
- dual_emac_res_vlan = <2>;
+ ti,dual-emac-pvid = <2>;
};
-&davinci_mdio {
+&davinci_mdio_sw {
dp83867_0: ethernet-phy@2 {
reg = <2>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
@@ -411,6 +519,23 @@
phy-supply = <&ldo3_reg>;
};
+&dss {
+ status = "okay";
+ vdda_video-supply = <&ldo5_reg>;
+};
+
+&hdmi {
+ status = "okay";
+
+ vdda-supply = <&ldo1_reg>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&tpd12s015_in>;
+ };
+ };
+};
+
&qspi {
spi-max-frequency = <96000000>;
m25p80@0 {
@@ -447,3 +572,31 @@
max-bitrate = <5000000>;
};
};
+
+&csi2_0 {
+ csi2_phy0: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+};
+
+&ipu2 {
+ status = "okay";
+ memory-region = <&ipu2_cma_pool>;
+};
+
+&ipu1 {
+ status = "okay";
+ memory-region = <&ipu1_cma_pool>;
+};
+
+&dsp1 {
+ status = "okay";
+ memory-region = <&dsp1_cma_pool>;
+};
+
+&dsp2 {
+ status = "okay";
+ memory-region = <&dsp2_cma_pool>;
+};
diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
index 859e438..2f32615 100644
--- a/arch/arm/boot/dts/dra76x.dtsi
+++ b/arch/arm/boot/dts/dra76x.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "dra74x.dtsi"
@@ -41,6 +41,48 @@
};
+&l4_per3 {
+ target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x1b0000 0x4>,
+ <0x1b0010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1b0000 0x10000>;
+
+ cal: cal@0 {
+ compatible = "ti,dra76-cal";
+ reg = <0x0000 0x400>,
+ <0x0800 0x40>,
+ <0x0900 0x40>;
+ reg-names = "cal_top",
+ "cal_rx_core0",
+ "cal_rx_core1";
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ ti,camerrx-control = <&scm_conf 0x6dc>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi2_0: port@0 {
+ reg = <0>;
+ };
+ csi2_1: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
+};
+
/* MCAN interrupts are hard-wired to irqs 67, 68 */
&crossbar_mpu {
ti,irqs-skip = <10 67 68 133 139 140>;
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d7d98d2..dc0a93b 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1583,10 +1583,10 @@
rtc_cm: rtc-cm@700 {
compatible = "ti,omap4-cm";
- reg = <0x700 0x100>;
+ reg = <0x700 0x60>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x700 0x100>;
+ ranges = <0 0x700 0x60>;
rtc_clkctrl: rtc-clkctrl@20 {
compatible = "ti,clkctrl";
@@ -1595,6 +1595,20 @@
};
};
+ vpe_cm: vpe-cm@760 {
+ compatible = "ti,omap4-cm";
+ reg = <0x760 0xc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x760 0xc>;
+
+ vpe_clkctrl: vpe-clkctrl@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
};
&cm_core {
@@ -1712,6 +1726,20 @@
};
};
+ cam_cm: cam-cm@1000 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x100>;
+
+ cam_clkctrl: cam-clkctrl@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x2c>;
+ #clock-cells = <2>;
+ };
+ };
+
dss_cm: dss-cm@1100 {
compatible = "ti,omap4-cm";
reg = <0x1100 0x100>;
@@ -1726,6 +1754,20 @@
};
};
+ gpu_cm: gpu-cm@1200 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1200 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1200 0x100>;
+
+ gpu_clkctrl: gpu-clkctrl@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
l3init_cm: l3init-cm@1300 {
compatible = "ti,omap4-cm";
reg = <0x1300 0x100>;
diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi
new file mode 100644
index 0000000..3af1ab4
--- /dev/null
+++ b/arch/arm/boot/dts/e60k02.dtsi
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Andreas Kemnade
+ * based on works
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * and
+ * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd
+ *
+ * Netronix E60K02 board common.
+ * This board is equipped with different SoCs and
+ * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and
+ * the Tolino Shine 3 (with i.MX6SL)
+ */
+#include <dt-bindings/input/input.h>
+
+/ {
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power";
+ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ cover {
+ label = "Cover";
+ gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ wakeup-source;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ on {
+ label = "e60k02:white:on";
+ gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ compatible = "regulator-fixed";
+ regulator-name = "SD3_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <20>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+
+&i2c1 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ lm3630a: backlight@36 {
+ reg = <0x36>;
+ compatible = "ti,lm3630a";
+ enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ led-sources = <0>;
+ label = "backlight_warm";
+ default-brightness = <0>;
+ max-brightness = <255>;
+ };
+
+ led@1 {
+ reg = <1>;
+ led-sources = <1>;
+ label = "backlight_cold";
+ default-brightness = <0>;
+ max-brightness = <255>;
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ /* TODO: CYTTSP5 touch controller at 0x24 */
+
+ /* TODO: TPS65185 PMIC for E Ink at 0x68 */
+
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ ricoh619: pmic@32 {
+ compatible = "ricoh,rc5t619";
+ reg = <0x32>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ system-power-controller;
+
+ regulators {
+ dcdc1_reg: DCDC1 {
+ regulator-name = "DCDC1";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <900000>;
+ regulator-suspend-min-microvolt = <900000>;
+ };
+ };
+
+ /* Core3_3V3 */
+ dcdc2_reg: DCDC2 {
+ regulator-name = "DCDC2";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <3300000>;
+ regulator-suspend-min-microvolt = <3300000>;
+ };
+ };
+
+ dcdc3_reg: DCDC3 {
+ regulator-name = "DCDC3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1140000>;
+ regulator-suspend-min-microvolt = <1140000>;
+ };
+ };
+
+ /* Core4_1V2 */
+ dcdc4_reg: DCDC4 {
+ regulator-name = "DCDC4";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1140000>;
+ regulator-suspend-min-microvolt = <1140000>;
+ };
+ };
+
+ /* Core4_1V8 */
+ dcdc5_reg: DCDC5 {
+ regulator-name = "DCDC5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1700000>;
+ regulator-suspend-min-microvolt = <1700000>;
+ };
+ };
+
+ /* IR_3V3 */
+ ldo1_reg: LDO1 {
+ regulator-name = "LDO1";
+ regulator-boot-on;
+ };
+
+ /* Core1_3V3 */
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <3000000>;
+ regulator-suspend-min-microvolt = <3000000>;
+ };
+ };
+
+ /* Core5_1V2 */
+ ldo3_reg: LDO3 {
+ regulator-name = "LDO3";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-boot-on;
+ };
+
+ /* SPD_3V3 */
+ ldo5_reg: LDO5 {
+ regulator-name = "LDO5";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* DDR_0V6 */
+ ldo6_reg: LDO6 {
+ regulator-name = "LDO6";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* VDD_PWM */
+ ldo7_reg: LDO7 {
+ regulator-name = "LDO7";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* ldo_1v8 */
+ ldo8_reg: LDO8 {
+ regulator-name = "LDO8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "LDO9";
+ regulator-boot-on;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "LDO10";
+ regulator-boot-on;
+ };
+
+ ldortc1_reg: LDORTC1 {
+ regulator-name = "LDORTC1";
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&snvs_rtc {
+ /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */
+ status = "disabled";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usdhc2 {
+ non-removable;
+ status = "okay";
+};
+
+&usdhc3 {
+ vmmc-supply = <®_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ cap-power-off-card;
+ non-removable;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ disable-over-current;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 5651ae6..f6eb715 100644
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -13,7 +13,6 @@
compatible = "calxeda,ecx-2000";
#address-cells = <2>;
#size-cells = <2>;
- clock-ranges;
cpus {
#address-cells = <1>;
@@ -83,8 +82,7 @@
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
- #size-cells = <0>;
- #address-cells = <1>;
+ #address-cells = <0>;
interrupt-controller;
interrupts = <1 9 0xf04>;
reg = <0xfff11000 0x1000>,
@@ -95,7 +93,7 @@
pmu {
compatible = "arm,cortex-a9-pmu";
- interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
+ interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
};
};
};
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index 66ee1d3..57a028a 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -27,10 +27,11 @@
reg = <0xffe08000 0x10000>;
interrupts = <0 83 4>;
dma-coherent;
- calxeda,port-phys = <&combophy5 0 &combophy0 0
- &combophy0 1 &combophy0 2
- &combophy0 3>;
- calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
+ calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
+ <&combophy0 1>, <&combophy0 2>,
+ <&combophy0 3>;
+ calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
+ <&gpioh 7 1>;
calxeda,led-order = <4 0 1 2 3>;
};
@@ -114,8 +115,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xfff36000 0x1000>;
interrupts = <0 20 4>;
- clocks = <&pclk>;
- clock-names = "apb_pclk";
+ clocks = <&pclk>, <&pclk>;
+ clock-names = "uartclk", "apb_pclk";
};
smic@fff3a000 {
@@ -202,14 +203,14 @@
ethernet@fff50000 {
compatible = "calxeda,hb-xgmac";
reg = <0xfff50000 0x1000>;
- interrupts = <0 77 4 0 78 4 0 79 4>;
+ interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
dma-coherent;
};
ethernet@fff51000 {
compatible = "calxeda,hb-xgmac";
reg = <0xfff51000 0x1000>;
- interrupts = <0 80 4 0 81 4 0 82 4>;
+ interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
dma-coherent;
};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index 67d8601..ecfaa0b 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -195,7 +195,7 @@
clock-names = "sclk";
};
- pfc: pin-controller@e0140200 {
+ pfc: pinctrl@e0140200 {
compatible = "renesas,pfc-emev2";
reg = <0xe0140200 0x100>;
};
@@ -212,6 +212,7 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
gpio1: gpio@e0050080 {
compatible = "renesas,em-gio";
reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
@@ -224,6 +225,7 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
gpio2: gpio@e0050100 {
compatible = "renesas,em-gio";
reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
@@ -236,6 +238,7 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
gpio3: gpio@e0050180 {
compatible = "renesas,em-gio";
reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
@@ -248,6 +251,7 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
gpio4: gpio@e0050200 {
compatible = "renesas,em-gio";
reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
index 052a52f..ad7a085 100644
--- a/arch/arm/boot/dts/ethernut5.dts
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -15,7 +15,7 @@
bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x08000000>;
};
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 69d134d..ad525f2 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -23,7 +23,7 @@
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x1ff00000>;
+ reg = <0x40000000 0x1f800000>;
};
firmware@205f000 {
@@ -55,6 +55,10 @@
assigned-clock-rates = <6000000>;
};
+&cmu {
+ clocks = <&xusbxti>;
+};
+
&cpu0 {
cpu0-supply = <&buck2_reg>;
};
@@ -352,6 +356,14 @@
};
&pinctrl_1 {
+ bten: bten {
+ samsung,pins ="gpx1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
wlanen: wlanen {
samsung,pins = "gpx2-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
@@ -364,6 +376,22 @@
samsung,pins = "gpx3-5";
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
};
+
+ bthostwake: bthostwake {
+ samsung,pins = "gpx3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ btwake: btwake {
+ samsung,pins = "gpx3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT0>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_DOWN>;
+ };
};
&rtc {
@@ -372,6 +400,23 @@
status = "okay";
};
+&serial_0 {
+ assigned-clocks = <&cmu CLK_SCLK_UART0>;
+ assigned-clock-rates = <100000000>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bten &btwake &bthostwake>;
+ max-speed = <3000000>;
+ shutdown-gpios = <&gpx1 7 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpx3 6 GPIO_ACTIVE_HIGH>;
+ clocks = <&s2mps14_osc S2MPS11_CLK_BT>;
+ };
+};
+
&tmu {
status = "okay";
};
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
index a23a874..7e99e58 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -26,7 +26,7 @@
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x1ff00000>;
+ reg = <0x40000000 0x1ff00000>;
};
firmware@205f000 {
@@ -57,7 +57,8 @@
i2c_max77836: i2c-gpio-0 {
compatible = "i2c-gpio";
- gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
@@ -163,6 +164,10 @@
status = "okay";
};
+&cmu {
+ clocks = <&xusbxti>;
+};
+
&cpu0 {
cpu0-supply = <&buck2_reg>;
};
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 468932f..f9e3b13 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -30,7 +30,7 @@
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x1ff00000>;
+ reg = <0x40000000 0x1ff00000>;
};
firmware@205f000 {
@@ -50,9 +50,15 @@
};
};
+ wlan_pwrseq: mshc1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>;
+ };
+
i2c_max77836: i2c-gpio-0 {
compatible = "i2c-gpio";
- gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
@@ -199,6 +205,10 @@
status = "okay";
};
+&cmu {
+ clocks = <&xusbxti>;
+};
+
&cpu0 {
cpu0-supply = <&buck2_reg>;
};
@@ -605,8 +615,6 @@
};
&mshc_0 {
- #address-cells = <1>;
- #size-cells = <0>;
broken-cd;
non-removable;
cap-mmc-highspeed;
@@ -625,10 +633,48 @@
status = "okay";
};
+&mshc_1 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ non-removable;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ samsung,dw-mshc-ciu-div = <1>;
+ samsung,dw-mshc-sdr-timing = <0 1>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>;
+ bus-width = <4>;
+
+ mmc-pwrseq = <&wlan_pwrseq>;
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4334-fmac";
+ reg = <1>;
+
+ interrupt-parent = <&gpx1>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};
+
&serial_0 {
assigned-clocks = <&cmu CLK_SCLK_UART0>;
assigned-clock-rates = <100000000>;
status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ max-speed = <3000000>;
+ shutdown-gpios = <&gpe0 0 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+ clocks = <&s2mps14_osc S2MPS11_CLK_BT>;
+ };
};
&serial_1 {
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 7848184..a1e93fb 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -97,33 +97,25 @@
};
};
- fixed-rate-clocks {
- #address-cells = <1>;
- #size-cells = <0>;
+ xusbxti: clock-0 {
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ clock-output-names = "xusbxti";
+ };
- xusbxti: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- clock-frequency = <0>;
- #clock-cells = <0>;
- clock-output-names = "xusbxti";
- };
+ xxti: clock-1 {
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ clock-output-names = "xxti";
+ };
- xxti: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- clock-frequency = <0>;
- #clock-cells = <0>;
- clock-output-names = "xxti";
- };
-
- xtcxo: clock@2 {
- compatible = "fixed-clock";
- reg = <2>;
- clock-frequency = <0>;
- #clock-cells = <0>;
- clock-output-names = "xtcxo";
- };
+ xtcxo: clock-2 {
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ clock-output-names = "xtcxo";
};
pmu {
@@ -138,19 +130,19 @@
#size-cells = <1>;
ranges;
- sysram@2020000 {
+ sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x40000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@3f000 {
+ smp-sram@3f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x3f000 0x1000>;
};
@@ -265,7 +257,7 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
- mct@10050000 {
+ timer@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
@@ -314,8 +306,7 @@
sysmmu_jpeg: sysmmu@11a60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11a60000 0x1000>;
- interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
power-domains = <&pd_cam>;
@@ -355,8 +346,7 @@
sysmmu_fimd0: sysmmu@11e20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11e20000 0x1000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
power-domains = <&pd_lcd0>;
@@ -364,7 +354,7 @@
};
hsotg: hsotg@12480000 {
- compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
+ compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBOTG>;
@@ -420,33 +410,26 @@
status = "disabled";
};
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ pdma0: pdma@12680000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12680000 0x1000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
- pdma0: pdma@12680000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12680000 0x1000>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu CLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- pdma1: pdma@12690000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12690000 0x1000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cmu CLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
+ pdma1: pdma@12690000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12690000 0x1000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
};
adc: adc@126c0000 {
@@ -507,8 +490,7 @@
sysmmu_mfc: sysmmu@13620000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13620000 0x1000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sysmmu", "master";
clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
power-domains = <&pd_mfc>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 433f109..a1e5444 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -111,28 +111,28 @@
syscon = <&pmu_system_controller>;
};
- pd_mfc: mfc-power-domain@10023c40 {
+ pd_mfc: power-domain@10023c40 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C40 0x20>;
#power-domain-cells = <0>;
label = "MFC";
};
- pd_g3d: g3d-power-domain@10023c60 {
+ pd_g3d: power-domain@10023c60 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C60 0x20>;
#power-domain-cells = <0>;
label = "G3D";
};
- pd_lcd0: lcd0-power-domain@10023c80 {
+ pd_lcd0: power-domain@10023c80 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C80 0x20>;
#power-domain-cells = <0>;
label = "LCD0";
};
- pd_tv: tv-power-domain@10023c20 {
+ pd_tv: power-domain@10023c20 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C20 0x20>;
#power-domain-cells = <0>;
@@ -140,21 +140,21 @@
label = "TV";
};
- pd_cam: cam-power-domain@10023c00 {
+ pd_cam: power-domain@10023c00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x20>;
#power-domain-cells = <0>;
label = "CAM";
};
- pd_gps: gps-power-domain@10023ce0 {
+ pd_gps: power-domain@10023ce0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CE0 0x20>;
#power-domain-cells = <0>;
label = "GPS";
};
- pd_gps_alive: gps-alive-power-domain@10023d00 {
+ pd_gps_alive: power-domain@10023d00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023D00 0x20>;
#power-domain-cells = <0>;
@@ -669,45 +669,37 @@
status = "disabled";
};
- amba: amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
+ pdma0: pdma@12680000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12680000 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
- pdma0: pdma@12680000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12680000 0x1000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
+ pdma1: pdma@12690000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12690000 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
- pdma1: pdma@12690000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12690000 0x1000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- mdma1: mdma@12850000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12850000 0x1000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_MDMA>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
- };
+ mdma1: mdma@12850000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12850000 0x1000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_MDMA>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <1>;
};
fimd: fimd@11c00000 {
diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts
new file mode 100644
index 0000000..ecc9d4d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-i9100.dts
@@ -0,0 +1,788 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2020 Stenkin Evgeniy <stenkinevgeniy@gmail.com>
+ * Copyright (c) 2020 Paul Cercueil <paul@crapouillou.net>
+ */
+
+/dts-v1/;
+#include "exynos4210.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+ model = "Samsung Galaxy S2 (GT-I9100)";
+ compatible = "samsung,i9100", "samsung,exynos4210", "samsung,exynos4";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ vemmc_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ tsp_reg: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "TSP_FIXED_VOLTAGES";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ cam_af_28v_reg: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "8M_AF_2.8V_EN";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ cam_io_en_reg: regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "CAM_IO_EN";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ cam_io_12v_reg: regulator-4 {
+ compatible = "regulator-fixed";
+ regulator-name = "8M_1.2V_EN";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vt_core_15v_reg: regulator-5 {
+ compatible = "regulator-fixed";
+ regulator-name = "VT_CORE_1.5V";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ vol-down {
+ gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ label = "volume down";
+ debounce-interval = <10>;
+ };
+
+ vol-up {
+ gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ label = "volume up";
+ debounce-interval = <10>;
+ };
+
+ power {
+ gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ label = "power";
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+
+ ok {
+ gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_OK>;
+ label = "ok";
+ debounce-interval = <10>;
+ };
+ };
+
+ wlan_pwrseq: sdhci3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ i2c_max17042_fuel: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sda-gpios = <&gpy4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpy4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>;
+
+ battery@36 {
+ compatible = "maxim,max17042";
+
+ interrupt-parent = <&gpx2>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&max17042_fuel_irq>;
+ pinctrl-names = "default";
+
+ reg = <0x36>;
+ maxim,over-heat-temp = <700>;
+ maxim,over-volt = <4500>;
+ };
+ };
+
+ spi-3 {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ num-chipselects = <1>;
+ cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>;
+ sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>;
+
+ lcd@0 {
+ compatible = "samsung,ld9040";
+ reg = <0>;
+
+ spi-max-frequency = <1200000>;
+
+ vdd3-supply = <&vmipi_reg>;
+ vci-supply = <&vcclcd_reg>;
+
+ reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>;
+ power-on-delay = <10>;
+ reset-delay = <10>;
+
+ panel-width-mm = <90>;
+ panel-height-mm = <154>;
+
+ display-timings {
+ timing {
+ clock-frequency = <23492370>;
+ hactive = <480>;
+ vactive = <800>;
+ hback-porch = <16>;
+ hfront-porch = <16>;
+ vback-porch = <2>;
+ vfront-porch = <28>;
+ hsync-len = <2>;
+ vsync-len = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <0>;
+ pixelclk-active = <0>;
+ };
+ };
+
+ port {
+ lcd_ep: endpoint {
+ remote-endpoint = <&fimd_dpi_ep>;
+ };
+ };
+ };
+ };
+
+ fixed-rate-clocks {
+ xxti {
+ compatible = "samsung,clock-xxti";
+ clock-frequency = <0>;
+ };
+
+ xusbxti {
+ compatible = "samsung,clock-xusbxti";
+ clock-frequency = <24000000>;
+ };
+
+ pmic_ap_clk: pmic-ap-clk {
+ /* Workaround for missing clock on max8997 PMIC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
+
+&camera {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu0-supply = <&varm_breg>;
+};
+
+&cpu_thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz */
+ cooling-device = <&cpu0 2 2>;
+ };
+ map1 {
+ /* Corresponds to 200MHz */
+ cooling-device = <&cpu0 4 4>;
+ };
+ };
+};
+
+&ehci {
+ status = "okay";
+
+ phys = <&exynos_usbphy 1>;
+ phy-names = "host";
+};
+
+&exynos_usbphy {
+ status = "okay";
+
+ vbus-supply = <&safe1_sreg>;
+};
+
+&fimc_0 {
+ status = "okay";
+
+ assigned-clocks = <&clock CLK_MOUT_FIMC0>, <&clock CLK_SCLK_FIMC0>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_1 {
+ status = "okay";
+
+ assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_2 {
+ status = "okay";
+
+ assigned-clocks = <&clock CLK_MOUT_FIMC2>, <&clock CLK_SCLK_FIMC2>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_3 {
+ status = "okay";
+
+ assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>;
+ assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+ assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimd {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ samsung,invert-vden;
+ samsung,invert-vclk;
+
+ pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
+ pinctrl-names = "default";
+
+ port@3 {
+ reg = <3>;
+
+ fimd_dpi_ep: endpoint {
+ remote-endpoint = <&lcd_ep>;
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+
+ mali-supply = <&vg3d_breg>;
+};
+
+&hsotg {
+ status = "okay";
+
+ dr_mode = "otg";
+ vusb_d-supply = <&vusb_reg>;
+ vusb_a-supply = <&vusbdac_reg>;
+};
+
+&i2c_3 {
+ status = "okay";
+
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+
+ pinctrl-0 = <&i2c3_bus>;
+ pinctrl-names = "default";
+
+ mxt224-touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+
+ interrupt-parent = <&gpx0>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&i2c_5 {
+ status = "okay";
+
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+
+ pinctrl-0 = <&i2c5_bus>;
+ pinctrl-names = "default";
+
+ max8997_pmic@66 {
+ compatible = "maxim,max8997-pmic";
+ reg = <0x66>;
+
+ interrupts-extended = <&gpx0 7 IRQ_TYPE_NONE>,
+ <&gpx2 3 IRQ_TYPE_EDGE_FALLING>;
+
+ max8997,pmic-buck1-uses-gpio-dvs;
+ max8997,pmic-buck2-uses-gpio-dvs;
+ max8997,pmic-buck5-uses-gpio-dvs;
+
+ max8997,pmic-ignore-gpiodvs-side-effect;
+ max8997,pmic-buck125-default-dvs-idx = <0>;
+
+ max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>,
+ <&gpx0 6 GPIO_ACTIVE_HIGH>,
+ <&gpl0 0 GPIO_ACTIVE_HIGH>;
+
+ max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
+ <1250000>, <1200000>,
+ <1150000>, <1100000>,
+ <1000000>, <950000>;
+
+ max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>,
+ <950000>, <900000>,
+ <1100000>, <1000000>,
+ <950000>, <900000>;
+
+ max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
+ <1200000>, <1200000>,
+ <1200000>, <1200000>,
+ <1200000>, <1200000>;
+
+ pinctrl-0 = <&max8997_irq>, <&otg_gp>, <&usb_sel>;
+ pinctrl-names = "default";
+
+ regulators {
+ vadc_reg: LDO1 {
+ regulator-name = "VADC_3.3V_C210";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+
+ };
+ valive_reg: LDO2 {
+ regulator-name = "VALIVE_1.1V_C210";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+
+ };
+
+ vusb_reg: LDO3 {
+ regulator-name = "VUSB_1.1V_C210";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ vmipi_reg: LDO4 {
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vhsic_reg: LDO5 {
+ regulator-name = "VHSIC_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vpda_reg: LDO6 {
+ regulator-name = "VCC_1.8V_PDA";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcam_reg: LDO7 {
+ regulator-name = "CAM_ISP_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vusbdac_reg: LDO8 {
+ regulator-name = "VUSB+VDAC_3.3V_C210";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vccpda_reg: LDO9 {
+ regulator-name = "VCC_2.8V_PDA";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ vtouch_reg: LDO11 {
+ regulator-name = "TOUCH_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ vpll_reg: LDO10 {
+ regulator-name = "VPLL_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ vtcam_reg: LDO12 {
+ regulator-name = "VT_CAM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcclcd_reg: LDO13 {
+ regulator-name = "VCC_3.0V_LCD";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vmotor_reg: LDO14 {
+ regulator-name = "VCC_2.8V_MOTOR";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vled_reg: LDO15 {
+ regulator-name = "LED_A_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ camsensor_reg: LDO16 {
+ regulator-name = "CAM_SENSOR_IO_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vtf_reg: LDO17 {
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ vtouchled_reg: LDO18 {
+ regulator-name = "TOUCH_LED_3.3V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddq_reg: LDO21 {
+ regulator-name = "VDDQ_M1M2_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ varm_breg: BUCK1 {
+ regulator-name = "VARM_1.2V_C210";
+ regulator-min-microvolt = <65000>;
+ regulator-max-microvolt = <2225000>;
+ regulator-always-on;
+ };
+
+ vint_breg: BUCK2 {
+ regulator-name = "VINT_1.1V_C210";
+ regulator-min-microvolt = <65000>;
+ regulator-max-microvolt = <2225000>;
+ regulator-always-on;
+ };
+
+ vg3d_breg: BUCK3 {
+ regulator-name = "G3D_1.1V";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-microvolt-offset = <50000>;
+ regulator-always-on;
+ };
+
+ camisp_breg: BUCK4 {
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vmem_breg: BUCK5 {
+ regulator-name = "VMEM_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vccsub_breg: BUCK7 {
+ regulator-name = "VCC_SUB_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ };
+
+ safe1_sreg: ESAFEOUT1 {
+ regulator-name = "SAFEOUT1";
+ };
+
+ safe2_sreg: ESAFEOUT2 {
+ regulator-name = "SAFEOUT2";
+ regulator-boot-on;
+ };
+
+ charger_reg: CHARGER {
+ regulator-name = "CHARGER";
+ regulator-min-microamp = <60000>;
+ regulator-max-microamp = <2580000>;
+ regulator-always-on;
+ };
+
+ chargercv_reg: CHARGER_CV {
+ regulator-name = "CHARGER_CV";
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <4100000>;
+ regulator-always-on;
+ };
+
+ EN32KHZ_AP {
+ regulator-name = "EN32KHZ_AP";
+ regulator-always-on;
+ };
+
+ EN32KHZ_CP {
+ regulator-name = "EN32KHZ_CP";
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c_7 {
+ status = "okay";
+
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <400000>;
+
+ pinctrl-0 = <&i2c7_bus>;
+ pinctrl-names = "default";
+
+ ak8975@c {
+ compatible = "asahi-kasei,ak8975";
+ reg = <0x0c>;
+
+ gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&pinctrl_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep0>;
+
+ sleep0: sleep-states {
+ gpa0-0 {
+ samsung,pins = "gpa0-0";
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ gpa0-1 {
+ samsung,pins = "gpa0-1";
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT0>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ gpa0-2 {
+ samsung,pins = "gpa0-2";
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ gpa0-3 {
+ samsung,pins = "gpa0-3";
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
+ };
+ };
+};
+
+&pinctrl_1 {
+ mhl_int: mhl-int {
+ samsung,pins = "gpf3-5";
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ i2c_mhl_bus: i2c-mhl-bus {
+ samsung,pins = "gpf0-4", "gpf0-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ usb_sel: usb-sel {
+ samsung,pins = "gpl0-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-val = <0>;
+ };
+
+ bt_en: bt-en {
+ samsung,pins = "gpl0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-val = <0>;
+ };
+
+ bt_res: bt-res {
+ samsung,pins = "gpl1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+ samsung,pin-val = <0>;
+ };
+
+ otg_gp: otg-gp {
+ samsung,pins = "gpx3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-val = <0>;
+ };
+
+ mag_mhl_gpio: mag-mhl {
+ samsung,pins = "gpd0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ max8997_irq: max8997-irq {
+ samsung,pins = "gpx0-7";
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ max17042_fuel_irq: max17042-fuel-irq {
+ samsung,pins = "gpx2-3";
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ tsp224_irq: tsp224-irq {
+ samsung,pins = "gpx0-4";
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ };
+};
+
+&rtc {
+ status = "okay";
+ clocks = <&clock CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
+};
+
+&sdhci_0 {
+ status = "okay";
+
+ bus-width = <8>;
+ non-removable;
+ vmmc-supply = <&vemmc_reg>;
+
+ pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_bus8>;
+ pinctrl-names = "default";
+};
+
+&sdhci_2 {
+ status = "okay";
+
+ bus-width = <4>;
+ cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&vtf_reg>;
+
+ pinctrl-0 = <&sd2_clk>, <&sd2_cmd>, <&sd2_bus4>;
+ pinctrl-names = "default";
+};
+
+&sdhci_3 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ non-removable;
+ bus-width = <4>;
+ mmc-pwrseq = <&wlan_pwrseq>;
+ vmmc-supply = <&vtf_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>;
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4330-fmac";
+ reg = <1>;
+
+ interrupt-parent = <&gpx2>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&serial_0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en>, <&bt_res>, <&uart0_data>, <&uart0_fctl>;
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+
+ shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpl1 0 GPIO_ACTIVE_LOW>;
+ device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&serial_1 {
+ status = "okay";
+};
+
+&serial_2 {
+ status = "okay";
+};
+
+&serial_3 {
+ status = "okay";
+};
+
+&tmu {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 0d1e1a9..7d2cfba 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -100,6 +100,13 @@
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
+
+ pmic_ap_clk: pmic-ap-clk {
+ /* Workaround for missing clock on max8997 PMIC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
display-timings {
@@ -122,6 +129,19 @@
cpu0-supply = <&buck1_reg>;
};
+&cpu_thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz */
+ cooling-device = <&cpu0 2 2>;
+ };
+ map1 {
+ /* Corresponds to 200MHz */
+ cooling-device = <&cpu0 4 4>;
+ };
+ };
+};
+
&exynos_usbphy {
status = "okay";
};
@@ -251,12 +271,7 @@
};
buck1_reg: BUCK1 {
- /*
- * HACK: The real name is VDD_ARM_1.2V,
- * but exynos-cpufreq does not support
- * DT-based regulator lookup yet.
- */
- regulator-name = "vdd_arm";
+ regulator-name = "VDD_ARM_1.2V";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
@@ -291,6 +306,11 @@
regulator-boot-on;
regulator-always-on;
};
+
+ EN32KHZ_AP {
+ regulator-name = "EN32KHZ_AP";
+ regulator-always-on;
+ };
};
};
};
@@ -336,6 +356,8 @@
&rtc {
status = "okay";
+ clocks = <&clock CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
};
&tmu {
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 77fc11e..c5609af 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -40,6 +40,26 @@
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
+
+ pmic_ap_clk: pmic-ap-clk {
+ /* Workaround for missing clock on PMIC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
+
+&cpu_thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz */
+ cooling-device = <&cpu0 2 2>;
+ };
+ map1 {
+ /* Corresponds to 200MHz */
+ cooling-device = <&cpu0 4 4>;
+ };
};
};
@@ -148,6 +168,11 @@
};
};
+&rtc {
+ clocks = <&clock CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
+};
+
&sdhci_2 {
bus-width = <4>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 7c39dd1..a226bec 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -30,62 +30,58 @@
stdout-path = "serial2:115200n8";
};
- regulators {
- compatible = "simple-bus";
+ vemmc_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vemmc_reg: regulator-0 {
- compatible = "regulator-fixed";
- regulator-name = "VMEM_VDD_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ tsp_reg: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "TSP_FIXED_VOLTAGES";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- tsp_reg: regulator-1 {
- compatible = "regulator-fixed";
- regulator-name = "TSP_FIXED_VOLTAGES";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ cam_af_28v_reg: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "8M_AF_2.8V_EN";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- cam_af_28v_reg: regulator-2 {
- compatible = "regulator-fixed";
- regulator-name = "8M_AF_2.8V_EN";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ cam_io_en_reg: regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "CAM_IO_EN";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- cam_io_en_reg: regulator-3 {
- compatible = "regulator-fixed";
- regulator-name = "CAM_IO_EN";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ cam_io_12v_reg: regulator-4 {
+ compatible = "regulator-fixed";
+ regulator-name = "8M_1.2V_EN";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- cam_io_12v_reg: regulator-4 {
- compatible = "regulator-fixed";
- regulator-name = "8M_1.2V_EN";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vt_core_15v_reg: regulator-5 {
- compatible = "regulator-fixed";
- regulator-name = "VT_CORE_1.5V";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vt_core_15v_reg: regulator-5 {
+ compatible = "regulator-fixed";
+ regulator-name = "VT_CORE_1.5V";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
gpio-keys {
@@ -121,6 +117,11 @@
};
};
+ wlan_pwrseq: sdhci3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>;
+ };
+
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
@@ -131,23 +132,14 @@
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
- };
- thermal-zones {
- cpu_thermal: cpu-thermal {
- cooling-maps {
- map0 {
- /* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 2 2>, <&cpu1 2 2>;
- };
- map1 {
- /* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 4 4>, <&cpu1 4 4>;
- };
- };
+ pmic_ap_clk: pmic-ap-clk {
+ /* Workaround for missing clock on max8997 PMIC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
};
};
-
};
&camera {
@@ -160,6 +152,19 @@
cpu0-supply = <&varm_breg>;
};
+&cpu_thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 2 2>, <&cpu1 2 2>;
+ };
+ map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 4 4>, <&cpu1 4 4>;
+ };
+ };
+};
+
&dsi_0 {
vddcore-supply = <&vusb_reg>;
vddio-supply = <&vmipi_reg>;
@@ -280,11 +285,10 @@
max8997_pmic@66 {
compatible = "maxim,max8997-pmic";
- interrupts-extended = <&gpx0 7 0>, <&gpx2 3 0>;
reg = <0x66>;
- interrupt-parent = <&gpx0>;
- interrupts = <7 IRQ_TYPE_NONE>;
+ interrupts-extended = <&gpx0 7 IRQ_TYPE_LEVEL_LOW>,
+ <&gpx2 3 IRQ_TYPE_EDGE_FALLING>;
max8997,pmic-buck1-uses-gpio-dvs;
max8997,pmic-buck2-uses-gpio-dvs;
@@ -314,145 +318,156 @@
regulators {
valive_reg: LDO2 {
- regulator-name = "VALIVE_1.1V_C210";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
+ regulator-name = "VALIVE_1.1V_C210";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
};
vusb_reg: LDO3 {
- regulator-name = "VUSB_1.1V_C210";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
+ regulator-name = "VUSB_1.1V_C210";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
};
vmipi_reg: LDO4 {
- regulator-name = "VMIPI_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
};
vpda_reg: LDO6 {
- regulator-name = "VCC_1.8V_PDA";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
+ regulator-name = "VCC_1.8V_PDA";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
};
vcam_reg: LDO7 {
- regulator-name = "CAM_ISP_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-name = "CAM_ISP_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
};
vusbdac_reg: LDO8 {
- regulator-name = "VUSB+VDAC_3.3V_C210";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ regulator-name = "VUSB+VDAC_3.3V_C210";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
vccpda_reg: LDO9 {
- regulator-name = "VCC_2.8V_PDA";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
+ regulator-name = "VCC_2.8V_PDA";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
};
vpll_reg: LDO10 {
- regulator-name = "VPLL_1.1V_C210";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
+ regulator-name = "VPLL_1.1V_C210";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
};
vtcam_reg: LDO12 {
- regulator-name = "VT_CAM_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-name = "VT_CAM_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
};
vcclcd_reg: LDO13 {
- regulator-name = "VCC_3.3V_LCD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ regulator-name = "VCC_3.3V_LCD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
vlcd_reg: LDO15 {
- regulator-name = "VLCD_2.2V";
- regulator-min-microvolt = <2200000>;
- regulator-max-microvolt = <2200000>;
+ regulator-name = "VLCD_2.2V";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
};
camsensor_reg: LDO16 {
- regulator-name = "CAM_SENSOR_IO_1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-name = "CAM_SENSOR_IO_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
};
tflash_reg: LDO17 {
- regulator-name = "VTF_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
};
vddq_reg: LDO21 {
- regulator-name = "VDDQ_M1M2_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
+ regulator-name = "VDDQ_M1M2_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
};
varm_breg: BUCK1 {
- /*
- * HACK: The real name is VARM_1.2V_C210,
- * but exynos-cpufreq does not support
- * DT-based regulator lookup yet.
- */
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
+ regulator-name = "VARM_1.2V_C210";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
};
vint_breg: BUCK2 {
- regulator-name = "VINT_1.1V_C210";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
+ regulator-name = "VINT_1.1V_C210";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
};
camisp_breg: BUCK4 {
- regulator-name = "CAM_ISP_CORE_1.2V";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
};
vmem_breg: BUCK5 {
- regulator-name = "VMEM_1.2V_C210";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
+ regulator-name = "VMEM_1.2V_C210";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
};
vccsub_breg: BUCK7 {
- regulator-name = "VCC_SUB_2.0V";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-always-on;
+ regulator-name = "VCC_SUB_2.0V";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
};
safe1_sreg: ESAFEOUT1 {
- regulator-name = "SAFEOUT1";
+ regulator-name = "SAFEOUT1";
};
safe2_sreg: ESAFEOUT2 {
- regulator-name = "SAFEOUT2";
- regulator-boot-on;
+ regulator-name = "SAFEOUT2";
+ regulator-boot-on;
+ };
+
+ EN32KHZ_AP {
+ regulator-name = "EN32KHZ_AP";
+ regulator-always-on;
+ };
+
+ EN32KHZ_CP {
+ regulator-name = "EN32KHZ_CP";
+ regulator-always-on;
};
};
};
};
+&rtc {
+ status = "okay";
+ clocks = <&clock CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
+};
+
&sdhci_0 {
bus-width = <8>;
non-removable;
@@ -471,6 +486,30 @@
status = "okay";
};
+&sdhci_3 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ non-removable;
+ bus-width = <4>;
+ mmc-pwrseq = <&wlan_pwrseq>;
+ vmmc-supply = <&tflash_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>;
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4330-fmac";
+ reg = <1>;
+
+ interrupt-parent = <&gpx2>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};
+
&serial_0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 1b55783..08284e8 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -39,10 +39,17 @@
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
+
+ pmic_ap_clk: pmic-ap-clk {
+ /* Workaround for missing clock on PMIC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
vemmc_reg: voltage-regulator {
- compatible = "regulator-fixed";
+ compatible = "regulator-fixed";
regulator-name = "VMEM_VDD_2_8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@@ -50,6 +57,11 @@
enable-active-high;
};
+ wlan_pwrseq: sdhci3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpe3 1 GPIO_ACTIVE_LOW>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -99,7 +111,7 @@
};
tsp_reg: voltage-regulator {
- compatible = "regulator-fixed";
+ compatible = "regulator-fixed";
regulator-name = "TSP_2_8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@@ -107,13 +119,13 @@
enable-active-high;
};
- spi-lcd {
+ spi-3 {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
- gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>;
@@ -164,7 +176,8 @@
hdmi_ddc: i2c-ddc {
compatible = "i2c-gpio";
- gpios = <&gpe4 2 GPIO_ACTIVE_HIGH &gpe4 3 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpe4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpe4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <100>;
#address-cells = <1>;
#size-cells = <0>;
@@ -175,20 +188,6 @@
};
};
-&amba {
- mdma0: mdma@12840000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x12840000 0x1000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_MDMA>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
- power-domains = <&pd_lcd0>;
- };
-};
-
&camera {
status = "okay";
@@ -200,6 +199,19 @@
cpu0-supply = <&vdd_arm_reg>;
};
+&cpu_thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz */
+ cooling-device = <&cpu0 2 2>;
+ };
+ map1 {
+ /* Corresponds to 200MHz */
+ cooling-device = <&cpu0 4 4>;
+ };
+ };
+};
+
&ehci {
status = "okay";
phys = <&exynos_usbphy 1>;
@@ -317,7 +329,7 @@
max8952,sync-freq = <0>;
max8952,ramp-speed = <0>;
- regulator-name = "vdd_arm";
+ regulator-name = "VARM_1.2V_C210";
regulator-min-microvolt = <770000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
@@ -545,6 +557,12 @@
status = "okay";
};
+&rtc {
+ status = "okay";
+ clocks = <&clock CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
+};
+
&sdhci_0 {
bus-width = <8>;
non-removable;
@@ -563,6 +581,29 @@
status = "okay";
};
+&sdhci_3 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ non-removable;
+ bus-width = <4>;
+ mmc-pwrseq = <&wlan_pwrseq>;
+ vmmc-supply = <&ldo5_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>;
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4330-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpx2>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+};
+
&serial_0 {
status = "okay";
/delete-property/dmas;
@@ -587,17 +628,31 @@
/delete-property/dma-names;
};
+&soc {
+ mdma0: mdma@12840000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x12840000 0x1000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_MDMA>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <1>;
+ power-domains = <&pd_lcd0>;
+ };
+};
+
&sysram {
- smp-sysram@0 {
+ smp-sram@0 {
status = "disabled";
};
- smp-sysram@5000 {
+ smp-sram@5000 {
compatible = "samsung,exynos4210-sysram";
reg = <0x5000 0x1000>;
};
- smp-sysram@1f000 {
+ smp-sram@1f000 {
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index f220716..fddc661 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -72,60 +72,53 @@
};
soc: soc {
- sysram: sysram@2020000 {
+ sysram: sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x20000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@1f000 {
+ smp-sram@1f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x1f000 0x1000>;
};
};
- pd_lcd1: lcd1-power-domain@10023ca0 {
+ pd_lcd1: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
label = "LCD1";
};
- l2c: l2-cache-controller@10502000 {
+ l2c: cache-controller@10502000 {
compatible = "arm,pl310-cache";
reg = <0x10502000 0x1000>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
arm,tag-latency = <2 2 1>;
arm,data-latency = <2 2 1>;
};
- mct: mct@10050000 {
+ mct: timer@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map =
- <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
- <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
- <2 &combiner 12 6>,
- <3 &combiner 12 7>,
- <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
- <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
- };
+ interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <&combiner 12 6>,
+ <&combiner 12 7>,
+ <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@10060000 {
@@ -372,26 +365,24 @@
};
};
};
+};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&tmu 0>;
+&cpu_alert0 {
+ temperature = <85000>; /* millicelsius */
+};
- trips {
- cpu_alert0: cpu-alert-0 {
- temperature = <85000>; /* millicelsius */
- };
- cpu_alert1: cpu-alert-1 {
- temperature = <100000>; /* millicelsius */
- };
- cpu_alert2: cpu-alert-2 {
- temperature = <110000>; /* millicelsius */
- };
- };
- };
- };
+&cpu_alert1 {
+ temperature = <100000>; /* millicelsius */
+};
+
+&cpu_alert2 {
+ temperature = <110000>; /* millicelsius */
+};
+
+&cpu_thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tmu 0>;
};
&gic {
diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
index 4b9c4ca..89ed81f 100644
--- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
+++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
@@ -33,7 +33,7 @@
};
};
- lcd_vdd3_reg: voltage-regulator-6 {
+ lcd_vdd3_reg: voltage-regulator-10 {
compatible = "regulator-fixed";
regulator-name = "LCD_VDD_2.2V";
regulator-min-microvolt = <2200000>;
@@ -42,7 +42,7 @@
enable-active-high;
};
- ps_als_reg: voltage-regulator-7 {
+ ps_als_reg: voltage-regulator-11 {
compatible = "regulator-fixed";
regulator-name = "LED_A_3.0V";
regulator-min-microvolt = <3000000>;
@@ -53,7 +53,8 @@
i2c_ak8975: i2c-gpio-0 {
compatible = "i2c-gpio";
- gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
@@ -68,7 +69,8 @@
i2c_cm36651: i2c-gpio-2 {
compatible = "i2c-gpio";
- gpios = <&gpf0 0 GPIO_ACTIVE_HIGH>, <&gpf0 1 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpf0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpf0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
@@ -168,3 +170,46 @@
vdda-supply = <&ldo17_reg>;
status = "okay";
};
+
+&sound {
+ samsung,audio-routing =
+ "HP", "HPOUT1L",
+ "HP", "HPOUT1R",
+
+ "SPK", "SPKOUTLN",
+ "SPK", "SPKOUTLP",
+ "SPK", "SPKOUTRN",
+ "SPK", "SPKOUTRP",
+
+ "RCV", "HPOUT2N",
+ "RCV", "HPOUT2P",
+
+ "HDMI", "LINEOUT1N",
+ "HDMI", "LINEOUT1P",
+
+ "LINE", "LINEOUT2N",
+ "LINE", "LINEOUT2P",
+
+ "IN1LP", "MICBIAS1",
+ "IN1LN", "MICBIAS1",
+ "Main Mic", "MICBIAS1",
+
+ "IN1RP", "Sub Mic",
+ "IN1RN", "Sub Mic",
+
+ "IN2LP:VXRN", "MICBIAS2",
+ "Headset Mic", "MICBIAS2",
+
+ "IN2RN", "FM In",
+ "IN2RP:VXRP", "FM In";
+};
+
+&submic_bias_reg {
+ gpio = <&gpf2 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+};
+
+&touchkey_reg {
+ gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-i9300.dts b/arch/arm/boot/dts/exynos4412-i9300.dts
index f8125a9..07fbcf8 100644
--- a/arch/arm/boot/dts/exynos4412-i9300.dts
+++ b/arch/arm/boot/dts/exynos4412-i9300.dts
@@ -17,6 +17,10 @@
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
};
};
+
+&sound {
+ fm-sel-gpios = <&gpl0 3 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/boot/dts/exynos4412-i9305.dts b/arch/arm/boot/dts/exynos4412-i9305.dts
index 54a2a55..6bc3d89 100644
--- a/arch/arm/boot/dts/exynos4412-i9305.dts
+++ b/arch/arm/boot/dts/exynos4412-i9305.dts
@@ -10,7 +10,7 @@
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x80000000>;
+ reg = <0x40000000 0x80000000>;
};
};
diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
index fedb213..0645006 100644
--- a/arch/arm/boot/dts/exynos4412-midas.dtsi
+++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
@@ -13,6 +13,7 @@
#include "exynos4412.dtsi"
#include "exynos4412-ppmu-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/maxim,max77686.h>
#include <dt-bindings/pinctrl/samsung.h>
@@ -36,12 +37,12 @@
fixed-rate-clocks {
xxti {
- compatible = "samsung,clock-xxti", "fixed-clock";
+ compatible = "samsung,clock-xxti";
clock-frequency = <0>;
};
xusbxti {
- compatible = "samsung,clock-xusbxti", "fixed-clock";
+ compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
};
@@ -92,6 +93,39 @@
enable-active-high;
};
+ touchkey_reg: voltage-regulator-6 {
+ compatible = "regulator-fixed";
+ regulator-name = "LED_VDD_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ status = "disabled";
+ };
+
+ vbatt_reg: voltage-regulator-7 {
+ compatible = "regulator-fixed";
+ regulator-name = "VBATT";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ mic_bias_reg: voltage-regulator-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "MICBIAS_LDO_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpf1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ submic_bias_reg: voltage-regulator-9 {
+ compatible = "regulator-fixed";
+ regulator-name = "SUB_MICBIAS_LDO_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -130,7 +164,8 @@
i2c_max77693: i2c-gpio-1 {
compatible = "i2c-gpio";
- gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
@@ -178,7 +213,8 @@
i2c_max77693_fuel: i2c-gpio-3 {
compatible = "i2c-gpio";
- gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpf1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpf1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
@@ -197,9 +233,29 @@
};
};
+ i2c-gpio-4 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpl0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpl0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchkey@20 {
+ compatible = "cypress,midas-touchkey";
+ reg = <0x20>;
+ vdd-supply = <&touchkey_reg>;
+ vcc-supply = <&ldo5_reg>;
+ interrupt-parent = <&gpj0>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ linux,keycodes = <KEY_BACK KEY_MENU>;
+ };
+ };
+
i2c-mhl {
compatible = "i2c-gpio";
- gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpf0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpf0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <100>;
#address-cells = <1>;
#size-cells = <0>;
@@ -234,16 +290,18 @@
clock-names = "ext_clock";
};
- sound {
- compatible = "samsung,trats2-audio";
- samsung,i2s-controller = <&i2s0>;
- samsung,model = "Trats2";
- samsung,audio-codec = <&wm1811>;
- samsung,audio-routing =
- "SPK", "SPKOUTLN",
- "SPK", "SPKOUTLP",
- "SPK", "SPKOUTRN",
- "SPK", "SPKOUTRP";
+ sound: sound {
+ compatible = "samsung,midas-audio";
+ model = "Midas";
+ mic-bias-supply = <&mic_bias_reg>;
+ submic-bias-supply = <&submic_bias_reg>;
+
+ cpu {
+ sound-dai = <&i2s0 0>;
+ };
+ codec {
+ sound-dai = <&wm1811>;
+ };
};
thermistor-ap {
@@ -261,25 +319,6 @@
pulldown-ohm = <100000>; /* 100K */
io-channels = <&adc 2>; /* Battery temperature */
};
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- cooling-maps {
- map0 {
- /* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
- <&cpu2 7 7>, <&cpu3 7 7>;
- };
- map1 {
- /* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 13 13>,
- <&cpu1 13 13>,
- <&cpu2 13 13>,
- <&cpu3 13 13>;
- };
- };
- };
- };
};
&adc {
@@ -348,6 +387,21 @@
cpu0-supply = <&buck2_reg>;
};
+&cpu_thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
+ <&cpu2 7 7>, <&cpu3 7 7>;
+ };
+ map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 13 13>, <&cpu1 13 13>,
+ <&cpu2 13 13>, <&cpu3 13 13>;
+ };
+ };
+};
+
&csis_0 {
status = "okay";
vddcore-supply = <&ldo8_reg>;
@@ -565,11 +619,37 @@
wm1811: wm1811@1a {
compatible = "wlf,wm1811";
reg = <0x1a>;
- clocks = <&pmu_system_controller 0>;
- clock-names = "MCLK1";
- DCVDD-supply = <&ldo3_reg>;
+ clocks = <&pmu_system_controller 0>,
+ <&max77686 MAX77686_CLK_PMIC>;
+ clock-names = "MCLK1", "MCLK2";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpx3>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ #sound-dai-cells = <0>;
+
+ wlf,gpio-cfg = <0x3 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x8000 0x0 0x0 0x0>;
+ wlf,micbias-cfg = <0x2f 0x2b>;
+
+ wlf,lineout1-feedback;
+ wlf,lineout1-se;
+ wlf,lineout2-se;
+ wlf,ldoena-always-driven;
+
+ AVDD2-supply = <&vbatt_reg>;
DBVDD1-supply = <&ldo3_reg>;
+ DBVDD2-supply = <&vbatt_reg>;
+ DBVDD3-supply = <&vbatt_reg>;
+ DCVDD-supply = <&ldo3_reg>;
+ CPVDD-supply = <&vbatt_reg>;
+ SPKVDD1-supply = <&vbatt_reg>;
+ SPKVDD2-supply = <&vbatt_reg>;
wlf,ldo1ena = <&gpj0 4 0>;
+ wlf,ldo2ena = <&gpj0 4 0>;
};
};
@@ -791,7 +871,7 @@
};
buck1_reg: BUCK1 {
- regulator-name = "vdd_mif";
+ regulator-name = "VDD_MIF";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
@@ -802,7 +882,7 @@
};
buck2_reg: BUCK2 {
- regulator-name = "vdd_arm";
+ regulator-name = "VDD_ARM";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
@@ -813,7 +893,7 @@
};
buck3_reg: BUCK3 {
- regulator-name = "vdd_int";
+ regulator-name = "VDD_INT";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
@@ -824,7 +904,7 @@
};
buck4_reg: BUCK4 {
- regulator-name = "vdd_g3d";
+ regulator-name = "VDD_G3D";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts
index fe2bfd7..a47b7f3 100644
--- a/arch/arm/boot/dts/exynos4412-n710x.dts
+++ b/arch/arm/boot/dts/exynos4412-n710x.dts
@@ -8,12 +8,12 @@
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x80000000>;
+ reg = <0x40000000 0x80000000>;
};
/* bootargs are passed in by bootloader */
- cam_vdda_reg: voltage-regulator-6 {
+ cam_vdda_reg: voltage-regulator-10 {
compatible = "regulator-fixed";
regulator-name = "CAM_SENSOR_CORE_1.2V";
regulator-min-microvolt = <1200000>;
@@ -73,3 +73,43 @@
vdda-supply = <&cam_vdda_reg>;
status = "okay";
};
+
+&sound {
+ samsung,audio-routing =
+ "HP", "HPOUT1L",
+ "HP", "HPOUT1R",
+
+ "SPK", "SPKOUTLN",
+ "SPK", "SPKOUTLP",
+
+ "RCV", "HPOUT2N",
+ "RCV", "HPOUT2P",
+
+ "HDMI", "LINEOUT1N",
+ "HDMI", "LINEOUT1P",
+
+ "LINE", "LINEOUT2N",
+ "LINE", "LINEOUT2P",
+
+ "IN1LP", "MICBIAS2",
+ "IN1LN", "MICBIAS2",
+ "Headset Mic", "MICBIAS2",
+
+ "IN1RP", "Sub Mic",
+ "IN1RN", "Sub Mic",
+
+ "IN2LP:VXRN", "Main Mic",
+ "IN2LN", "Main Mic",
+
+ "IN2RN", "FM In",
+ "IN2RP:VXRP", "FM In";
+};
+
+&submic_bias_reg {
+ regulator-always-on;
+};
+
+&touchkey_reg {
+ gpio = <&gpm0 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 424d12e..869d80b 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -66,25 +66,6 @@
clock-frequency = <24000000>;
};
};
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- cooling-maps {
- cooling_map0: map0 {
- /* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
- <&cpu2 7 7>, <&cpu3 7 7>;
- };
- cooling_map1: map1 {
- /* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 13 13>,
- <&cpu1 13 13>,
- <&cpu2 13 13>,
- <&cpu3 13 13>;
- };
- };
- };
- };
};
&bus_dmc {
@@ -165,6 +146,30 @@
cpu0-supply = <&buck2_reg>;
};
+&cpu0_opp_table {
+ opp-1000000000 {
+ opp-suspend;
+ };
+ opp-800000000 {
+ /delete-property/opp-suspend;
+ };
+};
+
+&cpu_thermal {
+ cooling-maps {
+ cooling_map0: map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
+ <&cpu2 7 7>, <&cpu3 7 7>;
+ };
+ cooling_map1: map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 13 13>, <&cpu1 13 13>,
+ <&cpu2 13 13>, <&cpu3 13 13>;
+ };
+ };
+};
+
&pinctrl_1 {
gpio_power_key: power_key {
samsung,pins = "gpx1-3";
@@ -267,7 +272,7 @@
intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
};
@@ -421,7 +426,7 @@
};
buck1_reg: BUCK1 {
- regulator-name = "vdd_mif";
+ regulator-name = "VDD_MIF";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
@@ -429,7 +434,7 @@
};
buck2_reg: BUCK2 {
- regulator-name = "vdd_arm";
+ regulator-name = "VDD_ARM";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
@@ -437,7 +442,7 @@
};
buck3_reg: BUCK3 {
- regulator-name = "vdd_int";
+ regulator-name = "VDD_INT";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
@@ -445,7 +450,7 @@
};
buck4_reg: BUCK4 {
- regulator-name = "vdd_g3d";
+ regulator-name = "VDD_G3D";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1100000>;
regulator-microvolt-offset = <50000>;
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts
index 8ff243b..b8549d8 100644
--- a/arch/arm/boot/dts/exynos4412-odroidu3.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
@@ -37,31 +37,6 @@
#cooling-cells = <2>;
cooling-levels = <0 102 170 230>;
};
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- cooling-maps {
- map0 {
- trip = <&cpu_alert1>;
- cooling-device = <&cpu0 9 9>, <&cpu1 9 9>,
- <&cpu2 9 9>, <&cpu3 9 9>,
- <&fan0 1 2>;
- };
- map1 {
- trip = <&cpu_alert2>;
- cooling-device = <&cpu0 15 15>,
- <&cpu1 15 15>,
- <&cpu2 15 15>,
- <&cpu3 15 15>,
- <&fan0 2 3>;
- };
- map2 {
- trip = <&cpu_alert0>;
- cooling-device = <&fan0 0 1>;
- };
- };
- };
- };
};
&adc {
@@ -76,6 +51,27 @@
regulator-max-microvolt = <3300000>;
};
+&cpu_thermal {
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&cpu0 9 9>, <&cpu1 9 9>,
+ <&cpu2 9 9>, <&cpu3 9 9>,
+ <&fan0 1 2>;
+ };
+ map1 {
+ trip = <&cpu_alert2>;
+ cooling-device = <&cpu0 15 15>, <&cpu1 15 15>,
+ <&cpu2 15 15>, <&cpu3 15 15>,
+ <&fan0 2 3>;
+ };
+ map2 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&fan0 0 1>;
+ };
+ };
+};
+
&hdmicec {
needs-hpd;
};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index ecd14b2..c2e793b 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -11,6 +11,7 @@
/dts-v1/;
#include "exynos4412.dtsi"
+#include <dt-bindings/clock/samsung,s2mps11.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "exynos-mfc-reserved-memory.dtsi"
@@ -33,20 +34,13 @@
reg = <0x0203F000 0x1000>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- mmc_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "VMEM_VDD_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ mmc_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VMEM_VDD_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
display-timings {
@@ -81,6 +75,21 @@
cpu0-supply = <&buck2_reg>;
};
+&cpu_thermal {
+ cooling-maps {
+ cooling_map0: map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
+ <&cpu2 7 7>, <&cpu3 7 7>;
+ };
+ cooling_map1: map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 13 13>, <&cpu1 13 13>,
+ <&cpu2 13 13>, <&cpu3 13 13>;
+ };
+ };
+};
+
&exynos_usbphy {
status = "okay";
};
@@ -136,6 +145,13 @@
<1200000>, <1200000>,
<1200000>, <1200000>;
+ s5m8767_osc: clocks {
+ compatible = "samsung,s5m8767-clk";
+ #clock-cells = <1>;
+ clock-output-names = "s5m8767_ap", "s5m8767_cp",
+ "s5m8767_bt";
+ };
+
regulators {
ldo1_reg: LDO1 {
regulator-name = "VDD_ALIVE";
@@ -363,7 +379,7 @@
};
buck1_reg: BUCK1 {
- regulator-name = "vdd_mif";
+ regulator-name = "VDD_MIF";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
@@ -372,7 +388,7 @@
};
buck2_reg: BUCK2 {
- regulator-name = "vdd_arm";
+ regulator-name = "VDD_ARM";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
@@ -381,7 +397,7 @@
};
buck3_reg: BUCK3 {
- regulator-name = "vdd_int";
+ regulator-name = "VDD_INT";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
@@ -390,7 +406,7 @@
};
buck4_reg: BUCK4 {
- regulator-name = "vdd_g3d";
+ regulator-name = "VDD_G3D";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
@@ -399,7 +415,7 @@
};
buck5_reg: BUCK5 {
- regulator-name = "vdd_m12";
+ regulator-name = "VDD_M12";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
@@ -408,7 +424,7 @@
};
buck6_reg: BUCK6 {
- regulator-name = "vdd12_5m";
+ regulator-name = "VDD12_5M";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
@@ -417,7 +433,7 @@
};
buck9_reg: BUCK9 {
- regulator-name = "vddf28_emmc";
+ regulator-name = "VDDF28_EMMC";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
@@ -506,6 +522,8 @@
&rtc {
status = "okay";
+ clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
};
&sdhci_2 {
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index e70fb6e..4997120 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -37,6 +37,28 @@
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
+
+ pmic_ap_clk: pmic-ap-clk {
+ /* Workaround for missing clock on PMIC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
+
+&cpu_thermal {
+ cooling-maps {
+ cooling_map0: map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
+ <&cpu2 7 7>, <&cpu3 7 7>;
+ };
+ cooling_map1: map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 13 13>, <&cpu1 13 13>,
+ <&cpu2 13 13>, <&cpu3 13 13>;
+ };
};
};
@@ -127,6 +149,11 @@
};
};
+&rtc {
+ clocks = <&clock CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
+};
+
&sdhci_2 {
bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
index 01f37b5..017b261 100644
--- a/arch/arm/boot/dts/exynos4412-tiny4412.dts
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -65,11 +65,60 @@
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
+
+ pmic_ap_clk: pmic-ap-clk {
+ /* Workaround for missing clock on PMIC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ panel {
+ compatible = "innolux,at070tn92";
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&lcdc_output>;
+ };
+ };
+ };
+};
+
+&cpu_thermal {
+ cooling-maps {
+ cooling_map0: map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
+ <&cpu2 7 7>, <&cpu3 7 7>;
+ };
+ cooling_map1: map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 13 13>, <&cpu1 13 13>,
+ <&cpu2 13 13>, <&cpu3 13 13>;
+ };
+ };
+};
+
+&fimd {
+ pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ port@3 {
+ reg = <3>;
+ lcdc_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
};
};
&rtc {
status = "okay";
+ clocks = <&clock CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
};
&sdhci_2 {
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index aac5339..7b447b6 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -18,7 +18,7 @@
memory@40000000 {
device_type = "memory";
- reg = <0x40000000 0x40000000>;
+ reg = <0x40000000 0x40000000>;
};
chosen {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d20db2d..e76881d 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -76,7 +76,7 @@
};
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
@@ -188,36 +188,38 @@
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
- sysram@2020000 {
+ sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x40000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@2f000 {
+ smp-sram@2f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x2f000 0x1000>;
};
};
- pd_isp: isp-power-domain@10023ca0 {
+ pd_isp: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
label = "ISP";
};
- l2c: l2-cache-controller@10502000 {
+ l2c: cache-controller@10502000 {
compatible = "arm,pl310-cache";
reg = <0x10502000 0x1000>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
arm,tag-latency = <2 2 1>;
arm,data-latency = <3 2 1>;
arm,double-linefill = <1>;
@@ -243,25 +245,16 @@
clock-names = "aclk200", "aclk400_mcuisp";
};
- mct@10050000 {
+ timer@10050000 {
compatible = "samsung,exynos4412-mct";
reg = <0x10050000 0x800>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map =
- <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
- <1 &combiner 12 5>,
- <2 &combiner 12 6>,
- <3 &combiner 12 7>,
- <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
- };
+ interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <&combiner 12 5>,
+ <&combiner 12 6>,
+ <&combiner 12 7>,
+ <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@10060000 {
@@ -409,7 +402,7 @@
status = "disabled";
};
- bus_dmc_opp_table: opp_table1 {
+ bus_dmc_opp_table: opp-table1 {
compatible = "operating-points-v2";
opp-shared;
@@ -436,7 +429,7 @@
};
};
- bus_acp_opp_table: opp_table2 {
+ bus_acp_opp_table: opp-table2 {
compatible = "operating-points-v2";
opp-shared;
@@ -502,7 +495,7 @@
status = "disabled";
};
- bus_leftbus_opp_table: opp_table3 {
+ bus_leftbus_opp_table: opp-table3 {
compatible = "operating-points-v2";
opp-shared;
@@ -525,7 +518,7 @@
};
};
- bus_display_opp_table: opp_table4 {
+ bus_display_opp_table: opp-table4 {
compatible = "operating-points-v2";
opp-shared;
@@ -537,7 +530,7 @@
};
};
- bus_fsys_opp_table: opp_table5 {
+ bus_fsys_opp_table: opp-table5 {
compatible = "operating-points-v2";
opp-shared;
@@ -549,7 +542,7 @@
};
};
- bus_peri_opp_table: opp_table6 {
+ bus_peri_opp_table: opp-table6 {
compatible = "operating-points-v2";
opp-shared;
@@ -741,7 +734,7 @@
"pmu";
operating-points-v2 = <&gpu_opp_table>;
- gpu_opp_table: opp_table {
+ gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 67f9b45..9ce9fb3 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -35,7 +35,7 @@
#size-cells = <1>;
ranges;
- chipid@10000000 {
+ chipid: chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
@@ -86,7 +86,7 @@
};
gic: interrupt-controller@10481000 {
- compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10481000 0x1000>,
@@ -211,13 +211,13 @@
};
prng: rng@10830400 {
- compatible = "samsung,exynos5250-prng";
- reg = <0x10830400 0x200>;
+ compatible = "samsung,exynos5250-prng";
+ reg = <0x10830400 0x200>;
};
trng: rng@10830600 {
- compatible = "samsung,exynos5250-trng";
- reg = <0x10830600 0x100>;
+ compatible = "samsung,exynos5250-trng";
+ reg = <0x10830600 0x100>;
};
g2d: g2d@10850000 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 6fcb78a..79546f1 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -11,10 +11,11 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/samsung,s2mps11.h>
+#include <dt-bindings/sound/samsung-i2s.h>
#include "exynos5250.dtsi"
/ {
- model = "Insignal Arndale evaluation board based on EXYNOS5250";
+ model = "Insignal Arndale evaluation board based on Exynos5250";
compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5";
memory@40000000 {
@@ -83,56 +84,54 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ main_dc_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "MAIN_DC";
+ regulator-always-on;
+ };
- main_dc_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "MAIN_DC";
- };
+ mmc_reg: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_MMC";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
- mmc_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "VDD_33ON_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ reg_hdmi_en: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi-en";
+ regulator-always-on;
+ };
- reg_hdmi_en: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "hdmi-en";
- };
+ vcc_1v2_reg: regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
- vcc_1v2_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "VCC_1V2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- };
+ vcc_1v8_reg: regulator-4 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
- vcc_1v8_reg: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
+ vcc_3v3_reg: regulator-5 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
- vcc_3v3_reg: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
+ sound {
+ compatible = "samsung,arndale-wm1811";
+ samsung,audio-cpu = <&i2s0>;
+ samsung,audio-codec = <&wm1811>;
};
fixed-rate-clocks {
@@ -147,10 +146,20 @@
compatible = "smsc,usb3503a";
reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
- connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>;
+ connect-gpios = <&gpd1 7 GPIO_ACTIVE_HIGH>;
};
};
+&clock {
+ assigned-clocks = <&clock CLK_FOUT_EPLL>;
+ assigned-clock-rates = <49152000>;
+};
+
+&clock_audss {
+ assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+};
+
&cpu0 {
cpu0-supply = <&buck2_reg>;
};
@@ -234,11 +243,11 @@
s5m8767,pmic-buck3-dvs-voltage = <1100000>;
s5m8767,pmic-buck4-dvs-voltage = <1200000>;
s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>,
- <&gpd1 1 GPIO_ACTIVE_HIGH>,
- <&gpd1 2 GPIO_ACTIVE_HIGH>;
+ <&gpd1 1 GPIO_ACTIVE_HIGH>,
+ <&gpd1 2 GPIO_ACTIVE_HIGH>;
s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>,
- <&gpx2 4 GPIO_ACTIVE_HIGH>,
- <&gpx2 5 GPIO_ACTIVE_HIGH>;
+ <&gpx2 4 GPIO_ACTIVE_HIGH>,
+ <&gpx2 5 GPIO_ACTIVE_HIGH>;
s5m8767_osc: clocks {
compatible = "samsung,s5m8767-clk";
@@ -433,7 +442,7 @@
};
buck1_reg: BUCK1 {
- regulator-name = "vdd_mif";
+ regulator-name = "VDD_MIF";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
@@ -442,7 +451,7 @@
};
buck2_reg: BUCK2 {
- regulator-name = "vdd_arm";
+ regulator-name = "VDD_ARM";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
@@ -451,7 +460,7 @@
};
buck3_reg: BUCK3 {
- regulator-name = "vdd_int";
+ regulator-name = "VDD_INT";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
@@ -460,7 +469,7 @@
};
buck4_reg: BUCK4 {
- regulator-name = "vdd_g3d";
+ regulator-name = "VDD_G3D";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
@@ -502,9 +511,11 @@
&i2c_3 {
status = "okay";
- wm1811a@1a {
+ wm1811: codec@1a {
compatible = "wlf,wm1811";
reg = <0x1a>;
+ clocks = <&i2s0 CLK_I2S_CDCLK>;
+ clock-names = "MCLK1";
AVDD2-supply = <&main_dc_reg>;
CPVDD-supply = <&main_dc_reg>;
@@ -531,18 +542,18 @@
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <40000>;
- samsung,i2c-slave-addr = <0x38>;
-
- sata_phy_i2c:sata-phy@38 {
- compatible = "samsung,exynos-sataphy-i2c";
- reg = <0x38>;
- };
};
&i2s0 {
+ assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+ assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
status = "okay";
};
+&i2s0_bus {
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+};
+
&mali {
mali-supply = <&buck4_reg>;
status = "okay";
@@ -602,19 +613,22 @@
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
};
+&sata_phy_i2c {
+ status = "okay";
+};
+
&soc {
/*
* For unknown reasons HDMI-DDC does not work with Exynos I2C
* controllers. Lets use software I2C over GPIO pins as a workaround.
*/
- i2c_ddc: i2c-gpio {
+ i2c_ddc: i2c-10 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_gpio_bus>;
status = "okay";
compatible = "i2c-gpio";
- gpios = <&gpa0 6 0 /* sda */
- &gpa0 7 0 /* scl */
- >;
+ sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 70a2b6e..d0e48c1 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -1,18 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG SMDK5250 board device tree source
+ * Samsung SMDK5250 board device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*/
/dts-v1/;
+#include <dt-bindings/clock/maxim,max77686.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos5250.dtsi"
/ {
- model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+ model = "Samsung SMDK5250 board based on Exynos5250";
compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5";
aliases {
@@ -129,13 +130,14 @@
reg = <0x50>;
};
- max77686@9 {
+ max77686: pmic@9 {
compatible = "maxim,max77686";
reg = <0x09>;
interrupt-parent = <&gpx3>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&max77686_irq>;
+ #clock-cells = <1>;
wakeup-source;
voltage-regulators {
@@ -324,12 +326,6 @@
status = "okay";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <40000>;
- samsung,i2c-slave-addr = <0x38>;
-
- sata_phy_i2c: sata-phy@38 {
- compatible = "samsung,exynos-sataphy-i2c";
- reg = <0x38>;
- };
};
&i2s0 {
@@ -368,6 +364,8 @@
&rtc {
status = "okay";
+ clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
};
&sata {
@@ -379,6 +377,10 @@
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
};
+&sata_phy_i2c {
+ status = "okay";
+};
+
&spi_1 {
status = "okay";
cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index 2355c53..5a9c936 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -7,6 +7,7 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/samsung,s2mps11.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
@@ -114,12 +115,12 @@
wakeup-source;
s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */
- <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */
- <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */
+ <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */
+ <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */
s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */
- <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */
- <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */
+ <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */
+ <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */
/*
* The following arrays of DVS voltages are not used, since we are
@@ -127,26 +128,26 @@
* to please the driver.
*/
s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>,
- <1250000>, <1200000>,
- <1150000>, <1100000>,
- <1000000>, <950000>;
+ <1250000>, <1200000>,
+ <1150000>, <1100000>,
+ <1000000>, <950000>;
s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
- <1100000>, <1100000>,
- <1000000>, <1000000>,
- <1000000>, <1000000>;
+ <1100000>, <1100000>,
+ <1000000>, <1000000>,
+ <1000000>, <1000000>;
s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
- <1200000>, <1200000>,
- <1200000>, <1200000>,
- <1200000>, <1200000>;
+ <1200000>, <1200000>,
+ <1200000>, <1200000>,
+ <1200000>, <1200000>;
- clocks {
+ s5m8767_osc: clocks {
compatible = "samsung,s5m8767-clk";
#clock-cells = <1>;
clock-output-names = "en32khz_ap",
- "en32khz_cp",
- "en32khz_bt";
+ "en32khz_cp",
+ "en32khz_bt";
};
regulators {
@@ -456,7 +457,7 @@
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
- dp_hpd_gpio: dp-hpd-gpio {
+ dp_hpd_gpio: dp-hpd {
samsung,pins = "gpc3-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
@@ -522,6 +523,12 @@
};
};
+&rtc {
+ status = "okay";
+ clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
+};
+
&sd1_bus4 {
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index fc966c1..bd2d883 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -1,16 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5250 SoC device tree source
+ * Samsung Exynos5250 SoC device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
- * EXYNOS5250 based board files can include this file and provide
+ * Samsung Exynos5250 SoC device nodes are listed in this file.
+ * Exynos5250 based board files can include this file and provide
* values for board specfic bindings.
*
* Note: This file does not include device nodes for all the controllers in
- * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
+ * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
* additional nodes can be added to this file.
*/
@@ -164,19 +164,19 @@
};
soc: soc {
- sysram@2020000 {
+ sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x30000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x30000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@2f000 {
+ smp-sram@2f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x2f000 0x1000>;
};
@@ -233,28 +233,17 @@
power-domains = <&pd_mau>;
};
- mct@101c0000 {
+ timer@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
- <4 0>, <5 0>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <2>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0x0 0 &combiner 23 3>,
- <0x1 0 &combiner 23 4>,
- <0x2 0 &combiner 25 2>,
- <0x3 0 &combiner 25 3>,
- <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
- <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
- };
+ interrupts-extended = <&combiner 23 3>,
+ <&combiner 23 4>,
+ <&combiner 25 2>,
+ <&combiner 25 3>,
+ <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_0: pinctrl@11400000 {
@@ -341,7 +330,7 @@
power-domains = <&pd_g3d>;
status = "disabled";
- gpu_opp_table: gpu-opp-table {
+ gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
@@ -484,6 +473,12 @@
clocks = <&clock CLK_SATA_PHYI2C>;
clock-names = "i2c";
status = "disabled";
+
+ sata_phy_i2c: sata-phy-i2c@38 {
+ compatible = "samsung,exynos-sataphy-i2c";
+ reg = <0x38>;
+ status = "disabled";
+ };
};
spi_0: spi@12d20000 {
@@ -586,9 +581,9 @@
compatible = "samsung,s5pv210-i2s";
status = "disabled";
reg = <0x03830000 0x100>;
- dmas = <&pdma0 10
- &pdma0 9
- &pdma0 8>;
+ dmas = <&pdma0 10>,
+ <&pdma0 9>,
+ <&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
@@ -606,8 +601,8 @@
compatible = "samsung,s3c6410-i2s";
status = "disabled";
reg = <0x12D60000 0x100>;
- dmas = <&pdma1 12
- &pdma1 11>;
+ dmas = <&pdma1 12>,
+ <&pdma1 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
clock-names = "iis", "i2s_opclk0";
@@ -621,8 +616,8 @@
compatible = "samsung,s3c6410-i2s";
status = "disabled";
reg = <0x12D70000 0x100>;
- dmas = <&pdma0 12
- &pdma0 11>;
+ dmas = <&pdma0 12>,
+ <&pdma0 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
clock-names = "iis", "i2s_opclk0";
@@ -690,59 +685,51 @@
samsung,pmureg-phandle = <&pmu_system_controller>;
};
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- pdma0: pdma@121a0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x121A0000 0x1000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- pdma1: pdma@121b0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x121B0000 0x1000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- mdma0: mdma@10800000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x10800000 0x1000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_MDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
- };
-
- mdma1: mdma@11c10000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x11C10000 0x1000>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_MDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
- };
+ pdma0: pdma@121a0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121A0000 0x1000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
};
- gsc_0: gsc@13e00000 {
+ pdma1: pdma@121b0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121B0000 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ mdma0: mdma@10800000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x10800000 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_MDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <1>;
+ };
+
+ mdma1: mdma@11c10000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x11C10000 0x1000>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_MDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <1>;
+ };
+
+ gsc_0: gsc@13e00000 {
compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -752,7 +739,7 @@
iommus = <&sysmmu_gsc0>;
};
- gsc_1: gsc@13e10000 {
+ gsc_1: gsc@13e10000 {
compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
@@ -762,7 +749,7 @@
iommus = <&sysmmu_gsc1>;
};
- gsc_2: gsc@13e20000 {
+ gsc_2: gsc@13e20000 {
compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
reg = <0x13e20000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
@@ -772,7 +759,7 @@
iommus = <&sysmmu_gsc2>;
};
- gsc_3: gsc@13e30000 {
+ gsc_3: gsc@13e30000 {
compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
reg = <0x13e30000 0x1000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
@@ -1104,26 +1091,6 @@
};
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&tmu 0>;
-
- cooling-maps {
- map0 {
- /* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
- };
- map1 {
- /* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 15 15>,
- <&cpu1 15 15>;
- };
- };
- };
- };
-
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -1139,6 +1106,24 @@
};
};
+&cpu_thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tmu 0>;
+
+ cooling-maps {
+ map0 {
+ /* Corresponds to 800MHz at freq_table */
+ cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
+ };
+ map1 {
+ /* Corresponds to 200MHz at freq_table */
+ cooling-device = <&cpu0 15 15>,
+ <&cpu1 15 15>;
+ };
+ };
+};
+
&dp {
power-domains = <&pd_disp1>;
clocks = <&clock CLK_DP>;
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 36a2b77..0dc2ec1 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG XYREF5260 board device tree source
+ * Samsung XYREF5260 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -10,7 +10,7 @@
#include "exynos5260.dtsi"
/ {
- model = "SAMSUNG XYREF5260 board based on EXYNOS5260";
+ model = "Samsung XYREF5260 board based on Exynos5260";
compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5";
memory@20000000 {
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 3581b57..973448c 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5260 SoC device tree source
+ * Samsung Exynos5260 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -162,10 +162,8 @@
};
gic: interrupt-controller@10481000 {
- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
- #address-cells = <0>;
- #size-cells = <0>;
interrupt-controller;
reg = <0x10481000 0x1000>,
<0x10482000 0x2000>,
@@ -180,7 +178,7 @@
reg = <0x10000000 0x100>;
};
- mct: mct@100b0000 {
+ mct: timer@100b0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x100B0000 0x1000>;
clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
index f68baaf..bd1d849 100644
--- a/arch/arm/boot/dts/exynos5410-odroidxu.dts
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -109,10 +109,10 @@
assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>;
- assigned-clock-rates = <0>,
- <0>,
- <96000000>,
- <19200000>;
+ assigned-clock-rates = <0>,
+ <0>,
+ <96000000>,
+ <19200000>;
};
&cpu0_thermal {
@@ -170,7 +170,7 @@
intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpx1 4 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
clock-names = "refclk";
diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
index 481ee99..d0aa184 100644
--- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
@@ -3,7 +3,7 @@
* Exynos5410 SoC pin-mux and pin-config device tree source
*
* Copyright (c) 2013 Hardkernel Co., Ltd.
- * http://www.hardkernel.com
+ * https://www.hardkernel.com
*/
#include <dt-bindings/pinctrl/samsung.h>
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index dffa5e3..2a3ade7 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG SMDK5410 board device tree source
+ * Samsung SMDK5410 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -10,7 +10,7 @@
#include "exynos5410.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
- model = "Samsung SMDK5410 board based on EXYNOS5410";
+ model = "Samsung SMDK5410 board based on Exynos5410";
compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
memory@40000000 {
@@ -29,6 +29,13 @@
#clock-cells = <0>;
};
+ pmic_ap_clk: pmic-ap-clk {
+ /* Workaround for missing PMIC and its clock */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
firmware@2037000 {
compatible = "samsung,secure-firmware";
reg = <0x02037000 0x1000>;
@@ -79,6 +86,11 @@
};
};
+&rtc {
+ clocks = <&clock CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
+};
+
&sromc {
pinctrl-names = "default";
pinctrl-0 = <&srom_ctl>, <&srom_ebi>;
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index d077373..584ce62 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -1,12 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5410 SoC device tree source
+ * Samsung Exynos5410 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
- * EXYNOS5410 based board files can include this file and provide
+ * Samsung Exynos5410 SoC device nodes are listed in this file.
+ * Exynos5410 based board files can include this file and provide
* values for board specfic bindings.
*/
@@ -189,42 +189,34 @@
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
};
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
+ pdma0: pdma@121a0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121a0000 0x1000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
- pdma0: pdma@121a0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x121a0000 0x1000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
-
- pdma1: pdma@121b0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x121b0000 0x1000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
+ pdma1: pdma@121b0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121b0000 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
};
audi2s0: i2s@3830000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x03830000 0x100>;
- dmas = <&pdma0 10
- &pdma0 9
- &pdma0 8>;
+ dmas = <&pdma0 10>,
+ <&pdma0 9>,
+ <&pdma0 8>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
@@ -246,16 +238,16 @@
#include "exynos5420-trip-points.dtsi"
};
cpu1_thermal: cpu1-thermal {
- thermal-sensors = <&tmu_cpu1>;
- #include "exynos5420-trip-points.dtsi"
+ thermal-sensors = <&tmu_cpu1>;
+ #include "exynos5420-trip-points.dtsi"
};
cpu2_thermal: cpu2-thermal {
- thermal-sensors = <&tmu_cpu2>;
- #include "exynos5420-trip-points.dtsi"
+ thermal-sensors = <&tmu_cpu2>;
+ #include "exynos5420-trip-points.dtsi"
};
cpu3_thermal: cpu3-thermal {
- thermal-sensors = <&tmu_cpu3>;
- #include "exynos5420-trip-points.dtsi"
+ thermal-sensors = <&tmu_cpu3>;
+ #include "exynos5420-trip-points.dtsi"
};
};
};
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 53bf988..3d9b93d 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -15,7 +15,7 @@
#include <dt-bindings/clock/samsung,s2mps11.h>
/ {
- model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
+ model = "Insignal Arndale Octa evaluation board based on Exynos5420";
compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
memory@20000000 {
@@ -584,6 +584,7 @@
regulator-name = "PVDD_G3DS_1V0";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
+ regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
@@ -672,7 +673,7 @@
};
buck2_reg: BUCK2 {
- regulator-name = "vdd_arm";
+ regulator-name = "PVDD_ARM_1V0";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
@@ -697,6 +698,7 @@
regulator-name = "PVDD_G3D_1V0";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
+ regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 0ee6e92..58d1c54 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5420 SoC cpu device tree source
+ * Samsung Exynos5420 SoC cpu device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 9eb48ca..2bcbdf8 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -1065,6 +1065,10 @@
status = "okay";
};
+&timer {
+ arm,cpu-registers-not-fw-configured;
+};
+
&tmu_cpu0 {
vtmu-supply = <&ldo10_reg>;
};
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 8240e51..4e49d80 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG SMDK5420 board device tree source
+ * Samsung SMDK5420 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -9,10 +9,11 @@
/dts-v1/;
#include "exynos5420.dtsi"
#include "exynos5420-cpus.dtsi"
+#include <dt-bindings/clock/samsung,s2mps11.h>
#include <dt-bindings/gpio/gpio.h>
/ {
- model = "Samsung SMDK5420 board based on EXYNOS5420";
+ model = "Samsung SMDK5420 board based on Exynos5420";
compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5";
memory@20000000 {
@@ -32,40 +33,31 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vdd: fixed-regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd-supply";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- dbvdd: fixed-regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "dbvdd-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- spkvdd: fixed-regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "spkvdd-supply";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ vdd: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-supply";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
};
- usb300_vbus_reg: regulator-usb300 {
+ dbvdd: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "dbvdd-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ spkvdd: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "spkvdd-supply";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ usb300_vbus_reg: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "VBUS0";
regulator-min-microvolt = <5000000>;
@@ -76,7 +68,7 @@
enable-active-high;
};
- usb301_vbus_reg: regulator-usb301 {
+ usb301_vbus_reg: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "VBUS1";
regulator-min-microvolt = <5000000>;
@@ -410,6 +402,8 @@
&rtc {
status = "okay";
+ clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
};
&usbdrd_phy0 {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 7d51e0f..83580f0 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1,12 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5420 SoC device tree source
+ * Samsung Exynos5420 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * SAMSUNG EXYNOS5420 SoC device nodes are listed in this file.
- * EXYNOS5420 based board files can include this file and provide
+ * Samsung Exynos5420 SoC device nodes are listed in this file.
+ * Exynos5420 based board files can include this file and provide
* values for board specfic bindings.
*/
@@ -48,62 +48,62 @@
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1250000>;
+ opp-microvolt = <1250000 1250000 1500000>;
clock-latency-ns = <140000>;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
- opp-microvolt = <1212500>;
+ opp-microvolt = <1212500 1212500 1500000>;
clock-latency-ns = <140000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
- opp-microvolt = <1175000>;
+ opp-microvolt = <1175000 1175000 1500000>;
clock-latency-ns = <140000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <1137500>;
+ opp-microvolt = <1137500 1137500 1500000>;
clock-latency-ns = <140000>;
};
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
- opp-microvolt = <1112500>;
+ opp-microvolt = <1112500 1112500 1500000>;
clock-latency-ns = <140000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
- opp-microvolt = <1062500>;
+ opp-microvolt = <1062500 1062500 1500000>;
clock-latency-ns = <140000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1037500>;
+ opp-microvolt = <1037500 1037500 1500000>;
clock-latency-ns = <140000>;
};
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
- opp-microvolt = <1012500>;
+ opp-microvolt = <1012500 1012500 1500000>;
clock-latency-ns = <140000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = < 987500>;
+ opp-microvolt = < 987500 987500 1500000>;
clock-latency-ns = <140000>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
- opp-microvolt = < 962500>;
+ opp-microvolt = < 962500 962500 1500000>;
clock-latency-ns = <140000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = < 937500>;
+ opp-microvolt = < 937500 937500 1500000>;
clock-latency-ns = <140000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = < 912500>;
+ opp-microvolt = < 912500 912500 1500000>;
clock-latency-ns = <140000>;
};
};
@@ -175,7 +175,7 @@
};
clock: clock-controller@10010000 {
- compatible = "samsung,exynos5420-clock";
+ compatible = "samsung,exynos5420-clock", "syscon";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
@@ -237,6 +237,32 @@
status = "disabled";
};
+ dmc: memory-controller@10c20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>, <16 1>;
+ interrupt-names = "drex_0", "drex_1";
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MCLK_CDREX>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mclk_cdrex";
+ samsung,syscon-clk = <&clock>;
+ status = "disabled";
+ };
+
nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>;
@@ -273,6 +299,54 @@
status = "disabled";
};
+ ppmu_dmc0_0: ppmu@10d00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+ ppmu_dmc0_1: ppmu@10d10000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d10000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
+ event-name = "ppmu-event3-dmc0_1";
+ };
+ };
+ };
+
+ ppmu_dmc1_0: ppmu@10d60000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d60000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
+ event-name = "ppmu-event3-dmc1_0";
+ };
+ };
+ };
+
+ ppmu_dmc1_1: ppmu@10d70000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d70000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
+ event-name = "ppmu-event3-dmc1_1";
+ };
+ };
+ };
+
gsc_pd: power-domain@10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
@@ -359,84 +433,76 @@
power-domains = <&mau_pd>;
};
- amba {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
+ adma: adma@3880000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x03880000 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_audss EXYNOS_ADMA>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <6>;
+ #dma-requests = <16>;
+ power-domains = <&mau_pd>;
+ };
- adma: adma@3880000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x03880000 0x1000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock_audss EXYNOS_ADMA>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <6>;
- #dma-requests = <16>;
- power-domains = <&mau_pd>;
- };
+ pdma0: pdma@121a0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121A0000 0x1000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
- pdma0: pdma@121a0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x121A0000 0x1000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
+ pdma1: pdma@121b0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x121B0000 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
- pdma1: pdma@121b0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x121B0000 0x1000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_PDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
+ mdma0: mdma@10800000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x10800000 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_MDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <1>;
+ };
- mdma0: mdma@10800000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x10800000 0x1000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_MDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
- };
-
- mdma1: mdma@11c10000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x11C10000 0x1000>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clock CLK_MDMA1>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <1>;
- /*
- * MDMA1 can support both secure and non-secure
- * AXI transactions. When this is enabled in
- * the kernel for boards that run in secure
- * mode, we are getting imprecise external
- * aborts causing the kernel to oops.
- */
- status = "disabled";
- };
+ mdma1: mdma@11c10000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x11C10000 0x1000>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock CLK_MDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <1>;
+ /*
+ * MDMA1 can support both secure and non-secure
+ * AXI transactions. When this is enabled in
+ * the kernel for boards that run in secure
+ * mode, we are getting imprecise external
+ * aborts causing the kernel to oops.
+ */
+ status = "disabled";
};
i2s0: i2s@3830000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x03830000 0x100>;
- dmas = <&adma 0
- &adma 2
- &adma 1>;
+ dmas = <&adma 0>,
+ <&adma 2>,
+ <&adma 1>;
dma-names = "tx", "rx", "tx-sec";
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_I2S_BUS>,
@@ -455,8 +521,8 @@
i2s1: i2s@12d60000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D60000 0x100>;
- dmas = <&pdma1 12
- &pdma1 11>;
+ dmas = <&pdma1 12>,
+ <&pdma1 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
clock-names = "iis", "i2s_opclk0";
@@ -471,8 +537,8 @@
i2s2: i2s@12d70000 {
compatible = "samsung,exynos5420-i2s";
reg = <0x12D70000 0x100>;
- dmas = <&pdma0 12
- &pdma0 11>;
+ dmas = <&pdma0 12>,
+ <&pdma0 11>;
dma-names = "tx", "rx";
clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
clock-names = "iis", "i2s_opclk0";
@@ -670,6 +736,56 @@
iommus = <&sysmmu_gscl1>;
};
+ gpu: gpu@11800000 {
+ compatible = "samsung,exynos5420-mali", "arm,mali-t628";
+ reg = <0x11800000 0x5000>;
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+
+ clocks = <&clock CLK_G3D>;
+ clock-names = "core";
+ power-domains = <&g3d_pd>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ status = "disabled";
+ #cooling-cells = <2>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-177000000 {
+ opp-hz = /bits/ 64 <177000000>;
+ opp-microvolt = <812500>;
+ };
+ opp-266000000 {
+ opp-hz = /bits/ 64 <266000000>;
+ opp-microvolt = <862500>;
+ };
+ opp-350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ opp-microvolt = <912500>;
+ };
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ opp-microvolt = <962500>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-543000000 {
+ opp-hz = /bits/ 64 <543000000>;
+ opp-microvolt = <1037500>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1150000>;
+ };
+ };
+ };
+
scaler_0: scaler@12800000 {
compatible = "samsung,exynos5420-scaler";
reg = <0x12800000 0x1294>;
@@ -968,7 +1084,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
clock-names = "bus";
- operating-points-v2 = <&bus_wcore_opp_table>;
status = "disabled";
};
@@ -976,7 +1091,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK100_NOC>;
clock-names = "bus";
- operating-points-v2 = <&bus_noc_opp_table>;
status = "disabled";
};
@@ -984,7 +1098,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
clock-names = "bus";
- operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
};
@@ -992,7 +1105,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
clock-names = "bus";
- operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
};
@@ -1000,7 +1112,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
clock-names = "bus";
- operating-points-v2 = <&bus_fsys2_opp_table>;
status = "disabled";
};
@@ -1008,7 +1119,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333>;
clock-names = "bus";
- operating-points-v2 = <&bus_mfc_opp_table>;
status = "disabled";
};
@@ -1016,7 +1126,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266>;
clock-names = "bus";
- operating-points-v2 = <&bus_gen_opp_table>;
status = "disabled";
};
@@ -1024,7 +1133,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK66>;
clock-names = "bus";
- operating-points-v2 = <&bus_peri_opp_table>;
status = "disabled";
};
@@ -1032,7 +1140,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333_G2D>;
clock-names = "bus";
- operating-points-v2 = <&bus_g2d_opp_table>;
status = "disabled";
};
@@ -1040,7 +1147,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266_G2D>;
clock-names = "bus";
- operating-points-v2 = <&bus_g2d_acp_opp_table>;
status = "disabled";
};
@@ -1048,7 +1154,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
clock-names = "bus";
- operating-points-v2 = <&bus_jpeg_opp_table>;
status = "disabled";
};
@@ -1056,7 +1161,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK166>;
clock-names = "bus";
- operating-points-v2 = <&bus_jpeg_apb_opp_table>;
status = "disabled";
};
@@ -1064,7 +1168,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
clock-names = "bus";
- operating-points-v2 = <&bus_disp1_fimd_opp_table>;
status = "disabled";
};
@@ -1072,7 +1175,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
clock-names = "bus";
- operating-points-v2 = <&bus_disp1_opp_table>;
status = "disabled";
};
@@ -1080,7 +1182,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
clock-names = "bus";
- operating-points-v2 = <&bus_gscl_opp_table>;
status = "disabled";
};
@@ -1088,252 +1189,8 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
clock-names = "bus";
- operating-points-v2 = <&bus_mscl_opp_table>;
status = "disabled";
};
-
- bus_wcore_opp_table: opp_table2 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <84000000>;
- opp-microvolt = <925000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <111000000>;
- opp-microvolt = <950000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <222000000>;
- opp-microvolt = <950000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <333000000>;
- opp-microvolt = <950000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <987500>;
- };
- };
-
- bus_noc_opp_table: opp_table3 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <67000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <75000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <86000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <100000000>;
- };
- };
-
- bus_fsys_apb_opp_table: opp_table4 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <200000000>;
- };
- };
-
- bus_fsys2_opp_table: opp_table5 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <75000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <100000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <150000000>;
- };
- };
-
- bus_mfc_opp_table: opp_table6 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <96000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <111000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <167000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <222000000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <333000000>;
- };
- };
-
- bus_gen_opp_table: opp_table7 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <89000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <133000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <178000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <267000000>;
- };
- };
-
- bus_peri_opp_table: opp_table8 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <67000000>;
- };
- };
-
- bus_g2d_opp_table: opp_table9 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <84000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <167000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <222000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <300000000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <333000000>;
- };
- };
-
- bus_g2d_acp_opp_table: opp_table10 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <67000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <133000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <178000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <267000000>;
- };
- };
-
- bus_jpeg_opp_table: opp_table11 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <75000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <150000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <200000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <300000000>;
- };
- };
-
- bus_jpeg_apb_opp_table: opp_table12 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <84000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <111000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <134000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <167000000>;
- };
- };
-
- bus_disp1_fimd_opp_table: opp_table13 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <120000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <200000000>;
- };
- };
-
- bus_disp1_opp_table: opp_table14 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <120000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <200000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <300000000>;
- };
- };
-
- bus_gscl_opp_table: opp_table15 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <150000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <200000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <300000000>;
- };
- };
-
- bus_mscl_opp_table: opp_table16 {
- compatible = "operating-points-v2";
-
- opp00 {
- opp-hz = /bits/ 64 <84000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <167000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <222000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <333000000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <400000000>;
- };
- };
};
thermal-zones {
@@ -1342,20 +1199,20 @@
#include "exynos5420-trip-points.dtsi"
};
cpu1_thermal: cpu1-thermal {
- thermal-sensors = <&tmu_cpu1>;
- #include "exynos5420-trip-points.dtsi"
+ thermal-sensors = <&tmu_cpu1>;
+ #include "exynos5420-trip-points.dtsi"
};
cpu2_thermal: cpu2-thermal {
- thermal-sensors = <&tmu_cpu2>;
- #include "exynos5420-trip-points.dtsi"
+ thermal-sensors = <&tmu_cpu2>;
+ #include "exynos5420-trip-points.dtsi"
};
cpu3_thermal: cpu3-thermal {
- thermal-sensors = <&tmu_cpu3>;
- #include "exynos5420-trip-points.dtsi"
+ thermal-sensors = <&tmu_cpu3>;
+ #include "exynos5420-trip-points.dtsi"
};
gpu_thermal: gpu-thermal {
- thermal-sensors = <&tmu_gpu>;
- #include "exynos5420-trip-points.dtsi"
+ thermal-sensors = <&tmu_gpu>;
+ #include "exynos5420-trip-points.dtsi"
};
};
};
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index e4a5857..4b641b9 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5422 SoC cpu device tree source
+ * Samsung Exynos5422 SoC cpu device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@@ -31,6 +31,7 @@
operating-points-v2 = <&cluster_a7_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
+ dynamic-power-coefficient = <90>;
};
cpu1: cpu@101 {
@@ -43,6 +44,7 @@
operating-points-v2 = <&cluster_a7_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
+ dynamic-power-coefficient = <90>;
};
cpu2: cpu@102 {
@@ -55,6 +57,7 @@
operating-points-v2 = <&cluster_a7_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
+ dynamic-power-coefficient = <90>;
};
cpu3: cpu@103 {
@@ -67,6 +70,7 @@
operating-points-v2 = <&cluster_a7_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
+ dynamic-power-coefficient = <90>;
};
cpu4: cpu@0 {
@@ -79,6 +83,7 @@
operating-points-v2 = <&cluster_a15_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <310>;
};
cpu5: cpu@1 {
@@ -91,6 +96,7 @@
operating-points-v2 = <&cluster_a15_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <310>;
};
cpu6: cpu@2 {
@@ -103,6 +109,7 @@
operating-points-v2 = <&cluster_a15_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <310>;
};
cpu7: cpu@3 {
@@ -115,6 +122,7 @@
operating-points-v2 = <&cluster_a15_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <310>;
};
};
};
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 9e64a4a..d51c1d8 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -34,6 +34,355 @@
clock-frequency = <24000000>;
};
};
+
+ bus_wcore_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+
+ /* derived from 532MHz MPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <88700000>;
+ opp-microvolt = <925000 925000 1400000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <133000000>;
+ opp-microvolt = <950000 950000 1400000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <177400000>;
+ opp-microvolt = <950000 950000 1400000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <266000000>;
+ opp-microvolt = <950000 950000 1400000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <532000000>;
+ opp-microvolt = <1000000 1000000 1400000>;
+ };
+ };
+
+ bus_noc_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <66600000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <74000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <83250000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <111000000>;
+ };
+ };
+
+ bus_fsys_apb_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <111000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <222000000>;
+ };
+ };
+
+ bus_fsys2_opp_table: opp_table5 {
+ compatible = "operating-points-v2";
+
+ /* derived from 600MHz DPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <75000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <120000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ };
+
+ bus_mfc_opp_table: opp_table6 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <83250000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <111000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <166500000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <222000000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <333000000>;
+ };
+ };
+
+ bus_gen_opp_table: opp_table7 {
+ compatible = "operating-points-v2";
+
+ /* derived from 532MHz MPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <88700000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <133000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <178000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <266000000>;
+ };
+ };
+
+ bus_peri_opp_table: opp_table8 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <66600000>;
+ };
+ };
+
+ bus_g2d_opp_table: opp_table9 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <83250000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <111000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <166500000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <222000000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <333000000>;
+ };
+ };
+
+ bus_g2d_acp_opp_table: opp_table10 {
+ compatible = "operating-points-v2";
+
+ /* derived from 532MHz MPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <66500000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <133000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <178000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <266000000>;
+ };
+ };
+
+ bus_jpeg_opp_table: opp_table11 {
+ compatible = "operating-points-v2";
+
+ /* derived from 600MHz DPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <75000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <150000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <300000000>;
+ };
+ };
+
+ bus_jpeg_apb_opp_table: opp_table12 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <83250000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <111000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <133000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <166500000>;
+ };
+ };
+
+ bus_disp1_fimd_opp_table: opp_table13 {
+ compatible = "operating-points-v2";
+
+ /* derived from 600MHz DPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <120000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ };
+
+ bus_disp1_opp_table: opp_table14 {
+ compatible = "operating-points-v2";
+
+ /* derived from 600MHz DPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <120000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <300000000>;
+ };
+ };
+
+ bus_gscl_opp_table: opp_table15 {
+ compatible = "operating-points-v2";
+
+ /* derived from 600MHz DPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <150000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <300000000>;
+ };
+ };
+
+ bus_mscl_opp_table: opp_table16 {
+ compatible = "operating-points-v2";
+
+ /* derived from 666MHz CPLL */
+ opp00 {
+ opp-hz = /bits/ 64 <84000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <167000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <222000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <333000000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <666000000>;
+ };
+ };
+
+ dmc_opp_table: opp_table17 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <165000000>;
+ opp-microvolt = <875000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <206000000>;
+ opp-microvolt = <875000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <275000000>;
+ opp-microvolt = <875000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <413000000>;
+ opp-microvolt = <887500>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <543000000>;
+ opp-microvolt = <937500>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <633000000>;
+ opp-microvolt = <1012500>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <728000000>;
+ opp-microvolt = <1037500>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <825000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
+ samsung_K3QF2F20DB: lpddr3 {
+ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
+ density = <16384>;
+ io-width = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tRFC-min-tck = <17>;
+ tRRD-min-tck = <2>;
+ tRPab-min-tck = <2>;
+ tRPpb-min-tck = <2>;
+ tRCD-min-tck = <3>;
+ tRC-min-tck = <6>;
+ tRAS-min-tck = <5>;
+ tWTR-min-tck = <2>;
+ tWR-min-tck = <7>;
+ tRTP-min-tck = <2>;
+ tW2W-C2C-min-tck = <0>;
+ tR2R-C2C-min-tck = <0>;
+ tWL-min-tck = <8>;
+ tDQSCK-min-tck = <5>;
+ tRL-min-tck = <14>;
+ tFAW-min-tck = <5>;
+ tXSR-min-tck = <12>;
+ tXP-min-tck = <2>;
+ tCKE-min-tck = <2>;
+ tCKESR-min-tck = <2>;
+ tMRD-min-tck = <5>;
+
+ timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
+ compatible = "jedec,lpddr3-timings";
+ /* workaround: 'reg' shows max-freq */
+ reg = <800000000>;
+ min-freq = <100000000>;
+ tRFC = <65000>;
+ tRRD = <6000>;
+ tRPab = <12000>;
+ tRPpb = <12000>;
+ tRCD = <10000>;
+ tRC = <33750>;
+ tRAS = <23000>;
+ tWTR = <3750>;
+ tWR = <7500>;
+ tRTP = <3750>;
+ tW2W-C2C = <0>;
+ tR2R-C2C = <0>;
+ tFAW = <25000>;
+ tXSR = <70000>;
+ tXP = <3750>;
+ tCKE = <3750>;
+ tCKESR = <3750>;
+ tMRD = <7000>;
+ };
+ };
};
&adc {
@@ -42,6 +391,7 @@
};
&bus_wcore {
+ operating-points-v2 = <&bus_wcore_opp_table>;
devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
<&nocp_mem1_0>, <&nocp_mem1_1>;
vdd-supply = <&buck3_reg>;
@@ -50,76 +400,85 @@
};
&bus_noc {
+ operating-points-v2 = <&bus_noc_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys_apb {
- devfreq = <&bus_wcore>;
- status = "okay";
-};
-
-&bus_fsys {
+ operating-points-v2 = <&bus_fsys_apb_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys2 {
+ operating-points-v2 = <&bus_fsys2_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_mfc {
+ operating-points-v2 = <&bus_mfc_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_gen {
+ operating-points-v2 = <&bus_gen_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_peri {
+ operating-points-v2 = <&bus_peri_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_g2d {
+ operating-points-v2 = <&bus_g2d_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_g2d_acp {
+ operating-points-v2 = <&bus_g2d_acp_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_jpeg {
+ operating-points-v2 = <&bus_jpeg_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_jpeg_apb {
+ operating-points-v2 = <&bus_jpeg_apb_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_disp1_fimd {
+ operating-points-v2 = <&bus_disp1_fimd_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_disp1 {
+ operating-points-v2 = <&bus_disp1_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_gscl_scaler {
+ operating-points-v2 = <&bus_gscl_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_mscl {
+ operating-points-v2 = <&bus_mscl_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
@@ -132,6 +491,15 @@
cpu-supply = <&buck2_reg>;
};
+&dmc {
+ devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
+ <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
+ device-handle = <&samsung_K3QF2F20DB>;
+ operating-points-v2 = <&dmc_opp_table>;
+ vdd-supply = <&buck1_reg>;
+ status = "okay";
+};
+
&hsi2c_4 {
status = "okay";
@@ -500,6 +868,8 @@
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&buck3_reg>;
+ regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -512,6 +882,8 @@
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&buck2_reg>;
+ regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
@@ -522,8 +894,8 @@
regulator-name = "vdd_g3d";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
- regulator-always-on;
regulator-boot-on;
+ regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
@@ -634,6 +1006,22 @@
};
};
+&ppmu_dmc0_0 {
+ status = "okay";
+};
+
+&ppmu_dmc0_1 {
+ status = "okay";
+};
+
+&ppmu_dmc1_0 {
+ status = "okay";
+};
+
+&ppmu_dmc1_1 {
+ status = "okay";
+};
+
&tmu_cpu0 {
vtmu-supply = <&ldo7_reg>;
};
@@ -654,6 +1042,11 @@
vtmu-supply = <&ldo7_reg>;
};
+&gpu {
+ mali-supply = <&buck4_reg>;
+ status = "okay";
+};
+
&rtc {
status = "okay";
clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
index fce5a45..88f5c15 100644
--- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts
@@ -72,14 +72,14 @@
*/
map1 {
trip = <&cpu0_alert1>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -116,14 +116,14 @@
};
map1 {
trip = <&cpu1_alert1>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -160,14 +160,14 @@
};
map1 {
trip = <&cpu2_alert1>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -204,14 +204,44 @@
};
map1 {
trip = <&cpu3_alert1>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
+ };
+ };
+ };
+ gpu_thermal: gpu-thermal {
+ thermal-sensors = <&tmu_gpu 0>;
+ trips {
+ gpu_alert0: gpu-alert-0 {
+ temperature = <70000>;
+ hysteresis = <10000>;
+ type = "active";
+ };
+ gpu_alert1: gpu-alert-1 {
+ temperature = <85000>;
+ hysteresis = <10000>;
+ type = "active";
+ };
+ gpu_crit0: gpu-crit-0 {
+ temperature = <120000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device = <&gpu 0 2>;
+ };
+ map1 {
+ trip = <&gpu_alert1>;
+ cooling-device = <&gpu 3 6>;
};
};
};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
index c3c2d85..b5ec4f4 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
@@ -29,30 +29,6 @@
"HiFi Playback", "Mixer DAI TX",
"Mixer DAI RX", "HiFi Capture";
- assigned-clocks = <&clock CLK_MOUT_EPLL>,
- <&clock CLK_MOUT_MAU_EPLL>,
- <&clock CLK_MOUT_USER_MAU_EPLL>,
- <&clock_audss EXYNOS_MOUT_AUDSS>,
- <&clock_audss EXYNOS_MOUT_I2S>,
- <&clock_audss EXYNOS_DOUT_SRP>,
- <&clock_audss EXYNOS_DOUT_AUD_BUS>,
- <&clock_audss EXYNOS_DOUT_I2S>;
-
- assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
- <&clock CLK_MOUT_EPLL>,
- <&clock CLK_MOUT_MAU_EPLL>,
- <&clock CLK_MAU_EPLL>,
- <&clock_audss EXYNOS_MOUT_AUDSS>;
-
- assigned-clock-rates = <0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <196608001>,
- <(196608002 / 2)>,
- <196608000>;
-
cpu {
sound-dai = <&i2s0 0>, <&i2s0 1>;
};
@@ -62,13 +38,6 @@
};
};
-&clock_audss {
- assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
- <&clock CLK_FOUT_EPLL>;
- assigned-clock-rates = <(196608000 / 256)>,
- <196608000>;
-};
-
&hsi2c_5 {
status = "okay";
max98090: max98090@10 {
@@ -84,6 +53,31 @@
&i2s0 {
status = "okay";
- assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
- assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
+ assigned-clocks = <&clock CLK_MOUT_EPLL>,
+ <&clock CLK_MOUT_MAU_EPLL>,
+ <&clock CLK_MOUT_USER_MAU_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_MOUT_I2S>,
+ <&i2s0 CLK_I2S_RCLK_SRC>,
+ <&clock_audss EXYNOS_DOUT_SRP>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>,
+ <&clock_audss EXYNOS_DOUT_I2S>;
+
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+ <&clock CLK_MOUT_EPLL>,
+ <&clock CLK_MOUT_MAU_EPLL>,
+ <&clock CLK_MAU_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+
+ assigned-clock-rates = <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <196608001>,
+ <(196608002 / 2)>,
+ <196608000>;
+
};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 8388720..5da2d81 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -107,7 +107,7 @@
/*
* When reaching cpu0_alert3, reduce CPU
* by 2 steps. On Exynos5422/5800 that would
- * be: 1600 MHz and 1100 MHz.
+ * (usually) be: 1800 MHz and 1200 MHz.
*/
map3 {
trip = <&cpu0_alert3>;
@@ -122,19 +122,19 @@
};
/*
* When reaching cpu0_alert4, reduce CPU
- * further, down to 600 MHz (12 steps for big,
- * 7 steps for LITTLE).
+ * further, down to 600 MHz (14 steps for big,
+ * 8 steps for LITTLE).
*/
- map4 {
+ cpu0_cooling_map4: map4 {
trip = <&cpu0_alert4>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -198,16 +198,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
- map4 {
+ cpu1_cooling_map4: map4 {
trip = <&cpu1_alert4>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -271,16 +271,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
- map4 {
+ cpu2_cooling_map4: map4 {
trip = <&cpu2_alert4>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
};
};
};
@@ -344,16 +344,75 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
- map4 {
+ cpu3_cooling_map4: map4 {
trip = <&cpu3_alert4>;
- cooling-device = <&cpu0 3 7>,
- <&cpu1 3 7>,
- <&cpu2 3 7>,
- <&cpu3 3 7>,
- <&cpu4 3 12>,
- <&cpu5 3 12>,
- <&cpu6 3 12>,
- <&cpu7 3 12>;
+ cooling-device = <&cpu0 3 8>,
+ <&cpu1 3 8>,
+ <&cpu2 3 8>,
+ <&cpu3 3 8>,
+ <&cpu4 3 14>,
+ <&cpu5 3 14>,
+ <&cpu6 3 14>,
+ <&cpu7 3 14>;
+ };
+ };
+ };
+ gpu_thermal: gpu-thermal {
+ thermal-sensors = <&tmu_gpu 0>;
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+ trips {
+ gpu_alert0: gpu-alert-0 {
+ temperature = <50000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+ gpu_alert1: gpu-alert-1 {
+ temperature = <60000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+ gpu_alert2: gpu-alert-2 {
+ temperature = <70000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+ gpu_crit0: gpu-crit-0 {
+ temperature = <120000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ gpu_alert3: gpu-alert-3 {
+ temperature = <70000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ gpu_alert4: gpu-alert-4 {
+ temperature = <85000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device = <&fan0 0 1>;
+ };
+ map1 {
+ trip = <&gpu_alert1>;
+ cooling-device = <&fan0 1 2>;
+ };
+ map2 {
+ trip = <&gpu_alert2>;
+ cooling-device = <&fan0 2 3>;
+ };
+ map3 {
+ trip = <&gpu_alert3>;
+ cooling-device = <&gpu 0 2>;
+ };
+ map4 {
+ trip = <&gpu_alert4>;
+ cooling-device = <&gpu 3 6>;
};
};
};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index c19b5a5..98feeca 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -26,6 +26,68 @@
status = "disabled";
};
+&chipid {
+ samsung,asv-bin = <2>;
+};
+
+/*
+ * Odroid XU3-Lite board uses SoC revision with lower maximum frequencies
+ * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
+ * Therefore we need to update OPPs tables and thermal maps accordingly.
+ */
+&cluster_a15_opp_table {
+ /delete-node/opp-2000000000;
+ /delete-node/opp-1900000000;
+};
+
+&cluster_a7_opp_table {
+ /delete-node/opp-1400000000;
+};
+
+&cpu0_cooling_map4 {
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
+};
+
+&cpu1_cooling_map4 {
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
+};
+
+&cpu2_cooling_map4 {
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
+};
+
+&cpu3_cooling_map4 {
+ cooling-device = <&cpu0 3 7>,
+ <&cpu1 3 7>,
+ <&cpu2 3 7>,
+ <&cpu3 3 7>,
+ <&cpu4 3 12>,
+ <&cpu5 3 12>,
+ <&cpu6 3 12>,
+ <&cpu7 3 12>;
+};
+
&pwm {
/*
* PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
index 1fc3544..4ef0dbc 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts
@@ -35,30 +35,6 @@
samsung,audio-routing = "I2S Playback", "Mixer DAI TX";
- assigned-clocks = <&clock CLK_MOUT_EPLL>,
- <&clock CLK_MOUT_MAU_EPLL>,
- <&clock CLK_MOUT_USER_MAU_EPLL>,
- <&clock_audss EXYNOS_MOUT_AUDSS>,
- <&clock_audss EXYNOS_MOUT_I2S>,
- <&clock_audss EXYNOS_DOUT_SRP>,
- <&clock_audss EXYNOS_DOUT_AUD_BUS>,
- <&clock_audss EXYNOS_DOUT_I2S>;
-
- assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
- <&clock CLK_MOUT_EPLL>,
- <&clock CLK_MOUT_MAU_EPLL>,
- <&clock CLK_MAU_EPLL>,
- <&clock_audss EXYNOS_MOUT_AUDSS>;
-
- assigned-clock-rates = <0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <196608001>,
- <(196608002 / 2)>,
- <196608000>;
-
cpu {
sound-dai = <&i2s0 0>, <&i2s0 1>;
};
@@ -69,17 +45,35 @@
};
};
-&clock_audss {
- assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
- <&clock CLK_FOUT_EPLL>;
- assigned-clock-rates = <(196608000 / 256)>,
- <196608000>;
-};
-
&i2s0 {
status = "okay";
- assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
- assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
+
+ assigned-clocks = <&clock CLK_MOUT_EPLL>,
+ <&clock CLK_MOUT_MAU_EPLL>,
+ <&clock CLK_MOUT_USER_MAU_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_MOUT_I2S>,
+ <&i2s0 CLK_I2S_RCLK_SRC>,
+ <&clock_audss EXYNOS_DOUT_SRP>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>,
+ <&clock_audss EXYNOS_DOUT_I2S>;
+
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+ <&clock CLK_MOUT_EPLL>,
+ <&clock CLK_MOUT_MAU_EPLL>,
+ <&clock CLK_MAU_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+
+ assigned-clock-rates = <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <196608001>,
+ <(196608002 / 2)>,
+ <196608000>;
};
&pwm {
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 9c3b63b..8aa5117 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -45,49 +45,49 @@
status = "disabled";
};
+ timer: timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ };
+
soc: soc {
- sysram@2020000 {
+ sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x54000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x54000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@53000 {
+ smp-sram@53000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x53000 0x1000>;
};
};
- mct: mct@101c0000 {
+ mct: timer@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101c0000 0xb00>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
- <8>, <9>, <10>, <11>;
-
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0 &combiner 23 3>,
- <1 &combiner 23 4>,
- <2 &combiner 25 2>,
- <3 &combiner 25 3>,
- <4 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
- <5 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>,
- <6 &gic 0 122 IRQ_TYPE_LEVEL_HIGH>,
- <7 &gic 0 123 IRQ_TYPE_LEVEL_HIGH>,
- <8 &gic 0 128 IRQ_TYPE_LEVEL_HIGH>,
- <9 &gic 0 129 IRQ_TYPE_LEVEL_HIGH>,
- <10 &gic 0 130 IRQ_TYPE_LEVEL_HIGH>,
- <11 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
- };
+ interrupts-extended = <&combiner 23 3>,
+ <&combiner 23 4>,
+ <&combiner 25 2>,
+ <&combiner 25 3>,
+ <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@101d0000 {
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 4398f2d..60ab0ef 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -156,6 +156,15 @@
assigned-clock-parents = <&clock CLK_MAU_EPLL>;
};
+/*
+ * Peach Pi board uses SoC revision with lower maximum frequency for A7 cores
+ * (1.3 GHz instead of 1.4 GHz) than Odroid XU3/XU4 boards. Thus we need to
+ * update A7 OPPs table accordingly.
+ */
+&cluster_a7_opp_table {
+ /delete-node/opp-1400000000;
+};
+
&cpu0 {
cpu-supply = <&buck2_reg>;
};
@@ -257,6 +266,8 @@
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12500>;
+ regulator-coupled-with = <&buck3_reg>;
+ regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -269,6 +280,8 @@
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12500>;
+ regulator-coupled-with = <&buck2_reg>;
+ regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -1034,6 +1047,10 @@
status = "okay";
};
+&timer {
+ arm,cpu-registers-not-fw-configured;
+};
+
&tmu_cpu0 {
vtmu-supply = <&ldo10_reg>;
};
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index de639ee..526729d 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -1,12 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG EXYNOS5800 SoC device tree source
+ * Samsung Exynos5800 SoC device tree source
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * SAMSUNG EXYNOS5800 SoC device nodes are listed in this file.
- * EXYNOS5800 based board files can include this file and provide
+ * Samsung Exynos5800 SoC device nodes are listed in this file.
+ * Exynos5800 based board files can include this file and provide
* values for board specfic bindings.
*/
@@ -17,71 +17,91 @@
};
&clock {
- compatible = "samsung,exynos5800-clock";
+ compatible = "samsung,exynos5800-clock", "syscon";
};
&cluster_a15_opp_table {
+ opp-2000000000 {
+ opp-hz = /bits/ 64 <2000000000>;
+ opp-microvolt = <1312500 1312500 1500000>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1900000000 {
+ opp-hz = /bits/ 64 <1900000000>;
+ opp-microvolt = <1262500 1262500 1500000>;
+ clock-latency-ns = <140000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1237500 1237500 1500000>;
+ clock-latency-ns = <140000>;
+ };
opp-1700000000 {
- opp-microvolt = <1250000>;
+ opp-microvolt = <1250000 1250000 1500000>;
};
opp-1600000000 {
- opp-microvolt = <1250000>;
+ opp-microvolt = <1250000 1250000 1500000>;
};
opp-1500000000 {
- opp-microvolt = <1100000>;
+ opp-microvolt = <1100000 1100000 1500000>;
};
opp-1400000000 {
- opp-microvolt = <1100000>;
+ opp-microvolt = <1100000 1100000 1500000>;
};
opp-1300000000 {
- opp-microvolt = <1100000>;
+ opp-microvolt = <1100000 1100000 1500000>;
};
opp-1200000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-1100000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-1000000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-900000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-800000000 {
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
};
opp-700000000 {
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
};
&cluster_a7_opp_table {
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1275000>;
+ clock-latency-ns = <140000>;
+ };
opp-1300000000 {
opp-microvolt = <1250000>;
};
diff --git a/arch/arm/boot/dts/gemini-dlink-dir-685.dts b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
index e2030ba..cc39289 100644
--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
@@ -119,13 +119,11 @@
/*
* This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
- * Since the platform has no temperature sensor, this is controlled
- * from userspace by using the hard disks S.M.A.R.T. temperature
* sensor. It is turned on when the temperature exceeds 46 degrees
* and turned off when the temperatures goes below 41 degrees
* (celsius).
*/
- gpio-fan {
+ fan0: gpio-fan {
compatible = "gpio-fan";
/* Collides with IDE */
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
@@ -133,6 +131,40 @@
#cooling-cells = <2>;
};
+ thermal-zones {
+ chassis-thermal {
+ /* Poll every 20 seconds */
+ polling-delay = <20000>;
+ /* Poll every 2nd second when cooling */
+ polling-delay-passive = <2000>;
+ /* Use the thermal sensor in the hard drive */
+ thermal-sensors = <&drive0>;
+
+ /* Tripping points from the fan.script in the rootfs */
+ trips {
+ alert: chassis-alert {
+ /* At 43 degrees turn on the fan */
+ temperature = <43000>;
+ hysteresis = <3000>;
+ type = "active";
+ };
+ crit: chassis-crit {
+ /* Just shut down at 60 degrees */
+ temperature = <60000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&alert>;
+ cooling-device = <&fan0 1 1>;
+ };
+ };
+ };
+ };
+
/*
* The touchpad input is connected to a GPIO bit-banged
* I2C bus.
@@ -443,8 +475,18 @@
};
};
- ata@63000000 {
+ ide@63000000 {
status = "okay";
+
+ /*
+ * This drive may have a temperature sensor with a
+ * thermal zone we can use for thermal control of the
+ * chassis temperature using the fan.
+ */
+ drive0: ide-port@0 {
+ reg = <0>;
+ #thermal-sensor-cells = <0>;
+ };
};
display-controller@6a000000 {
diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
index d0bbf2b..b8acc6e 100644
--- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
@@ -297,7 +297,7 @@
};
};
- ata@63000000 {
+ ide@63000000 {
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts
index e1020e0..6544c73 100644
--- a/arch/arm/boot/dts/gemini-nas4220b.dts
+++ b/arch/arm/boot/dts/gemini-nas4220b.dts
@@ -84,7 +84,7 @@
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0xfe0000 */
- fis-index-block = <0x1fc>;
+ fis-index-block = <0x7f>;
};
};
@@ -170,11 +170,11 @@
};
};
- ata@63000000 {
+ ide@63000000 {
status = "okay";
};
- ata@63400000 {
+ ide@63400000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/gemini-sl93512r.dts b/arch/arm/boot/dts/gemini-sl93512r.dts
index a98af03..a0916d3 100644
--- a/arch/arm/boot/dts/gemini-sl93512r.dts
+++ b/arch/arm/boot/dts/gemini-sl93512r.dts
@@ -293,11 +293,11 @@
};
};
- ata@63000000 {
+ ide@63000000 {
status = "okay";
};
- ata@63400000 {
+ ide@63400000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/gemini-sq201.dts b/arch/arm/boot/dts/gemini-sq201.dts
index 239dfac..0c6e6d3 100644
--- a/arch/arm/boot/dts/gemini-sq201.dts
+++ b/arch/arm/boot/dts/gemini-sq201.dts
@@ -289,7 +289,7 @@
};
};
- ata@63000000 {
+ ide@63000000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi
index ef4f1c5..07448c0 100644
--- a/arch/arm/boot/dts/gemini.dtsi
+++ b/arch/arm/boot/dts/gemini.dtsi
@@ -357,7 +357,7 @@
};
};
- ata@63000000 {
+ ide@63000000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63000000 0x1000>;
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
@@ -366,9 +366,11 @@
clock-names = "PCLK";
sata = <&sata>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
- ata@63400000 {
+ ide@63400000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63400000 0x1000>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
@@ -377,6 +379,8 @@
clock-names = "PCLK";
sata = <&sata>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
dma-controller@67000000 {
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index 9c207a6..f683440 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -71,7 +71,7 @@
interrupt-parent = <&gic>;
ranges = <0 0xfc000000 0x2000000>;
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0x100000 0x100000>;
interrupts = <0 15 4>;
@@ -89,7 +89,7 @@
};
sysctrl: system-controller@802000 {
- compatible = "hisilicon,sysctrl";
+ compatible = "hisilicon,sysctrl", "syscon";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x802000 0x1000>;
@@ -111,8 +111,10 @@
reg = <0x800000 0x1000>;
/* timer00 & timer01 */
interrupts = <0 0 4>, <0 1 4>;
- clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
- clock-names = "apb_pclk";
+ clocks = <&clock HI3620_TIMER0_MUX>,
+ <&clock HI3620_TIMER1_MUX>,
+ <&clock HI3620_TIMER0_MUX>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -121,8 +123,10 @@
reg = <0x801000 0x1000>;
/* timer10 & timer11 */
interrupts = <0 2 4>, <0 3 4>;
- clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
- clock-names = "apb_pclk";
+ clocks = <&clock HI3620_TIMER2_MUX>,
+ <&clock HI3620_TIMER3_MUX>,
+ <&clock HI3620_TIMER2_MUX>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -131,8 +135,10 @@
reg = <0xa01000 0x1000>;
/* timer20 & timer21 */
interrupts = <0 4 4>, <0 5 4>;
- clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
- clock-names = "apb_pclk";
+ clocks = <&clock HI3620_TIMER4_MUX>,
+ <&clock HI3620_TIMER5_MUX>,
+ <&clock HI3620_TIMER4_MUX>;
+ clock-names = "timer0lck", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -141,8 +147,10 @@
reg = <0xa02000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 6 4>, <0 7 4>;
- clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
- clock-names = "apb_pclk";
+ clocks = <&clock HI3620_TIMER6_MUX>,
+ <&clock HI3620_TIMER7_MUX>,
+ <&clock HI3620_TIMER6_MUX>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -151,8 +159,10 @@
reg = <0xa03000 0x1000>;
/* timer40 & timer41 */
interrupts = <0 96 4>, <0 97 4>;
- clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
- clock-names = "apb_pclk";
+ clocks = <&clock HI3620_TIMER8_MUX>,
+ <&clock HI3620_TIMER9_MUX>,
+ <&clock HI3620_TIMER8_MUX>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index f4e4dca..b6b0225 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -13,7 +13,6 @@
compatible = "calxeda,highbank";
#address-cells = <1>;
#size-cells = <1>;
- clock-ranges;
cpus {
#address-cells = <1>;
@@ -96,7 +95,7 @@
};
};
- memory {
+ memory@0 {
name = "memory";
device_type = "memory";
reg = <0x00000000 0xff900000>;
@@ -128,14 +127,12 @@
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
- #size-cells = <0>;
- #address-cells = <1>;
interrupt-controller;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xfff12000 0x1000>;
interrupts = <0 70 4>;
@@ -145,14 +142,14 @@
pmu {
compatible = "arm,cortex-a9-pmu";
- interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
+ interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
};
sregs@fff3c200 {
compatible = "calxeda,hb-sregs-l2-ecc";
reg = <0xfff3c200 0x100>;
- interrupts = <0 71 4 0 72 4>;
+ interrupts = <0 71 4>, <0 72 4>;
};
};
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 4263a93..555bc6b 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -213,7 +213,7 @@
};
sysctrl: sysctrl {
- compatible = "hisilicon,sysctrl";
+ compatible = "hisilicon,sysctrl", "syscon";
reg = <0x3e00000 0x00100000>;
};
@@ -226,8 +226,8 @@
compatible = "arm,sp804", "arm,primecell";
reg = <0x3000000 0x1000>;
interrupts = <0 224 4>;
- clocks = <&clk_50m>, <&clk_50m>;
- clock-names = "apb_pclk";
+ clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
};
arm-pmu {
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index 696e698..e2dbf1d 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -370,8 +370,9 @@
arm,primecell-periphid = <0x00141805>;
reg = <0xa2c000 0x1000>;
interrupts = <0 29 4>;
- clocks = <&clock HIX5HD2_WDG0_RST>;
- clock-names = "apb_pclk";
+ clocks = <&clock HIX5HD2_WDG0_RST>,
+ <&clock HIX5HD2_WDG0_RST>;
+ clock-names = "wdog_clk", "apb_pclk";
};
};
@@ -381,7 +382,7 @@
interrupts = <1 13 0xf01>;
};
- l2: l2-cache {
+ l2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0x00a10000 0x100000>;
interrupts = <0 15 4>;
diff --git a/arch/arm/boot/dts/ibm-power9-dual.dtsi b/arch/arm/boot/dts/ibm-power9-dual.dtsi
index 2abc42e..a0fa65b 100644
--- a/arch/arm/boot/dts/ibm-power9-dual.dtsi
+++ b/arch/arm/boot/dts/ibm-power9-dual.dtsi
@@ -86,7 +86,7 @@
#address-cells = <1>;
#size-cells = <0>;
- fsi_occ0: occ {
+ fsi_occ0: occ@1 {
compatible = "ibm,p9-occ";
};
};
@@ -187,7 +187,7 @@
#address-cells = <1>;
#size-cells = <0>;
- fsi_occ1: occ {
+ fsi_occ1: occ@2 {
compatible = "ibm,p9-occ";
};
};
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
index b30448c..9b94098 100644
--- a/arch/arm/boot/dts/imx1.dtsi
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -125,7 +125,7 @@
};
pwm: pwm@208000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx1-pwm";
reg = <0x00208000 0x1000>;
interrupts = <34>;
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 0b2701c..3b609d9 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -53,7 +53,7 @@
apb@80000000 {
apbh@80000000 {
- gpmi-nand@8000c000 {
+ nand-controller@8000c000 {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;
status = "okay";
@@ -79,7 +79,6 @@
MX23_PAD_LCD_RESET__GPIO_1_18
MX23_PAD_PWM3__GPIO_1_29
MX23_PAD_PWM4__GPIO_1_30
- MX23_PAD_SSP1_DETECT__SSP1_DETECT
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 4c9aafe..0729e72 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -23,7 +23,7 @@
ssp0: spi@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+ pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
bus-width = <4>;
broken-cd;
status = "okay";
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 8257630..7f4c602 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -76,7 +76,7 @@
status = "disabled";
};
- gpmi-nand@8000c000 {
+ nand-controller@8000c000 {
compatible = "fsl,imx23-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
@@ -267,6 +267,14 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
+ mmc0_sck_cfg: mmc0-sck-cfg@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_SSP1_SCK__SSP1_SCK
+ >;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
mmc1_4bit_pins_a: mmc1-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
@@ -422,7 +430,7 @@
clocks = <&clks 16>;
};
- dcp@80028000 {
+ dcp: crypto@80028000 {
compatible = "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <53 54>;
@@ -434,7 +442,7 @@
status = "disabled";
};
- ocotp@8002c000 {
+ efuse@8002c000 {
compatible = "fsl,imx23-ocotp", "fsl,ocotp";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 0fde90d..3f38c2e 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -165,8 +165,6 @@
};
&usbhost1 {
- phy_type = "serial";
- dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 05cccd1..fb66884 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -304,8 +304,6 @@
};
&usbhost1 {
- phy_type = "serial";
- dr_mode = "host";
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index f4516cc..f984b70 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -82,10 +82,12 @@
#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000
#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000
#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000
+#define MX25_PAD_EB0__CSPI3_SS0 0x040 0x258 0x4bc 0x06 0x000
#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000
#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000
#define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000
+#define MX25_PAD_EB1__CSPI3_SS1 0x044 0x25c 0x4c0 0x06 0x000
#define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000
#define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000
@@ -102,22 +104,27 @@
#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000
#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000
#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000
+#define MX25_PAD_CS4__CSPI3_MOSI 0x054 0x264 0x4b8 0x06 0x000
#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000
#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000
#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000
#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000
+#define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000
#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000
+#define MX25_PAD_NF_CE0__CSPI1_SS3 0x05c 0x26c 0x490 0x01 0x000
#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000
#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000
#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000
#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000
+#define MX25_PAD_ECB__CSPI3_SCLK 0x060 0x270 0x4ac 0x06 0x000
#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000
#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000
#define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000
+#define MX25_PAD_LBA__CSPI3_RDY 0x064 0x274 0x4b0 0x06 0x000
#define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000
#define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000
@@ -251,10 +258,12 @@
#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000
#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
+#define MX25_PAD_LD12__KPP_ROW6 0x0f8 0x2f0 0x544 0x04 0x000
#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001
#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000
#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000
+#define MX25_PAD_LD13__KPP_ROW7 0x0fc 0x2f4 0x548 0x04 0x000
#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000
#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000
@@ -279,7 +288,8 @@
#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000
#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000
-#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x01 0x000
+#define MX25_PAD_CONTRAST__GPT4_CAPIN1 0x118 0x310 0x000 0x01 0x000
+#define MX25_PAD_CONTRAST__CSPI2_SS1 0x118 0x310 0x4a8 0x02 0x000
#define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000
#define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001
#define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000
@@ -292,7 +302,7 @@
#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001
#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000
#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000
-#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x07 0x000
+#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x4b8 0x07 0x001
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000
#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000
@@ -304,23 +314,25 @@
#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001
#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000
#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000
-#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000
+#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x4ac 0x07 0x001
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000
#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000
#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000
-#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000
+#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x4b0 0x07 0x001
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000
/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000
+#define MX25_PAD_CSI_D6__CSPI3_SS0 0x130 0x328 0x4bc 0x07 0x001
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000
#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000
+#define MX25_PAD_CSI_D7__CSPI3_SS1 0x134 0x32c 0x4c0 0x07 0x001
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000
#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000
@@ -392,7 +404,7 @@
#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000
#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001
-#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x02 0x000
+#define MX25_PAD_UART1_RTS__GPT3_CAPIN1 0x178 0x370 0x000 0x02 0x000
#define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000
#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000
@@ -409,12 +421,14 @@
#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000
#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002
-#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000
+#define MX25_PAD_UART2_RTS__GPT1_CAPIN1 0x188 0x380 0x000 0x03 0x000
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000
+#define MX25_PAD_UART2_RTS__CSPI2_SS3 0x188 0x380 0x000 0x06 0x000
#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000
+#define MX25_PAD_UART2_CTS__CSPI3_SS3 0x18c 0x384 0x4c8 0x06 0x001
/*
* Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD
@@ -440,14 +454,17 @@
#define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000
#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA1__CSPI2_RDY 0x19c 0x394 0x498 0x01 0x001
#define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000
#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000
#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA2__CSPI2_SS0 0x1a0 0x398 0x4a4 0x01 0x001
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002
#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000
#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA3__CSPI2_SS1 0x1a4 0x39c 0x4a8 0x01 0x001
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002
#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000
@@ -512,9 +529,11 @@
#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000
#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000
+#define MX25_PAD_FEC_TX_EN__KPP_ROW4 0x1d8 0x3d0 0x53c 0x06 0x000
#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000
+#define MX25_PAD_FEC_RDATA0__KPP_ROW5 0x1dc 0x3d4 0x540 0x06 0x000
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000
/*
@@ -556,11 +575,15 @@
#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000
#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001
#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001
+#define MX25_PAD_GPIO_C__GPT2_CAPIN1 0x1fc 0x3f8 0x000 0x04 0x000
+#define MX25_PAD_GPIO_C__CSPI1_SS2 0x1fc 0x3f8 0x000 0x05 0x000
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000
+#define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000
#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000
#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001
+#define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001
#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000
#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002
@@ -585,6 +608,7 @@
#define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000
+#define MX25_PAD_VSTBY_ACK__CSPI1_SS3 0x218 0x40c 0x490 0x02 0x001
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000
#define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 9a097ef..1ab19f1 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -75,7 +75,7 @@
interrupt-parent = <&asic>;
ranges;
- aips@43f00000 { /* AIPS1 */
+ bus@43f00000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -332,7 +332,7 @@
};
};
- aips@53f00000 { /* AIPS2 */
+ bus@53f00000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -411,7 +411,7 @@
pwm2: pwm@53fa0000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
reg = <0x53fa0000 0x4000>;
clocks = <&clks 106>, <&clks 52>;
clock-names = "ipg", "per";
@@ -430,7 +430,7 @@
pwm3: pwm@53fa8000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
reg = <0x53fa8000 0x4000>;
clocks = <&clks 107>, <&clks 52>;
clock-names = "ipg", "per";
@@ -453,7 +453,7 @@
interrupts = <22>;
};
- esdhc1: esdhc@53fb4000 {
+ esdhc1: mmc@53fb4000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <9>;
@@ -462,7 +462,7 @@
status = "disabled";
};
- esdhc2: esdhc@53fb8000 {
+ esdhc2: mmc@53fb8000 {
compatible = "fsl,imx25-esdhc";
reg = <0x53fb8000 0x4000>;
interrupts = <8>;
@@ -488,7 +488,7 @@
pwm4: pwm@53fc8000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
reg = <0x53fc8000 0x4000>;
clocks = <&clks 108>, <&clks 52>;
clock-names = "ipg", "per";
@@ -535,14 +535,14 @@
pwm1: pwm@53fe0000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
reg = <0x53fe0000 0x4000>;
clocks = <&clks 105>, <&clks 52>;
clock-names = "ipg", "per";
interrupts = <26>;
};
- iim: iim@53ff0000 {
+ iim: efuse@53ff0000 {
compatible = "fsl,imx25-iim", "fsl,imx27-iim";
reg = <0x53ff0000 0x4000>;
interrupts = <19>;
@@ -570,6 +570,9 @@
clock-names = "ipg", "ahb", "per";
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
+ maximum-speed = "full-speed";
+ phy_type = "serial";
+ dr_mode = "host";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
index 52c9524..303f920 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
@@ -18,8 +18,8 @@
};
&cspi1 {
- cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
- <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>,
+ <&gpio4 27 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index bf883e4..344e777 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -65,7 +65,7 @@
&cspi1 {
pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>;
- cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
+ cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>,
<&gpio4 27 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 3652f55..7bc1327 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -134,7 +134,7 @@
};
pwm: pwm@10006000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx27-pwm";
reg = <0x10006000 0x1000>;
interrupts = <23>;
@@ -265,7 +265,7 @@
status = "disabled";
};
- sdhci1: sdhci@10013000 {
+ sdhci1: mmc@10013000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10013000 0x1000>;
interrupts = <11>;
@@ -277,7 +277,7 @@
status = "disabled";
};
- sdhci2: sdhci@10014000 {
+ sdhci2: mmc@10014000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10014000 0x1000>;
interrupts = <10>;
@@ -431,7 +431,7 @@
status = "disabled";
};
- sdhci3: sdhci@1001e000 {
+ sdhci3: mmc@1001e000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x1001e000 0x1000>;
interrupts = <9>;
@@ -525,7 +525,7 @@
reg = <0x10024600 0x200>;
};
- sahara2: sahara@10025000 {
+ sahara2: crypto@10025000 {
compatible = "fsl,imx27-sahara";
reg = <0x10025000 0x1000>;
interrupts = <59>;
@@ -540,7 +540,7 @@
#clock-cells = <1>;
};
- iim: iim@10028000 {
+ iim: efuse@10028000 {
compatible = "fsl,imx27-iim";
reg = <0x10028000 0x1000>;
interrupts = <62>;
@@ -558,7 +558,7 @@
};
};
- nfc: nand@d8000000 {
+ nfc: nand-controller@d8000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx27-nand";
@@ -585,7 +585,7 @@
status = "disabled";
};
- iram: iram@ffff4c00 {
+ iram: sram@ffff4c00 {
compatible = "mmio-sram";
reg = <0xffff4c00 0xb400>;
};
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 3ed2b32..14a92fe 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -17,7 +17,7 @@
apb@80000000 {
apbh@80000000 {
- gpmi-nand@8000c000 {
+ nand-controller@8000c000 {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index 3a184d1..b86be32 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -13,7 +13,7 @@
apb@80000000 {
apbh@80000000 {
- gpmi-nand@8000c000 {
+ nand-controller@8000c000 {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
status = "okay";
@@ -183,10 +183,20 @@
pinctrl-0 = <&auart2_2pins_a>;
status = "okay";
};
+
+ usbphy1: usbphy@8007e000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins_a>;
+ status = "okay";
+ };
};
};
ahb@80080000 {
+ usb1: usb@80090000 {
+ status = "okay";
+ };
+
mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 96c1d10..7e2b0f1 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -97,7 +97,7 @@
apb@80000000 {
apbh@80000000 {
- gpmi-nand@8000c000 {
+ nand-controller@8000c000 {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg
&gpmi_pins_evk>;
diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi
index 0bac72d..2bdb4c0 100644
--- a/arch/arm/boot/dts/imx28-m28.dtsi
+++ b/arch/arm/boot/dts/imx28-m28.dtsi
@@ -16,7 +16,7 @@
apb@80000000 {
apbh@80000000 {
- gpmi-nand@8000c000 {
+ nand-controller@8000c000 {
#address-cells = <1>;
#size-cells = <1>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 91bd6de..865ac3d 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -17,7 +17,7 @@
apb@80000000 {
apbh@80000000 {
- gpmi-nand@8000c000 {
+ nand-controller@8000c000 {
#address-cells = <1>;
#size-cells = <1>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index e14d8ef..94dfbf5 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -100,7 +100,7 @@
status = "disabled";
};
- gpmi: gpmi-nand@8000c000 {
+ gpmi: nand-controller@8000c000 {
compatible = "fsl,imx28-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
@@ -998,7 +998,7 @@
clocks = <&clks 26>;
};
- dcp: dcp@80028000 {
+ dcp: crypto@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <52 53 54>;
@@ -1011,7 +1011,7 @@
status = "disabled";
};
- ocotp: ocotp@8002c000 {
+ ocotp: efuse@8002c000 {
compatible = "fsl,imx28-ocotp", "fsl,ocotp";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index d7f6fb7..45333f7 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -55,7 +55,7 @@
interrupt-parent = <&avic>;
ranges;
- iram: iram@1fffc000 {
+ iram: sram@1fffc000 {
compatible = "mmio-sram";
reg = <0x1fffc000 0x4000>;
#address-cells = <1>;
@@ -63,7 +63,7 @@
ranges = <0 0x1fffc000 0x4000>;
};
- aips@43f00000 { /* AIPS1 */
+ bus@43f00000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -173,7 +173,7 @@
reg = <0x50000000 0x100000>;
ranges;
- sdhci1: sdhci@50004000 {
+ sdhci1: mmc@50004000 {
compatible = "fsl,imx31-mmc";
reg = <0x50004000 0x4000>;
interrupts = <9>;
@@ -184,7 +184,7 @@
status = "disabled";
};
- sdhci2: sdhci@50008000 {
+ sdhci2: mmc@50008000 {
compatible = "fsl,imx31-mmc";
reg = <0x50008000 0x4000>;
interrupts = <8>;
@@ -217,7 +217,7 @@
status = "disabled";
};
- iim: iim@5001c000 {
+ iim: efuse@5001c000 {
compatible = "fsl,imx31-iim", "fsl,imx27-iim";
reg = <0x5001c000 0x1000>;
interrupts = <19>;
@@ -225,7 +225,7 @@
};
};
- aips@53f00000 { /* AIPS2 */
+ bus@53f00000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -327,7 +327,7 @@
interrupts = <26>;
clocks = <&clks 10>, <&clks 42>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 9cbdc1a..aba1625 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -59,14 +59,14 @@
interrupt-parent = <&avic>;
ranges;
- L2: l2-cache@30000000 {
+ L2: cache-controller@30000000 {
compatible = "arm,l210-cache";
reg = <0x30000000 0x1000>;
cache-unified;
cache-level = <2>;
};
- aips1: aips@43f00000 {
+ aips1: bus@43f00000 {
compatible = "fsl,aips", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -199,7 +199,7 @@
};
};
- aips2: aips@53f00000 {
+ aips2: bus@53f00000 {
compatible = "fsl,aips", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -231,7 +231,7 @@
#interrupt-cells = <2>;
};
- esdhc1: esdhc@53fb4000 {
+ esdhc1: mmc@53fb4000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <7>;
@@ -240,7 +240,7 @@
status = "disabled";
};
- esdhc2: esdhc@53fb8000 {
+ esdhc2: mmc@53fb8000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb8000 0x4000>;
interrupts = <8>;
@@ -249,7 +249,7 @@
status = "disabled";
};
- esdhc3: esdhc@53fbc000 {
+ esdhc3: mmc@53fbc000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fbc000 0x4000>;
interrupts = <9>;
@@ -320,7 +320,7 @@
status = "disabled";
};
- iim@53ff0000 {
+ efuse@53ff0000 {
compatible = "fsl,imx35-iim";
reg = <0x53ff0000 0x4000>;
interrupts = <19>;
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
index 907339b..4ea5c23 100644
--- a/arch/arm/boot/dts/imx50-evk.dts
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -20,7 +20,7 @@
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi>;
- cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
+ cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>;
status = "okay";
flash: m25p32@1 {
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 0bfe7c9..b6b2e6a 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -101,7 +101,7 @@
interrupt-parent = <&tzic>;
ranges;
- aips@50000000 { /* AIPS1 */
+ bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -115,7 +115,7 @@
reg = <0x50000000 0x40000>;
ranges;
- esdhc1: esdhc@50004000 {
+ esdhc1: mmc@50004000 {
compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
@@ -127,7 +127,7 @@
status = "disabled";
};
- esdhc2: esdhc@50008000 {
+ esdhc2: mmc@50008000 {
compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
@@ -176,7 +176,7 @@
status = "disabled";
};
- esdhc3: esdhc@50020000 {
+ esdhc3: mmc@50020000 {
compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
@@ -188,7 +188,7 @@
status = "disabled";
};
- esdhc4: esdhc@50024000 {
+ esdhc4: mmc@50024000 {
compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
@@ -288,13 +288,8 @@
reg = <0x53fa8000 0x4000>;
};
- gpr: iomuxc-gpr@53fa8000 {
- compatible = "fsl,imx50-iomuxc-gpr", "syscon";
- reg = <0x53fa8000 0xc>;
- };
-
pwm1: pwm@53fb4000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
@@ -304,7 +299,7 @@
};
pwm2: pwm@53fb8000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
@@ -333,9 +328,10 @@
status = "disabled";
};
- src: src@53fd0000 {
+ src: reset-controller@53fd0000 {
compatible = "fsl,imx50-src", "fsl,imx51-src";
reg = <0x53fd0000 0x4000>;
+ interrupts = <75>;
#reset-cells = <1>;
};
@@ -389,7 +385,7 @@
};
};
- aips@60000000 { /* AIPS2 */
+ bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index 563c1aa..c66f274 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -74,8 +74,8 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
- <&gpio4 25 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>,
+ <&gpio4 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index ed6a3ce..552196d 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -58,27 +58,25 @@
display1: disp1 {
compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1>;
- display-timings {
- native-mode = <&timing0>;
- timing0: dvi {
- clock-frequency = <65000000>;
- hactive = <1024>;
- vactive = <768>;
- hback-porch = <220>;
- hfront-porch = <40>;
- vback-porch = <21>;
- vfront-porch = <7>;
- hsync-len = <60>;
- vsync-len = <10>;
+
+ port@0 {
+ reg = <0>;
+
+ display0_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp1>;
};
};
- port {
- display0_in: endpoint {
- remote-endpoint = <&ipu_di0_disp1>;
+ port@1 {
+ reg = <1>;
+
+ parallel_display_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
};
};
};
@@ -115,6 +113,42 @@
};
};
+ dvi-connector {
+ compatible = "dvi-connector";
+ digital;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ dvi-encoder {
+ compatible = "ti,tfp410";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <¶llel_display_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
index 4344632..6ecb83e 100644
--- a/arch/arm/boot/dts/imx51-ts4800.dts
+++ b/arch/arm/boot/dts/imx51-ts4800.dts
@@ -113,6 +113,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_backlight>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index 3596060..e559ab0 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -217,8 +217,8 @@
simple-audio-card,widgets =
"Headphone", "Headphone Jack";
simple-audio-card,routing =
- "Headphone Jack", "HPLEFT",
- "Headphone Jack", "HPRIGHT";
+ "Headphone Jack", "TPA6130A2 HPLEFT",
+ "Headphone Jack", "TPA6130A2 HPRIGHT";
simple-audio-card,aux-devs = <&hpa1>;
sound_cpu: simple-audio-card,cpu {
@@ -470,6 +470,7 @@
compatible = "ti,tpa6130a2";
reg = <0x60>;
Vdd-supply = <®_3p3v>;
+ sound-name-prefix = "TPA6130A2";
};
ds1341: rtc@68 {
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 0a4b9a5..985e1be 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -104,6 +104,11 @@
#phy-cells = <0>;
};
+ capture-subsystem {
+ compatible = "fsl,imx-capture-subsystem";
+ ports = <&ipu_csi0>, <&ipu_csi1>;
+ };
+
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>, <&ipu_di1>;
@@ -116,7 +121,7 @@
interrupt-parent = <&tzic>;
ranges;
- iram: iram@1ffe0000 {
+ iram: sram@1ffe0000 {
compatible = "mmio-sram";
reg = <0x1ffe0000 0x20000>;
};
@@ -143,6 +148,14 @@
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
+ ipu_csi0: port@0 {
+ reg = <0>;
+ };
+
+ ipu_csi1: port@1 {
+ reg = <1>;
+ };
+
ipu_di0: port@2 {
reg = <2>;
@@ -158,7 +171,7 @@
};
};
- aips@70000000 { /* AIPS1 */
+ bus@70000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -172,7 +185,7 @@
reg = <0x70000000 0x40000>;
ranges;
- esdhc1: esdhc@70004000 {
+ esdhc1: mmc@70004000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
@@ -183,7 +196,7 @@
status = "disabled";
};
- esdhc2: esdhc@70008000 {
+ esdhc2: mmc@70008000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
@@ -232,7 +245,7 @@
status = "disabled";
};
- esdhc3: esdhc@70020000 {
+ esdhc3: mmc@70020000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70020000 0x4000>;
interrupts = <3>;
@@ -244,7 +257,7 @@
status = "disabled";
};
- esdhc4: esdhc@70024000 {
+ esdhc4: mmc@70024000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70024000 0x4000>;
interrupts = <4>;
@@ -387,7 +400,7 @@
};
pwm1: pwm@73fb4000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
@@ -397,7 +410,7 @@
};
pwm2: pwm@73fb8000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
@@ -426,9 +439,10 @@
status = "disabled";
};
- src: src@73fd0000 {
+ src: reset-controller@73fd0000 {
compatible = "fsl,imx51-src";
reg = <0x73fd0000 0x4000>;
+ interrupts = <75>;
#reset-cells = <1>;
};
@@ -440,7 +454,7 @@
};
};
- aips@80000000 { /* AIPS2 */
+ bus@80000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -452,7 +466,7 @@
reg = <0x83f00000 0x60>;
};
- iim: iim@83f98000 {
+ iim: efuse@83f98000 {
compatible = "fsl,imx51-iim", "fsl,imx27-iim";
reg = <0x83f98000 0x4000>;
interrupts = <69>;
diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts
index 0a475c2..cfb1884 100644
--- a/arch/arm/boot/dts/imx53-cx9020.dts
+++ b/arch/arm/boot/dts/imx53-cx9020.dts
@@ -59,23 +59,26 @@
};
dvi-converter {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "ti,tfp410";
- port@0 {
- reg = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- tfp410_in: endpoint {
- remote-endpoint = <&display0_out>;
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <&display0_out>;
+ };
};
- };
- port@1 {
- reg = <1>;
+ port@1 {
+ reg = <1>;
- tfp410_out: endpoint {
- remote-endpoint = <&dvi_connector_in>;
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/imx53-kp.dtsi b/arch/arm/boot/dts/imx53-kp.dtsi
index 8b25416..4508f34 100644
--- a/arch/arm/boot/dts/imx53-kp.dtsi
+++ b/arch/arm/boot/dts/imx53-kp.dtsi
@@ -162,6 +162,14 @@
>;
};
+&pwm1 {
+ #pwm-cells = <2>;
+};
+
+&pwm2 {
+ #pwm-cells = <2>;
+};
+
&uart1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index daab56a..a1a6228 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -321,6 +321,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts
index 64faf5b..4f88e96 100644
--- a/arch/arm/boot/dts/imx53-m53menlo.dts
+++ b/arch/arm/boot/dts/imx53-m53menlo.dts
@@ -56,6 +56,7 @@
panel {
compatible = "edt,etm0700g0dh6";
pinctrl-0 = <&pinctrl_display_gpio>;
+ pinctrl-names = "default";
enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
port {
@@ -76,8 +77,7 @@
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
+ gpio = <&gpio1 2 0>;
};
};
@@ -104,7 +104,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
- cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio2 27 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>;
status = "okay";
spidev@0 {
diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts
index c80d170..6d9a5ed 100644
--- a/arch/arm/boot/dts/imx53-ppd.dts
+++ b/arch/arm/boot/dts/imx53-ppd.dts
@@ -182,7 +182,7 @@
power-supply = <®_3v3_lcd>;
};
- leds {
+ leds-brightness {
compatible = "pwm-leds";
alarm-brightness {
@@ -191,6 +191,32 @@
};
};
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_alarmled_pins>;
+
+ alarm1 {
+ label = "alarm:red";
+ gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm2 {
+ label = "alarm:yellow";
+ gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm3 {
+ label = "alarm:blue";
+ gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm4 {
+ label = "alarm:silenced";
+ gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
@@ -601,12 +627,14 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
@@ -912,18 +940,10 @@
MX53_PAD_NANDF_CS3__GPIO6_16 0x0
/* POWER_AND_BOOT_STATUS_INDICATOR */
MX53_PAD_PATA_INTRQ__GPIO7_2 0x1e4
- /* ACTIVATE_ALARM_LIGHT_RED */
- MX53_PAD_PATA_DIOR__GPIO7_3 0x0
- /* ACTIVATE_ALARM_LIGHT_YELLOW */
- MX53_PAD_PATA_DA_1__GPIO7_7 0x0
- /* ACTIVATE_ALARM_LIGHT_CYAN */
- MX53_PAD_PATA_DA_2__GPIO7_8 0x0
/* RUNNING_ON_BATTERY_INDICATOR_GREEN */
MX53_PAD_GPIO_16__GPIO7_11 0x0
/* BATTERY_STATUS_INDICATOR_AMBER */
MX53_PAD_GPIO_17__GPIO7_12 0x0
- /* AUDIO_ALARMS_SILENCED_INDICATOR */
- MX53_PAD_GPIO_18__GPIO7_13 0x0
>;
};
@@ -1083,4 +1103,17 @@
MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x180
>;
};
+
+ pinctrl_alarmled_pins: qmx6alarmledgrp {
+ fsl,pins = <
+ /* ACTIVATE_ALARM_LIGHT_RED */
+ MX53_PAD_PATA_DIOR__GPIO7_3 0x0
+ /* ACTIVATE_ALARM_LIGHT_YELLOW */
+ MX53_PAD_PATA_DA_1__GPIO7_7 0x0
+ /* ACTIVATE_ALARM_LIGHT_CYAN */
+ MX53_PAD_PATA_DA_2__GPIO7_8 0x0
+ /* AUDIO_ALARMS_SILENCED_INDICATOR */
+ MX53_PAD_GPIO_18__GPIO7_13 0x0
+ >;
+ };
};
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index f00dda3..9b4efcd 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -18,32 +18,26 @@
display0: disp0 {
compatible = "fsl,imx-parallel-display";
- interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
- display-timings {
- claawvga {
- native-mode;
- clock-frequency = <27000000>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <40>;
- hfront-porch = <60>;
- vback-porch = <10>;
- vfront-porch = <10>;
- hsync-len = <20>;
- vsync-len = <10>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ display0_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp0>;
};
};
- port {
- display0_in: endpoint {
- remote-endpoint = <&ipu_di0_disp0>;
+ port@1 {
+ reg = <1>;
+
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
};
};
};
@@ -84,6 +78,16 @@
};
};
+ panel {
+ compatible = "sii,43wvf1g";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index ec9fb89..9be44e8 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -58,7 +58,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
status = "okay";
zigbee: mc1323@0 {
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index ea90fd9..7e7f9f3 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -50,8 +50,8 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
- <&gpio3 24 0>, <&gpio3 25 0>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>,
+ <&gpio3 24 GPIO_ACTIVE_LOW>, <&gpio3 25 GPIO_ACTIVE_LOW>;
status = "disabled";
};
@@ -209,6 +209,14 @@
};
};
+&pwm1 {
+ #pwm-cells = <2>;
+};
+
+&pwm2 {
+ #pwm-cells = <2>;
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -243,8 +251,8 @@
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi>;
- cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
- <&gpio1 21 0>;
+ cs-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>, <&gpio1 19 GPIO_ACTIVE_LOW>,
+ <&gpio1 21 GPIO_ACTIVE_LOW>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index 4ab1359..7c9730f 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -542,7 +542,6 @@
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
- #pwm-cells = <3>;
};
&sdma {
diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/imx53-usbarmory.dts
index ee6263d..f34993a 100644
--- a/arch/arm/boot/dts/imx53-usbarmory.dts
+++ b/arch/arm/boot/dts/imx53-usbarmory.dts
@@ -120,7 +120,7 @@
};
/*
- * UART mode pin header configration
+ * UART mode pin header configuration
* 3 - GPIO5[26], pull-down 100K
* 4 - GPIO5[27], pull-down 100K
* 5 - TX, pull-up 100K
diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
index 289feab..24859d0 100644
--- a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
+++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
@@ -119,7 +119,8 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>,
+ <&gpio2 16 GPIO_ACTIVE_LOW>, <&gpio2 17 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index ed341cf..500eeaa 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -222,7 +222,7 @@
clock-names = "core_clk", "mem_iface_clk";
};
- aips@50000000 { /* AIPS1 */
+ bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -236,7 +236,7 @@
reg = <0x50000000 0x40000>;
ranges;
- esdhc1: esdhc@50004000 {
+ esdhc1: mmc@50004000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
@@ -248,7 +248,7 @@
status = "disabled";
};
- esdhc2: esdhc@50008000 {
+ esdhc2: mmc@50008000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
@@ -301,7 +301,7 @@
status = "disabled";
};
- esdhc3: esdhc@50020000 {
+ esdhc3: mmc@50020000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
@@ -313,7 +313,7 @@
status = "disabled";
};
- esdhc4: esdhc@50024000 {
+ esdhc4: mmc@50024000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
@@ -525,7 +525,7 @@
};
pwm1: pwm@53fb4000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
@@ -535,7 +535,7 @@
};
pwm2: pwm@53fb8000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
@@ -588,9 +588,10 @@
status = "disabled";
};
- src: src@53fd0000 {
+ src: reset-controller@53fd0000 {
compatible = "fsl,imx53-src", "fsl,imx51-src";
reg = <0x53fd0000 0x4000>;
+ interrupts = <75>;
#reset-cells = <1>;
};
@@ -654,7 +655,7 @@
};
};
- aips@60000000 { /* AIPS2 */
+ bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -666,7 +667,7 @@
reg = <0x63f00000 0x60>;
};
- iim: iim@63f98000 {
+ iim: efuse@63f98000 {
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
reg = <0x63f98000 0x4000>;
interrupts = <69>;
diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
index 9e027b9..665d637 100644
--- a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
+++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
@@ -212,6 +212,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
status = "disabled";
};
@@ -383,7 +384,7 @@
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
>;
};
diff --git a/arch/arm/boot/dts/imx6dl-apf6dev.dts b/arch/arm/boot/dts/imx6dl-apf6dev.dts
index 6632e99..3dcce34 100644
--- a/arch/arm/boot/dts/imx6dl-apf6dev.dts
+++ b/arch/arm/boot/dts/imx6dl-apf6dev.dts
@@ -1,49 +1,6 @@
-/*
- * Copyright 2015 Armadeus Systems
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6dl.dtsi"
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index 37f80ab..5c7e853 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -61,7 +61,7 @@
};
&ecspi2 {
- cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
@@ -79,5 +79,6 @@
};
&pwm1 {
+ #pwm-cells = <2>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
index 8d8c8c2..4d58cb4 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -69,5 +69,6 @@
};
&pwm3 {
+ #pwm-cells = <2>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 9a5d6c9..65359ae 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -1,44 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014-2016 Toradex AG
+ * Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -168,6 +132,21 @@
&i2c3 {
status = "okay";
+ /*
+ * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
+ * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+ */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcap_1>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
+ status = "disabled";
+ };
+
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
@@ -175,6 +154,30 @@
};
};
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2
+ &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4
+ &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
+ &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
+ >;
+
+ pinctrl_pcap_1: pcap1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */
+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */
+ >;
+ };
+
+ pinctrl_mxt_ts: mxttsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */
+ >;
+ };
+};
+
&ipu1_di0_disp0 {
remote-endpoint = <&lcd_display_in>;
};
@@ -236,7 +239,7 @@
/* SRAM on Colibri nEXT_CS0 */
sram@0,0 {
- compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
+ compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
reg = <0 0 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -247,7 +250,7 @@
/* SRAM on Colibri nEXT_CS1 */
sram@1,0 {
- compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
+ compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
reg = <1 0 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts
new file mode 100644
index 0000000..223275f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2020 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6dl-colibri-eval-v3.dts"
+#include "imx6qdl-colibri-v1_1-uhs.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri_imx6dl-v1_1-eval-v3",
+ "toradex,colibri_imx6dl-v1_1",
+ "toradex,colibri_imx6dl-eval-v3",
+ "toradex,colibri_imx6dl",
+ "fsl,imx6dl";
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ status = "okay";
+ /*
+ * Please make sure your carrier board does not pull-up any of
+ * the MMC/SD signals to 3.3 volt before attempting to activate
+ * UHS-I support.
+ * To let signaling voltage be changed to 1.8V, please
+ * delete no-1-8-v property (example below):
+ * /delete-property/no-1-8-v;
+ */
+};
diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
index 9eb2b73..b4a9523 100644
--- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
+++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
@@ -67,7 +67,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
- cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
@@ -80,7 +80,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@0 {
diff --git a/arch/arm/boot/dts/imx6dl-gw5907.dts b/arch/arm/boot/dts/imx6dl-gw5907.dts
new file mode 100644
index 0000000..3fa2822
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw5907.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5907.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907";
+ compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw5910.dts b/arch/arm/boot/dts/imx6dl-gw5910.dts
new file mode 100644
index 0000000..0d5e7e5
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw5910.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5910.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910";
+ compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw5912.dts b/arch/arm/boot/dts/imx6dl-gw5912.dts
new file mode 100644
index 0000000..5260e01
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw5912.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5912.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912";
+ compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-gw5913.dts b/arch/arm/boot/dts/imx6dl-gw5913.dts
new file mode 100644
index 0000000..b74e533
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-gw5913.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-gw5913.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913";
+ compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts
index 385ce7b..0289519 100644
--- a/arch/arm/boot/dts/imx6dl-mamoj.dts
+++ b/arch/arm/boot/dts/imx6dl-mamoj.dts
@@ -303,6 +303,7 @@
};
&pwm3 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts
new file mode 100644
index 0000000..659a8e8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-pico-pi.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard";
+ compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts
new file mode 100644
index 0000000..d7403c5
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-pico-hobbit.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard";
+ compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-pico-nymph.dts b/arch/arm/boot/dts/imx6dl-pico-nymph.dts
new file mode 100644
index 0000000..b282dbf
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-pico-nymph.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-pico-pi.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard";
+ compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-pico-pi.dts b/arch/arm/boot/dts/imx6dl-pico-pi.dts
new file mode 100644
index 0000000..b7b1c07
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-pico-pi.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-pico-pi.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard";
+ compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/imx6dl-prtrvt.dts
new file mode 100644
index 0000000..5ac8444
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-prtrvt.dts
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2014 Protonic Holland
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-prti6q.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Protonic RVT board";
+ compatible = "prt,prtrvt", "fsl,imx6dl";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x10000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+
+ led-debug0 {
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&ecspi3 {
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ status = "okay";
+
+ nfc@0 {
+ compatible = "ti,trf7970a";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nfc>;
+ spi-max-frequency = <2000000>;
+ interrupts-extended = <&gpio5 14 IRQ_TYPE_LEVEL_LOW>;
+ ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>,
+ <&gpio5 11 GPIO_ACTIVE_LOW>;
+ vin-supply = <®_3v3>;
+ vin-voltage-override = <3100000>;
+ autosuspend-delay = <30000>;
+ irq-status-read-quirk;
+ en2-rf-quirk;
+ t5t-rmb-extra-byte-quirk;
+ status = "okay";
+ };
+};
+
+&i2c3 {
+ adc@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* nc */
+ channel@4 {
+ reg = <4>;
+ ti,gain = <3>;
+ ti,datarate = <3>;
+ };
+
+ /* nc */
+ channel@5 {
+ reg = <5>;
+ ti,gain = <3>;
+ ti,datarate = <3>;
+ };
+
+ /* can1_l */
+ channel@6 {
+ reg = <6>;
+ ti,gain = <3>;
+ ti,datarate = <3>;
+ };
+
+ /* can1_h */
+ channel@7 {
+ reg = <7>;
+ ti,gain = <3>;
+ ti,datarate = <3>;
+ };
+ };
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "disabled";
+};
+
+&vpu {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_can1phy: can1phy {
+ fsl,pins = <
+ /* CAN1_SR */
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070
+ /* CAN1_TERM */
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ /* CS */
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1
+ >;
+ };
+
+ pinctrl_leds: ledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+ >;
+ };
+
+ pinctrl_nfc: nfcgrp {
+ fsl,pins = <
+ /* NFC_ASK_OOK */
+ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x100b1
+ /* NFC_PWR_EN */
+ MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x100b1
+ /* NFC_EN2 */
+ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x100b1
+ /* NFC_EN */
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
+ /* NFC_MOD */
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
+ /* NFC_IRQ */
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts
new file mode 100644
index 0000000..ae6da24
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2016 Protonic Holland
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-prti6q.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
+
+/ {
+ model = "Protonic VT7";
+ compatible = "prt,prtvt7", "fsl,imx6dl";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+
+ backlight_lcd: backlight-lcd {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pwms = <&pwm1 0 500000>;
+ brightness-levels = <0 20 81 248 1000>;
+ default-brightness-level = <20>;
+ num-interpolated-steps = <21>;
+ power-supply = <®_bl_12v0>;
+ enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ esc {
+ label = "GPIO Key ESC";
+ linux,code = <KEY_ESC>;
+ gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>;
+ };
+
+ up {
+ label = "GPIO Key UP";
+ linux,code = <KEY_UP>;
+ gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>;
+ };
+
+ down {
+ label = "GPIO Key DOWN";
+ linux,code = <KEY_DOWN>;
+ gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>;
+ };
+
+ enter {
+ label = "GPIO Key Enter";
+ linux,code = <KEY_ENTER>;
+ gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>;
+ };
+
+ cycle {
+ label = "GPIO Key CYCLE";
+ linux,code = <KEY_CYCLEWINDOWS>;
+ gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>;
+ };
+
+ f1 {
+ label = "GPIO Key F1";
+ linux,code = <KEY_F1>;
+ gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>;
+ };
+
+ f2 {
+ label = "GPIO Key F2";
+ linux,code = <KEY_F2>;
+ gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>;
+ };
+
+ f3 {
+ label = "GPIO Key F3";
+ linux,code = <KEY_F3>;
+ gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>;
+ };
+
+ f4 {
+ label = "GPIO Key F4";
+ linux,code = <KEY_F4>;
+ gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>;
+ };
+
+ f5 {
+ label = "GPIO Key F5";
+ linux,code = <KEY_F5>;
+ gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>;
+ };
+
+ f6 {
+ label = "GPIO Key F6";
+ linux,code = <KEY_F6>;
+ gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>;
+ };
+
+ f7 {
+ label = "GPIO Key F7";
+ linux,code = <KEY_F7>;
+ gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>;
+ };
+
+ f8 {
+ label = "GPIO Key F8";
+ linux,code = <KEY_F8>;
+ gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>;
+ };
+
+ f9 {
+ label = "GPIO Key F9";
+ linux,code = <KEY_F9>;
+ gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>;
+ };
+
+ f10 {
+ label = "GPIO Key F10";
+ linux,code = <KEY_F10>;
+ gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+
+ led-debug0 {
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ reg_bl_12v0: regulator-bl-12v0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_bl_12v0>;
+ regulator-name = "bl-12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "prti6q-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Line", "Line In Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "External Speaker";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "External Speaker", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&ssi1>;
+ system-clock-frequency = <0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ bitclock-master;
+ frame-master;
+ };
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+
+ mux-ssi1 {
+ fsl,audmux-port = <0>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN 0
+ IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
+ IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
+ IMX_AUDMUX_V2_PTCR_TFSDIR 0
+ IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
+ >;
+ };
+
+ mux-pins3 {
+ fsl,audmux-port = <2>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
+ 0 IMX_AUDMUX_V2_PDCR_TXRXEN
+ >;
+ };
+};
+
+&can1 {
+ pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+};
+
+&i2c1 {
+ sgtl5000: audio-codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0xa>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_codec>;
+ #sound-dai-cells = <0>;
+ clocks = <&clks 201>;
+ VDDA-supply = <®_3v3>;
+ VDDIO-supply = <®_3v3>;
+ VDDD-supply = <®_1v8>;
+ };
+};
+
+&i2c3 {
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+
+ gpio_pca: gpio@74 {
+ compatible = "nxp,pca9539";
+ reg = <0x74>;
+ interrupts-extended = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+};
+
+&ipu1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+ status = "okay";
+};
+
+&pwm1 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&ssi1 {
+ #sound-dai-cells = <0>;
+ fsl,mode = "ac97-slave";
+ status = "okay";
+};
+
+&usbh1 {
+ status = "disabled";
+};
+
+&vpu {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
+ };
+
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
+ >;
+ };
+
+ pinctrl_can1phy: can1phy {
+ fsl,pins = <
+ /* CAN1_SR */
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070
+ /* CAN1_TERM */
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_codec: codecgrp {
+ fsl,pins = <
+ /* AUDIO_nRESET */
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ /* ITU656_nRESET */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ /* ITU656_nPDN */
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
+ >;
+ };
+
+ pinctrl_ipu1_disp: ipudisp1grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xb0
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xb0
+
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xb0
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xb0
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xb0
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xb0
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xb0
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xb0
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xb0
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xb0
+
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xb0
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xb0
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xb0
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xb0
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xb0
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xb0
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xb0
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xb0
+
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xb0
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xb0
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xb0
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xb0
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xb0
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xb0
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xb0
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xb0
+ >;
+ };
+
+ pinctrl_leds: ledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_reg_bl_12v0: 12blgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_tsc: tscgrp {
+
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 829654e..e7d9bfb 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -89,11 +89,27 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
- phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ phy-handle = <&rgmii_phy>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Atheros AR8035 PHY */
+ rgmii_phy: ethernet-phy@4 {
+ reg = <4>;
+ interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <1000>;
+ qca,smarteee-tw-us-1g = <24>;
+ qca,clk-out-frequency = <125000000>;
+ };
+ };
};
&gpio1 {
diff --git a/arch/arm/boot/dts/imx6dl-tqma6a.dtsi b/arch/arm/boot/dts/imx6dl-tqma6a.dtsi
new file mode 100644
index 0000000..e891ef9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-tqma6a.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-tqma6a.dtsi"
+#include "imx6qdl-tqma6.dtsi"
+
+/ {
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-tqma6b.dtsi b/arch/arm/boot/dts/imx6dl-tqma6b.dtsi
new file mode 100644
index 0000000..38cd850
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-tqma6b.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-tqma6b.dtsi"
+#include "imx6qdl-tqma6.dtsi"
+
+/ {
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
index ce4a5a8..ebc0892 100644
--- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
+++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
@@ -4,9 +4,16 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
/ {
+ aliases: aliases {
+ ethernet1 = ð1;
+ ethernet2 = ð2;
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>;
@@ -138,13 +145,13 @@
};
};
- port@2 {
+ eth2: port@2 {
reg = <2>;
label = "eth2";
phy-handle = <&phy_port2>;
};
- port@3 {
+ eth1: port@3 {
reg = <3>;
label = "eth1";
phy-handle = <&phy_port3>;
@@ -261,29 +268,39 @@
reg = <0x30>;
clock-mode = /bits/ 8 <1>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
- chan0 {
+ chan@0 {
chan-name = "R";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
+ reg = <0>;
+ color = <LED_COLOR_ID_RED>;
};
- chan1 {
+ chan@1 {
chan-name = "G";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
};
- chan2 {
+ chan@2 {
chan-name = "B";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
+ reg = <2>;
+ color = <LED_COLOR_ID_BLUE>;
};
- chan3 {
+ chan@3 {
chan-name = "W";
led-cur = /bits/ 8 <0x0>;
max-cur = /bits/ 8 <0x0>;
+ reg = <3>;
+ color = <LED_COLOR_ID_WHITE>;
};
};
@@ -312,9 +329,22 @@
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
- status = "disabled";
+ status = "okay";
- oled: oled@3d {
+ oled_1309: oled@3c {
+ compatible = "solomon,ssd1309fb-i2c";
+ reg = <0x3c>;
+ solomon,height = <64>;
+ solomon,width = <128>;
+ solomon,page-offset = <0>;
+ solomon,segment-no-remap;
+ solomon,prechargep2 = <15>;
+ reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
+ vbat-supply = <&sw2_reg>;
+ status = "disabled";
+ };
+
+ oled_1305: oled@3d {
compatible = "solomon,ssd1305fb-i2c";
reg = <0x3d>;
solomon,height = <64>;
@@ -334,6 +364,18 @@
vcc-supply = <&sw2_reg>;
status = "disabled";
};
+
+ touchkeys: keys@5a {
+ compatible = "fsl,mpr121-touchkey";
+ reg = <0x5a>;
+ vdd-supply = <&sw2_reg>;
+ autorepeat;
+ linux,keycodes = <KEY_1>, <KEY_2>, <KEY_3>, <KEY_4>, <KEY_5>,
+ <KEY_6>, <KEY_7>, <KEY_8>, <KEY_9>,
+ <KEY_BACKSPACE>, <KEY_0>, <KEY_ENTER>;
+ poll-interval = <50>;
+ status = "disabled";
+ };
};
&iomuxc {
@@ -451,6 +493,13 @@
>;
};
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098
+ MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098
+ >;
+ };
+
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098
@@ -524,7 +573,6 @@
};
&pwm1 {
- #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "disabled";
@@ -536,10 +584,17 @@
status = "okay";
};
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <®_usb_h1_vbus>;
+ over-current-active-low;
status = "disabled";
};
@@ -547,6 +602,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
vbus-supply = <®_usb_otg_vbus>;
+ over-current-active-low;
srp-disable;
hnp-disable;
adp-disable;
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts
index f979270..a19609c 100644
--- a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts
+++ b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts
@@ -25,15 +25,15 @@
status = "okay";
};
-&i2c3 {
- status = "okay";
-};
-
&leds {
status = "okay";
};
-&oled {
+&oled_1305 {
+ status = "okay";
+};
+
+&oled_1309 {
status = "okay";
};
@@ -45,6 +45,10 @@
status = "okay";
};
+&touchkeys {
+ status = "okay";
+};
+
&usdhc3 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-orion.dts b/arch/arm/boot/dts/imx6dl-yapp4-orion.dts
new file mode 100644
index 0000000..884b236
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-yapp4-orion.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2020 Y Soft Corporation, a.s.
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6dl-yapp4-common.dtsi"
+
+/ {
+ model = "Y Soft IOTA Orion i.MX6DualLite board";
+ compatible = "ysoft,imx6dl-yapp4-orion", "fsl,imx6dl";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0xf0000000>;
+ };
+};
+
+&gpio_oled {
+ status = "okay";
+};
+
+&leds {
+ status = "okay";
+};
+
+&oled_1305 {
+ status = "okay";
+};
+
+&oled_1309 {
+ status = "okay";
+};
+
+®_usb_h1_vbus {
+ status = "okay";
+};
+
+&touchkeys {
+ status = "okay";
+};
+
+&uart2 {
+ status = "disabled";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbphy2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts
index a1173bf..f6ae24e 100644
--- a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts
+++ b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts
@@ -17,6 +17,10 @@
};
};
+&aliases {
+ /delete-property/ ethernet1;
+};
+
&backlight {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 2ed1031..fdd81fd 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -44,6 +44,8 @@
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
cpu@1 {
@@ -64,6 +66,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -84,11 +87,7 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips1: aips-bus@2000000 {
- iomuxc: iomuxc@20e0000 {
- compatible = "fsl,imx6dl-iomuxc";
- };
-
+ aips1: bus@2000000 {
pxp: pxp@20f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
@@ -100,7 +99,7 @@
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -295,6 +294,10 @@
compatible = "fsl,imx6dl-hdmi";
};
+&iomuxc {
+ compatible = "fsl,imx6dl-iomuxc";
+};
+
&ipu1_csi1 {
ipu1_csi1_from_ipu1_csi1_mux: endpoint {
remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
index 0edd304..fab83ab 100644
--- a/arch/arm/boot/dts/imx6q-apalis-eval.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
@@ -1,44 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014-2017 Toradex AG
+ * Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -167,6 +131,19 @@
&i2c1 {
status = "okay";
+ /*
+ * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
+ * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+ */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+ status = "disabled";
+ };
+
pcie-switch@58 {
compatible = "plx,pex8605";
reg = <0x58>;
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
index b94bb68..1614b1a 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
@@ -1,44 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014-2017 Toradex AG
+ * Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -172,6 +136,19 @@
&i2c1 {
status = "okay";
+ /*
+ * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
+ * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+ */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+ status = "disabled";
+ };
+
/* M41T0M6 real time clock on carrier board */
rtc_i2c: rtc@68 {
compatible = "st,m41t0";
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 302fd6a..fa9f98d 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -1,44 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014-2017 Toradex AG
+ * Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@@ -171,6 +135,19 @@
&i2c1 {
status = "okay";
+ /*
+ * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
+ * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+ */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+ status = "disabled";
+ };
+
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
diff --git a/arch/arm/boot/dts/imx6q-apf6dev.dts b/arch/arm/boot/dts/imx6q-apf6dev.dts
index 07a36bb..664b0af 100644
--- a/arch/arm/boot/dts/imx6q-apf6dev.dts
+++ b/arch/arm/boot/dts/imx6q-apf6dev.dts
@@ -1,49 +1,6 @@
-/*
- * Copyright 2015 Armadeus Systems
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6q.dtsi"
diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
index fb09801..604f242 100644
--- a/arch/arm/boot/dts/imx6q-b450v3.dts
+++ b/arch/arm/boot/dts/imx6q-b450v3.dts
@@ -84,19 +84,19 @@
};
&pca9539 {
- P04 {
+ P04-hog {
gpio-hog;
gpios = <4 0>;
output-low;
line-name = "PCA9539-P04";
};
- P07 {
- gpio-hog;
- gpios = <7 0>;
- output-low;
- line-name = "PCA9539-P07";
- };
+ P07-hog {
+ gpio-hog;
+ gpios = <7 0>;
+ output-low;
+ line-name = "PCA9539-P07";
+ };
};
&pci_root {
diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
index 8f762d9..56d2aeb 100644
--- a/arch/arm/boot/dts/imx6q-b650v3.dts
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -84,12 +84,12 @@
};
&pca9539 {
- P07 {
- gpio-hog;
- gpios = <7 0>;
- output-low;
- line-name = "PCA9539-P07";
- };
+ P07-hog {
+ gpio-hog;
+ gpios = <7 0>;
+ output-low;
+ line-name = "PCA9539-P07";
+ };
};
&usbphy1 {
diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
index 1ea64ec..3d6b757 100644
--- a/arch/arm/boot/dts/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -199,14 +199,14 @@
};
&pca9539 {
- P10 {
+ P10-hog {
gpio-hog;
gpios = <8 0>;
output-low;
line-name = "PCA9539-P10";
};
- P11 {
+ P11-hog {
gpio-hog;
gpios = <9 0>;
output-low;
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
index 37c6340..e4578ed 100644
--- a/arch/arm/boot/dts/imx6q-ba16.dtsi
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -134,7 +134,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@@ -334,6 +334,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index 1938b04..2a98cc6 100644
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -102,10 +102,15 @@
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch: switch@0 {
compatible = "marvell,mv88e6085"; /* 88e6240*/
reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
switch_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -117,22 +122,32 @@
switchphy0: switchphy@0 {
reg = <0>;
+ interrupt-parent = <&switch>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy1: switchphy@1 {
reg = <1>;
+ interrupt-parent = <&switch>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy2: switchphy@2 {
reg = <2>;
+ interrupt-parent = <&switch>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy3: switchphy@3 {
reg = <3>;
+ interrupt-parent = <&switch>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy4: switchphy@4 {
reg = <4>;
+ interrupt-parent = <&switch>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
@@ -140,7 +155,7 @@
};
&ecspi5 {
- cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
status = "okay";
@@ -233,42 +248,42 @@
interrupt-parent = <&gpio2>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- P12 {
+ P12-hog {
gpio-hog;
gpios = <10 0>;
output-low;
line-name = "PCA9539-P12";
};
- P13 {
+ P13-hog {
gpio-hog;
gpios = <11 0>;
output-low;
line-name = "PCA9539-P13";
};
- P14 {
+ P14-hog {
gpio-hog;
gpios = <12 0>;
output-low;
line-name = "PCA9539-P14";
};
- P15 {
+ P15-hog {
gpio-hog;
gpios = <13 0>;
output-low;
line-name = "PCA9539-P15";
};
- P16 {
+ P16-hog {
gpio-hog;
gpios = <14 0>;
output-low;
line-name = "PCA9539-P16";
};
- P17 {
+ P17-hog {
gpio-hog;
gpios = <15 0>;
output-low;
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index cab9e92..bfb530f 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -255,7 +255,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index 1c46df6..a685b1c 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -22,6 +22,53 @@
clock-frequency = <24000000>;
};
+ display_bl: display-bl {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
+ default-brightness-level = <8>;
+ enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ lcd_display: disp0 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "edt,etm0700g0edh6";
+ ddc-i2c-bus = <&i2c2>;
+ backlight = <&display_bl>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx-sgtl5000";
@@ -43,6 +90,14 @@
status = "okay";
};
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "disabled";
+};
+
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
@@ -57,6 +112,15 @@
VDDA-supply = <®_3p3v>;
VDDIO-supply = <&sw2_reg>;
};
+
+ touchscreen@38 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touchscreen>;
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
+ };
};
&iomuxc {
@@ -69,9 +133,7 @@
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0
MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0
- MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0
@@ -124,6 +186,52 @@
>;
};
+ pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1-grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_touchscreen: touchscreen-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1
+ >;
+ };
+
pinctrl_pcie: pcie-grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1
@@ -131,6 +239,10 @@
};
};
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
@@ -138,6 +250,12 @@
status = "okay";
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
&ssi1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index 3233927..e3de2b4 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -51,17 +51,15 @@
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
- status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
- status = "okay";
};
&ecspi1 {
- cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio4 11 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi
index 83524bb..fef5d72 100644
--- a/arch/arm/boot/dts/imx6q-display5.dtsi
+++ b/arch/arm/boot/dts/imx6q-display5.dtsi
@@ -399,7 +399,6 @@
};
&pwm2 {
- #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index f9df207..fa2307d 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -99,7 +99,7 @@
&ecspi5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
- cs-gpios = <&gpio1 12 0>;
+ cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
flash: m25p80@0 {
diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts
index 57761f3..48fb47e 100644
--- a/arch/arm/boot/dts/imx6q-dms-ba16.dts
+++ b/arch/arm/boot/dts/imx6q-dms-ba16.dts
@@ -42,7 +42,7 @@
};
&ecspi5 {
- cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index b6e2b58..4cde45d 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -132,7 +132,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts
index ecc3989..d5d4690 100644
--- a/arch/arm/boot/dts/imx6q-gw54xx.dts
+++ b/arch/arm/boot/dts/imx6q-gw54xx.dts
@@ -15,19 +15,16 @@
sound-digital {
compatible = "simple-audio-card";
simple-audio-card,name = "tda1997x-audio";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sound_codec>;
+ simple-audio-card,frame-master = <&sound_codec>;
- simple-audio-card,dai-link@0 {
- format = "i2s";
+ sound_cpu: simple-audio-card,cpu {
+ sound-dai = <&ssi2>;
+ };
- cpu {
- sound-dai = <&ssi2>;
- };
-
- codec {
- bitclock-master;
- frame-master;
- sound-dai = <&hdmi_receiver>;
- };
+ sound_codec: simple-audio-card,codec {
+ sound-dai = <&hdmi_receiver>;
};
};
};
diff --git a/arch/arm/boot/dts/imx6q-gw5907.dts b/arch/arm/boot/dts/imx6q-gw5907.dts
new file mode 100644
index 0000000..b25526e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5907.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5907.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5907";
+ compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw5910.dts b/arch/arm/boot/dts/imx6q-gw5910.dts
new file mode 100644
index 0000000..6aafa2f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5910.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5910.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5910";
+ compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw5912.dts b/arch/arm/boot/dts/imx6q-gw5912.dts
new file mode 100644
index 0000000..4dcbd94
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5912.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5912.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5912";
+ compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-gw5913.dts b/arch/arm/boot/dts/imx6q-gw5913.dts
new file mode 100644
index 0000000..6f511f1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-gw5913.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-gw5913.dtsi"
+
+/ {
+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5913";
+ compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi
index 2618ecc..4d6a0c3 100644
--- a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi
@@ -14,10 +14,9 @@
/* Quad/Dual SoMs have 3 chip-select signals */
&ecspi4 {
- fsl,spi-num-chipselects = <3>;
- cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>,
- <&gpio3 29 GPIO_ACTIVE_HIGH>,
- <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
+ <&gpio3 29 GPIO_ACTIVE_LOW>,
+ <&gpio3 25 GPIO_ACTIVE_LOW>;
};
&pinctrl_ecspi4 {
diff --git a/arch/arm/boot/dts/imx6q-kp.dtsi b/arch/arm/boot/dts/imx6q-kp.dtsi
index 24c8169..1ade0bf 100644
--- a/arch/arm/boot/dts/imx6q-kp.dtsi
+++ b/arch/arm/boot/dts/imx6q-kp.dtsi
@@ -378,12 +378,14 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts
index d96ae54..46a4dde 100644
--- a/arch/arm/boot/dts/imx6q-logicpd.dts
+++ b/arch/arm/boot/dts/imx6q-logicpd.dts
@@ -9,11 +9,11 @@
/ {
model = "Logic PD i.MX6QD SOM-M3";
- compatible = "fsl,imx6q";
+ compatible = "logicpd,imx6q-logicpd", "fsl,imx6q";
backlight: backlight-lvds {
compatible = "pwm-backlight";
- pwms = <&pwm3 0 20000>;
+ pwms = <&pwm3 0 20000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <®_lcd>;
@@ -73,6 +73,16 @@
status = "okay";
};
+&i2c1 {
+ touchscreen@26 {
+ compatible = "ilitek,ili2117";
+ reg = <0x26>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touchscreen>;
+ interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
+ };
+};
+
&ldb {
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts
index 84b30bd..05ee283 100644
--- a/arch/arm/boot/dts/imx6q-marsboard.dts
+++ b/arch/arm/boot/dts/imx6q-marsboard.dts
@@ -111,8 +111,22 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
- phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ phy-handle = <&rgmii_phy>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Atheros AR8035 PHY */
+ rgmii_phy: ethernet-phy@4 {
+ reg = <4>;
+ interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <1000>;
+ };
+ };
};
&hdmi {
diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts
index a4d2954..55692c7 100644
--- a/arch/arm/boot/dts/imx6q-mccmon6.dts
+++ b/arch/arm/boot/dts/imx6q-mccmon6.dts
@@ -237,7 +237,6 @@
};
&pwm2 {
- #pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts
index 61347a5..52e3567 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -107,7 +107,7 @@
};
panel: panel {
- compatible = "innolux,n133hse-ea1", "simple-panel";
+ compatible = "innolux,n133hse-ea1";
backlight = <&backlight>;
};
@@ -455,6 +455,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6q-pico-dwarf.dts b/arch/arm/boot/dts/imx6q-pico-dwarf.dts
new file mode 100644
index 0000000..618d274
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-pico-dwarf.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-pico-pi.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard";
+ compatible = "technexion,imx6q-pico", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-pico-hobbit.dts b/arch/arm/boot/dts/imx6q-pico-hobbit.dts
new file mode 100644
index 0000000..7a66650
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-pico-hobbit.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-pico-hobbit.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard";
+ compatible = "technexion,imx6q-pico", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-pico-nymph.dts b/arch/arm/boot/dts/imx6q-pico-nymph.dts
new file mode 100644
index 0000000..fe5a7be
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-pico-nymph.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-pico-pi.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard";
+ compatible = "technexion,imx6q-pico", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-pico-pi.dts b/arch/arm/boot/dts/imx6q-pico-pi.dts
new file mode 100644
index 0000000..9413f0a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-pico-pi.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-pico-pi.dtsi"
+
+/ {
+ model = "TechNexion PICO-IMX6 Quad Board and PI baseboard";
+ compatible = "technexion,imx6q-pico", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts
index a31b17e..7a33e54 100644
--- a/arch/arm/boot/dts/imx6q-pistachio.dts
+++ b/arch/arm/boot/dts/imx6q-pistachio.dts
@@ -570,6 +570,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-prti6q.dts b/arch/arm/boot/dts/imx6q-prti6q.dts
new file mode 100644
index 0000000..b4605ed
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-prti6q.dts
@@ -0,0 +1,543 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2014 Protonic Holland
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-prti6q.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
+
+/ {
+ model = "Protonic PRTI6Q board";
+ compatible = "prt,prti6q", "fsl,imx6q";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0xf0000000>;
+ };
+
+ backlight_lcd: backlight-lcd {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 16 64 255>;
+ num-interpolated-steps = <16>;
+ default-brightness-level = <1>;
+ power-supply = <®_3v3>;
+ enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ };
+
+ can_osc: can-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+
+ led-debug0 {
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-debug1 {
+ function = LED_FUNCTION_SD;
+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
+ };
+
+ panel {
+ compatible = "kyo,tcg121xglp";
+ backlight = <&backlight_lcd>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_npd>;
+ enable-active-high;
+ gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "regulator-WL12xx";
+ startup-delay-us = <70000>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "prti6q-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Line", "Line In Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "External Speaker";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "External Speaker", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&ssi1>;
+ system-clock-frequency = <0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ bitclock-master;
+ frame-master;
+ };
+ };
+
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-in;
+ spdif-out;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+
+ mux-ssi1 {
+ fsl,audmux-port = <0>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN 0
+ IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
+ IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
+ IMX_AUDMUX_V2_PTCR_TFSDIR 0
+ IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
+ >;
+ };
+
+ mux-pins3 {
+ fsl,audmux-port = <2>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
+ 0 IMX_AUDMUX_V2_PDCR_TXRXEN
+ >;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
+ status = "okay";
+
+ can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can3>;
+ clocks = <&can_osc>;
+ interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <5000000>;
+ };
+
+ adc@1 {
+ compatible = "ti,adc128s052";
+ reg = <1>;
+ spi-max-frequency = <2000000>;
+ vref-supply = <®_3v3>;
+ };
+};
+
+&ecspi3 {
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&rgmii_phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Microchip KSZ9031RNX PHY */
+ rgmii_phy: ethernet-phy@0 {
+ reg = <0>;
+ interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <300>;
+ };
+ };
+};
+
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi>;
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ sgtl5000: audio-codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0xa>;
+ #sound-dai-cells = <0>;
+ clocks = <&clks 201>;
+ VDDA-supply = <®_3v3>;
+ VDDIO-supply = <®_3v3>;
+ VDDD-supply = <®_1v8>;
+ };
+};
+
+/* DDC */
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ adc@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* can2_l */
+ channel@4 {
+ reg = <4>;
+ ti,gain = <3>;
+ ti,datarate = <3>;
+ };
+
+ /* can2_h */
+ channel@5 {
+ reg = <5>;
+ ti,gain = <3>;
+ ti,datarate = <3>;
+ };
+
+ /* can1_l */
+ channel@6 {
+ reg = <6>;
+ ti,gain = <3>;
+ ti,datarate = <3>;
+ };
+
+ /* can1_h */
+ channel@7 {
+ reg = <7>;
+ ti,gain = <3>;
+ ti,datarate = <3>;
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&pwm1 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&ldb {
+ status = "okay";
+
+ lvds-channel@0 {
+ status = "okay";
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&sata {
+ status = "okay";
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif>;
+ status = "okay";
+};
+
+&ssi1 {
+ #sound-dai-cells = <0>;
+ fsl,mode = "ac97-slave";
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ non-removable;
+ vmmc-supply = <®_wifi>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ status = "okay";
+
+ wifi {
+ compatible = "ti,wl1271";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi>;
+ interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
+ ref-clock-frequency = "38400000";
+ tcxo-clock-frequency = "19200000";
+ };
+};
+
+&iomuxc {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
+ };
+
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
+ >;
+ };
+
+ pinctrl_can2: can2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b008
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b008
+ >;
+ };
+
+ pinctrl_can3: can3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ /* CS */
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
+ >;
+ };
+
+ pinctrl_ecspi2_cs: ecspi2csgrp {
+ fsl,pins = <
+ /* ADC128S022 CS */
+ MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
+
+ /* Phy reset */
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
+ >;
+ };
+
+ pinctrl_hdmi: hdmigrp {
+ fsl,pins = <
+ /* NOTE: DDC is done via I2C2, so DON'T
+ * configure DDC pins for HDMI!
+ */
+ MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
+ >;
+ };
+
+ /* DDC */
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_leds: ledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
+ MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg_id: usbotgidgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_wifi: wifigrp {
+ fsl,pins = <
+ /* WL12xx IRQ */
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880
+ >;
+ };
+
+ pinctrl_wifi_npd: wifinpd {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q-prtwd2.dts b/arch/arm/boot/dts/imx6q-prtwd2.dts
new file mode 100644
index 0000000..349959d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-prtwd2.dts
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2018 Protonic Holland
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-prti6q.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Protonic WD2 board";
+ compatible = "prt,prtwd2", "fsl,imx6q";
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_npd>;
+ reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
+ };
+
+ /* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */
+ i2c {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+ i2c-gpio,delay-us = <20>; /* ~10 kHz */
+ i2c-gpio,scl-output-only;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rmii";
+ clocks = <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>;
+ clock-names = "ipg", "ahb";
+ status = "okay";
+
+ fixed-link {
+ speed = <100>;
+ pause;
+ full-duplex;
+ };
+};
+
+&i2c3 {
+ adc@49 {
+ compatible = "ti,ads1015";
+ reg = <0x49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* V in */
+ channel@4 {
+ reg = <4>;
+ ti,gain = <1>;
+ ti,datarate = <3>;
+ };
+
+ /* I charge */
+ channel@5 {
+ reg = <5>;
+ ti,gain = <1>;
+ ti,datarate = <3>;
+ };
+
+ /* V bus */
+ channel@6 {
+ reg = <6>;
+ ti,gain = <1>;
+ ti,datarate = <3>;
+ };
+
+ /* nc */
+ channel@7 {
+ reg = <7>;
+ ti,gain = <1>;
+ ti,datarate = <3>;
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ no-1-8-v;
+ non-removable;
+ mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_eth_chg>;
+
+ pinctrl_can1phy: can1phy {
+ fsl,pins = <
+ /* CAN1_SR */
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ /* MX6QDL_ENET_PINGRP4 */
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x130b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
+ /* Phy reset */
+ MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0
+ /* nINTRP */
+ MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0
+
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1f8b0
+ MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f8b0
+ >;
+ };
+
+ pinctrl_usb_eth_chg: usbethchggrp {
+ fsl,pins = <
+ /* USB charging control */
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_wifi_npd: wifinpd {
+ fsl,pins = <
+ /* WL_REG_ON */
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
index bfff87c..343364d 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -16,6 +16,13 @@
stdout-path = &uart1;
};
+ aliases {
+ mmc0 = &usdhc2;
+ mmc1 = &usdhc3;
+ mmc2 = &usdhc4;
+ /delete-property/ mmc3;
+ };
+
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x80000000>;
@@ -99,8 +106,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ phy-handle = <&phy>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@4 {
+ reg = <4>;
+ qca,clk-out-frequency = <125000000>;
+ reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ };
+ };
};
&hdmi {
diff --git a/arch/arm/boot/dts/imx6q-tqma6a.dtsi b/arch/arm/boot/dts/imx6q-tqma6a.dtsi
new file mode 100644
index 0000000..ab4c07c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tqma6a.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include "imx6q.dtsi"
+#include "imx6qdl-tqma6a.dtsi"
+#include "imx6qdl-tqma6.dtsi"
+
+/ {
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q-tqma6b.dtsi b/arch/arm/boot/dts/imx6q-tqma6b.dtsi
new file mode 100644
index 0000000..7224c37
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tqma6b.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ */
+
+#include "imx6q.dtsi"
+#include "imx6qdl-tqma6b.dtsi"
+#include "imx6qdl-tqma6.dtsi"
+
+/ {
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts
index c54362f..6355035 100644
--- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts
+++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts
@@ -144,8 +144,8 @@
};
&ecspi1 {
- cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>,
- <&gpio4 10 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>,
+ <&gpio4 10 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -203,6 +203,7 @@
};
&pwm2 {
+ #pwm-cells = <2>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index d038f41..5277e39 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -49,6 +49,8 @@
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
cpu1: cpu@1 {
@@ -73,6 +75,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -107,6 +110,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -141,6 +145,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
@@ -161,7 +166,7 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips-bus@2000000 { /* AIPS1 */
+ bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
#address-cells = <1>;
@@ -177,10 +182,6 @@
status = "disabled";
};
};
-
- iomuxc: iomuxc@20e0000 {
- compatible = "fsl,imx6q-iomuxc";
- };
};
sata: sata@2200000 {
@@ -422,6 +423,10 @@
};
};
+&iomuxc {
+ compatible = "fsl,imx6q-iomuxc";
+};
+
&ipu1_csi1 {
ipu1_csi1_from_mipi_vc1: endpoint {
remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 7c4ad54..30fa349 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -1,44 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014-2017 Toradex AG
+ * Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
@@ -148,20 +112,22 @@
};
&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_flexcan1_default>;
+ pinctrl-1 = <&pinctrl_flexcan1_sleep>;
status = "disabled";
};
&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_flexcan2_default>;
+ pinctrl-1 = <&pinctrl_flexcan2_sleep>;
status = "disabled";
};
/* Apalis SPI1 */
&ecspi1 {
- cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "disabled";
@@ -169,7 +135,7 @@
/* Apalis SPI2 */
&ecspi2 {
- cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "disabled";
@@ -178,7 +144,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-handle = <ðphy>;
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
@@ -198,15 +164,18 @@
&hdmi {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hdmi_ddc>;
+ pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>;
status = "disabled";
};
/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -216,8 +185,11 @@
*/
&i2c2 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pfuze100@8 {
@@ -372,9 +344,9 @@
*/
&i2c3 {
clock-frequency = <100000>;
- pinctrl-names = "default", "recovery";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_recovery>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
@@ -399,6 +371,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "disabled";
@@ -599,19 +572,32 @@
>;
};
- pinctrl_flexcan1: flexcan1grp {
+ pinctrl_flexcan1_default: flexcan1defgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
>;
};
- pinctrl_flexcan2: flexcan2grp {
+ pinctrl_flexcan1_sleep: flexcan1slpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
+ >;
+ };
+
+ pinctrl_flexcan2_default: flexcan2defgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
>;
};
+ pinctrl_flexcan2_sleep: flexcan2slpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
+ >;
+ };
pinctrl_gpio_bl_on: gpioblon {
fsl,pins = <
@@ -646,6 +632,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
@@ -653,6 +646,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
@@ -660,7 +660,7 @@
>;
};
- pinctrl_i2c3_recovery: i2c3recoverygrp {
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
diff --git a/arch/arm/boot/dts/imx6qdl-apf6.dtsi b/arch/arm/boot/dts/imx6qdl-apf6.dtsi
index 4738c3c..b78ed79 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6.dtsi
@@ -1,66 +1,56 @@
-/*
- * Copyright 2015 Armadeus Systems
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Armadeus Systems <support@armadeus.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
+/ {
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <®_3p3v>;
+ };
+
+ usdhc1_pwrseq: usdhc1-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <15>;
+ power-off-delay-us = <70>;
+ };
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy1>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+ };
};
/* Bluetooth */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
status = "okay";
};
@@ -68,6 +58,12 @@
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ mmc-pwrseq = <&usdhc1_pwrseq>;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ cap-power-off-card;
+ keep-power-in-suspend;
non-removable;
status = "okay";
@@ -94,65 +90,63 @@
};
&iomuxc {
- apf6 {
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
- >;
- };
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
+ >;
+ };
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
- MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
- MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
- >;
- };
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
+ >;
+ };
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* WL_EN */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* WL_IRQ */
- >;
- };
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */
+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */
+ >;
+ };
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
- >;
- };
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
index 9fc1fa4..2577eb4 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
@@ -1,49 +1,6 @@
-/*
- * Copyright 2015 Armadeus Systems
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Armadeus Systems <support@armadeus.com>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -54,33 +11,35 @@
stdout-path = &uart4;
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 191000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <0>;
+ power-supply = <®_5v>;
+ };
+
disp0 {
compatible = "fsl,imx-parallel-display";
- interface-pix-fmt = "bgr666";
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_disp1>;
+ pinctrl-0 = <&pinctrl_ipu1_disp0>;
- display-timings {
- lw700 {
- clock-frequency = <33000033>;
- hactive = <800>;
- vactive = <480>;
- hback-porch = <96>;
- hfront-porch = <96>;
- vback-porch = <20>;
- vfront-porch = <21>;
- hsync-len = <64>;
- vsync-len = <4>;
- hsync-active = <1>;
- vsync-active = <1>;
- de-active = <1>;
- pixelclk-active = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
};
};
- port {
- display_in: endpoint {
- remote-endpoint = <&ipu1_di0_disp0>;
+ port@1 {
+ reg = <1>;
+
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
};
};
};
@@ -111,17 +70,30 @@
};
};
+ panel {
+ compatible = "armadeus,st0700-adapt";
+ power-supply = <®_3p3v>;
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
+ vin-supply = <®_5v>;
};
- reg_usbh1_vbus: regulator-usb-h1-vbus {
+ reg_5v: regulator-5v {
compatible = "regulator-fixed";
- regulator-name = "usb_h1_vbus";
+ regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
@@ -166,6 +138,7 @@
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_5v>;
status = "okay";
};
@@ -212,6 +185,11 @@
VDDA-supply = <®_3p3v>;
VDDIO-supply = <®_3p3v>;
};
+
+ rtc@6f {
+ compatible = "microchip,mcp7940x";
+ reg = <0x6f>;
+ };
};
&i2c3 {
@@ -233,6 +211,7 @@
};
&pwm3 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
@@ -261,7 +240,7 @@
};
&usbh1 {
- vbus-supply = <®_usbh1_vbus>;
+ vbus-supply = <®_5v>;
phy_type = "utmi";
status = "okay";
};
@@ -297,178 +276,176 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
- apf6dev {
- pinctrl_audmux: audmuxgrp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
- MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
- >;
- };
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
- >;
- };
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ >;
+ };
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
- >;
- };
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
- pinctrl_gpio_keys: gpiokeysgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
- >;
- };
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
- pinctrl_gpio_leds: gpioledsgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0
- >;
- };
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0
+ >;
+ };
- pinctrl_gpios: gpiosgrp {
- fsl,pins = <
- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
- MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
- MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
- MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
- MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
- MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
- MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
- >;
- };
+ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
+ >;
+ };
- pinctrl_gsm: gsmgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */
- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */
- >;
- };
+ pinctrl_gsm: gsmgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */
+ >;
+ };
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
- >;
- };
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
- >;
- };
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
- >;
- };
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ >;
+ };
- pinctrl_ipu1_disp1: ipu1disp1grp {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1
- >;
- };
+ pinctrl_ipu1_disp0: ipu1disp0grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1
+ >;
+ };
- pinctrl_pcie: pciegrp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0
- >;
- };
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0
+ >;
+ };
- pinctrl_pwm3: pwm3grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
- >;
- };
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
- >;
- };
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
+ >;
+ };
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0
- >;
- };
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0
+ >;
+ };
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0
- MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0
- >;
- };
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0
+ >;
+ };
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
- >;
- };
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
+ >;
+ };
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
- pinctrl_spdif: spdifgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
- >;
- };
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
+ >;
+ };
- pinctrl_touchscreen: touchscreengrp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
- >;
- };
+ pinctrl_touchscreen: touchscreengrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
+ >;
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
index d954661..e21f6ac 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
@@ -91,7 +91,7 @@
};
&ecspi4 {
- cs-gpios = <&gpio3 20 0>;
+ cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
index 3767508..ead7ba2 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
@@ -110,23 +110,23 @@
};
&ecspi1 {
- cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH
- &gpio4 10 GPIO_ACTIVE_HIGH
- &gpio4 11 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW
+ &gpio4 10 GPIO_ACTIVE_LOW
+ &gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
};
&ecspi2 {
- cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW &gpio2 27 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
};
&ecspi4 {
- cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 29 GPIO_ACTIVE_LOW &gpio5 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";
@@ -336,6 +336,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi
new file mode 100644
index 0000000..7672fbf
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2020 Toradex
+ */
+
+&iomuxc {
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
+ >;
+ };
+};
+
+/* Colibri MMC */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
+ vmmc-supply = <®_module_3v3>;
+ vqmmc-supply = <&vgen3_reg>;
+ wakeup-source;
+ keep-power-in-suspend;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+};
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index 019dda6..4e2a309 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -1,44 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014-2016 Toradex AG
+ * Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
@@ -130,7 +94,7 @@
/* Colibri SSP */
&ecspi4 {
- cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "disabled";
@@ -166,8 +130,11 @@
*/
&i2c2 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-0 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pfuze100@8 {
@@ -226,7 +193,16 @@
regulator-always-on;
};
- /* vgen3: unused */
+ /*
+ * +V3.3_1.8_SD1 coming off VGEN3 and supplying
+ * the i.MX 6 NVCC_SD1.
+ */
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
@@ -312,9 +288,9 @@
*/
&i2c3 {
clock-frequency = <100000>;
- pinctrl-names = "default", "recovery";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_recovery>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
@@ -336,6 +312,7 @@
/* Colibri PWM<A> */
&pwm3 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "disabled";
@@ -386,7 +363,6 @@
};
&usbotg {
- pinctrl-names = "default";
disable-over-current;
dr_mode = "peripheral";
status = "disabled";
@@ -426,6 +402,9 @@
};
&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_oc_1>;
+
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
@@ -509,6 +488,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
+ MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
@@ -516,7 +502,7 @@
>;
};
- pinctrl_i2c3_recovery: i2c3recoverygrp {
+ pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
@@ -615,6 +601,13 @@
>;
};
+ pinctrl_usbh_oc_1: usbhoc1grp {
+ fsl,pins = <
+ /* USBH_OC */
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
+ >;
+ };
+
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
@@ -681,6 +674,13 @@
>;
};
+ pinctrl_usbc_id_1: usbc_id-1 {
+ fsl,pins = <
+ /* USBC_ID */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index e3be453..6704279 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -233,6 +233,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
index ebe7a8b..648f5fc 100644
--- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
@@ -30,7 +30,7 @@
};
&ecspi3 {
- cs-gpios = <&gpio4 24 0>;
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi
index 70d2661..7228b89 100644
--- a/arch/arm/boot/dts/imx6qdl-emcon.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi
@@ -168,8 +168,8 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
- cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>,
- <&gpio2 27 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>,
+ <&gpio2 27 GPIO_ACTIVE_LOW>;
};
&ecspi4 {
@@ -737,14 +737,17 @@
};
&pwm1 {
+ #pwm-cells = <2>;
status = "okay";
};
&pwm3 {
+ #pwm-cells = <2>;
status = "okay";
};
&pwm4 {
+ #pwm-cells = <2>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 419a7cd..3c04b5a 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@@ -19,6 +21,51 @@
bootargs = "console=ttymxc1,115200";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -102,6 +149,103 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_an1";
+ };
+
+ channel@23 {
+ gw,mode = <1>;
+ reg = <0x23>;
+ label = "vdd_2p5";
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
@@ -126,13 +270,6 @@
pagesize = <16>;
};
- gpio: pca9555@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
@@ -387,6 +524,7 @@
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 14d6fec..959d8ac 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@@ -28,6 +30,53 @@
default-brightness-level = <7>;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -134,7 +183,7 @@
};
&ecspi3 {
- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
@@ -165,6 +214,109 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_1p0";
+ };
+
+ channel@23 {
+ gw,mode = <1>;
+ reg = <0x23>;
+ label = "vdd_2p5";
+ };
+
+ channel@29 {
+ gw,mode = <1>;
+ reg = <0x29>;
+ label = "vdd_an1";
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
@@ -189,13 +341,6 @@
pagesize = <16>;
};
- gpio: pca9555@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
@@ -313,6 +458,11 @@
interrupts = <12 2>;
wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
};
+
+ accel@1e {
+ compatible = "nxp,fxos8700";
+ reg = <0x1e>;
+ };
};
&ldb {
@@ -360,6 +510,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
@@ -499,6 +650,7 @@
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 54b2bea..8072ed4 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@@ -28,6 +30,53 @@
default-brightness-level = <7>;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -158,6 +207,115 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_1p0";
+ };
+
+ channel@23 {
+ gw,mode = <1>;
+ reg = <0x23>;
+ label = "vdd_2p5";
+ };
+
+ channel@26 {
+ gw,mode = <1>;
+ reg = <0x26>;
+ label = "vdd_gps";
+ };
+
+ channel@29 {
+ gw,mode = <1>;
+ reg = <0x29>;
+ label = "vdd_an1";
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
@@ -182,13 +340,6 @@
pagesize = <16>;
};
- gpio: pca9555@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
@@ -304,6 +455,11 @@
interrupts = <11 2>;
wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
+
+ accel@1e {
+ compatible = "nxp,fxos8700";
+ reg = <0x1e>;
+ };
};
&ldb {
@@ -351,6 +507,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
@@ -481,6 +638,7 @@
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 1b6c133..8c9bcdd 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
@@ -29,6 +31,53 @@
default-brightness-level = <7>;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -164,7 +213,7 @@
};
&ecspi2 {
- cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
@@ -195,6 +244,117 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_1p0";
+ };
+
+ channel@23 {
+ gw,mode = <1>;
+ reg = <0x23>;
+ label = "vdd_2p5";
+ };
+
+ channel@26 {
+ gw,mode = <1>;
+ reg = <0x26>;
+ label = "vdd_gps";
+ };
+ };
+
+ fan-controller@2c {
+ compatible = "gw,gsc-fan";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2c>;
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
@@ -219,13 +379,6 @@
pagesize = <16>;
};
- gpio: pca9555@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
@@ -361,6 +514,11 @@
interrupts = <12 2>;
wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
};
+
+ accel@1e {
+ compatible = "nxp,fxos8700";
+ reg = <0x1e>;
+ };
};
&ldb {
@@ -414,6 +572,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default", "state_dio";
pinctrl-0 = <&pinctrl_pwm4_backlight>;
pinctrl-1 = <&pinctrl_pwm4_dio>;
@@ -566,6 +725,7 @@
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 8c33510..e5d803d 100644
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -47,6 +47,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/tda1997x.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
@@ -63,6 +65,53 @@
bootargs = "console=ttymxc1,115200";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -167,6 +216,97 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8a";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_1p0b";
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
@@ -191,13 +331,6 @@
pagesize = <16>;
};
- gpio: pca9555@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
@@ -464,6 +597,7 @@
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index dc646b7..290a607 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@@ -20,6 +22,53 @@
bootargs = "console=ttymxc1,115200";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -92,6 +141,103 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_1p0";
+ };
+
+ channel@23 {
+ gw,mode = <1>;
+ reg = <0x23>;
+ label = "vdd_2p5";
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
@@ -116,13 +262,6 @@
pagesize = <16>;
};
- gpio: pca9555@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
@@ -258,6 +397,14 @@
status = "okay";
};
+&usbotg {
+ vbus-supply = <®_5p0v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
@@ -297,6 +444,7 @@
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
@@ -359,6 +507,12 @@
>;
};
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059
+ >;
+ };
+
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
index a106689..c15b9cc 100644
--- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
@@ -46,6 +46,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@@ -61,6 +63,51 @@
stdout-path = &uart2;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -130,11 +177,101 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- gpio: pca9555@23 {
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8a";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_1p0b";
+ };
+
+ channel@26 {
+ gw,mode = <1>;
+ reg = <0x26>;
+ label = "vdd_an1";
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
};
eeprom1: eeprom@50 {
@@ -173,6 +310,25 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+ magn@1c {
+ compatible = "st,lsm9ds1-magn";
+ reg = <0x1c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mag>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ imu@6a {
+ compatible = "st,lsm9ds1-imu";
+ reg = <0x6a>;
+ st,drdy-int-pin = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_imu>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
@@ -409,6 +565,7 @@
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
@@ -426,6 +583,12 @@
>;
};
+ pinctrl_imu: imugrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
+ >;
+ };
+
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
@@ -449,6 +612,12 @@
>;
};
+ pinctrl_mag: maggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
index e8e36df..093a219 100644
--- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
@@ -47,6 +47,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@@ -88,6 +89,53 @@
default-on;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -205,7 +253,7 @@
};
&ecspi3 {
- cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
@@ -243,6 +291,115 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_an1";
+ };
+
+ channel@23 {
+ gw,mode = <1>;
+ reg = <0x23>;
+ label = "vdd_2p5";
+ };
+
+ channel@26 {
+ gw,mode = <1>;
+ reg = <0x26>;
+ label = "vdd_gps";
+ };
+
+ channel@29 {
+ gw,mode = <1>;
+ reg = <0x29>;
+ label = "vdd_an2";
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
@@ -267,13 +424,6 @@
pagesize = <16>;
};
- pca9555: gpio@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
ds1672: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
@@ -295,6 +445,15 @@
VDDIO-supply = <®_3p3v>;
};
+ magn@1c {
+ compatible = "st,lsm9ds1-magn";
+ reg = <0x1c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mag>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <9 IRQ_TYPE_EDGE_RISING>;
+ };
+
tca8418: keypad@34 {
compatible = "ti,tca8418";
pinctrl-names = "default";
@@ -389,6 +548,16 @@
};
};
};
+
+ imu@6a {
+ compatible = "st,lsm9ds1-imu";
+ reg = <0x6a>;
+ st,drdy-int-pin = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_imu>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
&i2c3 {
@@ -452,6 +621,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
@@ -589,6 +759,7 @@
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
>;
};
@@ -609,6 +780,12 @@
>;
};
+ pinctrl_imu: imugrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0
+ >;
+ };
+
pinctrl_keypad: keypadgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
@@ -616,6 +793,12 @@
>;
};
+ pinctrl_mag: maggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
index aee9221..e1c8dd2 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
@@ -46,6 +46,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
chosen {
@@ -71,6 +73,53 @@
default-brightness-level = <100>;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -183,11 +232,101 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- pca9555: gpio@23 {
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_an1";
+ };
+
+ channel@23 {
+ gw,mode = <1>;
+ reg = <0x23>;
+ label = "vdd_2p5";
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
};
eeprom1: eeprom@50 {
@@ -365,6 +504,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
index 6d21cc6..3cd2e71 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
@@ -46,6 +46,8 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
/* these are used by bootloader for disabling nodes */
@@ -68,6 +70,53 @@
default-brightness-level = <7>;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -205,11 +254,101 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- pca9555: gpio@23 {
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_an1";
+ };
+
+ channel@23 {
+ gw,mode = <1>;
+ reg = <0x23>;
+ label = "vdd_2p5";
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
};
eeprom1: eeprom@50 {
@@ -248,6 +387,15 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+ magn@1c {
+ compatible = "st,lsm9ds1-magn";
+ reg = <0x1c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mag>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <17 IRQ_TYPE_EDGE_RISING>;
+ };
+
ltc3676: pmic@3c {
compatible = "lltc,ltc3676";
reg = <0x3c>;
@@ -320,6 +468,16 @@
};
};
};
+
+ imu@6a {
+ compatible = "st,lsm9ds1-imu";
+ reg = <0x6a>;
+ st,drdy-int-pin = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_imu>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
&i2c3 {
@@ -382,6 +540,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
@@ -484,6 +643,7 @@
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
>;
};
@@ -501,6 +661,18 @@
>;
};
+ pinctrl_imu: imugrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
+ >;
+ };
+
+ pinctrl_mag: maggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi
new file mode 100644
index 0000000..21c68a5
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi
@@ -0,0 +1,538 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ /* these are used by bootloader for disabling nodes */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ nand = &gpmi;
+ usb0 = &usbh1;
+ usb1 = &usbotg;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+ default-state = "off";
+ };
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "5P0V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c3>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_an1";
+ };
+
+ channel@23 {
+ gw,mode = <1>;
+ reg = <0x23>;
+ label = "vdd_2p5";
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ ds1672@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ gpio@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ adc@48 {
+ compatible = "ti,ads1015";
+ reg = <0x48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@4 {
+ reg = <4>;
+ ti,gain = <0>;
+ ti,datarate = <5>;
+ };
+
+ channel@5 {
+ reg = <5>;
+ ti,gain = <0>;
+ ti,datarate = <5>;
+ };
+
+ channel@6 {
+ reg = <6>;
+ ti,gain = <0>;
+ ti,datarate = <5>;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+ status = "disabled";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
new file mode 100644
index 0000000..ed4e222
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
@@ -0,0 +1,666 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ /* these are used by bootloader for disabling nodes */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ led2 = &led2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+ default-state = "off";
+ };
+
+ led2: user3 {
+ label = "user3";
+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
+ default-state = "off";
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "5P0V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_wl: regulator-wl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wl>;
+ compatible = "regulator-fixed";
+ regulator-name = "wl";
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+
+&ecspi3 {
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@8 {
+ gw,mode = <3>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vdd_vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ gw,voltage-offset-microvolt = <800000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vdd_5p0";
+ gw,voltage-divider-ohms = <22100 10000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_2p5";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_3p0";
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_arm";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_soc";
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_1p5";
+ };
+
+ channel@98 {
+ gw,mode = <2>;
+ reg = <0x98>;
+ label = "vdd_1p8";
+ };
+
+ channel@9a {
+ gw,mode = <2>;
+ reg = <0x9a>;
+ label = "vdd_1p0";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@9c {
+ gw,mode = <2>;
+ reg = <0x9c>;
+ label = "vdd_an1";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ accel@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <13 0>;
+ interrupt-names = "INT1";
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+ status = "disabled";
+};
+
+/* off-board RS232 */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* serial console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* cc1352 */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* Sterling-LWB Bluetooth */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* GPS */
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_5p0v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+/* Sterling-LWB SDIO WiFi */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ vmmc-supply = <®_wl>;
+ non-removable;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl_accel: accelmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
+ >;
+ };
+
+ pinctrl_bten: btengrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
+ >;
+ };
+
+ pinctrl_ecspi3: escpi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
+ MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
+ MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
+ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
+ MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
+ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
new file mode 100644
index 0000000..797f160
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
@@ -0,0 +1,608 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ /* these are used by bootloader for disabling nodes */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ led2 = &led2;
+ nand = &gpmi;
+ usb0 = &usbh1;
+ usb1 = &usbotg;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+ default-state = "off";
+ };
+
+ led2: user3 {
+ label = "user3";
+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
+ default-state = "off";
+ };
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_vbus: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ gw,mode = <0>;
+ reg = <0x00>;
+ label = "temp";
+ };
+
+ channel@2 {
+ gw,mode = <1>;
+ reg = <0x02>;
+ label = "vdd_vin";
+ };
+
+ channel@5 {
+ gw,mode = <1>;
+ reg = <0x05>;
+ label = "vdd_3p3";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@b {
+ gw,mode = <1>;
+ reg = <0x0b>;
+ label = "vdd_5p0";
+ };
+
+ channel@e {
+ gw,mode = <1>;
+ reg = <0xe>;
+ label = "vdd_arm";
+ };
+
+ channel@11 {
+ gw,mode = <1>;
+ reg = <0x11>;
+ label = "vdd_soc";
+ };
+
+ channel@14 {
+ gw,mode = <1>;
+ reg = <0x14>;
+ label = "vdd_3p0";
+ };
+
+ channel@17 {
+ gw,mode = <1>;
+ reg = <0x17>;
+ label = "vdd_1p5";
+ };
+
+ channel@1d {
+ gw,mode = <1>;
+ reg = <0x1d>;
+ label = "vdd_1p8";
+ };
+
+ channel@20 {
+ gw,mode = <1>;
+ reg = <0x20>;
+ label = "vdd_1p0";
+ };
+
+ channel@23 {
+ gw,mode = <1>;
+ reg = <0x23>;
+ label = "vdd_2p5";
+ };
+ };
+
+ fan-controller@a {
+ compatible = "gw,gsc-fan";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0a>;
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ accel@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <13 0>;
+ interrupt-names = "INT1";
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
+ status = "disabled";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+ status = "disabled";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_vbus>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_3p3v>;
+ no-1-8-v; /* firmware will remove if board revision supports */
+ status = "okay";
+};
+
+&wdog1 {
+ status = "disabled";
+};
+
+&wdog2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_accel: accelmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi2: escpi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
new file mode 100644
index 0000000..4cd7d29
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ /* these are used by bootloader for disabling nodes */
+ aliases {
+ led0 = &led0;
+ led1 = &led1;
+ nand = &gpmi;
+ usb0 = &usbh1;
+ usb1 = &usbotg;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key-erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
+ default-state = "off";
+ };
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x20000000>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "5P0V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@8 {
+ gw,mode = <3>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vdd_vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ gw,voltage-offset-microvolt = <800000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vdd_5p0";
+ gw,voltage-divider-ohms = <22100 10000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_2p5";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_arm";
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_soc";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_1p5";
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_1p0";
+ };
+
+ channel@98 {
+ gw,mode = <2>;
+ reg = <0x98>;
+ label = "vdd_3p0";
+ };
+
+ channel@9a {
+ gw,mode = <2>;
+ reg = <0x9a>;
+ label = "vdd_an1";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+ };
+
+ gsc_gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+ status = "disabled";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+ status = "disabled";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
index e423133..eb1ad28 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
@@ -203,7 +203,7 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>;
- cs-gpios = <&gpio2 26 0>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi b/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi
index d91d46b..0fd7f2e 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi
@@ -25,10 +25,8 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>;
- phy-mode = "rmii";
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index fde56f9..23c318d 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -150,10 +150,23 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
phy-mode = "rmii";
+ phy-handle = <ð_phy>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <4000>;
+ reset-deassert-us = <4000>;
+ };
+ };
};
&gpmi {
@@ -232,6 +245,7 @@
};
&pwm3 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index eea317b..92f9977 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -137,7 +137,7 @@
lcd_backlight: lcd-backlight {
compatible = "pwm-backlight";
- pwms = <&pwm4 0 5000000>;
+ pwms = <&pwm4 0 5000000 0>;
pwm-names = "LCD_BKLT_PWM";
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
@@ -245,16 +245,16 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
- cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>,
- <&gpio2 27 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>,
+ <&gpio2 27 GPIO_ACTIVE_LOW>;
};
/* SPI0 */
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
- cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>,
- <&gpio3 29 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
+ <&gpio3 29 GPIO_ACTIVE_LOW>;
status = "okay";
/* default boot source: workaround #1 for errata ERR006282 */
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index 2418cf8..d526f01 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -497,6 +497,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@@ -509,6 +510,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index c3415aa..a091782 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -316,7 +316,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@@ -736,12 +736,14 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
@@ -754,6 +756,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
index ed53f07..92d09a3 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -247,7 +247,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@@ -639,6 +639,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@@ -651,6 +652,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 8b0e432..1243677 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -232,7 +232,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio3 19 0>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@@ -596,6 +596,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@@ -608,6 +609,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
index 9ebd438..0199385 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
@@ -218,6 +218,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 3617089..33a70f4 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -71,7 +71,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
- cs-gpios = <&gpio4 24 0>;
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
som_flash: flash@0 {
compatible = "m25p80", "jedec,spi-nor";
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
index 31fa37d..41ebe45 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/dlg,da9063-regulator.h>
/ {
aliases {
@@ -87,7 +88,7 @@
reg = <0x50>;
};
- pmic@58 {
+ pmic: pmic@58 {
compatible = "dlg,da9062";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
@@ -95,13 +96,20 @@
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ gpio-controller;
+ #gpio-cells = <2>;
da9062_rtc: rtc {
compatible = "dlg,da9062-rtc";
};
+ da9062_onkey: onkey {
+ compatible = "dlg,da9062-onkey";
+ };
+
watchdog {
compatible = "dlg,da9062-watchdog";
+ dlg,use-sw-pm;
};
regulators {
@@ -109,6 +117,7 @@
regulator-name = "vdd_arm";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1380000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
regulator-always-on;
};
@@ -116,6 +125,7 @@
regulator-name = "vdd_soc";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1380000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
regulator-always-on;
};
@@ -123,6 +133,7 @@
regulator-name = "vdd_ddr3";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
regulator-always-on;
};
@@ -130,6 +141,7 @@
regulator-name = "vdd_eth";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
regulator-always-on;
};
diff --git a/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi b/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi
new file mode 100644
index 0000000..3a96878
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-pico-dwarf.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2017 NXP
+
+#include "imx6qdl-pico.dtsi"
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led {
+ label = "gpio-led";
+ gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+};
+
+&i2c1 {
+ mpl3115@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ };
+};
+
+&i2c2 {
+ io-expander@25 {
+ compatible = "nxp,pca9554";
+ reg = <0x25>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+};
+
+&iomuxc {
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi b/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi
new file mode 100644
index 0000000..144c472
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-pico-hobbit.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2017 NXP
+
+#include "imx6qdl-pico.dtsi"
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led {
+ label = "gpio-led";
+ gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+};
+
+&i2c2 {
+ status = "okay";
+
+ adc081c: adc@50 {
+ compatible = "ti,adc081c";
+ reg = <0x50>;
+ vref-supply = <®_3p3v>;
+ };
+};
+
+&iomuxc {
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi b/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi
new file mode 100644
index 0000000..3d56a42
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-pico-nymph.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+
+#include "imx6qdl-pico.dtsi"
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led {
+ label = "gpio-led";
+ gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+};
+
+&i2c1 {
+ adc@52 {
+ compatible = "ti,adc081c";
+ reg = <0x52>;
+ vref-supply = <®_2p5v>;
+ };
+};
+
+&i2c2 {
+ io-expander@25 {
+ compatible = "nxp,pca9554";
+ reg = <0x25>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+};
+
+&i2c3 {
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi b/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi
new file mode 100644
index 0000000..b823dce
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-pico-pi.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2017 NXP
+
+#include "imx6qdl-pico.dtsi"
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led {
+ label = "gpio-led";
+ gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+};
+
+&hdmi {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-pico.dtsi b/arch/arm/boot/dts/imx6qdl-pico.dtsi
new file mode 100644
index 0000000..f7a56d6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-pico.dtsi
@@ -0,0 +1,628 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2018 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ reg_2p5v: regulator-2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_1p5v: regulator-1p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P5V";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ reg_2p8v: regulator-2p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg_vbus>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ };
+
+ codec_osc: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx6-pico-sgtl5000";
+ ssi-controller = <&ssi1>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <3>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 50000 0>;
+ brightness-levels = <0 36 72 108 144 180 216 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ reg_lcd_3v3: regulator-lcd-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_lcd>;
+ regulator-name = "lcd-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ lcd_display: disp0 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ lcd_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "vxt,vl050-8048nt-c01";
+ backlight = <&backlight>;
+ power-supply = <®_lcd_3v3>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
+ phy-handle = <&phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@1 {
+ reg = <1>;
+ qca,clk-out-frequency = <125000000>;
+ };
+ };
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ sgtl5000: audio-codec@a {
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ compatible = "fsl,sgtl5000";
+ clocks = <&codec_osc>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_1p8v>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ wakeup-source;
+ };
+
+ camera@3c {
+ compatible = "ovti,ov5645";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5645>;
+ reg = <0x3c>;
+ clocks = <&clks IMX6QDL_CLK_CKO2>;
+ clock-names = "xclk";
+ clock-frequency = <24000000>;
+ vdddo-supply = <®_1p8v>;
+ vdda-supply = <®_2p8v>;
+ vddd-supply = <®_1p5v>;
+ enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+
+ port {
+ ov5645_to_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+&ipu1_di0_disp0 {
+ remote-endpoint = <&lcd_display_in>;
+};
+
+&mipi_csi {
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_csi2_in: endpoint {
+ remote-endpoint = <&ov5645_to_mipi_csi2>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie_reset>;
+ reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&ssi1 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 { /* Bluetooth module */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usdhc2 { /* Wifi/BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */
+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */
+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */
+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */
+ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */
+ MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */
+ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */
+ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */
+ >;
+ };
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0
+ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_ipu1: ipu1grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
+ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
+ >;
+ };
+
+ pinctrl_ov5645: ov5645grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x0b0b0
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0
+ MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
+ >;
+ };
+
+ pinctrl_pcie_reset: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_reg_lcd: reglcdgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usbotg_vbus: usbotgvbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-prti6q.dtsi b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
new file mode 100644
index 0000000..19578f6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-prti6q.dtsi
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2014 Protonic Holland
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb_h1_vbus: regulator-h1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "h1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg_vbus: regulator-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "otg-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ temperature-sensor@70 {
+ compatible = "ti,tmp103";
+ reg = <0x70>;
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ phy_type = "utmi";
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ phy_type = "utmi";
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_can1: can1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b008
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b008
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
+ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
index 97f1659..de514eb 100644
--- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -132,6 +132,19 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+ pca9535: gpio-expander@27 {
+ compatible = "nxp,pca9535";
+ reg = <0x27>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9535>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
eeprom@57 {
compatible = "atmel,24c02";
reg = <0x57>;
@@ -237,6 +250,12 @@
>;
};
+ pinctrl_pca9535: pca9535grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index cf62846..afe477f 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -267,7 +267,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio3 19 0>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
status = "disabled"; /* pin conflict with WEIM NOR */
@@ -800,6 +800,7 @@
};
&pwm3 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 8468216..fdc3aa9 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -308,7 +308,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio3 19 0>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@@ -687,18 +687,21 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index fe59dde..f824c9a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -105,9 +105,13 @@
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
- "IN3R", "AMIC";
+ "IN3R", "AMIC",
+ "DMIC", "MICBIAS",
+ "DMICDAT", "DMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
+ hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>;
+ mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
backlight_lvds: backlight-lvds {
@@ -185,7 +189,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio4 9 0>;
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@@ -203,8 +207,21 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ phy-handle = <&phy>;
+ fsl,magic-packet;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@1 {
+ reg = <1>;
+ qca,clk-out-frequency = <125000000>;
+ reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ };
+ };
};
&hdmi {
@@ -728,6 +745,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-savageboard.dtsi b/arch/arm/boot/dts/imx6qdl-savageboard.dtsi
index a616e3c..02e6d36 100644
--- a/arch/arm/boot/dts/imx6qdl-savageboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-savageboard.dtsi
@@ -140,6 +140,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
index f264924..c56337b 100644
--- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
@@ -63,6 +63,25 @@
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * The PHY can appear at either address 0 or 4 due to the
+ * configuration (LED) pin not being pulled sufficiently.
+ */
+ ethernet-phy@0 {
+ reg = <0>;
+ qca,clk-out-frequency = <125000000>;
+ };
+
+ ethernet-phy@4 {
+ reg = <4>;
+ qca,clk-out-frequency = <125000000>;
+ };
+ };
};
&iomuxc {
diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi
new file mode 100644
index 0000000..b18b83a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "supply-3p3v";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ m25p80: flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ };
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099
+ /* eCSPI1 SS1 */
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+};
+
+&pmic {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ reg_vddcore: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ };
+
+ reg_vddsoc: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ };
+
+ reg_gen_3v3: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_ddr_1v5a: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-always-on;
+ };
+
+ reg_ddr_1v5b: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5v_600mA: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ regulator-always-on;
+ };
+
+ reg_snvs_3v: vsnvs {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ reg_vrefddr: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vgen1_1v5: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ /* not used */
+ };
+
+ reg_vgen2_1v2_eth: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-always-on;
+ };
+
+ reg_vgen3_2v8: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_vgen4_1v8: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_vgen5_1v8_eth: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_vgen6_3v3: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ vmmc-supply = <®_3p3v>;
+ non-removable;
+ disable-wp;
+ no-sd;
+ no-sdio;
+ bus-width = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ mmccard: mmccard@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi
new file mode 100644
index 0000000..b679bec
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ pmic: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+ };
+
+ sensor@48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ };
+
+ eeprom@50 {
+ compatible = "st,24c64", "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi
new file mode 100644
index 0000000..49c4722
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com>
+ */
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ pmic: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+ };
+
+ sensor@48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ };
+
+ eeprom@50 {
+ compatible = "st,24c64", "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi
index 267c956..f88da75 100644
--- a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi
@@ -95,7 +95,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@@ -108,7 +108,7 @@
};
&ecspi2 {
- cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi
index f0be516..e6aa0c3 100644
--- a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi
@@ -165,7 +165,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@@ -179,9 +179,9 @@
&ecspi2 {
cs-gpios = <
- &gpio5 31 GPIO_ACTIVE_HIGH
- &gpio7 12 GPIO_ACTIVE_HIGH
- &gpio5 18 GPIO_ACTIVE_HIGH
+ &gpio5 31 GPIO_ACTIVE_LOW
+ &gpio7 12 GPIO_ACTIVE_LOW
+ &gpio5 18 GPIO_ACTIVE_LOW
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index c68cb90..362e65c 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -738,14 +738,12 @@
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
- #pwm-cells = <3>;
status = "disabled";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
- #pwm-cells = <3>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
index 16672cb..ccfa8e3 100644
--- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -5,6 +5,8 @@
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*/
+#include <dt-bindings/gpio/gpio.h>
+
/ {
aliases {
backlight = &backlight;
@@ -210,6 +212,14 @@
>;
};
+ pinctrl_usbotg: usbotg {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059
+ MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059
+ >;
+ };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
@@ -218,6 +228,7 @@
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
>;
};
@@ -287,10 +298,16 @@
status = "okay";
};
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ status = "okay";
+};
+
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
- non-removable;
+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 2cfb411..5bad982 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -279,8 +279,19 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
+ phy-handle = <ðphy>;
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@1 {
+ reg = <1>;
+ qca,clk-out-frequency = <125000000>;
+ };
+ };
};
&mipi_csi {
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index a66c4fa..66b1574 100644
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -60,18 +60,6 @@
regulator-always-on;
};
- reg_5p0v_user_usb: regulator-5p0v-user-usb {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_user_usb>;
- vin-supply = <®_5p0v_main>;
- regulator-name = "5V_USER_USB";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
- startup-delay-us = <1000>;
- };
-
reg_3p3v_pmic: regulator-3p3v-pmic {
compatible = "regulator-fixed";
vin-supply = <®_12p0v>;
@@ -228,6 +216,13 @@
};
};
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
+};
+
&cpu0 {
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
@@ -321,7 +316,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
@@ -331,6 +326,39 @@
};
};
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio3_hog>;
+
+ usb-emulation {
+ gpio-hog;
+ gpios = <19 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "usb-emulation";
+ };
+
+ usb-mode1 {
+ gpio-hog;
+ gpios = <20 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-mode1";
+ };
+
+ usb-pwr {
+ gpio-hog;
+ gpios = <22 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "usb-pwr-ctrl-en-n";
+ };
+
+ usb-mode2 {
+ gpio-hog;
+ gpios = <23 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-mode2";
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
@@ -358,8 +386,10 @@
compatible = "fsl,mma8451";
reg = <0x1c>;
interrupt-parent = <&gpio1>;
- interrupt-names = "int1", "int2";
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT2";
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <®_3p3v>;
+ vddio-supply = <®_3p3v>;
};
hpa2: amp@60 {
@@ -590,6 +620,16 @@
status = "disabled";
};
+ reg_5p0v_user_usb: charger@32 {
+ compatible = "microchip,ucs1002";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ucs1002_pins>;
+ reg = <0x32>;
+ interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>,
+ <&gpio3 21 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "a_det", "alert";
+ };
+
hpa1: amp@60 {
compatible = "ti,tpa6130a2";
pinctrl-names = "default";
@@ -679,6 +719,8 @@
mdio {
#address-cells = <1>;
#size-cells = <0>;
+ clock-frequency = <12500000>;
+ suppress-preamble;
status = "okay";
switch: switch@0 {
@@ -850,7 +892,6 @@
&iomuxc {
pinctrl_accel: accelgrp {
fsl,pins = <
- MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x4001b000
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x4001b000
>;
};
@@ -936,6 +977,15 @@
>;
};
+ pinctrl_gpio3_hog: gpio3hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
@@ -983,12 +1033,6 @@
>;
};
- pinctrl_reg_user_usb: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x40000038
- >;
- };
-
pinctrl_rmii_phy_irq: phygrp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x40010000
@@ -1048,6 +1092,13 @@
>;
};
+ pinctrl_ucs1002_pins: ucs1002grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0
+ >;
+ };
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x10059
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index bc488df..7a8837c 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -69,16 +69,6 @@
};
};
- tempmon: tempmon {
- compatible = "fsl,imx6q-tempmon";
- interrupt-parent = <&gpc>;
- interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
- fsl,tempmon = <&anatop>;
- fsl,tempmon-data = <&ocotp>;
- clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
- #thermal-sensor-cells = <0>;
- };
-
ldb: ldb {
#address-cells = <1>;
#size-cells = <0>;
@@ -169,7 +159,7 @@
clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
};
- gpmi: gpmi-nand@112000 {
+ gpmi: nand-controller@112000 {
compatible = "fsl,imx6q-gpmi-nand";
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
reg-names = "gpmi-nand", "bch";
@@ -255,7 +245,7 @@
interrupt-parent = <&intc>;
};
- L2: l2-cache@a02000 {
+ L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -294,7 +284,7 @@
status = "disabled";
};
- aips-bus@2000000 { /* AIPS1 */
+ bus@2000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -509,7 +499,7 @@
};
pwm1: pwm@2080000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -520,7 +510,7 @@
};
pwm2: pwm@2084000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -531,7 +521,7 @@
};
pwm3: pwm@2088000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -542,7 +532,7 @@
};
pwm4: pwm@208c000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
@@ -574,7 +564,7 @@
status = "disabled";
};
- gpt: gpt@2098000 {
+ gpt: timer@2098000 {
compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -661,7 +651,7 @@
#interrupt-cells = <2>;
};
- kpp: kpp@20b8000 {
+ kpp: keypad@20b8000 {
compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -669,14 +659,14 @@
status = "disabled";
};
- wdog1: wdog@20bc000 {
+ wdog1: watchdog@20bc000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_IPG>;
};
- wdog2: wdog@20c0000 {
+ wdog2: watchdog@20c0000 {
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -684,7 +674,7 @@
status = "disabled";
};
- clks: ccm@20c4000 {
+ clks: clock-controller@20c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
@@ -794,6 +784,17 @@
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6q-tempmon";
+ interrupt-parent = <&gpc>;
+ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ #thermal-sensor-cells = <0>;
+ };
};
usbphy1: usbphy@20c9000 {
@@ -857,7 +858,7 @@
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
};
- src: src@20d8000 {
+ src: reset-controller@20d8000 {
compatible = "fsl,imx6q-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -870,8 +871,7 @@
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
- interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
- <0 90 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
clocks = <&clks IMX6QDL_CLK_IPG>;
clock-names = "ipg";
@@ -908,7 +908,7 @@
};
};
- iomuxc: iomuxc@20e0000 {
+ iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
reg = <0x20e0000 0x4000>;
};
@@ -935,14 +935,14 @@
};
};
- aips-bus@2100000 { /* AIPS2 */
+ bus@2100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
- crypto: caam@2100000 {
+ crypto: crypto@2100000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
@@ -954,13 +954,13 @@
<&clks IMX6QDL_CLK_EIM_SLOW>;
clock-names = "mem", "aclk", "ipg", "emi_slow";
- sec_jr0: jr0@1000 {
+ sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
- sec_jr1: jr1@2000 {
+ sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -1043,8 +1043,10 @@
<0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET_REF>,
<&clks IMX6QDL_CLK_ENET_REF>;
- clock-names = "ipg", "ahb", "ptp";
+ clock-names = "ipg", "ahb", "ptp", "enet_out";
+ fsl,stop-mode = <&gpr 0x34 27>;
status = "disabled";
};
@@ -1055,7 +1057,7 @@
<0 126 IRQ_TYPE_LEVEL_HIGH>;
};
- usdhc1: usdhc@2190000 {
+ usdhc1: mmc@2190000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -1067,7 +1069,7 @@
status = "disabled";
};
- usdhc2: usdhc@2194000 {
+ usdhc2: mmc@2194000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -1079,7 +1081,7 @@
status = "disabled";
};
- usdhc3: usdhc@2198000 {
+ usdhc3: mmc@2198000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -1091,7 +1093,7 @@
status = "disabled";
};
- usdhc4: usdhc@219c000 {
+ usdhc4: mmc@219c000 {
compatible = "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -1160,10 +1162,24 @@
status = "disabled";
};
- ocotp: ocotp@21bc000 {
+ ocotp: efuse@21bc000 {
compatible = "fsl,imx6q-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6QDL_CLK_IIM>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
+
+ tempmon_calib: calib@38 {
+ reg = <0x38 4>;
+ };
+
+ tempmon_temp_grade: temp-grade@20 {
+ reg = <0x20 4>;
+ };
};
tzasc@21d0000 { /* TZASC1 */
diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts
index d4caeeb..2bb3bfb 100644
--- a/arch/arm/boot/dts/imx6qp-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6qp-sabreauto.dts
@@ -47,7 +47,12 @@
};
&pcie {
- status = "disabled";
+ reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
};
&vgen3_reg {
diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts
index f1b9cb1..480e731 100644
--- a/arch/arm/boot/dts/imx6qp-sabresd.dts
+++ b/arch/arm/boot/dts/imx6qp-sabresd.dts
@@ -53,3 +53,7 @@
&pcie {
status = "disabled";
};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qp-tqma6b.dtsi b/arch/arm/boot/dts/imx6qp-tqma6b.dtsi
new file mode 100644
index 0000000..bb6ff7c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-tqma6b.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ */
+
+#include "imx6q.dtsi"
+#include "imx6qp.dtsi"
+#include "imx6qdl-tqma6b.dtsi"
+#include "imx6qdl-tqma6.dtsi"
+
+/ {
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi
index d91f92f..b310f13 100644
--- a/arch/arm/boot/dts/imx6qp.dtsi
+++ b/arch/arm/boot/dts/imx6qp.dtsi
@@ -18,7 +18,7 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
- aips-bus@2100000 {
+ bus@2100000 {
pre1: pre@21c8000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021c8000 0x1000>;
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index bc86cfa..25f6f2f 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -94,6 +94,8 @@
sound {
compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
@@ -106,6 +108,7 @@
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
+ hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
};
panel {
@@ -129,7 +132,7 @@
};
&ecspi1 {
- cs-gpios = <&gpio4 11 0>;
+ cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@@ -343,6 +346,12 @@
>;
};
+ pinctrl_hp: hpgrp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
@@ -575,6 +584,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts
new file mode 100644
index 0000000..caa2796
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts
@@ -0,0 +1,588 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree for the Tolino Shine 2 HD ebook reader
+ *
+ * Name on mainboard is: 37NB-E60QF0+4A2 or 37NB-E60QF0+4A3
+ * Serials start with: E60QF2
+ *
+ * Copyright 2020 Andreas Kemnade
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sl.dtsi"
+
+/ {
+ model = "Tolino Shine 2 HD";
+ compatible = "kobo,tolino-shine2hd", "fsl,imx6sl";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ cover {
+ label = "Cover";
+ gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ wakeup-source;
+ };
+
+ fl {
+ label = "Frontlight";
+ gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_BRIGHTNESS_CYCLE>;
+ };
+
+ home {
+ label = "Home";
+ gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOME>;
+ };
+
+ power {
+ label = "Power";
+ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+
+ on {
+ label = "tolinoshine2hd:white:on";
+ gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_power>;
+ regulator-name = "SD3_SPWR";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+ post-power-on-delay-ms = <20>;
+ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_sleep>;
+ status = "okay";
+
+ /* TODO: embedded controller at 0x43 (driver missing) */
+
+};
+
+&i2c2 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_sleep>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ zforce: touchscreen@50 {
+ compatible = "neonode,zforce";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_zforce>;
+ reg = <0x50>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&ldo1_reg>;
+ reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ x-size = <1072>;
+ y-size = <1448>;
+ };
+
+ /* TODO: TPS65185 PMIC for E Ink at 0x68 */
+
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ ricoh619: pmic@32 {
+ compatible = "ricoh,rc5t619";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ricoh_gpio>;
+ reg = <0x32>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ system-power-controller;
+
+ regulators {
+ dcdc1_reg: DCDC1 {
+ regulator-name = "DCDC1";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <900000>;
+ regulator-suspend-min-microvolt = <900000>;
+ };
+ };
+
+ /* Core3_3V3 */
+ dcdc2_reg: DCDC2 {
+ regulator-name = "DCDC2";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <3100000>;
+ regulator-suspend-min-microvolt = <3100000>;
+ };
+ };
+
+ dcdc3_reg: DCDC3 {
+ regulator-name = "DCDC3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1140000>;
+ regulator-suspend-min-microvolt = <1140000>;
+ };
+ };
+
+ /* Core4_1V2 */
+ dcdc4_reg: DCDC4 {
+ regulator-name = "DCDC4";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1140000>;
+ regulator-suspend-min-microvolt = <1140000>;
+ };
+ };
+
+ /* Core4_1V8 */
+ dcdc5_reg: DCDC5 {
+ regulator-name = "DCDC5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <1700000>;
+ regulator-suspend-min-microvolt = <1700000>;
+ };
+ };
+
+ /* IR_3V3 */
+ ldo1_reg: LDO1 {
+ regulator-name = "LDO1";
+ regulator-boot-on;
+ };
+
+ /* Core1_3V3 */
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-max-microvolt = <3000000>;
+ regulator-suspend-min-microvolt = <3000000>;
+ };
+ };
+
+ /* Core5_1V2 */
+ ldo3_reg: LDO3 {
+ regulator-name = "LDO3";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-boot-on;
+ };
+
+ /* SPD_3V3 */
+ ldo5_reg: LDO5 {
+ regulator-name = "LDO5";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* DDR_0V6 */
+ ldo6_reg: LDO6 {
+ regulator-name = "LDO6";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* VDD_PWM */
+ ldo7_reg: LDO7 {
+ regulator-name = "LDO7";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /* ldo_1v8 */
+ ldo8_reg: LDO8 {
+ regulator-name = "LDO8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-name = "LDO9";
+ regulator-boot-on;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "LDO10";
+ regulator-boot-on;
+ };
+
+ ldortc1_reg: LDORTC1 {
+ regulator-name = "LDORTC1";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059
+ MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059
+ MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x17059
+ MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x17059
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79
+ MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79
+ MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79
+ MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79
+ MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79
+ MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79
+ MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79
+ MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79
+ MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79
+ MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79
+ MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79
+ MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79
+ MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79
+ MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79
+ MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79
+ MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79
+ MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79
+ MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79
+ MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79
+ MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79
+ MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79
+ MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79
+ MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79
+ MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79
+ MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79
+ MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
+ MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
+ MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
+ MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79
+ MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79
+ MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79
+ MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
+ MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79
+ MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x79
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c1_sleep: i2c1grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c2_sleep: i2c2grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
+ MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059
+ >;
+ };
+
+ pinctrl_ricoh_gpio: ricoh_gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */
+ MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
+ MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
+ MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
+ MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9
+ MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9
+ MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9
+ MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
+ MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
+ MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1
+ MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1
+ MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1
+ MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1
+ >;
+ };
+
+ pinctrl_wifi_power: wifi-powergrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
+ >;
+ };
+
+ pinctrl_wifi_reset: wifi-resetgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */
+ >;
+ };
+
+ pinctrl_zforce: zforcegrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */
+ MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x10059 /* TP_RST */
+ >;
+ };
+};
+
+®_vdd1p1 {
+ vin-supply = <&dcdc2_reg>;
+};
+
+®_vdd2p5 {
+ vin-supply = <&dcdc2_reg>;
+};
+
+®_arm {
+ vin-supply = <&dcdc3_reg>;
+};
+
+®_soc {
+ vin-supply = <&dcdc1_reg>;
+};
+
+®_pu {
+ vin-supply = <&dcdc1_reg>;
+};
+
+&snvs_rtc {
+ /*
+ * We are using the RTC in the PMIC, but this one is not disabled
+ * in imx6sl.dtsi.
+ */
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>;
+ non-removable;
+ status = "okay";
+
+ /* internal uSD card */
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+ vmmc-supply = <®_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ cap-power-off-card;
+ non-removable;
+ status = "okay";
+
+ /*
+ * 37NB-E60QF0+4A2: CyberTan WC121 (BCM43362) SDIO WiFi
+ * 37NB-E60QF0+4A3: RTL8189F SDIO WiFi
+ */
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ disable-over-current;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
new file mode 100644
index 0000000..27143ea
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Device tree for the Tolino Shine 3 ebook reader
+ *
+ * Name on mainboard is: 37NB-E60K00+4A4
+ * Serials start with: E60K02 (a number also seen in
+ * vendor kernel sources)
+ *
+ * This mainboard seems to be equipped with different SoCs.
+ * In the Toline Shine 3 ebook reader it is a i.MX6SL
+ *
+ * Copyright 2019 Andreas Kemnade
+ * based on works
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sl.dtsi"
+#include "e60k02.dtsi"
+
+/ {
+ model = "Tolino Shine 3";
+ compatible = "kobo,tolino-shine3", "fsl,imx6sl";
+};
+
+&gpio_keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+};
+
+&i2c1 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_sleep>;
+};
+
+&i2c2 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_sleep>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */
+ MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 /* HALL_EN */
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79
+ MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79
+ MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79
+ MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79
+ MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79
+ MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79
+ MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79
+ MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79
+ MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79
+ MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79
+ MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79
+ MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79
+ MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79
+ MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79
+ MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79
+ MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79
+ MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79
+ MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79
+ MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79
+ MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79
+ MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79
+ MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79
+ MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79
+ MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79
+ MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79
+ MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
+ MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
+ MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
+ MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79
+ MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79
+ MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79
+ MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
+ MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79
+ MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x79
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c1_sleep: i2c1grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c2_sleep: i2c2grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
+ MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059
+ >;
+ };
+
+ pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */
+ >;
+ };
+
+ pinctrl_ricoh_gpio: ricoh_gpiogrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */
+ MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
+ MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
+ MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
+ MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9
+ MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9
+ MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9
+ MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3grp-sleep {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
+ MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
+ MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1
+ MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1
+ MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1
+ MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1
+ >;
+ };
+
+ pinctrl_wifi_power: wifi-powergrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
+ >;
+ };
+
+ pinctrl_wifi_reset: wifi-resetgrp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */
+ >;
+ };
+};
+
+&leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+};
+
+&lm3630a {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
+};
+
+®_wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_power>;
+};
+
+®_vdd1p1 {
+ vin-supply = <&dcdc2_reg>;
+};
+
+®_vdd2p5 {
+ vin-supply = <&dcdc2_reg>;
+};
+
+&ricoh619 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ricoh_gpio>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>;
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+};
+
+&wifi_pwrseq {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 540880f..91a8c54 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -74,6 +74,8 @@
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -91,15 +93,6 @@
};
};
- tempmon: tempmon {
- compatible = "fsl,imx6q-tempmon";
- interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gpc>;
- fsl,tempmon = <&anatop>;
- fsl,tempmon-data = <&ocotp>;
- clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
- };
-
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&gpc>;
@@ -133,7 +126,7 @@
interrupt-parent = <&intc>;
};
- L2: l2-cache@a02000 {
+ L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -143,7 +136,7 @@
arm,data-latency = <4 2 3>;
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -341,7 +334,7 @@
};
pwm1: pwm@2080000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -351,7 +344,7 @@
};
pwm2: pwm@2084000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -361,7 +354,7 @@
};
pwm3: pwm@2088000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -371,7 +364,7 @@
};
pwm4: pwm@208c000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
@@ -380,7 +373,7 @@
clock-names = "ipg", "per";
};
- gpt: gpt@2098000 {
+ gpt: timer@2098000 {
compatible = "fsl,imx6sl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -491,7 +484,7 @@
<&iomuxc 21 161 1>;
};
- kpp: kpp@20b8000 {
+ kpp: keypad@20b8000 {
compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -499,14 +492,14 @@
status = "disabled";
};
- wdog1: wdog@20bc000 {
+ wdog1: watchdog@20bc000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_IPG>;
};
- wdog2: wdog@20c0000 {
+ wdog2: watchdog@20c0000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -514,7 +507,7 @@
status = "disabled";
};
- clks: ccm@20c4000 {
+ clks: clock-controller@20c4000 {
compatible = "fsl,imx6sl-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
@@ -525,7 +518,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6sl-anatop",
"fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>,
@@ -625,6 +618,16 @@
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6q-tempmon";
+ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gpc>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
+ };
};
usbphy1: usbphy@20c9000 {
@@ -675,7 +678,7 @@
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
};
- src: src@20d8000 {
+ src: reset-controller@20d8000 {
compatible = "fsl,imx6sl-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -728,7 +731,7 @@
reg = <0x020e0000 0x38>;
};
- iomuxc: iomuxc@20e0000 {
+ iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6sl-iomuxc";
reg = <0x020e0000 0x4000>;
};
@@ -777,7 +780,7 @@
power-domains = <&pd_disp>;
};
- dcp: dcp@20fc000 {
+ dcp: crypto@20fc000 {
compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
reg = <0x020fc000 0x4000>;
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
@@ -786,7 +789,7 @@
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -851,7 +854,7 @@
status = "disabled";
};
- usdhc1: usdhc@2190000 {
+ usdhc1: mmc@2190000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -863,7 +866,7 @@
status = "disabled";
};
- usdhc2: usdhc@2194000 {
+ usdhc2: mmc@2194000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -875,7 +878,7 @@
status = "disabled";
};
- usdhc3: usdhc@2198000 {
+ usdhc3: mmc@2198000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -887,7 +890,7 @@
status = "disabled";
};
- usdhc4: usdhc@219c000 {
+ usdhc4: mmc@219c000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -951,10 +954,24 @@
status = "disabled";
};
- ocotp: ocotp@21bc000 {
+ ocotp: efuse@21bc000 {
compatible = "fsl,imx6sl-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SL_CLK_OCOTP>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
+
+ tempmon_calib: calib@38 {
+ reg = <0x38 4>;
+ };
+
+ tempmon_temp_grade: temp-grade@20 {
+ reg = <0x20 4>;
+ };
};
audmux: audmux@21d8000 {
diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts
index 5ace9e6..32b3d82 100644
--- a/arch/arm/boot/dts/imx6sll-evk.dts
+++ b/arch/arm/boot/dts/imx6sll-evk.dts
@@ -132,6 +132,31 @@
};
};
};
+
+ sound {
+ compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hp>;
+ model = "wm8962-audio";
+ audio-cpu = <&ssi2>;
+ audio-codec = <&wm8962>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Ext Spk", "SPKOUTL",
+ "Ext Spk", "SPKOUTR",
+ "AMIC", "MICBIAS",
+ "IN3R", "AMIC";
+ mux-int-port = <2>;
+ mux-ext-port = <3>;
+ hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux3>;
+ status = "okay";
};
&cpu0 {
@@ -247,6 +272,27 @@
};
};
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ wm8962: audio-codec@1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
+ DCVDD-supply = <&vgen3_reg>;
+ DBVDD-supply = <®_aud3v>;
+ AVDD-supply = <&vgen3_reg>;
+ CPVDD-supply = <&vgen3_reg>;
+ MICVDD-supply = <®_aud3v>;
+ PLLVDD-supply = <&vgen3_reg>;
+ SPKVDD1-supply = <®_aud4v>;
+ SPKVDD2-supply = <®_aud4v>;
+ };
+};
+
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
@@ -260,6 +306,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@@ -273,6 +320,10 @@
status = "okay";
};
+&ssi2 {
+ status = "okay";
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -329,6 +380,22 @@
};
&iomuxc {
+ pinctrl_audmux3: audmux3grp {
+ fsl,pins = <
+ MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
+ MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
+ MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
+ MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
+ MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
+ >;
+ };
+
+ pinctrl_hp: hpgrp {
+ fsl,pins = <
+ MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
+ >;
+ };
+
pinctrl_reg_sd3_vmmc: sd3vmmcgrp {
fsl,pins = <
MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059
@@ -448,6 +515,13 @@
>;
};
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1
+ MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1
+ >;
+ };
+
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79
diff --git a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts b/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts
new file mode 100644
index 0000000..7214d1c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Device tree for the Kobo Clara HD ebook reader
+ *
+ * Name on mainboard is: 37NB-E60K00+4A4
+ * Serials start with: E60K02 (a number also seen in
+ * vendor kernel sources)
+ *
+ * This mainboard seems to be equipped with different SoCs.
+ * In the Kobo Clara HD ebook reader it is an i.MX6SLL
+ *
+ * Copyright 2019 Andreas Kemnade
+ * based on works
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sll.dtsi"
+#include "e60k02.dtsi"
+
+/ {
+ model = "Kobo Clara HD";
+ compatible = "kobo,clarahd", "fsl,imx6sll";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <393216000>;
+};
+
+&cpu0 {
+ arm-supply = <&dcdc3_reg>;
+ soc-supply = <&dcdc1_reg>;
+};
+
+&gpio_keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+};
+
+&i2c1 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_sleep>;
+};
+
+&i2c2 {
+ pinctrl-names = "default","sleep";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_sleep>;
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */
+ MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x17059 /* HALL_EN */
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x79
+ MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79
+ MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x79
+ MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x79
+ MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79
+ MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79
+ MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79
+ MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79
+ MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79
+ MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79
+ MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79
+ MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79
+ MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79
+ MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79
+ MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79
+ MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79
+ MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79
+ MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79
+ MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79
+ MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79
+ MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79
+ MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79
+ MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79
+ MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79
+ MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79
+ MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79
+ MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79
+ MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79
+ MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79
+ MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79
+ MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79
+ MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79
+ MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x79
+ MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x79
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1
+ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c1_sleep: i2c1grp-sleep {
+ fsl,pins = <
+ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1
+ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1
+ MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_i2c2_sleep: i2c2grp-sleep {
+ fsl,pins = <
+ MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1
+ MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
+ MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059
+ >;
+ };
+
+ pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */
+ >;
+ };
+
+ pinctrl_ricoh_gpio: ricoh-gpiogrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */
+ MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
+ MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+ MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9
+ MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9
+ MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9
+ MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9
+ MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2grp-sleep {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x100f9
+ MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x100f9
+ MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x100f9
+ MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x100f9
+ MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x100f9
+ MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x100f9
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9
+ MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9
+ MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9
+ MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9
+ MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc3_sleep: usdhc3grp-sleep {
+ fsl,pins = <
+ MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1
+ MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1
+ MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1
+ MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1
+ MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1
+ MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1
+ >;
+ };
+
+ pinctrl_wifi_power: wifi-powergrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */
+ >;
+ };
+
+ pinctrl_wifi_reset: wifi-resetgrp {
+ fsl,pins = <
+ MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */
+ >;
+ };
+};
+
+&leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+};
+
+&lm3630a {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
+};
+
+®_wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_power>;
+};
+
+&ricoh619 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ricoh_gpio>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>;
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc3_sleep>;
+};
+
+&wifi_pwrseq {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_reset>;
+};
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 13c7ba7..0b62220 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -72,6 +72,8 @@
<&clks IMX6SLL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -103,16 +105,6 @@
clock-output-names = "ipp_di1";
};
- tempmon: temperature-sensor {
- compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gpc>;
- fsl,tempmon = <&anatop>;
- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
- nvmem-cell-names = "calib", "temp_grade";
- clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
- };
-
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -134,7 +126,7 @@
interrupt-parent = <&intc>;
};
- L2: l2-cache@a02000 {
+ L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -144,7 +136,7 @@
arm,data-latency = <4 2 3>;
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -269,7 +261,7 @@
status = "disabled";
};
- ssi1: ssi-controller@2028000 {
+ ssi1: ssi@2028000 {
compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
@@ -282,7 +274,7 @@
status = "disabled";
};
- ssi2: ssi-controller@202c000 {
+ ssi2: ssi@202c000 {
compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -295,7 +287,7 @@
status = "disabled";
};
- ssi3: ssi-controller@2030000 {
+ ssi3: ssi@2030000 {
compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
@@ -329,7 +321,7 @@
clocks = <&clks IMX6SLL_CLK_PWM1>,
<&clks IMX6SLL_CLK_PWM1>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm2: pwm@2084000 {
@@ -339,7 +331,7 @@
clocks = <&clks IMX6SLL_CLK_PWM2>,
<&clks IMX6SLL_CLK_PWM2>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm3: pwm@2088000 {
@@ -349,7 +341,7 @@
clocks = <&clks IMX6SLL_CLK_PWM3>,
<&clks IMX6SLL_CLK_PWM3>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm4: pwm@208c000 {
@@ -359,7 +351,7 @@
clocks = <&clks IMX6SLL_CLK_PWM4>,
<&clks IMX6SLL_CLK_PWM4>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
gpt1: timer@2098000 {
@@ -507,7 +499,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6sll-anatop",
"fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x4000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@@ -529,6 +521,16 @@
anatop-max-voltage = <3400000>;
anatop-enable-bit = <0>;
};
+
+ tempmon: temperature-sensor {
+ compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gpc>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
+ };
};
usbphy1: usb-phy@20c9000 {
@@ -632,6 +634,15 @@
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
};
+ pxp: pxp@20f0000 {
+ compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
+ reg = <0x20f0000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_PXP>;
+ clock-names = "axi";
+ };
+
lcdif: lcd-controller@20f8000 {
compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
reg = <0x020f8000 0x4000>;
@@ -643,7 +654,7 @@
status = "disabled";
};
- dcp: dcp@20fc000 {
+ dcp: crypto@20fc000 {
compatible = "fsl,imx28-dcp";
reg = <0x020fc000 0x4000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
@@ -654,7 +665,7 @@
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -775,13 +786,24 @@
clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
};
- ocotp: ocotp-ctrl@21bc000 {
+ rngb: rng@21b4000 {
+ compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
+ reg = <0x021b4000 0x4000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_DUMMY>;
+ };
+
+ ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6sll-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SLL_CLK_OCOTP>;
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
+
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
index 832b5c5..66af78e 100644
--- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
+++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
@@ -229,6 +229,7 @@
};
&pwm4 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
@@ -484,31 +485,31 @@
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
- MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
- MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1
- MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1
+ MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x1b0b1
+ MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
- MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
- MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
- MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1
- MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1
+ MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1
+ MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1
+ MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x1b0b1
+ MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x1b0b1
>;
};
diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h
index aa194a2..f4dc462 100644
--- a/arch/arm/boot/dts/imx6sx-pinfunc.h
+++ b/arch/arm/boot/dts/imx6sx-pinfunc.h
@@ -42,8 +42,8 @@
#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0
-#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0
-#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x0024 0x036C 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX 0x0024 0x036C 0x0830 0x0 0x0
#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0
@@ -51,8 +51,8 @@
#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0
-#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1
-#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x0028 0x0370 0x0830 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX 0x0028 0x0370 0x0000 0x0 0x0
#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0
#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0
@@ -60,21 +60,23 @@
#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0
-#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0
-#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x002C 0x0374 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX 0x002C 0x0374 0x0838 0x0 0x0
#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1
#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0
#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0
-#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS 0x002C 0x0374 0x082C 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART1_DTE_CTS 0x002C 0x0374 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0
-#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1
-#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0
+#define MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x0030 0x0378 0x0838 0x0 0x1
+#define MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX 0x0030 0x0378 0x0000 0x0 0x0
#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1
#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
-#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS 0x0030 0x0378 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO07__UART1_DTE_RTS 0x0030 0x0378 0x082C 0x4 0x1
#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
@@ -83,7 +85,8 @@
#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0
#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1
-#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS 0x0034 0x037C 0x0834 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO08__UART2_DTE_CTS 0x0034 0x037C 0x0000 0x4 0x0
#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0
@@ -92,7 +95,8 @@
#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0
#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
-#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS 0x0038 0x0380 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO09__UART2_DTE_RTS 0x0038 0x0380 0x0834 0x4 0x1
#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
@@ -177,8 +181,8 @@
#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1
#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0
#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0
-#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0
-#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x005C 0x03A4 0x0858 0x4 0x0
+#define MX6SX_PAD_CSI_DATA04__UART6_DTE_TX 0x005C 0x03A4 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0
@@ -188,8 +192,8 @@
#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1
#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1
#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0
-#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1
-#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x0060 0x03A8 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA05__UART6_DTE_RX 0x0060 0x03A8 0x0858 0x4 0x1
#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0
@@ -199,7 +203,8 @@
#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1
#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2
#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0
-#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0
+#define MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x0064 0x03AC 0x0854 0x4 0x0
+#define MX6SX_PAD_CSI_DATA06__UART6_DTE_CTS 0x0064 0x03AC 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0
@@ -209,7 +214,8 @@
#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1
#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
-#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x0068 0x03B0 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA07__UART6_DTE_RTS 0x0068 0x03B0 0x0854 0x4 0x1
#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
@@ -218,7 +224,8 @@
#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0
#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1
#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1
-#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2
+#define MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS 0x006C 0x03B4 0x0844 0x3 0x2
+#define MX6SX_PAD_CSI_HSYNC__UART4_DTE_CTS 0x006C 0x03B4 0x0000 0x3 0x0
#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0
@@ -228,8 +235,8 @@
#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0
#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1
#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0
-#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2
-#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_MCLK__UART4_DCE_RX 0x0070 0x03B8 0x0848 0x3 0x2
+#define MX6SX_PAD_CSI_MCLK__UART4_DTE_TX 0x0070 0x03B8 0x0000 0x3 0x0
#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0
@@ -239,8 +246,8 @@
#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0
#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1
#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0
-#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3
-#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX 0x0074 0x03BC 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX 0x0074 0x03BC 0x0848 0x3 0x3
#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0
@@ -250,7 +257,8 @@
#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0
#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
-#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS 0x0078 0x03C0 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_VSYNC__UART4_DTE_RTS 0x0078 0x03C0 0x0844 0x3 0x3
#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
@@ -330,8 +338,8 @@
#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0
#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0
#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1
-#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2
-#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_COL__UART1_DCE_RX 0x0094 0x03DC 0x0830 0x3 0x2
+#define MX6SX_PAD_ENET2_COL__UART1_DTE_TX 0x0094 0x03DC 0x0000 0x3 0x0
#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3
#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0
#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1
@@ -341,8 +349,8 @@
#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0
#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2
#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1
-#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3
-#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_CRS__UART1_DCE_TX 0x0098 0x03E0 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_CRS__UART1_DTE_RX 0x0098 0x03E0 0x0830 0x3 0x3
#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1
#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0
#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1
@@ -352,7 +360,8 @@
#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0
#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0
#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1
-#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2
+#define MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS 0x009C 0x03E4 0x082C 0x3 0x2
+#define MX6SX_PAD_ENET2_RX_CLK__UART1_DTE_CTS 0x009C 0x03E4 0x0000 0x3 0x0
#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1
#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0
#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1
@@ -362,7 +371,8 @@
#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0
#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
-#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS 0x00A0 0x03E8 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_TX_CLK__UART1_DTE_RTS 0x00A0 0x03E8 0x082C 0x3 0x3
#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
@@ -371,7 +381,8 @@
#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0
#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0
-#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2
+#define MX6SX_PAD_KEY_COL0__UART6_DCE_RTS 0x00A4 0x03EC 0x0854 0x2 0x2
+#define MX6SX_PAD_KEY_COL0__UART6_DTE_CTS 0x00A4 0x03EC 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0
#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0
#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0
@@ -380,8 +391,8 @@
#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0
#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0
-#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2
-#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL1__UART6_DCE_TX 0x00A8 0x03F0 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL1__UART6_DTE_RX 0x00A8 0x03F0 0x0858 0x2 0x2
#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0
#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0
#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0
@@ -389,7 +400,8 @@
#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0
#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1
-#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2
+#define MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x00AC 0x03F4 0x084C 0x2 0x2
+#define MX6SX_PAD_KEY_COL2__UART5_DTE_CTS 0x00AC 0x03F4 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0
#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0
#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0
@@ -397,8 +409,8 @@
#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0
#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0
-#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2
-#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x00B0 0x03F8 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL3__UART5_DTE_RX 0x00B0 0x03F8 0x0850 0x2 0x2
#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0
#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0
#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0
@@ -414,7 +426,8 @@
#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0
#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
-#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS 0x00B8 0x0400 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW0__UART6_DTE_RTS 0x00B8 0x0400 0x0854 0x2 0x3
#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
@@ -423,8 +436,8 @@
#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0
#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0
-#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3
-#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW1__UART6_DCE_RX 0x00BC 0x0404 0x0858 0x2 0x3
+#define MX6SX_PAD_KEY_ROW1__UART6_DTE_TX 0x00BC 0x0404 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0
#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0
#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0
@@ -433,7 +446,8 @@
#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0
#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
-#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x00C0 0x0408 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW2__UART5_DTE_RTS 0x00C0 0x0408 0x084C 0x2 0x3
#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
@@ -441,8 +455,8 @@
#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0
#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0
#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0
-#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3
-#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x00C4 0x040C 0x0850 0x2 0x3
+#define MX6SX_PAD_KEY_ROW3__UART5_DTE_TX 0x00C4 0x040C 0x0000 0x2 0x0
#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1
#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1
#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0
@@ -815,7 +829,8 @@
#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0
-#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0
+#define MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS 0x0160 0x04A8 0x083C 0x3 0x0
+#define MX6SX_PAD_NAND_DATA04__UART3_DTE_CTS 0x0160 0x04A8 0x0000 0x3 0x0
#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0
#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0
@@ -825,7 +840,8 @@
#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
-#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS 0x0164 0x04AC 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA05__UART3_DTE_RTS 0x0164 0x04AC 0x083C 0x3 0x1
#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
@@ -835,8 +851,8 @@
#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0
-#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0
-#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA06__UART3_DCE_RX 0x0168 0x04B0 0x0840 0x3 0x0
+#define MX6SX_PAD_NAND_DATA06__UART3_DTE_TX 0x0168 0x04B0 0x0000 0x3 0x0
#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0
#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0
@@ -846,8 +862,8 @@
#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0
#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0
#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0
-#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1
-#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA07__UART3_DCE_TX 0x016C 0x04B4 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA07__UART3_DTE_RX 0x016C 0x04B4 0x0840 0x3 0x1
#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0
#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0
#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0
@@ -967,7 +983,8 @@
#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
-#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS 0x01A0 0x04E8 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_DATA0__UART3_DTE_RTS 0x01A0 0x04E8 0x083C 0x1 0x4
#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
@@ -975,7 +992,8 @@
#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0
-#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5
+#define MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS 0x01A4 0x04EC 0x083C 0x1 0x5
+#define MX6SX_PAD_QSPI1B_DATA1__UART3_DTE_CTS 0x01A4 0x04EC 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1
#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2
#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1
@@ -1007,8 +1025,8 @@
#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0
-#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4
-#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0
+#define MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX 0x01B4 0x04FC 0x0840 0x1 0x4
+#define MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX 0x01B4 0x04FC 0x0000 0x1 0x0
#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1
@@ -1016,8 +1034,8 @@
#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0
#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0
#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0
-#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5
-#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX 0x01B8 0x0500 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX 0x01B8 0x0500 0x0840 0x1 0x5
#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1
#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3
#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1
@@ -1224,8 +1242,8 @@
#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1
#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0
#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0
-#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2
-#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA0__UART2_DCE_RX 0x0228 0x0570 0x0838 0x4 0x2
+#define MX6SX_PAD_SD1_DATA0__UART2_DTE_TX 0x0228 0x0570 0x0000 0x4 0x0
#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0
@@ -1235,8 +1253,8 @@
#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1
#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0
#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0
-#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3
-#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA1__UART2_DCE_TX 0x022C 0x0574 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA1__UART2_DTE_RX 0x022C 0x0574 0x0838 0x4 0x3
#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0
@@ -1246,7 +1264,8 @@
#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1
#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
-#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS 0x0230 0x0578 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA2__UART2_DTE_RTS 0x0230 0x0578 0x0834 0x4 0x2
#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
@@ -1255,7 +1274,8 @@
#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1
#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2
#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0
-#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3
+#define MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS 0x0234 0x057C 0x0834 0x4 0x3
+#define MX6SX_PAD_SD1_DATA3__UART2_DTE_CTS 0x0234 0x057C 0x0000 0x4 0x0
#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0
#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0
#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2
@@ -1287,8 +1307,8 @@
#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3
#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0
#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0
-#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4
-#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA0__UART4_DCE_RX 0x0240 0x0588 0x0848 0x7 0x4
+#define MX6SX_PAD_SD2_DATA0__UART4_DTE_TX 0x0240 0x0588 0x0000 0x7 0x0
#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0
#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0
@@ -1298,8 +1318,8 @@
#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3
#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0
#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0
-#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5
-#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA1__UART4_DCE_TX 0x0244 0x058C 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA1__UART4_DTE_RX 0x0244 0x058C 0x0848 0x7 0x5
#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0
#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0
@@ -1309,8 +1329,8 @@
#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2
#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0
#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0
-#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4
-#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA2__UART6_DCE_RX 0x0248 0x0590 0x0858 0x7 0x4
+#define MX6SX_PAD_SD2_DATA2__UART6_DTE_TX 0x0248 0x0590 0x0000 0x7 0x0
#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0
#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0
@@ -1320,12 +1340,13 @@
#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2
#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0
#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4
-#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5
-#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA3__UART6_DCE_TX 0x024C 0x0594 0x0000 0x7 0x0
+#define MX6SX_PAD_SD2_DATA3__UART6_DTE_RX 0x024C 0x0594 0x0858 0x7 0x5
#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0
#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
-#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_CLK__UART4_DCE_CTS 0x0250 0x0598 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_CLK__UART4_DTE_RTS 0x0250 0x0598 0x0844 0x1 0x0
#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
@@ -1334,8 +1355,8 @@
#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0
#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0
-#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0
-#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_CMD__UART4_DCE_TX 0x0254 0x059C 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_CMD__UART4_DTE_RX 0x0254 0x059C 0x0848 0x1 0x0
#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0
#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0
#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1
@@ -1364,7 +1385,8 @@
#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0
#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0
-#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1
+#define MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS 0x0260 0x05A8 0x0844 0x1 0x1
+#define MX6SX_PAD_SD3_DATA2__UART4_DTE_CTS 0x0260 0x05A8 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0
#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0
#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0
@@ -1374,8 +1396,8 @@
#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0
#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0
#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0
-#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1
-#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_DATA3__UART4_DCE_RX 0x0264 0x05AC 0x0848 0x1 0x1
+#define MX6SX_PAD_SD3_DATA3__UART4_DTE_TX 0x0264 0x05AC 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0
#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0
#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0
@@ -1387,8 +1409,8 @@
#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0
#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0
-#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2
-#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x0268 0x05B0 0x0840 0x3 0x2
+#define MX6SX_PAD_SD3_DATA4__UART3_DTE_TX 0x0268 0x05B0 0x0000 0x3 0x0
#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0
@@ -1398,8 +1420,8 @@
#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0
-#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3
-#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x026C 0x05B4 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA5__UART3_DTE_RX 0x026C 0x05B4 0x0840 0x3 0x3
#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0
@@ -1409,7 +1431,8 @@
#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0
#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0
-#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2
+#define MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x0270 0x05B8 0x083C 0x3 0x2
+#define MX6SX_PAD_SD3_DATA6__UART3_DTE_CTS 0x0270 0x05B8 0x0000 0x3 0x0
#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0
@@ -1419,7 +1442,8 @@
#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0
#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
-#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x0274 0x05BC 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA7__UART3_DTE_RTS 0x0274 0x05BC 0x083C 0x3 0x3
#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
@@ -1488,8 +1512,8 @@
#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0
-#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0
-#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x0290 0x05D8 0x0850 0x2 0x0
+#define MX6SX_PAD_SD4_DATA4__UART5_DTE_TX 0x0290 0x05D8 0x0000 0x2 0x0
#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0
#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0
@@ -1499,8 +1523,8 @@
#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0
-#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1
-#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x0294 0x05DC 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA5__UART5_DTE_RX 0x0294 0x05DC 0x0850 0x2 0x1
#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0
#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0
@@ -1510,7 +1534,8 @@
#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0
-#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0
+#define MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS 0x0298 0x05E0 0x084C 0x2 0x0
+#define MX6SX_PAD_SD4_DATA6__UART5_DTE_CTS 0x0298 0x05E0 0x0000 0x2 0x0
#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0
#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0
@@ -1520,7 +1545,8 @@
#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0
#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
-#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS 0x029C 0x05E4 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA7__UART5_DTE_RTS 0x029C 0x05E4 0x084C 0x2 0x1
#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
@@ -1551,4 +1577,92 @@
#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0
#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0
+/* these are not supposed to be used any more and remove them after some time */
+#define MX6SX_PAD_GPIO1_IO04__UART1_RX MX6SX_PAD_GPIO1_IO04__UART1_DTE_RX
+#define MX6SX_PAD_GPIO1_IO04__UART1_TX MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX
+#define MX6SX_PAD_GPIO1_IO05__UART1_RX MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX
+#define MX6SX_PAD_GPIO1_IO05__UART1_TX MX6SX_PAD_GPIO1_IO05__UART1_DTE_TX
+#define MX6SX_PAD_GPIO1_IO06__UART2_RX MX6SX_PAD_GPIO1_IO06__UART2_DTE_RX
+#define MX6SX_PAD_GPIO1_IO06__UART2_TX MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX
+#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS
+#define MX6SX_PAD_GPIO1_IO07__UART2_RX MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX
+#define MX6SX_PAD_GPIO1_IO07__UART2_TX MX6SX_PAD_GPIO1_IO07__UART2_DTE_TX
+#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS
+#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS
+#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS
+#define MX6SX_PAD_CSI_DATA04__UART6_RX MX6SX_PAD_CSI_DATA04__UART6_DCE_RX
+#define MX6SX_PAD_CSI_DATA04__UART6_TX MX6SX_PAD_CSI_DATA04__UART6_DTE_TX
+#define MX6SX_PAD_CSI_DATA05__UART6_RX MX6SX_PAD_CSI_DATA05__UART6_DTE_RX
+#define MX6SX_PAD_CSI_DATA05__UART6_TX MX6SX_PAD_CSI_DATA05__UART6_DCE_TX
+#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS
+#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS
+#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS
+#define MX6SX_PAD_CSI_MCLK__UART4_RX MX6SX_PAD_CSI_MCLK__UART4_DCE_RX
+#define MX6SX_PAD_CSI_MCLK__UART4_TX MX6SX_PAD_CSI_MCLK__UART4_DTE_TX
+#define MX6SX_PAD_CSI_PIXCLK__UART4_RX MX6SX_PAD_CSI_PIXCLK__UART4_DTE_RX
+#define MX6SX_PAD_CSI_PIXCLK__UART4_TX MX6SX_PAD_CSI_PIXCLK__UART4_DCE_TX
+#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS
+#define MX6SX_PAD_ENET2_COL__UART1_RX MX6SX_PAD_ENET2_COL__UART1_DCE_RX
+#define MX6SX_PAD_ENET2_COL__UART1_TX MX6SX_PAD_ENET2_COL__UART1_DTE_TX
+#define MX6SX_PAD_ENET2_CRS__UART1_RX MX6SX_PAD_ENET2_CRS__UART1_DTE_RX
+#define MX6SX_PAD_ENET2_CRS__UART1_TX MX6SX_PAD_ENET2_CRS__UART1_DCE_TX
+#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS
+#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS
+#define MX6SX_PAD_KEY_COL0__UART6_RTS_B MX6SX_PAD_KEY_COL0__UART6_DCE_RTS
+#define MX6SX_PAD_KEY_COL1__UART6_RX MX6SX_PAD_KEY_COL1__UART6_DTE_RX
+#define MX6SX_PAD_KEY_COL1__UART6_TX MX6SX_PAD_KEY_COL1__UART6_DCE_TX
+#define MX6SX_PAD_KEY_COL2__UART5_RTS_B MX6SX_PAD_KEY_COL2__UART5_DCE_RTS
+#define MX6SX_PAD_KEY_COL3__UART5_RX MX6SX_PAD_KEY_COL3__UART5_DTE_RX
+#define MX6SX_PAD_KEY_COL3__UART5_TX MX6SX_PAD_KEY_COL3__UART5_DCE_TX
+#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS
+#define MX6SX_PAD_KEY_ROW1__UART6_RX MX6SX_PAD_KEY_ROW1__UART6_DCE_RX
+#define MX6SX_PAD_KEY_ROW1__UART6_TX MX6SX_PAD_KEY_ROW1__UART6_DTE_TX
+#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS
+#define MX6SX_PAD_KEY_ROW3__UART5_RX MX6SX_PAD_KEY_ROW3__UART5_DCE_RX
+#define MX6SX_PAD_KEY_ROW3__UART5_TX MX6SX_PAD_KEY_ROW3__UART5_DTE_TX
+#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS
+#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS
+#define MX6SX_PAD_NAND_DATA06__UART3_RX MX6SX_PAD_NAND_DATA06__UART3_DCE_RX
+#define MX6SX_PAD_NAND_DATA06__UART3_TX MX6SX_PAD_NAND_DATA06__UART3_DTE_TX
+#define MX6SX_PAD_NAND_DATA07__UART3_RX MX6SX_PAD_NAND_DATA07__UART3_DTE_RX
+#define MX6SX_PAD_NAND_DATA07__UART3_TX MX6SX_PAD_NAND_DATA07__UART3_DCE_TX
+#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS
+#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS
+#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX MX6SX_PAD_QSPI1B_SCLK__UART3_DCE_RX
+#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX MX6SX_PAD_QSPI1B_SCLK__UART3_DTE_TX
+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX MX6SX_PAD_QSPI1B_SS0_B__UART3_DTE_RX
+#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX MX6SX_PAD_QSPI1B_SS0_B__UART3_DCE_TX
+#define MX6SX_PAD_SD1_DATA0__UART2_RX MX6SX_PAD_SD1_DATA0__UART2_DCE_RX
+#define MX6SX_PAD_SD1_DATA0__UART2_TX MX6SX_PAD_SD1_DATA0__UART2_DTE_TX
+#define MX6SX_PAD_SD1_DATA1__UART2_RX MX6SX_PAD_SD1_DATA1__UART2_DTE_RX
+#define MX6SX_PAD_SD1_DATA1__UART2_TX MX6SX_PAD_SD1_DATA1__UART2_DCE_TX
+#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS
+#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS
+#define MX6SX_PAD_SD2_DATA0__UART4_RX MX6SX_PAD_SD2_DATA0__UART4_DCE_RX
+#define MX6SX_PAD_SD2_DATA0__UART4_TX MX6SX_PAD_SD2_DATA0__UART4_DTE_TX
+#define MX6SX_PAD_SD2_DATA1__UART4_RX MX6SX_PAD_SD2_DATA1__UART4_DTE_RX
+#define MX6SX_PAD_SD2_DATA1__UART4_TX MX6SX_PAD_SD2_DATA1__UART4_DCE_TX
+#define MX6SX_PAD_SD2_DATA2__UART6_RX MX6SX_PAD_SD2_DATA2__UART6_DCE_RX
+#define MX6SX_PAD_SD2_DATA2__UART6_TX MX6SX_PAD_SD2_DATA2__UART6_DTE_TX
+#define MX6SX_PAD_SD2_DATA3__UART6_RX MX6SX_PAD_SD2_DATA3__UART6_DTE_RX
+#define MX6SX_PAD_SD2_DATA3__UART6_TX MX6SX_PAD_SD2_DATA3__UART6_DCE_TX
+#define MX6SX_PAD_SD3_CLK__UART4_CTS_B MX6SX_PAD_SD3_CLK__UART4_DCE_CTS
+#define MX6SX_PAD_SD3_CMD__UART4_RX MX6SX_PAD_SD3_CMD__UART4_DTE_RX
+#define MX6SX_PAD_SD3_CMD__UART4_TX MX6SX_PAD_SD3_CMD__UART4_DCE_TX
+#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS
+#define MX6SX_PAD_SD3_DATA3__UART4_RX MX6SX_PAD_SD3_DATA3__UART4_DCE_RX
+#define MX6SX_PAD_SD3_DATA3__UART4_TX MX6SX_PAD_SD3_DATA3__UART4_DTE_TX
+#define MX6SX_PAD_SD3_DATA4__UART3_RX MX6SX_PAD_SD3_DATA4__UART3_DCE_RX
+#define MX6SX_PAD_SD3_DATA4__UART3_TX MX6SX_PAD_SD3_DATA4__UART3_DTE_TX
+#define MX6SX_PAD_SD3_DATA5__UART3_RX MX6SX_PAD_SD3_DATA5__UART3_DTE_RX
+#define MX6SX_PAD_SD3_DATA5__UART3_TX MX6SX_PAD_SD3_DATA5__UART3_DCE_TX
+#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS
+#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS
+#define MX6SX_PAD_SD4_DATA4__UART5_RX MX6SX_PAD_SD4_DATA4__UART5_DCE_RX
+#define MX6SX_PAD_SD4_DATA4__UART5_TX MX6SX_PAD_SD4_DATA4__UART5_DTE_TX
+#define MX6SX_PAD_SD4_DATA5__UART5_RX MX6SX_PAD_SD4_DATA5__UART5_DTE_RX
+#define MX6SX_PAD_SD4_DATA5__UART5_TX MX6SX_PAD_SD4_DATA5__UART5_DCE_TX
+#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS
+#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS
+
#endif /* __DTS_IMX6SX_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index e471956..83ee972 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -66,12 +66,68 @@
enable-active-high;
vin-supply = <®_can_en>;
};
+
+ reg_cs42888: cs42888_supply {
+ compatible = "regulator-fixed";
+ regulator-name = "cs42888_supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sound-cs42888 {
+ compatible = "fsl,imx6-sabreauto-cs42888",
+ "fsl,imx-audio-cs42888";
+ model = "imx-cs42888";
+ audio-cpu = <&esai>;
+ audio-asrc = <&asrc>;
+ audio-codec = <&cs42888>;
+ audio-routing =
+ "Line Out Jack", "AOUT1L",
+ "Line Out Jack", "AOUT1R",
+ "Line Out Jack", "AOUT2L",
+ "Line Out Jack", "AOUT2R",
+ "Line Out Jack", "AOUT3L",
+ "Line Out Jack", "AOUT3R",
+ "Line Out Jack", "AOUT4L",
+ "Line Out Jack", "AOUT4R",
+ "AIN1L", "Line In Jack",
+ "AIN1R", "Line In Jack",
+ "AIN2L", "Line In Jack",
+ "AIN2R", "Line In Jack";
+ };
+
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-in;
+ };
};
&anaclk2 {
clock-frequency = <24576000>;
};
+&clks {
+ assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
+ <&clks IMX6SX_PLL4_BYPASS>,
+ <&clks IMX6SX_CLK_PLL4_POST_DIV>;
+ assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>,
+ <&clks IMX6SX_PLL4_BYPASS_SRC>;
+ assigned-clock-rates = <0>, <0>, <24576000>;
+};
+
+&esai {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esai>;
+ assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>,
+ <&clks IMX6SX_CLK_ESAI_EXTAL>;
+ assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <0>, <24576000>;
+ status = "okay";
+};
+
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
@@ -193,6 +249,21 @@
>;
};
+ pinctrl_esai: esaigrp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
+ MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
+ MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
+ MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
+ MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
+ MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
+ MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
+ MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
+ MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
+ MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
+ >;
+ };
+
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
@@ -227,10 +298,16 @@
>;
};
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
>;
};
@@ -313,6 +390,17 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+ cs42888: cs42888@48 {
+ compatible = "cirrus,cs42888";
+ reg = <0x48>;
+ clocks = <&anaclk2 0>;
+ clock-names = "mclk";
+ VA-supply = <®_cs42888>;
+ VD-supply = <®_cs42888>;
+ VLS-supply = <®_cs42888>;
+ VLC-supply = <®_cs42888>;
+ };
+
touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
@@ -454,6 +542,14 @@
};
};
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif>;
+ assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
diff --git a/arch/arm/boot/dts/imx6sx-sdb-mqs.dts b/arch/arm/boot/dts/imx6sx-sdb-mqs.dts
new file mode 100644
index 0000000..a4ab2d3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb-mqs.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2014 Freescale Semiconductor, Inc.
+
+#include "imx6sx-sdb.dts"
+/ {
+
+ sound {
+ status = "disabled";
+ };
+
+ sound-mqs {
+ compatible = "fsl,imx6sx-sdb-mqs",
+ "fsl,imx-audio-mqs";
+ model = "mqs-audio";
+ audio-cpu = <&sai1>;
+ audio-asrc = <&asrc>;
+ audio-codec = <&mqs>;
+ };
+};
+
+&usdhc2 {
+ /* pin conflict with mqs*/
+ status = "disabled";
+};
+
+&mqs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mqs>;
+ clocks = <&clks IMX6SX_CLK_SAI1>;
+ clock-names = "mclk";
+ status = "okay";
+};
+
+&sai1 {
+ pinctrl-0 = <>;
+ status = "okay";
+};
+
+&ssi2 {
+ status = "disabled";
+};
+
+&sdma {
+ gpr = <&gpr>;
+ /* SDMA event remap for SAI1 */
+ fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
+};
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
index 91a7548..dce5dcf 100644
--- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -6,6 +6,7 @@
/ {
model = "Freescale i.MX6 SoloX SDB RevA Board";
+ compatible = "fsl,imx6sx-sdb-reva", "fsl,imx6sx";
};
&i2c1 {
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index 865528b..1351d7f 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -153,6 +153,8 @@
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hp>;
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
@@ -165,6 +167,7 @@
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <6>;
+ hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
};
panel {
@@ -179,6 +182,15 @@
};
};
};
+
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif",
+ "fsl,imx6sx-sdb-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-out;
+ };
+
};
&audmux {
@@ -281,6 +293,7 @@
};
&pwm3 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
@@ -296,6 +309,14 @@
status = "disabled";
};
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif>;
+ assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
&ssi2 {
status = "okay";
};
@@ -450,6 +471,12 @@
>;
};
+ pinctrl_hp: hpgrp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
@@ -505,6 +532,13 @@
>;
};
+ pinctrl_mqs: mqsgrp {
+ fsl,pins = <
+ MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
+ MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
@@ -562,19 +596,25 @@
>;
};
+ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
+ MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
- MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
- MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
- MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
- MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
+ MX6SX_PAD_KEY_ROW3__UART5_DCE_RX 0x1b0b1
+ MX6SX_PAD_KEY_COL3__UART5_DCE_TX 0x1b0b1
+ MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS 0x1b0b1
+ MX6SX_PAD_KEY_COL2__UART5_DCE_RTS 0x1b0b1
>;
};
diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
index 28563f2..5547916 100644
--- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
+++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
@@ -93,7 +93,7 @@
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
- cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -352,6 +352,12 @@
>;
};
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0
+ >;
+ };
+
pinctrl_pwm1: pwm1grp-1 {
fsl,pins = <
/* blue LED */
@@ -384,15 +390,15 @@
pinctrl_uart1: uart1grp {
fsl,pins = <
- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
- MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1
>;
};
@@ -490,19 +496,30 @@
};
};
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+ reset-gpio-active-high;
+ status = "okay";
+};
+
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm6 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
index 25d4aa9..ee64565 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi
@@ -235,28 +235,28 @@
pinctrl_uart1: uart1grp {
fsl,pins =
- <MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1>,
- <MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1>;
+ <MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1>,
+ <MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1>;
};
pinctrl_uart2: uart2grp {
fsl,pins =
- <MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1>,
- <MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1>;
+ <MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1>,
+ <MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1>;
};
pinctrl_uart3: uart3grp {
fsl,pins =
- <MX6SX_PAD_SD3_DATA4__UART3_RX 0x13059>,
- <MX6SX_PAD_SD3_DATA5__UART3_TX 0x13059>,
- <MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x13059>,
- <MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x13059>;
+ <MX6SX_PAD_SD3_DATA4__UART3_DCE_RX 0x13059>,
+ <MX6SX_PAD_SD3_DATA5__UART3_DCE_TX 0x13059>,
+ <MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS 0x13059>,
+ <MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS 0x13059>;
};
pinctrl_uart5: uart5grp {
fsl,pins =
- <MX6SX_PAD_SD4_DATA4__UART5_RX 0x1b0b1>,
- <MX6SX_PAD_SD4_DATA5__UART5_TX 0x1b0b1>;
+ <MX6SX_PAD_SD4_DATA4__UART5_DCE_RX 0x1b0b1>,
+ <MX6SX_PAD_SD4_DATA5__UART5_DCE_TX 0x1b0b1>;
};
pinctrl_uart6: uart6grp {
@@ -265,10 +265,10 @@
<MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x1b0b1>,
<MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x1b0b1>,
<MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x1b0b1>,
- <MX6SX_PAD_CSI_DATA04__UART6_RX 0x1b0b1>,
- <MX6SX_PAD_CSI_DATA05__UART6_TX 0x1b0b1>,
- <MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x1b0b1>,
- <MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x1b0b1>;
+ <MX6SX_PAD_CSI_DATA04__UART6_DCE_RX 0x1b0b1>,
+ <MX6SX_PAD_CSI_DATA05__UART6_DCE_TX 0x1b0b1>,
+ <MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS 0x1b0b1>,
+ <MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS 0x1b0b1>;
};
pinctrl_otg1_reg: otg1grp {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 531a52c..dfdca18 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -87,6 +87,8 @@
"pll1_sw", "pll1_sys";
arm-supply = <®_arm>;
soc-supply = <®_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -132,14 +134,10 @@
clock-output-names = "anaclk2";
};
- tempmon: tempmon {
- compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
- interrupt-parent = <&gpc>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- fsl,tempmon = <&anatop>;
- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
- nvmem-cell-names = "calib", "temp_grade";
- clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
+ mqs: mqs {
+ compatible = "fsl,imx6sx-mqs";
+ gpr = <&gpr>;
+ status = "disabled";
};
pmu {
@@ -181,7 +179,7 @@
interrupt-parent = <&intc>;
};
- L2: l2-cache@a02000 {
+ L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -215,7 +213,7 @@
clocks = <&clks IMX6SX_CLK_APBH_DMA>;
};
- gpmi: gpmi-nand@1806000{
+ gpmi: nand-controller@1806000{
compatible = "fsl,imx6sx-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
@@ -235,7 +233,7 @@
status = "disabled";
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -333,6 +331,7 @@
};
esai: esai@2024000 {
+ compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
reg = <0x02024000 0x4000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
@@ -342,6 +341,9 @@
<&clks IMX6SX_CLK_SPBA>;
clock-names = "core", "mem", "extal",
"fsys", "spba";
+ dmas = <&sdma 23 21 0>,
+ <&sdma 24 21 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -388,18 +390,28 @@
};
asrc: asrc@2034000 {
+ compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
reg = <0x02034000 0x4000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
- <&clks IMX6SX_CLK_ASRC_IPG>,
- <&clks IMX6SX_CLK_SPDIF>,
- <&clks IMX6SX_CLK_SPBA>;
- clock-names = "mem", "ipg", "asrck", "spba";
- dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
- <&sdma 19 20 1>, <&sdma 20 20 1>,
- <&sdma 21 20 1>, <&sdma 22 20 1>;
+ clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
+ <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
+ <&clks IMX6SX_CLK_SPBA>;
+ clock-names = "mem", "ipg", "asrck_0",
+ "asrck_1", "asrck_2", "asrck_3", "asrck_4",
+ "asrck_5", "asrck_6", "asrck_7", "asrck_8",
+ "asrck_9", "asrck_a", "asrck_b", "asrck_c",
+ "asrck_d", "asrck_e", "asrck_f", "spba";
+ dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
+ <&sdma 19 23 1>, <&sdma 20 23 1>,
+ <&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
+ fsl,asrc-rate = <48000>;
+ fsl,asrc-width = <16>;
status = "okay";
};
};
@@ -411,7 +423,7 @@
clocks = <&clks IMX6SX_CLK_PWM1>,
<&clks IMX6SX_CLK_PWM1>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm2: pwm@2084000 {
@@ -421,7 +433,7 @@
clocks = <&clks IMX6SX_CLK_PWM2>,
<&clks IMX6SX_CLK_PWM2>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm3: pwm@2088000 {
@@ -431,7 +443,7 @@
clocks = <&clks IMX6SX_CLK_PWM3>,
<&clks IMX6SX_CLK_PWM3>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm4: pwm@208c000 {
@@ -441,7 +453,7 @@
clocks = <&clks IMX6SX_CLK_PWM4>,
<&clks IMX6SX_CLK_PWM4>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
flexcan1: can@2090000 {
@@ -466,7 +478,7 @@
status = "disabled";
};
- gpt: gpt@2098000 {
+ gpt: timer@2098000 {
compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -559,7 +571,7 @@
gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
};
- kpp: kpp@20b8000 {
+ kpp: keypad@20b8000 {
compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -567,14 +579,14 @@
status = "disabled";
};
- wdog1: wdog@20bc000 {
+ wdog1: watchdog@20bc000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_IPG>;
};
- wdog2: wdog@20c0000 {
+ wdog2: watchdog@20c0000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -582,7 +594,7 @@
status = "disabled";
};
- clks: ccm@20c4000 {
+ clks: clock-controller@20c4000 {
compatible = "fsl,imx6sx-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
@@ -594,7 +606,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@@ -694,6 +706,16 @@
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
+ interrupt-parent = <&gpc>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
+ };
};
usbphy1: usbphy@20c9000 {
@@ -752,7 +774,7 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
- src: src@20d8000 {
+ src: reset-controller@20d8000 {
compatible = "fsl,imx6sx-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -806,7 +828,7 @@
};
};
- iomuxc: iomuxc@20e0000 {
+ iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6sx-iomuxc";
reg = <0x020e0000 0x4000>;
};
@@ -830,14 +852,14 @@
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
- crypto: caam@2100000 {
+ crypto: crypto@2100000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
@@ -850,13 +872,13 @@
<&clks IMX6SX_CLK_EIM_SLOW>;
clock-names = "mem", "aclk", "ipg", "emi_slow";
- sec_jr0: jr0@1000 {
+ sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
- sec_jr1: jr1@2000 {
+ sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -928,6 +950,7 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
+ fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
@@ -940,7 +963,7 @@
status = "disabled";
};
- usdhc1: usdhc@2190000 {
+ usdhc1: mmc@2190000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -952,7 +975,7 @@
status = "disabled";
};
- usdhc2: usdhc@2194000 {
+ usdhc2: mmc@2194000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -964,7 +987,7 @@
status = "disabled";
};
- usdhc3: usdhc@2198000 {
+ usdhc3: mmc@2198000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -976,7 +999,7 @@
status = "disabled";
};
- usdhc4: usdhc@219c000 {
+ usdhc4: mmc@219c000 {
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -1037,6 +1060,7 @@
<&clks IMX6SX_CLK_ENET_PTP>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
+ fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
@@ -1051,13 +1075,17 @@
status = "disabled";
};
- ocotp: ocotp@21bc000 {
+ ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6sx-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6SX_CLK_OCOTP>;
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
+
tempmon_calib: calib@38 {
reg = <0x38 4>;
};
@@ -1188,7 +1216,7 @@
};
};
- aips3: aips-bus@2200000 {
+ aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -1289,7 +1317,7 @@
status = "disabled";
};
- wdog3: wdog@2288000 {
+ wdog3: watchdog@2288000 {
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
reg = <0x02288000 0x4000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
@@ -1329,7 +1357,7 @@
clocks = <&clks IMX6SX_CLK_PWM5>,
<&clks IMX6SX_CLK_PWM5>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm6: pwm@22a8000 {
@@ -1339,7 +1367,7 @@
clocks = <&clks IMX6SX_CLK_PWM6>,
<&clks IMX6SX_CLK_PWM6>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm7: pwm@22ac000 {
@@ -1349,7 +1377,7 @@
clocks = <&clks IMX6SX_CLK_PWM7>,
<&clks IMX6SX_CLK_PWM7>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm8: pwm@22b0000 {
@@ -1359,7 +1387,7 @@
clocks = <&clks IMX6SX_CLK_PWM8>,
<&clks IMX6SX_CLK_PWM8>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
};
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
index aa86341..64c2d1e 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -30,6 +30,28 @@
enable-active-high;
};
+ reg_peri_3v3: regulator-peri-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_peri_3v3>;
+ regulator-name = "VPERI_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ /*
+ * If you want to want to make this dynamic please
+ * check schematics and test all affected peripherals:
+ *
+ * - sensors
+ * - ethernet phy
+ * - can
+ * - bluetooth
+ * - wm8960 audio codec
+ * - ov5640 camera
+ */
+ regulator-always-on;
+ };
+
reg_can_3v3: regulator-can-3v3 {
compatible = "regulator-fixed";
regulator-name = "can-3v3";
@@ -130,6 +152,7 @@
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <ðphy0>;
+ phy-supply = <®_peri_3v3>;
status = "okay";
};
@@ -138,6 +161,7 @@
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
+ phy-supply = <®_peri_3v3>;
status = "okay";
mdio {
@@ -180,9 +204,11 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- mag3110@e {
+ magnetometer@e {
compatible = "fsl,mag3110";
reg = <0x0e>;
+ vdd-supply = <®_peri_3v3>;
+ vddio-supply = <®_peri_3v3>;
};
};
@@ -202,6 +228,7 @@
};
&pwm1 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@@ -266,6 +293,8 @@
&usbotg1 {
dr_mode = "otg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
status = "okay";
};
@@ -299,6 +328,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v;
+ broken-cd;
keep-power-in-suspend;
wakeup-source;
status = "okay";
@@ -448,6 +478,12 @@
>;
};
+ pinctrl_peri_3v3: peri3v3grp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
+ >;
+ };
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
@@ -499,6 +535,12 @@
>;
};
+ pinctrl_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts
index 3749fdd..a0bbec5 100644
--- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts
+++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts
@@ -25,7 +25,7 @@
};
panel {
- compatible = "auo,g101evn010", "simple-panel";
+ compatible = "auo,g101evn010";
power-supply = <&ldo4_ext>;
backlight = <&lcd_backlight>;
@@ -168,6 +168,7 @@
};
&pwm5 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts
index 9f63706..a0097da 100644
--- a/arch/arm/boot/dts/imx6ul-geam.dts
+++ b/arch/arm/boot/dts/imx6ul-geam.dts
@@ -195,6 +195,7 @@
};
&pwm8 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi
new file mode 100644
index 0000000..f2386dc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0>; /* will be filled by U-Boot */
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-reset-duration = <1>;
+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy1>;
+ phy-supply = <®_3v3>;
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+ };
+};
+
+/* Bluetooth */
+&uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
+
+/* WiFi */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ /* INT# */
+ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
+ /* RST# */
+ MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_uart8: uart8grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
+ /* BT_REG_ON */
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
+ MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
+ MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
+ MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
+ MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
+ MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
+ MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
+ MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
+ MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
+ /* WL_REG_ON */
+ MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
+ /* WL_IRQ */
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi
new file mode 100644
index 0000000..935a77d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 191000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_5v>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ user-button {
+ label = "User button";
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user-led {
+ label = "User";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+ gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ onewire {
+ compatible = "w1-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_w1>;
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ panel: panel {
+ compatible = "armadeus,st0700-adapt";
+ power-supply = <®_3v3>;
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbotg1_vbus: regulator-usbotg1vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbotg1vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_vbus>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usbotg2_vbus: regulator-usbotg2vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbotg2vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg2_vbus>;
+ gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&adc1 {
+ vref-supply = <®_3v3>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_5v>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_5v>;
+ status = "okay";
+};
+
+&ecspi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ };
+
+ spidev1: spi@1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ status = "okay";
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&pwm3 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "disabled";
+};
+
+&tsc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc>;
+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ measure-delay-time = <0xffff>;
+ pre-charge-time = <0xffff>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ vbus-supply = <®_usbotg1_vbus>;
+ dr_mode = "otg";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usbotg2_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpios>;
+
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
+ MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
+ MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
+ MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
+ MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
+ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
+ MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
+ MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ >;
+ };
+
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_tsc: tscgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1_id: usbotg1idgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg1_vbus: usbotg1vbusgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
index cc9adce..14fc482 100644
--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
@@ -187,6 +187,7 @@
};
&pwm8 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts b/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts
index 5bad296..5bfad46 100644
--- a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts
+++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts
@@ -41,6 +41,7 @@
};
&pwm7 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts b/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts
index 4e99e6c..5a3e06d 100644
--- a/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts
+++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts
@@ -8,409 +8,10 @@
/dts-v1/;
#include "imx6ul-kontron-n6310-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
/ {
model = "Kontron N6310 S";
compatible = "kontron,imx6ul-n6310-s", "kontron,imx6ul-n6310-som",
"fsl,imx6ul";
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led1 {
- label = "debug-led1";
- gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
- default-state = "off";
- linux,default-trigger = "heartbeat";
- };
-
- led2 {
- label = "debug-led2";
- gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led3 {
- label = "debug-led3";
- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- pwm-beeper {
- compatible = "pwm-beeper";
- pwms = <&pwm8 0 5000>;
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb_otg1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_vref_adc: regulator-vref-adc {
- compatible = "regulator-fixed";
- regulator-name = "vref-adc";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&adc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_adc1>;
- num-channels = <3>;
- vref-supply = <®_vref_adc>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- status = "okay";
-};
-
-&ecspi1 {
- cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-
- eeprom@0 {
- compatible = "anvo,anv32e61w", "atmel,at25";
- reg = <0>;
- spi-max-frequency = <20000000>;
- spi-cpha;
- spi-cpol;
- pagesize = <1>;
- size = <8192>;
- address-width = <16>;
- };
-};
-
-&fec1 {
- pinctrl-0 = <&pinctrl_enet1>;
- /delete-node/ mdio;
-};
-
-&fec2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
- phy-mode = "rmii";
- phy-handle = <ðphy2>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- micrel,led-mode = <0>;
- clocks = <&clks IMX6UL_CLK_ENET_REF>;
- clock-names = "rmii-ref";
- };
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- micrel,led-mode = <0>;
- clocks = <&clks IMX6UL_CLK_ENET2_REF>;
- clock-names = "rmii-ref";
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-};
-
-&i2c4 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
-
- rtc@32 {
- compatible = "epson,rx8900";
- reg = <0x32>;
- };
-};
-
-&pwm8 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm8>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- linux,rs485-enabled-at-boot-time;
- rs485-rx-during-tx;
- rs485-rts-active-low;
- uart-has-rtscts;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- fsl,uart-has-rtscts;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1>;
- dr_mode = "otg";
- srp-disable;
- hnp-disable;
- adp-disable;
- vbus-supply = <®_usb_otg1_vbus>;
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
- keep-power-in-suspend;
- wakeup-source;
- vmmc-supply = <®_3v3>;
- voltage-ranges = <3300 3300>;
- no-1-8-v;
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
- non-removable;
- keep-power-in-suspend;
- wakeup-source;
- vmmc-supply = <®_3v3>;
- voltage-ranges = <3300 3300>;
- no-1-8-v;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
-
- pinctrl_adc1: adc1grp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
- MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
- >;
- };
-
- /* FRAM */
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
- MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
- MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
- MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
- >;
- };
-
- pinctrl_enet2: enet2grp {
- fsl,pins = <
- MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
- MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
- MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
- >;
- };
-
- pinctrl_enet2_mdio: enet2mdiogrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
- MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp{
- fsl,pins = <
- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
- >;
- };
-
- pinctrl_gpio: gpiogrp {
- fsl,pins = <
- MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
- MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
- MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
- MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
- >;
- };
-
- pinctrl_gpio_leds: gpioledsgrp {
- fsl,pins = <
- MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
- MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
- MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
- MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
- MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
- >;
- };
-
- pinctrl_pwm8: pwm8grp {
- fsl,pins = <
- MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
- MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
- MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
- /*
- * mux unused RTS to make sure it doesn't cause
- * any interrupts when it is undefined
- */
- MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
- MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
- MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
- MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
- MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_usbotg1: usbotg1 {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
- MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
- MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
- MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
- MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
- MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
- >;
- };
};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi
index a896b23..47d3ce5 100644
--- a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi
@@ -6,7 +6,7 @@
*/
#include "imx6ul.dtsi"
-#include <dt-bindings/gpio/gpio.h>
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
/ {
model = "Kontron N6310 SOM";
@@ -18,49 +18,7 @@
};
};
-&ecspi2 {
- cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
- status = "okay";
-
- spi-flash@0 {
- compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
- phy-mode = "rmii";
- phy-handle = <ðphy1>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- micrel,led-mode = <0>;
- clocks = <&clks IMX6UL_CLK_ENET_REF>;
- clock-names = "rmii-ref";
- };
- };
-};
-
-&fec2 {
- phy-mode = "rmii";
- status = "disabled";
-};
-
&qspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi>;
- status = "okay";
-
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
@@ -81,54 +39,3 @@
};
};
};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reset_out>;
-
- pinctrl_ecspi2: ecspi2grp {
- fsl,pins = <
- MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
- MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
- MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
- MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
- >;
- };
-
- pinctrl_enet1: enet1grp {
- fsl,pins = <
- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
- >;
- };
-
- pinctrl_enet1_mdio: enet1mdiogrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
- >;
- };
-
- pinctrl_qspi: qspigrp {
- fsl,pins = <
- MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
- MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
- MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
- MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
- MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
- MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
- >;
- };
-
- pinctrl_reset_out: rstoutgrp {
- fsl,pins = <
- MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
- >;
- };
-};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts b/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts
new file mode 100644
index 0000000..239a1af
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-kontron-n6311-s.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6ul-kontron-n6311-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
+
+/ {
+ model = "Kontron N6311 S";
+ compatible = "kontron,imx6ul-n6311-s", "kontron,imx6ul-n6311-som",
+ "fsl,imx6ul";
+};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi
new file mode 100644
index 0000000..a095a76
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ul.dtsi"
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+
+/ {
+ model = "Kontron N6311 SOM";
+ compatible = "kontron,imx6ul-n6311-som", "fsl,imx6ul";
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ device_type = "memory";
+ };
+};
+
+&qspi {
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+
+ partition@0 {
+ label = "ubi1";
+ reg = <0x00000000 0x08000000>;
+ };
+
+ partition@8000000 {
+ label = "ubi2";
+ reg = <0x08000000 0x18000000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi
new file mode 100644
index 0000000..770f59b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi
@@ -0,0 +1,406 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led1 {
+ label = "debug-led1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "debug-led2";
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "debug-led3";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm8 0 5000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vref_adc: regulator-vref-adc {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-adc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&adc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
+ num-channels = <3>;
+ vref-supply = <®_vref_adc>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ eeprom@0 {
+ compatible = "anvo,anv32e61w", "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <8192>;
+ address-width = <16>;
+ };
+};
+
+&fec1 {
+ pinctrl-0 = <&pinctrl_enet1>;
+ /delete-node/ mdio;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy2>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm8 {
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ rs485-rts-active-low;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ over-current-active-low;
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ non-removable;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
+ >;
+ };
+
+ pinctrl_enet2_mdio: enet2mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
+ /*
+ * mux unused RTS to make sure it doesn't cause
+ * any interrupts when it is undefined
+ */
+ MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi
new file mode 100644
index 0000000..2a449a3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = &uart4;
+ };
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&fec2 {
+ phy-mode = "rmii";
+ status = "disabled";
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_out>;
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
+ >;
+ };
+
+ pinctrl_enet1_mdio: enet1mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+
+ pinctrl_reset_out: rstoutgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
index cf7faf4..6ce84f9 100644
--- a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
@@ -1,193 +1,6 @@
-/*
- * Copyright 2017 Armadeus Systems <support@armadeus.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2017 Armadeus Systems <support@armadeus.com>
#include "imx6ul.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0>; /* will be filled by U-Boot */
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- usdhc3_pwrseq: usdhc3-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet1>;
- phy-mode = "rmii";
- phy-reset-duration = <1>;
- phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
- phy-handle = <ðphy1>;
- phy-supply = <®_3v3>;
- status = "okay";
-
- mdio: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&gpio4>;
- interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
- status = "okay";
- };
- };
-};
-
-/* Bluetooth */
-&uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart8>;
- uart-has-rtscts;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- bus-width = <8>;
- no-1-8-v;
- non-removable;
- status = "okay";
-};
-
-/* WiFi */
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- bus-width = <4>;
- no-1-8-v;
- non-removable;
- mmc-pwrseq = <&usdhc3_pwrseq>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio2>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "host-wake";
- };
-};
-
-&iomuxc {
- pinctrl_enet1: enet1grp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
- /* INT# */
- MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
- /* RST# */
- MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
- >;
- };
-
- pinctrl_uart8: uart8grp {
- fsl,pins = <
- MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
- MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
- /* BT_REG_ON */
- MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
- MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
- MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
- MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
- MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
- MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
- MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
- MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
- MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
- MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
- /* WL_REG_ON */
- MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
- /* WL_IRQ */
- MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
- >;
- };
-};
+#include "imx6ul-imx6ull-opos6ul.dtsi"
diff --git a/arch/arm/boot/dts/imx6ul-opos6uldev.dts b/arch/arm/boot/dts/imx6ul-opos6uldev.dts
index 8ecdb9a..375b98d 100644
--- a/arch/arm/boot/dts/imx6ul-opos6uldev.dts
+++ b/arch/arm/boot/dts/imx6ul-opos6uldev.dts
@@ -1,293 +1,21 @@
-/*
- * Copyright 2017 Armadeus Systems <support@armadeus.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2017 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6ul-opos6ul.dtsi"
+#include "imx6ul-imx6ull-opos6uldev.dtsi"
/ {
- model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board";
- compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul";
-
- chosen {
- stdout-path = &uart1;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm3 0 191000>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <7>;
- power-supply = <®_5v>;
- status = "okay";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- user-button {
- label = "User button";
- gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_MISC>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- user-led {
- label = "User";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_led>;
- gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- onewire {
- compatible = "w1-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_w1>;
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- };
-
- panel: panel {
- compatible = "armadeus,st0700-adapt";
- power-supply = <®_3v3>;
- backlight = <&backlight>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lcdif_out>;
- };
- };
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usbotg1_vbus: regulator-usbotg1vbus {
- compatible = "regulator-fixed";
- regulator-name = "usbotg1vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_vbus>;
- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usbotg2_vbus: regulator-usbotg2vbus {
- compatible = "regulator-fixed";
- regulator-name = "usbotg2vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg2_vbus>;
- gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&adc1 {
- vref-supply = <®_3v3>;
- status = "okay";
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- xceiver-supply = <®_5v>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- xceiver-supply = <®_5v>;
- status = "okay";
-};
-
-&ecspi4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi4>;
- cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- spidev0: spi@0 {
- compatible = "spidev";
- reg = <0>;
- spi-max-frequency = <5000000>;
- };
-
- spidev1: spi@1 {
- compatible = "spidev";
- reg = <1>;
- spi-max-frequency = <5000000>;
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clock_frequency = <400000>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clock_frequency = <400000>;
- status = "okay";
-};
-
-&lcdif {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcdif>;
- status = "okay";
-
- port {
- lcdif_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "disabled";
-};
-
-&tsc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tsc>;
- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
- measure-delay-time = <0xffff>;
- pre-charge-time = <0xffff>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_id>;
- vbus-supply = <®_usbotg1_vbus>;
- dr_mode = "otg";
- disable-over-current;
- status = "okay";
-};
-
-&usbotg2 {
- vbus-supply = <®_usbotg2_vbus>;
- dr_mode = "host";
- disable-over-current;
- status = "okay";
+ model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board";
+ compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul";
};
&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpios>;
+ pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>;
- pinctrl_ecspi4: ecspi4grp {
+ pinctrl_tamper_gpios: tampergpiosgrp {
fsl,pins = <
- MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
- MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
- MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
- MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
- MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
- >;
- };
-
- pinctrl_gpios: gpiosgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
- MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
- MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
- MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
- MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
- MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
@@ -299,100 +27,6 @@
>;
};
- pinctrl_gpio_keys: gpiokeysgrp {
- fsl,pins = <
- MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
- >;
- };
-
- pinctrl_lcdif: lcdifgrp {
- fsl,pins = <
- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
- >;
- };
-
- pinctrl_led: ledgrp {
- fsl,pins = <
- MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
- >;
- };
-
- pinctrl_pwm3: pwm3grp {
- fsl,pins = <
- MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
- >;
- };
-
- pinctrl_tsc: tscgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_usbotg1_id: usbotg1idgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
- >;
- };
-
- pinctrl_usbotg1_vbus: usbotg1vbusgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
- >;
- };
-
pinctrl_usbotg2_vbus: usbotg2vbusgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
index 41f3b7f..88f631c 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi
@@ -20,7 +20,7 @@
* Set the minimum memory size here and
* let the bootloader set the real size.
*/
- memory {
+ memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x8000000>;
};
diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 8d5f8dc..f1513e6 100644
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -106,7 +106,7 @@
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
- cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx6ul-pico-dwarf.dts b/arch/arm/boot/dts/imx6ul-pico-dwarf.dts
new file mode 100644
index 0000000..162dc25
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-pico-dwarf.dts
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright 2015 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+/dts-v1/;
+
+#include "imx6ul-pico.dtsi"
+/ {
+ model = "TechNexion PICO-IMX6UL and DWARF baseboard";
+ compatible = "technexion,imx6ul-pico-dwarf", "fsl,imx6ul";
+
+ sound {
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx6ul-sgtl5000";
+ audio-cpu = <&sai1>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "LINE_IN", "Line In Jack",
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ };
+
+ sys_mclk: clock-sys-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+};
+
+&i2c2 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ sgtl5000: audio-codec@a {
+ reg = <0x0a>;
+ compatible = "fsl,sgtl5000";
+ clocks = <&sys_mclk>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+
+ pressure-sensor@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-pico.dtsi b/arch/arm/boot/dts/imx6ul-pico.dtsi
index de9f831..357ffb2 100644
--- a/arch/arm/boot/dts/imx6ul-pico.dtsi
+++ b/arch/arm/boot/dts/imx6ul-pico.dtsi
@@ -20,7 +20,7 @@
stdout-path = &uart6;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -72,6 +72,17 @@
regulator-max-microvolt = <3300000>;
startup-delay-us = <200000>;
};
+
+ panel {
+ compatible = "vxt,vl050-8048nt-c01";
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
};
&can1 {
@@ -154,36 +165,17 @@
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
- display = <&display0>;
status = "okay";
- display0: display0 {
- bits-per-pixel = <32>;
- bus-width = <24>;
-
- display-timings {
- native-mode = <&timing0>;
-
- timing0: timing0 {
- clock-frequency = <33200000>;
- hactive = <800>;
- vactive = <480>;
- hfront-porch = <210>;
- hback-porch = <46>;
- hsync-len = <1>;
- vback-porch = <22>;
- vfront-porch = <23>;
- vsync-len = <1>;
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <0>;
- };
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
};
};
};
&pwm3 {
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
index bb6dbfd..938a32c 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
@@ -549,7 +549,6 @@
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
- #pwm-cells = <3>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index f008036..d7d9f3e 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -131,16 +131,6 @@
clock-output-names = "ipp_di1";
};
- tempmon: tempmon {
- compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
- interrupt-parent = <&gpc>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- fsl,tempmon = <&anatop>;
- nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
- nvmem-cell-names = "calib", "temp_grade";
- clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
- };
-
pmu {
compatible = "arm,cortex-a7-pmu";
interrupt-parent = <&gpc>;
@@ -184,7 +174,7 @@
clocks = <&clks IMX6UL_CLK_APBHDMA>;
};
- gpmi: gpmi-nand@1806000 {
+ gpmi: nand-controller@1806000 {
compatible = "fsl,imx6q-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
@@ -204,7 +194,7 @@
status = "disabled";
};
- aips1: aips-bus@2000000 {
+ aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -351,6 +341,31 @@
dma-names = "rx", "tx";
status = "disabled";
};
+
+ asrc: asrc@2034000 {
+ compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc";
+ reg = <0x2034000 0x4000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
+ <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+ <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
+ <&clks IMX6UL_CLK_SPBA>;
+ clock-names = "mem", "ipg", "asrck_0",
+ "asrck_1", "asrck_2", "asrck_3", "asrck_4",
+ "asrck_5", "asrck_6", "asrck_7", "asrck_8",
+ "asrck_9", "asrck_a", "asrck_b", "asrck_c",
+ "asrck_d", "asrck_e", "asrck_f", "spba";
+ dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
+ <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
+ dma-names = "rxa", "rxb", "rxc",
+ "txa", "txb", "txc";
+ fsl,asrc-rate = <48000>;
+ fsl,asrc-width = <16>;
+ status = "okay";
+ };
};
tsc: tsc@2040000 {
@@ -371,7 +386,7 @@
clocks = <&clks IMX6UL_CLK_PWM1>,
<&clks IMX6UL_CLK_PWM1>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -382,7 +397,7 @@
clocks = <&clks IMX6UL_CLK_PWM2>,
<&clks IMX6UL_CLK_PWM2>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -393,7 +408,7 @@
clocks = <&clks IMX6UL_CLK_PWM3>,
<&clks IMX6UL_CLK_PWM3>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -404,7 +419,7 @@
clocks = <&clks IMX6UL_CLK_PWM4>,
<&clks IMX6UL_CLK_PWM4>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -430,7 +445,7 @@
status = "disabled";
};
- gpt1: gpt@2098000 {
+ gpt1: timer@2098000 {
compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
reg = <0x02098000 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -520,10 +535,11 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
+ fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
- kpp: kpp@20b8000 {
+ kpp: keypad@20b8000 {
compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -531,14 +547,14 @@
status = "disabled";
};
- wdog1: wdog@20bc000 {
+ wdog1: watchdog@20bc000 {
compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_WDOG1>;
};
- wdog2: wdog@20c0000 {
+ wdog2: watchdog@20c0000 {
compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -546,7 +562,7 @@
status = "disabled";
};
- clks: ccm@20c4000 {
+ clks: clock-controller@20c4000 {
compatible = "fsl,imx6ul-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
@@ -558,7 +574,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@@ -611,6 +627,16 @@
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
+ interrupt-parent = <&gpc>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
+ };
};
usbphy1: usbphy@20c9000 {
@@ -676,7 +702,7 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
- src: src@20d8000 {
+ src: reset-controller@20d8000 {
compatible = "fsl,imx6ul-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -693,7 +719,7 @@
interrupt-parent = <&intc>;
};
- iomuxc: iomuxc@20e0000 {
+ iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6ul-iomuxc";
reg = <0x020e0000 0x4000>;
};
@@ -704,13 +730,14 @@
reg = <0x020e4000 0x4000>;
};
- gpt2: gpt@20e8000 {
+ gpt2: timer@20e8000 {
compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
reg = <0x020e8000 0x4000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
<&clks IMX6UL_CLK_GPT2_SERIAL>;
clock-names = "ipg", "per";
+ status = "disabled";
};
sdma: sdma@20ec000 {
@@ -732,7 +759,7 @@
clocks = <&clks IMX6UL_CLK_PWM5>,
<&clks IMX6UL_CLK_PWM5>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -743,7 +770,7 @@
clocks = <&clks IMX6UL_CLK_PWM6>,
<&clks IMX6UL_CLK_PWM6>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -754,7 +781,7 @@
clocks = <&clks IMX6UL_CLK_PWM7>,
<&clks IMX6UL_CLK_PWM7>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -765,19 +792,19 @@
clocks = <&clks IMX6UL_CLK_PWM8>,
<&clks IMX6UL_CLK_PWM8>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
};
- aips2: aips-bus@2100000 {
+ aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
- crypto: caam@2140000 {
+ crypto: crypto@2140000 {
compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
@@ -788,19 +815,19 @@
<&clks IMX6UL_CLK_CAAM_MEM>;
clock-names = "ipg", "aclk", "mem";
- sec_jr0: jr0@1000 {
+ sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
- sec_jr1: jr1@2000 {
+ sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
- sec_jr2: jr2@3000 {
+ sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
@@ -855,10 +882,11 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
+ fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
- usdhc1: usdhc@2190000 {
+ usdhc1: mmc@2190000 {
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -872,7 +900,7 @@
status = "disabled";
};
- usdhc2: usdhc@2194000 {
+ usdhc2: mmc@2194000 {
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -945,7 +973,7 @@
status = "disabled";
};
- ocotp: ocotp-ctrl@21bc000 {
+ ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6ul-ocotp", "syscon";
@@ -1006,7 +1034,7 @@
status = "disabled";
};
- wdog3: wdog@21e4000 {
+ wdog3: watchdog@21e4000 {
compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
reg = <0x021e4000 0x4000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index b6147c7..a78849f 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -8,6 +8,20 @@
stdout-path = "serial0:115200n8";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
/* fixed crystal dedicated to mcp2515 */
clk16m: clk16m {
compatible = "fixed-clock";
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
index fb213be..95a11b8 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -15,7 +15,7 @@
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
- &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6>;
+ &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>;
};
&iomuxc_snvs {
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
index 6213968..9f1e382 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -26,7 +26,7 @@
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
- &pinctrl_gpio4 &pinctrl_gpio5>;
+ &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>;
};
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index d56728f..4436556 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -54,16 +54,29 @@
vref-supply = <®_module_3v3_avdd>;
};
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
/* Colibri SPI */
&ecspi1 {
- cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};
&fec2 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet2>;
+ pinctrl-1 = <&pinctrl_enet2_sleep>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
status = "okay";
@@ -132,25 +145,21 @@
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
- #pwm-cells = <3>;
};
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
- #pwm-cells = <3>;
};
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
- #pwm-cells = <3>;
};
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
- #pwm-cells = <3>;
};
&sdma {
@@ -198,10 +207,16 @@
assigned-clock-rates = <0>, <198000000>;
};
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
&iomuxc {
pinctrl_can_int: canint-grp {
fsl,pins = <
- MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */
+ MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
>;
};
@@ -220,17 +235,39 @@
>;
};
+ pinctrl_enet2_sleep: enet2sleepgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
+ MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0
+ MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0
+ MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0
+ MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0
+ MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0
+ >;
+ };
+
pinctrl_ecspi1_cs: ecspi1-cs-grp {
fsl,pins = <
- MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
+ MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */
>;
};
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
- MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
- MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
- MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
+ MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */
+ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */
+ MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1-grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
+ MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
>;
};
@@ -243,63 +280,68 @@
pinctrl_gpio_bl_on: gpio-bl-on-grp {
fsl,pins = <
- MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
+ MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */
>;
};
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
- MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
- MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
- MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
- MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
- MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
- MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */
- MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */
- MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */
- MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */
- MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */
+ MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */
+ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */
+ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */
+ MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */
+ MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */
+ MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */
+ MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */
>;
};
pinctrl_gpio2: gpio2-grp { /* Camera */
fsl,pins = <
- MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */
- MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */
- MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */
- MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */
- MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */
+ MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */
+ MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */
+ MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */
+ MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */
>;
};
pinctrl_gpio3: gpio3-grp { /* CAN2 */
fsl,pins = <
- MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */
- MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */
+ MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */
+ MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */
>;
};
pinctrl_gpio4: gpio4-grp {
fsl,pins = <
- MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */
+ MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */
>;
};
pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
fsl,pins = <
- MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
>;
};
pinctrl_gpio6: gpio6-grp { /* Wifi pins */
fsl,pins = <
- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */
- MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */
- MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */
- MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */
- MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */
- MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */
- MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */
+ MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */
+ MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */
+ MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */
+ MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */
+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */
+ MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */
+ >;
+ };
+
+ pinctrl_gpio7: gpio7-grp { /* CAN1 */
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */
+ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
>;
};
@@ -324,15 +366,15 @@
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
fsl,pins = <
- MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
- MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
+ MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */
+ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */
>;
};
@@ -352,107 +394,107 @@
pinctrl_lcdif_dat: lcdif-dat-grp {
fsl,pins = <
- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079
- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079
- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079
- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079
- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079
- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079
- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079
- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079
- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079
- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079
- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079
- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079
- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079
- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079
- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079
- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079
- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079
- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */
>;
};
pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
fsl,pins = <
- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079
- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079
- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079
- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */
>;
};
pinctrl_pwm4: pwm4-grp {
fsl,pins = <
- MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079
+ MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */
>;
};
pinctrl_pwm5: pwm5-grp {
fsl,pins = <
- MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079
+ MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */
>;
};
pinctrl_pwm6: pwm6-grp {
fsl,pins = <
- MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
+ MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */
>;
};
pinctrl_pwm7: pwm7-grp {
fsl,pins = <
- MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079
+ MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */
>;
};
pinctrl_uart1: uart1-grp {
fsl,pins = <
- MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1
- MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1
- MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1
- MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1
+ MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */
+ MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */
+ MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */
+ MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */
>;
};
pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
fsl,pins = <
- MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */
- MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */
- MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */
- MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */
+ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */
+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */
+ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */
>;
};
pinctrl_uart2: uart2-grp {
fsl,pins = <
- MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
- MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
- MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
- MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
+ MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */
+ MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */
+ MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */
+ MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */
>;
};
pinctrl_uart5: uart5-grp {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1
- MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1
+ MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */
+ MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
>;
};
pinctrl_usbh_reg: gpio-usbh-reg {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */
>;
};
pinctrl_usdhc1: usdhc1-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */
>;
};
@@ -487,7 +529,13 @@
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
- MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
+ MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10
+ >;
+ };
+
+ pinctrl_wdog: wdog-grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
>;
};
};
@@ -495,53 +543,53 @@
&iomuxc_snvs {
pinctrl_snvs_gpio1: snvs-gpio1-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */
- MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */
- MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */
- MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */
- MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */
+ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
+ MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */
+ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
>;
};
pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
>;
};
pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
fsl,pins = <
- MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */
+ MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */
>;
};
pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
+ MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
>;
};
pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
>;
};
pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
>;
};
pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */
>;
};
pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */
>;
};
@@ -553,7 +601,7 @@
pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
fsl,pins = <
- MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14
+ MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0
>;
};
};
diff --git a/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts b/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts
new file mode 100644
index 0000000..57588a5
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-kontron-n6411-s.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx6ull-kontron-n6411-som.dtsi"
+#include "imx6ul-kontron-n6x1x-s.dtsi"
+
+/ {
+ model = "Kontron N6411 S";
+ compatible = "kontron,imx6ull-n6411-s", "kontron,imx6ull-n6411-som",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi b/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi
new file mode 100644
index 0000000..b7e9842
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (C) 2018 Kontron Electronics GmbH
+ */
+
+#include "imx6ull.dtsi"
+#include "imx6ul-kontron-n6x1x-som-common.dtsi"
+
+/ {
+ model = "Kontron N6411 SOM";
+ compatible = "kontron,imx6ull-n6311-som", "fsl,imx6ull";
+
+ memory@80000000 {
+ reg = <0x80000000 0x20000000>;
+ device_type = "memory";
+ };
+};
+
+&qspi {
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+
+ partition@0 {
+ label = "ubi1";
+ reg = <0x00000000 0x08000000>;
+ };
+
+ partition@8000000 {
+ label = "ubi2";
+ reg = <0x08000000 0x18000000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts
new file mode 100644
index 0000000..79cc457
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx-eval.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Linumiz
+ * Author: Parthiban Nallathambi <parthiban@linumiz.com>
+ */
+
+/dts-v1/;
+#include "imx6ull.dtsi"
+#include "imx6ull-myir-mys-6ulx.dtsi"
+
+/ {
+ model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
+ compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull";
+};
+
+&gpmi {
+ fsl,use-minimum-ecc;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
new file mode 100644
index 0000000..d03694f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Linumiz
+ * Author: Parthiban Nallathambi <parthiban@linumiz.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "MYiR MYS-6ULX Single Board Computer";
+ compatible = "fsl,imx6ull";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ reg_vdd_5v: regulator-vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_vdd_3v3: regulator-vdd-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <®_vdd_5v>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ phy-supply = <®_vdd_3v3>;
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1_id>;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_vdd_3v3>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ keep-power-in-suspend;
+ vmmc-supply = <®_vdd_3v3>;
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpmi_nand: gpminandgrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
+ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
+ MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
+ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
+ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
+ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
+ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
+ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
+ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
+ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
+ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
+ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
+ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
+ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
+ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usb_otg1_id: usbotg1idgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/imx6ull-opos6ul.dtsi
new file mode 100644
index 0000000..155f941
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-opos6ul.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+#include "imx6ull.dtsi"
+#include "imx6ul-imx6ull-opos6ul.dtsi"
diff --git a/arch/arm/boot/dts/imx6ull-opos6uldev.dts b/arch/arm/boot/dts/imx6ull-opos6uldev.dts
new file mode 100644
index 0000000..198fdb7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-opos6uldev.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+/dts-v1/;
+#include "imx6ull-opos6ul.dtsi"
+#include "imx6ul-imx6ull-opos6uldev.dtsi"
+
+/ {
+ model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board";
+ compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull";
+};
+
+&iomuxc_snvs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tamper_gpios>;
+
+ pinctrl_tamper_gpios: tampergpiosgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0
+ >;
+ };
+
+ pinctrl_usbotg2_vbus: usbotg2vbusgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_w1: w1grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h
index eb025a9..7328d4e 100644
--- a/arch/arm/boot/dts/imx6ull-pinfunc.h
+++ b/arch/arm/boot/dts/imx6ull-pinfunc.h
@@ -82,6 +82,6 @@
#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
-#define MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
+#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0 0x0200 0x048C 0x0000 0x9 0x0
#endif /* __DTS_IMX6ULL_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index b7e67d1..9bf6749 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -51,7 +51,7 @@
/ {
soc {
- aips3: aips-bus@2200000 {
+ aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -68,6 +68,13 @@
clock-names = "dcp";
};
+ rngb: rng@2284000 {
+ compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
+ reg = <0x02284000 0x4000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_DUMMY>;
+ };
+
iomuxc_snvs: iomuxc-snvs@2290000 {
compatible = "fsl,imx6ull-iomuxc-snvs";
reg = <0x02290000 0x4000>;
diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi
new file mode 100644
index 0000000..9fa701b
--- /dev/null
+++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017-2020 Toradex AG
+ *
+ */
+
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ panel: panel {
+ compatible = "edt,et057090dhu";
+ backlight = <&bl>;
+ power-supply = <®_3v3>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ vin-supply = <®_5v0>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+/*
+ * ADC2 is not available on the Aster board and
+ * conflicts with AD7879 resistive touchscreen.
+ */
+&adc2 {
+ status = "disabled";
+};
+
+&bl {
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ power-supply = <®_3v3>;
+ status = "okay";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+
+ /* Microchip/Atmel maxtouch controller */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiotouch>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */
+ reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc: m41t0m6@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+&iomuxc {
+ pinctrl_gpiotouch: touchgpios {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74
+ MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14
+ >;
+ };
+};
+
+&lcdif {
+ status = "okay";
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ keep-power-in-suspend;
+ no-1-8-v;
+ wakeup-source;
+ vmmc-supply = <®_3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index 3f27461..9760137 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -1,46 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2016 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2016-2020 Toradex
*/
/ {
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &snvs_rtc;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -52,6 +20,20 @@
clock-frequency = <16000000>;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
panel: panel {
compatible = "edt,et057090dhu";
backlight = <&bl>;
@@ -131,6 +113,21 @@
&i2c4 {
status = "okay";
+ /*
+ * Touchscreen is using SODIMM 28/30, also used for PWM<B>, PWM<C>,
+ * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms
+ */
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiotouch>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
+ status = "disabled";
+ };
+
/* M41T0M6 real time clock on carrier board */
rtc: m41t0m6@68 {
compatible = "st,m41t0";
@@ -186,3 +183,12 @@
vmmc-supply = <®_3v3>;
status = "okay";
};
+
+&iomuxc {
+ pinctrl_gpiotouch: touchgpios {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74
+ MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index 8bba03d..62b771c 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2016 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2016-2020 Toradex
*/
/ {
@@ -97,7 +60,7 @@
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
- cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
};
&fec1 {
@@ -130,6 +93,184 @@
status = "disabled";
};
+&gpio1 {
+ gpio-line-names = "SODIMM_43",
+ "SODIMM_45",
+ "SODIMM_135",
+ "SODIMM_22",
+ "",
+ "",
+ "SODIMM_37",
+ "SODIMM_29",
+ "SODIMM_59",
+ "SODIMM_28",
+ "SODIMM_30",
+ "SODIMM_67",
+ "",
+ "",
+ "SODIMM_188",
+ "SODIMM_178";
+};
+
+&gpio2 {
+ gpio-line-names = "SODIMM_111",
+ "SODIMM_113",
+ "SODIMM_115",
+ "SODIMM_117",
+ "SODIMM_119",
+ "SODIMM_121",
+ "SODIMM_123",
+ "SODIMM_125",
+ "SODIMM_91",
+ "SODIMM_89",
+ "SODIMM_105",
+ "SODIMM_152",
+ "SODIMM_150",
+ "SODIMM_95",
+ "SODIMM_126",
+ "SODIMM_107",
+ "SODIMM_114",
+ "SODIMM_116",
+ "SODIMM_118",
+ "SODIMM_120",
+ "SODIMM_122",
+ "SODIMM_124",
+ "SODIMM_127",
+ "SODIMM_130",
+ "SODIMM_132",
+ "SODIMM_134",
+ "SODIMM_133",
+ "SODIMM_104",
+ "SODIMM_106",
+ "SODIMM_110",
+ "SODIMM_112",
+ "SODIMM_128";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_56",
+ "SODIMM_44",
+ "SODIMM_68",
+ "SODIMM_82",
+ "SODIMM_93",
+ "SODIMM_76",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_57",
+ "SODIMM_61",
+ "SODIMM_136",
+ "SODIMM_138",
+ "SODIMM_140",
+ "SODIMM_142",
+ "SODIMM_144",
+ "SODIMM_146";
+};
+
+&gpio4 {
+ gpio-line-names = "SODIMM_35",
+ "SODIMM_33",
+ "SODIMM_38",
+ "SODIMM_36",
+ "SODIMM_21",
+ "SODIMM_19",
+ "SODIMM_131",
+ "SODIMM_129",
+ "SODIMM_90",
+ "SODIMM_92",
+ "SODIMM_88",
+ "SODIMM_86",
+ "SODIMM_81",
+ "SODIMM_94",
+ "SODIMM_96",
+ "SODIMM_75",
+ "SODIMM_101",
+ "SODIMM_103",
+ "SODIMM_79",
+ "SODIMM_97",
+ "SODIMM_67",
+ "SODIMM_59",
+ "SODIMM_85",
+ "SODIMM_65";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_69",
+ "SODIMM_71",
+ "SODIMM_73",
+ "SODIMM_47",
+ "SODIMM_190",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_51",
+ "SODIMM_53",
+ "",
+ "",
+ "SODIMM_98",
+ "SODIMM_184",
+ "SODIMM_186",
+ "SODIMM_23",
+ "SODIMM_31",
+ "SODIMM_100",
+ "SODIMM_102";
+};
+
+&gpio6 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_169",
+ "",
+ "",
+ "",
+ "SODIMM_77",
+ "SODIMM_24",
+ "",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_32",
+ "SODIMM_34";
+};
+
+&gpio7 {
+ gpio-line-names = "",
+ "",
+ "SODIMM_63",
+ "SODIMM_55",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_196",
+ "SODIMM_194",
+ "",
+ "SODIMM_99",
+ "",
+ "",
+ "SODIMM_137";
+};
+
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -322,7 +463,6 @@
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
- no-1-8-v;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
disable-wp;
vqmmc-supply = <®_LDO2>;
@@ -357,7 +497,6 @@
MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
- MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 */
MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
@@ -374,7 +513,6 @@
MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x74 /* SODIMM 106 */
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
@@ -671,6 +809,28 @@
>;
};
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
+ >;
+ };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
@@ -741,12 +901,17 @@
pinctrl_gpio_lpsr: gpio1-grp {
fsl,pins = <
- MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59
MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
>;
};
+ pinctrl_gpiokeys: gpiokeysgrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19
+ >;
+ };
+
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi
index 9aaed85..8773344 100644
--- a/arch/arm/boot/dts/imx7-tqma7.dtsi
+++ b/arch/arm/boot/dts/imx7-tqma7.dtsi
@@ -16,7 +16,7 @@
};
&cpu0 {
- arm-supply = <&sw1a_reg>;
+ cpu-supply = <&sw1a_reg>;
};
&i2c1 {
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index 7646284..713483c 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -37,6 +37,10 @@
cpu-supply = <&sw1a_reg>;
};
+&cpu1 {
+ cpu-supply = <&sw1a_reg>;
+};
+
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
@@ -85,12 +89,12 @@
pmic: pmic@8 {
compatible = "fsl,pfuze3000";
- reg = <0x08>;
+ reg = <0x8>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1475000>;
+ regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/imx7d-colibri-aster.dts
new file mode 100644
index 0000000..f3f0537
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-aster.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017-2020 Toradex AG
+ *
+ */
+
+/dts-v1/;
+#include "imx7d-colibri.dtsi"
+#include "imx7-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7D on Aster Carrier Board";
+ compatible = "toradex,colibri-imx7d-aster", "toradex,colibri-imx7d",
+ "fsl,imx7d";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts
new file mode 100644
index 0000000..2048027
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017-2020 Toradex AG
+ *
+ */
+
+/dts-v1/;
+#include "imx7d-colibri-emmc.dtsi"
+#include "imx7-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board";
+ compatible = "toradex,colibri-imx7d-emmc-aster",
+ "toradex,colibri-imx7d-emmc", "fsl,imx7d";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
index 898f4b8..af39e53 100644
--- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
@@ -13,6 +13,32 @@
};
};
+&gpio6 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_169",
+ "SODIMM_157",
+ "",
+ "SODIMM_163",
+ "SODIMM_77",
+ "SODIMM_24",
+ "",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_32",
+ "SODIMM_34";
+};
+
&usbotg2 {
dr_mode = "host";
};
diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
index 136e11a..87b132b 100644
--- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2016 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2016-2020 Toradex
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi
index e2e327f..219a040 100644
--- a/arch/arm/boot/dts/imx7d-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2016 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2016-2020 Toradex
*/
#include "imx7d.dtsi"
@@ -50,6 +13,10 @@
};
};
+&cpu1 {
+ cpu-supply = <®_DCDC2>;
+};
+
&gpmi {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts
index 6b4acea..e0751e6 100644
--- a/arch/arm/boot/dts/imx7d-nitrogen7.dts
+++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts
@@ -121,6 +121,10 @@
cpu-supply = <&sw1a_reg>;
};
+&cpu1 {
+ cpu-supply = <&sw1a_reg>;
+};
+
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
diff --git a/arch/arm/boot/dts/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/imx7d-pico-dwarf.dts
new file mode 100644
index 0000000..5162fe2
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-pico-dwarf.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright 2015 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+/dts-v1/;
+
+#include "imx7d-pico.dtsi"
+/ {
+ model = "TechNexion PICO-IMX7D and DWARF baseboard";
+ compatible = "technexion,imx7d-pico-dwarf", "fsl,imx7d";
+
+ sound {
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx7d-sgtl5000";
+ audio-cpu = <&sai1>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "LINE_IN", "Line In Jack",
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ };
+
+ sys_mclk: clock-sys-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+};
+
+&i2c1 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ sgtl5000: audio-codec@a {
+ reg = <0x0a>;
+ compatible = "fsl,sgtl5000";
+ clocks = <&sys_mclk>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+
+ pressure-sensor@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ };
+};
+
+&i2c4 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pca9554: io-expander@25 {
+ compatible = "nxp,pca9554";
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ reg = <0x25>;
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touchscreen>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pca9554 4 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ };
+};
+
+&iomuxc {
+ pinctrl_touchscreen: touchscreengrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx7d-pico-nymph.dts b/arch/arm/boot/dts/imx7d-pico-nymph.dts
new file mode 100644
index 0000000..104a852
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-pico-nymph.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright 2015 Technexion Ltd.
+//
+// Author: Wig Cheng <wig.cheng@technexion.com>
+// Richard Hu <richard.hu@technexion.com>
+// Tapani Utriainen <tapani@technexion.com>
+/dts-v1/;
+
+#include "imx7d-pico.dtsi"
+/ {
+ model = "TechNexion PICO-IMX7 and NYMPH baseboard";
+ compatible = "technexion,imx7d-pico-nymph", "fsl,imx7d";
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led {
+ label = "gpio-led";
+ gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx-audio-sgtl5000";
+ model = "imx7d-sgtl5000";
+ audio-cpu = <&sai1>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "LINE_IN", "Line In Jack",
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ };
+
+ sys_mclk: clock-sys-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+};
+
+&i2c1 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ sgtl5000: audio-codec@a {
+ reg = <0x0a>;
+ compatible = "fsl,sgtl5000";
+ clocks = <&sys_mclk>;
+ VDDA-supply = <®_2p5v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+
+ adc@52 {
+ compatible = "ti,adc081c";
+ reg = <0x52>;
+ vref-supply = <®_2p5v>;
+ };
+};
+
+&i2c2 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ };
+};
+
+&iomuxc {
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi
index 8a8df54..e519897 100644
--- a/arch/arm/boot/dts/imx7d-pico.dtsi
+++ b/arch/arm/boot/dts/imx7d-pico.dtsi
@@ -7,12 +7,42 @@
#include "imx7d.dtsi"
/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 50000 0>;
+ brightness-levels = <0 36 72 108 144 180 216 255>;
+ default-brightness-level = <6>;
+ };
+
/* Will be filled by the bootloader */
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>;
};
+ panel {
+ compatible = "vxt,vl050-8048nt-c01";
+ backlight = <&backlight>;
+ power-supply = <®_lcd_3v3>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+
+ reg_lcd_3v3: regulator-lcd-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_lcdreg_on>;
+ regulator-name = "lcd-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_wlreg_on: regulator-wlreg_on {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -230,6 +260,18 @@
};
};
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ status = "okay";
+
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
@@ -260,6 +302,8 @@
};
&pwm4 { /* Backlight */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
@@ -413,6 +457,40 @@
>;
};
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
+ MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
+ MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
+ MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
+ MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
+ MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
+ MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
+ MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
+ MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
+ MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
+ MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
+ MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
+ MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
+ MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
+ MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
+ MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
+ MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
+ MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
+ MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
+ MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
+ MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
+ MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
+ MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
+ MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
+ MX7D_PAD_LCD_CLK__LCD_CLK 0x79
+ MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x78
+ MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x78
+ MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x78
+ MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14
+ >;
+ };
+
pinctrl_pwm1: pwm1 {
fsl,pins = <
MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
@@ -431,6 +509,12 @@
>;
};
+ pinctrl_pwm4: pwm4grp{
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x7f
+ >;
+ };
+
pinctrl_reg_wlreg_on: regregongrp {
fsl,pins = <
MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
@@ -577,6 +661,12 @@
>;
};
+ pinctrl_reg_lcdreg_on: reglcdongrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x59
+ >;
+ };
+
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h
index 08ca160..69f2c1e 100644
--- a/arch/arm/boot/dts/imx7d-pinfunc.h
+++ b/arch/arm/boot/dts/imx7d-pinfunc.h
@@ -592,7 +592,7 @@
#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0
#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0
#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0
-#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0
+#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0574 0x6 0x1
#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0
#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3
#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0
diff --git a/arch/arm/boot/dts/imx7d-sdb-reva.dts b/arch/arm/boot/dts/imx7d-sdb-reva.dts
index 7ce9d8c..cabdaa6 100644
--- a/arch/arm/boot/dts/imx7d-sdb-reva.dts
+++ b/arch/arm/boot/dts/imx7d-sdb-reva.dts
@@ -7,6 +7,9 @@
#include "imx7d-sdb.dts"
/ {
+ model = "Freescale i.MX7 SabreSD RevA Board";
+ compatible = "fsl,imx7d-sdb-reva", "fsl,imx7d";
+
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg_reva>;
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 869efbc..ac0751b 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -146,6 +146,24 @@
};
};
};
+
+ sound {
+ compatible = "fsl,imx7d-evk-wm8960",
+ "fsl,imx-audio-wm8960";
+ model = "wm8960-audio";
+ audio-cpu = <&sai1>;
+ audio-codec = <&codec>;
+ hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+ audio-routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT1", "AMIC",
+ "AMIC", "MICB";
+ };
};
&adc1 {
@@ -162,10 +180,14 @@
cpu-supply = <&sw1a_reg>;
};
+&cpu1 {
+ cpu-supply = <&sw1a_reg>;
+};
+
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
tsc2046@0 {
@@ -359,6 +381,13 @@
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clock-names = "mclk";
wlf,shared-lrclk;
+ wlf,hp-cfg = <2 2 3>;
+ wlf,gpio-cfg = <1 3>;
+ assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
+ <&clks IMX7D_PLL_AUDIO_POST_DIV>,
+ <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+ assigned-clock-rates = <0>, <884736000>, <12288000>;
};
};
@@ -387,6 +416,28 @@
vin-supply = <&sw2_reg>;
};
+&sai1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
+ <&clks IMX7D_PLL_AUDIO_POST_DIV>,
+ <&clks IMX7D_SAI1_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+ assigned-clock-rates = <0>, <884736000>, <36864000>;
+ status = "okay";
+};
+
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>;
+ assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
+ <&clks IMX7D_PLL_AUDIO_POST_DIV>,
+ <&clks IMX7D_SAI3_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+ assigned-clock-rates = <0>, <884736000>, <36864000>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -546,6 +597,7 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
+ MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */
>;
};
@@ -611,6 +663,33 @@
>;
};
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
+ MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
+ MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
+ MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
+ MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
+ MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
+ MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
+ MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f
+ MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f
+ MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30
+ >;
+ };
+
pinctrl_spi4: spi4grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
@@ -772,4 +851,10 @@
MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
>;
};
+
+ pinctrl_sai3_mclk: sai3grp_mclk {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f
+ >;
+ };
};
diff --git a/arch/arm/boot/dts/imx7d-tqma7.dtsi b/arch/arm/boot/dts/imx7d-tqma7.dtsi
index 8ad3048..598aed1 100644
--- a/arch/arm/boot/dts/imx7d-tqma7.dtsi
+++ b/arch/arm/boot/dts/imx7d-tqma7.dtsi
@@ -9,3 +9,7 @@
#include "imx7d.dtsi"
#include "imx7-tqma7.dtsi"
+
+&cpu1 {
+ cpu-supply = <&sw1a_reg>;
+};
diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/imx7d-zii-rmu2.dts
index 2b8d6cc..1065941 100644
--- a/arch/arm/boot/dts/imx7d-zii-rmu2.dts
+++ b/arch/arm/boot/dts/imx7d-zii-rmu2.dts
@@ -33,13 +33,13 @@
};
&cpu0 {
- arm-supply = <&sw1a_reg>;
+ cpu-supply = <&sw1a_reg>;
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
@@ -58,7 +58,7 @@
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-handle = <&fec1_phy>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts
index 39812c9..893bd30 100644
--- a/arch/arm/boot/dts/imx7d-zii-rpu2.dts
+++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts
@@ -182,7 +182,7 @@
};
&cpu0 {
- arm-supply = <&sw1a_reg>;
+ cpu-supply = <&sw1a_reg>;
};
&clks {
@@ -193,7 +193,7 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 9c8dd32..cff875b 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -12,7 +12,7 @@
clock-frequency = <996000000>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>;
- nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cells = <&fuse_grade>;
nvmem-cell-names = "speed_grade";
};
@@ -22,6 +22,7 @@
reg = <1>;
clock-frequency = <996000000>;
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
cpu-idle-states = <&cpu_sleep_wait>;
};
};
@@ -43,21 +44,24 @@
opp-hz = /bits/ 64 <792000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
- opp-supported-hw = <0xf>, <0xf>;
+ opp-supported-hw = <0xd>, <0x7>;
+ opp-suspend;
};
opp-996000000 {
opp-hz = /bits/ 64 <996000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <150000>;
- opp-supported-hw = <0xc>, <0xf>;
+ opp-supported-hw = <0xc>, <0x7>;
+ opp-suspend;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1225000>;
clock-latency-ns = <150000>;
- opp-supported-hw = <0x8>, <0xf>;
+ opp-supported-hw = <0x8>, <0x3>;
+ opp-suspend;
};
};
@@ -149,6 +153,7 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
+ fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/imx7s-colibri-aster.dts
new file mode 100644
index 0000000..fca4e0a
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s-colibri-aster.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017-2020 Toradex AG
+ *
+ */
+
+/dts-v1/;
+#include "imx7s-colibri.dtsi"
+#include "imx7-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7S on Aster Carrier Board";
+ compatible = "toradex,colibri-imx7s-aster", "toradex,colibri-imx7s",
+ "fsl,imx7s";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
index bd2a49c..aa70d3f 100644
--- a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2016 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2016-2020 Toradex
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi
index 6d16e32..94de220 100644
--- a/arch/arm/boot/dts/imx7s-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7s-colibri.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2016 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2016-2020 Toradex
*/
#include "imx7s.dtsi"
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index e2e604d..84d9cc1 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -147,17 +147,6 @@
};
};
- tempmon: tempmon {
- compatible = "fsl,imx7d-tempmon";
- interrupt-parent = <&gpc>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- fsl,tempmon = <&anatop>;
- nvmem-cells = <&tempmon_calib>,
- <&tempmon_temp_grade>;
- nvmem-cell-names = "calib", "temp_grade";
- clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
- };
-
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&intc>;
@@ -316,7 +305,7 @@
<0x31006000 0x2000>;
};
- aips1: aips-bus@30000000 {
+ aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -407,14 +396,14 @@
gpio-ranges = <&iomuxc 0 139 16>;
};
- wdog1: wdog@30280000 {
+ wdog1: watchdog@30280000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
};
- wdog2: wdog@30290000 {
+ wdog2: watchdog@30290000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x30290000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
@@ -422,7 +411,7 @@
status = "disabled";
};
- wdog3: wdog@302a0000 {
+ wdog3: watchdog@302a0000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x302a0000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
@@ -430,7 +419,7 @@
status = "disabled";
};
- wdog4: wdog@302b0000 {
+ wdog4: watchdog@302b0000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x302b0000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
@@ -444,7 +433,7 @@
fsl,input-sel = <&iomuxc>;
};
- gpt1: gpt@302d0000 {
+ gpt1: timer@302d0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -453,7 +442,7 @@
clock-names = "ipg", "per";
};
- gpt2: gpt@302e0000 {
+ gpt2: timer@302e0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -463,7 +452,7 @@
status = "disabled";
};
- gpt3: gpt@302f0000 {
+ gpt3: timer@302f0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
@@ -473,7 +462,7 @@
status = "disabled";
};
- gpt4: gpt@30300000 {
+ gpt4: timer@30300000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x30300000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
@@ -483,7 +472,7 @@
status = "disabled";
};
- kpp: kpp@30320000 {
+ kpp: keypad@30320000 {
compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
reg = <0x30320000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
@@ -491,7 +480,7 @@
status = "disabled";
};
- iomuxc: iomuxc@30330000 {
+ iomuxc: pinctrl@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
};
@@ -537,7 +526,7 @@
};
};
- ocotp: ocotp-ctrl@30350000 {
+ ocotp: efuse@30350000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx7d-ocotp", "syscon";
@@ -548,18 +537,14 @@
reg = <0x3c 0x4>;
};
- tempmon_temp_grade: temp-grade@10 {
- reg = <0x10 0x4>;
- };
-
- cpu_speed_grade: speed-grade@10 {
+ fuse_grade: fuse-grade@10 {
reg = <0x10 0x4>;
};
};
anatop: anatop@30360000 {
compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
- "syscon", "simple-bus";
+ "syscon", "simple-mfd";
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
@@ -591,6 +576,16 @@
anatop-max-voltage = <1300000>;
anatop-enable-bit = <0>;
};
+
+ tempmon: tempmon {
+ compatible = "fsl,imx7d-tempmon";
+ interrupt-parent = <&gpc>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
+ nvmem-cell-names = "calib", "temp_grade";
+ clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
+ };
};
snvs: snvs@30370000 {
@@ -611,13 +606,15 @@
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-pwrkey";
linux,keycode = <KEY_POWER>;
wakeup-source;
status = "disabled";
};
};
- clks: ccm@30380000 {
+ clks: clock-controller@30380000 {
compatible = "fsl,imx7d-ccm";
reg = <0x30380000 0x10000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
@@ -627,7 +624,7 @@
clock-names = "ckil", "osc";
};
- src: src@30390000 {
+ src: reset-controller@30390000 {
compatible = "fsl,imx7d-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
@@ -658,11 +655,17 @@
reg = <1>;
power-supply = <®_1p0d>;
};
+
+ pgc_hsic_phy: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <2>;
+ power-supply = <®_1p2>;
+ };
};
};
};
- aips2: aips-bus@30400000 {
+ aips2: bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -802,7 +805,7 @@
};
};
- aips3: aips-bus@30800000 {
+ aips3: bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -931,7 +934,7 @@
};
};
- crypto: caam@30900000 {
+ crypto: crypto@30900000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
@@ -942,19 +945,19 @@
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
clock-names = "ipg", "aclk";
- sec_jr0: jr0@1000 {
+ sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
- sec_jr1: jr1@2000 {
+ sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
- sec_jr2: jr1@3000 {
+ sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -1101,6 +1104,7 @@
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b30000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pgc_hsic_phy>;
clocks = <&clks IMX7D_USB_CTRL_CLK>;
fsl,usbphy = <&usbphynop3>;
fsl,usbmisc = <&usbmisc3 0>;
@@ -1122,7 +1126,7 @@
reg = <0x30b30200 0x200>;
};
- usdhc1: usdhc@30b40000 {
+ usdhc1: mmc@30b40000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -1134,7 +1138,7 @@
status = "disabled";
};
- usdhc2: usdhc@30b50000 {
+ usdhc2: mmc@30b50000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -1146,7 +1150,7 @@
status = "disabled";
};
- usdhc3: usdhc@30b60000 {
+ usdhc3: mmc@30b60000 {
compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -1158,6 +1162,19 @@
status = "disabled";
};
+ qspi: spi@30bb0000 {
+ compatible = "fsl,imx7d-qspi";
+ reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
+ <&clks IMX7D_QSPI_ROOT_CLK>;
+ clock-names = "qspi_en", "qspi";
+ status = "disabled";
+ };
+
sdma: sdma@30bd0000 {
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
reg = <0x30bd0000 0x10000>;
@@ -1186,6 +1203,7 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
+ fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
};
@@ -1203,7 +1221,7 @@
clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
};
- gpmi: gpmi-nand@33002000{
+ gpmi: nand-controller@33002000{
compatible = "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx7ulp-com.dts b/arch/arm/boot/dts/imx7ulp-com.dts
new file mode 100644
index 0000000..d76fea3
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-com.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2019 NXP
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Embedded Artists i.MX7ULP COM";
+ compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
+
+ chosen {
+ stdout-path = &lpuart4;
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x4000000>;
+ };
+};
+
+&lpuart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usdhc0 {
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ non-removable;
+ bus-width = <8>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&iomuxc1 {
+ pinctrl_lpuart4: lpuart4grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
+ IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
+ >;
+ };
+
+ pinctrl_usbotg1_id: otg1idgrp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC13__USB0_ID 0x10003
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
+ IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
+ IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
+ IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
+ IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
+ IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
+ IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
+ IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
+ IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
+ IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
+ IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
index 4245b33..eff51e1 100644
--- a/arch/arm/boot/dts/imx7ulp-evk.dts
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -72,11 +72,13 @@
srp-disable;
hnp-disable;
adp-disable;
- over-current-active-low;
+ disable-over-current;
status = "okay";
};
&usdhc0 {
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
@@ -108,7 +110,6 @@
pinctrl_usbotg1_id: otg1idgrp {
fsl,pins = <
IMX7ULP_PAD_PTC13__USB0_ID 0x10003
- IMX7ULP_PAD_PTC16__USB1_OC2 0x10003
>;
};
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 0108b63..bcec98b 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -87,13 +87,6 @@
#clock-cells = <0>;
};
- mpll: clock-mpll {
- compatible = "fixed-clock";
- clock-frequency = <480000000>;
- clock-output-names = "mpll";
- #clock-cells = <0>;
- };
-
ahbbridge0: bus@40000000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -139,13 +132,13 @@
<&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
clock-names = "aclk", "ipg";
- sec_jr0: jr0@1000 {
+ sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
};
- sec_jr1: jr1@2000 {
+ sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -230,8 +223,6 @@
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
@@ -246,8 +237,6 @@
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
<&pcc2 IMX7ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
@@ -258,12 +247,22 @@
compatible = "fsl,imx7ulp-scg1";
reg = <0x403e0000 0x10000>;
clocks = <&rosc>, <&sosc>, <&sirc>,
- <&firc>, <&upll>, <&mpll>;
+ <&firc>, <&upll>;
clock-names = "rosc", "sosc", "sirc",
- "firc", "upll", "mpll";
+ "firc", "upll";
#clock-cells = <1>;
};
+ wdog1: watchdog@403d0000 {
+ compatible = "fsl,imx7ulp-wdt";
+ reg = <0x403d0000 0x10000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
+ timeout-sec = <40>;
+ };
+
pcc2: clock-controller@403f0000 {
compatible = "fsl,imx7ulp-pcc2";
reg = <0x403f0000 0x10000>;
@@ -276,13 +275,12 @@
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
- "upll", "sosc_bus_clk", "mpll",
+ "upll", "sosc_bus_clk",
"firc_bus_clk", "rosc", "spll_bus_clk";
assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
@@ -309,13 +307,12 @@
<&scg1 IMX7ULP_CLK_APLL_PFD0>,
<&scg1 IMX7ULP_CLK_UPLL>,
<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
- <&scg1 IMX7ULP_CLK_MIPI_PLL>,
<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
<&scg1 IMX7ULP_CLK_ROSC>,
<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
"apll_pfd2", "apll_pfd1", "apll_pfd0",
- "upll", "sosc_bus_clk", "mpll",
+ "upll", "sosc_bus_clk",
"firc_bus_clk", "rosc", "spll_bus_clk";
};
};
@@ -455,7 +452,7 @@
reg = <0x410a3000 0x1000>;
};
- ocotp: ocotp-ctrl@410a6000 {
+ ocotp: efuse@410a6000 {
compatible = "fsl,imx7ulp-ocotp", "syscon";
reg = <0x410a6000 0x4000>;
clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
diff --git a/arch/arm/boot/dts/integratorap-im-pd1.dts b/arch/arm/boot/dts/integratorap-im-pd1.dts
new file mode 100644
index 0000000..1412a1a
--- /dev/null
+++ b/arch/arm/boot/dts/integratorap-im-pd1.dts
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree for the ARM Integrator/AP platform
+ * with the IM-PD1 example logical module mounted.
+ */
+
+#include "integratorap.dts"
+
+/ {
+ model = "ARM Integrator/AP with IM-PD1";
+ compatible = "arm,integrator-ap";
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ impd1_ram: vram@c2000000 {
+ /* 1 MB of designated video RAM on the IM-PD1 */
+ compatible = "shared-dma-pool";
+ reg = <0xc2000000 0x00100000>;
+ no-map;
+ };
+ };
+};
+
+&lm0 {
+ syscon@0 {
+ compatible = "arm,im-pd1-syscon", "syscon";
+ reg = <0x00000000 0x1000>;
+
+ vco1: clock@00 {
+ compatible = "arm,impd1-vco1";
+ #clock-cells = <0>;
+ lock-offset = <0x08>;
+ vco-offset = <0x00>;
+ clocks = <&sysclk>;
+ clock-output-names = "IM-PD1-VCO1";
+ };
+
+ vco2: clock@04 {
+ compatible = "arm,impd1-vco2";
+ #clock-cells = <0>;
+ lock-offset = <0x08>;
+ vco-offset = <0x04>;
+ clocks = <&sysclk>;
+ clock-output-names = "IM-PD1-VCO2";
+ };
+ };
+
+ /* Also used for the Smart Card Interface SCI */
+ impd1_uartclk: clock@1_4 {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <&vco2>;
+ clock-output-names = "VCO2_DIV4";
+ };
+
+ /* For the SSP the clock is divided by 64 */
+ impd1_sspclk: clock@1_64 {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <64>;
+ clock-mult = <1>;
+ clocks = <&vco2>;
+ clock-output-names = "VCO2_DIV64";
+ };
+
+ /* Fixed regulator for the MMC */
+ impd1_3v3: regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* Push buttons on the IM-PD1 */
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@0 {
+ debounce-interval = <50>;
+ linux,code = <KEY_UP>;
+ label = "UP";
+ gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>;
+ };
+ button@1 {
+ debounce-interval = <50>;
+ linux,code = <KEY_DOWN>;
+ label = "DOWN";
+ gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>;
+ };
+ button@2 {
+ debounce-interval = <50>;
+ linux,code = <KEY_LEFT>;
+ label = "LEFT";
+ gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+ button@3 {
+ debounce-interval = <50>;
+ linux,code = <KEY_RIGHT>;
+ label = "UP";
+ gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+ button@4 {
+ debounce-interval = <50>;
+ linux,code = <KEY_ESC>;
+ label = "ESC";
+ gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>;
+ };
+ button@5 {
+ debounce-interval = <50>;
+ linux,code = <KEY_ENTER>;
+ label = "ENTER";
+ gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+
+ bridge {
+ compatible = "ti,ths8134b", "ti,ths8134";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&clcd_pads_vga_dac>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_con_in: endpoint {
+ remote-endpoint = <&vga_bridge_out>;
+ };
+ };
+ };
+
+ uart@100000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x00100000 0x1000>;
+ interrupts-extended = <&impd1_vic 1>;
+ clocks = <&impd1_uartclk>, <&sysclk>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ uart@200000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x00200000 0x1000>;
+ interrupts-extended = <&impd1_vic 2>;
+ clocks = <&impd1_uartclk>, <&sysclk>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ ssp@300000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x00300000 0x1000>;
+ interrupts-extended = <&impd1_vic 3>;
+ clocks = <&impd1_sspclk>, <&sysclk>;
+ clock-names = "spiclk", "apb_pclk";
+ };
+
+ impd1_gpio0: gpio@400000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x00400000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts-extended = <&impd1_vic 4>;
+ clocks = <&sysclk>;
+ clock-names = "apb_pclk";
+ };
+
+ impd1_gpio1: gpio@500000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x00500000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts-extended = <&impd1_vic 5>;
+ clocks = <&sysclk>;
+ clock-names = "apb_pclk";
+ };
+
+ rtc@600000 {
+ compatible = "arm,pl030", "arm,primecell";
+ reg = <0x00600000 0x1000>;
+ interrupts-extended = <&impd1_vic 6>;
+ clocks = <&sysclk>;
+ clock-names = "apb_pclk";
+ };
+
+ mmc@700000 {
+ compatible = "arm,pl181", "arm,primecell";
+ reg = <0x00700000 0x1000>;
+ interrupts-extended = <&impd1_vic 7>,
+ <&impd1_vic 8>;
+ clocks = <&sysclk>, <&sysclk>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <1>;
+ max-frequency = <515633>;
+ vmmc-supply = <&impd1_3v3>;
+ wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>;
+ };
+
+ aaci@800000 {
+ compatible = "arm,pl041", "arm,primecell";
+ reg = <0x00800000 0x1000>;
+ interrupts-extended = <&impd1_vic 9>;
+ clocks = <&sysclk>;
+ clock-names = "apb_pclk";
+ };
+
+ display@1000000 {
+ compatible = "arm,pl110", "arm,primecell";
+ reg = <0x01000000 0x1000>;
+ interrupts-extended = <&impd1_vic 11>;
+ clocks = <&vco1>, <&sysclk>;
+ clock-names = "clcdclk", "apb_pclk";
+ /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
+ max-memory-bandwidth = <40000000>;
+ memory-region = <&impd1_ram>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clcd_pads_vga_dac: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vga_bridge_in>;
+ arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+ };
+ };
+ };
+
+ impd1_vic: interrupt-controller@3000000 {
+ compatible = "arm,pl192-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x03000000 0x1000>;
+ /* Valid interrupts, 0-9 and 11 */
+ valid-mask = <0x00000bff>;
+ /* LM site 0 has IRQ 9 on the PIC */
+ interrupts-extended = <&pic 9>;
+ };
+};
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index 94d2ff9..67d1f9b 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -4,12 +4,13 @@
*/
/dts-v1/;
-/include/ "integrator.dtsi"
+#include "integrator.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "ARM Integrator/AP";
compatible = "arm,integrator-ap";
- dma-ranges = <0x80000000 0x0 0x80000000>;
cpus {
#address-cells = <1>;
@@ -108,9 +109,6 @@
syscon {
compatible = "arm,integrator-ap-syscon", "syscon";
reg = <0x11000000 0x100>;
- interrupt-parent = <&pic>;
- /* These are the logical module IRQs */
- interrupts = <9>, <10>, <11>, <12>;
/*
* SYSCLK clocks PCIv3 bridge, system controller and the
@@ -240,4 +238,50 @@
clock-names = "KMIREFCLK", "apb_pclk";
};
};
+
+ /*
+ * Logic module bus, we support up to 4 logical modules
+ * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000
+ * and use interrupts 9, 10, 11 and 12 respectively.
+ */
+ bus@c0000000 {
+ compatible = "arm,integrator-ap-lm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xc0000000 0xc0000000 0x40000000>;
+ dma-ranges;
+
+ lm0: bus@c0000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0xc0000000 0x10000000>;
+ dma-ranges = <0x00000000 0x80000000 0x10000000>;
+ reg = <0xc0000000 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ lm1: bus@d0000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0xd0000000 0x10000000>;
+ dma-ranges = <0x00000000 0x80000000 0x10000000>;
+ reg = <0xd0000000 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ lm2: bus@e0000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0xe0000000 0x10000000>;
+ dma-ranges = <0x00000000 0x80000000 0x10000000>;
+ reg = <0xe0000000 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ lm3: bus@f0000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0xf0000000 0x10000000>;
+ dma-ranges = <0x00000000 0x80000000 0x10000000>;
+ reg = <0xf0000000 0x10000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index ae75a1d..63cafd2 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -46,6 +46,50 @@
clock-frequency = <26000000>;
};
+ lcd_backlight: backlight {
+ compatible = "pwm-backlight";
+
+ pwms = <&pwm3 0 5000000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ lvds-receiver {
+ compatible = "ti,ds90cf384a", "lvds-decoder";
+ power-supply = <&vcc_3v3_tft1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds_receiver_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds_receiver_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+
+ panel {
+ compatible = "edt,etm0700g0dh6";
+ backlight = <&lcd_backlight>;
+ power-supply = <&vcc_3v3_tft1>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds_receiver_out>;
+ };
+ };
+ };
+
reg_1p5v: 1p5v {
compatible = "regulator-fixed";
regulator-name = "1P5V";
@@ -70,6 +114,17 @@
};
};
+ vcc_3v3_tft1: regulator-panel {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vcc-3v3-tft1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ startup-delay-us = <500>;
+ gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
+ };
+
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
@@ -89,8 +144,7 @@
gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
};
@@ -120,6 +174,18 @@
status = "okay";
};
+&du {
+ status = "okay";
+};
+
+&gpio2 {
+ touch-interrupt {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_LOW>;
+ input;
+ };
+};
+
&hsusb {
status = "okay";
pinctrl-0 = <&usb0_pins>;
@@ -147,6 +213,26 @@
VDDIO-supply = <®_3p3v>;
VDDD-supply = <®_1p5v>;
};
+
+ touch: touchpanel@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ vcc-supply = <&vcc_3v3_tft1>;
+ };
+};
+
+&lvds0 {
+ status = "okay";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&lvds_receiver_in>;
+ };
+ };
+ };
};
&pci0 {
@@ -180,6 +266,11 @@
function = "i2c2";
};
+ pwm3_pins: pwm3 {
+ groups = "pwm3";
+ function = "pwm3";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data_d";
function = "scif0";
@@ -218,6 +309,12 @@
};
};
+&pwm3 {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&rcar_sound {
pinctrl-0 = <&sound_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
index 0e99df2..e10f992 100644
--- a/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi
@@ -39,7 +39,6 @@
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
- status = "okay";
ports {
port@0 {
@@ -73,8 +72,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
index 457515b..0397c34 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -408,4 +408,31 @@
reg-names = "control", "domain";
domain-id = <0>;
};
+
+ /*
+ * Below are set of fixed, input clocks definitions,
+ * for which real frequencies have to be defined in board files.
+ * Those clocks can be used as reference clocks for some HW modules
+ * (as cpts, for example) by configuring corresponding clock muxes.
+ */
+ timi0: timi0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "timi0";
+ };
+
+ timi1: timi1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "timi1";
+ };
+
+ tsrefclk: tsrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "tsrefclk";
+ };
};
diff --git a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
index f759215..cf30e00 100644
--- a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
@@ -71,4 +71,24 @@
reg-names = "control", "domain";
domain-id = <29>;
};
+
+ /*
+ * Below are set of fixed, input clocks definitions,
+ * for which real frequencies have to be defined in board files.
+ * Those clocks can be used as reference clocks for some HW modules
+ * (as cpts, for example) by configuring corresponding clock muxes.
+ */
+ tsipclka: tsipclka {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "tsipclka";
+ };
+
+ tsipclkb: tsipclkb {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "tsipclkb";
+ };
};
diff --git a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
index 1db17ec..ad15e77 100644
--- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi
@@ -135,8 +135,8 @@
/* NetCP address range */
ranges = <0 0x24000000 0x1000000>;
- clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
- clock-names = "pa_clk", "ethss_clk", "cpts";
+ clocks = <&clkpa>, <&clkcpgmac>;
+ clock-names = "pa_clk", "ethss_clk";
dma-coherent;
ti,navigator-dmas = <&dma_gbe 0>,
@@ -156,6 +156,23 @@
tx-queue = <896>;
tx-channel = "nettx";
+ cpts {
+ clocks = <&cpts_refclk_mux>;
+ clock-names = "cpts";
+
+ cpts_refclk_mux: cpts-refclk-mux {
+ #clock-cells = <0>;
+ clocks = <&chipclk12>, <&chipclk13>,
+ <&timi0>, <&timi1>,
+ <&tsipclka>, <&tsrefclk>,
+ <&tsipclkb>;
+ ti,mux-tbl = <0x0>, <0x1>, <0x2>,
+ <0x3>, <0x4>, <0x8>, <0xC>;
+ assigned-clocks = <&cpts_refclk_mux>;
+ assigned-clock-parents = <&chipclk12>;
+ };
+ };
+
interfaces {
gbe0: interface-0 {
slave-port = <0>;
diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi
index 085e732..2d94faf 100644
--- a/arch/arm/boot/dts/keystone-k2e.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e.dtsi
@@ -86,14 +86,14 @@
};
};
- msm_ram: msmram@c000000 {
+ msm_ram: sram@c000000 {
compatible = "mmio-sram";
reg = <0x0c000000 0x200000>;
ranges = <0x0 0x0c000000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
- sram-bm@1f0000 {
+ bm-sram@1f0000 {
reg = <0x001f0000 0x8000>;
};
};
diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts
index b7f10bf..8b3d64c 100644
--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
@@ -45,6 +45,19 @@
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
+
+ hdmi: connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&sii9022_out>;
+ };
+ };
+ };
};
&k2g_pinctrl {
@@ -89,6 +102,13 @@
>;
};
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */
+ K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */
+ >;
+ };
+
ecap0_pins: ecap0_pins {
pinctrl-single,pins = <
K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */
@@ -160,6 +180,40 @@
K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
>;
};
+
+ vout_pins: pinmux_vout_pins {
+ pinctrl-single,pins = <
+ K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */
+ K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */
+ K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */
+ K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */
+ K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */
+ K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */
+ K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */
+ K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */
+ K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */
+ K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */
+ K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */
+ K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */
+ K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */
+ K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */
+ K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */
+ K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */
+ K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */
+ K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */
+ K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */
+ K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */
+ K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */
+ K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */
+ K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */
+ K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */
+ K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */
+ K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */
+ K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */
+ K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */
+ K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */
+ >;
+ };
};
&uart0 {
@@ -348,7 +402,7 @@
&gbe0 {
phy-handle = <ðphy0>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii-rxid";
status = "okay";
};
@@ -357,3 +411,50 @@
pinctrl-0 = <&emac_pins>;
status = "okay";
};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+ clock-frequency = <400000>;
+
+ sii9022: sii9022@3b {
+ #sound-dai-cells = <0>;
+ compatible = "sil,sii9022";
+ reg = <0x3b>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sii9022_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ sii9022_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
+
+&dss {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vout_pins>;
+ status = "ok";
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&sii9022_in>;
+ data-lines = <24>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 1c83310..05a7501 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -95,14 +95,14 @@
ranges = <0x0 0x0 0x0 0xc0000000>;
dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
- msm_ram: msmram@c000000 {
+ msm_ram: sram@c000000 {
compatible = "mmio-sram";
reg = <0x0c000000 0x100000>;
ranges = <0x0 0x0c000000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
- sram-bm@f7000 {
+ bm-sram@f7000 {
reg = <0x000f7000 0x8000>;
};
};
@@ -324,6 +324,28 @@
clock-names = "gpio";
};
+ dss: dss@02540000 {
+ compatible = "ti,k2g-dss";
+ reg = <0x02540000 0x400>,
+ <0x02550000 0x1000>,
+ <0x02557000 0x1000>,
+ <0x0255a800 0x100>,
+ <0x0255ac00 0x100>;
+ reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
+ clocks = <&k2g_clks 0x2 0>,
+ <&k2g_clks 0x2 1>;
+ clock-names = "fck", "vp1";
+ interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&k2g_pds 0x2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ max-memory-bandwidth = <230000000>;
+ };
+
edma0: edma@2700000 {
compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
reg = <0x02700000 0x8000>;
diff --git a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
index e203145..d5a6c1f 100644
--- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi
@@ -152,8 +152,8 @@
/* NetCP address range */
ranges = <0 0x2000000 0x100000>;
- clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
- clock-names = "pa_clk", "ethss_clk", "cpts";
+ clocks = <&clkpa>, <&clkcpgmac>;
+ clock-names = "pa_clk", "ethss_clk";
dma-coherent;
ti,navigator-dmas = <&dma_gbe 22>,
@@ -175,6 +175,22 @@
tx-queue = <648>;
tx-channel = "nettx";
+ cpts {
+ clocks = <&cpts_refclk_mux>;
+ clock-names = "cpts";
+
+ cpts_refclk_mux: cpts-refclk-mux {
+ #clock-cells = <0>;
+ clocks = <&chipclk12>, <&chipclk13>,
+ <&timi0>, <&timi1>,
+ <&tsrefclk>;
+ ti,mux-tbl = <0x0>, <0x1>, <0x2>,
+ <0x3>, <0x8>;
+ assigned-clocks = <&cpts_refclk_mux>;
+ assigned-clock-parents = <&chipclk12>;
+ };
+ };
+
interfaces {
gbe0: interface-0 {
slave-port = <0>;
diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi
index ca0f198..8a94477 100644
--- a/arch/arm/boot/dts/keystone-k2hk.dtsi
+++ b/arch/arm/boot/dts/keystone-k2hk.dtsi
@@ -57,14 +57,14 @@
&soc0 {
/include/ "keystone-k2hk-clocks.dtsi"
- msm_ram: msmram@c000000 {
+ msm_ram: sram@c000000 {
compatible = "mmio-sram";
reg = <0x0c000000 0x600000>;
ranges = <0x0 0x0c000000 0x600000>;
#address-cells = <1>;
#size-cells = <1>;
- sram-bm@5f0000 {
+ bm-sram@5f0000 {
reg = <0x5f0000 0x8000>;
};
};
diff --git a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
index a2e47ba..c1f9826 100644
--- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
@@ -134,8 +134,8 @@
/* NetCP address range */
ranges = <0 0x26000000 0x1000000>;
- clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
- clock-names = "pa_clk", "ethss_clk", "cpts";
+ clocks = <&clkpa>, <&clkcpgmac>;
+ clock-names = "pa_clk", "ethss_clk";
dma-coherent;
ti,navigator-dmas = <&dma_gbe 0>,
@@ -155,6 +155,22 @@
tx-queue = <896>;
tx-channel = "nettx";
+ cpts {
+ clocks = <&cpts_refclk_mux>;
+ clock-names = "cpts";
+
+ cpts_refclk_mux: cpts-refclk-mux {
+ #clock-cells = <0>;
+ clocks = <&chipclk12>, <&chipclk13>,
+ <&timi0>, <&timi1>,
+ <&tsrefclk>;
+ ti,mux-tbl = <0x0>, <0x1>, <0x2>,
+ <0x3>, <0x8>;
+ assigned-clocks = <&cpts_refclk_mux>;
+ assigned-clock-parents = <&chipclk12>;
+ };
+ };
+
interfaces {
gbe0: interface-0 {
slave-port = <0>;
diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi
index 374c801..dff5fea 100644
--- a/arch/arm/boot/dts/keystone-k2l.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
@@ -255,14 +255,14 @@
};
};
- msm_ram: msmram@c000000 {
+ msm_ram: sram@c000000 {
compatible = "mmio-sram";
reg = <0x0c000000 0x200000>;
ranges = <0x0 0x0c000000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
- sram-bm@1f8000 {
+ bm-sram@1f8000 {
reg = <0x001f8000 0x8000>;
};
};
diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts
index 17f48f8..a7636fe 100644
--- a/arch/arm/boot/dts/kirkwood-b3.dts
+++ b/arch/arm/boot/dts/kirkwood-b3.dts
@@ -9,7 +9,7 @@
* L2 cache. If your B3 silently fails to boot, u-boot is probably too
* old. Either upgrade, or consider the following email:
*
- * http://lists.debian.org/debian-arm/2012/08/msg00128.html
+ * https://lists.debian.org/debian-arm/2012/08/msg00128.html
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/kirkwood-l-50.dts b/arch/arm/boot/dts/kirkwood-l-50.dts
new file mode 100644
index 0000000..0d81c43
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-l-50.dts
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Check Point L-50 Board Description
+ * Copyright 2020 Pawel Dembicki <paweldembicki@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "Check Point L-50";
+ compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ stdout-path = &uart0;
+ };
+
+ ocp@f1000000 {
+ pinctrl: pin-controller@10000 {
+ pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
+ pinctrl-names = "default";
+
+ pmx_sysrst: pmx-sysrst {
+ marvell,pins = "mpp6";
+ marvell,function = "sysrst";
+ };
+
+ pmx_button29: pmx_button29 {
+ marvell,pins = "mpp29";
+ marvell,function = "gpio";
+ };
+
+ pmx_led38: pmx_led38 {
+ marvell,pins = "mpp38";
+ marvell,function = "gpio";
+ };
+
+ pmx_sdio_cd: pmx-sdio-cd {
+ marvell,pins = "mpp46";
+ marvell,function = "gpio";
+ };
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+
+ mvsdio@90000 {
+ status = "okay";
+ cd-gpios = <&gpio1 14 9>;
+ };
+
+ i2c@11000 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ gpio2: gpio-expander@20{
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "semtech,sx1505q";
+ reg = <0x20>;
+
+ gpio-controller;
+ };
+
+ /* Three GPIOs from 0x21 exp. are undescribed in dts:
+ * 1: DSL module reset (active low)
+ * 5: mPCIE reset (active low)
+ * 6: Express card reset (active low)
+ */
+ gpio3: gpio-expander@21{
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "semtech,sx1505q";
+ reg = <0x21>;
+
+ gpio-controller;
+ };
+
+ rtc@30 {
+ compatible = "s35390a";
+ reg = <0x30>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "l-50:green:status";
+ gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ };
+
+ status_red {
+ label = "l-50:red:status";
+ gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi {
+ label = "l-50:green:wifi";
+ gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ internet_green {
+ label = "l-50:green:internet";
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ };
+
+ internet_red {
+ label = "l-50:red:internet";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ usb1_green {
+ label = "l-50:green:usb1";
+ gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "usbport";
+ trigger-sources = <&hub_port3>;
+ };
+
+ usb1_red {
+ label = "l-50:red:usb1";
+ gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ };
+
+ usb2_green {
+ label = "l-50:green:usb2";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "usbport";
+ trigger-sources = <&hub_port1>;
+ };
+
+ usb2_red {
+ label = "l-50:red:usb2";
+ gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ usb2_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "usb2_pwr";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+
+ usb1_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_pwr";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+
+ mpcie_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "mpcie_pwr";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ express_card_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "express_card_pwr";
+
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ factory_defaults {
+ label = "factory_defaults";
+ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy8: ethernet-phy@8 {
+ reg = <0x08>;
+ };
+
+ switch0: switch@10 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10>;
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan5";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan6";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan7";
+ };
+
+ switch0port5: port@5 {
+ reg = <5>;
+ phy-mode = "rgmii-txid";
+ link = <&switch1port5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ phy-mode = "rgmii-id";
+ ethernet = <ð1port>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ switch@11 {
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x11>;
+ dsa,member = <0 1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan3";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan8";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan4";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "dmz";
+ };
+
+ switch1port5: port@5 {
+ reg = <5>;
+ phy-mode = "rgmii-txid";
+ link = <&switch0port5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "dsl";
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy8>;
+ };
+};
+
+ð1 {
+ status = "okay";
+ ethernet1-port@0 {
+ speed = <1000>;
+ duplex = <1>;
+ };
+};
+
+&nand {
+ status = "okay";
+ pinctrl-0 = <&pmx_nand>;
+ pinctrl-names = "default";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x000c0000>;
+ };
+
+ partition@a0000 {
+ label = "bootldr-env";
+ reg = <0x000c0000 0x00040000>;
+ };
+
+ partition@100000 {
+ label = "kernel-1";
+ reg = <0x00100000 0x00800000>;
+ };
+
+ partition@900000 {
+ label = "rootfs-1";
+ reg = <0x00900000 0x07100000>;
+ };
+
+ partition@7a00000 {
+ label = "kernel-2";
+ reg = <0x07a00000 0x00800000>;
+ };
+
+ partition@8200000 {
+ label = "rootfs-2";
+ reg = <0x08200000 0x07100000>;
+ };
+
+ partition@f300000 {
+ label = "default_sw";
+ reg = <0x0f300000 0x07900000>;
+ };
+
+ partition@16c00000 {
+ label = "logs";
+ reg = <0x16c00000 0x01800000>;
+ };
+
+ partition@18400000 {
+ label = "preset_cfg";
+ reg = <0x18400000 0x00100000>;
+ };
+
+ partition@18500000 {
+ label = "adsl";
+ reg = <0x18500000 0x00100000>;
+ };
+
+ partition@18600000 {
+ label = "storage";
+ reg = <0x18600000 0x07a00000>;
+ };
+};
+
+&rtc {
+ status = "disabled";
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&sata_phy0 {
+ status = "disabled";
+};
+
+&sata_phy1 {
+ status = "disabled";
+};
+
+&usb0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ #trigger-source-cells = <0>;
+
+ hub_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ hub_port3: port@3 {
+ reg = <3>;
+ #trigger-source-cells = <0>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
index 8cc8550..b13aee5 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
@@ -113,6 +113,20 @@
};
};
+ auxdisplay {
+ compatible = "hit,hd44780";
+ data-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>,
+ <&gpio1 1 GPIO_ACTIVE_HIGH>,
+ <&gpio1 3 GPIO_ACTIVE_HIGH>,
+ <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ rs-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ rw-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ backlight-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ display-height-chars = <2>;
+ display-width-chars = <16>;
+ };
+
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi
index c97ed29..217bd37 100644
--- a/arch/arm/boot/dts/kirkwood-synology.dtsi
+++ b/arch/arm/boot/dts/kirkwood-synology.dtsi
@@ -244,7 +244,7 @@
rs5c372: rs5c372@32 {
status = "disabled";
- compatible = "ricoh,rs5c372";
+ compatible = "ricoh,rs5c372a";
reg = <0x32>;
};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 2161e23..6c8d94b 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -228,7 +228,7 @@
reg = <0x20128 0x4>;
};
- intc: main-interrupt-ctrl@20200 {
+ intc: interrupt-controller@20200 {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts
index f7a841a..2a0a98f 100644
--- a/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts
+++ b/arch/arm/boot/dts/logicpd-som-lv-35xx-devkit.dts
@@ -9,5 +9,5 @@
/ {
model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";
- compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3";
+ compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3430", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi
index 395e05f..7d0468a 100644
--- a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi
+++ b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi
@@ -79,7 +79,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
vdds_dsi-supply = <&vpll2>;
vdda_video-supply = <&video_reg>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts
index 7675bc3..57bae2a 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts
+++ b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts
@@ -9,5 +9,5 @@
/ {
model = "LogicPD Zoom OMAP35xx Torpedo Development Kit";
- compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3";
+ compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts
index cdb89b3..b553613 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts
+++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit-28.dts
@@ -11,6 +11,5 @@
#include "logicpd-torpedo-37xx-devkit.dts"
&lcd0 {
- /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */
compatible = "logicpd,type28";
};
diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
index 18c27e8..5532db0 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
+++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
@@ -50,6 +50,20 @@
};
};
+&uart2 {
+ /delete-property/dma-names;
+ bluetooth {
+ compatible = "ti,wl1283-st";
+ enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio 162 */
+ max-speed = <3000000>;
+ };
+};
+
+/* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */
+&mt9p031_out {
+ pixel-clock-frequency = <90000000>;
+};
+
&omap3_pmx_core {
mmc3_pins: pinmux_mm3_pins {
pinctrl-single,pins = <
diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi
index e7a8f8a..533a47b 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi
+++ b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi
@@ -65,6 +65,7 @@
pinctrl-0 = <&pwm_pins>;
ti,timers = <&timer10>;
#pwm-cells = <3>;
+ ti,clock-source = <0x01>;
};
};
@@ -103,13 +104,20 @@
};
};
+&hdqw1w {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdq_pins>;
+};
+
+
&vpll2 {
regulator-always-on;
};
&dss {
- status = "ok";
+ status = "okay";
vdds_dsi-supply = <&vpll2>;
+ vdda_video-supply = <&vpll2>;
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins1>;
port {
@@ -127,7 +135,6 @@
lcd0: display {
/* This isn't the exact LCD, but the timings meet spec */
- /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */
compatible = "newhaven,nhd-4.3-480272ef-atxl";
label = "15";
pinctrl-names = "default";
@@ -170,6 +177,12 @@
>;
};
+ hdq_pins: hdq_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* hdq_sio */
+ >;
+ };
+
pwm_pins: pinmux_pwm_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */
diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
index 506b118..3a52285 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
@@ -35,6 +35,11 @@
};
};
+/* The Torpedo doesn't route the USB host pins */
+&usbhshost {
+ status = "disabled";
+};
+
&gpmc {
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts
index 5b76890..aca78b5 100644
--- a/arch/arm/boot/dts/ls1021a-tsn.dts
+++ b/arch/arm/boot/dts/ls1021a-tsn.dts
@@ -203,11 +203,15 @@
/* AR8031 */
sgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
+ /* SGMII1_PHY_INT_B: connected to IRQ2, active low */
+ interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
};
/* AR8031 */
sgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
+ /* SGMII2_PHY_INT_B: connected to IRQ2, active low */
+ interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
};
/* BCM5464 quad PHY */
@@ -247,7 +251,7 @@
flash@0 {
/* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */
- compatible = "jedec,spi-nor", "s25fl256s1", "s25fl512s";
+ compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index 9b1fe99..5edf001 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -242,6 +242,20 @@
status = "okay";
};
+&qspi {
+ status = "okay";
+
+ n25q128a130: flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
&sai1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c62fcca..37026b2 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,7 @@
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
+ rtc1 = &ftm_alarm0;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial2 = &lpuart2;
@@ -216,6 +217,25 @@
compatible = "fsl,ls1021a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1570000 0x10000>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1021a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xffffffff 0x0>;
+ };
};
crypto: crypto@1700000 {
@@ -311,39 +331,6 @@
#thermal-sensor-cells = <1>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
-
- thermal-sensors = <&tmu 0>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit: cpu-crit {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT
- THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
dspi0: spi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
@@ -983,5 +970,52 @@
big-endian;
};
+ rcpm: power-controller@1ee2140 {
+ compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x8>;
+ #fsl,rcpm-wakeup-cells = <2>;
+ };
+
+ ftm_alarm0: timer0@29d0000 {
+ compatible = "fsl,ls1021a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ reg-names = "ftm";
+ fsl,rcpm-wakeup = <&rcpm 0x20000 0x0>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index c4447f6..c928ae3 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -11,13 +11,6 @@
#size-cells = <1>;
interrupt-parent = <&gic>;
- L2: l2-cache-controller@c4200000 {
- compatible = "arm,pl310-cache";
- reg = <0xc4200000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -49,14 +42,14 @@
};
uart_A: serial@84c0 {
- compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart";
reg = <0x84c0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
uart_B: serial@84dc {
- compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart";
reg = <0x84dc 0x18>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@@ -94,7 +87,7 @@
};
uart_C: serial@8700 {
- compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart";
reg = <0x8700 0x18>;
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@@ -140,6 +133,13 @@
status = "disabled";
};
+ sdhc: mmc@8e00 {
+ compatible = "amlogic,meson-mx-sdhc";
+ reg = <0x8e00 0x42>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
gpio_intc: interrupt-controller@9880 {
compatible = "amlogic,meson-gpio-intc";
reg = <0x9880 0x10>;
@@ -165,6 +165,13 @@
};
};
+ L2: cache-controller@c4200000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xc4200000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
periph: bus@c4300000 {
compatible = "simple-bus";
reg = <0xc4300000 0x10000>;
@@ -196,7 +203,7 @@
};
uart_AO: serial@4c0 {
- compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
+ compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart";
reg = <0x4c0 0x18>;
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@@ -229,6 +236,9 @@
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb0_phy>;
phy-names = "usb2-phy";
+ g-rx-fifo-size = <512>;
+ g-np-tx-fifo-size = <500>;
+ g-tx-fifo-size = <256 192 128 128 128>;
dr_mode = "host";
status = "disabled";
};
@@ -282,4 +292,11 @@
};
};
};
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
}; /* end of / */
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 2d31b7c..4716030 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -36,13 +36,6 @@
ranges = <0x0 0xd0000000 0x40000>;
};
- xtal: xtal-clk {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xtal";
- #clock-cells = <0>;
- };
-
clk81: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index d7c9dbe..0853311 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -3,8 +3,10 @@
* Copyright 2014 Carlo Caione <carlo@caione.org>
*/
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
+#include <dt-bindings/power/meson8-power.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
#include "meson.dtsi"
@@ -195,6 +197,14 @@
#size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>;
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
dmcbus: bus@6000 {
compatible = "simple-bus";
reg = <0x6000 0x400>;
@@ -379,6 +389,15 @@
};
};
+ sdxc_b_pins: sdxc-b {
+ mux {
+ groups = "sdxc_d0_b", "sdxc_d13_b",
+ "sdxc_clk_b", "sdxc_cmd_b";
+ function = "sdxc_b";
+ bias-pull-up;
+ };
+ };
+
spi_nor_pins: nor {
mux {
groups = "nor_d", "nor_q", "nor_c", "nor_cs";
@@ -448,6 +467,8 @@
ðmac {
clocks = <&clkc CLKID_ETH>;
clock-names = "stmmaceth";
+
+ power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
};
&gpio_intc {
@@ -458,9 +479,21 @@
&hhi {
clkc: clock-controller {
compatible = "amlogic,meson8-clkc";
+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ clock-names = "xtal", "ddr_pll";
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson8-pwrc";
+ #power-domain-cells = <1>;
+ amlogic,ao-sysctrl = <&pmu>;
+ clocks = <&clkc CLKID_VPU>;
+ clock-names = "vpu";
+ assigned-clocks = <&clkc CLKID_VPU>;
+ assigned-clock-rates = <364285714>;
+ };
};
&hwrng {
@@ -532,14 +565,23 @@
&saradc {
compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
- clocks = <&clkc CLKID_XTAL>,
- <&clkc CLKID_SAR_ADC>;
+ clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
clock-names = "clkin", "core";
amlogic,hhi-sysctrl = <&hhi>;
nvmem-cells = <&temperature_calib>;
nvmem-cell-names = "temperature_calib";
};
+&sdhc {
+ compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
+ clocks = <&xtal>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <&clkc CLKID_FCLK_DIV3>,
+ <&clkc CLKID_FCLK_DIV5>,
+ <&clkc CLKID_SDHC>;
+ clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
+};
+
&sdio {
compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
@@ -551,32 +593,32 @@
};
&timer_abcde {
- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "pclk";
};
&uart_AO {
- compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
- clock-names = "baud", "xtal", "pclk";
+ compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart";
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "pclk", "baud";
};
&uart_A {
- compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
- clock-names = "baud", "xtal", "pclk";
+ compatible = "amlogic,meson8-uart";
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "pclk", "baud";
};
&uart_B {
- compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
- clock-names = "baud", "xtal", "pclk";
+ compatible = "amlogic,meson8-uart";
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "pclk", "baud";
};
&uart_C {
- compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
- clock-names = "baud", "xtal", "pclk";
+ compatible = "amlogic,meson8-uart";
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "pclk", "baud";
};
&usb0 {
diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index 32d1c32..c6824d2 100644
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -27,6 +27,11 @@
reg = <0x40000000 0x40000000>;
};
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
gpio-keys {
compatible = "gpio-keys-polled";
#address-cells = <1>;
@@ -299,6 +304,26 @@
vref-supply = <&vcc_1v8>;
};
+&sdhc {
+ status = "okay";
+
+ pinctrl-0 = <&sdxc_c_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ max-frequency = <50000000>;
+
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ no-sdio;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_3v3>;
+};
+
&sdio {
status = "okay";
@@ -377,7 +402,7 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
+ clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};
diff --git a/arch/arm/boot/dts/meson8b-mxq.dts b/arch/arm/boot/dts/meson8b-mxq.dts
index ab8fe55..b2edac1 100644
--- a/arch/arm/boot/dts/meson8b-mxq.dts
+++ b/arch/arm/boot/dts/meson8b-mxq.dts
@@ -167,7 +167,7 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
+ clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index c413af9..73ce1c1 100644
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -15,6 +15,7 @@
aliases {
serial0 = &uart_AO;
mmc0 = &sd_card_slot;
+ mmc1 = &sdhc;
};
chosen {
@@ -26,6 +27,11 @@
reg = <0x40000000 0x40000000>;
};
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
leds {
compatible = "gpio-leds";
blue {
@@ -202,9 +208,8 @@
pinctrl-0 = <ð_rgmii_pins>;
pinctrl-names = "default";
- phy-mode = "rgmii";
phy-handle = <ð_phy>;
- amlogic,tx-delay-ns = <4>;
+ phy-mode = "rgmii-id";
nvmem-cells = <ðernet_mac_address>;
nvmem-cell-names = "mac-address";
@@ -311,6 +316,26 @@
vref-supply = <&vcc_1v8>;
};
+&sdhc {
+ status = "okay";
+
+ pinctrl-0 = <&sdxc_c_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ max-frequency = <100000000>;
+
+ disable-wp;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sdio;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+};
+
&sdio {
status = "okay";
@@ -340,7 +365,7 @@
status = "okay";
pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
pinctrl-names = "default";
- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_XTAL>;
+ clocks = <&xtal>, <&xtal>;
clock-names = "clkin0", "clkin1";
};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 1e8c5d7..f6eb7c8 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -4,8 +4,10 @@
* Author: Carlo Caione <carlo@endlessm.com>
*/
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8b-gpio.h>
+#include <dt-bindings/power/meson8-power.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#include "meson.dtsi"
@@ -172,6 +174,14 @@
#size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>;
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8b-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
dmcbus: bus@6000 {
compatible = "simple-bus";
reg = <0x6000 0x400>;
@@ -353,6 +363,16 @@
};
};
+ sdxc_c_pins: sdxc-c {
+ mux {
+ groups = "sdxc_d0_c", "sdxc_d13_c",
+ "sdxc_d47_c", "sdxc_clk_c",
+ "sdxc_cmd_c";
+ function = "sdxc_c";
+ bias-pull-up;
+ };
+ };
+
pwm_c1_pins: pwm-c1 {
mux {
groups = "pwm_c1";
@@ -416,13 +436,16 @@
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
resets = <&reset RESET_ETHERNET>;
reset-names = "stmmaceth";
+
+ power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
};
&gpio_intc {
@@ -433,10 +456,36 @@
&hhi {
clkc: clock-controller {
- compatible = "amlogic,meson8-clkc";
+ compatible = "amlogic,meson8b-clkc";
+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ clock-names = "xtal", "ddr_pll";
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ pwrc: power-controller {
+ compatible = "amlogic,meson8b-pwrc";
+ #power-domain-cells = <1>;
+ amlogic,ao-sysctrl = <&pmu>;
+ resets = <&reset RESET_DBLK>,
+ <&reset RESET_PIC_DC>,
+ <&reset RESET_HDMI_APB>,
+ <&reset RESET_HDMI_SYSTEM_RESET>,
+ <&reset RESET_VENCI>,
+ <&reset RESET_VENCP>,
+ <&reset RESET_VDAC_4>,
+ <&reset RESET_VENCL>,
+ <&reset RESET_VIU>,
+ <&reset RESET_VENC>,
+ <&reset RESET_RDMA>;
+ reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
+ "venci", "vencp", "vdac", "vencl", "viu",
+ "venc", "rdma";
+ clocks = <&clkc CLKID_VPU>;
+ clock-names = "vpu";
+ assigned-clocks = <&clkc CLKID_VPU>;
+ assigned-clock-rates = <182142857>;
+ };
};
&hwrng {
@@ -508,14 +557,23 @@
&saradc {
compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
- clocks = <&clkc CLKID_XTAL>,
- <&clkc CLKID_SAR_ADC>;
+ clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
clock-names = "clkin", "core";
amlogic,hhi-sysctrl = <&hhi>;
nvmem-cells = <&temperature_calib>;
nvmem-cell-names = "temperature_calib";
};
+&sdhc {
+ compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
+ clocks = <&xtal>,
+ <&clkc CLKID_FCLK_DIV4>,
+ <&clkc CLKID_FCLK_DIV3>,
+ <&clkc CLKID_FCLK_DIV5>,
+ <&clkc CLKID_SDHC>;
+ clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
+};
+
&sdio {
compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
@@ -523,32 +581,32 @@
};
&timer_abcde {
- clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "pclk";
};
&uart_AO {
- compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
- clock-names = "baud", "xtal", "pclk";
+ compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart";
+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "pclk", "baud";
};
&uart_A {
- compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
- clock-names = "baud", "xtal", "pclk";
+ compatible = "amlogic,meson8b-uart";
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "pclk", "baud";
};
&uart_B {
- compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
- clock-names = "baud", "xtal", "pclk";
+ compatible = "amlogic,meson8b-uart";
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "pclk", "baud";
};
&uart_C {
- compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
- clock-names = "baud", "xtal", "pclk";
+ compatible = "amlogic,meson8b-uart";
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "pclk", "baud";
};
&usb0 {
diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
index 84b6ed5..8f4eb1e 100644
--- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
+++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts
@@ -69,9 +69,7 @@
pinctrl-names = "default";
phy-handle = <ð_phy0>;
- phy-mode = "rgmii";
-
- amlogic,tx-delay-ns = <4>;
+ phy-mode = "rgmii-id";
mdio {
compatible = "snps,dwmac-mdio";
diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi
index 5bde7f5..6725dd9 100644
--- a/arch/arm/boot/dts/meson8m2.dtsi
+++ b/arch/arm/boot/dts/meson8m2.dtsi
@@ -30,8 +30,9 @@
0xc1108140 0x8>;
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
resets = <&reset RESET_ETHERNET>;
reset-names = "stmmaceth";
};
@@ -60,10 +61,41 @@
};
};
+&pwrc {
+ compatible = "amlogic,meson8m2-pwrc";
+ resets = <&reset RESET_DBLK>,
+ <&reset RESET_PIC_DC>,
+ <&reset RESET_HDMI_APB>,
+ <&reset RESET_HDMI_SYSTEM_RESET>,
+ <&reset RESET_VENCI>,
+ <&reset RESET_VENCP>,
+ <&reset RESET_VDAC_4>,
+ <&reset RESET_VENCL>,
+ <&reset RESET_VIU>,
+ <&reset RESET_VENC>,
+ <&reset RESET_RDMA>;
+ reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci",
+ "vencp", "vdac", "vencl", "viu", "venc", "rdma";
+ assigned-clocks = <&clkc CLKID_VPU>;
+ assigned-clock-rates = <364000000>;
+};
+
&saradc {
compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
};
+&sdhc {
+ compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc";
+};
+
+&usb0_phy {
+ compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
+};
+
+&usb1_phy {
+ compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
+};
+
&wdt {
compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
};
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
index aaedc4c..04f1ae1 100644
--- a/arch/arm/boot/dts/mmp2-brownstone.dts
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -19,176 +19,174 @@
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
+};
- soc {
- apb@d4000000 {
- uart3: uart@d4018000 {
- status = "okay";
- };
- twsi1: i2c@d4011000 {
- status = "okay";
- pmic: max8925@3c {
- compatible = "maxium,max8925";
- reg = <0x3c>;
- interrupts = <1>;
- interrupt-parent = <&intcmux4>;
- interrupt-controller;
- #interrupt-cells = <1>;
- maxim,tsc-irq = <0>;
+&uart3 {
+ status = "okay";
+};
- regulators {
- SDV1 {
- regulator-min-microvolt = <637500>;
- regulator-max-microvolt = <1425000>;
- regulator-boot-on;
- regulator-always-on;
- };
- SDV2 {
- regulator-min-microvolt = <650000>;
- regulator-max-microvolt = <2225000>;
- regulator-boot-on;
- regulator-always-on;
- };
- SDV3 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO1 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO2 {
- regulator-min-microvolt = <650000>;
- regulator-max-microvolt = <2250000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO3 {
- regulator-min-microvolt = <650000>;
- regulator-max-microvolt = <2250000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO4 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO5 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO6 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO7 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO8 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO9 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO10 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- };
- LDO11 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO12 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO13 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO14 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO15 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO16 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO17 {
- regulator-min-microvolt = <650000>;
- regulator-max-microvolt = <2250000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO18 {
- regulator-min-microvolt = <650000>;
- regulator-max-microvolt = <2250000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO19 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO20 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- backlight {
- maxim,max8925-dual-string = <0>;
- };
- charger {
- batt-detect = <0>;
- topoff-threshold = <1>;
- fast-charge = <7>;
- no-temp-support = <0>;
- no-insert-detect = <0>;
- };
- };
+&twsi1 {
+ status = "okay";
+ pmic: max8925@3c {
+ compatible = "maxium,max8925";
+ reg = <0x3c>;
+ interrupts = <1>;
+ interrupt-parent = <&intcmux4>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ maxim,tsc-irq = <0>;
+
+ regulators {
+ SDV1 {
+ regulator-min-microvolt = <637500>;
+ regulator-max-microvolt = <1425000>;
+ regulator-boot-on;
+ regulator-always-on;
};
- rtc: rtc@d4010000 {
- status = "okay";
+ SDV2 {
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <2225000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ SDV3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO1 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO2 {
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <2250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO3 {
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <2250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO4 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO5 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO6 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO7 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO8 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO9 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO10 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ };
+ LDO11 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO12 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO13 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO14 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO15 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO16 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO17 {
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <2250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO18 {
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <2250000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO19 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO20 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <3900000>;
+ regulator-boot-on;
+ regulator-always-on;
};
};
+ backlight {
+ maxim,max8925-dual-string = <0>;
+ };
+ charger {
+ batt-detect = <0>;
+ topoff-threshold = <1>;
+ fast-charge = <7>;
+ no-temp-support = <0>;
+ no-insert-detect = <0>;
+ };
};
};
+
+&rtc {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts b/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts
index 6cfa0d4..342304f 100644
--- a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts
+++ b/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts
@@ -57,30 +57,12 @@
linux,code = <SW_TABLET_MODE>;
wakeup-source;
};
-
- microphone_insert {
- label = "Microphone Plug";
- gpios = <&gpio 96 GPIO_ACTIVE_HIGH>;
- linux,input-type = <EV_SW>;
- linux,code = <SW_MICROPHONE_INSERT>;
- debounce-interval = <100>;
- wakeup-source;
- };
-
- headphone_insert {
- label = "Headphone Plug";
- gpios = <&gpio 97 GPIO_ACTIVE_HIGH>;
- linux,input-type = <EV_SW>;
- linux,code = <SW_HEADPHONE_INSERT>;
- debounce-interval = <100>;
- wakeup-source;
- };
};
- camera_i2c {
+ i2c {
compatible = "i2c-gpio";
- gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>,
- <&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
i2c-gpio,timeout-ms = <1000>;
@@ -123,6 +105,18 @@
reset-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>;
};
+ sound-card {
+ compatible = "audio-graph-card";
+ label = "OLPC XO";
+ dais = <&sspa0_dai>;
+ routing = "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "MIC2", "Mic Jack";
+ widgets = "Headphone", "Headphones", "Microphone", "Mic Jack";
+ hp-det-gpio = <&gpio 97 GPIO_ACTIVE_HIGH>;
+ mic-det-gpio = <&gpio 96 GPIO_ACTIVE_HIGH>;
+ };
+
soc {
axi@d4200000 {
ap-sp@d4290000 {
@@ -197,6 +191,14 @@
compatible = "realtek,alc5631";
reg = <0x1a>;
status = "okay";
+
+ port {
+ rt5631_0: endpoint {
+ mclk-fs = <256>;
+ clocks = <&audio_clk 0>;
+ remote-endpoint = <&sspa0_0>;
+ };
+ };
};
};
@@ -224,12 +226,12 @@
#address-cells = <0>;
spi-slave;
status = "okay";
- ready-gpio = <&gpio 125 GPIO_ACTIVE_HIGH>;
+ ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>;
slave {
compatible = "olpc,xo1.75-ec";
spi-cpha;
- cmd-gpio = <&gpio 155 GPIO_ACTIVE_HIGH>;
+ cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>;
};
};
@@ -242,3 +244,34 @@
};
};
};
+
+&asram {
+ status = "okay";
+};
+
+&adma0 {
+ status = "okay";
+};
+
+&audio_clk {
+ status = "okay";
+};
+
+&sspa0 {
+ status = "okay";
+ dmas = <&adma0 0>, <&adma0 1>;
+ dma-names = "tx", "rx";
+
+ sspa0_dai: port {
+ sspa0_0: endpoint {
+ remote-endpoint = <&rt5631_0>;
+ frame-master;
+ bitclock-master;
+ dai-format = "i2s";
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 6a2f072..445bdcd 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/clock/marvell,mmp2.h>
+#include <dt-bindings/power/marvell,mmp2.h>
/ {
#address-cells = <1>;
@@ -38,6 +39,17 @@
reg = <0xd4200000 0x00200000>;
ranges;
+ gpu: gpu@d420d000 {
+ compatible = "vivante,gc";
+ reg = <0xd420d000 0x4000>;
+ interrupts = <8>;
+ status = "disabled";
+ clocks = <&soc_clocks MMP2_CLK_GPU_3D>,
+ <&soc_clocks MMP2_CLK_GPU_BUS>;
+ clock-names = "core", "bus";
+ power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
+ };
+
intc: interrupt-controller@d4282000 {
compatible = "mrvl,mmp2-intc";
interrupt-controller;
@@ -192,6 +204,63 @@
clock-output-names = "mclk";
status = "disabled";
};
+
+ adma0: dma-controller@d42a0800 {
+ compatible = "marvell,adma-1.0";
+ reg = <0xd42a0800 0x100>;
+ interrupts = <48>;
+ #dma-cells = <1>;
+ asram = <&asram>;
+ iram = <&asram>;
+ status = "disabled";
+ };
+
+ adma1: dma-controller@d42a0900 {
+ compatible = "marvell,adma-1.0";
+ reg = <0xd42a0900 0x100>;
+ interrupts = <48>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ audio_clk: clocks@d42a0c30 {
+ compatible = "marvell,mmp2-audio-clock";
+ reg = <0xd42a0c30 0x10>;
+ clock-names = "audio", "vctcxo", "i2s0", "i2s1";
+ clocks = <&soc_clocks MMP2_CLK_AUDIO>,
+ <&soc_clocks MMP2_CLK_VCTCXO>,
+ <&soc_clocks MMP2_CLK_I2S0>,
+ <&soc_clocks MMP2_CLK_I2S1>;
+ power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
+ #clock-cells = <1>;
+ status = "disabled";
+ };
+
+ sspa0: audio-controller@d42a0c00 {
+ compatible = "marvell,mmp-sspa";
+ reg = <0xd42a0c00 0x30>,
+ <0xd42a0c80 0x30>;
+ interrupts = <2>;
+ clock-names = "audio", "bitclk";
+ clocks = <&soc_clocks MMP2_CLK_AUDIO>,
+ <&audio_clk 1>;
+ power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ sspa1: audio-controller@d42a0d00 {
+ compatible = "marvell,mmp-sspa";
+ reg = <0xd42a0d00 0x30>,
+ <0xd42a0d80 0x30>;
+ interrupts = <3>;
+ clock-names = "audio", "bitclk";
+ clocks = <&soc_clocks MMP2_CLK_AUDIO>,
+ <&audio_clk 2>;
+ power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
};
apb@d4000000 { /* APB */
@@ -201,6 +270,14 @@
reg = <0xd4000000 0x00200000>;
ranges;
+ dma-controller@d4000000 {
+ compatible = "marvell,pdma-1.0";
+ reg = <0xd4000000 0x10000>;
+ interrupts = <48>;
+ #dma-channels = <16>;
+ status = "disabled";
+ };
+
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
@@ -208,8 +285,8 @@
clocks = <&soc_clocks MMP2_CLK_TIMER>;
};
- uart1: uart@d4030000 {
- compatible = "mrvl,mmp-uart";
+ uart1: serial@d4030000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4030000 0x1000>;
interrupts = <27>;
clocks = <&soc_clocks MMP2_CLK_UART0>;
@@ -218,8 +295,8 @@
status = "disabled";
};
- uart2: uart@d4017000 {
- compatible = "mrvl,mmp-uart";
+ uart2: serial@d4017000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4017000 0x1000>;
interrupts = <28>;
clocks = <&soc_clocks MMP2_CLK_UART1>;
@@ -228,8 +305,8 @@
status = "disabled";
};
- uart3: uart@d4018000 {
- compatible = "mrvl,mmp-uart";
+ uart3: serial@d4018000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4018000 0x1000>;
interrupts = <24>;
clocks = <&soc_clocks MMP2_CLK_UART2>;
@@ -238,8 +315,8 @@
status = "disabled";
};
- uart4: uart@d4016000 {
- compatible = "mrvl,mmp-uart";
+ uart4: serial@d4016000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4016000 0x1000>;
interrupts = <46>;
clocks = <&soc_clocks MMP2_CLK_UART3>;
@@ -364,7 +441,7 @@
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0xd4010000 0x1000>;
- interrupts = <1 0>;
+ interrupts = <1>, <0>;
interrupt-names = "rtc 1Hz", "rtc alarm";
interrupt-parent = <&intcmux5>;
clocks = <&soc_clocks MMP2_CLK_RTC>;
@@ -413,14 +490,24 @@
};
};
+ asram: sram@e0000000 {
+ compatible = "mmio-sram";
+ reg = <0xe0000000 0x10000>;
+ ranges = <0 0xe0000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+
soc_clocks: clocks {
compatible = "marvell,mmp2-clock";
- reg = <0xd4050000 0x1000>,
+ reg = <0xd4050000 0x2000>,
<0xd4282800 0x400>,
<0xd4015000 0x1000>;
reg-names = "mpmu", "apmu", "apbc";
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
};
};
};
diff --git a/arch/arm/boot/dts/mmp3-dell-ariel.dts b/arch/arm/boot/dts/mmp3-dell-ariel.dts
new file mode 100644
index 0000000..fe3b1cd
--- /dev/null
+++ b/arch/arm/boot/dts/mmp3-dell-ariel.dts
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Dell Wyse 3020 a.k.a. "Ariel" a.k.a. Tx0D (T00D, T10D)
+ *
+ * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+
+/dts-v1/;
+#include "mmp3.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "Dell Ariel";
+ compatible = "dell,wyse-ariel", "marvell,mmp3";
+
+ aliases {
+ serial2 = &uart3;
+ };
+
+ chosen {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges;
+ bootargs = "earlyprintk=ttyS2,115200 console=ttyS2,115200";
+ };
+
+ memory@0 {
+ linux,usable-memory = <0x0 0x7f600000>;
+ available = <0x7f700000 0x7ff00000 0x00000000 0x7f600000>;
+ reg = <0x0 0x80000000>;
+ device_type = "memory";
+ };
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&usb_otg0 {
+ status = "okay";
+};
+
+&usb_otg_phy0 {
+ status = "okay";
+};
+
+&hsic0 {
+ status = "okay";
+
+ usb1@1 {
+ compatible = "usb424,2640";
+ reg = <0x01>;
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ mass-storage@1 {
+ compatible = "usb424,4040";
+ reg = <0x01>;
+ status = "disabled";
+ };
+ };
+};
+
+&hsic_phy0 {
+ status = "okay";
+ reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
+};
+
+&mmc3 {
+ status = "okay";
+ max-frequency = <50000000>;
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-highspeed;
+};
+
+&twsi1 {
+ status = "okay";
+
+ rtc@68 {
+ compatible = "dallas,ds1338";
+ reg = <0x68>;
+ status = "okay";
+ };
+};
+
+&twsi3 {
+ status = "okay";
+};
+
+&twsi4 {
+ status = "okay";
+};
+
+&ssp1 {
+ status = "okay";
+ cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+
+ firmware-flash@0 {
+ compatible = "winbond,w25q32", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ m25p,fast-read;
+ };
+};
+
+&ssp2 {
+ cs-gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&gpu_2d {
+ status = "okay";
+};
+
+&gpu_3d {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi
new file mode 100644
index 0000000..4ae630d
--- /dev/null
+++ b/arch/arm/boot/dts/mmp3.dtsi
@@ -0,0 +1,606 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+
+#include <dt-bindings/clock/marvell,mmp2.h>
+#include <dt-bindings/power/marvell,mmp2.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "marvell,mmp3-smp";
+
+ cpu@0 {
+ compatible = "marvell,pj4b";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "marvell,pj4b";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <1>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ axi@d4200000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xd4200000 0x00200000>;
+ ranges;
+
+ interrupt-controller@d4282000 {
+ compatible = "marvell,mmp3-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xd4282000 0x1000>,
+ <0xd4284000 0x100>;
+ mrvl,intc-nr-irqs = <64>;
+ };
+
+ pmic_mux: interrupt-controller@d4282150 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x150 0x4>, <0x168 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <4>;
+ };
+
+ rtc_mux: interrupt-controller@d4282154 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x154 0x4>, <0x16c 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+
+ hsi3_mux: interrupt-controller@d42821bc {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1bc 0x4>, <0x1a4 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <3>;
+ };
+
+ gpu_mux: interrupt-controller@d42821c0 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1c0 0x4>, <0x1a8 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <3>;
+ };
+
+ twsi_mux: interrupt-controller@d4282158 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x158 0x4>, <0x170 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <5>;
+ };
+
+ hsi2_mux: interrupt-controller@d42821c4 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1c4 0x4>, <0x1ac 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+
+ dxo_mux: interrupt-controller@d42821c8 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1c8 0x4>, <0x1b0 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+
+ misc1_mux: interrupt-controller@d428215c {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x15c 0x4>, <0x174 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <31>;
+ };
+
+ ci_mux: interrupt-controller@d42821cc {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1cc 0x4>, <0x1b4 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+
+ ssp_mux: interrupt-controller@d4282160 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x160 0x4>, <0x178 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+
+ hsi1_mux: interrupt-controller@d4282184 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x184 0x4>, <0x17c 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <4>;
+ };
+
+ misc2_mux: interrupt-controller@d4282188 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x188 0x4>, <0x180 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <20>;
+ };
+
+ hsi0_mux: interrupt-controller@d42821d0 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x1d0 0x4>, <0x1b8 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <5>;
+ };
+
+ usb_otg_phy0: usb-phy@d4207000 {
+ compatible = "marvell,mmp3-usb-phy";
+ reg = <0xd4207000 0x40>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb_otg0: usb@d4208000 {
+ compatible = "marvell,pxau2o-ehci";
+ reg = <0xd4208000 0x200>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_USB>;
+ clock-names = "USBCLK";
+ phys = <&usb_otg_phy0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ hsic_phy0: usb-phy@f0001800 {
+ compatible = "marvell,mmp3-hsic-phy";
+ reg = <0xf0001800 0x40>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ hsic0: usb@f0001000 {
+ compatible = "marvell,pxau2o-ehci";
+ reg = <0xf0001000 0x200>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
+ clock-names = "USBCLK";
+ phys = <&hsic_phy0>;
+ phy-names = "usb";
+ phy_type = "hsic";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ };
+
+ hsic_phy1: usb-phy@f0002800 {
+ compatible = "marvell,mmp3-hsic-phy";
+ reg = <0xf0002800 0x40>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ hsic1: usb@f0002000 {
+ compatible = "marvell,pxau2o-ehci";
+ reg = <0xf0002000 0x200>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
+ clock-names = "USBCLK";
+ phys = <&hsic_phy1>;
+ phy-names = "usb";
+ phy_type = "hsic";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@d4280000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4280000 0x120>;
+ clocks = <&soc_clocks MMP2_CLK_SDH0>;
+ clock-names = "io";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@d4280800 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4280800 0x120>;
+ clocks = <&soc_clocks MMP2_CLK_SDH1>;
+ clock-names = "io";
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mmc3: mmc@d4281000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4281000 0x120>;
+ clocks = <&soc_clocks MMP2_CLK_SDH2>;
+ clock-names = "io";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mmc4: mmc@d4281800 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4281800 0x120>;
+ clocks = <&soc_clocks MMP2_CLK_SDH3>;
+ clock-names = "io";
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ mmc5: mmc@d4217000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4217000 0x120>;
+ clocks = <&soc_clocks MMP3_CLK_SDH4>;
+ clock-names = "io";
+ interrupt-parent = <&hsi1_mux>;
+ interrupts = <0>;
+ status = "disabled";
+ };
+
+ camera0: camera@d420a000 {
+ compatible = "marvell,mmp2-ccic";
+ reg = <0xd420a000 0x800>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_CCIC0>;
+ clock-names = "axi";
+ power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ status = "disabled";
+ };
+
+ camera1: camera@d420a800 {
+ compatible = "marvell,mmp2-ccic";
+ reg = <0xd420a800 0x800>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_CCIC1>;
+ clock-names = "axi";
+ power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ status = "disabled";
+ };
+
+ gpu_3d: gpu@d420d000 {
+ compatible = "vivante,gc";
+ reg = <0xd420d000 0x2000>;
+ interrupt-parent = <&gpu_mux>;
+ interrupts = <0>;
+ status = "disabled";
+ clocks = <&soc_clocks MMP3_CLK_GPU_3D>,
+ <&soc_clocks MMP3_CLK_GPU_BUS>;
+ clock-names = "core", "bus";
+ power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
+ };
+
+ gpu_2d: gpu@d420f000 {
+ compatible = "vivante,gc";
+ reg = <0xd420f000 0x2000>;
+ interrupt-parent = <&gpu_mux>;
+ interrupts = <2>;
+ status = "disabled";
+ clocks = <&soc_clocks MMP3_CLK_GPU_2D>,
+ <&soc_clocks MMP3_CLK_GPU_BUS>;
+ clock-names = "core", "bus";
+ power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
+ };
+ };
+
+ apb@d4000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xd4000000 0x00200000>;
+ ranges;
+
+ timer: timer@d4014000 {
+ compatible = "mrvl,mmp-timer";
+ reg = <0xd4014000 0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_TIMER>;
+ };
+
+ uart1: serial@d4030000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0xd4030000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_UART0>;
+ resets = <&soc_clocks MMP2_CLK_UART0>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@d4017000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0xd4017000 0x1000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_UART1>;
+ resets = <&soc_clocks MMP2_CLK_UART1>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@d4018000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0xd4018000 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_UART2>;
+ resets = <&soc_clocks MMP2_CLK_UART2>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@d4016000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0xd4016000 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_UART3>;
+ resets = <&soc_clocks MMP2_CLK_UART3>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ gpio: gpio@d4019000 {
+ compatible = "marvell,mmp2-gpio";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xd4019000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpio_mux";
+ clocks = <&soc_clocks MMP2_CLK_GPIO>;
+ resets = <&soc_clocks MMP2_CLK_GPIO>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges;
+
+ gcb0: gpio@d4019000 {
+ reg = <0xd4019000 0x4>;
+ };
+
+ gcb1: gpio@d4019004 {
+ reg = <0xd4019004 0x4>;
+ };
+
+ gcb2: gpio@d4019008 {
+ reg = <0xd4019008 0x4>;
+ };
+
+ gcb3: gpio@d4019100 {
+ reg = <0xd4019100 0x4>;
+ };
+
+ gcb4: gpio@d4019104 {
+ reg = <0xd4019104 0x4>;
+ };
+
+ gcb5: gpio@d4019108 {
+ reg = <0xd4019108 0x4>;
+ };
+ };
+
+ twsi1: i2c@d4011000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4011000 0x70>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI0>;
+ resets = <&soc_clocks MMP2_CLK_TWSI0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ twsi2: i2c@d4031000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4031000 0x70>;
+ interrupt-parent = <&twsi_mux>;
+ interrupts = <0>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI1>;
+ resets = <&soc_clocks MMP2_CLK_TWSI1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ twsi3: i2c@d4032000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4032000 0x70>;
+ interrupt-parent = <&twsi_mux>;
+ interrupts = <1>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI2>;
+ resets = <&soc_clocks MMP2_CLK_TWSI2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ twsi4: i2c@d4033000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4033000 0x70>;
+ interrupt-parent = <&twsi_mux>;
+ interrupts = <2>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI3>;
+ resets = <&soc_clocks MMP2_CLK_TWSI3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+
+ twsi5: i2c@d4033800 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4033800 0x70>;
+ interrupt-parent = <&twsi_mux>;
+ interrupts = <3>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI4>;
+ resets = <&soc_clocks MMP2_CLK_TWSI4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ twsi6: i2c@d4034000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4034000 0x70>;
+ interrupt-parent = <&twsi_mux>;
+ interrupts = <4>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI5>;
+ resets = <&soc_clocks MMP2_CLK_TWSI5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rtc: rtc@d4010000 {
+ compatible = "mrvl,mmp-rtc";
+ reg = <0xd4010000 0x1000>;
+ interrupts = <1>, <0>;
+ interrupt-names = "rtc 1Hz", "rtc alarm";
+ interrupt-parent = <&rtc_mux>;
+ clocks = <&soc_clocks MMP2_CLK_RTC>;
+ resets = <&soc_clocks MMP2_CLK_RTC>;
+ status = "disabled";
+ };
+
+ ssp1: spi@d4035000 {
+ compatible = "marvell,mmp2-ssp";
+ reg = <0xd4035000 0x1000>;
+ clocks = <&soc_clocks MMP2_CLK_SSP0>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssp2: spi@d4036000 {
+ compatible = "marvell,mmp2-ssp";
+ reg = <0xd4036000 0x1000>;
+ clocks = <&soc_clocks MMP2_CLK_SSP1>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssp3: spi@d4037000 {
+ compatible = "marvell,mmp2-ssp";
+ reg = <0xd4037000 0x1000>;
+ clocks = <&soc_clocks MMP2_CLK_SSP2>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssp4: spi@d4039000 {
+ compatible = "marvell,mmp2-ssp";
+ reg = <0xd4039000 0x1000>;
+ clocks = <&soc_clocks MMP2_CLK_SSP3>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ l2: cache-controller@d0020000 {
+ compatible = "marvell,tauros3-cache", "arm,pl310-cache";
+ reg = <0xd0020000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ soc_clocks: clocks@d4050000 {
+ compatible = "marvell,mmp3-clock";
+ reg = <0xd4050000 0x1000>,
+ <0xd4282800 0x400>,
+ <0xd4015000 0x1000>;
+ reg-names = "mpmu", "apmu", "apbc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ snoop-control-unit@e0000000 {
+ compatible = "arm,arm11mp-scu";
+ reg = <0xe0000000 0x100>;
+ };
+
+ gic: interrupt-controller@e0001000 {
+ compatible = "arm,arm11mp-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0xe0001000 0x1000>,
+ <0xe0000100 0x100>;
+ };
+
+ local-timer@e0000600 {
+ compatible = "arm,arm11mp-twd-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ reg = <0xe0000600 0x20>;
+ };
+
+ watchdog@e0000620 {
+ compatible = "arm,arm11mp-twd-wdt";
+ reg = <0xe0000620 0x20>;
+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
index ab91c4e..08a7d3c 100644
--- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
+++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
@@ -29,11 +29,12 @@
compatible = "motorola,cpcap-battery";
interrupts-extended = <
&cpcap 6 0 &cpcap 5 0 &cpcap 3 0
- &cpcap 20 0 &cpcap 54 0
+ &cpcap 20 0 &cpcap 54 0 &cpcap 57 0
>;
interrupt-names =
"eol", "lowbph", "lowbpl",
- "chrgcurr1", "battdetb";
+ "chrgcurr1", "battdetb",
+ "cccal";
io-channels = <&cpcap_adc 0 &cpcap_adc 1
&cpcap_adc 5 &cpcap_adc 6>;
io-channel-names = "battdetb", "battp",
@@ -45,11 +46,13 @@
compatible = "motorola,mapphone-cpcap-charger";
interrupts-extended = <
&cpcap 13 0 &cpcap 12 0 &cpcap 29 0 &cpcap 28 0
- &cpcap 22 0 &cpcap 20 0 &cpcap 19 0 &cpcap 54 0
+ &cpcap 22 0 &cpcap 21 0 &cpcap 20 0 &cpcap 19 0
+ &cpcap 54 0
>;
interrupt-names =
"chrg_det", "rvrs_chrg", "chrg_se1b", "se0conn",
- "rvrs_mode", "chrgcurr1", "vbusvld", "battdetb";
+ "rvrs_mode", "chrgcurr2", "chrgcurr1", "vbusvld",
+ "battdetb";
mode-gpios = <&gpio3 29 GPIO_ACTIVE_LOW
&gpio3 23 GPIO_ACTIVE_LOW>;
io-channels = <&cpcap_adc 0 &cpcap_adc 1
diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi
new file mode 100644
index 0000000..d5ded4f
--- /dev/null
+++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi
@@ -0,0 +1,853 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "omap443x.dtsi"
+#include "motorola-cpcap-mapphone.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ display0 = &lcd0;
+ display1 = &hdmi0;
+ };
+
+ /*
+ * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
+ * then 1023 - 1024 seems to contain mbm.
+ */
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x3fd00000>; /* 1021 MB */
+ };
+
+ /* Poweroff GPIO probably connected to CPCAP */
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-0 = <&poweroff_gpio>;
+ pinctrl-names = "default";
+ gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */
+ };
+
+ hdmi0: connector {
+ compatible = "hdmi-connector";
+ pinctrl-0 = <&hdmi_hpd_gpio>;
+ pinctrl-names = "default";
+ label = "hdmi";
+ type = "d";
+
+ hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_out>;
+ };
+ };
+ };
+
+ /*
+ * HDMI 5V regulator probably sourced from battery. Let's keep
+ * keep this as always enabled for HDMI to work until we've
+ * figured what the encoder chip is.
+ */
+ hdmi_regulator: regulator-hdmi {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* FS USB Host PHY on port 1 for mdm6600 */
+ fsusb1_phy: usb-phy@1 {
+ compatible = "motorola,mapphone-mdm6600";
+ pinctrl-0 = <&usb_mdm6600_pins>;
+ pinctrl-names = "default";
+ enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */
+ power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */
+ reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */
+ /* mode: gpio_148 gpio_149 */
+ motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
+ <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ /* cmd: gpio_103 gpio_104 gpio_142 */
+ motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
+ <&gpio4 8 GPIO_ACTIVE_HIGH>,
+ <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ /* status: gpio_52 gpio_53 gpio_55 */
+ motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
+ <&gpio2 21 GPIO_ACTIVE_HIGH>,
+ <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ #phy-cells = <0>;
+ };
+
+ /* HS USB host TLL nop-phy on port 2 for w3glte */
+ hsusb2_phy: usb-phy@2 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ /* LCD regulator from sw5 source */
+ lcd_regulator: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd";
+ regulator-min-microvolt = <5050000>;
+ regulator-max-microvolt = <5050000>;
+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */
+ enable-active-high;
+ vin-supply = <&sw5>;
+ };
+
+ /* This is probably coming straight from the battery.. */
+ wl12xx_vmmc: regulator-wl12xx {
+ compatible = "regulator-fixed";
+ regulator-name = "vwl1271";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1650000>;
+ gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ volume_down {
+ label = "Volume Down";
+ gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */
+ linux,code = <KEY_VOLUMEDOWN>;
+ linux,can-disable;
+ /* Value above 7.95ms for no GPIO hardware debounce */
+ debounce-interval = <10>;
+ };
+
+ slider {
+ label = "Keypad Slide";
+ gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_KEYPAD_SLIDE>;
+ linux,can-disable;
+ /* Value above 7.95ms for no GPIO hardware debounce */
+ debounce-interval = <10>;
+ };
+ };
+
+ soundcard {
+ compatible = "audio-graph-card";
+ label = "Droid 4 Audio";
+
+ widgets =
+ "Speaker", "Earpiece",
+ "Speaker", "Loudspeaker",
+ "Headphone", "Headphone Jack",
+ "Microphone", "Internal Mic";
+
+ routing =
+ "Earpiece", "EP",
+ "Loudspeaker", "SPKR",
+ "Headphone Jack", "HSL",
+ "Headphone Jack", "HSR",
+ "MICR", "Internal Mic";
+
+ dais = <&mcbsp2_port>, <&mcbsp3_port>;
+ };
+
+ pwm8: dmtimer-pwm-8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_direction_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer8>;
+ ti,clock-source = <0x01>;
+ };
+
+ pwm9: dmtimer-pwm-9 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_enable_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer9>;
+ ti,clock-source = <0x01>;
+ };
+
+ vibrator {
+ compatible = "pwm-vibrator";
+ pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>;
+ pwm-names = "enable", "direction";
+ direction-duty-cycle-ns = <10000000>;
+ };
+
+ backlight: backlight {
+ compatible = "led-backlight";
+
+ leds = <&backlight_led>;
+ brightness-levels = <31 63 95 127 159 191 223 255>;
+ default-brightness-level = <6>;
+ };
+};
+
+&dss {
+ status = "okay";
+};
+
+&dsi1 {
+ status = "okay";
+ vdd-supply = <&vcsi>;
+
+ port {
+ dsi1_out_ep: endpoint {
+ remote-endpoint = <&lcd0_in>;
+ lanes = <0 1 2 3 4 5>;
+ };
+ };
+
+ lcd0: panel@0 {
+ compatible = "motorola,droid4-panel", "panel-dsi-cm";
+ reg = <0>;
+ label = "lcd0";
+ vddi-supply = <&lcd_regulator>;
+ reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */
+
+ backlight = <&backlight>;
+
+ width-mm = <50>;
+ height-mm = <89>;
+ rotation = <90>;
+
+ panel-timing {
+ clock-frequency = <0>; /* Calculated by dsi */
+
+ hback-porch = <2>;
+ hactive = <540>;
+ hfront-porch = <0>;
+ hsync-len = <2>;
+
+ vback-porch = <1>;
+ vactive = <960>;
+ vfront-porch = <0>;
+ vsync-len = <1>;
+
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+
+ port {
+ lcd0_in: endpoint {
+ remote-endpoint = <&dsi1_out_ep>;
+ };
+ };
+ };
+};
+
+&hdmi {
+ status = "okay";
+ pinctrl-0 = <&dss_hdmi_pins>;
+ pinctrl-names = "default";
+ vdda-supply = <&vdac>;
+
+ port {
+ hdmi_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ lanes = <1 0 3 2 5 4 7 6>;
+ };
+ };
+};
+
+/* Battery NVRAM on 1-wire handled by w1_ds250x driver */
+&hdqw1w {
+ pinctrl-0 = <&hdq_pins>;
+ pinctrl-names = "default";
+ ti,mode = "1w";
+};
+
+&i2c1 {
+ tmp105@48 {
+ compatible = "ti,tmp105";
+ reg = <0x48>;
+ pinctrl-0 = <&tmp105_irq>;
+ pinctrl-names = "default";
+ /* kpd_row0.gpio_178 */
+ interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING
+ &omap4_pmx_core 0x14e>;
+ interrupt-names = "irq", "wakeup";
+ wakeup-source;
+ };
+};
+
+&keypad {
+ keypad,num-rows = <8>;
+ keypad,num-columns = <8>;
+ linux,keymap = <
+
+ /* Row 1 */
+ MATRIX_KEY(0, 2, KEY_1)
+ MATRIX_KEY(0, 6, KEY_2)
+ MATRIX_KEY(2, 3, KEY_3)
+ MATRIX_KEY(0, 7, KEY_4)
+ MATRIX_KEY(0, 4, KEY_5)
+ MATRIX_KEY(5, 5, KEY_6)
+ MATRIX_KEY(0, 1, KEY_7)
+ MATRIX_KEY(0, 5, KEY_8)
+ MATRIX_KEY(0, 0, KEY_9)
+ MATRIX_KEY(1, 6, KEY_0)
+
+ /* Row 2 */
+ MATRIX_KEY(3, 4, KEY_APOSTROPHE)
+ MATRIX_KEY(7, 6, KEY_Q)
+ MATRIX_KEY(7, 7, KEY_W)
+ MATRIX_KEY(7, 2, KEY_E)
+ MATRIX_KEY(1, 0, KEY_R)
+ MATRIX_KEY(4, 4, KEY_T)
+ MATRIX_KEY(1, 2, KEY_Y)
+ MATRIX_KEY(6, 7, KEY_U)
+ MATRIX_KEY(2, 2, KEY_I)
+ MATRIX_KEY(5, 6, KEY_O)
+ MATRIX_KEY(3, 7, KEY_P)
+ MATRIX_KEY(6, 5, KEY_BACKSPACE)
+
+ /* Row 3 */
+ MATRIX_KEY(5, 4, KEY_TAB)
+ MATRIX_KEY(5, 7, KEY_A)
+ MATRIX_KEY(2, 7, KEY_S)
+ MATRIX_KEY(7, 0, KEY_D)
+ MATRIX_KEY(2, 6, KEY_F)
+ MATRIX_KEY(6, 2, KEY_G)
+ MATRIX_KEY(6, 6, KEY_H)
+ MATRIX_KEY(1, 4, KEY_J)
+ MATRIX_KEY(3, 1, KEY_K)
+ MATRIX_KEY(2, 1, KEY_L)
+ MATRIX_KEY(4, 6, KEY_ENTER)
+
+ /* Row 4 */
+ MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */
+ MATRIX_KEY(6, 1, KEY_Z)
+ MATRIX_KEY(7, 4, KEY_X)
+ MATRIX_KEY(5, 1, KEY_C)
+ MATRIX_KEY(1, 7, KEY_V)
+ MATRIX_KEY(2, 4, KEY_B)
+ MATRIX_KEY(4, 1, KEY_N)
+ MATRIX_KEY(1, 1, KEY_M)
+ MATRIX_KEY(3, 5, KEY_COMMA)
+ MATRIX_KEY(5, 2, KEY_DOT)
+ MATRIX_KEY(6, 3, KEY_UP)
+ MATRIX_KEY(7, 3, KEY_OK)
+
+ /* Row 5 */
+ MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */
+ MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */
+ MATRIX_KEY(6, 0, KEY_MINUS)
+ MATRIX_KEY(4, 7, KEY_EQUAL)
+ MATRIX_KEY(1, 5, KEY_SPACE)
+ MATRIX_KEY(3, 2, KEY_SLASH)
+ MATRIX_KEY(4, 3, KEY_LEFT)
+ MATRIX_KEY(5, 3, KEY_DOWN)
+ MATRIX_KEY(3, 3, KEY_RIGHT)
+
+ /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */
+ MATRIX_KEY(5, 0, KEY_VOLUMEUP)
+ >;
+};
+
+&mmc1 {
+ vmmc-supply = <&vwlan2>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */
+};
+
+&mmc2 {
+ vmmc-supply = <&vsdio>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins>;
+ vmmc-supply = <&wl12xx_vmmc>;
+ /* uart2_tx.sdmmc3_dat1 pad as wakeirq */
+ interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0xde>;
+ interrupt-names = "irq", "wakeup";
+ non-removable;
+ bus-width = <4>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1285", "ti,wl1283";
+ reg = <2>;
+ /* gpio_100 with gpmc_wait2 pad as wakeirq */
+ interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
+ <&omap4_pmx_core 0x4e>;
+ interrupt-names = "irq", "wakeup";
+ ref-clock-frequency = <26000000>;
+ tcxo-clock-frequency = <26000000>;
+ };
+};
+
+&i2c1 {
+ led-controller@38 {
+ compatible = "ti,lm3532";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x38>;
+
+ enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+
+ ramp-up-us = <1024>;
+ ramp-down-us = <8193>;
+
+ backlight_led: led@0 {
+ reg = <0>;
+ led-sources = <2>;
+ ti,led-mode = <0>;
+ label = ":backlight";
+ };
+
+ led@1 {
+ reg = <1>;
+ led-sources = <1>;
+ ti,led-mode = <0>;
+ label = ":kbd_backlight";
+ };
+ };
+};
+
+&i2c2 {
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */
+
+ /* gpio_183 with sys_nirq2 pad as wakeup */
+ interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>,
+ <&omap4_pmx_core 0x160>;
+ interrupt-names = "irq", "wakeup";
+ wakeup-source;
+ };
+
+ isl29030@44 {
+ compatible = "isil,isl29030";
+ reg = <0x44>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&als_proximity_pins>;
+
+ interrupt-parent = <&gpio6>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */
+ };
+};
+
+&omap4_pmx_core {
+
+ /* hdmi_hpd.gpio_63 */
+ hdmi_hpd_gpio: pinmux_hdmi_hpd_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3)
+ >;
+ };
+
+ hdq_pins: pinmux_hdq_pins {
+ pinctrl-single,pins = <
+ /* 0x4a100120 hdq_sio.hdq_sio aa27 */
+ OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0)
+ >;
+ };
+
+ /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
+ dss_hdmi_pins: pinmux_dss_hdmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0)
+ >;
+ };
+
+ /*
+ * Android uses PIN_OFF_INPUT_PULLDOWN | PIN_INPUT_PULLUP | MUX_MODE3
+ * for gpio_100, but the internal pull makes wlan flakey on some
+ * devices. Off mode value should be tested if we have off mode working
+ * later on.
+ */
+ mmc3_pins: pinmux_mmc3_pins {
+ pinctrl-single,pins = <
+ /* 0x4a10008e gpmc_wait2.gpio_100 d23 */
+ OMAP4_IOPAD(0x08e, PIN_INPUT | MUX_MODE3)
+
+ /* 0x4a100102 abe_mcbsp1_dx.sdmmc3_dat2 ab25 */
+ OMAP4_IOPAD(0x102, PIN_INPUT_PULLUP | MUX_MODE1)
+
+ /* 0x4a100104 abe_mcbsp1_fsx.sdmmc3_dat3 ac27 */
+ OMAP4_IOPAD(0x104, PIN_INPUT_PULLUP | MUX_MODE1)
+
+ /* 0x4a100118 uart2_cts.sdmmc3_clk ab26 */
+ OMAP4_IOPAD(0x118, PIN_INPUT | MUX_MODE1)
+
+ /* 0x4a10011a uart2_rts.sdmmc3_cmd ab27 */
+ OMAP4_IOPAD(0x11a, PIN_INPUT_PULLUP | MUX_MODE1)
+
+ /* 0x4a10011c uart2_rx.sdmmc3_dat0 aa25 */
+ OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE1)
+
+ /* 0x4a10011e uart2_tx.sdmmc3_dat1 aa26 */
+ OMAP4_IOPAD(0x11e, PIN_INPUT_PULLUP | MUX_MODE1)
+ >;
+ };
+
+ /* gpmc_ncs0.gpio_50 */
+ poweroff_gpio: pinmux_poweroff_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ /* kpd_row0.gpio_178 */
+ tmp105_irq: pinmux_tmp105_irq {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins {
+ /* gpio_60 */
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3)
+ >;
+ };
+
+ touchscreen_pins: pinmux_touchscreen_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ als_proximity_pins: pinmux_als_proximity_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ usb_mdm6600_pins: pinmux_usb_mdm6600_pins {
+ pinctrl-single,pins = <
+ /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */
+ OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3)
+
+ /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */
+ OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3)
+
+ /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */
+ OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3)
+
+ /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */
+ OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3)
+
+ /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */
+ OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3)
+
+ /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */
+ OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3)
+
+ /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */
+ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)
+
+ /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */
+ OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3)
+
+ /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */
+ OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3)
+
+ /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */
+ OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3)
+
+ /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */
+ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3)
+ >;
+ };
+
+ usb_ulpi_pins: pinmux_usb_ulpi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, MUX_MODE7)
+ OMAP4_IOPAD(0x198, MUX_MODE7)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0)
+ >;
+ };
+
+ /* usb0_otg_dp and usb0_otg_dm */
+ usb_utmi_pins: pinmux_usb_utmi_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+
+ /*
+ * Note that the v3.0.8 stock userspace dynamically remuxes uart1
+ * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7
+ * when not used. If needed, we can add rts pin remux later based
+ * on power measurements.
+ */
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */
+ OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1)
+
+ /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */
+ OMAP4_IOPAD(0x13e, MUX_MODE1)
+
+ /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */
+ OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1)
+
+ /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */
+ OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2)
+ >;
+ };
+
+ /* uart3_tx_irtx and uart3_rx_irrx */
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x196, MUX_MODE7)
+ OMAP4_IOPAD(0x198, MUX_MODE7)
+ OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1ba, MUX_MODE2)
+ OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2)
+ OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7)
+ OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
+ >;
+ };
+
+ uart4_pins: pinmux_uart4_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */
+ OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */
+ OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */
+ OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */
+ >;
+ };
+
+ mcbsp2_pins: pinmux_mcbsp2_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */
+ OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */
+ OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */
+ OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */
+ >;
+ };
+
+ mcbsp3_pins: pinmux_mcbsp3_pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */
+ OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */
+ OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */
+ OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */
+ >;
+ };
+
+ vibrator_direction_pin: pinmux_vibrator_direction_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
+ >;
+ };
+
+ vibrator_enable_pin: pinmux_vibrator_enable_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
+ >;
+ };
+};
+
+&omap4_pmx_wkup {
+ usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins {
+ /* gpio_wk0 */
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
+ >;
+ };
+};
+
+/* RNG is used by secure mode and not accessible */
+&rng_target {
+ status = "disabled";
+};
+
+/* Configure pwm clock source for timers 8 & 9 */
+&timer8 {
+ assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+};
+
+&timer9 {
+ assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+};
+
+/*
+ * The uart1 port is wired to mdm6600 with rts and cts. The modem uses gpio_149
+ * for wake-up events for both the USB PHY and the UART. We can use gpio_149
+ * pad as the shared wakeirq for the UART rather than the RX or CTS pad as we
+ * have gpio_149 trigger before the UART transfer starts.
+ */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0x110>;
+ uart-has-rtscts;
+ current-speed = <115200>;
+};
+
+&uart3 {
+ interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+ &omap4_pmx_core 0x17c>;
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+
+ bluetooth {
+ compatible = "ti,wl1285-st";
+ enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */
+ max-speed = <3686400>;
+ };
+};
+
+&usbhsohci {
+ phys = <&fsusb1_phy>;
+ phy-names = "usb";
+};
+
+&usbhsehci {
+ phys = <&hsusb2_phy>;
+};
+
+&usbhshost {
+ port1-mode = "ohci-phy-4pin-dpdm";
+ port2-mode = "ehci-tll";
+};
+
+/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */
+&usb_otg_hs {
+ interface-type = <1>;
+ mode = <3>;
+
+ /*
+ * Max 300 mA steps based on similar PMIC MC13783UG.pdf "Table 10-4.
+ * VBUS Regulator Main Characteristics". Binding uses 2 mA units.
+ */
+ power = <150>;
+};
+
+&i2c4 {
+ ak8975: magnetometer@c {
+ compatible = "asahi-kasei,ak8975";
+ reg = <0x0c>;
+
+ vdd-supply = <&vhvio>;
+
+ interrupt-parent = <&gpio6>;
+ interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */
+
+ rotation-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+
+ };
+
+ lis3dh: accelerometer@18 {
+ compatible = "st,lis3dh-accel";
+ reg = <0x18>;
+
+ vdd-supply = <&vhvio>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */
+
+ rotation-matrix = "0", "-1", "0",
+ "1", "0", "0",
+ "0", "0", "1";
+ };
+};
+
+&mcbsp2 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp2_pins>;
+ status = "okay";
+
+ mcbsp2_port: port {
+ cpu_dai2: endpoint {
+ dai-format = "i2s";
+ remote-endpoint = <&cpcap_audio_codec0>;
+ frame-master = <&cpcap_audio_codec0>;
+ bitclock-master = <&cpcap_audio_codec0>;
+ };
+ };
+};
+
+&mcbsp3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcbsp3_pins>;
+ status = "okay";
+
+ mcbsp3_port: port {
+ cpu_dai3: endpoint {
+ dai-format = "dsp_a";
+ frame-master = <&cpcap_audio_codec1>;
+ bitclock-master = <&cpcap_audio_codec1>;
+ remote-endpoint = <&cpcap_audio_codec1>;
+ };
+ };
+};
+
+&cpcap_audio_codec0 {
+ remote-endpoint = <&cpu_dai2>;
+};
+
+&cpcap_audio_codec1 {
+ remote-endpoint = <&cpu_dai3>;
+};
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index a5c91c2..005c275 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -11,7 +11,7 @@
model = "Phontech MPA 1600";
compatible = "phontech,mpa1600", "atmel,at91rm9200";
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi
index 96fb5a5..37f5023 100644
--- a/arch/arm/boot/dts/mps2.dtsi
+++ b/arch/arm/boot/dts/mps2.dtsi
@@ -161,9 +161,11 @@
};
timer2: dual-timer@2000 {
- compatible = "arm,sp804";
+ compatible = "arm,sp804", "arm,primecell";
reg = <0x2000 0x1000>;
- clocks = <&sysclk>;
+ clocks = <&sysclk>, <&sysclk>, <&sysclk>;
+ clock-names = "timer0clk", "timer1clk",
+ "apb_pclk";
interrupts = <10>;
status = "disabled";
};
@@ -197,8 +199,8 @@
arm,primecell-periphid = <0x00141805>;
reg = <0x8000 0x1000>;
interrupts = <0>;
- clocks = <&sysclk>;
- clock-names = "apb_pclk";
+ clocks = <&sysclk>, <&sysclk>;
+ clock-names = "wdog_clk", "apb_pclk";
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts
new file mode 100644
index 0000000..f9db2ff
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+/dts-v1/;
+#include "mstar-infinity-msc313.dtsi"
+
+/ {
+ model = "BreadBee Crust";
+ compatible = "thingyjp,breadbee-crust", "mstar,infinity";
+
+ aliases {
+ serial0 = &pm_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&pm_uart {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/mstar-infinity-msc313.dtsi b/arch/arm/boot/dts/mstar-infinity-msc313.dtsi
new file mode 100644
index 0000000..3499fde
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity-msc313.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-infinity.dtsi"
+
+/ {
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x4000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi
new file mode 100644
index 0000000..cd911ad
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-v7.dtsi"
+
+&imi {
+ reg = <0xa0000000 0x16000>;
+};
diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts
new file mode 100644
index 0000000..f0eda80
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+/dts-v1/;
+#include "mstar-infinity3-msc313e.dtsi"
+
+/ {
+ model = "BreadBee";
+ compatible = "thingyjp,breadbee", "mstar,infinity3";
+
+ aliases {
+ serial0 = &pm_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&pm_uart {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi b/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi
new file mode 100644
index 0000000..f581b6f
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-infinity3.dtsi"
+
+/ {
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x4000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mstar-infinity3.dtsi
new file mode 100644
index 0000000..9857e2a
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-infinity3.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-infinity.dtsi"
+
+&imi {
+ reg = <0xa0000000 0x20000>;
+};
diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts
new file mode 100644
index 0000000..7306b73
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+/dts-v1/;
+#include "mstar-mercury5-ssc8336n.dtsi"
+
+/ {
+ model = "70mai Midrive D08";
+ compatible = "70mai,midrived08", "mstar,mercury5";
+
+ aliases {
+ serial0 = &pm_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&pm_uart {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi
new file mode 100644
index 0000000..3f5a4c0
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-mercury5.dtsi"
+
+/ {
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x4000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi b/arch/arm/boot/dts/mstar-mercury5.dtsi
new file mode 100644
index 0000000..a7d0dd9
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-mercury5.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include "mstar-v7.dtsi"
+
+&imi {
+ reg = <0xa0000000 0x20000>;
+};
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
new file mode 100644
index 0000000..f078805
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ };
+ };
+
+ arch_timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
+ | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
+ | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
+ | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
+ | IRQ_TYPE_LEVEL_LOW)>;
+ /*
+ * we shouldn't need this but the vendor
+ * u-boot is broken
+ */
+ clock-frequency = <6000000>;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x16001000 0x16001000 0x00007000>,
+ <0x1f000000 0x1f000000 0x00400000>,
+ <0xa0000000 0xa0000000 0x20000>;
+
+ gic: interrupt-controller@16001000 {
+ compatible = "arm,cortex-a7-gic";
+ reg = <0x16001000 0x1000>,
+ <0x16002000 0x2000>,
+ <0x16004000 0x2000>,
+ <0x16006000 0x2000>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
+ | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ riu: bus@1f000000 {
+ compatible = "simple-bus";
+ reg = <0x1f000000 0x00400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1f000000 0x00400000>;
+
+ pmsleep: syscon@1c00 {
+ compatible = "mstar,msc313-pmsleep", "syscon";
+ reg = <0x1c00 0x100>;
+ };
+
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pmsleep>;
+ offset = <0xb8>;
+ mask = <0x79>;
+ };
+
+ intc_fiq: interrupt-controller@201310 {
+ compatible = "mstar,mst-intc";
+ reg = <0x201310 0x40>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ mstar,irqs-map-range = <96 127>;
+ };
+
+ intc_irq: interrupt-controller@201350 {
+ compatible = "mstar,mst-intc";
+ reg = <0x201350 0x40>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ mstar,irqs-map-range = <32 95>;
+ mstar,intc-no-eoi;
+ };
+
+ l3bridge: l3bridge@204400 {
+ compatible = "mstar,l3bridge";
+ reg = <0x204400 0x200>;
+ };
+
+ pm_uart: uart@221000 {
+ compatible = "ns16550a";
+ reg = <0x221000 0x100>;
+ reg-shift = <3>;
+ interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <172000000>;
+ status = "disabled";
+ };
+ };
+
+ imi: sram@a0000000 {
+ compatible = "mmio-sram";
+ reg = <0xa0000000 0x10000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index 88f8fd2..d1535f3 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -6,6 +6,7 @@
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "mt2701.dtsi"
/ {
@@ -61,6 +62,15 @@
>;
default-brightness-level = <9>;
};
+
+ usb_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 45 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&auxadc {
@@ -230,3 +240,14 @@
&uart0 {
status = "okay";
};
+
+&usb2 {
+ status = "okay";
+ usb-role-switch;
+ connector{
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
+ vbus-supply = <&usb_vbus>;
+ };
+};
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 51e1305..fade142 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -148,7 +148,7 @@
reg = <0 0x10005000 0 0x1000>;
};
- scpsys: scpsys@10006000 {
+ scpsys: power-controller@10006000 {
compatible = "mediatek,mt2701-scpsys", "syscon";
#power-domain-cells = <1>;
reg = <0 0x10006000 0 0x1000>;
@@ -569,6 +569,19 @@
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
+ jpegenc: jpegenc@1500a000 {
+ compatible = "mediatek,mt2701-jpgenc",
+ "mediatek,mtk-jpgenc";
+ reg = <0 0x1500a000 0 0x1000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&imgsys CLK_IMG_VENC>;
+ clock-names = "jpgenc";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ mediatek,larb = <&larb2>;
+ iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
+ <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
+ };
+
vdecsys: syscon@16000000 {
compatible = "mediatek,mt2701-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
@@ -671,6 +684,39 @@
};
};
+ usb2: usb@11200000 {
+ compatible = "mediatek,mt2701-musb",
+ "mediatek,mtk-musb";
+ reg = <0 0x11200000 0 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "mc";
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ dr_mode = "otg";
+ clocks = <&pericfg CLK_PERI_USB0>,
+ <&pericfg CLK_PERI_USB0_MCU>,
+ <&pericfg CLK_PERI_USB_SLV>;
+ clock-names = "main","mcu","univpll";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ status = "disabled";
+ };
+
+ u2phy0: usb-phy@11210000 {
+ compatible = "mediatek,generic-tphy-v1";
+ reg = <0 0x11210000 0 0x0800>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ u2port2: usb-phy@1a1c4800 {
+ reg = <0 0x11210800 0 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
ethsys: syscon@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
diff --git a/arch/arm/boot/dts/mt6323.dtsi b/arch/arm/boot/dts/mt6323.dtsi
index ba39740..7fda40a 100644
--- a/arch/arm/boot/dts/mt6323.dtsi
+++ b/arch/arm/boot/dts/mt6323.dtsi
@@ -238,5 +238,32 @@
regulator-enable-ramp-delay = <216>;
};
};
+
+ mt6323keys: mt6323keys {
+ compatible = "mediatek,mt6323-keys";
+ mediatek,long-press-mode = <1>;
+ power-off-time-sec = <0>;
+
+ power {
+ linux,keycodes = <116>;
+ wakeup-source;
+ };
+
+ home {
+ linux,keycodes = <114>;
+ };
+ };
+
+ codec: mt6397codec {
+ compatible = "mediatek,mt6397-codec";
+ };
+
+ power-controller {
+ compatible = "mediatek,mt6323-pwrc";
+ };
+
+ rtc {
+ compatible = "mediatek,mt6323-rtc";
+ };
};
};
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index a79f0b6..aea6809 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2017-2018 MediaTek Inc.
* Author: John Crispin <john@phrozen.org>
* Sean Wang <sean.wang@mediatek.com>
+ * Ryder Lee <ryder.lee@mediatek.com>
*
*/
@@ -13,7 +14,6 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include <dt-bindings/thermal/thermal.h>
@@ -268,7 +268,7 @@
reg = <0 0x10005000 0 0x1000>;
};
- scpsys: scpsys@10006000 {
+ scpsys: power-controller@10006000 {
compatible = "mediatek,mt7623-scpsys",
"mediatek,mt2701-scpsys",
"syscon";
@@ -296,17 +296,6 @@
clock-names = "system-clk", "rtc-clk";
};
- smi_common: smi@1000c000 {
- compatible = "mediatek,mt7623-smi-common",
- "mediatek,mt2701-smi-common";
- reg = <0 0x1000c000 0 0x1000>;
- clocks = <&infracfg CLK_INFRA_SMI>,
- <&mmsys CLK_MM_SMI_COMMON>,
- <&infracfg CLK_INFRA_SMI>;
- clock-names = "apb", "smi", "async";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
- };
-
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt7623-pwrap",
"mediatek,mt2701-pwrap";
@@ -338,17 +327,6 @@
reg = <0 0x10200100 0 0x1c>;
};
- iommu: mmsys_iommu@10205000 {
- compatible = "mediatek,mt7623-m4u",
- "mediatek,mt2701-m4u";
- reg = <0 0x10205000 0 0x1000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_M4U>;
- clock-names = "bclk";
- mediatek,larbs = <&larb0 &larb1 &larb2>;
- #iommu-cells = <1>;
- };
-
efuse: efuse@10206000 {
compatible = "mediatek,mt7623-efuse",
"mediatek,mt8173-efuse";
@@ -724,70 +702,6 @@
status = "disabled";
};
- g3dsys: syscon@13000000 {
- compatible = "mediatek,mt7623-g3dsys",
- "mediatek,mt2701-g3dsys",
- "syscon";
- reg = <0 0x13000000 0 0x200>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- mmsys: syscon@14000000 {
- compatible = "mediatek,mt7623-mmsys",
- "mediatek,mt2701-mmsys",
- "syscon";
- reg = <0 0x14000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- larb0: larb@14010000 {
- compatible = "mediatek,mt7623-smi-larb",
- "mediatek,mt2701-smi-larb";
- reg = <0 0x14010000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- mediatek,larb-id = <0>;
- clocks = <&mmsys CLK_MM_SMI_LARB0>,
- <&mmsys CLK_MM_SMI_LARB0>;
- clock-names = "apb", "smi";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
- };
-
- imgsys: syscon@15000000 {
- compatible = "mediatek,mt7623-imgsys",
- "mediatek,mt2701-imgsys",
- "syscon";
- reg = <0 0x15000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- larb2: larb@15001000 {
- compatible = "mediatek,mt7623-smi-larb",
- "mediatek,mt2701-smi-larb";
- reg = <0 0x15001000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- mediatek,larb-id = <2>;
- clocks = <&imgsys CLK_IMG_SMI_COMM>,
- <&imgsys CLK_IMG_SMI_COMM>;
- clock-names = "apb", "smi";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- };
-
- jpegdec: jpegdec@15004000 {
- compatible = "mediatek,mt7623-jpgdec",
- "mediatek,mt2701-jpgdec";
- reg = <0 0x15004000 0 0x1000>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
- <&imgsys CLK_IMG_JPGDEC>;
- clock-names = "jpgdec-smi",
- "jpgdec";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
- mediatek,larb = <&larb2>;
- iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
- <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
- };
-
vdecsys: syscon@16000000 {
compatible = "mediatek,mt7623-vdecsys",
"mediatek,mt2701-vdecsys",
@@ -796,18 +710,6 @@
#clock-cells = <1>;
};
- larb1: larb@16010000 {
- compatible = "mediatek,mt7623-smi-larb",
- "mediatek,mt2701-smi-larb";
- reg = <0 0x16010000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- mediatek,larb-id = <1>;
- clocks = <&vdecsys CLK_VDEC_CKGEN>,
- <&vdecsys CLK_VDEC_LARB>;
- clock-names = "apb", "smi";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
- };
-
hifsys: syscon@1a000000 {
compatible = "mediatek,mt7623-hifsys",
"mediatek,mt2701-hifsys",
diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
index 5375c66..e96aa0e 100644
--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -6,7 +6,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
-#include "mt7623.dtsi"
+#include "mt7623n.dtsi"
#include "mt6323.dtsi"
/ {
@@ -21,6 +21,19 @@
stdout-path = "serial2:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "d";
+ ddc-i2c-bus = <&hdmiddc0>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi0_out>;
+ };
+ };
+ };
+
cpus {
cpu@0 {
proc-supply = <&mt6323_vproc_reg>;
@@ -66,6 +79,13 @@
regulator-always-on;
};
+ reg_vgpu: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_fixed_vgpu";
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -114,10 +134,18 @@
};
};
+&bls {
+ status = "okay";
+};
+
&btif {
status = "okay";
};
+&cec {
+ status = "okay";
+};
+
&cir {
pinctrl-names = "default";
pinctrl-0 = <&cir_pins_a>;
@@ -128,6 +156,21 @@
status = "okay";
};
+&dpi0 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dpi0_out: endpoint {
+ remote-endpoint = <&hdmi0_in>;
+ };
+ };
+ };
+};
+
ð {
status = "okay";
@@ -200,6 +243,42 @@
};
};
+&hdmi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins_a>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmiddc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_ddc_pins_a>;
+ status = "okay";
+};
+
+&hdmi_phy {
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
@@ -212,6 +291,11 @@
status = "okay";
};
+&mali {
+ mali-supply = <®_vgpu>;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
@@ -331,4 +415,3 @@
&u3phy2 {
status = "okay";
};
-
diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
index 0447748..1b9b9a8 100644
--- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
+++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts
@@ -7,7 +7,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
-#include "mt7623.dtsi"
+#include "mt7623n.dtsi"
#include "mt6323.dtsi"
/ {
@@ -24,6 +24,19 @@
stdout-path = "serial2:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "d";
+ ddc-i2c-bus = <&hdmiddc0>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi0_out>;
+ };
+ };
+ };
+
cpus {
cpu@0 {
proc-supply = <&mt6323_vproc_reg>;
@@ -106,10 +119,18 @@
};
};
+&bls {
+ status = "okay";
+};
+
&btif {
status = "okay";
};
+&cec {
+ status = "okay";
+};
+
&cir {
pinctrl-names = "default";
pinctrl-0 = <&cir_pins_a>;
@@ -120,6 +141,21 @@
status = "okay";
};
+&dpi0 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dpi0_out: endpoint {
+ remote-endpoint = <&hdmi0_in>;
+ };
+ };
+ };
+};
+
ð {
status = "okay";
@@ -203,6 +239,42 @@
};
};
+&hdmi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins_a>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+};
+
+&hdmiddc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_ddc_pins_a>;
+ status = "okay";
+};
+
+&hdmi_phy {
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ status = "okay";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi
new file mode 100644
index 0000000..1880ac9
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623n.dtsi
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2017-2020 MediaTek Inc.
+ * Author: Sean Wang <sean.wang@mediatek.com>
+ * Ryder Lee <ryder.lee@mediatek.com>
+ *
+ */
+
+#include "mt7623.dtsi"
+#include <dt-bindings/memory/mt2701-larb-port.h>
+
+/ {
+ aliases {
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ };
+
+ g3dsys: syscon@13000000 {
+ compatible = "mediatek,mt7623-g3dsys",
+ "mediatek,mt2701-g3dsys",
+ "syscon";
+ reg = <0 0x13000000 0 0x200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mali: gpu@13040000 {
+ compatible = "mediatek,mt7623-mali", "arm,mali-450";
+ reg = <0 0x13040000 0 0x30000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
+ "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
+ "pp";
+ clocks = <&topckgen CLK_TOP_MMPLL>,
+ <&g3dsys CLK_G3DSYS_CORE>;
+ clock-names = "bus", "core";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
+ resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt7623-mmsys",
+ "mediatek,mt2701-mmsys",
+ "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ larb0: larb@14010000 {
+ compatible = "mediatek,mt7623-smi-larb",
+ "mediatek,mt2701-smi-larb";
+ reg = <0 0x14010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <0>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
+ larb1: larb@16010000 {
+ compatible = "mediatek,mt7623-smi-larb",
+ "mediatek,mt2701-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <1>;
+ clocks = <&vdecsys CLK_VDEC_CKGEN>,
+ <&vdecsys CLK_VDEC_LARB>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+ };
+
+ larb2: larb@15001000 {
+ compatible = "mediatek,mt7623-smi-larb",
+ "mediatek,mt2701-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <2>;
+ clocks = <&imgsys CLK_IMG_SMI_COMM>,
+ <&imgsys CLK_IMG_SMI_COMM>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ };
+
+ imgsys: syscon@15000000 {
+ compatible = "mediatek,mt7623-imgsys",
+ "mediatek,mt2701-imgsys",
+ "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ iommu: mmsys_iommu@10205000 {
+ compatible = "mediatek,mt7623-m4u",
+ "mediatek,mt2701-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ mediatek,larbs = <&larb0 &larb1 &larb2>;
+ #iommu-cells = <1>;
+ };
+
+ jpegdec: jpegdec@15004000 {
+ compatible = "mediatek,mt7623-jpgdec",
+ "mediatek,mt2701-jpgdec";
+ reg = <0 0x15004000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
+ <&imgsys CLK_IMG_JPGDEC>;
+ clock-names = "jpgdec-smi",
+ "jpgdec";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ mediatek,larb = <&larb2>;
+ iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
+ <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
+ };
+
+ smi_common: smi@1000c000 {
+ compatible = "mediatek,mt7623-smi-common",
+ "mediatek,mt2701-smi-common";
+ reg = <0 0x1000c000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_SMI>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&infracfg CLK_INFRA_SMI>;
+ clock-names = "apb", "smi", "async";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
+ ovl: ovl@14007000 {
+ compatible = "mediatek,mt7623-disp-ovl",
+ "mediatek,mt2701-disp-ovl";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DISP_OVL>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma0: rdma@14008000 {
+ compatible = "mediatek,mt7623-disp-rdma",
+ "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
+ mediatek,larb = <&larb0>;
+ };
+
+ wdma@14009000 {
+ compatible = "mediatek,mt7623-disp-wdma",
+ "mediatek,mt2701-disp-wdma";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
+ mediatek,larb = <&larb0>;
+ };
+
+ bls: pwm@1400a000 {
+ compatible = "mediatek,mt7623-disp-pwm",
+ "mediatek,mt2701-disp-pwm";
+ reg = <0 0x1400a000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
+ <&mmsys CLK_MM_DISP_BLS>;
+ clock-names = "main", "mm";
+ status = "disabled";
+ };
+
+ color: color@1400b000 {
+ compatible = "mediatek,mt7623-disp-color",
+ "mediatek,mt2701-disp-color";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR>;
+ };
+
+ dsi: dsi@1400c000 {
+ compatible = "mediatek,mt7623-dsi",
+ "mediatek,mt2701-dsi";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DSI_ENGINE>,
+ <&mmsys CLK_MM_DSI_DIG>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
+ mutex: mutex@1400e000 {
+ compatible = "mediatek,mt7623-disp-mutex",
+ "mediatek,mt2701-disp-mutex";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ };
+
+ rdma1: rdma@14012000 {
+ compatible = "mediatek,mt7623-disp-rdma",
+ "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb0>;
+ };
+
+ dpi0: dpi@14014000 {
+ compatible = "mediatek,mt7623-dpi",
+ "mediatek,mt2701-dpi";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DPI1_DIGL>,
+ <&mmsys CLK_MM_DPI1_ENGINE>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ status = "disabled";
+ };
+
+ hdmi0: hdmi@14015000 {
+ compatible = "mediatek,mt7623-hdmi",
+ "mediatek,mt2701-hdmi";
+ reg = <0 0x14015000 0 0x400>;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+ <&mmsys CLK_MM_HDMI_PLL>,
+ <&mmsys CLK_MM_HDMI_AUDIO>,
+ <&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+ cec = <&cec>;
+ status = "disabled";
+ };
+
+ mipi_tx0: mipi-dphy@10010000 {
+ compatible = "mediatek,mt7623-mipi-tx",
+ "mediatek,mt2701-mipi-tx";
+ reg = <0 0x10010000 0 0x90>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
+ cec: cec@10012000 {
+ compatible = "mediatek,mt7623-cec",
+ "mediatek,mt8173-cec";
+ reg = <0 0x10012000 0 0xbc>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+ status = "disabled";
+ };
+
+ hdmi_phy: phy@10209100 {
+ compatible = "mediatek,mt7623-hdmi-phy",
+ "mediatek,mt2701-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ clock-output-names = "hdmitx_dig_cts";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ hdmiddc0: i2c@11013000 {
+ compatible = "mediatek,mt7623-hdmi-ddc",
+ "mediatek,mt8173-hdmi-ddc";
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+ reg = <0 0x11013000 0 0x1C>;
+ clocks = <&pericfg CLK_PERI_I2C3>;
+ clock-names = "ddc-i2c";
+ status = "disabled";
+ };
+};
+
+&pio {
+ hdmi_pins_a: hdmi-default {
+ pins-hdmi {
+ pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ hdmi_ddc_pins_a: hdmi_ddc-default {
+ pins-hdmi-ddc {
+ pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>,
+ <MT7623_PIN_125_GPIO125_FUNC_HDMISD>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
index 867b881..5cbb3d2 100644
--- a/arch/arm/boot/dts/mt7629.dtsi
+++ b/arch/arm/boot/dts/mt7629.dtsi
@@ -90,7 +90,7 @@
#clock-cells = <1>;
};
- scpsys: scpsys@10006000 {
+ scpsys: power-controller@10006000 {
compatible = "mediatek,mt7629-scpsys",
"mediatek,mt7622-scpsys";
#power-domain-cells = <1>;
@@ -241,6 +241,20 @@
status = "disabled";
};
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt7629-pwm";
+ reg = <0x11006000 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&pericfg CLK_PERI_PWM_PD>,
+ <&pericfg CLK_PERI_PWM1_PD>;
+ clock-names = "top", "main", "pwm1";
+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
+ assigned-clock-parents =
+ <&topckgen CLK_TOP_UNIVPLL2_D4>;
+ status = "disabled";
+ };
+
i2c: i2c@11007000 {
compatible = "mediatek,mt7629-i2c",
"mediatek,mt2712-i2c";
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
index d9a0fd7..90e033d 100644
--- a/arch/arm/boot/dts/nspire.dtsi
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -145,15 +145,19 @@
timer0: timer@900C0000 {
reg = <0x900C0000 0x1000>;
-
- clocks = <&timer_clk>;
+ clocks = <&timer_clk>, <&timer_clk>,
+ <&timer_clk>;
+ clock-names = "timer0clk", "timer1clk",
+ "apb_pclk";
};
timer1: timer@900D0000 {
reg = <0x900D0000 0x1000>;
interrupts = <19>;
-
- clocks = <&timer_clk>;
+ clocks = <&timer_clk>, <&timer_clk>,
+ <&timer_clk>;
+ clock-names = "timer0clk", "timer1clk",
+ "apb_pclk";
};
watchdog: watchdog@90060000 {
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
index 7f6aefd..e7534fe 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
@@ -29,7 +29,7 @@
compatible = "smsc,lan9221","smsc,lan9115";
bank-width = <2>;
- gpmc,mux-add-data;
+ gpmc,mux-add-data = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <42>;
gpmc,cs-wr-off-ns = <36>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 000bf16..f9c2a99 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -1,13 +1,14 @@
/*
* Device Tree Source for OMAP2 SoC
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
+#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/omap.h>
@@ -79,17 +80,37 @@
reg = <0x480FE000 0x1000>;
};
- sdma: dma-controller@48056000 {
- compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
- ti,hwmods = "dma";
- reg = <0x48056000 0x1000>;
- interrupts = <12>,
- <13>,
- <14>,
- <15>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <64>;
+ target-module@48056000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x48056000 0x4>,
+ <0x4805602c 0x4>,
+ <0x48056028 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&core_l3_ck>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x48056000 0x1000>;
+
+ sdma: dma-controller@0 {
+ compatible = "ti,omap2420-sdma", "ti,omap-sdma";
+ reg = <0 0x1000>;
+ interrupts = <12>,
+ <13>,
+ <14>,
+ <15>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <64>;
+ };
};
i2c1: i2c@48070000 {
@@ -180,11 +201,32 @@
clock-frequency = <48000000>;
};
- timer2: timer@4802a000 {
- compatible = "ti,omap2420-timer";
- reg = <0x4802a000 0x400>;
- interrupts = <38>;
- ti,hwmods = "timer2";
+ timer2_target: target-module@4802a000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x4802a000 0x4>,
+ <0x4802a010 0x4>,
+ <0x4802a014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt2_fck>, <&gpt2_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4802a000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,omap2420-timer";
+ reg = <0 0x400>;
+ interrupts = <38>;
+ };
};
timer3: timer@48078000 {
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 7d66027..af964f1 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index aba542d..494bf69 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP2420 SoC
*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -68,10 +68,23 @@
};
};
- counter32k: counter@4000 {
- compatible = "ti,omap-counter32k";
- reg = <0x4000 0x20>;
- ti,hwmods = "counter_32k";
+ target-module@4000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ clocks = <&func_32k_ck>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,omap-counter32k";
+ reg = <0 0x20>;
+ };
};
};
@@ -194,12 +207,33 @@
};
};
- timer1: timer@48028000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48028000 0x400>;
- interrupts = <37>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
+ timer1_target: target-module@48028000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x48028000 0x4>,
+ <0x48028010 0x4>,
+ <0x48028014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt1_fck>, <&gpt1_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48028000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,omap2420-timer";
+ reg = <0 0x400>;
+ interrupts = <37>;
+ ti,timer-alwon;
+ };
};
wd_timer2: wdt@48022000 {
@@ -218,5 +252,15 @@
compatible = "ti,omap2420-i2c";
};
-/include/ "omap24xx-clocks.dtsi"
-/include/ "omap2420-clocks.dtsi"
+#include "omap24xx-clocks.dtsi"
+#include "omap2420-clocks.dtsi"
+
+/* Preferred always-on timer for clockevent */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt1_fck>;
+ assigned-clock-parents = <&func_32k_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts
index f7e3248..7d27e90 100644
--- a/arch/arm/boot/dts/omap2430-sdp.dts
+++ b/arch/arm/boot/dts/omap2430-sdp.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 7f57af2..d19d8ba 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP243x SoC
*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -81,10 +81,23 @@
};
};
- counter32k: counter@20000 {
- compatible = "ti,omap-counter32k";
- reg = <0x20000 0x20>;
- ti,hwmods = "counter_32k";
+ target-module@20000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x20000 0x4>,
+ <0x20004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ clocks = <&func_32k_ck>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,omap-counter32k";
+ reg = <0 0x20>;
+ };
};
};
@@ -277,12 +290,33 @@
};
};
- timer1: timer@49018000 {
- compatible = "ti,omap2420-timer";
- reg = <0x49018000 0x400>;
- interrupts = <37>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
+ timer1_target: target-module@49018000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x49018000 0x4>,
+ <0x49018010 0x4>,
+ <0x49018014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt1_fck>, <&gpt1_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49018000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,omap2420-timer";
+ reg = <0 0x400>;
+ interrupts = <37>;
+ ti,timer-alwon;
+ };
};
mcspi3: spi@480b8000 {
@@ -309,6 +343,10 @@
};
};
+&sdma {
+ compatible = "ti,omap2430-sdma", "ti,omap-sdma";
+};
+
&i2c1 {
compatible = "ti,omap2430-i2c";
};
@@ -317,5 +355,15 @@
compatible = "ti,omap2430-i2c";
};
-/include/ "omap24xx-clocks.dtsi"
-/include/ "omap2430-clocks.dtsi"
+#include "omap24xx-clocks.dtsi"
+#include "omap2430-clocks.dtsi"
+
+/* Preferred always-on timer for clockevent */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt1_fck>;
+ assigned-clock-parents = <&func_32k_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle-ab4.dts b/arch/arm/boot/dts/omap3-beagle-ab4.dts
new file mode 100644
index 0000000..990ff2d
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-beagle-ab4.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "omap3-beagle.dts"
+
+/ {
+ model = "TI OMAP3 BeagleBoard A to B4";
+ compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
+};
+
+/*
+ * Workaround for capacitor C70 issue, see "Boards revision A and < B5"
+ * section at https://elinux.org/BeagleBoard_Community
+ */
+
+/* Unusable as clocksource because of unreliable oscillator */
+&counter32k {
+ status = "disabled";
+};
+
+/* Unusable as clockevent because of unreliable oscillator, allow to idle */
+&timer1_target {
+ /delete-property/ti,no-reset-on-init;
+ /delete-property/ti,no-idle;
+ timer@0 {
+ /delete-property/ti,timer-alwon;
+ };
+};
+
+/* Preferred always-on timer for clocksource */
+&timer12_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ /* Always clocked by secure_32k_fck */
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt2_fck>;
+ assigned-clock-parents = <&sys_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle-xm-ab.dts b/arch/arm/boot/dts/omap3-beagle-xm-ab.dts
index e498495..cb6968a 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm-ab.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm-ab.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap3-beagle-xm.dts"
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 1aa99fc..252507c 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 BeagleBoard xM";
- compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
@@ -389,7 +389,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <
@@ -406,7 +406,7 @@
};
&venc {
- status = "ok";
+ status = "okay";
vdda-supply = <&vdac>;
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index e3df3c1..0548b39 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 BeagleBoard";
- compatible = "ti,omap3-beagle", "ti,omap3";
+ compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
cpus {
cpu@0 {
@@ -353,7 +353,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
@@ -367,7 +367,7 @@
};
&venc {
- status = "ok";
+ status = "okay";
vdda-supply = <&vdac>;
@@ -380,7 +380,7 @@
};
&gpmc {
- status = "ok";
+ status = "okay";
ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */
/* Chip select 0 */
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
index 632f52e..3b83490 100644
--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -147,7 +147,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <
diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts
index 76e52c7..bc545ee 100644
--- a/arch/arm/boot/dts/omap3-cm-t3530.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3530.dts
@@ -9,7 +9,7 @@
/ {
model = "CompuLab CM-T3530";
- compatible = "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
+ compatible = "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
/* Regulator to trigger the reset signal of the Wifi module */
mmc2_sdio_reset: regulator-mmc2-sdio-reset {
@@ -49,7 +49,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index 6e944df..48e48b0 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -9,7 +9,7 @@
/ {
model = "CompuLab CM-T3730";
- compatible = "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
+ compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3";
wl12xx_vmmc2: wl12xx_vmmc2 {
compatible = "regulator-fixed";
@@ -87,7 +87,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index cdb632d..e61b8a2 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -246,7 +246,7 @@
};
&venc {
- status = "ok";
+ status = "okay";
port {
venc_out: endpoint {
@@ -257,7 +257,7 @@
};
&mcbsp2 {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
index 235ecfd..1ed8378 100644
--- a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP3 SoC CPU thermal
*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -17,4 +17,25 @@
/* sensor ID */
thermal-sensors = <&bandgap 0>;
+
+ cpu_trips: trips {
+ cpu_alert0: cpu_alert {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cpu_cooling_maps: cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
index ac3d996..6883ccb 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
+++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
@@ -158,6 +158,24 @@
status = "disabled";
};
+/* Unusable as clockevent because if unreliable oscillator, allow to idle */
+&timer1_target {
+ /delete-property/ti,no-reset-on-init;
+ /delete-property/ti,no-idle;
+ timer@0 {
+ /delete-property/ti,timer-alwon;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer12_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ /* Always clocked by secure_32k_fck */
+ };
+};
+
&twl_gpio {
ti,use-leds;
/*
@@ -337,7 +355,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
@@ -361,7 +379,7 @@
};
&venc {
- status = "ok";
+ status = "okay";
vdda-supply = <&vdac>;
diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts
index a80fc60..afed850 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts
@@ -11,7 +11,7 @@
#include "omap3-devkit8000-lcd-common.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel";
- compatible = "timll,omap3-devkit8000", "ti,omap3";
+ compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
lcd0: display {
panel-timing {
diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts
index 0753776..07c51a1 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts
@@ -11,7 +11,7 @@
#include "omap3-devkit8000-lcd-common.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel";
- compatible = "timll,omap3-devkit8000", "ti,omap3";
+ compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
lcd0: display {
panel-timing {
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index faafc48..162d072 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
#include "omap3-devkit8000-common.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000";
- compatible = "timll,omap3-devkit8000", "ti,omap3";
+ compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
aliases {
display1 = &dvi0;
diff --git a/arch/arm/boot/dts/omap3-echo.dts b/arch/arm/boot/dts/omap3-echo.dts
new file mode 100644
index 0000000..93ffedd
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-echo.dts
@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2019 André Hentschel <nerv@dawncrow.de>
+ */
+/dts-v1/;
+
+#include "dm3725.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Amazon Echo (first generation)";
+ compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0xc600000>; /* 198 MB */
+ };
+
+ vcc5v: fixedregulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc3v3: fixedregulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc1v8: fixedregulator2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <40>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&button_pins>;
+
+ mute-button {
+ label = "mute";
+ linux,code = <KEY_MUTE>;
+ gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; /* GPIO_70 */
+ wakeup-source;
+ };
+
+ help-button {
+ label = "help";
+ linux,code = <KEY_HELP>;
+ gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; /* GPIO_72 */
+ wakeup-source;
+ };
+ };
+
+ rotary: rotary-encoder {
+ compatible = "rotary-encoder";
+ gpios = <
+ &gpio3 5 GPIO_ACTIVE_HIGH /* GPIO_69 */
+ &gpio3 12 GPIO_ACTIVE_HIGH /* GPIO_76 */
+ >;
+ linux,axis = <REL_X>;
+ rotary-encoder,relative-axis;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+
+ tps: tps@2d {
+ reg = <0x2d>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+
+ lp5523A: lp5523A@32 {
+ compatible = "national,lp5523";
+ label = "q1";
+ reg = <0x32>;
+ clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
+ enable-gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */
+
+ chan0 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan1 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan2 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan3 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan4 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan5 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan6 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan7 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan8 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ };
+
+ lp5523B: lp5523B@33 {
+ compatible = "national,lp5523";
+ label = "q3";
+ reg = <0x33>;
+ clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
+
+ chan0 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan1 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan2 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan3 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan4 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan5 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan6 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan7 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan8 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ };
+
+ lp5523C: lp5523C@34 {
+ compatible = "national,lp5523";
+ label = "q4";
+ reg = <0x34>;
+ clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
+
+ chan0 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan1 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan2 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan3 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan4 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan5 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan6 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan7 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan8 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ };
+
+ lp5523D: lp552D@35 {
+ compatible = "national,lp5523";
+ label = "q2";
+ reg = <0x35>;
+ clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
+
+ chan0 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan1 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan2 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan3 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan4 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan5 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan6 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan7 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ chan8 {
+ led-cur = /bits/ 8 <12>;
+ max-cur = /bits/ 8 <15>;
+ };
+ };
+};
+
+#include "tps65910.dtsi"
+
+&omap3_pmx_core {
+ tps_pins: pinmux_tps_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_INPUT_PULLUP | PIN_OFF_OUTPUT_LOW | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */
+ >;
+ };
+
+ button_pins: pinmux_button_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x20dc, PIN_INPUT | MUX_MODE4) /* dss_data0.gpio_70 */
+ OMAP3_CORE1_IOPAD(0x20e0, PIN_INPUT | MUX_MODE4) /* dss_data2.gpio_72 */
+ >;
+ };
+
+ mmc1_pins: pinmux_mmc1_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
+ OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
+ OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
+ OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
+ OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
+ OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
+ >;
+ };
+
+ mmc2_pins: pinmux_mmc2_pins {
+ pinctrl-single,pins = <
+ OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
+ OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
+ OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
+ OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
+ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
+ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
+ OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4.sdmmc2_dat4 */
+ OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5.sdmmc2_dat5 */
+ OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6.sdmmc2_dat6 */
+ OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7.sdmmc2_dat7 */
+ >;
+ };
+};
+
+&omap3_pmx_core2 {
+ mmc3_pins: pinmux_mmc3_pins {
+ pinctrl-single,pins = <
+ OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
+ OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_ctl.sdmmc3_cmd */
+ OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */
+ OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */
+ OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
+ OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */
+ >;
+ };
+};
+
+&mmc1 {
+ status = "okay";
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&vmmc_reg>;
+};
+
+&mmc2 {
+ status = "okay";
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&vmmc_reg>;
+};
+
+&mmc3 {
+ status = "okay";
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins>;
+ non-removable;
+ disable-wp;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vmmc-supply = <&vcc3v3>;
+ vqmmc-supply = <&vcc1v8>;
+};
+
+&tps {
+ pinctrl-names = "default";
+ pinctrl-0 = <&tps_pins>;
+
+ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+ interrupt-parent = <&intc>;
+
+ ti,en-ck32k-xtal;
+ ti,system-power-controller;
+
+ vcc1-supply = <&vcc5v>;
+ vcc2-supply = <&vcc5v>;
+ vcc3-supply = <&vcc5v>;
+ vcc4-supply = <&vcc5v>;
+ vcc5-supply = <&vcc5v>;
+ vcc6-supply = <&vcc5v>;
+ vcc7-supply = <&vcc5v>;
+ vccio-supply = <&vcc5v>;
+
+ regulators {
+
+ vio_reg: regulator@1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ regulator-name = "vdd_dsp";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-always-on;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index e0c0382..c933219 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 6a94815..5cc0cf7 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index b6ef1a7..80c9e5e 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -11,7 +11,7 @@
/ {
model = "OMAP3 GTA04";
- compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
@@ -114,7 +114,7 @@
gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio1 18 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 20 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
/* lcd panel */
@@ -124,7 +124,6 @@
spi-max-frequency = <100000>;
spi-cpol;
spi-cpha;
- spi-cs-high;
backlight= <&backlight>;
label = "lcd";
@@ -150,6 +149,7 @@
compatible = "ti,omap-dmtimer-pwm";
ti,timers = <&timer11>;
#pwm-cells = <3>;
+ ti,clock-source = <0x01>;
};
hsusb2_phy: hsusb2_phy {
@@ -515,7 +515,7 @@
compatible = "bosch,bma180";
reg = <0x41>;
pinctrl-names = "default";
- pintcrl-0 = <&bma180_pins>;
+ pinctrl-0 = <&bma180_pins>;
interrupt-parent = <&gpio4>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */
};
@@ -821,27 +821,27 @@
};
&mcbsp1 { /* FM Transceiver PCM */
- status = "ok";
+ status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
};
&mcbsp2 { /* TPS65950 I2S */
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
};
&mcbsp3 { /* Bluetooth PCM */
- status = "ok";
+ status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp3_pins>;
};
&mcbsp4 { /* GSM voice PCM */
- status = "ok";
+ status = "okay";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp4_pins>;
diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/omap3-ha-common.dtsi
index 3313285..a010585 100644
--- a/arch/arm/boot/dts/omap3-ha-common.dtsi
+++ b/arch/arm/boot/dts/omap3-ha-common.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*/
diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts
index badb9b3..643283f 100644
--- a/arch/arm/boot/dts/omap3-ha-lcd.dts
+++ b/arch/arm/boot/dts/omap3-ha-lcd.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*/
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM";
- compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+ compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
};
&omap3_pmx_core {
@@ -100,7 +100,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/omap3-ha.dts
index a536525..19e471e 100644
--- a/arch/arm/boot/dts/omap3-ha.dts
+++ b/arch/arm/boot/dts/omap3-ha.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*/
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM";
- compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+ compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
};
&omap3_pmx_core {
diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
index 91caa50..af8aa5f 100644
--- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi
+++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
@@ -245,7 +245,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
port {
dpi_out: endpoint {
diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
index 03dcd05..5672325 100644
--- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
+++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap36xx", "ti,omap3";
/* Regulator to trigger the WL_EN signal of the Wifi module */
lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
@@ -49,3 +49,11 @@
interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* gpio 177 */
};
};
+
+&uart2 {
+ bluetooth {
+ compatible = "ti,wl1835-st";
+ enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */
+ max-speed = <300000>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index 6d0519e..e341535 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap36xx", "ti,omap3";
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
index 060acd1..df6ba12 100644
--- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
+++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap36xx", "ti,omap3";
/* Regulator to trigger the WL_EN signal of the Wifi module */
lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
@@ -71,3 +71,11 @@
interrupts = <8 IRQ_TYPE_EDGE_RISING>; /* gpio 136 */
};
};
+
+&uart2 {
+ bluetooth {
+ compatible = "ti,wl1835-st";
+ enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* gpio 137 */
+ max-speed = <300000>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 25170bd..32f3103 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -10,7 +10,7 @@
/ {
model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap36xx", "ti,omap3";
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index 9a5fde2..9c6a927 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -10,7 +10,7 @@
/ {
model = "TI OMAP3430 LDP (Zoom1 Labrador)";
- compatible = "ti,omap3-ldp", "ti,omap3";
+ compatible = "ti,omap3-ldp", "ti,omap3430", "ti,omap3";
memory@80000000 {
device_type = "memory";
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index c22833d..73d4778 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -7,7 +7,7 @@
/ {
model = "INCOstartec LILLY-A83X module (DM3730)";
- compatible = "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+ compatible = "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3";
chosen {
bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
index fec3354..ecb4ef7 100644
--- a/arch/arm/boot/dts/omap3-lilly-dbb056.dts
+++ b/arch/arm/boot/dts/omap3-lilly-dbb056.dts
@@ -8,7 +8,7 @@
/ {
model = "INCOstartec LILLY-DBB056 (DM3730)";
- compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap36xx", "ti,omap3";
+ compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&twl {
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index 74c0ff2..d211bcc 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -12,7 +12,7 @@
/ {
model = "Nokia N9";
- compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3";
+ compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&i2c2 {
@@ -23,7 +23,6 @@
vana-supply = <&vaux3>;
clocks = <&isp 0>;
clock-frequency = <9600000>;
- nokia,nvm-size = <(16 * 64)>;
flash-leds = <&as3645a_flash &as3645a_indicator>;
port {
smia_1_1: endpoint {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 4227da7..d40c3d2 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -8,6 +8,7 @@
#include "omap34xx.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/*
* Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
@@ -19,7 +20,11 @@
* but it is not widely used and to prevent kernel crash rather AES is disabled.
* There is also no runtime detection code if AES is disabled in L3 firewall...
*/
-&aes {
+&aes1_target {
+ status = "disabled";
+};
+
+&aes2_target {
status = "disabled";
};
@@ -490,6 +495,11 @@
regulator-always-on;
};
+/* First two dma channels are reserved on secure omap3 */
+&sdma {
+ dma-channel-mask = <0xfffffffc>;
+};
+
&twl {
twl_audio: audio {
compatible = "ti,twl4030-audio";
@@ -621,63 +631,92 @@
};
lp5523: lp5523@32 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "national,lp5523";
reg = <0x32>;
clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
- enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
+ enable-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
- chan0 {
+ led@0 {
+ reg = <0>;
chan-name = "lp5523:kb1";
led-cur = /bits/ 8 <50>;
max-cur = /bits/ 8 <100>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_KBD_BACKLIGHT;
};
- chan1 {
+ led@1 {
+ reg = <1>;
chan-name = "lp5523:kb2";
led-cur = /bits/ 8 <50>;
max-cur = /bits/ 8 <100>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_KBD_BACKLIGHT;
};
- chan2 {
+ led@2 {
+ reg = <2>;
chan-name = "lp5523:kb3";
led-cur = /bits/ 8 <50>;
max-cur = /bits/ 8 <100>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_KBD_BACKLIGHT;
};
- chan3 {
+ led@3 {
+ reg = <3>;
chan-name = "lp5523:kb4";
led-cur = /bits/ 8 <50>;
max-cur = /bits/ 8 <100>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_KBD_BACKLIGHT;
};
- chan4 {
+ led@4 {
+ reg = <4>;
chan-name = "lp5523:b";
led-cur = /bits/ 8 <50>;
max-cur = /bits/ 8 <100>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
};
- chan5 {
+ led@5 {
+ reg = <5>;
chan-name = "lp5523:g";
led-cur = /bits/ 8 <50>;
max-cur = /bits/ 8 <100>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
};
- chan6 {
+ led@6 {
+ reg = <6>;
chan-name = "lp5523:r";
led-cur = /bits/ 8 <50>;
max-cur = /bits/ 8 <100>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
};
- chan7 {
+ led@7 {
+ reg = <7>;
chan-name = "lp5523:kb5";
led-cur = /bits/ 8 <50>;
max-cur = /bits/ 8 <100>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_KBD_BACKLIGHT;
};
- chan8 {
+ led@8 {
+ reg = <8>;
chan-name = "lp5523:kb6";
led-cur = /bits/ 8 <50>;
max-cur = /bits/ 8 <100>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_KBD_BACKLIGHT;
};
};
@@ -1035,6 +1074,11 @@
};
};
+/* RNG not directly accessible on n900, see omap3-rom-rng instead */
+&rng_target {
+ status = "disabled";
+};
+
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
@@ -1069,7 +1113,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_sdi_pins>;
@@ -1092,7 +1136,7 @@
};
&venc {
- status = "ok";
+ status = "okay";
vdda-supply = <&vdac>;
@@ -1105,7 +1149,7 @@
};
&mcbsp2 {
- status = "ok";
+ status = "okay";
};
&ssi_port1 {
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 6681d45..7dde9fb 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -11,13 +11,6 @@
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
- operating-points = <
- /* kHz uV */
- 300000 1012500
- 600000 1200000
- 800000 1325000
- 1000000 1375000
- >;
};
};
@@ -348,6 +341,11 @@
status = "disabled";
};
+/* RNG not directly accessible on N950/N9. */
+&rng_target {
+ status = "disabled";
+};
+
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
@@ -496,3 +494,11 @@
clock-names = "sysclk";
};
};
+
+&aes1_target {
+ status = "disabled";
+};
+
+&aes2_target {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts
index 9886bf8..b2f4800 100644
--- a/arch/arm/boot/dts/omap3-n950.dts
+++ b/arch/arm/boot/dts/omap3-n950.dts
@@ -12,7 +12,7 @@
/ {
model = "Nokia N950";
- compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
+ compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap36xx", "ti,omap3";
keys {
compatible = "gpio-keys";
@@ -76,7 +76,6 @@
vana-supply = <&vaux3>;
clocks = <&isp 0>;
clock-frequency = <9600000>;
- nokia,nvm-size = <(16 * 64)>;
flash-leds = <&as3645a_flash &as3645a_indicator>;
port {
smia_1_1: endpoint {
@@ -205,13 +204,13 @@
};
&dss {
- status = "ok";
+ status = "okay";
vdda_video-supply = <&vdac>;
};
&dsi {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dsi_pins>;
@@ -225,8 +224,9 @@
};
};
- lcd0: display {
+ lcd0: panel@0 {
compatible = "nokia,himalaya", "panel-dsi-cm";
+ reg = <0>;
label = "lcd0";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi
index c9e62e4..339a51f 100644
--- a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi
@@ -48,7 +48,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi
index 185ce53..1d6e88f 100644
--- a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi
@@ -76,7 +76,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi
index 7fe0f91..7e30f9d 100644
--- a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi
@@ -75,7 +75,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
diff --git a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
index 1833857..7f04dfa 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts
@@ -14,5 +14,5 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35";
- compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
index f204c8a..bc5a04e 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43";
- compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
index c633f7c..065c31c 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43";
- compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts
index fb88ebc..e38c1c5 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35";
- compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
index 76cca00..e6dc231 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43";
- compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/omap3-overo-storm-summit.dts
index cc081a9..587c08c 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-summit.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-summit.dts
@@ -14,7 +14,7 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit";
- compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
index 1de41c0..f57de60 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
@@ -14,6 +14,6 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi";
- compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts
index 9ed1311..281af6c 100644
--- a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts
+++ b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts
@@ -14,5 +14,5 @@
/ {
model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo";
- compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+ compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
diff --git a/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi b/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi
index e5da3bc..218a10c 100644
--- a/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi
@@ -22,7 +22,7 @@
compatible = "smsc,lan9221","smsc,lan9115";
bank-width = <2>;
- gpmc,mux-add-data;
+ gpmc,mux-add-data = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <42>;
gpmc,cs-wr-off-ns = <36>;
diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
index 81b957f..ea50995 100644
--- a/arch/arm/boot/dts/omap3-pandora-1ghz.dts
+++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts
@@ -16,7 +16,7 @@
/ {
model = "Pandora Handheld Console 1GHz";
- compatible = "openpandora,omap3-pandora-1ghz", "ti,omap36xx", "ti,omap3";
+ compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap36xx", "ti,omap3";
};
&omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi
index 150d5be..37608af 100644
--- a/arch/arm/boot/dts/omap3-pandora-common.dtsi
+++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi
@@ -702,7 +702,7 @@
};
&venc {
- status = "ok";
+ status = "okay";
vdda-supply = <&vdac>;
@@ -718,7 +718,7 @@
pinctrl-names = "default";
pinctrl-0 = < &dss_dpi_pins >;
- status = "ok";
+ status = "okay";
vdds_dsi-supply = <&vpll2>;
port {
diff --git a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi
index b8b9fcc..2dbb687 100644
--- a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi
+++ b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi
@@ -46,7 +46,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
port {
dpi_out: endpoint {
remote-endpoint = <&lcd_in>;
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
index ae96002..24bf3fd 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3530.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -8,7 +8,7 @@
/ {
model = "CompuLab SBC-T3530 with CM-T3530";
- compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
+ compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
aliases {
display0 = &dvi0;
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index 7de6df1..eb3893b 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -8,7 +8,7 @@
/ {
model = "CompuLab SBC-T3730 with CM-T3730";
- compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
+ compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3";
aliases {
display0 = &dvi0;
diff --git a/arch/arm/boot/dts/omap3-sniper.dts b/arch/arm/boot/dts/omap3-sniper.dts
index 40a8733..b6879cd 100644
--- a/arch/arm/boot/dts/omap3-sniper.dts
+++ b/arch/arm/boot/dts/omap3-sniper.dts
@@ -9,7 +9,7 @@
/ {
model = "LG Optimus Black";
- compatible = "lg,omap3-sniper", "ti,omap36xx", "ti,omap3";
+ compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index f24e232..580bfa1 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*/
/dts-v1/;
@@ -8,7 +8,11 @@
#include "omap34xx.dtsi"
/* Secure omaps have some devices inaccessible depending on the firmware */
-&aes {
+&aes1_target {
+ status = "disabled";
+};
+
+&aes2_target {
status = "disabled";
};
diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts
index 6276e70..d82cab8 100644
--- a/arch/arm/boot/dts/omap3-thunder.dts
+++ b/arch/arm/boot/dts/omap3-thunder.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*/
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3 Thunder baseboard with TAO3530 SOM";
- compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
+ compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap3430", "ti,omap34xx", "ti,omap3";
};
&omap3_pmx_core {
@@ -64,7 +64,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts
index db3a2fe..0482676 100644
--- a/arch/arm/boot/dts/omap3-zoom3.dts
+++ b/arch/arm/boot/dts/omap3-zoom3.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -9,7 +9,7 @@
/ {
model = "TI Zoom3";
- compatible = "ti,omap3-zoom3", "ti,omap36xx", "ti,omap3";
+ compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 0c8fcfb..c5b9da0 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -1,13 +1,14 @@
/*
* Device Tree Source for OMAP3 SoC
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
+#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/omap.h>
@@ -159,13 +160,56 @@
};
};
- aes: aes@480c5000 {
- compatible = "ti,omap3-aes";
- ti,hwmods = "aes";
- reg = <0x480c5000 0x50>;
- interrupts = <0>;
- dmas = <&sdma 65 &sdma 66>;
- dma-names = "tx", "rx";
+ aes1_target: target-module@480a6000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x480a6044 0x4>,
+ <0x480a6048 0x4>,
+ <0x480a604c 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&aes1_ick>;
+ clock-names = "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x480a6000 0x2000>;
+
+ aes1: aes1@0 {
+ compatible = "ti,omap3-aes";
+ reg = <0 0x50>;
+ interrupts = <0>;
+ dmas = <&sdma 9 &sdma 10>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ aes2_target: target-module@480c5000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x480c5044 0x4>,
+ <0x480c5048 0x4>,
+ <0x480c504c 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&aes2_ick>;
+ clock-names = "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x480c5000 0x2000>;
+
+ aes2: aes2@0 {
+ compatible = "ti,omap3-aes";
+ reg = <0 0x50>;
+ interrupts = <0>;
+ dmas = <&sdma 65 &sdma 66>;
+ dma-names = "tx", "rx";
+ };
};
prm: prm@48306000 {
@@ -195,10 +239,23 @@
};
};
- counter32k: counter@48320000 {
- compatible = "ti,omap-counter32k";
- reg = <0x48320000 0x20>;
- ti,hwmods = "counter_32k";
+ target-module@48320000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x48320000 0x4>,
+ <0x48320004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48320000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x0 0x20>;
+ };
};
intc: interrupt-controller@48200000 {
@@ -208,17 +265,41 @@
reg = <0x48200000 0x1000>;
};
- sdma: dma-controller@48056000 {
- compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
- reg = <0x48056000 0x1000>;
- interrupts = <12>,
- <13>,
- <14>,
- <15>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <96>;
- ti,hwmods = "dma";
+ target-module@48056000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x48056000 0x4>,
+ <0x4805602c 0x4>,
+ <0x48056028 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */
+ clocks = <&core_l3_ick>;
+ clock-names = "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x48056000 0x1000>;
+
+ sdma: dma-controller@0 {
+ compatible = "ti,omap3430-sdma", "ti,omap-sdma";
+ reg = <0x0 0x1000>;
+ interrupts = <12>,
+ <13>,
+ <14>,
+ <15>;
+ #dma-cells = <1>;
+ dma-channels = <32>;
+ dma-requests = <96>;
+ };
};
gpio1: gpio@48310000 {
@@ -505,6 +586,30 @@
status = "disabled";
};
+ /* Likely needs to be tagged disabled on HS devices */
+ rng_target: target-module@480a0000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x480a003c 0x4>,
+ <0x480a0040 0x4>,
+ <0x480a0044 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,syss-mask = <1>;
+ clocks = <&rng_ick>;
+ clock-names = "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x480a0000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap2-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <52>;
+ };
+ };
+
mcbsp2: mcbsp@49022000 {
compatible = "ti,omap3-mcbsp";
reg = <0x49022000 0xff>,
@@ -591,19 +696,63 @@
dma-names = "rx";
};
- timer1: timer@48318000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48318000 0x400>;
- interrupts = <37>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
+ timer1_target: target-module@48318000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x48318000 0x4>,
+ <0x48318010 0x4>,
+ <0x48318014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt1_fck>, <&gpt1_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48318000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&gpt1_fck>;
+ clock-names = "fck";
+ interrupts = <37>;
+ ti,timer-alwon;
+ };
};
- timer2: timer@49032000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49032000 0x400>;
- interrupts = <38>;
- ti,hwmods = "timer2";
+ timer2_target: target-module@49032000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x49032000 0x4>,
+ <0x49032010 0x4>,
+ <0x49032014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt2_fck>, <&gpt2_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49032000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0 0x400>;
+ interrupts = <38>;
+ };
};
timer3: timer@49034000 {
@@ -677,13 +826,34 @@
ti,timer-pwm;
};
- timer12: timer@48304000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48304000 0x400>;
- interrupts = <95>;
- ti,hwmods = "timer12";
- ti,timer-alwon;
- ti,timer-secure;
+ timer12_target: target-module@48304000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x48304000 0x4>,
+ <0x48304010 0x4>,
+ <0x48304014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt12_fck>, <&gpt12_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48304000 0x1000>;
+
+ timer12: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0 0x400>;
+ interrupts = <95>;
+ ti,timer-alwon;
+ ti,timer-secure;
+ };
};
usbhstll: usbhstll@48062000 {
@@ -774,6 +944,9 @@
ti,hwmods = "dss_dsi1";
clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
clock-names = "fck", "sys_clk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
};
rfbi: encoder@48050800 {
@@ -840,4 +1013,14 @@
};
};
-/include/ "omap3xxx-clocks.dtsi"
+#include "omap3xxx-clocks.dtsi"
+
+/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt1_fck>;
+ assigned-clock-parents = <&omap_32k_fck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 0abd611..7d530ae 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -8,7 +8,7 @@
/ {
model = "TI OMAP3430 SDP";
- compatible = "ti,omap3430-sdp", "ti,omap3";
+ compatible = "ti,omap3430-sdp", "ti,omap3430", "ti,omap3";
memory@80000000 {
device_type = "memory";
@@ -101,7 +101,7 @@
nand@1,0 {
compatible = "ti,omap2-nand";
- reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
index 5e9d1af..21079cd 100644
--- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -260,6 +260,6 @@
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
<&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
- <&mspro_fck>;
+ <&rng_ick>, <&mspro_fck>;
};
};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 7b09cbe..feaa43b 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP34xx/OMAP35xx SoC
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -16,16 +16,65 @@
/ {
cpus {
cpu: cpu@0 {
- /* OMAP343x/OMAP35xx variants OPP1-5 */
- operating-points = <
- /* kHz uV */
- 125000 975000
- 250000 1075000
- 500000 1200000
- 550000 1270000
- 600000 1350000
- >;
+ /* OMAP343x/OMAP35xx variants OPP1-6 */
+ operating-points-v2 = <&cpu0_opp_table>;
+
clock-latency = <300000>; /* From legacy driver */
+ #cooling-cells = <2>;
+ };
+ };
+
+ /* see Documentation/devicetree/bindings/opp/opp.txt */
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_conf>;
+
+ opp1-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ /*
+ * we currently only select the max voltage from table
+ * Table 3-3 of the omap3530 Data sheet (SPRS507F).
+ * Format is: <target min max>
+ */
+ opp-microvolt = <975000 975000 975000>;
+ /*
+ * first value is silicon revision bit mask
+ * second one 720MHz Device Identification bit mask
+ */
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp2-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <1075000 1075000 1075000>;
+ opp-supported-hw = <0xffffffff 3>;
+ opp-suspend;
+ };
+
+ opp3-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1200000 1200000 1200000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp4-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-microvolt = <1275000 1275000 1275000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp5-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp6-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ /* only high-speed grade omap3530 devices */
+ opp-supported-hw = <0xffffffff 2>;
+ turbo-mode;
};
};
@@ -134,7 +183,7 @@
};
&ssi {
- status = "ok";
+ status = "okay";
clocks = <&ssi_ssr_fck>,
<&ssi_sst_fck>,
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
index e66fc57..4e9cc90 100644
--- a/arch/arm/boot/dts/omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -105,3 +105,7 @@
<&mcbsp4_ick>, <&uart4_fck>;
};
};
+
+&dpll4_m4_ck {
+ ti,max-div = <31>;
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 1e552f0..05fe5ed 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP3 SoC
*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -19,18 +19,68 @@
};
cpus {
- /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
+ /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
cpu: cpu@0 {
- operating-points = <
- /* kHz uV */
- 300000 1012500
- 600000 1200000
- 800000 1325000
- >;
- clock-latency = <300000>; /* From legacy driver */
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ vbb-supply = <&abb_mpu_iva>;
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+ #cooling-cells = <2>;
};
};
+ /* see Documentation/devicetree/bindings/opp/opp.txt */
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_conf>;
+
+ opp50-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ /*
+ * we currently only select the max voltage from table
+ * Table 4-19 of the DM3730 Data sheet (SPRS685B)
+ * Format is: cpu0-supply: <target min max>
+ * vbb-supply: <target min max>
+ */
+ opp-microvolt = <1012500 1012500 1012500>,
+ <1012500 1012500 1012500>;
+ /*
+ * first value is silicon revision bit mask
+ * second one is "speed binned" bit mask
+ */
+ opp-supported-hw = <0xffffffff 3>;
+ opp-suspend;
+ };
+
+ opp100-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1200000 1200000 1200000>,
+ <1200000 1200000 1200000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp130-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1325000 1325000 1325000>,
+ <1325000 1325000 1325000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp1g-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1375000 1375000 1375000>,
+ <1375000 1375000 1375000>;
+ /* only on am/dm37x with speed-binned bit set */
+ opp-supported-hw = <0xffffffff 2>;
+ turbo-mode;
+ };
+ };
+
+ opp_supply_mpu_iva: opp_supply {
+ compatible = "ti,omap-opp-supply";
+ ti,absolute-max-voltage-uv = <1375000>;
+ };
+
ocp@68000000 {
uart4: serial@49042000 {
compatible = "ti,omap3-uart";
@@ -174,6 +224,10 @@
};
};
+&sdma {
+ compatible = "ti,omap3630-sdma", "ti,omap-sdma";
+};
+
/* OMAP3630 needs dss_96m_fck for VENC */
&venc {
clocks = <&dss_tv_fck>, <&dss_96m_fck>;
@@ -181,7 +235,7 @@
};
&ssi {
- status = "ok";
+ status = "okay";
clocks = <&ssi_ssr_fck>,
<&ssi_sst_fck>,
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 685c82a..0656c32 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -416,7 +416,7 @@
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll4_ck>;
- ti,max-div = <32>;
+ ti,max-div = <16>;
reg = <0x0e40>;
ti,index-starts-at-one;
};
diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
index ab7f87a..03d054b 100644
--- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP4/5 SoC CPU thermal
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
* Contact: Eduardo Valentin <eduardo.valentin@ti.com>
*
* This file is licensed under the terms of the GNU General Public License
diff --git a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts
new file mode 100644
index 0000000..ba5c35b
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "motorola-mapphone-common.dtsi"
+
+/ {
+ model = "Motorola Droid Bionic XT875";
+ compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4";
+};
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
index a40fe8d..c0d2fd9 100644
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -1,784 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include "omap443x.dtsi"
-#include "motorola-cpcap-mapphone.dtsi"
+#include "motorola-mapphone-common.dtsi"
/ {
model = "Motorola Droid 4 XT894";
compatible = "motorola,droid4", "ti,omap4430", "ti,omap4";
-
- chosen {
- stdout-path = &uart3;
- };
-
- aliases {
- display0 = &lcd0;
- display1 = &hdmi0;
- };
-
- /*
- * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
- * then 1023 - 1024 seems to contain mbm.
- */
- memory {
- device_type = "memory";
- reg = <0x80000000 0x3fd00000>; /* 1021 MB */
- };
-
- /* Poweroff GPIO probably connected to CPCAP */
- gpio-poweroff {
- compatible = "gpio-poweroff";
- pinctrl-0 = <&poweroff_gpio>;
- pinctrl-names = "default";
- gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; /* gpio50 */
- };
-
- hdmi0: connector {
- compatible = "hdmi-connector";
- pinctrl-0 = <&hdmi_hpd_gpio>;
- pinctrl-names = "default";
- label = "hdmi";
- type = "d";
-
- hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio63 */
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_out>;
- };
- };
- };
-
- /*
- * HDMI 5V regulator probably sourced from battery. Let's keep
- * keep this as always enabled for HDMI to work until we've
- * figured what the encoder chip is.
- */
- hdmi_regulator: regulator-hdmi {
- compatible = "regulator-fixed";
- regulator-name = "hdmi";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio59 */
- enable-active-high;
- regulator-always-on;
- };
-
- /* FS USB Host PHY on port 1 for mdm6600 */
- fsusb1_phy: usb-phy@1 {
- compatible = "motorola,mapphone-mdm6600";
- pinctrl-0 = <&usb_mdm6600_pins>;
- pinctrl-names = "default";
- enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */
- power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */
- reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */
- /* mode: gpio_148 gpio_149 */
- motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
- <&gpio5 21 GPIO_ACTIVE_HIGH>;
- /* cmd: gpio_103 gpio_104 gpio_142 */
- motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
- <&gpio4 8 GPIO_ACTIVE_HIGH>,
- <&gpio5 14 GPIO_ACTIVE_HIGH>;
- /* status: gpio_52 gpio_53 gpio_55 */
- motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
- <&gpio2 21 GPIO_ACTIVE_HIGH>,
- <&gpio2 23 GPIO_ACTIVE_HIGH>;
- #phy-cells = <0>;
- };
-
- /* HS USB host TLL nop-phy on port 2 for w3glte */
- hsusb2_phy: usb-phy@2 {
- compatible = "usb-nop-xceiv";
- #phy-cells = <0>;
- };
-
- /* LCD regulator from sw5 source */
- lcd_regulator: regulator-lcd {
- compatible = "regulator-fixed";
- regulator-name = "lcd";
- regulator-min-microvolt = <5050000>;
- regulator-max-microvolt = <5050000>;
- gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */
- enable-active-high;
- vin-supply = <&sw5>;
- };
-
- /* This is probably coming straight from the battery.. */
- wl12xx_vmmc: regulator-wl12xx {
- compatible = "regulator-fixed";
- regulator-name = "vwl1271";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <1650000>;
- gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; /* gpio94 */
- startup-delay-us = <70000>;
- enable-active-high;
- };
-
- gpio_keys {
- compatible = "gpio-keys";
-
- volume_down {
- label = "Volume Down";
- gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */
- linux,code = <KEY_VOLUMEDOWN>;
- linux,can-disable;
- /* Value above 7.95ms for no GPIO hardware debounce */
- debounce-interval = <10>;
- };
-
- slider {
- label = "Keypad Slide";
- gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */
- linux,input-type = <EV_SW>;
- linux,code = <SW_KEYPAD_SLIDE>;
- linux,can-disable;
- /* Value above 7.95ms for no GPIO hardware debounce */
- debounce-interval = <10>;
- };
- };
-
- soundcard {
- compatible = "audio-graph-card";
- label = "Droid 4 Audio";
-
- simple-graph-card,widgets =
- "Speaker", "Earpiece",
- "Speaker", "Loudspeaker",
- "Headphone", "Headphone Jack",
- "Microphone", "Internal Mic";
-
- simple-graph-card,routing =
- "Earpiece", "EP",
- "Loudspeaker", "SPKR",
- "Headphone Jack", "HSL",
- "Headphone Jack", "HSR",
- "MICR", "Internal Mic";
-
- dais = <&mcbsp2_port>, <&mcbsp3_port>;
- };
-
- pwm8: dmtimer-pwm-8 {
- pinctrl-names = "default";
- pinctrl-0 = <&vibrator_direction_pin>;
-
- compatible = "ti,omap-dmtimer-pwm";
- #pwm-cells = <3>;
- ti,timers = <&timer8>;
- ti,clock-source = <0x01>;
- };
-
- pwm9: dmtimer-pwm-9 {
- pinctrl-names = "default";
- pinctrl-0 = <&vibrator_enable_pin>;
-
- compatible = "ti,omap-dmtimer-pwm";
- #pwm-cells = <3>;
- ti,timers = <&timer9>;
- ti,clock-source = <0x01>;
- };
-
- vibrator {
- compatible = "pwm-vibrator";
- pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>;
- pwm-names = "enable", "direction";
- direction-duty-cycle-ns = <10000000>;
- };
-};
-
-&dss {
- status = "okay";
-};
-
-&dsi1 {
- status = "okay";
- vdd-supply = <&vcsi>;
-
- port {
- dsi1_out_ep: endpoint {
- remote-endpoint = <&lcd0_in>;
- lanes = <0 1 2 3 4 5>;
- };
- };
-
- lcd0: display {
- compatible = "panel-dsi-cm";
- label = "lcd0";
- vddi-supply = <&lcd_regulator>;
- reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */
-
- width-mm = <50>;
- height-mm = <89>;
-
- panel-timing {
- clock-frequency = <0>; /* Calculated by dsi */
-
- hback-porch = <2>;
- hactive = <540>;
- hfront-porch = <0>;
- hsync-len = <2>;
-
- vback-porch = <1>;
- vactive = <960>;
- vfront-porch = <0>;
- vsync-len = <1>;
-
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
-
- port {
- lcd0_in: endpoint {
- remote-endpoint = <&dsi1_out_ep>;
- };
- };
- };
-};
-
-&hdmi {
- status = "okay";
- pinctrl-0 = <&dss_hdmi_pins>;
- pinctrl-names = "default";
- vdda-supply = <&vdac>;
-
- port {
- hdmi_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- lanes = <1 0 3 2 5 4 7 6>;
- };
- };
-};
-
-&i2c1 {
- tmp105@48 {
- compatible = "ti,tmp105";
- reg = <0x48>;
- pinctrl-0 = <&tmp105_irq>;
- pinctrl-names = "default";
- /* kpd_row0.gpio_178 */
- interrupts-extended = <&gpio6 18 IRQ_TYPE_EDGE_FALLING
- &omap4_pmx_core 0x14e>;
- interrupt-names = "irq", "wakeup";
- wakeup-source;
- };
-};
-
-&keypad {
- keypad,num-rows = <8>;
- keypad,num-columns = <8>;
- linux,keymap = <
-
- /* Row 1 */
- MATRIX_KEY(0, 2, KEY_1)
- MATRIX_KEY(0, 6, KEY_2)
- MATRIX_KEY(2, 3, KEY_3)
- MATRIX_KEY(0, 7, KEY_4)
- MATRIX_KEY(0, 4, KEY_5)
- MATRIX_KEY(5, 5, KEY_6)
- MATRIX_KEY(0, 1, KEY_7)
- MATRIX_KEY(0, 5, KEY_8)
- MATRIX_KEY(0, 0, KEY_9)
- MATRIX_KEY(1, 6, KEY_0)
-
- /* Row 2 */
- MATRIX_KEY(3, 4, KEY_APOSTROPHE)
- MATRIX_KEY(7, 6, KEY_Q)
- MATRIX_KEY(7, 7, KEY_W)
- MATRIX_KEY(7, 2, KEY_E)
- MATRIX_KEY(1, 0, KEY_R)
- MATRIX_KEY(4, 4, KEY_T)
- MATRIX_KEY(1, 2, KEY_Y)
- MATRIX_KEY(6, 7, KEY_U)
- MATRIX_KEY(2, 2, KEY_I)
- MATRIX_KEY(5, 6, KEY_O)
- MATRIX_KEY(3, 7, KEY_P)
- MATRIX_KEY(6, 5, KEY_BACKSPACE)
-
- /* Row 3 */
- MATRIX_KEY(5, 4, KEY_TAB)
- MATRIX_KEY(5, 7, KEY_A)
- MATRIX_KEY(2, 7, KEY_S)
- MATRIX_KEY(7, 0, KEY_D)
- MATRIX_KEY(2, 6, KEY_F)
- MATRIX_KEY(6, 2, KEY_G)
- MATRIX_KEY(6, 6, KEY_H)
- MATRIX_KEY(1, 4, KEY_J)
- MATRIX_KEY(3, 1, KEY_K)
- MATRIX_KEY(2, 1, KEY_L)
- MATRIX_KEY(4, 6, KEY_ENTER)
-
- /* Row 4 */
- MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */
- MATRIX_KEY(6, 1, KEY_Z)
- MATRIX_KEY(7, 4, KEY_X)
- MATRIX_KEY(5, 1, KEY_C)
- MATRIX_KEY(1, 7, KEY_V)
- MATRIX_KEY(2, 4, KEY_B)
- MATRIX_KEY(4, 1, KEY_N)
- MATRIX_KEY(1, 1, KEY_M)
- MATRIX_KEY(3, 5, KEY_COMMA)
- MATRIX_KEY(5, 2, KEY_DOT)
- MATRIX_KEY(6, 3, KEY_UP)
- MATRIX_KEY(7, 3, KEY_OK)
-
- /* Row 5 */
- MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */
- MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */
- MATRIX_KEY(6, 0, KEY_MINUS)
- MATRIX_KEY(4, 7, KEY_EQUAL)
- MATRIX_KEY(1, 5, KEY_SPACE)
- MATRIX_KEY(3, 2, KEY_SLASH)
- MATRIX_KEY(4, 3, KEY_LEFT)
- MATRIX_KEY(5, 3, KEY_DOWN)
- MATRIX_KEY(3, 3, KEY_RIGHT)
-
- /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */
- MATRIX_KEY(5, 0, KEY_VOLUMEUP)
- >;
-};
-
-&mmc1 {
- vmmc-supply = <&vwlan2>;
- bus-width = <4>;
- cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio176 */
-};
-
-&mmc2 {
- vmmc-supply = <&vsdio>;
- bus-width = <8>;
- ti,non-removable;
-};
-
-&mmc3 {
- vmmc-supply = <&wl12xx_vmmc>;
- /* uart2_tx.sdmmc3_dat1 pad as wakeirq */
- interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
- &omap4_pmx_core 0xde>;
- interrupt-names = "irq", "wakeup";
- non-removable;
- bus-width = <4>;
- cap-power-off-card;
- keep-power-in-suspend;
-
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1285", "ti,wl1283";
- reg = <2>;
- /* gpio_100 with gpmc_wait2 pad as wakeirq */
- interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
- <&omap4_pmx_core 0x4e>;
- interrupt-names = "irq", "wakeup";
- ref-clock-frequency = <26000000>;
- tcxo-clock-frequency = <26000000>;
- };
-};
-
-&i2c1 {
- led-controller@38 {
- compatible = "ti,lm3532";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x38>;
-
- enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
-
- ramp-up-us = <1024>;
- ramp-down-us = <8193>;
-
- led@0 {
- reg = <0>;
- led-sources = <2>;
- ti,led-mode = <0>;
- label = ":backlight";
- linux,default-trigger = "backlight";
- };
-
- led@1 {
- reg = <1>;
- led-sources = <1>;
- ti,led-mode = <0>;
- label = ":kbd_backlight";
- };
- };
-};
-
-&i2c2 {
- touchscreen@4a {
- compatible = "atmel,maxtouch";
- reg = <0x4a>;
- pinctrl-names = "default";
- pinctrl-0 = <&touchscreen_pins>;
-
- reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */
-
- /* gpio_183 with sys_nirq2 pad as wakeup */
- interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>,
- <&omap4_pmx_core 0x160>;
- interrupt-names = "irq", "wakeup";
- wakeup-source;
- };
-
- isl29030@44 {
- compatible = "isil,isl29030";
- reg = <0x44>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&als_proximity_pins>;
-
- interrupt-parent = <&gpio6>;
- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */
- };
-};
-
-&omap4_pmx_core {
-
- /* hdmi_hpd.gpio_63 */
- hdmi_hpd_gpio: pinmux_hdmi_hpd_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3)
- >;
- };
-
- /* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
- dss_hdmi_pins: pinmux_dss_hdmi_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0)
- OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0)
- OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0)
- >;
- };
-
- /* gpmc_ncs0.gpio_50 */
- poweroff_gpio: pinmux_poweroff_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x074, PIN_OUTPUT_PULLUP | MUX_MODE3)
- >;
- };
-
- /* kpd_row0.gpio_178 */
- tmp105_irq: pinmux_tmp105_irq {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3)
- >;
- };
-
- usb_gpio_mux_sel1: pinmux_usb_gpio_mux_sel1_pins {
- /* gpio_60 */
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3)
- >;
- };
-
- touchscreen_pins: pinmux_touchscreen_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3)
- OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3)
- >;
- };
-
- als_proximity_pins: pinmux_als_proximity_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3)
- >;
- };
-
- usb_mdm6600_pins: pinmux_usb_mdm6600_pins {
- pinctrl-single,pins = <
- /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */
- OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3)
-
- /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */
- OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3)
-
- /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */
- OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3)
-
- /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */
- OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3)
-
- /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */
- OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3)
-
- /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */
- OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3)
-
- /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */
- OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)
-
- /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */
- OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3)
-
- /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */
- OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3)
-
- /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */
- OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3)
-
- /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */
- OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3)
- >;
- };
-
- usb_ulpi_pins: pinmux_usb_ulpi_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x196, MUX_MODE7)
- OMAP4_IOPAD(0x198, MUX_MODE7)
- OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE0)
- OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE0)
- >;
- };
-
- /* usb0_otg_dp and usb0_otg_dm */
- usb_utmi_pins: pinmux_usb_utmi_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0)
- OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0)
- OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1ba, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1bc, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
- >;
- };
-
- /*
- * Note that the v3.0.8 stock userspace dynamically remuxes uart1
- * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7
- * when not used. If needed, we can add rts pin remux later based
- * on power measurements.
- */
- uart1_pins: pinmux_uart1_pins {
- pinctrl-single,pins = <
- /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */
- OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1)
-
- /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */
- OMAP4_IOPAD(0x13e, MUX_MODE1)
-
- /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */
- OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1)
-
- /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */
- OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2)
- >;
- };
-
- /* uart3_tx_irtx and uart3_rx_irrx */
- uart3_pins: pinmux_uart3_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x196, MUX_MODE7)
- OMAP4_IOPAD(0x198, MUX_MODE7)
- OMAP4_IOPAD(0x1b2, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1b6, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1b8, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1ba, MUX_MODE2)
- OMAP4_IOPAD(0x1bc, PIN_INPUT | MUX_MODE2)
- OMAP4_IOPAD(0x1be, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1c0, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1c2, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1c4, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1c6, PIN_INPUT_PULLUP | MUX_MODE7)
- OMAP4_IOPAD(0x1c8, PIN_INPUT_PULLUP | MUX_MODE7)
- >;
- };
-
- uart4_pins: pinmux_uart4_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx */
- OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx */
- OMAP4_IOPAD(0x110, PIN_INPUT_PULLUP | MUX_MODE5) /* uart4_cts */
- OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5) /* uart4_rts */
- >;
- };
-
- mcbsp2_pins: pinmux_mcbsp2_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx */
- OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_dr */
- OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0) /* abe_mcbsp2_dx */
- OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx */
- >;
- };
-
- mcbsp3_pins: pinmux_mcbsp3_pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_dr */
- OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1) /* abe_mcbsp3_dx */
- OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_clkx */
- OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */
- >;
- };
-
- vibrator_direction_pin: pinmux_vibrator_direction_pin {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
- >;
- };
-
- vibrator_enable_pin: pinmux_vibrator_enable_pin {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
- >;
- };
-};
-
-&omap4_pmx_wkup {
- usb_gpio_mux_sel2: pinmux_usb_gpio_mux_sel2_pins {
- /* gpio_wk0 */
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
- >;
- };
-};
-
-/* Configure pwm clock source for timers 8 & 9 */
-&timer8 {
- assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
- assigned-clock-parents = <&sys_clkin_ck>;
-};
-
-&timer9 {
- assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
- assigned-clock-parents = <&sys_clkin_ck>;
-};
-
-/*
- * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
- * uart1 wakeirq.
- */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
- interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
- &omap4_pmx_core 0xfc>;
-};
-
-&uart3 {
- interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
- &omap4_pmx_core 0x17c>;
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins>;
-
- bluetooth {
- compatible = "ti,wl1285-st";
- enable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; /* gpio 174 */
- max-speed = <3686400>;
- };
-};
-
-&usbhsohci {
- phys = <&fsusb1_phy>;
- phy-names = "usb";
-};
-
-&usbhsehci {
- phys = <&hsusb2_phy>;
-};
-
-&usbhshost {
- port1-mode = "ohci-phy-4pin-dpdm";
- port2-mode = "ehci-tll";
-};
-
-/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */
-&usb_otg_hs {
- interface-type = <1>;
- mode = <3>;
- power = <50>;
-};
-
-&i2c4 {
- ak8975: magnetometer@c {
- compatible = "asahi-kasei,ak8975";
- reg = <0x0c>;
-
- vdd-supply = <&vhvio>;
-
- interrupt-parent = <&gpio6>;
- interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */
-
- rotation-matrix = "-1", "0", "0",
- "0", "1", "0",
- "0", "0", "-1";
-
- };
-
- lis3dh: accelerometer@18 {
- compatible = "st,lis3dh-accel";
- reg = <0x18>;
-
- vdd-supply = <&vhvio>;
-
- interrupt-parent = <&gpio2>;
- interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */
-
- rotation-matrix = "0", "-1", "0",
- "1", "0", "0",
- "0", "0", "1";
- };
-};
-
-&mcbsp2 {
- #sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp2_pins>;
- status = "okay";
-
- mcbsp2_port: port {
- cpu_dai2: endpoint {
- dai-format = "i2s";
- remote-endpoint = <&cpcap_audio_codec0>;
- frame-master = <&cpcap_audio_codec0>;
- bitclock-master = <&cpcap_audio_codec0>;
- };
- };
-};
-
-&mcbsp3 {
- #sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp3_pins>;
- status = "okay";
-
- mcbsp3_port: port {
- cpu_dai3: endpoint {
- dai-format = "dsp_a";
- frame-master = <&cpcap_audio_codec1>;
- bitclock-master = <&cpcap_audio_codec1>;
- remote-endpoint = <&cpcap_audio_codec1>;
- };
- };
-};
-
-&cpcap_audio_codec0 {
- remote-endpoint = <&cpu_dai2>;
-};
-
-&cpcap_audio_codec1 {
- remote-endpoint = <&cpu_dai3>;
};
diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts
index 4548d87..b294c22 100644
--- a/arch/arm/boot/dts/omap4-duovero-parlor.dts
+++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts
@@ -171,11 +171,11 @@
};
&dss {
- status = "ok";
+ status = "okay";
};
&hdmi {
- status = "ok";
+ status = "okay";
vdda-supply = <&vdac>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi
index 8e6662b..a9573d4 100644
--- a/arch/arm/boot/dts/omap4-l4-abe.dtsi
+++ b/arch/arm/boot/dts/omap4-l4-abe.dtsi
@@ -1,14 +1,16 @@
&l4_abe { /* 0x40100000 */
- compatible = "ti,omap4-l4-abe", "simple-bus";
+ compatible = "ti,omap4-l4-abe", "simple-pm-bus";
reg = <0x40100000 0x400>,
<0x40100400 0x400>;
reg-names = "la", "ap";
+ power-domains = <&prm_abe>;
+ /* OMAP4_L4_ABE_CLKCTRL is read-only */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
<0x49000000 0x49000000 0x100000>;
segment@0 { /* 0x40100000 */
- compatible = "simple-bus";
+ compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges =
@@ -86,7 +88,6 @@
target-module@22000 { /* 0x40122000, ap 2 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mcbsp1";
reg = <0x2208c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
@@ -120,7 +121,6 @@
target-module@24000 { /* 0x40124000, ap 4 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mcbsp2";
reg = <0x2408c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
@@ -154,7 +154,6 @@
target-module@26000 { /* 0x40126000, ap 6 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mcbsp3";
reg = <0x2608c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
@@ -188,7 +187,6 @@
target-module@28000 { /* 0x40128000, ap 8 08.0 */
compatible = "ti,sysc-mcasp", "ti,sysc";
- ti,hwmods = "mcasp";
reg = <0x28000 0x4>,
<0x28004 0x4>;
reg-names = "rev", "sysc";
@@ -223,7 +221,6 @@
target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "dmic";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
@@ -283,7 +280,6 @@
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcpdm";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
@@ -318,7 +314,6 @@
target-module@38000 { /* 0x40138000, ap 18 12.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer5";
reg = <0x38000 0x4>,
<0x38010 0x4>;
reg-names = "rev", "sysc";
@@ -340,8 +335,9 @@
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x49038000 0x80>;
- clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>,
+ <&syc_clk_div_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
@@ -349,7 +345,6 @@
target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer6";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
@@ -371,8 +366,9 @@
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x4903a000 0x80>;
- clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>,
+ <&syc_clk_div_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
@@ -380,7 +376,6 @@
target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer7";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
@@ -402,8 +397,9 @@
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x4903c000 0x80>;
- clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>,
+ <&syc_clk_div_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
@@ -411,7 +407,6 @@
target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer8";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -433,8 +428,9 @@
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x4903e000 0x80>;
- clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>,
+ <&syc_clk_div_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,timer-dsp;
@@ -470,7 +466,6 @@
target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "aess";
reg = <0xf1000 0x4>,
<0xf1010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi
index d60d5e0..5015df4 100644
--- a/arch/arm/boot/dts/omap4-l4.dtsi
+++ b/arch/arm/boot/dts/omap4-l4.dtsi
@@ -136,7 +136,6 @@
target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "dma_system";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
@@ -160,7 +159,7 @@
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
- compatible = "ti,omap4430-sdma";
+ compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
@@ -174,7 +173,6 @@
target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "hsi";
reg = <0x58000 0x4>,
<0x58010 0x4>,
<0x58014 0x4>;
@@ -242,7 +240,6 @@
target-module@62000 { /* 0x4a062000, ap 11 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "usb_tll_hs";
reg = <0x62000 0x4>,
<0x62010 0x4>,
<0x62014 0x4>;
@@ -270,7 +267,6 @@
target-module@64000 { /* 0x4a064000, ap 86 1e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_host_hs";
reg = <0x64000 0x4>,
<0x64010 0x4>,
<0x64014 0x4>;
@@ -321,7 +317,6 @@
target-module@66000 { /* 0x4a066000, ap 25 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmu_dsp";
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
@@ -335,12 +330,18 @@
/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
clock-names = "fck";
+ resets = <&prm_tesla 1>;
+ reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
- /* mmu_dsp cannot be moved before reset driver */
- status = "disabled";
+ mmu_dsp: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ };
};
};
@@ -381,7 +382,6 @@
target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "usb_otg_hs";
reg = <0x2b400 0x4>,
<0x2b404 0x4>,
<0x2b408 0x4>;
@@ -421,7 +421,6 @@
target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "ocp2scp_usb_phy";
reg = <0x2d000 0x4>,
<0x2d010 0x4>,
<0x2d014 0x4>;
@@ -500,7 +499,6 @@
target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
- ti,hwmods = "smartreflex_mpu";
reg = <0x59038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@@ -524,7 +522,6 @@
target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
- ti,hwmods = "smartreflex_iva";
reg = <0x5b038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@@ -548,7 +545,6 @@
target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
- ti,hwmods = "smartreflex_core";
reg = <0x5d038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@@ -580,7 +576,6 @@
target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox";
reg = <0x74000 0x4>,
<0x74010 0x4>;
reg-names = "rev", "sysc";
@@ -602,11 +597,11 @@
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
- mbox_ipu: mbox_ipu {
+ mbox_ipu: mbox-ipu {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
- mbox_dsp: mbox_dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <2 0 0>;
};
@@ -615,7 +610,6 @@
target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spinlock";
reg = <0x76000 0x4>,
<0x76010 0x4>,
<0x76014 0x4>;
@@ -723,7 +717,6 @@
target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "fdif";
reg = <0xa000 0x4>,
<0xa010 0x4>;
reg-names = "rev", "sysc";
@@ -979,7 +972,6 @@
target-module@4000 { /* 0x4a304000, ap 17 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@@ -1007,7 +999,7 @@
ranges = <0x0 0x6000 0x2000>;
prm: prm@0 {
- compatible = "ti,omap4-prm";
+ compatible = "ti,omap4-prm", "simple-bus";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1085,7 +1077,6 @@
gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio1";
reg = <0x0 0x4>,
<0x10 0x4>,
<0x114 0x4>;
@@ -1145,9 +1136,8 @@
};
};
- target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
+ timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
- ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>,
<0x8014 0x4>;
@@ -1171,8 +1161,9 @@
timer1: timer@0 {
compatible = "ti,omap3430-timer";
reg = <0x0 0x80>;
- clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>,
+ <&sys_clkin_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-alwon;
};
@@ -1180,7 +1171,6 @@
target-module@c000 { /* 0x4a31c000, ap 11 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "kbd";
reg = <0xc000 0x4>,
<0xc010 0x4>,
<0xc014 0x4>;
@@ -1425,7 +1415,6 @@
target-module@32000 { /* 0x48032000, ap 5 02.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
- ti,hwmods = "timer2";
reg = <0x32000 0x4>,
<0x32010 0x4>,
<0x32014 0x4>;
@@ -1449,15 +1438,15 @@
timer2: timer@0 {
compatible = "ti,omap3430-timer";
reg = <0x0 0x80>;
- clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>,
+ <&sys_clkin_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@34000 { /* 0x48034000, ap 7 04.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer3";
reg = <0x34000 0x4>,
<0x34010 0x4>;
reg-names = "rev", "sysc";
@@ -1477,15 +1466,15 @@
timer3: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x0 0x80>;
- clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>,
+ <&sys_clkin_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@36000 { /* 0x48036000, ap 9 0e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer4";
reg = <0x36000 0x4>,
<0x36010 0x4>;
reg-names = "rev", "sysc";
@@ -1505,15 +1494,15 @@
timer4: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x0 0x80>;
- clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>,
+ <&sys_clkin_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@3e000 { /* 0x4803e000, ap 11 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer9";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -1533,13 +1522,15 @@
timer9: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x0 0x80>;
- clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>,
+ <&sys_clkin_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};
+ /* Unused DSS L4 access, see L3 instead */
target-module@40000 { /* 0x48040000, ap 13 0a.0 */
compatible = "ti,sysc";
status = "disabled";
@@ -1550,7 +1541,6 @@
target-module@55000 { /* 0x48055000, ap 15 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio2";
reg = <0x55000 0x4>,
<0x55010 0x4>,
<0x55114 0x4>;
@@ -1584,7 +1574,6 @@
target-module@57000 { /* 0x48057000, ap 17 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio3";
reg = <0x57000 0x4>,
<0x57010 0x4>,
<0x57114 0x4>;
@@ -1618,7 +1607,6 @@
target-module@59000 { /* 0x48059000, ap 19 10.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio4";
reg = <0x59000 0x4>,
<0x59010 0x4>,
<0x59114 0x4>;
@@ -1652,7 +1640,6 @@
target-module@5b000 { /* 0x4805b000, ap 21 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio5";
reg = <0x5b000 0x4>,
<0x5b010 0x4>,
<0x5b114 0x4>;
@@ -1686,7 +1673,6 @@
target-module@5d000 { /* 0x4805d000, ap 23 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio6";
reg = <0x5d000 0x4>,
<0x5d010 0x4>,
<0x5d114 0x4>;
@@ -1900,7 +1886,6 @@
target-module@76000 { /* 0x48076000, ap 39 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "slimbus2";
reg = <0x76000 0x4>,
<0x76010 0x4>;
reg-names = "rev", "sysc";
@@ -1921,7 +1906,6 @@
target-module@78000 { /* 0x48078000, ap 41 1a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "elm";
reg = <0x78000 0x4>,
<0x78010 0x4>,
<0x78014 0x4>;
@@ -1950,7 +1934,6 @@
target-module@86000 { /* 0x48086000, ap 43 24.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
- ti,hwmods = "timer10";
reg = <0x86000 0x4>,
<0x86010 0x4>,
<0x86014 0x4>;
@@ -1974,8 +1957,9 @@
timer10: timer@0 {
compatible = "ti,omap3430-timer";
reg = <0x0 0x80>;
- clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>,
+ <&sys_clkin_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
@@ -1983,7 +1967,6 @@
target-module@88000 { /* 0x48088000, ap 45 2e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer11";
reg = <0x88000 0x4>,
<0x88010 0x4>;
reg-names = "rev", "sysc";
@@ -2003,24 +1986,38 @@
timer11: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x0 0x80>;
- clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>,
+ <&sys_clkin_ck>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};
- target-module@90000 { /* 0x48090000, ap 57 2a.0 */
- compatible = "ti,sysc";
- status = "disabled";
+ rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x91fe0 0x4>,
+ <0x91fe4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x90000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
target-module@96000 { /* 0x48096000, ap 37 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mcbsp4";
reg = <0x9608c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
@@ -2052,7 +2049,6 @@
target-module@98000 { /* 0x48098000, ap 49 22.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcspi1";
reg = <0x98000 0x4>,
<0x98010 0x4>;
reg-names = "rev", "sysc";
@@ -2091,7 +2087,6 @@
target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcspi2";
reg = <0x9a000 0x4>,
<0x9a010 0x4>;
reg-names = "rev", "sysc";
@@ -2182,6 +2177,35 @@
<0x00001000 0x000a5000 0x00001000>;
};
+ des_target: target-module@a5000 { /* 0x480a5000 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xa5030 0x4>,
+ <0xa5034 0x4>,
+ <0xa5038 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa5000 0x00001000>;
+
+ des: des@0 {
+ compatible = "ti,omap4-des";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 117>, <&sdma 116>;
+ dma-names = "tx", "rx";
+ };
+ };
+
target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
compatible = "ti,sysc";
status = "disabled";
@@ -2232,7 +2256,6 @@
target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "hdq1w";
reg = <0xb2000 0x4>,
<0xb2014 0x4>,
<0xb2018 0x4>;
@@ -2289,7 +2312,6 @@
target-module@b8000 { /* 0x480b8000, ap 69 58.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcspi3";
reg = <0xb8000 0x4>,
<0xb8010 0x4>;
reg-names = "rev", "sysc";
@@ -2320,7 +2342,6 @@
target-module@ba000 { /* 0x480ba000, ap 71 32.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcspi4";
reg = <0xba000 0x4>,
<0xba010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index 6408307..8fd076e 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 55ea8b6..609a8de 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/input/input.h>
#include "elpida_ecb240abacn.dtsi"
@@ -12,6 +12,26 @@
reg = <0x80000000 0x40000000>; /* 1 GB */
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dsp_memory_region: dsp-memory@98000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x98000000 0x800000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu_memory_region: ipu-memory@98800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x98800000 0x7000000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
chosen {
stdout-path = &uart3;
};
@@ -546,7 +566,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
port {
dpi_out: endpoint {
@@ -557,12 +577,12 @@
};
&dsi2 {
- status = "ok";
+ status = "okay";
vdd-supply = <&vcxio>;
};
&hdmi {
- status = "ok";
+ status = "okay";
vdda-supply = <&vdac>;
port {
@@ -571,3 +591,17 @@
};
};
};
+
+&dsp {
+ status = "okay";
+ memory-region = <&dsp_memory_region>;
+ ti,timers = <&timer5>;
+ ti,watchdog-timers = <&timer6>;
+};
+
+&ipu {
+ status = "okay";
+ memory-region = <&ipu_memory_region>;
+ ti,timers = <&timer3>;
+ ti,watchdog-timers = <&timer9>, <&timer11>;
+};
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index 468ad1b..6afa8fd 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index fb2f477..529d5bc 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index 4215452..869f627 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap4-sdp.dts"
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 91480ac..afb49a2 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -428,7 +428,7 @@
/*
* Temperature Sensor
- * http://www.ti.com/lit/ds/symlink/tmp105.pdf
+ * https://www.ti.com/lit/ds/symlink/tmp105.pdf
*/
tmp105@48 {
compatible = "ti,tmp105";
@@ -453,7 +453,7 @@
/*
* 3-Axis Digital Compass
- * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
+ * https://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
*/
hmc5843@1e {
compatible = "honeywell,hmc5843";
@@ -648,11 +648,11 @@
};
&dss {
- status = "ok";
+ status = "okay";
};
&dsi1 {
- status = "ok";
+ status = "okay";
vdd-supply = <&vcxio>;
port {
@@ -662,8 +662,9 @@
};
};
- lcd0: display {
+ lcd0: panel@0 {
compatible = "tpo,taal", "panel-dsi-cm";
+ reg = <0>;
label = "lcd0";
reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
@@ -677,7 +678,7 @@
};
&dsi2 {
- status = "ok";
+ status = "okay";
vdd-supply = <&vcxio>;
port {
@@ -687,8 +688,9 @@
};
};
- lcd1: display {
+ lcd1: panel@0 {
compatible = "tpo,taal", "panel-dsi-cm";
+ reg = <0>;
label = "lcd1";
reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
@@ -702,7 +704,7 @@
};
&hdmi {
- status = "ok";
+ status = "okay";
vdda-supply = <&vdac>;
port {
diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
index 41de32b..334cbba 100644
--- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi
+++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com>
- * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com
+ * Copyright (C) 2012 Variscite Ltd. - https://www.variscite.com
*/
#include "omap4460.dtsi"
#include "omap4-mcpdm.dtsi"
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 0a36b8f..0491740 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/bus/ti-sysc.h>
@@ -31,6 +31,8 @@
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
+ rproc0 = &dsp;
+ rproc1 = &ipu;
};
cpus {
@@ -76,7 +78,7 @@
interrupt-parent = <&gic>;
};
- L2: l2-cache-controller@48242000 {
+ L2: cache-controller@48242000 {
compatible = "arm,pl310-cache";
reg = <0x48242000 0x1000>;
cache-unified;
@@ -111,11 +113,6 @@
sram = <&ocmcram>;
};
- dsp {
- compatible = "ti,omap3-c64";
- ti,hwmods = "dsp";
- };
-
iva {
compatible = "ti,ivahd";
ti,hwmods = "iva";
@@ -153,7 +150,7 @@
l4_abe: interconnect@40100000 {
};
- ocmcram: ocmcram@40304000 {
+ ocmcram: sram@40304000 {
compatible = "mmio-sram";
reg = <0x40304000 0xa000>; /* 40k */
};
@@ -178,14 +175,6 @@
#gpio-cells = <2>;
};
- mmu_dsp: mmu@4a066000 {
- compatible = "ti,omap4-iommu";
- reg = <0x4a066000 0x100>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_dsp";
- #iommu-cells = <0>;
- };
-
target-module@52000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "iss";
@@ -211,17 +200,37 @@
/* No child device binding, driver in staging */
};
- mmu_ipu: mmu@55082000 {
- compatible = "ti,omap4-iommu";
- reg = <0x55082000 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x55082000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu_ipu: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
+
target-module@4012c000 {
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "slimbus1";
reg = <0x4012c000 0x4>,
<0x4012c010 0x4>;
reg-names = "rev", "sysc";
@@ -271,40 +280,113 @@
hw-caps-temp-alert;
};
- aes1: aes@4b501000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes1";
- reg = <0x4b501000 0xa0>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 111>, <&sdma 110>;
- dma-names = "tx", "rx";
+ dsp: dsp {
+ compatible = "ti,omap4-dsp";
+ ti,bootreg = <&scm_conf 0x304 0>;
+ iommus = <&mmu_dsp>;
+ resets = <&prm_tesla 0>;
+ clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
+ firmware-name = "omap4-dsp-fw.xe64T";
+ mboxes = <&mailbox &mbox_dsp>;
+ status = "disabled";
};
- aes2: aes@4b701000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes2";
- reg = <0x4b701000 0xa0>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 114>, <&sdma 113>;
- dma-names = "tx", "rx";
+ ipu: ipu@55020000 {
+ compatible = "ti,omap4-ipu";
+ reg = <0x55020000 0x10000>;
+ reg-names = "l2ram";
+ iommus = <&mmu_ipu>;
+ resets = <&prm_core 0>, <&prm_core 1>;
+ clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
+ firmware-name = "omap4-ipu-fw.xem3";
+ mboxes = <&mailbox &mbox_ipu>;
+ status = "disabled";
};
- des: des@480a5000 {
- compatible = "ti,omap4-des";
- ti,hwmods = "des";
- reg = <0x480a5000 0xa0>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 117>, <&sdma 116>;
- dma-names = "tx", "rx";
+ aes1_target: target-module@4b501000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b501080 0x4>,
+ <0x4b501084 0x4>,
+ <0x4b501088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b501000 0x1000>;
+
+ aes1: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 111>, <&sdma 110>;
+ dma-names = "tx", "rx";
+ };
};
- sham: sham@4b100000 {
- compatible = "ti,omap4-sham";
- ti,hwmods = "sham";
- reg = <0x4b100000 0x300>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 119>;
- dma-names = "rx";
+ aes2_target: target-module@4b701000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b701080 0x4>,
+ <0x4b701084 0x4>,
+ <0x4b701088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b701000 0x1000>;
+
+ aes2: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 114>, <&sdma 113>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ sham_target: target-module@4b100000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x4b100100 0x4>,
+ <0x4b100110 0x4>,
+ <0x4b100114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
+ clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b100000 0x1000>;
+
+ sham: sham@0 {
+ compatible = "ti,omap4-sham";
+ reg = <0 0x300>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 119>;
+ dma-names = "rx";
+ };
};
abb_mpu: regulator-abb-mpu {
@@ -358,87 +440,219 @@
*/
};
- dss: dss@58000000 {
- compatible = "ti,omap4-dss";
- reg = <0x58000000 0x80>;
- status = "disabled";
- ti,hwmods = "dss_core";
- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
+ /*
+ * DSS is only using l3 mapping without l4 as noted in the TRM
+ * "10.1.3 DSS Register Manual" for omap4460.
+ */
+ target-module@58000000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58000000 4>,
+ <0x58000014 4>;
+ reg-names = "rev", "syss";
+ ti,syss-mask = <1>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0 0x58000000 0x1000000>;
- dispc@58001000 {
- compatible = "ti,omap4-dispc";
- reg = <0x58001000 0x1000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "dss_dispc";
+ dss: dss@0 {
+ compatible = "ti,omap4-dss";
+ reg = <0 0x80>;
+ status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
- };
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000000>;
- rfbi: encoder@58002000 {
- compatible = "ti,omap4-rfbi";
- reg = <0x58002000 0x1000>;
- status = "disabled";
- ti,hwmods = "dss_rfbi";
- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
- clock-names = "fck", "ick";
- };
+ target-module@1000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x1000 0x4>,
+ <0x1010 0x4>,
+ <0x1014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x1000>;
- venc: encoder@58003000 {
- compatible = "ti,omap4-venc";
- reg = <0x58003000 0x1000>;
- status = "disabled";
- ti,hwmods = "dss_venc";
- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
- clock-names = "fck";
- };
+ dispc@0 {
+ compatible = "ti,omap4-dispc";
+ reg = <0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ };
+ };
- dsi1: encoder@58004000 {
- compatible = "ti,omap4-dsi";
- reg = <0x58004000 0x200>,
- <0x58004200 0x40>,
- <0x58004300 0x20>;
- reg-names = "proto", "phy", "pll";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- ti,hwmods = "dss_dsi1";
- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
- clock-names = "fck", "sys_clk";
- };
+ target-module@2000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2000 0x4>,
+ <0x2010 0x4>,
+ <0x2014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x1000>;
- dsi2: encoder@58005000 {
- compatible = "ti,omap4-dsi";
- reg = <0x58005000 0x200>,
- <0x58005200 0x40>,
- <0x58005300 0x20>;
- reg-names = "proto", "phy", "pll";
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- ti,hwmods = "dss_dsi2";
- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
- clock-names = "fck", "sys_clk";
- };
+ rfbi: encoder@0 {
+ reg = <0 0x1000>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
+ clock-names = "fck", "ick";
+ };
+ };
- hdmi: encoder@58006000 {
- compatible = "ti,omap4-hdmi";
- reg = <0x58006000 0x200>,
- <0x58006200 0x100>,
- <0x58006300 0x100>,
- <0x58006400 0x1000>;
- reg-names = "wp", "pll", "phy", "core";
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- ti,hwmods = "dss_hdmi";
- clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
- <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
- clock-names = "fck", "sys_clk";
- dmas = <&sdma 76>;
- dma-names = "audio_tx";
+ target-module@3000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x3000 0x4>;
+ reg-names = "rev";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "sys_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x3000 0x1000>;
+
+ venc: encoder@0 {
+ compatible = "ti,omap4-venc";
+ reg = <0 0x1000>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module@4000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4010 0x4>,
+ <0x4014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4000 0x1000>;
+
+ dsi1: encoder@0 {
+ compatible = "ti,omap4-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x20>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@5000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x5000 0x4>,
+ <0x5010 0x4>,
+ <0x5014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5000 0x1000>;
+
+ dsi2: encoder@0 {
+ compatible = "ti,omap4-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x20>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ target-module@6000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x6000 0x4>,
+ <0x6010 0x4>;
+ reg-names = "rev", "sysc";
+ /*
+ * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
+ * but HDMI audio will fail with them.
+ */
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck", "dss_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x2000>;
+
+ hdmi: encoder@0 {
+ compatible = "ti,omap4-hdmi";
+ reg = <0 0x200>,
+ <0x200 0x100>,
+ <0x300 0x100>,
+ <0x400 0x1000>;
+ reg-names = "wp", "pll", "phy", "core";
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ dmas = <&sdma 76>;
+ dma-names = "audio_tx";
+ };
+ };
};
};
};
@@ -447,3 +661,45 @@
#include "omap4-l4.dtsi"
#include "omap4-l4-abe.dtsi"
#include "omap44xx-clocks.dtsi"
+
+&prm {
+ prm_tesla: prm@400 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_abe: prm@500 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x500 0x100>;
+ #power-domain-cells = <0>;
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_ivahd: prm@f00 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0xf00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm@1b00 {
+ compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1b00 0x40>;
+ #reset-cells = <1>;
+ };
+};
+
+/* Preferred always-on timer for clockevent */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_32k_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index 6e320ef..dd8ef58 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP443x SoC
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2223dc0..2d3e549 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP4460 SoC
*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 68ab6a9..1f1c04d 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -1271,13 +1271,18 @@
#size-cells = <1>;
ranges = <0 0x1400 0x200>;
- l4_per_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
+ l4_per_clkctrl: clock@20 {
+ compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
reg = <0x20 0x144>;
#clock-cells = <2>;
};
- };
+ l4_secure_clkctrl: clock@1a0 {
+ compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
+ reg = <0x1a0 0x3c>;
+ #clock-cells = <2>;
+ };
+ };
};
&prm {
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index c7bf68c..3a8f102 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
@@ -736,11 +736,11 @@
};
&dss {
- status = "ok";
+ status = "okay";
};
&hdmi {
- status = "ok";
+ status = "okay";
/* vdda-supply populated in board specific dts file */
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index e78d371..ca759b7 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -653,7 +653,7 @@
};
&dss {
- status = "ok";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
@@ -677,12 +677,12 @@
};
&dsi2 {
- status = "ok";
+ status = "okay";
vdd-supply = <&ldo4_reg>;
};
&hdmi {
- status = "ok";
+ status = "okay";
vdda-supply = <&ldo4_reg>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap5-core-thermal.dtsi b/arch/arm/boot/dts/omap5-core-thermal.dtsi
index de8a3d4..02e7633 100644
--- a/arch/arm/boot/dts/omap5-core-thermal.dtsi
+++ b/arch/arm/boot/dts/omap5-core-thermal.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP543x SoC CORE thermal
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
* Contact: Eduardo Valentin <eduardo.valentin@ti.com>
*
* This file is licensed under the terms of the GNU General Public License
diff --git a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
index bc3090f..bf8fa93 100644
--- a/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
+++ b/arch/arm/boot/dts/omap5-gpu-thermal.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP543x SoC GPU thermal
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
* Contact: Eduardo Valentin <eduardo.valentin@ti.com>
*
* This file is licensed under the terms of the GNU General Public License
diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/omap5-l4-abe.dtsi
index dc9d053..a03bca5 100644
--- a/arch/arm/boot/dts/omap5-l4-abe.dtsi
+++ b/arch/arm/boot/dts/omap5-l4-abe.dtsi
@@ -1,14 +1,16 @@
&l4_abe { /* 0x40100000 */
- compatible = "ti,omap5-l4-abe", "simple-bus";
+ compatible = "ti,omap5-l4-abe", "simple-pm-bus";
reg = <0x40100000 0x400>,
<0x40100400 0x400>;
reg-names = "la", "ap";
+ power-domains = <&prm_abe>;
+ /* OMAP5_L4_ABE_CLKCTRL is read-only */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
<0x49000000 0x49000000 0x100000>;
segment@0 { /* 0x40100000 */
- compatible = "simple-bus";
+ compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges =
@@ -86,7 +88,6 @@
target-module@22000 { /* 0x40122000, ap 2 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mcbsp1";
reg = <0x2208c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
@@ -120,7 +121,6 @@
target-module@24000 { /* 0x40124000, ap 4 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mcbsp2";
reg = <0x2408c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
@@ -154,7 +154,6 @@
target-module@26000 { /* 0x40126000, ap 6 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mcbsp3";
reg = <0x2608c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
@@ -206,7 +205,6 @@
target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "dmic";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
@@ -247,7 +245,6 @@
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcpdm";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
@@ -282,7 +279,6 @@
target-module@38000 { /* 0x40138000, ap 18 12.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer5";
reg = <0x38000 0x4>,
<0x38010 0x4>;
reg-names = "rev", "sysc";
@@ -304,8 +300,9 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>,
<0x49038000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>,
+ <&dss_syc_gfclk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
ti,timer-pwm;
@@ -314,7 +311,6 @@
target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer6";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
@@ -336,8 +332,9 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>,
<0x4903a000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>,
+ <&dss_syc_gfclk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
ti,timer-pwm;
@@ -346,7 +343,6 @@
target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer7";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
@@ -368,8 +364,9 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>,
<0x4903c000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>,
+ <&dss_syc_gfclk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
@@ -377,7 +374,6 @@
target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer8";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -399,8 +395,9 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>,
<0x4903e000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>,
+ <&dss_syc_gfclk_div>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
ti,timer-pwm;
@@ -435,8 +432,20 @@
};
target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
- compatible = "ti,sysc";
- status = "disabled";
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xf1000 0x4>,
+ <0xf1010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
+ clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf1000 0x1000>,
diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi
index 0960348..c67c869 100644
--- a/arch/arm/boot/dts/omap5-l4.dtsi
+++ b/arch/arm/boot/dts/omap5-l4.dtsi
@@ -167,7 +167,6 @@
target-module@20000 { /* 0x4a020000, ap 109 08.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_otg_ss";
reg = <0x20000 0x4>,
<0x20010 0x4>;
reg-names = "rev", "sysc";
@@ -213,7 +212,6 @@
target-module@56000 { /* 0x4a056000, ap 7 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "dma_system";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
@@ -237,7 +235,7 @@
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
- compatible = "ti,omap4430-sdma";
+ compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
@@ -270,7 +268,6 @@
target-module@62000 { /* 0x4a062000, ap 11 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "usb_tll_hs";
reg = <0x62000 0x4>,
<0x62010 0x4>,
<0x62014 0x4>;
@@ -299,7 +296,6 @@
target-module@64000 { /* 0x4a064000, ap 71 1e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_host_hs";
reg = <0x64000 0x4>,
<0x64010 0x4>;
reg-names = "rev", "sysc";
@@ -349,7 +345,6 @@
target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "mmu_dsp";
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
@@ -364,12 +359,18 @@
/* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
clock-names = "fck";
+ resets = <&prm_dsp 1>;
+ reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
- /* mmu_dsp cannot be moved before reset driver */
- status = "disabled";
+ mmu_dsp: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ };
};
target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
@@ -430,7 +431,6 @@
target-module@0 { /* 0x4a080000, ap 83 28.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "ocp2scp1";
reg = <0x0 0x4>,
<0x10 0x4>,
<0x14 0x4>;
@@ -488,7 +488,6 @@
target-module@10000 { /* 0x4a090000, ap 89 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "ocp2scp3";
reg = <0x10000 0x4>,
<0x10010 0x4>,
<0x10014 0x4>;
@@ -593,7 +592,6 @@
target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mailbox";
reg = <0x74000 0x4>,
<0x74010 0x4>;
reg-names = "rev", "sysc";
@@ -615,11 +613,11 @@
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
- mbox_ipu: mbox_ipu {
+ mbox_ipu: mbox-ipu {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
- mbox_dsp: mbox_dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <2 0 0>;
};
@@ -628,7 +626,6 @@
target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "spinlock";
reg = <0x76000 0x4>,
<0x76010 0x4>,
<0x76014 0x4>;
@@ -1003,6 +1000,7 @@
<0x00090000 0x00090000 0x002000>, /* ap 55 */
<0x00092000 0x00092000 0x001000>, /* ap 56 */
<0x000a4000 0x000a4000 0x001000>, /* ap 57 */
+ <0x000a5000 0x000a5000 0x001000>,
<0x000a6000 0x000a6000 0x001000>, /* ap 58 */
<0x000a8000 0x000a8000 0x004000>, /* ap 59 */
<0x000ac000 0x000ac000 0x001000>, /* ap 60 */
@@ -1033,7 +1031,6 @@
target-module@20000 { /* 0x48020000, ap 3 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart3";
reg = <0x20050 0x4>,
<0x20054 0x4>,
<0x20058 0x4>;
@@ -1063,7 +1060,6 @@
target-module@32000 { /* 0x48032000, ap 5 3e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer2";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
@@ -1083,15 +1079,15 @@
timer2: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>,
+ <&sys_clkin>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@34000 { /* 0x48034000, ap 7 46.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer3";
reg = <0x34000 0x4>,
<0x34010 0x4>;
reg-names = "rev", "sysc";
@@ -1111,15 +1107,15 @@
timer3: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>,
+ <&sys_clkin>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@36000 { /* 0x48036000, ap 9 4e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer4";
reg = <0x36000 0x4>,
<0x36010 0x4>;
reg-names = "rev", "sysc";
@@ -1139,15 +1135,15 @@
timer4: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>,
+ <&sys_clkin>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer9";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@@ -1167,8 +1163,9 @@
timer9: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>,
+ <&sys_clkin>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
@@ -1176,7 +1173,6 @@
target-module@51000 { /* 0x48051000, ap 45 2e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio7";
reg = <0x51000 0x4>,
<0x51010 0x4>,
<0x51114 0x4>;
@@ -1210,7 +1206,6 @@
target-module@53000 { /* 0x48053000, ap 35 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio8";
reg = <0x53000 0x4>,
<0x53010 0x4>,
<0x53114 0x4>;
@@ -1244,7 +1239,6 @@
target-module@55000 { /* 0x48055000, ap 13 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio2";
reg = <0x55000 0x4>,
<0x55010 0x4>,
<0x55114 0x4>;
@@ -1278,7 +1272,6 @@
target-module@57000 { /* 0x48057000, ap 15 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio3";
reg = <0x57000 0x4>,
<0x57010 0x4>,
<0x57114 0x4>;
@@ -1312,7 +1305,6 @@
target-module@59000 { /* 0x48059000, ap 17 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio4";
reg = <0x59000 0x4>,
<0x59010 0x4>,
<0x59114 0x4>;
@@ -1346,7 +1338,6 @@
target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio5";
reg = <0x5b000 0x4>,
<0x5b010 0x4>,
<0x5b114 0x4>;
@@ -1380,7 +1371,6 @@
target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio6";
reg = <0x5d000 0x4>,
<0x5d010 0x4>,
<0x5d114 0x4>;
@@ -1414,7 +1404,6 @@
target-module@60000 { /* 0x48060000, ap 23 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c3";
reg = <0x60000 0x8>,
<0x60010 0x8>,
<0x60090 0x8>;
@@ -1446,7 +1435,6 @@
target-module@66000 { /* 0x48066000, ap 63 4c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart5";
reg = <0x66050 0x4>,
<0x66054 0x4>,
<0x66058 0x4>;
@@ -1476,7 +1464,6 @@
target-module@68000 { /* 0x48068000, ap 53 54.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart6";
reg = <0x68050 0x4>,
<0x68054 0x4>,
<0x68058 0x4>;
@@ -1506,7 +1493,6 @@
target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart1";
reg = <0x6a050 0x4>,
<0x6a054 0x4>,
<0x6a058 0x4>;
@@ -1536,7 +1522,6 @@
target-module@6c000 { /* 0x4806c000, ap 26 22.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart2";
reg = <0x6c050 0x4>,
<0x6c054 0x4>,
<0x6c058 0x4>;
@@ -1566,7 +1551,6 @@
target-module@6e000 { /* 0x4806e000, ap 28 44.1 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "uart4";
reg = <0x6e050 0x4>,
<0x6e054 0x4>,
<0x6e058 0x4>;
@@ -1596,7 +1580,6 @@
target-module@70000 { /* 0x48070000, ap 30 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c1";
reg = <0x70000 0x8>,
<0x70010 0x8>,
<0x70090 0x8>;
@@ -1628,7 +1611,6 @@
target-module@72000 { /* 0x48072000, ap 32 1c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c2";
reg = <0x72000 0x8>,
<0x72010 0x8>,
<0x72090 0x8>;
@@ -1668,7 +1650,6 @@
target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c4";
reg = <0x7a000 0x8>,
<0x7a010 0x8>,
<0x7a090 0x8>;
@@ -1700,7 +1681,6 @@
target-module@7c000 { /* 0x4807c000, ap 83 34.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "i2c5";
reg = <0x7c000 0x8>,
<0x7c010 0x8>,
<0x7c090 0x8>;
@@ -1732,7 +1712,6 @@
target-module@86000 { /* 0x48086000, ap 41 5e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer10";
reg = <0x86000 0x4>,
<0x86010 0x4>;
reg-names = "rev", "sysc";
@@ -1752,8 +1731,9 @@
timer10: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>,
+ <&sys_clkin>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
@@ -1761,7 +1741,6 @@
target-module@88000 { /* 0x48088000, ap 43 66.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer11";
reg = <0x88000 0x4>,
<0x88010 0x4>;
reg-names = "rev", "sysc";
@@ -1781,24 +1760,38 @@
timer11: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>,
+ <&sys_clkin>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};
- target-module@90000 { /* 0x48090000, ap 55 1a.0 */
- compatible = "ti,sysc";
- status = "disabled";
+ rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x91fe0 0x4>,
+ <0x91fe4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
+ clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x90000 0x2000>;
+
+ rng: rng@0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
target-module@98000 { /* 0x48098000, ap 47 08.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcspi1";
reg = <0x98000 0x4>,
<0x98010 0x4>;
reg-names = "rev", "sysc";
@@ -1837,7 +1830,6 @@
target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcspi2";
reg = <0x9a000 0x4>,
<0x9a010 0x4>;
reg-names = "rev", "sysc";
@@ -1871,7 +1863,6 @@
target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mmc1";
reg = <0x9c000 0x4>,
<0x9c010 0x4>;
reg-names = "rev", "sysc";
@@ -1921,6 +1912,36 @@
<0x00001000 0x000a5000 0x00001000>;
};
+ des_target: target-module@a5000 { /* 0x480a5000 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xa5030 0x4>,
+ <0xa5034 0x4>,
+ <0xa5038 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa5000 0x00001000>;
+ status = "disabled";
+
+ des: des@0 {
+ compatible = "ti,omap4-des";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 117>, <&sdma 116>;
+ dma-names = "tx", "rx";
+ };
+ };
+
target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
compatible = "ti,sysc";
status = "disabled";
@@ -1931,7 +1952,6 @@
target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mmc3";
reg = <0xad000 0x4>,
<0xad010 0x4>;
reg-names = "rev", "sysc";
@@ -1972,7 +1992,6 @@
target-module@b4000 { /* 0x480b4000, ap 65 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mmc2";
reg = <0xb4000 0x4>,
<0xb4010 0x4>;
reg-names = "rev", "sysc";
@@ -2005,7 +2024,6 @@
target-module@b8000 { /* 0x480b8000, ap 67 32.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcspi3";
reg = <0xb8000 0x4>,
<0xb8010 0x4>;
reg-names = "rev", "sysc";
@@ -2036,7 +2054,6 @@
target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mcspi4";
reg = <0xba000 0x4>,
<0xba010 0x4>;
reg-names = "rev", "sysc";
@@ -2067,7 +2084,6 @@
target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mmc4";
reg = <0xd1000 0x4>,
<0xd1010 0x4>;
reg-names = "rev", "sysc";
@@ -2100,7 +2116,6 @@
target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "mmc5";
reg = <0xd5000 0x4>,
<0xd5010 0x4>;
reg-names = "rev", "sysc";
@@ -2169,7 +2184,6 @@
target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4010 0x4>;
reg-names = "rev", "sysc";
@@ -2296,7 +2310,6 @@
target-module@0 { /* 0x4ae10000, ap 5 10.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "gpio1";
reg = <0x0 0x4>,
<0x10 0x4>,
<0x114 0x4>;
@@ -2331,7 +2344,6 @@
target-module@4000 { /* 0x4ae14000, ap 7 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "wd_timer2";
reg = <0x4000 0x4>,
<0x4010 0x4>,
<0x4014 0x4>;
@@ -2357,9 +2369,8 @@
};
};
- target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
+ timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>;
reg-names = "rev", "sysc";
@@ -2379,8 +2390,9 @@
timer1: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>;
- clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
- clock-names = "fck";
+ clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>,
+ <&sys_clkin>;
+ clock-names = "fck", "timer_sys_ck";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-alwon;
};
@@ -2388,7 +2400,6 @@
target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "kbd";
reg = <0xc000 0x4>,
<0xc010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 9441e9a..51d5fca 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
@@ -15,6 +15,26 @@
reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_memory_region: dsp-memory@95000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x95000000 0 0x800000>;
+ reusable;
+ status = "okay";
+ };
+
+ ipu_memory_region: ipu-memory@95800000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x95800000 0 0x3800000>;
+ reusable;
+ status = "okay";
+ };
+ };
+
aliases {
ethernet = ðernet;
};
@@ -198,3 +218,17 @@
&wlcore {
compatible = "ti,wl1837";
};
+
+&dsp {
+ status = "okay";
+ memory-region = <&dsp_memory_region>;
+ ti,timers = <&timer5>;
+ ti,watchdog-timers = <&timer6>;
+};
+
+&ipu {
+ status = "okay";
+ memory-region = <&ipu_memory_region>;
+ ti,timers = <&timer3>;
+ ti,watchdog-timers = <&timer9>, <&timer11>;
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3b56e99..530210d 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on "omap4.dtsi"
*/
@@ -36,6 +36,8 @@
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
+ rproc0 = &dsp;
+ rproc1 = &ipu;
};
cpus {
@@ -168,7 +170,7 @@
l4_abe: interconnect@40100000 {
};
- ocmcram: ocmcram@40300000 {
+ ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x20000>; /* 128k */
};
@@ -192,21 +194,56 @@
#gpio-cells = <2>;
};
- mmu_dsp: mmu@4a066000 {
- compatible = "ti,omap4-iommu";
- reg = <0x4a066000 0x100>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_dsp";
- #iommu-cells = <0>;
+ target-module@55082000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x55082000 0x4>,
+ <0x55082010 0x4>,
+ <0x55082014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_core 2>;
+ reset-names = "rstctrl";
+ ranges = <0x0 0x55082000 0x100>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ mmu_ipu: mmu@0 {
+ compatible = "ti,omap4-iommu";
+ reg = <0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <0>;
+ ti,iommu-bus-err-back;
+ };
};
- mmu_ipu: mmu@55082000 {
- compatible = "ti,omap4-iommu";
- reg = <0x55082000 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mmu_ipu";
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
+ dsp: dsp {
+ compatible = "ti,omap5-dsp";
+ ti,bootreg = <&scm_conf 0x304 0>;
+ iommus = <&mmu_dsp>;
+ resets = <&prm_dsp 0>;
+ clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
+ firmware-name = "omap5-dsp-fw.xe64T";
+ mboxes = <&mailbox &mbox_dsp>;
+ status = "disabled";
+ };
+
+ ipu: ipu@55020000 {
+ compatible = "ti,omap5-ipu";
+ reg = <0x55020000 0x10000>;
+ reg-names = "l2ram";
+ iommus = <&mmu_ipu>;
+ resets = <&prm_core 0>, <&prm_core 1>;
+ clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
+ firmware-name = "omap5-ipu-fw.xem4";
+ mboxes = <&mailbox &mbox_ipu>;
+ status = "disabled";
};
dmm@4e000000 {
@@ -240,6 +277,92 @@
hw-caps-temp-alert;
};
+ aes1_target: target-module@4b501000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b501080 0x4>,
+ <0x4b501084 0x4>,
+ <0x4b501088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b501000 0x1000>;
+
+ aes1: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 111>, <&sdma 110>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ aes2_target: target-module@4b701000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4b701080 0x4>,
+ <0x4b701084 0x4>,
+ <0x4b701088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b701000 0x1000>;
+
+ aes2: aes@0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 114>, <&sdma 113>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ sham_target: target-module@4b100000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x4b100100 0x4>,
+ <0x4b100110 0x4>,
+ <0x4b100114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
+ clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4b100000 0x1000>;
+
+ sham: sham@0 {
+ compatible = "ti,omap4-sham";
+ reg = <0 0x300>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 119>;
+ dma-names = "rx";
+ };
+ };
+
bandgap: bandgap@4a0021e0 {
reg = <0x4a0021e0 0xc
0x4a00232c 0xc
@@ -286,78 +409,187 @@
*/
};
- dss: dss@58000000 {
- compatible = "ti,omap5-dss";
- reg = <0x58000000 0x80>;
- status = "disabled";
- ti,hwmods = "dss_core";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
+ target-module@58000000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x58000000 4>,
+ <0x58000014 4>;
+ reg-names = "rev", "syss";
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0 0x58000000 0x1000000>;
- dispc@58001000 {
- compatible = "ti,omap5-dispc";
- reg = <0x58001000 0x1000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "dss_dispc";
+ dss: dss@0 {
+ compatible = "ti,omap5-dss";
+ reg = <0 0x80>;
+ status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
- };
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1000000>;
- rfbi: encoder@58002000 {
- compatible = "ti,omap5-rfbi";
- reg = <0x58002000 0x100>;
- status = "disabled";
- ti,hwmods = "dss_rfbi";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
- clock-names = "fck", "ick";
- };
+ target-module@1000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x1000 0x4>,
+ <0x1010 0x4>,
+ <0x1014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x1000>;
- dsi1: encoder@58004000 {
- compatible = "ti,omap5-dsi";
- reg = <0x58004000 0x200>,
- <0x58004200 0x40>,
- <0x58004300 0x40>;
- reg-names = "proto", "phy", "pll";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- ti,hwmods = "dss_dsi1";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
- clock-names = "fck", "sys_clk";
- };
+ dispc@0 {
+ compatible = "ti,omap5-dispc";
+ reg = <0 0x1000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ };
+ };
- dsi2: encoder@58005000 {
- compatible = "ti,omap5-dsi";
- reg = <0x58009000 0x200>,
- <0x58009200 0x40>,
- <0x58009300 0x40>;
- reg-names = "proto", "phy", "pll";
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- ti,hwmods = "dss_dsi2";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
- clock-names = "fck", "sys_clk";
- };
+ target-module@2000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2000 0x4>,
+ <0x2010 0x4>,
+ <0x2014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2000 0x1000>;
- hdmi: encoder@58060000 {
- compatible = "ti,omap5-hdmi";
- reg = <0x58040000 0x200>,
- <0x58040200 0x80>,
- <0x58040300 0x80>,
- <0x58060000 0x19000>;
- reg-names = "wp", "pll", "phy", "core";
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- ti,hwmods = "dss_hdmi";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
- clock-names = "fck", "sys_clk";
- dmas = <&sdma 76>;
- dma-names = "audio_tx";
+ rfbi: encoder@0 {
+ compatible = "ti,omap5-rfbi";
+ reg = <0 0x100>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
+ clock-names = "fck", "ick";
+ };
+ };
+
+ target-module@4000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4010 0x4>,
+ <0x4014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4000 0x1000>;
+
+ dsi1: encoder@0 {
+ compatible = "ti,omap5-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x40>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ };
+ };
+
+ target-module@9000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x9000 0x4>,
+ <0x9010 0x4>,
+ <0x9014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,syss-mask = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x9000 0x1000>;
+
+ dsi2: encoder@0 {
+ compatible = "ti,omap5-dsi";
+ reg = <0 0x200>,
+ <0x200 0x40>,
+ <0x300 0x40>;
+ reg-names = "proto", "phy", "pll";
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ };
+ };
+
+ target-module@40000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x40000 0x4>,
+ <0x40010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
+ clock-names = "fck", "dss_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x40000 0x40000>;
+
+ hdmi: encoder@0 {
+ compatible = "ti,omap5-hdmi";
+ reg = <0 0x200>,
+ <0x200 0x80>,
+ <0x300 0x80>,
+ <0x20000 0x19000>;
+ reg-names = "wp", "pll", "phy", "core";
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
+ clock-names = "fck", "sys_clk";
+ dmas = <&sdma 76>;
+ dma-names = "audio_tx";
+ };
+ };
};
};
@@ -441,3 +673,45 @@
#include "omap5-l4-abe.dtsi"
#include "omap54xx-clocks.dtsi"
+
+&prm {
+ prm_dsp: prm@400 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x400 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_abe: prm@500 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x500 0x100>;
+ #power-domain-cells = <0>;
+ };
+
+ prm_core: prm@700 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x700 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_iva: prm@1200 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1200 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm@1c00 {
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1c00 0x100>;
+ #reset-cells = <1>;
+ };
+};
+
+/* Preferred always-on timer for clockevent */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_32k_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 4791834..42f2c44 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -1125,11 +1125,17 @@
#size-cells = <1>;
ranges = <0 0x1000 0x200>;
- l4per_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
+ l4per_clkctrl: clock@20 {
+ compatible = "ti,clkctrl-l4per", "ti,clkctrl";
reg = <0x20 0x15c>;
#clock-cells = <2>;
};
+
+ l4sec_clkctrl: clock@1a0 {
+ compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
+ reg = <0x1a0 0x3c>;
+ #clock-cells = <2>;
+ };
};
dss_cm: dss_cm@1400 {
diff --git a/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi
new file mode 100644
index 0000000..05101a3
--- /dev/null
+++ b/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0xe0000>; // 896KB
+ label = "u-boot";
+ };
+
+ u-boot-env@e0000 {
+ reg = <0xe0000 0x20000>; // 128KB
+ label = "u-boot-env";
+ };
+
+ kernel@100000 {
+ reg = <0x100000 0x900000>; // 9MB
+ label = "kernel";
+ };
+
+ rofs@a00000 {
+ reg = <0xa00000 0x5600000>; // 86MB
+ label = "rofs";
+ };
+
+ rwfs@6000000 {
+ reg = <0x6000000 0x2000000>; // 32MB
+ label = "rwfs";
+ };
+};
diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts
new file mode 100644
index 0000000..c92f8bd
--- /dev/null
+++ b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Caninos Labrador Base Board
+ *
+ * Copyright (c) 2019-2020 Matheus Castello
+ */
+
+/dts-v1/;
+
+#include "owl-s500-labrador-v2.dtsi"
+
+/ {
+ model = "Caninos Labrador Core v2 on Labrador Base-M v1";
+ compatible = "caninos,labrador-base-m",
+ "caninos,labrador-v2", "actions,s500";
+
+ aliases {
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ uart3_clk: uart3-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <921600>;
+ #clock-cells = <0>;
+ };
+};
+
+&uart3 {
+ status = "okay";
+ clocks = <&uart3_clk>;
+};
diff --git a/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi b/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi
new file mode 100644
index 0000000..883ff2f
--- /dev/null
+++ b/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Caninos Labrador SoM V2
+ *
+ * Copyright (c) 2019-2020 Matheus Castello
+ */
+
+#include "owl-s500.dtsi"
+
+/ {
+ model = "Caninos Labrador Core V2.1";
+ compatible = "caninos,labrador-v2", "actions,s500";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000>;
+ };
+};
+
+&timer {
+ clocks = <&hosc>;
+};
diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
new file mode 100644
index 0000000..a2087e6
--- /dev/null
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Roseapple Pi
+ *
+ * Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "owl-s500.dtsi"
+
+/ {
+ compatible = "roseapplepi,roseapplepi", "actions,s500";
+ model = "Roseapple Pi";
+
+ aliases {
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x80000000>; /* 2GB */
+ };
+
+ uart2_clk: uart2-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <921600>;
+ #clock-cells = <0>;
+ };
+};
+
+&twd_timer {
+ status = "okay";
+};
+
+&timer {
+ clocks = <&hosc>;
+};
+
+&uart2 {
+ status = "okay";
+ clocks = <&uart2_clk>;
+};
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index 3fcc86d..5898879 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -163,7 +163,6 @@
reg = <0x20000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- reg-io-width = <4>;
banka: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-bank";
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index fa93155..0e85bb6 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -243,7 +243,6 @@
reg = <0x20000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- reg-io-width = <4>;
banka: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-bank";
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
index 4dfe0f1..c349fd3 100644
--- a/arch/arm/boot/dts/pm9g45.dts
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -15,7 +15,7 @@
bootargs = "console=ttyS0,115200";
};
- memory {
+ memory@70000000 {
reg = <0x70000000 0x8000000>;
};
@@ -68,6 +68,7 @@
&pinctrl_board_mmc
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
+ pinctrl-names = "default";
status = "okay";
slot@0 {
reg = <0>;
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 9c7b46b..7d3d93c 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -50,7 +50,7 @@
#size-cells = <1>;
ranges = <0x40000000 0x40000000 0x80000000>;
- l2-cache-controller@80040000 {
+ cache-controller@80040000 {
compatible = "arm,pl310-cache";
reg = <0x80040000 0x1000>;
interrupts = <59>;
diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
index 2ad40e3..8bade6b 100644
--- a/arch/arm/boot/dts/pxa168-aspenite.dts
+++ b/arch/arm/boot/dts/pxa168-aspenite.dts
@@ -18,18 +18,16 @@
memory {
reg = <0x00000000 0x04000000>;
};
+};
- soc {
- apb@d4000000 {
- uart1: uart@d4017000 {
- status = "okay";
- };
- twsi1: i2c@d4011000 {
- status = "okay";
- };
- rtc: rtc@d4010000 {
- status = "okay";
- };
- };
- };
+&uart1 {
+ status = "okay";
+};
+
+&twsi1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index 72f8cb6..4fe7735 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -55,27 +55,30 @@
interrupts = <13>;
};
- uart1: uart@d4017000 {
- compatible = "mrvl,mmp-uart";
+ uart1: serial@d4017000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4017000 0x1000>;
+ reg-shift = <2>;
interrupts = <27>;
clocks = <&soc_clocks PXA168_CLK_UART0>;
resets = <&soc_clocks PXA168_CLK_UART0>;
status = "disabled";
};
- uart2: uart@d4018000 {
- compatible = "mrvl,mmp-uart";
+ uart2: serial@d4018000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4018000 0x1000>;
+ reg-shift = <2>;
interrupts = <28>;
clocks = <&soc_clocks PXA168_CLK_UART1>;
resets = <&soc_clocks PXA168_CLK_UART1>;
status = "disabled";
};
- uart3: uart@d4026000 {
- compatible = "mrvl,mmp-uart";
+ uart3: serial@d4026000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4026000 0x1000>;
+ reg-shift = <2>;
interrupts = <29>;
clocks = <&soc_clocks PXA168_CLK_UART2>;
resets = <&soc_clocks PXA168_CLK_UART2>;
@@ -94,7 +97,7 @@
resets = <&soc_clocks PXA168_CLK_GPIO>;
interrupt-names = "gpio_mux";
interrupt-controller;
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
ranges;
gcb0: gpio@d4019000 {
@@ -116,6 +119,8 @@
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0xd4011000 0x1000>;
interrupts = <7>;
clocks = <&soc_clocks PXA168_CLK_TWSI0>;
@@ -126,6 +131,8 @@
twsi2: i2c@d4025000 {
compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0xd4025000 0x1000>;
interrupts = <58>;
clocks = <&soc_clocks PXA168_CLK_TWSI1>;
@@ -136,7 +143,7 @@
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0xd4010000 0x1000>;
- interrupts = <5 6>;
+ interrupts = <5>, <6>;
interrupt-names = "rtc 1Hz", "rtc alarm";
clocks = <&soc_clocks PXA168_CLK_RTC>;
resets = <&soc_clocks PXA168_CLK_RTC>;
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
index c237a0e..d196748 100644
--- a/arch/arm/boot/dts/pxa3xx.dtsi
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -170,7 +170,7 @@
clocks = <&clks CLK_GPIO>;
gpio-ranges = <&pinctrl 0 0 128>;
interrupt-names = "gpio0", "gpio1", "gpio_mux";
- interrupts = <8 9 10>;
+ interrupts = <8>, <9>, <10>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
index 0f899e6..ce76158 100644
--- a/arch/arm/boot/dts/pxa910-dkb.dts
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -18,155 +18,153 @@
memory {
reg = <0x00000000 0x10000000>;
};
+};
- soc {
- apb@d4000000 {
- uart1: uart@d4017000 {
- status = "okay";
+&uart1 {
+ status = "okay";
+};
+
+&twsi1 {
+ status = "okay";
+
+ pmic: 88pm860x@34 {
+ compatible = "marvell,88pm860x";
+ reg = <0x34>;
+ interrupts = <4>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ marvell,88pm860x-irq-read-clr;
+ marvell,88pm860x-slave-addr = <0x11>;
+
+ regulators {
+ BUCK1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
};
- twsi1: i2c@d4011000 {
- status = "okay";
-
- pmic: 88pm860x@34 {
- compatible = "marvell,88pm860x";
- reg = <0x34>;
- interrupts = <4>;
- interrupt-parent = <&intc>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- marvell,88pm860x-irq-read-clr;
- marvell,88pm860x-slave-addr = <0x11>;
-
- regulators {
- BUCK1 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
- regulator-always-on;
- };
- BUCK2 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
- regulator-always-on;
- };
- BUCK3 {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO1 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <2800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO2 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- LDO5 {
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO7 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO8 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2900000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO9 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO10 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- LDO12 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- LDO13 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- LDO14 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
- };
- rtc {
- marvell,88pm860x-vrtc = <1>;
- };
- touch {
- marvell,88pm860x-gpadc-prebias = <1>;
- marvell,88pm860x-gpadc-slot-cycle = <1>;
- marvell,88pm860x-tsi-prebias = <6>;
- marvell,88pm860x-pen-prebias = <16>;
- marvell,88pm860x-pen-prechg = <2>;
- marvell,88pm860x-resistor-X = <300>;
- };
- backlights {
- backlight-0 {
- marvell,88pm860x-iset = <4>;
- marvell,88pm860x-pwm = <3>;
- };
- backlight-2 {
- };
- };
- leds {
- led0-red {
- marvell,88pm860x-iset = <12>;
- };
- led0-green {
- marvell,88pm860x-iset = <12>;
- };
- led0-blue {
- marvell,88pm860x-iset = <12>;
- };
- };
- };
+ BUCK2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
+ regulator-always-on;
};
- rtc: rtc@d4010000 {
- status = "okay";
+ BUCK3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ LDO5 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO10 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ LDO12 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ LDO13 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ LDO14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ rtc {
+ marvell,88pm860x-vrtc = <1>;
+ };
+ touch {
+ marvell,88pm860x-gpadc-prebias = <1>;
+ marvell,88pm860x-gpadc-slot-cycle = <1>;
+ marvell,88pm860x-tsi-prebias = <6>;
+ marvell,88pm860x-pen-prebias = <16>;
+ marvell,88pm860x-pen-prechg = <2>;
+ marvell,88pm860x-resistor-X = <300>;
+ };
+ backlights {
+ backlight-0 {
+ marvell,88pm860x-iset = <4>;
+ marvell,88pm860x-pwm = <3>;
+ };
+ backlight-2 {
+ };
+ };
+ leds {
+ led0-red {
+ marvell,88pm860x-iset = <12>;
+ };
+ led0-green {
+ marvell,88pm860x-iset = <12>;
+ };
+ led0-blue {
+ marvell,88pm860x-iset = <12>;
};
};
};
};
+
+&rtc {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index b3d6182..352a393 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -67,27 +67,30 @@
status = "disabled";
};
- uart1: uart@d4017000 {
- compatible = "mrvl,mmp-uart";
+ uart1: serial@d4017000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4017000 0x1000>;
+ reg-shift = <2>;
interrupts = <27>;
clocks = <&soc_clocks PXA910_CLK_UART0>;
resets = <&soc_clocks PXA910_CLK_UART0>;
status = "disabled";
};
- uart2: uart@d4018000 {
- compatible = "mrvl,mmp-uart";
+ uart2: serial@d4018000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4018000 0x1000>;
+ reg-shift = <2>;
interrupts = <28>;
clocks = <&soc_clocks PXA910_CLK_UART1>;
resets = <&soc_clocks PXA910_CLK_UART1>;
status = "disabled";
};
- uart3: uart@d4036000 {
- compatible = "mrvl,mmp-uart";
+ uart3: serial@d4036000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4036000 0x1000>;
+ reg-shift = <2>;
interrupts = <59>;
clocks = <&soc_clocks PXA910_CLK_UART2>;
resets = <&soc_clocks PXA910_CLK_UART2>;
@@ -106,7 +109,7 @@
clocks = <&soc_clocks PXA910_CLK_GPIO>;
resets = <&soc_clocks PXA910_CLK_GPIO>;
interrupt-controller;
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
ranges;
gcb0: gpio@d4019000 {
@@ -152,7 +155,7 @@
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0xd4010000 0x1000>;
- interrupts = <5 6>;
+ interrupts = <5>, <6>;
interrupt-names = "rtc 1Hz", "rtc alarm";
clocks = <&soc_clocks PXA910_CLK_RTC>;
resets = <&soc_clocks PXA910_CLK_RTC>;
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 2b075e2..72c4a9f 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -198,7 +198,7 @@
clock-frequency = <19200000>;
};
- pxo_board {
+ pxo_board: pxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
@@ -350,6 +350,7 @@
reg = <0x800000 0x4000>;
gpio-controller;
+ gpio-ranges = <&tlmm_pinmux 0 0 90>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -1147,7 +1148,7 @@
};
gpu: adreno-3xx@4300000 {
- compatible = "qcom,adreno-3xx";
+ compatible = "qcom,adreno-320.2", "qcom,adreno";
reg = <0x04300000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
@@ -1162,7 +1163,6 @@
<&mmcc GFX3D_AHB_CLK>,
<&mmcc GFX3D_AXI_CLK>,
<&mmcc MMSS_IMEM_AHB_CLK>;
- qcom,chipid = <0x03020002>;
iommus = <&gfx3d 0
&gfx3d 1
@@ -1305,7 +1305,7 @@
reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
clock-names = "iface_clk", "ref";
clocks = <&mmcc DSI_M_AHB_CLK>,
- <&cxo_board>;
+ <&pxo_board>;
};
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 0a0fb14..bf6a035 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
#include <dt-bindings/gpio/gpio.h>
@@ -184,7 +185,7 @@
cpu-pmu {
compatible = "qcom,krait-pmu";
- interrupts = <1 7 0xf04>;
+ interrupts = <GIC_PPI 7 0xf04>;
};
clocks {
@@ -203,10 +204,10 @@
timer {
compatible = "arm,armv7-timer";
- interrupts = <1 2 0xf08>,
- <1 3 0xf08>,
- <1 4 0xf08>,
- <1 1 0xf08>;
+ interrupts = <GIC_PPI 2 0xf08>,
+ <GIC_PPI 3 0xf08>,
+ <GIC_PPI 4 0xf08>,
+ <GIC_PPI 1 0xf08>;
clock-frequency = <19200000>;
};
@@ -253,12 +254,13 @@
tsens: thermal-sensor@fc4a8000 {
compatible = "qcom,msm8974-tsens";
- reg = <0xfc4a8000 0x2000>;
+ reg = <0xfc4a9000 0x1000>, /* TM */
+ <0xfc4a8000 0x1000>; /* SROT */
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
nvmem-cell-names = "calib", "calib_backup";
+ #qcom,sensors = <11>;
#thermal-sensor-cells = <1>;
};
-
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -269,50 +271,50 @@
frame@f9021000 {
frame-number = <0>;
- interrupts = <0 8 0x4>,
- <0 7 0x4>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9021000 0x1000>,
<0xf9022000 0x1000>;
};
frame@f9023000 {
frame-number = <1>;
- interrupts = <0 9 0x4>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9023000 0x1000>;
status = "disabled";
};
frame@f9024000 {
frame-number = <2>;
- interrupts = <0 10 0x4>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9024000 0x1000>;
status = "disabled";
};
frame@f9025000 {
frame-number = <3>;
- interrupts = <0 11 0x4>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9025000 0x1000>;
status = "disabled";
};
frame@f9026000 {
frame-number = <4>;
- interrupts = <0 12 0x4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9026000 0x1000>;
status = "disabled";
};
frame@f9027000 {
frame-number = <5>;
- interrupts = <0 13 0x4>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9027000 0x1000>;
status = "disabled";
};
frame@f9028000 {
frame-number = <6>;
- interrupts = <0 14 0x4>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9028000 0x1000>;
status = "disabled";
};
@@ -401,16 +403,17 @@
compatible = "qcom,apq8084-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
+ gpio-ranges = <&tlmm 0 0 147>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <0 208 0>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
blsp2_uart2: serial@f995e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995e000 0x1000>;
- interrupts = <0 114 0x0>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -420,7 +423,7 @@
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
- interrupts = <0 123 0>, <0 138 0>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
@@ -433,7 +436,7 @@
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
- interrupts = <0 125 0>, <0 221 0>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>,
@@ -449,7 +452,7 @@
<0xfc4cb000 0x1000>,
<0xfc4ca000 0x1000>;
interrupt-names = "periph_irq";
- interrupts = <0 190 0>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
@@ -463,7 +466,7 @@
compatible = "qcom,smd";
rpm {
- interrupts = <0 168 1>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 56f5159..74d8e2c 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -102,6 +102,7 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
+ qcom,saw = <&saw_l2>;
};
};
@@ -165,6 +166,7 @@
<1 4 0xf08>,
<1 1 0xf08>;
clock-frequency = <48000000>;
+ always-on;
};
soc {
@@ -200,12 +202,25 @@
compatible = "qcom,ipq4019-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
+ gpio-ranges = <&tlmm 0 0 100>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
+ sdhci: sdhci@7824900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x7824900 0x11c>, <0x7824000 0x800>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ bus-width = <8>;
+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_DCD_XO_CLK>;
+ clock-names = "core", "iface", "xo";
+ status = "disabled";
+ };
+
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x23000>;
@@ -341,6 +356,12 @@
regulator;
};
+ saw_l2: regulator@b012000 {
+ compatible = "qcom,saw2";
+ reg = <0xb012000 0x1000>;
+ regulator;
+ };
+
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
@@ -556,5 +577,33 @@
"legacy";
status = "disabled";
};
+
+ mdio: mdio@90000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,ipq4019-mdio";
+ reg = <0x90000 0x64>;
+ status = "disabled";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+
+ ethphy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+
+ ethphy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
new file mode 100644
index 0000000..33545cf
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-ipq8064.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "MikroTik RB3011UiAS-RM";
+ compatible = "mikrotik,rb3011";
+
+ aliases {
+ serial0 = &gsbi7_serial;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac3;
+ mdio-gpio0 = &mdio0;
+ mdio-gpio1 = &mdio1;
+ };
+
+ chosen {
+ bootargs = "loglevel=8 console=ttyMSM0,115200";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@42000000 {
+ reg = <0x42000000 0x3e000000>;
+ device_type = "memory";
+ };
+
+ mdio0: mdio-0 {
+ status = "okay";
+ compatible = "virtual,mdio-gpio";
+ gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
+ <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-0 = <&mdio0_pins>;
+ pinctrl-names = "default";
+
+ switch0: switch@10 {
+ compatible = "qca,qca8337";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsa,member = <0 0>;
+
+ pinctrl-0 = <&sw0_reset_pin>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
+ reg = <0x10>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0cpu: port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "sw1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "sw2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "sw3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "sw4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "sw5";
+ };
+ };
+ };
+ };
+
+ mdio1: mdio-1 {
+ status = "okay";
+ compatible = "virtual,mdio-gpio";
+ gpios = <&qcom_pinmux 11 GPIO_ACTIVE_HIGH>,
+ <&qcom_pinmux 10 GPIO_ACTIVE_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-0 = <&mdio1_pins>;
+ pinctrl-names = "default";
+
+ switch1: switch@14 {
+ compatible = "qca,qca8337";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsa,member = <1 0>;
+
+ pinctrl-0 = <&sw1_reset_pin>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&qcom_pinmux 17 GPIO_ACTIVE_LOW>;
+ reg = <0x10>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch1cpu: port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&gmac3>;
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "sw6";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "sw7";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "sw8";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "sw9";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "sw10";
+ };
+ };
+ };
+ };
+
+ soc {
+ gsbi5: gsbi@1a200000 {
+ qcom,mode = <GSBI_PROT_SPI>;
+ status = "okay";
+
+ spi4: spi@1a280000 {
+ status = "okay";
+ spi-max-frequency = <50000000>;
+
+ pinctrl-0 = <&spi_pins>;
+ pinctrl-names = "default";
+
+ cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
+
+ norflash: s25fl016k@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "RouterBoot";
+ reg = <0x0 0x40000>;
+ };
+ };
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&buttons_pins>;
+ pinctrl-names = "default";
+
+ button@1 {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ debounce-interval = <60>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&leds_pins>;
+ pinctrl-names = "default";
+
+ led@7 {
+ label = "rb3011:green:user";
+ gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ };
+};
+
+&gmac0 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ qcom,id = <0>;
+ phy-handle = <&switch0cpu>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&gmac3 {
+ status = "okay";
+
+ phy-mode = "sgmii";
+ qcom,id = <3>;
+ phy-handle = <&switch1cpu>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&gsbi7 {
+ status = "okay";
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+};
+
+&gsbi7_serial {
+ status = "okay";
+};
+
+&qcom_pinmux {
+ buttons_pins: buttons_pins {
+ mux {
+ pins = "gpio66";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ leds_pins: leds_pins {
+ mux {
+ pins = "gpio33";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ mdio0_pins: mdio0_pins {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ mdio1_pins: mdio1_pins {
+ mux {
+ pins = "gpio10", "gpio11";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ sw0_reset_pin: sw0_reset_pin {
+ mux {
+ pins = "gpio16";
+ drive-strength = <16>;
+ function = "gpio";
+ bias-disable;
+ input-disable;
+ };
+ };
+
+ sw1_reset_pin: sw1_reset_pin {
+ mux {
+ pins = "gpio17";
+ drive-strength = <16>;
+ function = "gpio";
+ bias-disable;
+ input-disable;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 16c0da9..c514814 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -93,6 +93,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq806x", "qcom,scm";
+ };
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -119,6 +125,7 @@
reg = <0x800000 0x4000>;
gpio-controller;
+ gpio-ranges = <&qcom_pinmux 0 0 69>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -418,6 +425,13 @@
qcom,controller-type = "pmic-arbiter";
};
+ qfprom: qfprom@700000 {
+ compatible = "qcom,qfprom";
+ reg = <0x00700000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
gcc: clock-controller@900000 {
compatible = "qcom,gcc-ipq8064";
reg = <0x00900000 0x4000>;
@@ -590,6 +604,114 @@
perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
};
+ nss_common: syscon@03000000 {
+ compatible = "syscon";
+ reg = <0x03000000 0x0000FFFF>;
+ };
+
+ qsgmii_csr: syscon@1bb00000 {
+ compatible = "syscon";
+ reg = <0x1bb00000 0x000001FF>;
+ };
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <7>;
+ snps,rd_osr_lmt = <7>;
+ snps,blen = <16 0 0 0 0 0 0>;
+ };
+
+ gmac0: ethernet@37000000 {
+ device_type = "network";
+ compatible = "qcom,ipq806x-gmac";
+ reg = <0x37000000 0x200000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
+ qcom,nss-common = <&nss_common>;
+ qcom,qsgmii-csr = <&qsgmii_csr>;
+
+ clocks = <&gcc GMAC_CORE1_CLK>;
+ clock-names = "stmmaceth";
+
+ resets = <&gcc GMAC_CORE1_RESET>;
+ reset-names = "stmmaceth";
+
+ status = "disabled";
+ };
+
+ gmac1: ethernet@37200000 {
+ device_type = "network";
+ compatible = "qcom,ipq806x-gmac";
+ reg = <0x37200000 0x200000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
+ qcom,nss-common = <&nss_common>;
+ qcom,qsgmii-csr = <&qsgmii_csr>;
+
+ clocks = <&gcc GMAC_CORE2_CLK>;
+ clock-names = "stmmaceth";
+
+ resets = <&gcc GMAC_CORE2_RESET>;
+ reset-names = "stmmaceth";
+
+ status = "disabled";
+ };
+
+ gmac2: ethernet@37400000 {
+ device_type = "network";
+ compatible = "qcom,ipq806x-gmac";
+ reg = <0x37400000 0x200000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
+ qcom,nss-common = <&nss_common>;
+ qcom,qsgmii-csr = <&qsgmii_csr>;
+
+ clocks = <&gcc GMAC_CORE3_CLK>;
+ clock-names = "stmmaceth";
+
+ resets = <&gcc GMAC_CORE3_RESET>;
+ reset-names = "stmmaceth";
+
+ status = "disabled";
+ };
+
+ gmac3: ethernet@37600000 {
+ device_type = "network";
+ compatible = "qcom,ipq806x-gmac";
+ reg = <0x37600000 0x200000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
+ qcom,nss-common = <&nss_common>;
+ qcom,qsgmii-csr = <&qsgmii_csr>;
+
+ clocks = <&gcc GMAC_CORE4_CLK>;
+ clock-names = "stmmaceth";
+
+ resets = <&gcc GMAC_CORE4_RESET>;
+ reset-names = "stmmaceth";
+
+ status = "disabled";
+ };
+
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
index 26160c3..942e3a2 100644
--- a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
+++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
@@ -143,7 +143,7 @@
compatible = "smsc,usb3503a";
reg = <0x8>;
connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>;
- intn-gpios = <&gpioext2 0 GPIO_ACTIVE_LOW>;
+ intn-gpios = <&gpioext2 0 GPIO_ACTIVE_HIGH>;
initial-mode = <1>;
};
};
diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
index 356e953..dda2cee 100644
--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -98,7 +98,7 @@
ranges;
compatible = "simple-bus";
- L2: l2-cache@2040000 {
+ L2: cache-controller@2040000 {
compatible = "arm,pl310-cache";
reg = <0x02040000 0x1000>;
arm,data-latency = <2 2 0>;
@@ -128,6 +128,7 @@
msmgpio: pinctrl@800000 {
compatible = "qcom,mdm9615-pinctrl";
gpio-controller;
+ gpio-ranges = <&msmgpio 0 0 88>;
#gpio-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index ec5cbc4..480fc08 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -115,6 +115,7 @@
reg = <0x800000 0x4000>;
gpio-controller;
+ gpio-ranges = <&tlmm 0 0 173>;
#gpio-cells = <2>;
interrupts = <0 16 0x4>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index f2aeacc..172ea3c 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -107,6 +107,7 @@
msmgpio: pinctrl@800000 {
compatible = "qcom,msm8960-pinctrl";
gpio-controller;
+ gpio-ranges = <&msmgpio 0 0 152>;
#gpio-cells = <2>;
interrupts = <0 16 0x4>;
interrupt-controller;
diff --git a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts
index bf402ae..d2d4877 100644
--- a/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts
@@ -221,6 +221,8 @@
regulator-max-microvolt = <2950000>;
regulator-boot-on;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
};
l21 {
@@ -257,6 +259,25 @@
status = "ok";
};
+ remoteproc@fb21b000 {
+ status = "ok";
+
+ vddmx-supply = <&pm8841_s1>;
+ vddcx-supply = <&pm8841_s2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcnss_pin_a>;
+
+ smd-edge {
+ qcom,remote-pid = <4>;
+ label = "pronto";
+
+ wcnss {
+ status = "ok";
+ };
+ };
+ };
+
pinctrl@fd510000 {
sdhc1_pin_a: sdhc1-pin-active {
clk {
@@ -272,14 +293,6 @@
};
};
- sdhc2_cd_pin_a: sdhc2-cd-pin-active {
- pins = "gpio62";
- function = "gpio";
-
- drive-strength = <2>;
- bias-disable;
- };
-
sdhc2_pin_a: sdhc2-pin-active {
clk {
pins = "sdc2_clk";
@@ -293,6 +306,32 @@
bias-pull-up;
};
};
+
+ wcnss_pin_a: wcnss-pin-active {
+ wlan {
+ pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
+ function = "wlan";
+
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ bt {
+ pins = "gpio35", "gpio43", "gpio44";
+ function = "bt";
+
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ fm {
+ pins = "gpio41", "gpio42";
+ function = "fm";
+
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
};
sdhci@f9824900 {
@@ -317,7 +356,7 @@
bus-width = <4>;
pinctrl-names = "default";
- pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>;
+ pinctrl-0 = <&sdhc2_pin_a>;
};
usb@f9a55000 {
@@ -344,6 +383,16 @@
};
};
};
+
+ imem@fe805000 {
+ status = "okay";
+
+ reboot-mode {
+ mode-normal = <0x77665501>;
+ mode-bootloader = <0x77665500>;
+ mode-recovery = <0x77665502>;
+ };
+ };
};
&spmi_bus {
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
index 3487daf..32b474b 100644
--- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -12,6 +12,7 @@
aliases {
serial0 = &blsp1_uart1;
+ serial1 = &blsp2_uart10;
};
chosen {
@@ -355,6 +356,57 @@
bias-disable;
};
};
+
+ bt_pin: bt {
+ hostwake {
+ pins = "gpio42";
+ function = "gpio";
+ };
+
+ devwake {
+ pins = "gpio62";
+ function = "gpio";
+ };
+
+ shutdown {
+ pins = "gpio41";
+ function = "gpio";
+ };
+ };
+
+ blsp2_uart10_pin_a: blsp2-uart10-pin-active {
+ tx {
+ pins = "gpio53";
+ function = "blsp_uart10";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio54";
+ function = "blsp_uart10";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cts {
+ pins = "gpio55";
+ function = "blsp_uart10";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ rts {
+ pins = "gpio56";
+ function = "blsp_uart10";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
};
sdhci@f9824900 {
@@ -418,6 +470,25 @@
};
};
+ serial@f9960000 {
+ status = "ok";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp2_uart10_pin_a>;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_pin>;
+
+ host-wakeup-gpios = <&msmgpio 42 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&msmgpio 62 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&msmgpio 41 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
i2c@f9967000 {
status = "ok";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
index eaa1001..d4dc982 100644
--- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
@@ -1,7 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-msm8974pro.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
+#include "qcom-pma8084.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "Samsung Galaxy S5";
@@ -14,6 +16,194 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ smd {
+ rpm {
+ rpm_requests {
+ pma8084-regulators {
+ compatible = "qcom,rpm-pma8084-regulators";
+ status = "okay";
+
+ pma8084_s1: s1 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pma8084_s2: s2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pma8084_s3: s3 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pma8084_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_s5: s5 {
+ regulator-min-microvolt = <2150000>;
+ regulator-max-microvolt = <2150000>;
+ };
+
+ pma8084_s6: s6 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pma8084_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pma8084_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pma8084_l3: l3 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pma8084_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pma8084_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l9: l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pma8084_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pma8084_l11: l11 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pma8084_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l13: l13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pma8084_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pma8084_l15: l15 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pma8084_l16: l16 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ pma8084_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pma8084_l18: l18 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pma8084_l19: l19 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pma8084_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+
+ regulator-allow-set-load;
+ regulator-system-load = <200000>;
+ };
+
+ pma8084_l21: l21 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pma8084_l22: l22 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pma8084_l23: l23 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pma8084_l24: l24 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pma8084_l25: l25 {
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ pma8084_l26: l26 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pma8084_l27: l27 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pma8084_lvs1: lvs1 {};
+ pma8084_lvs2: lvs2 {};
+ pma8084_lvs3: lvs3 {};
+ pma8084_lvs4: lvs4 {};
+
+ pma8084_5vs1: 5vs1 {};
+ };
+ };
+ };
+ };
+
+ /delete-node/ vreg-boost;
};
&soc {
@@ -21,4 +211,215 @@
status = "ok";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pin_a>;
+
+ volume-down {
+ label = "volume_down";
+ gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <15>;
+ };
+
+ home-key {
+ label = "home_key";
+ gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_HOMEPAGE>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+
+ volume-up {
+ label = "volume_up";
+ gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ pinctrl@fd510000 {
+ sdhc1_pin_a: sdhc1-pin-active {
+ clk {
+ pins = "sdc1_clk";
+ drive-strength = <4>;
+ bias-disable;
+ };
+
+ cmd-data {
+ pins = "sdc1_cmd", "sdc1_data";
+ drive-strength = <4>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ sdhci@f9824900 {
+ status = "ok";
+
+ vmmc-supply = <&pma8084_l20>;
+ vqmmc-supply = <&pma8084_s4>;
+
+ bus-width = <8>;
+ non-removable;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhc1_pin_a>;
+ };
+
+ usb@f9a55000 {
+ status = "ok";
+
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
+ /*extcon = <&smbb>, <&usb_id>;*/
+ /*vbus-supply = <&chg_otg>;*/
+
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+
+ ulpi {
+ phy@a {
+ status = "ok";
+
+ v1p8-supply = <&pma8084_l6>;
+ v3p3-supply = <&pma8084_l24>;
+
+ /*extcon = <&smbb>;*/
+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
+ };
+ };
+ };
+
+ pinctrl@fd510000 {
+ i2c6_pins: i2c6 {
+ mux {
+ pins = "gpio29", "gpio30";
+ function = "blsp_i2c6";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ i2c@f9928000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+
+ pmic@60 {
+ reg = <0x60>;
+ compatible = "maxim,max77826";
+
+ regulators {
+ max77826_ldo1: LDO1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ max77826_ldo2: LDO2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ max77826_ldo3: LDO3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ max77826_ldo4: LDO4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ max77826_ldo5: LDO5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ max77826_ldo6: LDO6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max77826_ldo7: LDO7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ max77826_ldo8: LDO8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max77826_ldo9: LDO9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ max77826_ldo10: LDO10 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ max77826_ldo11: LDO11 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ max77826_ldo12: LDO12 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max77826_ldo13: LDO13 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max77826_ldo14: LDO14 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ max77826_ldo15: LDO15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ max77826_buck: BUCK {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ max77826_buckboost: BUCKBOOST {
+ regulator-min-microvolt = <3400000>;
+ regulator-max-microvolt = <3400000>;
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pma8084@0 {
+ gpios@c000 {
+ gpio_keys_pin_a: gpio-keys-active {
+ pins = "gpio2", "gpio3", "gpio5";
+ function = "normal";
+
+ bias-pull-up;
+ power-source = <PMA8084_GPIO_S4>;
+ };
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
index 450b832..611bae9 100644
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
@@ -260,6 +260,31 @@
};
&soc {
+ usb@f9a55000 {
+ status = "ok";
+
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
+ extcon = <&smbb>, <&usb_id>;
+ vbus-supply = <&chg_otg>;
+
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+
+ ulpi {
+ phy@a {
+ status = "ok";
+
+ v1p8-supply = <&pm8941_l6>;
+ v3p3-supply = <&pm8941_l24>;
+
+ extcon = <&smbb>;
+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
+ };
+ };
+ };
+
sdhci@f9824900 {
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 369e58f..5f7426f 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
+#include <dt-bindings/interconnect/qcom,msm8974.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
@@ -20,17 +21,17 @@
#size-cells = <1>;
ranges;
- mpss@8000000 {
+ mpss_region: mpss@8000000 {
reg = <0x08000000 0x5100000>;
no-map;
};
- mba@d100000 {
+ mba_region: mba@d100000 {
reg = <0x0d100000 0x100000>;
no-map;
};
- reserved@d200000 {
+ wcnss_region: wcnss@d200000 {
reg = <0x0d200000 0xa00000>;
no-map;
};
@@ -61,8 +62,11 @@
};
rmtfs@fd80000 {
+ compatible = "qcom,rmtfs-mem";
reg = <0x0fd80000 0x180000>;
no-map;
+
+ qcom,client-id = <1>;
};
};
@@ -217,6 +221,96 @@
};
};
};
+
+ q6-dsp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 1>;
+
+ trips {
+ q6_dsp_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ modemtx-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 2>;
+
+ trips {
+ modemtx_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 3>;
+
+ trips {
+ video_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ wlan-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 4>;
+
+ trips {
+ wlan_alert0: trip-point0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ gpu-thermal-top {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 9>;
+
+ trips {
+ gpu1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ gpu-thermal-bottom {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 10>;
+
+ trips {
+ gpu2_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
};
cpu-pmu {
@@ -266,6 +360,15 @@
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
+
+ smd-edge {
+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 8>;
+ qcom,smd-edge = <1>;
+
+ label = "lpass";
+ };
};
smem {
@@ -441,6 +544,8 @@
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
nvmem-cell-names = "calib", "calib_backup";
#qcom,sensors = <11>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
#thermal-sensor-cells = <1>;
};
@@ -610,6 +715,15 @@
status = "disabled";
};
+ blsp2_uart10: serial@f9960000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf9960000 0x1000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
sdhci@f9824900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
@@ -703,10 +817,124 @@
clock-names = "core";
};
+ remoteproc@fc880000 {
+ compatible = "qcom,msm8974-mss-pil";
+ reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
+ reg-names = "qdsp6", "rmb";
+
+ interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+ <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>,
+ <&xo_board>;
+ clock-names = "iface", "bus", "mem", "xo";
+
+ resets = <&gcc GCC_MSS_RESTART>;
+ reset-names = "mss_restart";
+
+ cx-supply = <&pm8841_s2>;
+ mss-supply = <&pm8841_s3>;
+ mx-supply = <&pm8841_s1>;
+ pll-supply = <&pm8941_l12>;
+
+ qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ mba {
+ memory-region = <&mba_region>;
+ };
+
+ mpss {
+ memory-region = <&mpss_region>;
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 12>;
+ qcom,smd-edge = <0>;
+
+ label = "modem";
+ };
+ };
+
+ pronto: remoteproc@fb21b000 {
+ compatible = "qcom,pronto-v2-pil", "qcom,pronto";
+ reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
+ reg-names = "ccu", "dxe", "pmu";
+
+ memory-region = <&wcnss_region>;
+
+ interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+ vddpx-supply = <&pm8941_s3>;
+
+ qcom,smem-states = <&wcnss_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ iris {
+ compatible = "qcom,wcn3680";
+
+ clocks = <&rpmcc RPM_SMD_CXO_A2>;
+ clock-names = "xo";
+
+ vddxo-supply = <&pm8941_l6>;
+ vddrfa-supply = <&pm8941_l11>;
+ vddpa-supply = <&pm8941_l19>;
+ vdddig-supply = <&pm8941_s3>;
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 17>;
+ qcom,smd-edge = <6>;
+
+ wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+ status = "disabled";
+
+ qcom,mmio = <&pronto>;
+
+ bt {
+ compatible = "qcom,wcnss-bt";
+ };
+
+ wifi {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+ };
+ };
+ };
+ };
+
msmgpio: pinctrl@fd510000 {
compatible = "qcom,msm8974-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
+ gpio-ranges = <&msmgpio 0 0 146>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -746,6 +974,17 @@
#size-cells = <0>;
};
+ blsp_i2c6: i2c@f9928000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9928000 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
blsp_i2c8: i2c@f9964000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
@@ -1087,6 +1326,79 @@
};
};
+ ocmem@fdd00000 {
+ compatible = "qcom,msm8974-ocmem";
+ reg = <0xfdd00000 0x2000>,
+ <0xfec00000 0x180000>;
+ reg-names = "ctrl",
+ "mem";
+ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
+ <&mmcc OCMEMCX_OCMEMNOC_CLK>;
+ clock-names = "core",
+ "iface";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gmu_sram: gmu-sram@0 {
+ reg = <0x0 0x100000>;
+ };
+ };
+
+ bimc: interconnect@fc380000 {
+ reg = <0xfc380000 0x6a000>;
+ compatible = "qcom,msm8974-bimc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+ <&rpmcc RPM_SMD_BIMC_A_CLK>;
+ };
+
+ snoc: interconnect@fc460000 {
+ reg = <0xfc460000 0x4000>;
+ compatible = "qcom,msm8974-snoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+ <&rpmcc RPM_SMD_SNOC_A_CLK>;
+ };
+
+ pnoc: interconnect@fc468000 {
+ reg = <0xfc468000 0x4000>;
+ compatible = "qcom,msm8974-pnoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
+ <&rpmcc RPM_SMD_PNOC_A_CLK>;
+ };
+
+ ocmemnoc: interconnect@fc470000 {
+ reg = <0xfc470000 0x4000>;
+ compatible = "qcom,msm8974-ocmemnoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
+ <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
+ };
+
+ mmssnoc: interconnect@fc478000 {
+ reg = <0xfc478000 0x4000>;
+ compatible = "qcom,msm8974-mmssnoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&mmcc MMSS_S0_AXI_CLK>,
+ <&mmcc MMSS_S0_AXI_CLK>;
+ };
+
+ cnoc: interconnect@fc480000 {
+ reg = <0xfc480000 0x4000>;
+ compatible = "qcom,msm8974-cnoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
+ <&rpmcc RPM_SMD_CNOC_A_CLK>;
+ };
+
mdss: mdss@fd900000 {
status = "disabled";
@@ -1133,6 +1445,9 @@
"core",
"vsync";
+ interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
+ interconnect-names = "mdp0-mem";
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1213,8 +1528,19 @@
#phy-cells = <0>;
qcom,dsi-phy-index = <0>;
- clocks = <&mmcc MDSS_AHB_CLK>;
- clock-names = "iface";
+ clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
+ clock-names = "iface", "ref";
+ };
+ };
+
+ imem@fe805000 {
+ status = "disabled";
+ compatible = "syscon", "simple-mfd";
+ reg = <0xfe805000 0x1000>;
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x65c>;
};
};
};
@@ -1222,20 +1548,6 @@
smd {
compatible = "qcom,smd";
- adsp {
- interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
-
- qcom,ipc = <&apcs 8 8>;
- qcom,smd-edge = <1>;
- };
-
- modem {
- interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
-
- qcom,ipc = <&apcs 8 12>;
- qcom,smd-edge = <0>;
- };
-
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi
index f198480..c1f2012 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -178,6 +178,16 @@
qcom,vs-soft-start-strength = <0>;
regulator-initial-mode = <1>;
};
+
+ pm8941_5vs2: 5vs2 {
+ regulator-enable-ramp-delay = <1000>;
+ regulator-pull-down;
+ regulator-over-current-protection;
+ qcom,ocp-max-retries = <10>;
+ qcom,ocp-retry-delay = <30>;
+ qcom,vs-soft-start-strength = <0>;
+ regulator-initial-mode = <1>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
index fe1a4aa..2562cc9 100644
--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
+++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
@@ -41,6 +41,9 @@
bank-width = <4>;
device-width = <1>;
+ clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
+ power-domains = <&cpg_clocks>;
+
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index d03dcd9..45cf75b 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -313,9 +313,9 @@
mmcif: mmc@e804c800 {
compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
reg = <0xe804c800 0x80>;
- interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
power-domains = <&cpg_clocks>;
reg-io-width = <4>;
@@ -323,12 +323,12 @@
status = "disabled";
};
- sdhi0: sd@e804e000 {
+ sdhi0: mmc@e804e000 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e000 0x100>;
- interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>;
@@ -339,12 +339,12 @@
status = "disabled";
};
- sdhi1: sd@e804e800 {
+ sdhi1: mmc@e804e800 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e800 0x100>;
- interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>;
@@ -467,11 +467,12 @@
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0438 4>;
- clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
+ clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
clock-indices = <
R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
+ R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
>;
- clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
+ clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
};
mstp10_clks: mstp10_clks@fcfe043c {
@@ -498,7 +499,7 @@
clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
};
- pinctrl: pin-controller@fcfe3000 {
+ pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 72b7977..85c0399 100644
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -304,7 +304,6 @@
reg = <0xe803b000 0x30>;
interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD 36>;
- clock-names = "ostm0";
power-domains = <&cpg>;
status = "disabled";
};
@@ -314,7 +313,6 @@
reg = <0xe803c000 0x30>;
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD 35>;
- clock-names = "ostm1";
power-domains = <&cpg>;
status = "disabled";
};
@@ -324,7 +322,6 @@
reg = <0xe803d000 0x30>;
interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD 34>;
- clock-names = "ostm2";
power-domains = <&cpg>;
status = "disabled";
};
@@ -419,7 +416,7 @@
status = "disabled";
};
- sdhi0: sd@e8228000 {
+ sdhi0: mmc@e8228000 {
compatible = "renesas,sdhi-r7s9210";
reg = <0xe8228000 0x8c0>;
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
@@ -431,7 +428,7 @@
status = "disabled";
};
- sdhi1: sd@e822a000 {
+ sdhi1: mmc@e822a000 {
compatible = "renesas,sdhi-r7s9210";
reg = <0xe822a000 0x8c0>;
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
@@ -492,7 +489,7 @@
interrupt-map-mask = <7 0>;
};
- pinctrl: pin-controller@fcffe000 {
+ pinctrl: pinctrl@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index a5351dd..b088e8e 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -157,11 +157,8 @@
&cpu0 {
cpu0-supply = <&vdd_dvfs>;
- operating-points = <
- /* kHz uV */
- 1950000 1115000
- 1462500 995000
- >;
+ operating-points = <1950000 1115000>, /* kHz uV */
+ <1462500 995000>;
voltage-tolerance = <1>; /* 1% */
};
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 4447f45..e5fb1ce 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -84,27 +84,27 @@
dma0: dma-controller@e6700020 {
compatible = "renesas,shdma-r8a73a4";
reg = <0 0xe6700020 0 0x89e0>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -221,7 +221,7 @@
power-domains = <&pd_c4>;
};
- pfc: pin-controller@e6050000 {
+ pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a73a4";
reg = <0 0xe6050000 0 0x9000>;
gpio-controller;
@@ -409,7 +409,7 @@
status = "disabled";
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee100000 0 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
@@ -419,7 +419,7 @@
status = "disabled";
};
- sdhi1: sd@ee120000 {
+ sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee120000 0 0x100>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
@@ -429,7 +429,7 @@
status = "disabled";
};
- sdhi2: sd@ee140000 {
+ sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 758360a..d960c27 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -60,8 +60,7 @@
enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
- states = <3300000 0
- 1800000 1>;
+ states = <3300000 0>, <1800000 1>;
enable-active-high;
};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 155f58e..1b2cf5f 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -83,7 +83,7 @@
};
cmt1: timer@e6138000 {
- compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
+ compatible = "renesas,r8a7740-cmt1";
reg = <0xe6138000 0x170>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
@@ -102,14 +102,14 @@
<0xe6900020 1>,
<0xe6900040 1>,
<0xe6900060 1>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
};
@@ -124,14 +124,14 @@
<0xe6900024 1>,
<0xe6900044 1>,
<0xe6900064 1>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
};
@@ -146,14 +146,14 @@
<0xe6900028 1>,
<0xe6900048 1>,
<0xe6900068 1>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
};
@@ -168,14 +168,14 @@
<0xe690002c 1>,
<0xe690004c 1>,
<0xe690006c 1>;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>;
};
@@ -198,10 +198,10 @@
#size-cells = <0>;
compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
reg = <0xfff20000 0x425>;
- interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
power-domains = <&pd_a4r>;
status = "disabled";
@@ -212,10 +212,10 @@
#size-cells = <0>;
compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
reg = <0xe6c20000 0x425>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -311,7 +311,7 @@
status = "disabled";
};
- pfc: pin-controller@e6050000 {
+ pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a7740";
reg = <0xe6050000 0x8000>,
<0xe605800c 0x20>;
@@ -342,19 +342,19 @@
mmcif0: mmc@e6bd0000 {
compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
reg = <0xe6bd0000 0x100>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_MMC>;
power-domains = <&pd_a3sp>;
status = "disabled";
};
- sdhi0: sd@e6850000 {
+ sdhi0: mmc@e6850000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6850000 0x100>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed;
@@ -362,12 +362,12 @@
status = "disabled";
};
- sdhi1: sd@e6860000 {
+ sdhi1: mmc@e6860000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6860000 0x100>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed;
@@ -375,12 +375,12 @@
status = "disabled";
};
- sdhi2: sd@e6870000 {
+ sdhi2: mmc@e6870000 {
compatible = "renesas,sdhi-r8a7740";
reg = <0xe6870000 0x100>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed;
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
new file mode 100644
index 0000000..961c0f2
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave-RZ/G1H Qseven board development
+ * platform with camera daughter board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a7742-iwg21d-q7.dts"
+
+/ {
+ model = "iWave Systems RZ/G1H Qseven development platform with camera add-on";
+ compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
+
+ aliases {
+ serial0 = &scif0;
+ serial1 = &scif1;
+ serial3 = &scifb1;
+ serial5 = &hscif0;
+ ethernet1 = ðer;
+ };
+};
+
+&avb {
+ /* Pins shared with VIN0, keep status disabled */
+ status = "disabled";
+};
+
+&can0 {
+ pinctrl-0 = <&can0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+ðer {
+ pinctrl-0 = <ðer_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&hscif0 {
+ pinctrl-0 = <&hscif0_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&pfc {
+ can0_pins: can0 {
+ groups = "can0_data_d";
+ function = "can0";
+ };
+
+ ether_pins: ether {
+ groups = "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ hscif0_pins: hscif0 {
+ groups = "hscif0_data", "hscif0_ctrl";
+ function = "hscif0";
+ };
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif1_pins: scif1 {
+ groups = "scif1_data";
+ function = "scif1";
+ };
+
+ scifb1_pins: scifb1 {
+ groups = "scifb1_data";
+ function = "scifb1";
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif1 {
+ pinctrl-0 = <&scif1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scifb1 {
+ pinctrl-0 = <&scifb1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
new file mode 100644
index 0000000..c2c05c9
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave-RZ/G1H Qseven board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/*
+ * SSI-SGTL5000
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
+ * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ * amixer set "DVC Out Ramp" on
+ * aplay xxx.wav &
+ * amixer set "DVC Out" 80% // Volume Down
+ * amixer set "DVC Out" 100% // Volume Up
+ */
+
+/dts-v1/;
+#include "r8a7742-iwg21m.dtsi"
+
+/ {
+ model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H";
+ compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
+
+ aliases {
+ serial2 = &scifa2;
+ serial4 = &scifb2;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait";
+ stdout-path = "serial2:115200n8";
+ };
+
+ audio_clock: audio_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sdhi2_led {
+ label = "sdio-led";
+ gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ };
+ };
+
+ reg_1p5v: 1p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P5V";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ };
+
+ rsnd_sgtl5000: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sndcodec>;
+ simple-audio-card,frame-master = <&sndcodec>;
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ };
+ };
+
+ vcc_sdhi2: regulator-vcc-sdhi2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI2 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ };
+
+ vccq_sdhi2: regulator-vccq-sdhi2 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI2 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>, <1800000 0>;
+ };
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
+ phy-handle = <&phy3>;
+ phy-mode = "gmii";
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ micrel,led-mode = <1>;
+ };
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ clocks = <&audio_clock>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ VDDD-supply = <®_1p5v>;
+ };
+};
+
+&can1 {
+ pinctrl-0 = <&can1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&cmt0 {
+ status = "okay";
+};
+
+&gpio1 {
+ can-trx-en-gpio{
+ gpio-hog;
+ gpios = <28 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "can-trx-en-gpio";
+ };
+};
+
+&hsusb {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&msiof0 {
+ pinctrl-0 = <&msiof0_pins>;
+ pinctrl-names = "default";
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+
+ flash1: flash@0 {
+ compatible = "sst,sst25vf016b", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "user";
+ reg = <0x00000000 0x00200000>;
+ };
+ };
+ };
+};
+
+&pci0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+ /* Disable hsusb to enable USB2.0 host mode support on J2 */
+ /* status = "okay"; */
+};
+
+&pci1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pci2 {
+ /* Disable xhci to enable USB2.0 host mode support on J23 bottom port */
+ /* status = "okay"; */
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec {
+ /* SW2[6] determines which connector is activated
+ * ON = PCIe X4 (connector-J7)
+ * OFF = mini-PCIe (connector-J26)
+ */
+ status = "okay";
+};
+
+&pfc {
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_gmii";
+ function = "avb";
+ };
+
+ can1_pins: can1 {
+ groups = "can1_data_b";
+ function = "can1";
+ };
+
+ i2c2_pins: i2c2 {
+ groups = "i2c2_b";
+ function = "i2c2";
+ };
+
+ msiof0_pins: msiof0 {
+ groups = "msiof0_clk", "msiof0_sync", "msiof0_tx", "msiof0_rx";
+ function = "msiof0";
+ };
+
+ scifa2_pins: scifa2 {
+ groups = "scifa2_data_c";
+ function = "scifa2";
+ };
+
+ scifb2_pins: scifb2 {
+ groups = "scifb2_data", "scifb2_ctrl";
+ function = "scifb2";
+ };
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data4", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
+ };
+
+ sound_pins: sound {
+ groups = "ssi34_ctrl", "ssi3_data", "ssi4_data";
+ function = "ssi";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ groups = "usb1_pwen";
+ function = "usb1";
+ };
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi4 &src4 &dvc1>;
+ capture = <&ssi3 &src3 &dvc0>;
+ };
+ };
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
+&scifa2 {
+ pinctrl-0 = <&scifa2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scifb2 {
+ pinctrl-0 = <&scifb2_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&sdhi2 {
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi2>;
+ vqmmc-supply = <&vccq_sdhi2>;
+ cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+ sd-uhs-sdr50;
+ status = "okay";
+};
+
+&ssi4 {
+ shared-pin;
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
new file mode 100644
index 0000000..5621c9e
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave RZ/G1H Qseven SOM
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include "r8a7742.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "iwave,g21m", "renesas,r8a7742";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ memory@200000000 {
+ device_type = "memory";
+ reg = <2 0x00000000 0 0x40000000>;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&gpio0 {
+ /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */
+ qspi_en {
+ gpio-hog;
+ gpios = <18 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "QSPI_EN";
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rtc@68 {
+ compatible = "ti,bq32000";
+ reg = <0x68>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&mmcif1 {
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+
+ vmmc-supply = <®_3p3v>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&pfc {
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
+ mmc1_pins: mmc1 {
+ groups = "mmc1_data4", "mmc1_ctrl";
+ function = "mmc1";
+ };
+
+ qspi_pins: qspi {
+ groups = "qspi_ctrl", "qspi_data2";
+ function = "qspi";
+ };
+};
+
+&qspi {
+ pinctrl-0 = <&qspi_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "sst,sst25vf016b", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ spi-cpol;
+ spi-cpha;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bootloader";
+ reg = <0x00000000 0x000c0000>;
+ read-only;
+ };
+ partition@c0000 {
+ label = "env";
+ reg = <0x000c0000 0x00002000>;
+ };
+ partition@c2000 {
+ label = "user";
+ reg = <0x000c2000 0x0013e000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
new file mode 100644
index 0000000..6a78c81
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -0,0 +1,1885 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a7742 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/r8a7742-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7742";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "renesas,apmu";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
+ power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
+ power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <2>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
+ power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <3>;
+ clock-frequency = <1400000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
+ power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
+ next-level-cache = <&L2_CA15>;
+ capacity-dmips-mhz = <1024>;
+ voltage-tolerance = <1>; /* 1% */
+ clock-latency = <300000>; /* 300 us */
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1400000 1000000>,
+ <1225000 1000000>,
+ <1050000 1000000>,
+ < 875000 1000000>,
+ < 700000 1000000>,
+ < 350000 1000000>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
+ power-domains = <&sysc R8A7742_PD_CA7_CPU0>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
+ power-domains = <&sysc R8A7742_PD_CA7_CPU1>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
+ power-domains = <&sysc R8A7742_PD_CA7_CPU2>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ clock-frequency = <780000000>;
+ clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
+ power-domains = <&sysc R8A7742_PD_CA7_CPU3>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ L2_CA15: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7742_PD_CA15_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ L2_CA7: cache-controller-1 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7742_PD_CA7_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ pmu-0 {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ pmu-1 {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a7742-wdt",
+ "renesas,rcar-gen2-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 30>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 30>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a7742",
+ "renesas,rcar-gen2-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ pfc: pinctrl@e6060000 {
+ compatible = "renesas,pfc-r8a7742";
+ reg = <0 0xe6060000 0 0x250>;
+ };
+
+ tpu: pwm@e60f0000 {
+ compatible = "renesas,tpu-r8a7742", "renesas,tpu";
+ reg = <0 0xe60f0000 0 0x148>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7742-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ apmu@e6151000 {
+ compatible = "renesas,r8a7742-apmu", "renesas,apmu";
+ reg = <0 0xe6151000 0 0x188>;
+ cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+
+ apmu@e6152000 {
+ compatible = "renesas,r8a7742-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7742-rst";
+ reg = <0 0xe6160000 0 0x0100>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7742-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7742", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
+ thermal: thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7742",
+ "renesas,rcar-gen2-thermal";
+ reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ ipmmu_sy0: iommu@e6280000 {
+ compatible = "renesas,ipmmu-r8a7742",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6280000 0 0x1000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_sy1: iommu@e6290000 {
+ compatible = "renesas,ipmmu-r8a7742",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6290000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds: iommu@e6740000 {
+ compatible = "renesas,ipmmu-r8a7742",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xe6740000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mp: iommu@ec680000 {
+ compatible = "renesas,ipmmu-r8a7742",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xec680000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mx: iommu@fe951000 {
+ compatible = "renesas,ipmmu-r8a7742",
+ "renesas,ipmmu-vmsa";
+ reg = <0 0xfe951000 0 0x1000>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ icram0: sram@e63a0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
+ };
+
+ icram1: sram@e63c0000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe63c0000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63c0000 0x1000>;
+
+ smp-sram@0 {
+ compatible = "renesas,smp-sram";
+ reg = <0 0x100>;
+ };
+ };
+
+ icram2: sram@e6300000 {
+ compatible = "mmio-sram";
+ reg = <0 0xe6300000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x40000>;
+ };
+
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7742",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6518000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7742",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6518000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6530000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7742",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e6540000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7742",
+ "renesas,rcar-gen2-i2c";
+ reg = <0 0xe6540000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ iic0: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7742",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6500000 0 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+ <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
+
+ iic1: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7742",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6510000 0 0x425>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 323>;
+ dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+ <&dmac1 0x65>, <&dmac1 0x66>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 323>;
+ status = "disabled";
+ };
+
+ iic2: i2c@e6520000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7742",
+ "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe6520000 0 0x425>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
+ <&dmac1 0x69>, <&dmac1 0x6a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
+ iic3: i2c@e60b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a7742";
+ reg = <0 0xe60b0000 0 0x425>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+ <&dmac1 0x77>, <&dmac1 0x78>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 926>;
+ status = "disabled";
+ };
+
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a7742",
+ "renesas,rcar-gen2-usbhs";
+ reg = <0 0xe6590000 0 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy: usb-phy@e6590100 {
+ compatible = "renesas,usb-phy-r8a7742",
+ "renesas,rcar-gen2-usb-phy";
+ reg = <0 0xe6590100 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cpg CPG_MOD 704>;
+ clock-names = "usbhs";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 704>;
+ status = "disabled";
+
+ usb0: usb-channel@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+ usb2: usb-channel@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+ };
+
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a7742-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a7742-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7742",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7742",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7742",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ qspi: spi@e6b10000 {
+ compatible = "renesas,qspi-r8a7742", "renesas,qspi";
+ reg = <0 0xe6b10000 0 0x2c>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+ <&dmac1 0x17>, <&dmac1 0x18>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7742",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7742",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7742",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 0x40>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7742",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7742",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7742",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 216>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7742",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7742",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 720>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e56000 {
+ compatible = "renesas,scif-r8a7742",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e56000 0 0x40>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 310>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7742",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 717>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7742",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+ };
+
+ msiof0: spi@e6e20000 {
+ compatible = "renesas,msiof-r8a7742",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e20000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0>;
+ dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+ <&dmac1 0x51>, <&dmac1 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6e10000 {
+ compatible = "renesas,msiof-r8a7742",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e10000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>;
+ dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+ <&dmac1 0x55>, <&dmac1 0x56>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6e00000 {
+ compatible = "renesas,msiof-r8a7742",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6e00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 205>;
+ dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+ <&dmac1 0x41>, <&dmac1 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 205>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c90000 {
+ compatible = "renesas,msiof-r8a7742",
+ "renesas,rcar-gen2-msiof";
+ reg = <0 0xe6c90000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 215>;
+ dmas = <&dmac0 0x45>, <&dmac0 0x46>,
+ <&dmac1 0x45>, <&dmac1 0x46>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 215>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7742",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e80000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>,
+ <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
+
+ can1: can@e6e88000 {
+ compatible = "renesas,can-r8a7742",
+ "renesas,rcar-gen2-can";
+ reg = <0 0xe6e88000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>,
+ <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7742",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a7742",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ status = "disabled";
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a7742",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a7742",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+ };
+
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7742",
+ "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A7742_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>,
+ <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>,
+ <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>,
+ <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>,
+ <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>,
+ <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>,
+ <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>,
+ <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>,
+ <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>,
+ <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>,
+ <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a7742",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a7742",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
+ xhci: usb@ee000000 {
+ compatible = "renesas,xhci-r8a7742",
+ "renesas,rcar-gen2-xhci";
+ reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ phys = <&usb2 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ pci0: pci@ee090000 {
+ compatible = "renesas,pci-r8a7742",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee090000 0 0xc00>,
+ <0 0xee080000 0 0x1100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x800 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ phys = <&usb0 0>;
+ phy-names = "usb";
+ };
+ };
+
+ pci1: pci@ee0b0000 {
+ compatible = "renesas,pci-r8a7742",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ reg = <0 0xee0b0000 0 0xc00>,
+ <0 0xee0a0000 0 0x1100>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ status = "disabled";
+
+ bus-range = <1 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci2: pci@ee0d0000 {
+ compatible = "renesas,pci-r8a7742",
+ "renesas,pci-rcar-gen2";
+ device_type = "pci";
+ clocks = <&cpg CPG_MOD 703>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 703>;
+ reg = <0 0xee0d0000 0 0xc00>,
+ <0 0xee0c0000 0 0x1100>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <2 2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb@1,0 {
+ reg = <0x20800 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+
+ usb@2,0 {
+ reg = <0x21000 0 0 0 0>;
+ phys = <&usb2 0>;
+ phy-names = "usb";
+ };
+ };
+
+ sdhi0: mmc@ee100000 {
+ compatible = "renesas,sdhi-r8a7742",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ sdhi1: mmc@ee120000 {
+ compatible = "renesas,sdhi-r8a7742",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee120000 0 0x328>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 313>;
+ dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+ <&dmac1 0xc9>, <&dmac1 0xca>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 313>;
+ status = "disabled";
+ };
+
+ sdhi2: mmc@ee140000 {
+ compatible = "renesas,sdhi-r8a7742",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
+
+ sdhi3: mmc@ee160000 {
+ compatible = "renesas,sdhi-r8a7742",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
+
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7742",
+ "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
+
+ mmcif1: mmc@ee220000 {
+ compatible = "renesas,mmcif-r8a7742",
+ "renesas,sh-mmcif";
+ reg = <0 0xee220000 0 0x80>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 305>;
+ dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
+ <&dmac1 0xe1>, <&dmac1 0xe2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 305>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
+
+ sata0: sata@ee300000 {
+ compatible = "renesas,sata-r8a7742",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee300000 0 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ status = "disabled";
+ };
+
+ sata1: sata@ee500000 {
+ compatible = "renesas,sata-r8a7742",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee500000 0 0x200000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 814>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 814>;
+ status = "disabled";
+ };
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7742",
+ "renesas,rcar-gen2-ether";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&cpg CPG_MOD 408>;
+ clock-names = "clk";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 408>;
+ };
+
+ pciec: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7742",
+ "renesas,pcie-rcar-gen2";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+ <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
+ };
+
+ vsp@fe920000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe920000 0 0x8000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 130>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 130>;
+ };
+
+ vsp@fe928000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe928000 0 0x8000>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 131>;
+ };
+
+ vsp@fe930000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe930000 0 0x8000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 128>;
+ };
+
+ vsp@fe938000 {
+ compatible = "renesas,vsp1";
+ reg = <0 0xfe938000 0 0x8000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 127>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 127>;
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7742";
+ reg = <0 0xfeb00000 0 0x70000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>;
+ clock-names = "du.0", "du.1", "du.2";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ du_out_lvds1: endpoint {
+ remote-endpoint = <&lvds1_in>;
+ };
+ };
+ };
+ };
+
+ lvds0: lvds@feb90000 {
+ compatible = "renesas,r8a7742-lvds";
+ reg = <0 0xfeb90000 0 0x14>;
+ clocks = <&cpg CPG_MOD 726>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 726>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ lvds1: lvds@feb94000 {
+ compatible = "renesas,r8a7742-lvds";
+ reg = <0 0xfeb94000 0 0x14>;
+ clocks = <&cpg CPG_MOD 725>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 725>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds1_in: endpoint {
+ remote-endpoint = <&du_out_lvds1>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
+
+ cmt0: timer@ffca0000 {
+ compatible = "renesas,r8a7742-cmt0",
+ "renesas,rcar-gen2-cmt0";
+ reg = <0 0xffca0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a7742-cmt1",
+ "renesas,rcar-gen2-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 329>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 329>;
+ status = "disabled";
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index fdd2678..f444e41 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -265,7 +265,7 @@
resets = <&cpg 904>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7743";
reg = <0 0xe6060000 0 0x250>;
};
@@ -399,6 +399,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -417,6 +420,9 @@
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x40000>;
};
/* The memory map in the User's Manual maps the cores to
@@ -600,8 +606,8 @@
compatible = "renesas,r8a7743-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
@@ -614,8 +620,8 @@
compatible = "renesas,r8a7743-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
@@ -628,22 +634,22 @@
compatible = "renesas,dmac-r8a7743",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -661,22 +667,22 @@
compatible = "renesas,dmac-r8a7743",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1366,20 +1372,20 @@
compatible = "renesas,dmac-r8a7743",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1397,20 +1403,20 @@
compatible = "renesas,dmac-r8a7743",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1461,10 +1467,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1496,10 +1502,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
@@ -1514,7 +1520,7 @@
};
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@@ -1529,7 +1535,7 @@
status = "disabled";
};
- sdhi1: sd@ee140000 {
+ sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@@ -1544,7 +1550,7 @@
status = "disabled";
};
- sdhi2: sd@ee160000 {
+ sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7743",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@@ -1611,13 +1617,13 @@
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+ <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1663,9 +1669,10 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
status = "disabled";
ports {
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 8264481..0442aad 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -265,7 +265,7 @@
resets = <&cpg 904>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7744";
reg = <0 0xe6060000 0 0x250>;
};
@@ -399,6 +399,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -417,6 +420,9 @@
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x40000>;
};
/* The memory map in the User's Manual maps the cores to
@@ -600,8 +606,8 @@
compatible = "renesas,r8a7744-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
@@ -614,8 +620,8 @@
compatible = "renesas,r8a7744-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
@@ -628,22 +634,22 @@
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -661,22 +667,22 @@
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1366,20 +1372,20 @@
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1397,20 +1403,20 @@
compatible = "renesas,dmac-r8a7744",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1461,10 +1467,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1496,10 +1502,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
@@ -1514,7 +1520,7 @@
};
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7744",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@@ -1529,7 +1535,7 @@
status = "disabled";
};
- sdhi1: sd@ee140000 {
+ sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7744",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@@ -1544,7 +1550,7 @@
status = "disabled";
};
- sdhi2: sd@ee160000 {
+ sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7744",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@@ -1597,13 +1603,13 @@
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+ <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1649,9 +1655,10 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
status = "disabled";
ports {
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
index 2aeebfc..b1f679d 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dts
@@ -84,8 +84,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@@ -108,6 +106,12 @@
};
};
+&lcd_panel {
+ status = "disabled";
+
+ /delete-node/ port;
+};
+
&pfc {
can1_pins: can1 {
groups = "can1_data_b";
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index ce6603b..1c7b37a 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -30,6 +30,7 @@
/dts-v1/;
#include "r8a7745-iwg22m.dtsi"
+#include <dt-bindings/pwm/pwm.h>
/ {
model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E";
@@ -52,6 +53,46 @@
clock-frequency = <26000000>;
};
+ backlight_lcd: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&tpu 3 5000000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ };
+
+ lcd_panel: lcd {
+ compatible = "edt,etm043080dh6gp";
+ power-supply = <&vccq_panel>;
+ backlight = <&backlight_lcd>;
+
+ port {
+ lcd_in: endpoint {
+ remote-endpoint = <&du_out_rgb0>;
+ };
+ };
+ };
+
+ vccq_panel: regulator-vccq-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "Panel VccQ";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+ gpios-states = <1>;
+ states = <3300000 1>, <1800000 0>;
+ };
+
rsnd_sgtl5000: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -66,19 +107,6 @@
sound-dai = <&sgtl5000>;
};
};
-
- vccq_sdhi0: regulator-vccq-sdhi0 {
- compatible = "regulator-gpio";
-
- regulator-name = "SDHI0 VccQ";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
- gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
- };
};
&avb {
@@ -107,6 +135,21 @@
status = "okay";
};
+&du {
+ pinctrl-0 = <&du0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&lcd_in>;
+ };
+ };
+ };
+};
+
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
@@ -136,6 +179,39 @@
VDDA-supply = <®_3p3v>;
VDDIO-supply = <®_3p3v>;
};
+
+ stmpe811@44 {
+ compatible = "st,stmpe811";
+ reg = <0x44>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* ADC conversion time: 80 clocks */
+ st,sample-time = <4>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ /* 8 sample average control */
+ st,ave-ctrl = <3>;
+ /* 7 length fractional part in z */
+ st,fraction-z = <7>;
+ /*
+ * 50 mA typical 80 mA max touchscreen drivers
+ * current limit value
+ */
+ st,i-drive = <1>;
+ /* 1 ms panel driver settling time */
+ st,settling = <3>;
+ /* 5 ms touch detect interrupt delay */
+ st,touch-det-delay = <5>;
+ };
+ };
};
&pci1 {
@@ -150,11 +226,21 @@
function = "avb";
};
+ backlight_pins: backlight {
+ groups = "tpu_to3_c";
+ function = "tpu";
+ };
+
can0_pins: can0 {
groups = "can0_data";
function = "can0";
};
+ du0_pins: du0 {
+ groups = "du0_rgb666", "du0_sync", "du0_disp", "du0_clk0_out";
+ function = "du0";
+ };
+
hscif1_pins: hscif1 {
groups = "hscif1_data", "hscif1_ctrl";
function = "hscif1";
@@ -230,6 +316,12 @@
shared-pin;
};
+&tpu {
+ pinctrl-0 = <&backlight_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&usbphy {
status = "okay";
};
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index c306713..0f14ac2 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -230,7 +230,7 @@
resets = <&cpg 905>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7745";
reg = <0 0xe6060000 0 0x11c>;
};
@@ -363,6 +363,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -381,6 +384,9 @@
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x40000>;
};
i2c0: i2c@e6508000 {
#address-cells = <1>;
@@ -543,8 +549,8 @@
compatible = "renesas,r8a7745-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
@@ -557,8 +563,8 @@
compatible = "renesas,r8a7745-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
@@ -571,22 +577,22 @@
compatible = "renesas,dmac-r8a7745",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -604,22 +610,22 @@
compatible = "renesas,dmac-r8a7745",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1293,20 +1299,20 @@
compatible = "renesas,dmac-r8a7745",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1337,10 +1343,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1372,10 +1378,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
@@ -1390,7 +1396,7 @@
};
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@@ -1405,7 +1411,7 @@
status = "disabled";
};
- sdhi1: sd@ee140000 {
+ sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@@ -1420,7 +1426,7 @@
status = "disabled";
};
- sdhi2: sd@ee160000 {
+ sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7745",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@@ -1500,11 +1506,12 @@
du: display@feb00000 {
compatible = "renesas,du-r8a7745";
reg = <0 0xfeb00000 0 0x40000>;
- reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
status = "disabled";
ports {
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 450efe9..8ac61b5 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -65,8 +65,7 @@
gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
};
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 51806c7..691b1a1 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -187,7 +187,7 @@
resets = <&cpg 907>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a77470";
reg = <0 0xe6060000 0 0x118>;
};
@@ -242,6 +242,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -260,6 +263,9 @@
icram2: sram@e6300000 {
compatible = "mmio-sram";
reg = <0 0xe6300000 0 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe6300000 0x20000>;
};
i2c0: i2c@e6508000 {
@@ -407,8 +413,8 @@
compatible = "renesas,r8a77470-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
@@ -421,8 +427,8 @@
compatible = "renesas,r8a77470-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
@@ -435,8 +441,8 @@
compatible = "renesas,r8a77470-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a8000 0 0x100>;
- interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 326>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
@@ -449,8 +455,8 @@
compatible = "renesas,r8a77470-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b8000 0 0x100>;
- interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 327>;
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
@@ -463,22 +469,22 @@
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -496,22 +502,22 @@
compatible = "renesas,dmac-r8a77470",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -876,7 +882,7 @@
status = "disabled";
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a77470",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@@ -891,7 +897,7 @@
status = "disabled";
};
- sdhi1: sd@ee300000 {
+ sdhi1: mmc@ee300000 {
compatible = "renesas,sdhi-mmc-r8a77470";
reg = <0 0xee300000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
@@ -902,7 +908,7 @@
status = "disabled";
};
- sdhi2: sd@ee160000 {
+ sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a77470",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x328>;
@@ -936,9 +942,10 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
status = "disabled";
ports {
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 10d996d..c9f8735 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -78,11 +78,12 @@
<0xfe780010 4>,
<0xfe780024 4>,
<0xfe780044 4>,
- <0xfe780064 4>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ <0xfe780064 4>,
+ <0xfe780000 4>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
sense-bitfield-width = <2>;
};
@@ -141,7 +142,7 @@
interrupt-controller;
};
- pfc: pin-controller@fffc0000 {
+ pfc: pinctrl@fffc0000 {
compatible = "renesas,pfc-r8a7778";
reg = <0xfffc0000 0x118>;
};
@@ -400,7 +401,7 @@
status = "disabled";
};
- sdhi0: sd@ffe4c000 {
+ sdhi0: mmc@ffe4c000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4c000 0x100>;
@@ -410,7 +411,7 @@
status = "disabled";
};
- sdhi1: sd@ffe4d000 {
+ sdhi1: mmc@ffe4d000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4d000 0x100>;
@@ -420,7 +421,7 @@
status = "disabled";
};
- sdhi2: sd@ffe4f000 {
+ sdhi2: mmc@ffe4f000 {
compatible = "renesas,sdhi-r8a7778",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4f000 0x100>;
@@ -498,14 +499,17 @@
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
+ clock-frequency = <0>;
};
/* Fixed ratio clocks */
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 29599ad..4658453 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -48,8 +48,7 @@
gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
ethernet@18000000 {
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index b3cb649..3c5fcdf 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -172,10 +172,10 @@
<0xfe780044 4>,
<0xfe780064 4>,
<0xfe780000 4>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
sense-bitfield-width = <2>;
};
@@ -321,7 +321,7 @@
status = "disabled";
};
- pfc: pin-controller@fffc0000 {
+ pfc: pinctrl@fffc0000 {
compatible = "renesas,pfc-r8a7779";
reg = <0xfffc0000 0x23c>;
};
@@ -377,7 +377,7 @@
};
sata: sata@fc600000 {
- compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
+ compatible = "renesas,sata-r8a7779";
reg = <0xfc600000 0x200000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
@@ -385,7 +385,7 @@
status = "disabled";
};
- sdhi0: sd@ffe4c000 {
+ sdhi0: mmc@ffe4c000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4c000 0x100>;
@@ -395,7 +395,7 @@
status = "disabled";
};
- sdhi1: sd@ffe4d000 {
+ sdhi1: mmc@ffe4d000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4d000 0x100>;
@@ -405,7 +405,7 @@
status = "disabled";
};
- sdhi2: sd@ffe4e000 {
+ sdhi2: mmc@ffe4e000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4e000 0x100>;
@@ -415,7 +415,7 @@
status = "disabled";
};
- sdhi3: sd@ffe4f000 {
+ sdhi3: mmc@ffe4f000 {
compatible = "renesas,sdhi-r8a7779",
"renesas,rcar-gen1-sdhi";
reg = <0xffe4f000 0x100>;
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 83cc619..1d6f0c5 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -53,6 +53,9 @@
i2c11 = &i2cexio1;
i2c12 = &i2chdmi;
i2c13 = &i2cpwr;
+ mmc0 = &mmcif1;
+ mmc1 = &sdhi0;
+ mmc2 = &sdhi2;
};
chosen {
@@ -150,8 +153,7 @@
gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -174,8 +176,7 @@
gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
audio_clock: audio_clock {
@@ -325,10 +326,10 @@
#size-cells = <0>;
};
- /*
- * IIC2 and I2C2 may be switched using pinmux.
- * A fallback to GPIO is also provided.
- */
+ /*
+ * IIC2 and I2C2 may be switched using pinmux.
+ * A fallback to GPIO is also provided.
+ */
i2chdmi: i2c-12 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
@@ -345,7 +346,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
- remote = <&vin1>;
port {
adv7180: endpoint {
@@ -366,8 +366,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@@ -676,6 +674,7 @@
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts
index a315ba7..6a457bc 100644
--- a/arch/arm/boot/dts/r8a7790-stout.dts
+++ b/arch/arm/boot/dts/r8a7790-stout.dts
@@ -203,6 +203,7 @@
interrupt-parent = <&irqc0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
};
};
@@ -296,8 +297,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index e3ba00a..b0569b4 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -363,7 +363,7 @@
resets = <&cpg 907>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7790";
reg = <0 0xe6060000 0 0x250>;
};
@@ -487,6 +487,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -669,8 +672,8 @@
compatible = "renesas,r8a7790-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -683,8 +686,8 @@
compatible = "renesas,r8a7790-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -697,22 +700,22 @@
compatible = "renesas,dmac-r8a7790",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -730,22 +733,22 @@
compatible = "renesas,dmac-r8a7790",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1300,20 +1303,20 @@
compatible = "renesas,dmac-r8a7790",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1331,20 +1334,20 @@
compatible = "renesas,dmac-r8a7790",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1388,10 +1391,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1423,10 +1426,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
};
pci2: pci@ee0d0000 {
@@ -1446,10 +1449,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x20800 0 0 0 0>;
@@ -1464,7 +1467,7 @@
};
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@@ -1479,7 +1482,7 @@
status = "disabled";
};
- sdhi1: sd@ee120000 {
+ sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee120000 0 0x328>;
@@ -1494,7 +1497,7 @@
status = "disabled";
};
- sdhi2: sd@ee140000 {
+ sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@@ -1509,7 +1512,7 @@
status = "disabled";
};
- sdhi3: sd@ee160000 {
+ sdhi3: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7790",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@@ -1614,13 +1617,13 @@
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+ <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1716,6 +1719,8 @@
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>;
clock-names = "du.0", "du.1", "du.2";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
status = "disabled";
ports {
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index af6bd8f..6af1727 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -53,6 +53,9 @@
i2c12 = &i2cexio1;
i2c13 = &i2chdmi;
i2c14 = &i2cexio4;
+ mmc0 = &sdhi0;
+ mmc1 = &sdhi1;
+ mmc2 = &sdhi2;
};
chosen {
@@ -193,8 +196,7 @@
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
@@ -217,8 +219,7 @@
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -241,8 +242,7 @@
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
audio_clock: audio_clock {
@@ -369,7 +369,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
- remote = <&vin1>;
port {
adv7180: endpoint {
@@ -390,8 +389,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@@ -636,6 +633,7 @@
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index d6cf16a..bf51e29 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -28,6 +28,8 @@
serial0 = &scif0;
i2c9 = &gpioi2c2;
i2c10 = &i2chdmi;
+ mmc0 = &sdhi0;
+ mmc1 = &sdhi2;
};
chosen {
@@ -63,8 +65,7 @@
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -85,8 +86,7 @@
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
hdmi-out {
@@ -164,7 +164,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
- remote = <&vin0>;
port {
adv7180: endpoint {
@@ -183,8 +182,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@@ -309,6 +306,7 @@
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index a26f86c..87f0d6d 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -286,11 +286,22 @@
resets = <&cpg 904>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7791";
reg = <0 0xe6060000 0 0x250>;
};
+ tpu: pwm@e60f0000 {
+ compatible = "renesas,tpu-r8a7791", "renesas,tpu";
+ reg = <0 0xe60f0000 0 0x148>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 304>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7791-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -420,6 +431,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -618,8 +632,8 @@
compatible = "renesas,r8a7791-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
@@ -632,8 +646,8 @@
compatible = "renesas,r8a7791-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
@@ -646,22 +660,22 @@
compatible = "renesas,dmac-r8a7791",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -679,22 +693,22 @@
compatible = "renesas,dmac-r8a7791",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1064,6 +1078,76 @@
status = "disabled";
};
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
adc: adc@e6e54000 {
compatible = "renesas,r8a7791-gyroadc",
"renesas,rcar-gyroadc";
@@ -1338,20 +1422,20 @@
compatible = "renesas,dmac-r8a7791",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1369,20 +1453,20 @@
compatible = "renesas,dmac-r8a7791",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1426,10 +1510,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1461,10 +1545,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
@@ -1479,7 +1563,7 @@
};
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@@ -1494,7 +1578,7 @@
status = "disabled";
};
- sdhi1: sd@ee140000 {
+ sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@@ -1509,7 +1593,7 @@
status = "disabled";
};
- sdhi2: sd@ee160000 {
+ sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7791",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@@ -1598,13 +1682,13 @@
#size-cells = <2>;
bus-range = <0x00 0xff>;
device_type = "pci";
- ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
- 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
- 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
- 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
+ <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
+ <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
- dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
- 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
+ <0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
@@ -1678,9 +1762,10 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
status = "disabled";
ports {
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
index 248eb71..9368ac2 100644
--- a/arch/arm/boot/dts/r8a7792-blanche.dts
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -289,8 +289,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts
index bd2a63b..ba2d2a5 100644
--- a/arch/arm/boot/dts/r8a7792-wheat.dts
+++ b/arch/arm/boot/dts/r8a7792-wheat.dts
@@ -249,14 +249,12 @@
*/
hdmi@3d {
compatible = "adi,adv7513";
- reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>;
- reg-names = "main", "cec", "edid", "packet";
+ reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
+ reg-names = "main", "edid", "cec", "packet";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@@ -280,14 +278,12 @@
hdmi@39 {
compatible = "adi,adv7513";
- reg = <0x39>, <0x29>, <0x49>, <0x59>;
- reg-names = "main", "cec", "edid", "packet";
+ reg = <0x39>, <0x49>, <0x29>, <0x59>;
+ reg-names = "main", "edid", "cec", "packet";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index c4ea2d6..f5b299b 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -296,7 +296,7 @@
resets = <&cpg 913>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7792";
reg = <0 0xe6060000 0 0x144>;
};
@@ -345,6 +345,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -466,22 +469,22 @@
compatible = "renesas,dmac-r8a7792",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -499,22 +502,22 @@
compatible = "renesas,dmac-r8a7792",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -777,7 +780,7 @@
status = "disabled";
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7792",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@@ -849,9 +852,10 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
status = "disabled";
ports {
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 9f50739..2b59a04 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -49,6 +49,9 @@
i2c10 = &gpioi2c4;
i2c11 = &i2chdmi;
i2c12 = &i2cexio4;
+ mmc0 = &sdhi0;
+ mmc1 = &sdhi1;
+ mmc2 = &sdhi2;
};
chosen {
@@ -65,81 +68,81 @@
compatible = "gpio-keys";
key-1 {
- gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_1>;
- label = "SW2-1";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_1>;
+ label = "SW2-1";
+ wakeup-source;
+ debounce-interval = <20>;
};
key-2 {
- gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_2>;
- label = "SW2-2";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_2>;
+ label = "SW2-2";
+ wakeup-source;
+ debounce-interval = <20>;
};
key-3 {
- gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_3>;
- label = "SW2-3";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_3>;
+ label = "SW2-3";
+ wakeup-source;
+ debounce-interval = <20>;
};
key-4 {
- gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_4>;
- label = "SW2-4";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_4>;
+ label = "SW2-4";
+ wakeup-source;
+ debounce-interval = <20>;
};
key-a {
- gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_A>;
- label = "SW30";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_A>;
+ label = "SW30";
+ wakeup-source;
+ debounce-interval = <20>;
};
key-b {
- gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_B>;
- label = "SW31";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_B>;
+ label = "SW31";
+ wakeup-source;
+ debounce-interval = <20>;
};
key-c {
- gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_C>;
- label = "SW32";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_C>;
+ label = "SW32";
+ wakeup-source;
+ debounce-interval = <20>;
};
key-d {
- gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_D>;
- label = "SW33";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_D>;
+ label = "SW33";
+ wakeup-source;
+ debounce-interval = <20>;
};
key-e {
- gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_E>;
- label = "SW34";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_E>;
+ label = "SW34";
+ wakeup-source;
+ debounce-interval = <20>;
};
key-f {
- gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_F>;
- label = "SW35";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F>;
+ label = "SW35";
+ wakeup-source;
+ debounce-interval = <20>;
};
key-g {
- gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_G>;
- label = "SW36";
- wakeup-source;
- debounce-interval = <20>;
+ gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_G>;
+ label = "SW36";
+ wakeup-source;
+ debounce-interval = <20>;
};
};
@@ -179,8 +182,7 @@
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
@@ -203,8 +205,7 @@
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi2: regulator-vcc-sdhi2 {
@@ -227,8 +228,7 @@
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
audio_clock: audio_clock {
@@ -337,7 +337,6 @@
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
- remote = <&vin1>;
ports {
#address-cells = <1>;
@@ -369,8 +368,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@@ -594,6 +591,7 @@
interrupt-parent = <&irqc0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index fa38397..f930f69 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -271,7 +271,7 @@
resets = <&cpg 904>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7793";
reg = <0 0xe6060000 0 0x250>;
};
@@ -406,6 +406,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -565,22 +568,22 @@
compatible = "renesas,dmac-r8a7793",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -598,22 +601,22 @@
compatible = "renesas,dmac-r8a7793",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1166,20 +1169,20 @@
compatible = "renesas,dmac-r8a7793",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1197,20 +1200,20 @@
compatible = "renesas,dmac-r8a7793",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1224,7 +1227,7 @@
dma-channels = <13>;
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@@ -1239,7 +1242,7 @@
status = "disabled";
};
- sdhi1: sd@ee140000 {
+ sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@@ -1254,7 +1257,7 @@
status = "disabled";
};
- sdhi2: sd@ee160000 {
+ sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7793",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@@ -1338,9 +1341,10 @@
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>;
+ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
status = "disabled";
ports {
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 1d22fcd..3202598 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -19,6 +19,9 @@
i2c10 = &gpioi2c4;
i2c11 = &i2chdmi;
i2c12 = &i2cexio4;
+ mmc0 = &mmcif0;
+ mmc1 = &sdhi0;
+ mmc2 = &sdhi1;
};
chosen {
@@ -60,8 +63,7 @@
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
@@ -84,8 +86,7 @@
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
lbsc {
@@ -169,7 +170,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
- remote = <&vin0>;
port {
adv7180: endpoint {
@@ -345,6 +345,7 @@
interrupt-parent = <&irqc0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index b3177ae..af066ee 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -31,6 +31,8 @@
serial0 = &scif2;
i2c9 = &gpioi2c1;
i2c10 = &i2chdmi;
+ mmc0 = &mmcif0;
+ mmc1 = &sdhi1;
};
chosen {
@@ -126,8 +128,7 @@
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
- states = <3300000 1
- 1800000 0>;
+ states = <3300000 1>, <1800000 0>;
};
vga-encoder {
@@ -237,7 +238,6 @@
composite-in@20 {
compatible = "adi,adv7180";
reg = <0x20>;
- remote = <&vin0>;
port {
adv7180: endpoint {
@@ -256,8 +256,6 @@
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
ports {
#address-cells = <1>;
@@ -395,6 +393,7 @@
interrupt-parent = <&irqc0>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
+ reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 9dd9524..cd5e290 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -238,7 +238,7 @@
resets = <&cpg 905>;
};
- pfc: pin-controller@e6060000 {
+ pfc: pinctrl@e6060000 {
compatible = "renesas,pfc-r8a7794";
reg = <0 0xe6060000 0 0x11c>;
};
@@ -351,6 +351,9 @@
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xe63a0000 0x12000>;
};
icram1: sram@e63c0000 {
@@ -527,22 +530,22 @@
compatible = "renesas,dmac-r8a7794",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x20000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -560,22 +563,22 @@
compatible = "renesas,dmac-r8a7794",
"renesas,rcar-dmac";
reg = <0 0xe6720000 0 0x20000>;
- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -1132,20 +1135,20 @@
compatible = "renesas,dmac-r8a7794",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch4",
"ch5", "ch6", "ch7", "ch8", "ch9",
@@ -1176,10 +1179,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
@@ -1211,10 +1214,10 @@
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
- interrupt-map-mask = <0xff00 0 0 0x7>;
- interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
- 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
@@ -1229,7 +1232,7 @@
};
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee100000 0 0x328>;
@@ -1244,7 +1247,7 @@
status = "disabled";
};
- sdhi1: sd@ee140000 {
+ sdhi1: mmc@ee140000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee140000 0 0x100>;
@@ -1259,7 +1262,7 @@
status = "disabled";
};
- sdhi2: sd@ee160000 {
+ sdhi2: mmc@ee160000 {
compatible = "renesas,sdhi-r8a7794",
"renesas,rcar-gen2-sdhi";
reg = <0 0xee160000 0 0x100>;
@@ -1353,6 +1356,8 @@
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
+ resets = <&cpg 724>;
+ reset-names = "du.0";
status = "disabled";
ports {
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 4c1ab49..c47896e 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -165,7 +165,7 @@
status = "disabled";
};
- pinctrl: pin-controller@40067000 {
+ pinctrl: pinctrl@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
@@ -174,7 +174,7 @@
};
gic: interrupt-controller@44101000 {
- compatible = "arm,cortex-a7-gic", "arm,gic-400";
+ compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x44101000 0x1000>, /* Distributer */
diff --git a/arch/arm/boot/dts/rda8810pl.dtsi b/arch/arm/boot/dts/rda8810pl.dtsi
index 19cde89..f30d6ec 100644
--- a/arch/arm/boot/dts/rda8810pl.dtsi
+++ b/arch/arm/boot/dts/rda8810pl.dtsi
@@ -33,6 +33,21 @@
ranges;
};
+ modem@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000000 0xfffffff>;
+
+ gpioc@1a08000 {
+ compatible = "rda,8810pl-gpio";
+ reg = <0x1a08000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ };
+ };
+
apb@20800000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -60,6 +75,39 @@
<17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hwtimer", "ostimer";
};
+
+ gpioa@30000 {
+ compatible = "rda,8810pl-gpio";
+ reg = <0x30000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpiob@31000 {
+ compatible = "rda,8810pl-gpio";
+ reg = <0x31000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpiod@32000 {
+ compatible = "rda,8810pl-gpio";
+ reg = <0x32000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
apb@20a00000 {
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 2ef47eb..e817eba 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -16,7 +16,7 @@
leds: gpio-leds {
compatible = "gpio-leds";
- work {
+ work_led: led-0 {
gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
label = "kylin:red:led";
pinctrl-names = "default";
@@ -319,7 +319,7 @@
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
- default-sample-phase = <90>;
+ rockchip,default-sample-phase = <90>;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index d282a7b..0935670 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -54,7 +54,7 @@
};
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -67,6 +67,7 @@
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC2>;
clock-names = "apb_pclk";
};
@@ -101,7 +102,7 @@
#clock-cells = <0>;
};
- bus_intmem@10080000 {
+ bus_intmem: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x2000>;
#address-cells = <1>;
@@ -224,7 +225,7 @@
status = "disabled";
};
- sdmmc: dwmmc@10214000 {
+ sdmmc: mmc@10214000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
clock-frequency = <37500000>;
@@ -238,7 +239,7 @@
status = "disabled";
};
- sdio: dwmmc@10218000 {
+ sdio: mmc@10218000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10218000 0x4000>;
max-frequency = <37500000>;
@@ -252,7 +253,7 @@
status = "disabled";
};
- emmc: dwmmc@1021c000 {
+ emmc: mmc@1021c000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -263,7 +264,7 @@
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- default-sample-phase = <158>;
+ rockchip,default-sample-phase = <158>;
disable-wp;
dmas = <&pdma 12>;
dma-names = "rx-tx";
@@ -281,8 +282,6 @@
compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
reg = <0x10220000 0x4000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
dmas = <&pdma 0>, <&pdma 1>;
@@ -696,8 +695,8 @@
hdmi {
hdmi_ctl: hdmi-ctl {
- rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
- <1 RK_PB1 1 &pcfg_pull_none>,
+ rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
+ <1 RK_PB1 1 &pcfg_pull_none>,
<1 RK_PB2 1 &pcfg_pull_none>,
<1 RK_PB3 1 &pcfg_pull_none>;
};
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index 0a56a2f..eba7a13 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -63,7 +63,11 @@
};
&cpu0 {
- cpu0-supply = <&vdd_arm>;
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
};
&i2c1 {
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
index 7e01f64..6b12165 100644
--- a/arch/arm/boot/dts/rk3066a-marsboard.dts
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -47,7 +47,11 @@
};
&cpu0 {
- cpu0-supply = <&vdd_arm>;
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
};
&i2c1 {
diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts
index 365eff6..eed9e60 100644
--- a/arch/arm/boot/dts/rk3066a-mk808.dts
+++ b/arch/arm/boot/dts/rk3066a-mk808.dts
@@ -22,7 +22,7 @@
gpio-leds {
compatible = "gpio-leds";
- blue {
+ blue_led: led-0 {
label = "mk808:blue:power";
gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
default-state = "off";
diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts
index f9db6bb..3095184 100644
--- a/arch/arm/boot/dts/rk3066a-rayeager.dts
+++ b/arch/arm/boot/dts/rk3066a-rayeager.dts
@@ -128,7 +128,11 @@
};
&cpu0 {
- cpu0-supply = <&vdd_arm>;
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
};
&emac {
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 1ac9deb..bbc3bff 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -36,7 +36,7 @@
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
@@ -156,14 +156,12 @@
compatible = "rockchip,rk3066-i2s";
reg = <0x10118000 0x2000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
+ clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac1_s 4>, <&dmac1_s 5>;
dma-names = "tx", "rx";
- clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
rockchip,playback-channels = <8>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
@@ -174,14 +172,12 @@
compatible = "rockchip,rk3066-i2s";
reg = <0x1011a000 0x2000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
+ clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
dma-names = "tx", "rx";
- clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
@@ -192,14 +188,12 @@
compatible = "rockchip,rk3066-i2s";
reg = <0x1011c000 0x2000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
+ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
+ clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac1_s 9>, <&dmac1_s 10>;
dma-names = "tx", "rx";
- clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index c9a7f54..b0fef82 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -33,19 +33,19 @@
gpio-leds {
compatible = "gpio-leds";
- green {
+ green_led: led-0 {
label = "rock:green:user1";
gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>;
default-state = "off";
};
- blue {
+ blue_led: led-1 {
label = "rock:blue:user2";
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
default-state = "off";
};
- sleep {
+ sleep_led: led-2 {
label = "rock:red:power";
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
default-state = "off";
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ee8a24a..b6bde9d 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -166,14 +166,12 @@
compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
reg = <0x1011a000 0x2000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
+ clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
dma-names = "tx", "rx";
- clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
@@ -184,8 +182,8 @@
compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
reg = <0x1011e000 0x2000>;
#sound-dai-cells = <0>;
- clock-names = "hclk", "mclk";
- clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
+ clock-names = "mclk", "hclk";
dmas = <&dmac1_s 8>;
dma-names = "tx";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rk3229-xms6.dts
index 933ef69..263393a 100644
--- a/arch/arm/boot/dts/rk3229-xms6.dts
+++ b/arch/arm/boot/dts/rk3229-xms6.dts
@@ -33,12 +33,18 @@
power-led {
compatible = "gpio-leds";
- blue {
+ blue_led: led-0 {
gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>,
+ <&gpio2 29 GPIO_ACTIVE_LOW>;
+ };
+
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -131,7 +137,6 @@
&emmc {
cap-mmc-highspeed;
- disable-wp;
non-removable;
status = "okay";
};
@@ -202,6 +207,16 @@
status = "okay";
};
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ vqmmc-supply = <&vccio_1v8>;
+ status = "okay";
+};
+
&sdmmc {
cap-mmc-highspeed;
disable-wp;
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 140e22d..2f17bf3 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -95,7 +95,7 @@
};
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -107,6 +107,7 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
@@ -152,8 +153,6 @@
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100b0000 0x4000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
dmas = <&pdma 14>, <&pdma 15>;
@@ -167,8 +166,6 @@
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100c0000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
dmas = <&pdma 11>, <&pdma 12>;
@@ -193,8 +190,6 @@
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
reg = <0x100e0000 0x4000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
dmas = <&pdma 0>, <&pdma 1>;
@@ -526,10 +521,10 @@
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
- #thermal-sensor-cells = <0>;
+ pinctrl-2 = <&otp_pin>;
+ #thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
@@ -618,6 +613,16 @@
status = "disabled";
};
+ rga: rga@20060000 {
+ compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
+ reg = <0x20060000 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+ clock-names = "aclk", "hclk", "sclk";
+ resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
+ reset-names = "core", "axi", "ahb";
+ };
+
iep_mmu: iommu@20070800 {
compatible = "rockchip,iommu";
reg = <0x20070800 0x100>;
@@ -635,8 +640,8 @@
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru SCLK_HDMI_PHY>;
assigned-clock-parents = <&hdmi_phy>;
- clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
- clock-names = "isfr", "iahb", "cec";
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
+ clock-names = "iahb", "isfr", "cec";
pinctrl-names = "default";
pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
resets = <&cru SRST_HDMI_P>;
@@ -658,7 +663,7 @@
};
};
- sdmmc: dwmmc@30000000 {
+ sdmmc: mmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@@ -671,7 +676,7 @@
status = "disabled";
};
- sdio: dwmmc@30010000 {
+ sdio: mmc@30010000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30010000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
@@ -684,7 +689,7 @@
status = "disabled";
};
- emmc: dwmmc@30020000 {
+ emmc: mmc@30020000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -694,7 +699,7 @@
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
bus-width = <8>;
- default-sample-phase = <158>;
+ rockchip,default-sample-phase = <158>;
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
@@ -714,7 +719,6 @@
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
phys = <&u2phy0_otg>;
phy-names = "usb2-phy";
status = "disabled";
@@ -725,7 +729,6 @@
reg = <0x30080000 0x20000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy0>;
- clock-names = "usbhost", "utmi";
phys = <&u2phy0_host>;
phy-names = "usb";
status = "disabled";
@@ -736,7 +739,6 @@
reg = <0x300a0000 0x20000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy0>;
- clock-names = "usbhost", "utmi";
phys = <&u2phy0_host>;
phy-names = "usb";
status = "disabled";
@@ -747,7 +749,6 @@
reg = <0x300c0000 0x20000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST1>, <&u2phy1>;
- clock-names = "usbhost", "utmi";
phys = <&u2phy1_otg>;
phy-names = "usb";
status = "disabled";
@@ -758,7 +759,6 @@
reg = <0x300e0000 0x20000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST1>, <&u2phy1>;
- clock-names = "usbhost", "utmi";
phys = <&u2phy1_otg>;
phy-names = "usb";
status = "disabled";
@@ -771,7 +771,6 @@
clocks = <&cru HCLK_HOST2>, <&u2phy1>;
phys = <&u2phy1_host>;
phy-names = "usb";
- clock-names = "usbhost", "utmi";
status = "disabled";
};
@@ -780,7 +779,6 @@
reg = <0x30120000 0x20000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST2>, <&u2phy1>;
- clock-names = "usbhost", "utmi";
phys = <&u2phy1_host>;
phy-names = "usb";
status = "disabled";
@@ -1110,7 +1108,7 @@
};
tsadc {
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index 8008076..be695b8 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -4,6 +4,7 @@
#include "rk3288-evb.dtsi"
/ {
+ model = "Rockchip RK3288 EVB ACT8846";
compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
vcc_lcd: vcc-lcd {
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index 1678820..42384ea 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -4,6 +4,7 @@
#include "rk3288-evb.dtsi"
/ {
+ model = "Rockchip RK3288 EVB RK808";
compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
};
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 2afd686..c4ca73b 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -97,7 +97,7 @@
};
panel: panel {
- compatible = "lg,lp079qx1-sp0v", "simple-panel";
+ compatible = "lg,lp079qx1-sp0v";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&lcd_cs>;
@@ -247,7 +247,7 @@
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
+ status = "okay";
};
&gpu {
diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
index 61435d8..36efa36 100644
--- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi
@@ -61,7 +61,7 @@
snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
+ status = "okay";
};
&i2c0 {
diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts
index 1574383..9a4a974 100644
--- a/arch/arm/boot/dts/rk3288-firefly-reload.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts
@@ -45,20 +45,20 @@
leds {
compatible = "gpio-leds";
- power {
+ power_led: led-0 {
gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>;
label = "firefly:blue:power";
pinctrl-names = "default";
- pinctrl-0 = <&power_led>;
+ pinctrl-0 = <&power_led_pin>;
panic-indicator;
};
- work {
+ work_led: led-1 {
gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
label = "firefly:blue:user";
linux,default-trigger = "rc-feedback";
pinctrl-names = "default";
- pinctrl-0 = <&work_led>;
+ pinctrl-0 = <&work_led_pin>;
};
};
@@ -234,6 +234,7 @@
};
&saradc {
+ vref-supply = <&vcc_18>;
status = "okay";
};
@@ -333,11 +334,11 @@
};
leds {
- power_led: power-led {
+ power_led_pin: power-led-pin {
rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
- work_led: work-led {
+ work_led_pin: work-led-pin {
rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 5e0a190..7fb5823 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -62,20 +62,20 @@
leds {
compatible = "gpio-leds";
- work {
+ work_led: led-0 {
gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
label = "firefly:blue:user";
linux,default-trigger = "rc-feedback";
pinctrl-names = "default";
- pinctrl-0 = <&work_led>;
+ pinctrl-0 = <&work_led_pin>;
};
- power {
+ power_led: led-1 {
gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>;
label = "firefly:green:power";
linux,default-trigger = "default-on";
pinctrl-names = "default";
- pinctrl-0 = <&power_led>;
+ pinctrl-0 = <&power_led_pin>;
};
};
@@ -191,7 +191,7 @@
snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
+ status = "okay";
};
&gpu {
@@ -429,11 +429,11 @@
};
leds {
- power_led: power-led {
+ power_led_pin: power-led-pin {
rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
- work_led: work-led {
+ work_led_pin: work-led-pin {
rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index c41d012..cf54d5f 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -30,7 +30,7 @@
leds {
compatible = "gpio-leds";
- work {
+ work_led: led-0 {
gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
label = "miqi:green:user";
linux,default-trigger = "timer";
@@ -81,7 +81,19 @@
};
&cpu0 {
- cpu0-supply = <&vdd_cpu>;
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
};
&emmc {
@@ -108,7 +120,7 @@
snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
+ status = "okay";
};
&hdmi {
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index 77a47b9..e43887c 100644
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -36,9 +36,9 @@
leds: user-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&user_led>;
+ pinctrl-0 = <&user_led_pin>;
- user {
+ user_led: led-0 {
label = "green_led";
gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
@@ -372,7 +372,7 @@
};
leds {
- user_led: user-led {
+ user_led_pin: user-led-pin {
rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index 6a51940..8c7376d 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -103,7 +103,19 @@
};
&cpu0 {
- cpu0-supply = <&vdd_cpu>;
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
};
&emmc {
@@ -149,7 +161,7 @@
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
+ status = "okay";
};
&hdmi {
diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts
index a6ffc38..55467bc 100644
--- a/arch/arm/boot/dts/rk3288-r89.dts
+++ b/arch/arm/boot/dts/rk3288-r89.dts
@@ -9,6 +9,7 @@
#include "rk3288.dtsi"
/ {
+ model = "Netxeon R89";
compatible = "netxeon,r89", "rockchip,rk3288";
memory@0 {
@@ -90,7 +91,19 @@
};
&cpu0 {
- cpu0-supply = <&vdd_cpu>;
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
};
&gmac {
@@ -106,7 +119,7 @@
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
+ status = "okay";
};
&hdmi {
diff --git a/arch/arm/boot/dts/rk3288-rock-pi-n8.dts b/arch/arm/boot/dts/rk3288-rock-pi-n8.dts
new file mode 100644
index 0000000..b195930
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-rock-pi-n8.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Vamrs Limited
+ * Copyright (c) 2019 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "rk3288.dtsi"
+#include <arm/rockchip-radxa-dalang-carrier.dtsi>
+#include "rk3288-vmarc-som.dtsi"
+
+/ {
+ model = "Radxa ROCK Pi N8";
+ compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som",
+ "rockchip,rk3288";
+};
diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index 7b79a21..76363b8 100644
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -230,14 +230,14 @@
};
emmc {
- emmc_reset: emmc-reset {
- rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
+ emmc_reset: emmc-reset {
+ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
gmac {
phy_rst: phy-rst {
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
};
};
};
diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts
index cdcdc92..c4d1d14 100644
--- a/arch/arm/boot/dts/rk3288-rock2-square.dts
+++ b/arch/arm/boot/dts/rk3288-rock2-square.dts
@@ -41,13 +41,13 @@
gpio-leds {
compatible = "gpio-leds";
- heartbeat {
+ heartbeat_led: led-0 {
gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>;
label = "rock2:green:state1";
linux,default-trigger = "heartbeat";
};
- mmc {
+ mmc_led: led-1 {
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
label = "rock2:blue:state2";
linux,default-trigger = "mmc0";
@@ -156,7 +156,7 @@
};
&gmac {
- status = "ok";
+ status = "okay";
};
&hdmi {
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
index 81e4e95..9c1e38c 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
@@ -46,17 +46,17 @@
gpio-leds {
compatible = "gpio-leds";
- act-led {
+ act_led: led-0 {
gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
- heartbeat-led {
+ heartbeat_led: led-1 {
gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- pwr-led {
+ pwr_led: led-2 {
gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
@@ -113,6 +113,17 @@
cpu0-supply = <&vdd_cpu>;
};
+&cpu_opp_table {
+ opp-1704000000 {
+ opp-hz = /bits/ 64 <1704000000>;
+ opp-microvolt = <1350000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1400000>;
+ };
+};
+
&gmac {
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
@@ -126,7 +137,7 @@
snps,reset-delays-us = <0 10000 1000000>;
tx_delay = <0x30>;
rx_delay = <0x10>;
- status = "ok";
+ status = "okay";
};
&gpu {
@@ -175,7 +186,7 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1350000>;
+ regulator-max-microvolt = <1400000>;
regulator-name = "vdd_arm";
regulator-ramp-delay = <6000>;
regulator-state-mem {
@@ -265,6 +276,7 @@
};
vccio_sd: LDO_REG5 {
+ regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@@ -382,18 +394,15 @@
pmic {
pmic_int: pmic-int {
- rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO \
- &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
dvs_1: dvs-1 {
- rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO \
- &pcfg_pull_down>;
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
};
dvs_2: dvs-2 {
- rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO \
- &pcfg_pull_down>;
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
@@ -406,8 +415,7 @@
};
sdmmc_clk: sdmmc-clk {
- rockchip,pins = <6 RK_PC4 1 \
- &pcfg_pull_none_drv_8ma>;
+ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
};
sdmmc_cmd: sdmmc-cmd {
@@ -432,7 +440,7 @@
sdio {
wifi_enable: wifi-enable {
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
- <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
index 445270a..51208d1 100644
--- a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
@@ -17,6 +17,7 @@
rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>;
rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>;
rockchip,headset-codec = <&headsetcodec>;
+ rockchip,hdmi-codec = <&hdmi>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rk3288-veyron-brain.dts
index 406146c..aa33d09 100644
--- a/arch/arm/boot/dts/rk3288-veyron-brain.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-brain.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Brain";
@@ -40,6 +41,14 @@
};
&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+ >;
+
hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {
rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi
new file mode 100644
index 0000000..a10d25a
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth
+ * chip.
+ *
+ * Copyright 2019 Google, Inc
+ */
+
+&uart0 {
+ bluetooth {
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>,
+ <&bt_dev_wake>;
+
+ compatible = "brcm,bcm43540-bt";
+ host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ max-speed = <3000000>;
+ brcm,bt-pcm-int-params = [01 02 00 01 01];
+ };
+};
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index ffb60f8..05112c2 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -136,27 +136,6 @@
};
&pinctrl {
- pinctrl-0 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Wake only */
- &suspend_l_wake
- &bt_dev_wake_awake
- >;
- pinctrl-1 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Sleep only */
- &suspend_l_sleep
- &bt_dev_wake_sleep
- >;
-
buttons {
ap_lid_int_l: ap-lid-int-l {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-edp.dtsi b/arch/arm/boot/dts/rk3288-veyron-edp.dtsi
index b12e061..32c0f10 100644
--- a/arch/arm/boot/dts/rk3288-veyron-edp.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-edp.dtsi
@@ -41,39 +41,8 @@
backlight: backlight {
compatible = "pwm-backlight";
- brightness-levels = <
- 0 1 2 3 4 5 6 7
- 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23
- 24 25 26 27 28 29 30 31
- 32 33 34 35 36 37 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
default-brightness-level = <128>;
enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
@@ -85,7 +54,7 @@
};
panel: panel {
- compatible = "innolux,n116bge", "simple-panel";
+ compatible = "innolux,n116bge";
status = "okay";
power-supply = <&panel_regulator>;
backlight = <&backlight>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rk3288-veyron-fievel.dts
index 9a0f550..309b122 100644
--- a/arch/arm/boot/dts/rk3288-veyron-fievel.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-fievel.dts
@@ -18,8 +18,6 @@
"google,veyron-fievel-rev0", "google,veyron-fievel",
"google,veyron", "rockchip,rk3288";
- /delete-node/ bt-activity;
-
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vccsys";
@@ -215,7 +213,11 @@
"PHY_PMEB",
"PHY_INT",
- "REC_MODE_L",
+ /*
+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
+ * it REC_MODE_L.
+ */
+ "RECOVERY_SW_L",
"OTP_OUT",
"",
"USB_OTG_POWER_EN",
@@ -382,7 +384,11 @@
"PWR_LED1",
"TPM_INT_H",
"SPK_ON",
- "FW_WP_AP",
+ /*
+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
+ * it FW_WP_AP.
+ */
+ "AP_FLASH_WP_L",
"",
"CPU_NMI",
diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
index 8038620..af77ab2 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -20,39 +20,8 @@
&backlight {
/* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
- brightness-levels = <
- 0
- 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23
- 24 25 26 27 28 29 30 31
- 32 33 34 35 36 37 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255>;
+ brightness-levels = <0 8 255>;
+ num-interpolated-steps = <247>;
};
&rk808 {
@@ -75,10 +44,25 @@
};
};
+&sdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ btmrvl: btmrvl@2 {
+ compatible = "marvell,sd8897-bt";
+ reg = <2>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
+ marvell,wakeup-pin = /bits/ 16 <13>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l>;
+ };
+};
+
&sdmmc {
disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
};
@@ -304,6 +288,28 @@
};
&pinctrl {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ &bt_dev_wake_awake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ &bt_dev_wake_sleep
+ >;
+
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
index a6ee44f..2c916c5 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts
@@ -192,7 +192,7 @@
&sdmmc {
disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
};
@@ -418,6 +418,28 @@
};
&pinctrl {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ &bt_dev_wake_awake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ &bt_dev_wake_sleep
+ >;
+
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
index aa352d4..ffd1121 100644
--- a/arch/arm/boot/dts/rk3288-veyron-mickey.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-mickey.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Mickey";
@@ -28,6 +29,13 @@
regulator-boot-on;
vin-supply = <&vcc33_sys>;
};
+
+ sound {
+ compatible = "rockchip,rockchip-audio-max98090";
+ rockchip,model = "VEYRON-HDMI";
+ rockchip,hdmi-codec = <&hdmi>;
+ rockchip,i2s-controller = <&i2s>;
+ };
};
&cpu_thermal {
@@ -404,6 +412,14 @@
};
&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+ >;
+
hdmi {
power_hdmi_on: power-hdmi-on {
rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-mighty.dts b/arch/arm/boot/dts/rk3288-veyron-mighty.dts
index 27fbc07..fa695a8 100644
--- a/arch/arm/boot/dts/rk3288-veyron-mighty.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-mighty.dts
@@ -18,8 +18,8 @@
};
&sdmmc {
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
- &sdmmc_wp_gpio &sdmmc_bus4>;
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
+ &sdmmc_wp_pin &sdmmc_bus4>;
wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
/delete-property/ disable-wp;
@@ -27,7 +27,7 @@
&pinctrl {
sdmmc {
- sdmmc_wp_gpio: sdmmc-wp-gpio {
+ sdmmc_wp_pin: sdmmc-wp-pin {
rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
index 55955b0..f8b69e0 100644
--- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Minnie";
@@ -38,39 +39,8 @@
&backlight {
/* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
- brightness-levels = <
- 0 3 4 5 6 7
- 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23
- 24 25 26 27 28 29 30 31
- 32 33 34 35 36 37 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255>;
+ brightness-levels = <0 3 255>;
+ num-interpolated-steps = <252>;
};
&i2c_tunnel {
@@ -101,7 +71,7 @@
};
&panel {
- compatible = "auo,b101ean01", "simple-panel";
+ compatible = "auo,b101ean01";
/delete-node/ panel-timing;
@@ -144,7 +114,7 @@
&sdmmc {
disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
};
@@ -375,6 +345,26 @@
};
&pinctrl {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ >;
+
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
index f420499..4e9fdb0 100644
--- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts
@@ -64,6 +64,28 @@
};
&pinctrl {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ &bt_dev_wake_awake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ &bt_dev_wake_sleep
+ >;
+
/delete-node/ lcd;
backlight {
@@ -83,7 +105,7 @@
};
sdmmc {
- sdmmc_wp_gpio: sdmmc-wp-gpio {
+ sdmmc_wp_pin: sdmmc-wp-pin {
rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
@@ -104,8 +126,8 @@
&sdmmc {
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
- &sdmmc_wp_gpio &sdmmc_bus4>;
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
+ &sdmmc_wp_pin &sdmmc_bus4>;
wp-gpios = <&gpio7 RK_PB2 GPIO_ACTIVE_HIGH>;
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
index fe950f9..27fb06c 100644
--- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi
@@ -41,7 +41,7 @@
};
/* This is where we actually hook up CD */
- sdmmc_cd_gpio: sdmmc-cd-gpio {
+ sdmmc_cd_pin: sdmmc-cd-pin {
rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
index 2f2989b..4a3ea93 100644
--- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
#include "cros-ec-sbs.dtsi"
/ {
@@ -53,7 +54,7 @@
&sdmmc {
disable-wp;
pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
&sdmmc_bus4>;
};
@@ -279,6 +280,26 @@
};
&pinctrl {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Wake only */
+ &suspend_l_wake
+ >;
+ pinctrl-1 = <
+ /* Common for sleep and wake, but no owners */
+ &ddr0_retention
+ &ddrio_pwroff
+ &global_pwroff
+
+ /* Sleep only */
+ &suspend_l_sleep
+ >;
+
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rk3288-veyron-tiger.dts
index 2755720..069f0c2 100644
--- a/arch/arm/boot/dts/rk3288-veyron-tiger.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-tiger.dts
@@ -23,39 +23,8 @@
&backlight {
/* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */
- brightness-levels = <
- 0 3 4 5 6 7
- 8 9 10 11 12 13 14 15
- 16 17 18 19 20 21 22 23
- 24 25 26 27 28 29 30 31
- 32 33 34 35 36 37 38 39
- 40 41 42 43 44 45 46 47
- 48 49 50 51 52 53 54 55
- 56 57 58 59 60 61 62 63
- 64 65 66 67 68 69 70 71
- 72 73 74 75 76 77 78 79
- 80 81 82 83 84 85 86 87
- 88 89 90 91 92 93 94 95
- 96 97 98 99 100 101 102 103
- 104 105 106 107 108 109 110 111
- 112 113 114 115 116 117 118 119
- 120 121 122 123 124 125 126 127
- 128 129 130 131 132 133 134 135
- 136 137 138 139 140 141 142 143
- 144 145 146 147 148 149 150 151
- 152 153 154 155 156 157 158 159
- 160 161 162 163 164 165 166 167
- 168 169 170 171 172 173 174 175
- 176 177 178 179 180 181 182 183
- 184 185 186 187 188 189 190 191
- 192 193 194 195 196 197 198 199
- 200 201 202 203 204 205 206 207
- 208 209 210 211 212 213 214 215
- 216 217 218 219 220 221 222 223
- 224 225 226 227 228 229 230 231
- 232 233 234 235 236 237 238 239
- 240 241 242 243 244 245 246 247
- 248 249 250 251 252 253 254 255>;
+ brightness-levels = <0 3 255>;
+ num-interpolated-steps = <252>;
};
&backlight_regulator {
@@ -84,7 +53,7 @@
};
&panel {
- compatible = "auo,b101ean01", "simple-panel";
+ compatible = "auo,b101ean01";
/delete-node/ panel-timing;
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index 7525e3d..54a6838 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -23,30 +23,6 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
- bt_activity: bt-activity {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&bt_host_wake>;
-
- /*
- * HACK: until we have an LPM driver, we'll use an
- * ugly GPIO key to allow Bluetooth to wake from S3.
- * This is expected to only be used by BT modules that
- * use UART for comms. For BT modules that talk over
- * SDIO we should use a wakeup mechanism related to SDIO.
- *
- * Use KEY_RESERVED here since that will work as a wakeup but
- * doesn't get reported to higher levels (so doesn't confuse
- * Chrome).
- */
- bt-wake {
- label = "BT Wakeup";
- gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_RESERVED>;
- wakeup-source;
- };
-
- };
power_button: power-button {
compatible = "gpio-keys";
@@ -82,22 +58,17 @@
clocks = <&rk808 RK808_CLKOUT1>;
clock-names = "ext_clock";
pinctrl-names = "default";
- pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
+ pinctrl-0 = <&wifi_enable_h>;
/*
- * Depending on the actual card populated GPIO4 D4 and D5
+ * Depending on the actual card populated GPIO4 D4
* correspond to one of these signals on the module:
*
* D4:
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
- *
- * D5:
- * - BT_I2S_WS_BT_RFDISABLE_L
- * - No connect
*/
- reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>,
- <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc_5v: vcc-5v {
@@ -481,26 +452,6 @@
};
&pinctrl {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Wake only */
- &bt_dev_wake_awake
- >;
- pinctrl-1 = <
- /* Common for sleep and wake, but no owners */
- &ddr0_retention
- &ddrio_pwroff
- &global_pwroff
-
- /* Sleep only */
- &bt_dev_wake_sleep
- >;
-
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
bias-disable;
drive-strength = <8>;
@@ -622,6 +573,10 @@
bt_dev_wake_awake: bt-dev-wake-awake {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
};
+
+ bt_dev_wake: bt-dev-wake {
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
tpm {
diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
new file mode 100644
index 0000000..4a373f5
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Vamrs Limited
+ * Copyright (c) 2019 Amarula Solutions(India)
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+ compatible = "vamrs,rk3288-vmarc-som", "rockchip,rk3288";
+
+ vccio_flash: vccio-flash-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_flash";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_io>;
+ };
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vccio_flash>;
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ phy-supply = <&vcc_io>;
+ snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_cec_c0>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int &global_pwroff>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc_io>;
+ vcc9-supply = <&vcc_io>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc5v0_sys>;
+ vcc12-supply = <&vcc_io>;
+ vddio-supply = <&vcc_io>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-ramp-delay = <6000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: DCDC_REG4 {
+ regulator-name = "vcc_io";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_tp: LDO_REG1 {
+ regulator-name = "vcc_tp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_codec: LDO_REG2 {
+ regulator-name = "vcca_codec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_10: LDO_REG3 {
+ regulator-name = "vdd_10";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_wl: LDO_REG4 {
+ regulator-name = "vcc_wl";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd10_lcd: LDO_REG6 {
+ regulator-name = "vdd10_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_18: LDO_REG7 {
+ regulator-name = "vcc_18";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc18_lcd: LDO_REG8 {
+ regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_sd: SWITCH_REG1 {
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_lcd: SWITCH_REG2 {
+ regulator-name = "vcc_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&io_domains {
+ bb-supply = <&vcc_io>;
+ flash0-supply = <&vccio_flash>;
+ gpio1830-supply = <&vcc_18>;
+ gpio30-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&pinctrl {
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+ <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>,
+ <6 RK_PC1 1 &pcfg_pull_up_drv_8ma>,
+ <6 RK_PC2 1 &pcfg_pull_up_drv_8ma>,
+ <6 RK_PC3 1 &pcfg_pull_up_drv_8ma>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
+ };
+ };
+
+ vbus_host {
+ usb1_en_oc: usb1-en-oc {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ vbus_typec {
+ usb0_en_oc: usb0-en-oc {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1 {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&vbus_host {
+ enable-active-high;
+ gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */
+};
+
+&vbus_typec {
+ enable-active-high;
+ gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */
+};
diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts
index acfb7dc..b156a83 100644
--- a/arch/arm/boot/dts/rk3288-vyasa.dts
+++ b/arch/arm/boot/dts/rk3288-vyasa.dts
@@ -78,6 +78,18 @@
vin-supply = <&vcc_io>;
};
+ vcc50_hdmi: vcc50-hdmi {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc50_hdmi";
+ enable-active-high;
+ gpio = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>; /* HDMI_EN */
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc50_hdmi_en>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vsus_5v>;
+ };
+
vusb1_5v: vusb1-5v {
compatible = "regulator-fixed";
regulator-name = "vusb1_5v";
@@ -87,8 +99,6 @@
pinctrl-0 = <&otg_vbus_drv>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
vin-supply = <&vsus_5v>;
};
@@ -115,7 +125,19 @@
};
&cpu0 {
- cpu0-supply = <&vdd_cpu>;
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
};
&emmc {
@@ -150,7 +172,7 @@
};
&hdmi {
- ddc-i2c-bus = <&i2c2>;
+ ddc-i2c-bus = <&i2c5>;
status = "okay";
};
@@ -286,15 +308,15 @@
};
};
- vcc10_lcd: LDO_REG6 {
- regulator-name = "vcc10_lcd";
+ vdd10_lcd: LDO_REG6 {
+ regulator-name = "vdd10_lcd";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
+ regulator-suspend-microvolt = <1000000>;
};
};
@@ -347,7 +369,7 @@
};
};
-&i2c2 {
+&i2c5 {
status = "okay";
};
@@ -404,6 +426,7 @@
};
&usb_otg {
+ vbus-supply = <&vusb1_5v>;
status = "okay";
};
@@ -446,6 +469,12 @@
};
};
+ hdmi {
+ vcc50_hdmi_en: vcc50-hdmi-en {
+ rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int: pmic-int {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 658ceb9..9051fb4 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -7,7 +7,6 @@
#include <dt-bindings/clock/rk3288-cru.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
/ {
@@ -155,7 +154,7 @@
};
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -168,6 +167,7 @@
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC2>;
clock-names = "apb_pclk";
};
@@ -179,6 +179,7 @@
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
status = "disabled";
@@ -191,6 +192,7 @@
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC1>;
clock-names = "apb_pclk";
};
@@ -247,7 +249,7 @@
ports = <&vopl_out>, <&vopb_out>;
};
- sdmmc: dwmmc@ff0c0000 {
+ sdmmc: mmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
@@ -261,7 +263,7 @@
status = "disabled";
};
- sdio0: dwmmc@ff0d0000 {
+ sdio0: mmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
@@ -275,7 +277,7 @@
status = "disabled";
};
- sdio1: dwmmc@ff0e0000 {
+ sdio1: mmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
@@ -289,7 +291,7 @@
status = "disabled";
};
- emmc: dwmmc@ff0f0000 {
+ emmc: mmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
@@ -420,6 +422,8 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 1>, <&dmac_peri 2>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
status = "disabled";
@@ -433,6 +437,8 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 3>, <&dmac_peri 4>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "disabled";
@@ -459,6 +465,8 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 7>, <&dmac_peri 8>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
status = "disabled";
@@ -472,6 +480,8 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac_peri 9>, <&dmac_peri 10>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer>;
status = "disabled";
@@ -567,9 +577,9 @@
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
+ pinctrl-2 = <&otp_pin>;
#thermal-sensor-cells = <1>;
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <95000>;
@@ -601,13 +611,21 @@
reg = <0x0 0xff500000 0x0 0x100>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_USBHOST0>;
- clock-names = "usbhost";
phys = <&usbphy1>;
phy-names = "usb";
status = "disabled";
};
- /* NOTE: ohci@ff520000 doesn't actually work on hardware */
+ /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
+ usb_host0_ohci: usb@ff520000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff520000 0x0 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USBHOST0>;
+ phys = <&usbphy1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
usb_host1: usb@ff540000 {
compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
@@ -644,7 +662,6 @@
reg = <0x0 0xff5c0000 0x0 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HSIC>;
- clock-names = "usbhost";
status = "disabled";
};
@@ -718,7 +735,7 @@
status = "disabled";
};
- bus_intmem@ff700000 {
+ bus_intmem: sram@ff700000 {
compatible = "mmio-sram";
reg = <0x0 0xff700000 0x0 0x18000>;
#address-cells = <1>;
@@ -730,7 +747,7 @@
};
};
- sram@ff720000 {
+ pmu_sram: sram@ff720000 {
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
reg = <0x0 0xff720000 0x0 0x1000>;
};
@@ -946,8 +963,8 @@
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
reg = <0x0 0xff8b0000 0x0 0x10000>;
#sound-dai-cells = <0>;
- clock-names = "hclk", "mclk";
- clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
+ clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
+ clock-names = "mclk", "hclk";
dmas = <&dmac_bus_s 3>;
dma-names = "tx";
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -962,12 +979,10 @@
reg = <0x0 0xff890000 0x0 0x10000>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
+ clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
dma-names = "tx", "rx";
- clock-names = "i2s_hclk", "i2s_clk";
- clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
rockchip,playback-channels = <8>;
@@ -975,7 +990,7 @@
status = "disabled";
};
- crypto: cypto-controller@ff8a0000 {
+ crypto: crypto@ff8a0000 {
compatible = "rockchip,rk3288-crypto";
reg = <0x0 0xff8a0000 0x0 0x4000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
@@ -1023,7 +1038,7 @@
vopb: vop@ff930000 {
compatible = "rockchip,rk3288-vop";
- reg = <0x0 0xff930000 0x0 0x19c>;
+ reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1073,7 +1088,7 @@
vopl: vop@ff940000 {
compatible = "rockchip,rk3288-vop";
- reg = <0x0 0xff940000 0x0 0x19c>;
+ reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1391,6 +1406,9 @@
clocks = <&cru PCLK_EFUSE256>;
clock-names = "pclk_efuse";
+ cpu_id: cpu-id@7 {
+ reg = <0x07 0x10>;
+ };
cpu_leakage: cpu_leakage@17 {
reg = <0x17 0x1>;
};
@@ -1923,7 +1941,7 @@
};
tsadc {
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index bce0b05..859a747 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -32,7 +32,7 @@
spi1 = &spi1;
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -45,6 +45,7 @@
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMA1>;
clock-names = "apb_pclk";
};
@@ -56,6 +57,7 @@
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMA1>;
clock-names = "apb_pclk";
status = "disabled";
@@ -68,6 +70,7 @@
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMA2>;
clock-names = "apb_pclk";
};
@@ -91,7 +94,7 @@
status = "disabled";
};
- L2: l2-cache-controller@10138000 {
+ L2: cache-controller@10138000 {
compatible = "arm,pl310-cache";
reg = <0x10138000 0x1000>;
cache-unified;
@@ -231,7 +234,7 @@
status = "disabled";
};
- mmc0: dwmmc@10214000 {
+ mmc0: mmc@10214000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10214000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -245,7 +248,7 @@
status = "disabled";
};
- mmc1: dwmmc@10218000 {
+ mmc1: mmc@10218000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10218000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -259,7 +262,7 @@
status = "disabled";
};
- emmc: dwmmc@1021c000 {
+ emmc: mmc@1021c000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x1021c000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
new file mode 100644
index 0000000..26b53ea
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Radxa Limited
+ * Copyright (c) 2019 Amarula Solutions(India)
+ */
+
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vbus_host: vbus-host {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_en_oc>;
+ regulator-name = "vbus_host"; /* HOST-5V */
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vbus_typec: vbus-typec {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_en_oc>;
+ regulator-name = "vbus_typec";
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&gmac {
+ assigned-clock-parents = <&clkin_gmac>;
+ clock_in_out = "input";
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rtd1195-horseradish.dts b/arch/arm/boot/dts/rtd1195-horseradish.dts
new file mode 100644
index 0000000..9d06d3d
--- /dev/null
+++ b/arch/arm/boot/dts/rtd1195-horseradish.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Copyright (c) 2019 Andreas Färber
+ */
+
+/dts-v1/;
+
+#include "rtd1195.dtsi"
+
+/ {
+ compatible = "realtek,horseradish", "realtek,rtd1195";
+ model = "Realtek Horseradish EVB";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@a800 {
+ device_type = "memory";
+ reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */
+ <0x18070000 0x00090000>, /* r-bus to NOR flash */
+ <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rtd1195-mele-x1000.dts b/arch/arm/boot/dts/rtd1195-mele-x1000.dts
new file mode 100644
index 0000000..c7951b9
--- /dev/null
+++ b/arch/arm/boot/dts/rtd1195-mele-x1000.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Copyright (c) 2017-2019 Andreas Färber
+ */
+
+/dts-v1/;
+
+#include "rtd1195.dtsi"
+
+/ {
+ compatible = "mele,x1000", "realtek,rtd1195";
+ model = "MeLE X1000";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@a800 {
+ device_type = "memory";
+ reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */
+ <0x18070000 0x00090000>, /* r-bus to NOR flash */
+ <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi
new file mode 100644
index 0000000..2189721
--- /dev/null
+++ b/arch/arm/boot/dts/rtd1195.dtsi
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Copyright (c) 2017-2019 Andreas Färber
+ */
+
+/memreserve/ 0x00000000 0x0000a800; /* boot code */
+/memreserve/ 0x0000a800 0x000f5800;
+/memreserve/ 0x17fff000 0x00001000;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/realtek,rtd1195.h>
+
+/ {
+ compatible = "realtek,rtd1195";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clock-frequency = <1000000000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clock-frequency = <1000000000>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rpc_comm: rpc@b000 {
+ reg = <0x0000b000 0x1000>;
+ };
+
+ audio@1b00000 {
+ reg = <0x01b00000 0x400000>;
+ };
+
+ rpc_ringbuf: rpc@1ffe000 {
+ reg = <0x01ffe000 0x4000>;
+ };
+
+ secure@10000000 {
+ reg = <0x10000000 0x100000>;
+ no-map;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <27000000>;
+ };
+
+ osc27M: osc {
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ #clock-cells = <0>;
+ clock-output-names = "osc27M";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x0000a800>,
+ <0x18000000 0x18000000 0x00070000>,
+ <0x18100000 0x18100000 0x01000000>,
+ <0x80000000 0x80000000 0x80000000>;
+
+ rbus: bus@18000000 {
+ compatible = "simple-bus";
+ reg = <0x18000000 0x70000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000000 0x70000>;
+
+ crt: syscon@0 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x1000>;
+ reg-io-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+ };
+
+ iso: syscon@7000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x7000 0x1000>;
+ reg-io-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7000 0x1000>;
+ };
+
+ sb2: syscon@1a000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x1a000 0x1000>;
+ reg-io-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1a000 0x1000>;
+ };
+
+ misc: syscon@1b000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x1b000 0x1000>;
+ reg-io-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1b000 0x1000>;
+ };
+
+ scpu_wrapper: syscon@1d000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x1d000 0x1000>;
+ reg-io-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1d000 0x1000>;
+ };
+ };
+
+ gic: interrupt-controller@ff011000 {
+ compatible = "arm,cortex-a7-gic";
+ reg = <0xff011000 0x1000>,
+ <0xff012000 0x2000>,
+ <0xff014000 0x2000>,
+ <0xff016000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+ };
+};
+
+&crt {
+ reset1: reset-controller@0 {
+ compatible = "snps,dw-low-reset";
+ reg = <0x0 0x4>;
+ #reset-cells = <1>;
+ };
+
+ reset2: reset-controller@4 {
+ compatible = "snps,dw-low-reset";
+ reg = <0x4 0x4>;
+ #reset-cells = <1>;
+ };
+
+ reset3: reset-controller@8 {
+ compatible = "snps,dw-low-reset";
+ reg = <0x8 0x4>;
+ #reset-cells = <1>;
+ };
+};
+
+&iso {
+ iso_reset: reset-controller@88 {
+ compatible = "snps,dw-low-reset";
+ reg = <0x88 0x4>;
+ #reset-cells = <1>;
+ };
+
+ wdt: watchdog@680 {
+ compatible = "realtek,rtd1295-watchdog";
+ reg = <0x680 0x100>;
+ clocks = <&osc27M>;
+ };
+
+ uart0: serial@800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x800 0x400>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&iso_reset RTD1195_ISO_RSTN_UR0>;
+ clock-frequency = <27000000>;
+ status = "disabled";
+ };
+};
+
+&misc {
+ uart1: serial@200 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x200 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&reset2 RTD1195_RSTN_UR1>;
+ clock-frequency = <27000000>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 5876690..a1a08cb 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -85,7 +85,7 @@
#clock-cells = <0>;
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -97,12 +97,13 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
};
- bus_intmem@10080000 {
+ bus_intmem: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x2000>;
#address-cells = <1>;
@@ -120,7 +121,6 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
dmas = <&pdma 6>, <&pdma 7>;
- #dma-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "disabled";
@@ -136,7 +136,6 @@
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
dmas = <&pdma 4>, <&pdma 5>;
- #dma-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "disabled";
@@ -152,7 +151,6 @@
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
dmas = <&pdma 2>, <&pdma 3>;
- #dma-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "disabled";
@@ -208,7 +206,6 @@
clock-names = "spiclk", "apb_pclk";
dmas = <&pdma 8>, <&pdma 9>;
dma-names = "tx", "rx";
- #dma-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -355,9 +352,9 @@
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
+ pinctrl-2 = <&otp_pin>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
rockchip,hw-tshut-temp = <120000>;
@@ -370,7 +367,6 @@
reg = <0x1038c000 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
- clock-frequency = <1000000>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
status = "disabled";
@@ -456,7 +452,7 @@
#reset-cells = <1>;
};
- emmc: dwmmc@30110000 {
+ emmc: mmc@30110000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30110000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
@@ -468,7 +464,7 @@
status = "disabled";
};
- sdio: dwmmc@30120000 {
+ sdio: mmc@30120000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30120000 0x4000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@@ -480,7 +476,7 @@
status = "disabled";
};
- sdmmc: dwmmc@30130000 {
+ sdmmc: mmc@30130000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30130000 0x4000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
@@ -499,7 +495,6 @@
reg = <0x30140000 0x20000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy>;
- clock-names = "usbhost", "utmi";
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -510,7 +505,6 @@
reg = <0x30160000 0x20000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy>;
- clock-names = "usbhost", "utmi";
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -527,7 +521,6 @@
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
status = "disabled";
@@ -736,7 +729,7 @@
<0 RK_PC6 3 &pcfg_pull_none>;
};
- i2c2m1_gpio: i2c2m1-gpio {
+ i2c2m1_pins: i2c2m1-pins {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -748,7 +741,7 @@
<1 RK_PD4 2 &pcfg_pull_none>;
};
- i2c2m05v_gpio: i2c2m05v-gpio {
+ i2c2m05v_pins: i2c2m05v-pins {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -875,7 +868,7 @@
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
};
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -894,7 +887,7 @@
rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
};
- uart0_rts_gpio: uart0-rts-gpio {
+ uart0_rts_pin: uart0-rts-pin {
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index cb371bf..47626ed 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * SAMSUNG SMDK2416 board device tree source
+ * Samsung SMDK2416 board device tree source
*
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
*/
@@ -17,18 +17,11 @@
reg = <0x30000000 0x4000000>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- xti: xti@0 {
- compatible = "fixed-clock";
- reg = <0>;
- clock-frequency = <12000000>;
- clock-output-names = "xti";
- #clock-cells = <0>;
- };
+ xti: clock-0 {
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ clock-output-names = "xti";
+ #clock-cells = <0>;
};
};
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index 6adf64e..4f084f4 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -18,13 +18,14 @@
};
cpus {
- cpu {
- compatible = "arm,arm926ej-s";
- };
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
- interrupt-controller@4a000000 {
- compatible = "samsung,s3c2416-irq";
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ reg = <0x0>;
+ };
};
clocks: clock-controller@4c000000 {
@@ -33,39 +34,6 @@
#clock-cells = <1>;
};
- pinctrl@56000000 {
- compatible = "samsung,s3c2416-pinctrl";
- };
-
- timer@51000000 {
- clocks = <&clocks PCLK_PWM>;
- clock-names = "timers";
- };
-
- uart_0: serial@50000000 {
- compatible = "samsung,s3c2440-uart";
- clock-names = "uart", "clk_uart_baud2",
- "clk_uart_baud3";
- clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
- <&clocks SCLK_UART>;
- };
-
- uart_1: serial@50004000 {
- compatible = "samsung,s3c2440-uart";
- clock-names = "uart", "clk_uart_baud2",
- "clk_uart_baud3";
- clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
- <&clocks SCLK_UART>;
- };
-
- uart_2: serial@50008000 {
- compatible = "samsung,s3c2440-uart";
- clock-names = "uart", "clk_uart_baud2",
- "clk_uart_baud3";
- clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
- <&clocks SCLK_UART>;
- };
-
uart_3: serial@5000c000 {
compatible = "samsung,s3c2440-uart";
reg = <0x5000C000 0x4000>;
@@ -98,22 +66,59 @@
<&clocks MUX_HSMMC1>;
status = "disabled";
};
+};
- watchdog: watchdog@53000000 {
- interrupts = <1 9 27 3>;
- clocks = <&clocks PCLK_WDT>;
- clock-names = "watchdog";
- };
+&i2c {
+ compatible = "samsung,s3c2440-i2c";
+ clocks = <&clocks PCLK_I2C0>;
+ clock-names = "i2c";
+};
- rtc: rtc@57000000 {
- compatible = "samsung,s3c2416-rtc";
- clocks = <&clocks PCLK_RTC>;
- clock-names = "rtc";
- };
+&intc {
+ compatible = "samsung,s3c2416-irq";
+};
- i2c@54000000 {
- compatible = "samsung,s3c2440-i2c";
- clocks = <&clocks PCLK_I2C0>;
- clock-names = "i2c";
- };
+&pinctrl_0 {
+ compatible = "samsung,s3c2416-pinctrl";
+};
+
+&rtc {
+ compatible = "samsung,s3c2416-rtc";
+ clocks = <&clocks PCLK_RTC>;
+ clock-names = "rtc";
+};
+
+&timer {
+ clocks = <&clocks PCLK_PWM>;
+ clock-names = "timers";
+};
+
+&uart_0 {
+ compatible = "samsung,s3c2440-uart";
+ clock-names = "uart", "clk_uart_baud2",
+ "clk_uart_baud3";
+ clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
+ <&clocks SCLK_UART>;
+};
+
+&uart_1 {
+ compatible = "samsung,s3c2440-uart";
+ clock-names = "uart", "clk_uart_baud2",
+ "clk_uart_baud3";
+ clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
+ <&clocks SCLK_UART>;
+};
+
+&uart_2 {
+ compatible = "samsung,s3c2440-uart";
+ clock-names = "uart", "clk_uart_baud2",
+ "clk_uart_baud3";
+ clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
+ <&clocks SCLK_UART>;
+};
+
+&watchdog {
+ interrupts = <1 9 27 3>;
+ clocks = <&clocks PCLK_WDT>;
+ clock-names = "watchdog";
};
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
index 6d8dd3c..06f82c7 100644
--- a/arch/arm/boot/dts/s3c24xx.dtsi
+++ b/arch/arm/boot/dts/s3c24xx.dtsi
@@ -13,12 +13,12 @@
aliases {
pinctrl0 = &pinctrl_0;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
+ serial0 = &uart_0;
+ serial1 = &uart_1;
+ serial2 = &uart_2;
};
- intc:interrupt-controller@4a000000 {
+ intc: interrupt-controller@4a000000 {
compatible = "samsung,s3c2410-irq";
reg = <0x4a000000 0x100>;
interrupt-controller;
@@ -39,49 +39,49 @@
};
};
- timer@51000000 {
+ timer: pwm@51000000 {
compatible = "samsung,s3c2410-pwm";
reg = <0x51000000 0x1000>;
interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>;
- #pwm-cells = <4>;
+ #pwm-cells = <3>;
};
- uart0: serial@50000000 {
+ uart_0: serial@50000000 {
compatible = "samsung,s3c2410-uart";
reg = <0x50000000 0x4000>;
interrupts = <1 28 0 4>, <1 28 1 4>;
status = "disabled";
};
- uart1: serial@50004000 {
+ uart_1: serial@50004000 {
compatible = "samsung,s3c2410-uart";
reg = <0x50004000 0x4000>;
interrupts = <1 23 3 4>, <1 23 4 4>;
status = "disabled";
};
- uart2: serial@50008000 {
+ uart_2: serial@50008000 {
compatible = "samsung,s3c2410-uart";
reg = <0x50008000 0x4000>;
interrupts = <1 15 6 4>, <1 15 7 4>;
status = "disabled";
};
- watchdog@53000000 {
+ watchdog: watchdog@53000000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x53000000 0x100>;
interrupts = <0 0 9 3>;
status = "disabled";
};
- rtc@57000000 {
+ rtc: rtc@57000000 {
compatible = "samsung,s3c2410-rtc";
reg = <0x57000000 0x100>;
interrupts = <0 0 30 3>, <0 0 8 3>;
status = "disabled";
};
- i2c@54000000 {
+ i2c: i2c@54000000 {
compatible = "samsung,s3c2410-i2c";
reg = <0x54000000 0x100>;
interrupts = <0 0 27 3>;
diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts
index 1aeac33..285555b 100644
--- a/arch/arm/boot/dts/s3c6410-mini6410.dts
+++ b/arch/arm/boot/dts/s3c6410-mini6410.dts
@@ -28,29 +28,21 @@
bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- fin_pll: oscillator@0 {
- compatible = "fixed-clock";
- reg = <0>;
- clock-frequency = <12000000>;
- clock-output-names = "fin_pll";
- #clock-cells = <0>;
- };
-
- xusbxti: oscillator@1 {
- compatible = "fixed-clock";
- reg = <1>;
- clock-output-names = "xusbxti";
- clock-frequency = <48000000>;
- #clock-cells = <0>;
- };
+ fin_pll: oscillator-0 {
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
};
- srom-cs1@18000000 {
+ xusbxti: oscillator-1 {
+ compatible = "fixed-clock";
+ clock-output-names = "xusbxti";
+ clock-frequency = <48000000>;
+ #clock-cells = <0>;
+ };
+
+ srom-cs1-bus@18000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts
index 3bf6c45..69c9ec4 100644
--- a/arch/arm/boot/dts/s3c6410-smdk6410.dts
+++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts
@@ -4,7 +4,7 @@
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
- * Device tree source file for SAMSUNG SMDK6410 board which is based on
+ * Device tree source file for Samsung SMDK6410 board which is based on
* Samsung's S3C6410 SoC.
*/
@@ -16,7 +16,7 @@
#include "s3c6410.dtsi"
/ {
- model = "SAMSUNG SMDK6410 board based on S3C6410";
+ model = "Samsung SMDK6410 board based on S3C6410";
compatible = "samsung,mini6410", "samsung,s3c6410";
memory@50000000 {
@@ -28,29 +28,21 @@
bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- fin_pll: oscillator@0 {
- compatible = "fixed-clock";
- reg = <0>;
- clock-frequency = <12000000>;
- clock-output-names = "fin_pll";
- #clock-cells = <0>;
- };
-
- xusbxti: oscillator@1 {
- compatible = "fixed-clock";
- reg = <1>;
- clock-output-names = "xusbxti";
- clock-frequency = <48000000>;
- #clock-cells = <0>;
- };
+ fin_pll: oscillator-0 {
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
};
- srom-cs1@18000000 {
+ xusbxti: oscillator-1 {
+ compatible = "fixed-clock";
+ clock-output-names = "xusbxti";
+ clock-frequency = <48000000>;
+ #clock-cells = <0>;
+ };
+
+ srom-cs1-bus@18000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi
index 2e611df..cb11a87 100644
--- a/arch/arm/boot/dts/s3c64xx.dtsi
+++ b/arch/arm/boot/dts/s3c64xx.dtsi
@@ -34,7 +34,7 @@
cpu@0 {
device_type = "cpu";
- compatible = "arm,arm1176jzf-s", "arm,arm1176";
+ compatible = "arm,arm1176jzf-s";
reg = <0x0>;
};
};
diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts
index 14969b6..8e57e5a 100644
--- a/arch/arm/boot/dts/s5pv210-aquila.dts
+++ b/arch/arm/boot/dts/s5pv210-aquila.dts
@@ -11,6 +11,7 @@
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
@@ -32,42 +33,40 @@
0x40000000 0x18000000>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ pmic_ap_clk: clock-0 {
+ /* Workaround for missing clock on PMIC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
- vtf_reg: fixed-regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "V_TF_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&mp05 4 0>;
- enable-active-high;
- };
+ vtf_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_TF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&mp05 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- pda_reg: fixed-regulator@1 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1.8V_PDA";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- reg = <1>;
- };
+ pda_reg: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1.8V_PDA";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
- bat_reg: fixed-regulator@2 {
- compatible = "regulator-fixed";
- regulator-name = "V_BAT";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
- reg = <2>;
- };
+ bat_reg: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_BAT";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
};
i2c_pmic: i2c-pmic {
compatible = "i2c-gpio";
- gpios = <&gpj4 0 0>, /* sda */
- <&gpj4 3 0>; /* scl */
+ sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
@@ -77,13 +76,13 @@
reg = <0x66>;
max8998,pmic-buck1-default-dvs-idx = <0>;
- max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>,
- <&gph0 4 0>;
+ max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>,
+ <&gph0 4 GPIO_ACTIVE_HIGH>;
max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
<1200000>, <1200000>;
max8998,pmic-buck2-default-dvs-idx = <0>;
- max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>;
+ max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>;
max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;
regulators {
@@ -228,6 +227,11 @@
regulator-always-on;
};
+ ap32khz_reg: EN32KHz-AP {
+ regulator-name = "32KHz AP";
+ regulator-always-on;
+ };
+
vichg_reg: ENVICHG {
regulator-name = "VICHG";
};
@@ -326,6 +330,11 @@
status = "okay";
};
+&rtc {
+ clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
+};
+
&sdhci0 {
bus-width = <4>;
non-removable;
diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi
index d419b77..bd4450d 100644
--- a/arch/arm/boot/dts/s5pv210-aries.dtsi
+++ b/arch/arm/boot/dts/s5pv210-aries.dtsi
@@ -11,9 +11,15 @@
/ {
compatible = "samsung,aries", "samsung,s5pv210";
- aliases {
+ aliases: aliases {
+ i2c4 = &i2c_sound;
+ i2c5 = &i2c_accel;
i2c6 = &i2c_pmic;
+ i2c7 = &i2c_musb;
i2c9 = &i2c_fuel;
+ i2c10 = &i2c_touchkey;
+ i2c11 = &i2c_prox;
+ i2c12 = &i2c_magnetometer;
};
memory@30000000 {
@@ -41,11 +47,50 @@
};
};
+ pmic_ap_clk: clock-0 {
+ /* Workaround for missing clock on PMIC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ bt_codec: bt_sco {
+ compatible = "linux,bt-sco";
+ #sound-dai-cells = <0>;
+ };
+
vibrator_pwr: regulator-fixed-0 {
compatible = "regulator-fixed";
regulator-name = "vibrator-en";
enable-active-high;
gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_ena>;
+ };
+
+ touchkey_vdd: regulator-fixed-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VTOUCH_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpj3 2 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchkey_vdd_ena>;
+ };
+
+ gp2a_vled: regulator-fixed-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VLED";
+ enable-active-high;
+ gpio = <&gpj1 4 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gp2a_power>;
};
wifi_pwrseq: wifi-pwrseq {
@@ -57,7 +102,75 @@
power-off-delay-us = <500>;
};
- i2c_pmic: i2c-gpio-0 {
+ i2c_sound: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&mp05 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&mp05 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sound_i2c_pins>;
+
+ wm8994: wm8994@1a {
+ compatible = "wlf,wm8994";
+ reg = <0x1a>;
+
+ #sound-dai-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ clocks = <&clocks MOUT_CLKOUT>;
+ clock-names = "MCLK1";
+
+ AVDD2-supply = <&buck3_reg>;
+ DBVDD-supply = <&buck3_reg>;
+ CPVDD-supply = <&buck3_reg>;
+ SPKVDD1-supply = <&buck3_reg>;
+ SPKVDD2-supply = <&buck3_reg>;
+
+ wlf,gpio-cfg = <0xa101 0x8100 0x0100 0x0100 0x8100
+ 0xa101 0x0100 0x8100 0x0100 0x0100
+ 0x0100>;
+
+ wlf,ldo1ena = <&gpf3 4 GPIO_ACTIVE_HIGH>;
+ wlf,ldo2ena = <&gpf3 4 GPIO_ACTIVE_HIGH>;
+
+ wlf,lineout1-se;
+ wlf,lineout2-se;
+
+ assigned-clocks = <&clocks MOUT_CLKOUT>;
+ assigned-clock-rates = <0>;
+ assigned-clock-parents = <&xusbxti>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&codec_ldo>;
+ };
+ };
+
+ i2c_accel: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpj3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpj3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_i2c_pins>;
+
+ accelerometer@38 {
+ compatible = "bosch,bma023";
+ reg = <0x38>;
+
+ vdd-supply = <&ldo9_reg>;
+ vddio-supply = <&ldo9_reg>;
+ };
+ };
+
+ i2c_pmic: i2c-gpio-2 {
compatible = "i2c-gpio";
sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
@@ -65,6 +178,9 @@
#address-cells = <1>;
#size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_i2c_pins>;
+
pmic@66 {
compatible = "maxim,max8998";
reg = <0x66>;
@@ -81,6 +197,9 @@
max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>;
max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_dvs_pins &pmic_irq>;
+
regulators {
ldo2_reg: LDO2 {
regulator-name = "VALIVE_1.2V";
@@ -107,7 +226,6 @@
regulator-name = "VADC_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
@@ -134,8 +252,6 @@
regulator-name = "VLCD_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- /* Till we get panel driver */
- regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
@@ -234,8 +350,6 @@
regulator-name = "VCC_3.0V_LCD";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
- /* Till we get panel driver */
- regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
@@ -306,7 +420,29 @@
};
};
- i2c_fuel: i2c-gpio-1 {
+ i2c_musb: i2c-gpio-3 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpj3 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpj3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&musb_i2c_pins>;
+
+ fsa9480: musb@25 {
+ compatible = "fcs,fsa9480";
+ reg = <0x25>;
+ interrupt-parent = <&gph2>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&musb_irq>;
+ };
+ };
+
+ i2c_fuel: i2c-gpio-4 {
compatible = "i2c-gpio";
sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
@@ -314,14 +450,85 @@
#address-cells = <1>;
#size-cells = <0>;
- fuelgauge@36 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fg_i2c_pins>;
+
+ fg: fuelgauge@36 {
compatible = "maxim,max17040";
- interrupt-parent = <&vic0>;
- interrupts = <7>;
reg = <0x36>;
};
};
+ i2c_touchkey: i2c-gpio-5 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpj3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpj3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchkey_i2c_pins>;
+
+ touchkey@20 {
+ compatible = "cypress,aries-touchkey";
+ reg = <0x20>;
+ vdd-supply = <&touchkey_vdd>;
+ vcc-supply = <&buck3_reg>;
+ linux,keycodes = <KEY_MENU KEY_BACK
+ KEY_HOMEPAGE KEY_SEARCH>;
+ interrupt-parent = <&gpj4>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchkey_irq>;
+ };
+ };
+
+ i2c_prox: i2c-gpio-6 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpg2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpg0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&prox_i2c_pins>;
+
+ light-sensor@44 {
+ compatible = "sharp,gp2ap002a00f";
+ reg = <0x44>;
+ interrupt-parent = <&gph0>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&gp2a_vled>;
+ vio-supply = <&gp2a_vled>;
+ io-channels = <&gp2a_shunt>;
+ io-channel-names = "alsout";
+ sharp,proximity-far-hysteresis = /bits/ 8 <0x40>;
+ sharp,proximity-close-hysteresis = /bits/ 8 <0x20>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gp2a_irq>;
+ };
+ };
+
+ i2c_magnetometer: i2c-gpio-7 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpj0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpj0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&magnetometer_i2c_pins>;
+
+ status = "disabled";
+
+ /* Yamaha yas529 magnetometer, no mainline binding */
+ };
+
vibrator: pwm-vibrator {
compatible = "pwm-vibrator";
pwms = <&pwm 1 44642 0>;
@@ -337,6 +544,53 @@
offset = <0x681c>; /* PS_HOLD_CONTROL */
value = <0x5200>;
};
+
+ spi_lcd: spi-2 {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sck-gpios = <&mp04 1 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&mp04 3 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&mp01 1 GPIO_ACTIVE_HIGH>;
+ num-chipselects = <1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_spi_pins>;
+
+ panel@0 {
+ compatible = "samsung,s6e63m0";
+ reg = <0>;
+ reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>;
+ vdd3-supply = <&ldo7_reg>;
+ vci-supply = <&ldo17_reg>;
+ spi-cs-high;
+ spi-max-frequency = <1200000>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_rst>;
+
+ port {
+ lcd_ep: endpoint {
+ remote-endpoint = <&fimd_ep>;
+ };
+ };
+ };
+ };
+};
+
+&adc {
+ vdd-supply = <&ldo4_reg>;
+
+ status = "okay";
+
+ gp2a_shunt: current-sense-shunt {
+ compatible = "current-sense-shunt";
+ io-channels = <&adc 9>;
+ shunt-resistor-micro-ohms = <47000000>; /* 47 ohms */
+ #io-channel-cells = <0>;
+ io-channel-ranges;
+ };
};
&fimd {
@@ -347,18 +601,13 @@
samsung,invert-vden;
samsung,invert-vclk;
- display-timings {
- timing-0 {
- /* 480x800@60Hz */
- clock-frequency = <25628040>;
- hactive = <480>;
- vactive = <800>;
- hfront-porch = <16>;
- hback-porch = <16>;
- hsync-len = <2>;
- vfront-porch = <28>;
- vback-porch = <1>;
- vsync-len = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@3 {
+ reg = <3>;
+ fimd_ep: endpoint {
+ remote-endpoint = <&lcd_ep>;
};
};
};
@@ -387,11 +636,23 @@
};
};
+&i2s0 {
+ dmas = <&pdma0 9>, <&pdma0 10>, <&pdma0 11>;
+ status = "okay";
+};
+
&mfc {
memory-region = <&mfc_left>, <&mfc_right>;
};
&pinctrl0 {
+ bt_reset: bt-reset {
+ samsung,pins = "gpb-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
wlan_bt_en: wlan-bt-en {
samsung,pins = "gpb-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
@@ -399,12 +660,52 @@
samsung,pin-val = <1>;
};
+ codec_ldo: codec-ldo {
+ samsung,pins = "gpf3-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ };
+
+ prox_i2c_pins: gp2a-i2c-pins {
+ samsung,pins = "gpg0-2", "gpg2-2";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
wlan_gpio_rst: wlan-gpio-rst {
samsung,pins = "gpg1-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
+ bt_wake: bt-wake {
+ samsung,pins = "gpg3-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ };
+
+ gp2a_irq: gp2a-irq {
+ samsung,pins = "gph0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_DOWN>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pmic_dvs_pins: pmic-dvs-pins {
+ samsung,pins = "gph0-3", "gph0-4", "gph0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ samsung,pin-val = <0>;
+ };
+
+ pmic_irq: pmic-irq {
+ samsung,pins = "gph0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
wifi_host_wake: wifi-host-wake {
samsung,pins = "gph2-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
@@ -419,6 +720,13 @@
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
+ musb_irq: musq-irq {
+ samsung,pins = "gph2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
tf_detect: tf-detect {
samsung,pins = "gph3-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
@@ -432,18 +740,103 @@
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
+ magnetometer_i2c_pins: yas529-i2c-pins {
+ samsung,pins = "gpj0-0", "gpj0-1";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
ts_irq: ts-irq {
samsung,pins = "gpj0-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
+
+ vibrator_ena: vibrator-ena {
+ samsung,pins = "gpj1-1";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ gp2a_power: gp2a-power {
+ samsung,pins = "gpj1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ touchkey_i2c_pins: touchkey-i2c-pins {
+ samsung,pins = "gpj3-0", "gpj3-1";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ touchkey_vdd_ena: touchkey-vdd-ena {
+ samsung,pins = "gpj3-2";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ musb_i2c_pins: musb-i2c-pins {
+ samsung,pins = "gpj3-4", "gpj3-5";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ accel_i2c_pins: accel-i2c-pins {
+ samsung,pins = "gpj3-6", "gpj3-7";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ pmic_i2c_pins: pmic-i2c-pins {
+ samsung,pins = "gpj4-0", "gpj4-3";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ touchkey_irq: touchkey-irq {
+ samsung,pins = "gpj4-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ lcd_spi_pins: spi-lcd-pins {
+ samsung,pins = "mp01-1", "mp04-1", "mp04-3";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ fg_i2c_pins: fg-i2c-pins {
+ samsung,pins = "mp05-0", "mp05-1";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ sound_i2c_pins: sound-i2c-pins {
+ samsung,pins = "mp05-2", "mp05-3";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ panel_rst: panel-rst {
+ samsung,pins = "mp05-5";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
};
&pwm {
samsung,pwm-outputs = <1>;
};
+&rtc {
+ clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
+};
+
&sdhci1 {
#address-cells = <1>;
#size-cells = <0>;
@@ -460,6 +853,10 @@
non-removable;
status = "okay";
+ assigned-clocks = <&clocks MOUT_MMC1>, <&clocks SCLK_MMC1>;
+ assigned-clock-rates = <0>, <50000000>;
+ assigned-clock-parents = <&clocks MOUT_MPLL>;
+
wlan@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
@@ -476,19 +873,30 @@
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>;
pinctrl-names = "default";
status = "okay";
+
+ assigned-clocks = <&clocks MOUT_MMC2>, <&clocks SCLK_MMC2>;
+ assigned-clock-rates = <0>, <50000000>;
+ assigned-clock-parents = <&clocks MOUT_MPLL>;
};
&uart0 {
+ assigned-clocks = <&clocks MOUT_UART0>, <&clocks SCLK_UART0>;
+ assigned-clock-rates = <0>, <111166667>;
+ assigned-clock-parents = <&clocks MOUT_MPLL>;
+
status = "okay";
bluetooth {
- compatible = "brcm,bcm43438-bt";
- max-speed = <115200>;
+ compatible = "brcm,bcm4329-bt";
+ max-speed = <3000000>;
pinctrl-names = "default";
- pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake>;
+ pinctrl-0 = <&uart0_data &uart0_fctl &bt_host_wake
+ &bt_reset &bt_wake>;
shutdown-gpios = <&gpb 3 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpg3 4 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gph2 5 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&gph2>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
};
};
diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts
index 07a8d9b..b47d830 100644
--- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts
+++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts
@@ -35,4 +35,368 @@
linux,code = <KEY_VOLUMEUP>;
};
};
+
+ headset_micbias_reg: regulator-fixed-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "Headset_Micbias";
+ gpio = <&gpj2 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&headset_micbias_ena>;
+ };
+
+ main_micbias_reg: regulator-fixed-4 {
+ compatible = "regulator-fixed";
+ regulator-name = "Main_Micbias";
+ gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_micbias_ena>;
+ };
+
+ sound {
+ compatible = "samsung,fascinate4g-wm8994";
+
+ model = "Fascinate4G";
+
+ extcon = <&fsa9480>;
+
+ main-micbias-supply = <&main_micbias_reg>;
+ headset-micbias-supply = <&headset_micbias_reg>;
+
+ earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>;
+
+ io-channels = <&adc 3>;
+ io-channel-names = "headset-detect";
+ headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_HIGH>;
+ headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>;
+
+ samsung,audio-routing =
+ "HP", "HPOUT1L",
+ "HP", "HPOUT1R",
+
+ "SPK", "SPKOUTLN",
+ "SPK", "SPKOUTLP",
+
+ "RCV", "HPOUT2N",
+ "RCV", "HPOUT2P",
+
+ "LINE", "LINEOUT2N",
+ "LINE", "LINEOUT2P",
+
+ "IN1LP", "Main Mic",
+ "IN1LN", "Main Mic",
+
+ "IN1RP", "Headset Mic",
+ "IN1RN", "Headset Mic",
+
+ "Modem Out", "Modem TX",
+ "Modem RX", "Modem In",
+
+ "Bluetooth SPK", "TX",
+ "RX", "Bluetooth Mic";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&headset_det &earpath_sel>;
+
+ cpu {
+ sound-dai = <&i2s0>, <&bt_codec>;
+ };
+
+ codec {
+ sound-dai = <&wm8994>;
+ };
+ };
+};
+
+&fg {
+ compatible = "maxim,max77836-battery";
+
+ interrupt-parent = <&gph3>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fg_irq>;
+};
+
+&pinctrl0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep_cfg>;
+
+ headset_det: headset-det {
+ samsung,pins = "gph0-6", "gph3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ };
+
+ fg_irq: fg-irq {
+ samsung,pins = "gph3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ headset_micbias_ena: headset-micbias-ena {
+ samsung,pins = "gpj2-5";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ earpath_sel: earpath-sel {
+ samsung,pins = "gpj2-6";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ main_micbias_ena: main-micbias-ena {
+ samsung,pins = "gpj4-2";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ /* Based on vendor kernel v2.6.35.7 */
+ sleep_cfg: sleep-cfg {
+ PIN_SLP(gpa0-0, PREV, NONE);
+ PIN_SLP(gpa0-1, PREV, NONE);
+ PIN_SLP(gpa0-2, PREV, NONE);
+ PIN_SLP(gpa0-3, OUT1, NONE);
+ PIN_SLP(gpa0-4, PREV, NONE);
+ PIN_SLP(gpa0-5, PREV, NONE);
+ PIN_SLP(gpa0-6, PREV, NONE);
+ PIN_SLP(gpa0-7, PREV, NONE);
+
+ PIN_SLP(gpa1-0, INPUT, DOWN);
+ PIN_SLP(gpa1-1, OUT0, NONE);
+ PIN_SLP(gpa1-2, INPUT, DOWN);
+ PIN_SLP(gpa1-3, OUT0, NONE);
+
+ PIN_SLP(gpb-0, OUT0, NONE);
+ PIN_SLP(gpb-1, OUT1, NONE);
+ PIN_SLP(gpb-2, OUT0, NONE);
+ PIN_SLP(gpb-3, PREV, NONE);
+ PIN_SLP(gpb-4, INPUT, NONE);
+ PIN_SLP(gpb-5, PREV, NONE);
+ PIN_SLP(gpb-6, INPUT, DOWN);
+ PIN_SLP(gpb-7, OUT0, NONE);
+
+ PIN_SLP(gpc0-0, OUT0, NONE);
+ PIN_SLP(gpc0-1, INPUT, DOWN);
+ PIN_SLP(gpc0-2, OUT0, NONE);
+ PIN_SLP(gpc0-3, INPUT, DOWN);
+ PIN_SLP(gpc0-4, OUT0, NONE);
+
+ PIN_SLP(gpc1-0, INPUT, DOWN);
+ PIN_SLP(gpc1-1, INPUT, DOWN);
+ PIN_SLP(gpc1-2, INPUT, DOWN);
+ PIN_SLP(gpc1-3, INPUT, DOWN);
+ PIN_SLP(gpc1-4, INPUT, DOWN);
+
+ PIN_SLP(gpd0-0, INPUT, DOWN);
+ PIN_SLP(gpd0-1, OUT0, NONE);
+ PIN_SLP(gpd0-2, INPUT, DOWN);
+ PIN_SLP(gpd0-3, INPUT, DOWN);
+
+ PIN_SLP(gpd1-0, INPUT, NONE);
+ PIN_SLP(gpd1-1, INPUT, NONE);
+ PIN_SLP(gpd1-2, INPUT, DOWN);
+ PIN_SLP(gpd1-3, INPUT, DOWN);
+ PIN_SLP(gpd1-4, INPUT, DOWN);
+ PIN_SLP(gpd1-5, INPUT, DOWN);
+
+ PIN_SLP(gpe0-0, INPUT, DOWN);
+ PIN_SLP(gpe0-1, INPUT, DOWN);
+ PIN_SLP(gpe0-2, INPUT, DOWN);
+ PIN_SLP(gpe0-3, INPUT, DOWN);
+ PIN_SLP(gpe0-4, INPUT, DOWN);
+ PIN_SLP(gpe0-5, INPUT, DOWN);
+ PIN_SLP(gpe0-6, INPUT, DOWN);
+ PIN_SLP(gpe0-7, INPUT, DOWN);
+
+ PIN_SLP(gpe1-0, INPUT, DOWN);
+ PIN_SLP(gpe1-1, INPUT, DOWN);
+ PIN_SLP(gpe1-2, INPUT, DOWN);
+ PIN_SLP(gpe1-3, OUT0, NONE);
+ PIN_SLP(gpe1-4, INPUT, DOWN);
+
+ PIN_SLP(gpf0-0, OUT0, NONE);
+ PIN_SLP(gpf0-1, OUT0, NONE);
+ PIN_SLP(gpf0-2, OUT0, NONE);
+ PIN_SLP(gpf0-3, OUT0, NONE);
+ PIN_SLP(gpf0-4, OUT0, NONE);
+ PIN_SLP(gpf0-5, OUT0, NONE);
+ PIN_SLP(gpf0-6, OUT0, NONE);
+ PIN_SLP(gpf0-7, OUT0, NONE);
+
+ PIN_SLP(gpf1-0, OUT0, NONE);
+ PIN_SLP(gpf1-1, OUT0, NONE);
+ PIN_SLP(gpf1-2, OUT0, NONE);
+ PIN_SLP(gpf1-3, OUT0, NONE);
+ PIN_SLP(gpf1-4, OUT0, NONE);
+ PIN_SLP(gpf1-5, OUT0, NONE);
+ PIN_SLP(gpf1-6, OUT0, NONE);
+ PIN_SLP(gpf1-7, OUT0, NONE);
+
+ PIN_SLP(gpf2-0, OUT0, NONE);
+ PIN_SLP(gpf2-1, OUT0, NONE);
+ PIN_SLP(gpf2-2, OUT0, NONE);
+ PIN_SLP(gpf2-3, OUT0, NONE);
+ PIN_SLP(gpf2-4, OUT0, NONE);
+ PIN_SLP(gpf2-5, OUT0, NONE);
+ PIN_SLP(gpf2-6, OUT0, NONE);
+ PIN_SLP(gpf2-7, OUT0, NONE);
+
+ PIN_SLP(gpf3-0, OUT0, NONE);
+ PIN_SLP(gpf3-1, OUT0, NONE);
+ PIN_SLP(gpf3-2, OUT0, NONE);
+ PIN_SLP(gpf3-3, OUT0, NONE);
+ PIN_SLP(gpf3-4, PREV, NONE);
+ PIN_SLP(gpf3-5, INPUT, DOWN);
+
+ PIN_SLP(gpg0-0, INPUT, DOWN);
+ PIN_SLP(gpg0-1, INPUT, DOWN);
+ PIN_SLP(gpg0-2, INPUT, NONE);
+ PIN_SLP(gpg0-3, INPUT, DOWN);
+ PIN_SLP(gpg0-4, INPUT, DOWN);
+ PIN_SLP(gpg0-5, INPUT, DOWN);
+ PIN_SLP(gpg0-6, INPUT, DOWN);
+
+ PIN_SLP(gpg1-0, OUT0, NONE);
+ PIN_SLP(gpg1-1, OUT1, NONE);
+ PIN_SLP(gpg1-2, PREV, NONE);
+ PIN_SLP(gpg1-3, OUT1, NONE);
+ PIN_SLP(gpg1-4, OUT1, NONE);
+ PIN_SLP(gpg1-5, OUT1, NONE);
+ PIN_SLP(gpg1-6, OUT1, NONE);
+
+ PIN_SLP(gpg2-0, OUT0, NONE);
+ PIN_SLP(gpg2-1, OUT0, NONE);
+ PIN_SLP(gpg2-2, INPUT, NONE);
+ PIN_SLP(gpg2-3, OUT0, NONE);
+ PIN_SLP(gpg2-4, OUT0, NONE);
+ PIN_SLP(gpg2-5, OUT0, NONE);
+ PIN_SLP(gpg2-6, OUT0, NONE);
+
+ PIN_SLP(gpg3-0, PREV, UP);
+ PIN_SLP(gpg3-1, PREV, UP);
+ PIN_SLP(gpg3-2, INPUT, NONE);
+ PIN_SLP(gpg3-3, INPUT, DOWN);
+ PIN_SLP(gpg3-4, OUT0, NONE);
+ PIN_SLP(gpg3-5, OUT0, NONE);
+ PIN_SLP(gpg3-6, INPUT, DOWN);
+
+ PIN_SLP(gpi-0, PREV, NONE);
+ PIN_SLP(gpi-1, INPUT, DOWN);
+ PIN_SLP(gpi-2, PREV, NONE);
+ PIN_SLP(gpi-3, PREV, NONE);
+ PIN_SLP(gpi-4, PREV, NONE);
+ PIN_SLP(gpi-5, INPUT, DOWN);
+ PIN_SLP(gpi-6, INPUT, DOWN);
+
+ PIN_SLP(gpj0-0, INPUT, NONE);
+ PIN_SLP(gpj0-1, INPUT, NONE);
+ PIN_SLP(gpj0-2, INPUT, NONE);
+ PIN_SLP(gpj0-3, INPUT, NONE);
+ PIN_SLP(gpj0-4, INPUT, NONE);
+ PIN_SLP(gpj0-5, INPUT, DOWN);
+ PIN_SLP(gpj0-6, OUT0, NONE);
+ PIN_SLP(gpj0-7, INPUT, NONE);
+
+ PIN_SLP(gpj1-0, OUT1, NONE);
+ PIN_SLP(gpj1-1, OUT0, NONE);
+ PIN_SLP(gpj1-2, INPUT, DOWN);
+ PIN_SLP(gpj1-3, PREV, NONE);
+ PIN_SLP(gpj1-4, PREV, NONE);
+ PIN_SLP(gpj1-5, OUT0, NONE);
+
+ PIN_SLP(gpj2-0, INPUT, DOWN);
+ PIN_SLP(gpj2-1, INPUT, DOWN);
+ PIN_SLP(gpj2-2, OUT0, NONE);
+ PIN_SLP(gpj2-3, INPUT, DOWN);
+ PIN_SLP(gpj2-4, INPUT, DOWN);
+ PIN_SLP(gpj2-5, PREV, NONE);
+ PIN_SLP(gpj2-6, PREV, NONE);
+ PIN_SLP(gpj2-7, INPUT, DOWN);
+
+ PIN_SLP(gpj3-0, INPUT, NONE);
+ PIN_SLP(gpj3-1, INPUT, NONE);
+ PIN_SLP(gpj3-2, OUT0, NONE);
+ PIN_SLP(gpj3-3, INPUT, DOWN);
+ PIN_SLP(gpj3-4, INPUT, NONE);
+ PIN_SLP(gpj3-5, INPUT, NONE);
+ PIN_SLP(gpj3-6, INPUT, NONE);
+ PIN_SLP(gpj3-7, INPUT, NONE);
+
+ PIN_SLP(gpj4-0, INPUT, NONE);
+ PIN_SLP(gpj4-1, INPUT, DOWN);
+ PIN_SLP(gpj4-2, PREV, NONE);
+ PIN_SLP(gpj4-3, INPUT, NONE);
+ PIN_SLP(gpj4-4, INPUT, DOWN);
+
+ PIN_SLP(mp01-0, OUT1, NONE);
+ PIN_SLP(mp01-1, OUT0, NONE);
+ PIN_SLP(mp01-2, INPUT, DOWN);
+ PIN_SLP(mp01-3, INPUT, DOWN);
+ PIN_SLP(mp01-4, OUT1, NONE);
+ PIN_SLP(mp01-5, INPUT, DOWN);
+ PIN_SLP(mp01-6, INPUT, DOWN);
+ PIN_SLP(mp01-7, INPUT, DOWN);
+
+ PIN_SLP(mp02-0, INPUT, DOWN);
+ PIN_SLP(mp02-1, INPUT, DOWN);
+ PIN_SLP(mp02-2, INPUT, NONE);
+ PIN_SLP(mp02-3, INPUT, DOWN);
+
+ PIN_SLP(mp03-0, INPUT, DOWN);
+ PIN_SLP(mp03-1, INPUT, DOWN);
+ PIN_SLP(mp03-2, OUT1, NONE);
+ PIN_SLP(mp03-3, OUT0, NONE);
+ PIN_SLP(mp03-4, INPUT, NONE);
+ PIN_SLP(mp03-5, OUT0, NONE);
+ PIN_SLP(mp03-6, INPUT, DOWN);
+ PIN_SLP(mp03-7, INPUT, DOWN);
+
+ PIN_SLP(mp04-0, INPUT, DOWN);
+ PIN_SLP(mp04-1, OUT0, NONE);
+ PIN_SLP(mp04-2, INPUT, DOWN);
+ PIN_SLP(mp04-3, OUT0, NONE);
+ PIN_SLP(mp04-4, INPUT, DOWN);
+ PIN_SLP(mp04-5, INPUT, DOWN);
+ PIN_SLP(mp04-6, OUT0, NONE);
+ PIN_SLP(mp04-7, INPUT, DOWN);
+
+ PIN_SLP(mp05-0, INPUT, NONE);
+ PIN_SLP(mp05-1, INPUT, NONE);
+ PIN_SLP(mp05-2, INPUT, NONE);
+ PIN_SLP(mp05-3, INPUT, NONE);
+ PIN_SLP(mp05-4, INPUT, DOWN);
+ PIN_SLP(mp05-5, OUT0, NONE);
+ PIN_SLP(mp05-6, INPUT, DOWN);
+ PIN_SLP(mp05-7, PREV, NONE);
+
+ PIN_SLP(mp06-0, INPUT, DOWN);
+ PIN_SLP(mp06-1, INPUT, DOWN);
+ PIN_SLP(mp06-2, INPUT, DOWN);
+ PIN_SLP(mp06-3, INPUT, DOWN);
+ PIN_SLP(mp06-4, INPUT, DOWN);
+ PIN_SLP(mp06-5, INPUT, DOWN);
+ PIN_SLP(mp06-6, INPUT, DOWN);
+ PIN_SLP(mp06-7, INPUT, DOWN);
+
+ PIN_SLP(mp07-0, INPUT, DOWN);
+ PIN_SLP(mp07-1, INPUT, DOWN);
+ PIN_SLP(mp07-2, INPUT, DOWN);
+ PIN_SLP(mp07-3, INPUT, DOWN);
+ PIN_SLP(mp07-4, INPUT, DOWN);
+ PIN_SLP(mp07-5, INPUT, DOWN);
+ PIN_SLP(mp07-6, INPUT, DOWN);
+ PIN_SLP(mp07-7, INPUT, DOWN);
+ };
+};
+
+&wm8994 {
+ /* GPIO3 (BCLK2) and GPIO4 (LRCLK2) as outputs */
+ wlf,gpio-cfg = <0xa101 0x8100 0x8100 0x8100 0x8100 0xa101
+ 0x0100 0x8100 0x0100 0x0100 0x0100>;
};
diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts
index cf161bb..560f830 100644
--- a/arch/arm/boot/dts/s5pv210-galaxys.dts
+++ b/arch/arm/boot/dts/s5pv210-galaxys.dts
@@ -49,15 +49,388 @@
wakeup-source;
};
};
+
+ i2c_fmradio: i2c-gpio-8 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpd1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpd1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fm_i2c_pins>;
+
+ fmradio@10 {
+ compatible = "silabs,si470x";
+ reg = <0x10>;
+ interrupt-parent = <&gpj2>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpj2 5 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fm_irq &fm_rst>;
+ };
+ };
+
+ micbias_reg: regulator-fixed-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "MICBIAS";
+ gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&micbias_reg_ena>;
+ };
+
+ sound {
+ compatible = "samsung,aries-wm8994";
+
+ model = "Aries";
+
+ extcon = <&fsa9480>;
+
+ main-micbias-supply = <&micbias_reg>;
+ headset-micbias-supply = <&micbias_reg>;
+
+ earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>;
+
+ io-channels = <&adc 3>;
+ io-channel-names = "headset-detect";
+ headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_LOW>;
+ headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>;
+
+ samsung,audio-routing =
+ "HP", "HPOUT1L",
+ "HP", "HPOUT1R",
+
+ "SPK", "SPKOUTLN",
+ "SPK", "SPKOUTLP",
+
+ "RCV", "HPOUT2N",
+ "RCV", "HPOUT2P",
+
+ "LINE", "LINEOUT2N",
+ "LINE", "LINEOUT2P",
+
+ "IN1LP", "Main Mic",
+ "IN1LN", "Main Mic",
+
+ "IN1RP", "Headset Mic",
+ "IN1RN", "Headset Mic",
+
+ "IN2LN", "FM In",
+ "IN2RN", "FM In",
+
+ "Modem Out", "Modem TX",
+ "Modem RX", "Modem In",
+
+ "Bluetooth SPK", "TX",
+ "RX", "Bluetooth Mic";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&headset_det &earpath_sel>;
+
+ cpu {
+ sound-dai = <&i2s0>, <&bt_codec>;
+ };
+
+ codec {
+ sound-dai = <&wm8994>;
+ };
+ };
+};
+
+&aliases {
+ i2c8 = &i2c_fmradio;
};
&pinctrl0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sleep_cfg>;
+
+ fm_i2c_pins: fm-i2c-pins {
+ samsung,pins = "gpd1-2", "gpd1-3";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ headset_det: headset-det {
+ samsung,pins = "gph0-6", "gph3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ };
+
+ fm_irq: fm-irq {
+ samsung,pins = "gpj2-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ fm_rst: fm-rst {
+ samsung,pins = "gpj2-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ earpath_sel: earpath-sel {
+ samsung,pins = "gpj2-6";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
massmemory_en: massmemory-en {
samsung,pins = "gpj2-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
+
+ micbias_reg_ena: micbias-reg-ena {
+ samsung,pins = "gpj4-2";
+ samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ /* Based on CyanogenMod 3.0.101 kernel */
+ sleep_cfg: sleep-cfg {
+ PIN_SLP(gpa0-0, PREV, NONE);
+ PIN_SLP(gpa0-1, PREV, NONE);
+ PIN_SLP(gpa0-2, PREV, NONE);
+ PIN_SLP(gpa0-3, OUT1, NONE);
+ PIN_SLP(gpa0-4, INPUT, DOWN);
+ PIN_SLP(gpa0-5, OUT0, NONE);
+ PIN_SLP(gpa0-6, INPUT, DOWN);
+ PIN_SLP(gpa0-7, OUT1, NONE);
+
+ PIN_SLP(gpa1-0, INPUT, DOWN);
+ PIN_SLP(gpa1-1, OUT0, NONE);
+ PIN_SLP(gpa1-2, INPUT, NONE);
+ PIN_SLP(gpa1-3, OUT0, NONE);
+
+ PIN_SLP(gpb-0, OUT0, NONE);
+ PIN_SLP(gpb-1, OUT1, NONE);
+ PIN_SLP(gpb-2, OUT0, NONE);
+ PIN_SLP(gpb-3, PREV, NONE);
+ PIN_SLP(gpb-4, INPUT, NONE);
+ PIN_SLP(gpb-5, PREV, NONE);
+ PIN_SLP(gpb-6, INPUT, DOWN);
+ PIN_SLP(gpb-7, OUT0, NONE);
+
+ PIN_SLP(gpc0-0, OUT0, NONE);
+ PIN_SLP(gpc0-1, INPUT, DOWN);
+ PIN_SLP(gpc0-2, OUT0, NONE);
+ PIN_SLP(gpc0-3, INPUT, NONE);
+ PIN_SLP(gpc0-4, OUT0, NONE);
+
+ PIN_SLP(gpc1-0, INPUT, DOWN);
+ PIN_SLP(gpc1-1, INPUT, DOWN);
+ PIN_SLP(gpc1-2, INPUT, DOWN);
+ PIN_SLP(gpc1-3, INPUT, DOWN);
+ PIN_SLP(gpc1-4, INPUT, DOWN);
+
+ PIN_SLP(gpd0-0, INPUT, DOWN);
+ PIN_SLP(gpd0-1, OUT0, NONE);
+ PIN_SLP(gpd0-2, INPUT, DOWN);
+ PIN_SLP(gpd0-3, INPUT, DOWN);
+
+ PIN_SLP(gpd1-0, INPUT, NONE);
+ PIN_SLP(gpd1-1, INPUT, NONE);
+ PIN_SLP(gpd1-2, INPUT, NONE);
+ PIN_SLP(gpd1-3, INPUT, NONE);
+ PIN_SLP(gpd1-4, INPUT, DOWN);
+ PIN_SLP(gpd1-5, INPUT, DOWN);
+
+ PIN_SLP(gpe0-0, INPUT, DOWN);
+ PIN_SLP(gpe0-1, INPUT, DOWN);
+ PIN_SLP(gpe0-2, INPUT, DOWN);
+ PIN_SLP(gpe0-3, INPUT, DOWN);
+ PIN_SLP(gpe0-4, INPUT, DOWN);
+ PIN_SLP(gpe0-5, INPUT, DOWN);
+ PIN_SLP(gpe0-6, INPUT, DOWN);
+ PIN_SLP(gpe0-7, INPUT, DOWN);
+
+ PIN_SLP(gpe1-0, INPUT, DOWN);
+ PIN_SLP(gpe1-1, INPUT, DOWN);
+ PIN_SLP(gpe1-2, INPUT, DOWN);
+ PIN_SLP(gpe1-3, OUT0, NONE);
+ PIN_SLP(gpe1-4, INPUT, DOWN);
+
+ PIN_SLP(gpf0-0, OUT0, NONE);
+ PIN_SLP(gpf0-1, OUT0, NONE);
+ PIN_SLP(gpf0-2, OUT0, NONE);
+ PIN_SLP(gpf0-3, OUT0, NONE);
+ PIN_SLP(gpf0-4, OUT0, NONE);
+ PIN_SLP(gpf0-5, OUT0, NONE);
+ PIN_SLP(gpf0-6, OUT0, NONE);
+ PIN_SLP(gpf0-7, OUT0, NONE);
+
+ PIN_SLP(gpf1-0, OUT0, NONE);
+ PIN_SLP(gpf1-1, OUT0, NONE);
+ PIN_SLP(gpf1-2, OUT0, NONE);
+ PIN_SLP(gpf1-3, OUT0, NONE);
+ PIN_SLP(gpf1-4, OUT0, NONE);
+ PIN_SLP(gpf1-5, OUT0, NONE);
+ PIN_SLP(gpf1-6, OUT0, NONE);
+ PIN_SLP(gpf1-7, OUT0, NONE);
+
+ PIN_SLP(gpf2-0, OUT0, NONE);
+ PIN_SLP(gpf2-1, OUT0, NONE);
+ PIN_SLP(gpf2-2, OUT0, NONE);
+ PIN_SLP(gpf2-3, OUT0, NONE);
+ PIN_SLP(gpf2-4, OUT0, NONE);
+ PIN_SLP(gpf2-5, OUT0, NONE);
+ PIN_SLP(gpf2-6, OUT0, NONE);
+ PIN_SLP(gpf2-7, OUT0, NONE);
+
+ PIN_SLP(gpf3-0, OUT0, NONE);
+ PIN_SLP(gpf3-1, OUT0, NONE);
+ PIN_SLP(gpf3-2, OUT0, NONE);
+ PIN_SLP(gpf3-3, OUT0, NONE);
+ PIN_SLP(gpf3-4, PREV, NONE);
+ PIN_SLP(gpf3-5, INPUT, DOWN);
+
+ PIN_SLP(gpg0-0, OUT0, NONE);
+ PIN_SLP(gpg0-1, INPUT, NONE);
+ PIN_SLP(gpg0-2, INPUT, NONE);
+ PIN_SLP(gpg0-3, INPUT, NONE);
+ PIN_SLP(gpg0-4, INPUT, NONE);
+ PIN_SLP(gpg0-5, INPUT, NONE);
+ PIN_SLP(gpg0-6, INPUT, NONE);
+
+ PIN_SLP(gpg1-0, OUT0, NONE);
+ PIN_SLP(gpg1-1, OUT1, NONE);
+ PIN_SLP(gpg1-2, PREV, NONE);
+ PIN_SLP(gpg1-3, OUT1, NONE);
+ PIN_SLP(gpg1-4, OUT1, NONE);
+ PIN_SLP(gpg1-5, OUT1, NONE);
+ PIN_SLP(gpg1-6, OUT1, NONE);
+
+ PIN_SLP(gpg2-0, OUT0, NONE);
+ PIN_SLP(gpg2-1, OUT0, NONE);
+ PIN_SLP(gpg2-2, INPUT, NONE);
+ PIN_SLP(gpg2-3, OUT0, NONE);
+ PIN_SLP(gpg2-4, OUT0, NONE);
+ PIN_SLP(gpg2-5, OUT0, NONE);
+ PIN_SLP(gpg2-6, OUT0, NONE);
+
+ PIN_SLP(gpg3-0, OUT1, NONE);
+ PIN_SLP(gpg3-1, OUT0, NONE);
+ PIN_SLP(gpg3-2, INPUT, NONE);
+ PIN_SLP(gpg3-3, INPUT, DOWN);
+ PIN_SLP(gpg3-4, OUT0, NONE);
+ PIN_SLP(gpg3-5, OUT0, NONE);
+ PIN_SLP(gpg3-6, INPUT, DOWN);
+
+ PIN_SLP(gpi-0, PREV, NONE);
+ PIN_SLP(gpi-1, INPUT, DOWN);
+ PIN_SLP(gpi-2, PREV, NONE);
+ PIN_SLP(gpi-3, PREV, NONE);
+ PIN_SLP(gpi-4, PREV, NONE);
+ PIN_SLP(gpi-5, INPUT, DOWN);
+ PIN_SLP(gpi-6, INPUT, DOWN);
+
+ PIN_SLP(gpj0-0, INPUT, NONE);
+ PIN_SLP(gpj0-1, INPUT, NONE);
+ PIN_SLP(gpj0-2, INPUT, NONE);
+ PIN_SLP(gpj0-3, INPUT, NONE);
+ PIN_SLP(gpj0-4, INPUT, NONE);
+ PIN_SLP(gpj0-5, INPUT, DOWN);
+ PIN_SLP(gpj0-6, OUT0, NONE);
+ PIN_SLP(gpj0-7, INPUT, NONE);
+
+ PIN_SLP(gpj1-0, INPUT, DOWN);
+ PIN_SLP(gpj1-1, OUT0, NONE);
+ PIN_SLP(gpj1-2, INPUT, DOWN);
+ PIN_SLP(gpj1-3, PREV, NONE);
+ PIN_SLP(gpj1-4, PREV, NONE);
+ PIN_SLP(gpj1-5, OUT0, NONE);
+
+ PIN_SLP(gpj2-0, INPUT, DOWN);
+ PIN_SLP(gpj2-1, INPUT, DOWN);
+ PIN_SLP(gpj2-2, OUT0, NONE);
+ PIN_SLP(gpj2-3, INPUT, DOWN);
+ PIN_SLP(gpj2-4, INPUT, UP);
+ PIN_SLP(gpj2-5, PREV, NONE);
+ PIN_SLP(gpj2-6, PREV, NONE);
+ PIN_SLP(gpj2-7, OUT1, NONE);
+
+ PIN_SLP(gpj3-0, INPUT, NONE);
+ PIN_SLP(gpj3-1, INPUT, NONE);
+ PIN_SLP(gpj3-2, OUT0, NONE);
+ PIN_SLP(gpj3-3, INPUT, DOWN);
+ PIN_SLP(gpj3-4, INPUT, NONE);
+ PIN_SLP(gpj3-5, INPUT, NONE);
+ PIN_SLP(gpj3-6, INPUT, NONE);
+ PIN_SLP(gpj3-7, INPUT, NONE);
+
+ PIN_SLP(gpj4-0, INPUT, NONE);
+ PIN_SLP(gpj4-1, INPUT, DOWN);
+ PIN_SLP(gpj4-2, PREV, NONE);
+ PIN_SLP(gpj4-3, INPUT, NONE);
+ PIN_SLP(gpj4-4, INPUT, DOWN);
+
+ PIN_SLP(mp01-0, INPUT, DOWN);
+ PIN_SLP(mp01-1, OUT0, NONE);
+ PIN_SLP(mp01-2, INPUT, DOWN);
+ PIN_SLP(mp01-3, INPUT, DOWN);
+ PIN_SLP(mp01-4, OUT1, NONE);
+ PIN_SLP(mp01-5, INPUT, DOWN);
+ PIN_SLP(mp01-6, INPUT, DOWN);
+ PIN_SLP(mp01-7, INPUT, DOWN);
+
+ PIN_SLP(mp02-0, INPUT, DOWN);
+ PIN_SLP(mp02-1, INPUT, DOWN);
+ PIN_SLP(mp02-2, INPUT, NONE);
+ PIN_SLP(mp02-3, INPUT, DOWN);
+
+ PIN_SLP(mp03-0, INPUT, DOWN);
+ PIN_SLP(mp03-1, INPUT, DOWN);
+ PIN_SLP(mp03-2, OUT1, NONE);
+ PIN_SLP(mp03-3, OUT0, NONE);
+ PIN_SLP(mp03-4, INPUT, NONE);
+ PIN_SLP(mp03-5, OUT1, NONE);
+ PIN_SLP(mp03-6, INPUT, DOWN);
+ PIN_SLP(mp03-7, INPUT, DOWN);
+
+ PIN_SLP(mp04-0, INPUT, DOWN);
+ PIN_SLP(mp04-1, OUT0, NONE);
+ PIN_SLP(mp04-2, INPUT, DOWN);
+ PIN_SLP(mp04-3, OUT0, NONE);
+ PIN_SLP(mp04-4, INPUT, DOWN);
+ PIN_SLP(mp04-5, INPUT, DOWN);
+ PIN_SLP(mp04-6, OUT0, NONE);
+ PIN_SLP(mp04-7, INPUT, DOWN);
+
+ PIN_SLP(mp05-0, INPUT, NONE);
+ PIN_SLP(mp05-1, INPUT, NONE);
+ PIN_SLP(mp05-2, INPUT, NONE);
+ PIN_SLP(mp05-3, INPUT, NONE);
+ PIN_SLP(mp05-4, INPUT, DOWN);
+ PIN_SLP(mp05-5, OUT0, NONE);
+ PIN_SLP(mp05-6, INPUT, DOWN);
+ PIN_SLP(mp05-7, PREV, NONE);
+
+ PIN_SLP(mp06-0, INPUT, DOWN);
+ PIN_SLP(mp06-1, INPUT, DOWN);
+ PIN_SLP(mp06-2, INPUT, DOWN);
+ PIN_SLP(mp06-3, INPUT, DOWN);
+ PIN_SLP(mp06-4, INPUT, DOWN);
+ PIN_SLP(mp06-5, INPUT, DOWN);
+ PIN_SLP(mp06-6, INPUT, DOWN);
+ PIN_SLP(mp06-7, INPUT, DOWN);
+
+ PIN_SLP(mp07-0, INPUT, DOWN);
+ PIN_SLP(mp07-1, INPUT, DOWN);
+ PIN_SLP(mp07-2, INPUT, DOWN);
+ PIN_SLP(mp07-3, INPUT, DOWN);
+ PIN_SLP(mp07-4, INPUT, DOWN);
+ PIN_SLP(mp07-5, INPUT, DOWN);
+ PIN_SLP(mp07-6, INPUT, DOWN);
+ PIN_SLP(mp07-7, INPUT, DOWN);
+ };
};
&sdhci0 {
@@ -67,4 +440,8 @@
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
pinctrl-names = "default";
status = "okay";
+
+ assigned-clocks = <&clocks MOUT_MMC0>, <&clocks SCLK_MMC0>;
+ assigned-clock-rates = <0>, <52000000>;
+ assigned-clock-parents = <&clocks MOUT_MPLL>;
};
diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts
index fbbd937..ad8d5d2 100644
--- a/arch/arm/boot/dts/s5pv210-goni.dts
+++ b/arch/arm/boot/dts/s5pv210-goni.dts
@@ -11,6 +11,8 @@
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
@@ -33,52 +35,49 @@
0x50000000 0x08000000>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ pmic_ap_clk: clock-0 {
+ /* Workaround for missing clock on PMIC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
- vtf_reg: fixed-regulator@0 {
- compatible = "regulator-fixed";
- regulator-name = "V_TF_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- reg = <0>;
- gpio = <&mp05 4 0>;
- enable-active-high;
- };
+ vtf_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_TF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&mp05 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- pda_reg: fixed-regulator@1 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1.8V_PDA";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- reg = <1>;
- };
+ pda_reg: regulator-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1.8V_PDA";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
- bat_reg: fixed-regulator@2 {
- compatible = "regulator-fixed";
- regulator-name = "V_BAT";
- regulator-min-microvolt = <3700000>;
- regulator-max-microvolt = <3700000>;
- reg = <2>;
- };
+ bat_reg: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_BAT";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
- tsp_reg: fixed-regulator@3 {
- compatible = "regulator-fixed";
- regulator-name = "TSP_VDD";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- reg = <3>;
- gpio = <&gpj1 3 0>;
- enable-active-high;
- };
+ tsp_reg: regulator-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "TSP_VDD";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpj1 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
i2c_pmic: i2c-pmic {
compatible = "i2c-gpio";
- gpios = <&gpj4 0 0>, /* sda */
- <&gpj4 3 0>; /* scl */
+ sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
@@ -88,13 +87,13 @@
reg = <0x66>;
max8998,pmic-buck1-default-dvs-idx = <0>;
- max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>,
- <&gph0 4 0>;
+ max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>,
+ <&gph0 4 GPIO_ACTIVE_HIGH>;
max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
<1200000>, <1200000>;
max8998,pmic-buck2-default-dvs-idx = <0>;
- max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>;
+ max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>;
max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;
regulators {
@@ -224,6 +223,11 @@
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
+
+ ap32khz_reg: EN32KHz-AP {
+ regulator-name = "32KHz AP";
+ regulator-always-on;
+ };
};
};
};
@@ -308,6 +312,11 @@
status = "okay";
};
+&rtc {
+ clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
+};
+
&sdhci0 {
bus-width = <4>;
non-removable;
@@ -348,7 +357,7 @@
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&gpj0>;
- interrupts = <5 2>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
atmel,x-line = <17>;
atmel,y-line = <11>;
@@ -378,8 +387,8 @@
clock-frequency = <16000000>;
clocks = <&camera 0>;
clock-names = "mclk";
- nreset-gpios = <&gpb 2 0>;
- nstby-gpios = <&gpb 0 0>;
+ nreset-gpios = <&gpb 2 GPIO_ACTIVE_HIGH>;
+ nstby-gpios = <&gpb 0 GPIO_ACTIVE_HIGH>;
port {
noon010pc30_ep: endpoint {
diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
index 7f0c9d4..b8c5172 100644
--- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi
@@ -18,6 +18,13 @@
#include <dt-bindings/pinctrl/samsung.h>
+#define PIN_SLP(_pin, _mode, _pull) \
+ _pin { \
+ samsung,pins = #_pin; \
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
+ samsung,pin-pud-pdn = <S3C64XX_PIN_PULL_ ##_pull>; \
+ }
+
&pinctrl0 {
gpa0: gpa0 {
gpio-controller;
@@ -195,7 +202,7 @@
#interrupt-cells = <2>;
};
- gpgi: gpgi {
+ gpi: gpi {
gpio-controller;
#gpio-cells = <2>;
};
@@ -266,6 +273,8 @@
gph3: gph3 {
gpio-controller;
#gpio-cells = <2>;
+
+ interrupt-controller;
#interrupt-cells = <2>;
};
diff --git a/arch/arm/boot/dts/s5pv210-smdkc110.dts b/arch/arm/boot/dts/s5pv210-smdkc110.dts
index e5aec6c..0c623b7 100644
--- a/arch/arm/boot/dts/s5pv210-smdkc110.dts
+++ b/arch/arm/boot/dts/s5pv210-smdkc110.dts
@@ -30,6 +30,13 @@
device_type = "memory";
reg = <0x20000000 0x20000000>;
};
+
+ pmic_ap_clk: clock-0 {
+ /* Workaround for missing PMIC and its clock */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
&xusbxti {
@@ -54,6 +61,8 @@
&rtc {
status = "okay";
+ clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
};
&i2c0 {
diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts
index 84b38f1..7459e41 100644
--- a/arch/arm/boot/dts/s5pv210-smdkv210.dts
+++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts
@@ -15,6 +15,7 @@
*/
/dts-v1/;
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"
@@ -31,11 +32,18 @@
reg = <0x20000000 0x40000000>;
};
- ethernet@18000000 {
+ pmic_ap_clk: clock-0 {
+ /* Workaround for missing PMIC and its clock */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ ethernet@a8000000 {
compatible = "davicom,dm9000";
reg = <0xA8000000 0x2 0xA8000002 0x2>;
interrupt-parent = <&gph1>;
- interrupts = <1 4>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
local-mac-address = [00 00 de ad be ef];
davicom,no-eeprom;
};
@@ -147,6 +155,8 @@
&rtc {
status = "okay";
+ clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
};
&sdhci0 {
diff --git a/arch/arm/boot/dts/s5pv210-torbreck.dts b/arch/arm/boot/dts/s5pv210-torbreck.dts
index cd25e72..e182597 100644
--- a/arch/arm/boot/dts/s5pv210-torbreck.dts
+++ b/arch/arm/boot/dts/s5pv210-torbreck.dts
@@ -30,6 +30,13 @@
device_type = "memory";
reg = <0x20000000 0x20000000>;
};
+
+ pmic_ap_clk: clock-0 {
+ /* Workaround for missing PMIC and its clock */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
&xusbxti {
@@ -54,6 +61,8 @@
&rtc {
status = "okay";
+ clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>;
+ clock-names = "rtc", "rtc_src";
};
&sdhci0 {
diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
index 61822af..2871351 100644
--- a/arch/arm/boot/dts/s5pv210.dtsi
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -141,6 +141,18 @@
#dma-requests = <32>;
};
+ adc: adc@e1700000 {
+ compatible = "samsung,s5pv210-adc";
+ reg = <0xe1700000 0x1000>;
+ interrupt-parent = <&vic2>;
+ interrupts = <23>, <24>;
+ clocks = <&clocks CLK_TSADC>;
+ clock-names = "adc";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ status = "disabled";
+ };
+
spi0: spi@e1300000 {
compatible = "samsung,s5pv210-spi";
reg = <0xe1300000 0x1000>;
@@ -589,7 +601,7 @@
clock-names = "fimc",
"sclk_fimc";
samsung,pix-limits = <4224 8192 1920 4224>;
- samsung,mainscaler-ext;
+ samsung,min-pix-alignment = <16 8>;
samsung,cam-if;
};
@@ -603,8 +615,10 @@
clock-names = "fimc",
"sclk_fimc";
samsung,pix-limits = <4224 8192 1920 4224>;
+ samsung,min-pix-alignment = <1 1>;
samsung,mainscaler-ext;
samsung,cam-if;
+ samsung,lcd-wb;
};
fimc2: fimc@fb400000 {
@@ -616,9 +630,10 @@
<&clocks SCLK_FIMC2>;
clock-names = "fimc",
"sclk_fimc";
- samsung,pix-limits = <4224 8192 1920 4224>;
- samsung,mainscaler-ext;
- samsung,lcd-wb;
+ samsung,pix-limits = <1920 8192 1280 1920>;
+ samsung,min-pix-alignment = <16 8>;
+ samsung,rotators = <0>;
+ samsung,cam-if;
};
};
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
new file mode 100644
index 0000000..ec45ced
--- /dev/null
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
+ */
+
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Microchip SAM9X60 SoC";
+ compatible = "microchip,sam9x60";
+ interrupt-parent = <&aic>;
+
+ aliases {
+ serial0 = &dbgu;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ gpio2 = &pioC;
+ gpio3 = &pioD;
+ tcb0 = &tcb0;
+ tcb1 = &tcb1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x10000000>;
+ };
+
+ clocks {
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ sram: sram@300000 {
+ compatible = "mmio-sram";
+ reg = <0x00300000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00300000 0x100000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usb0: gadget@500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "microchip,sam9x60-udc";
+ reg = <0x00500000 0x100000
+ 0xf803c000 0x400>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ clock-names = "pclk", "hclk";
+ assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-rates = <480000000>;
+ status = "disabled";
+ };
+
+ usb1: ohci@600000 {
+ compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+ reg = <0x00600000 0x100000>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
+ status = "disabled";
+ };
+
+ usb2: ehci@700000 {
+ compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+ reg = <0x00700000 0x100000>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+ clock-names = "usb_clk", "ehci_clk";
+ assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+ assigned-clock-rates = <480000000>;
+ status = "disabled";
+ };
+
+ ebi: ebi@10000000 {
+ compatible = "microchip,sam9x60-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&smc>;
+ microchip,sfr = <&sfr>;
+ reg = <0x10000000 0x60000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x20000000 0x10000000
+ 0x2 0x0 0x30000000 0x10000000
+ 0x3 0x0 0x40000000 0x10000000
+ 0x4 0x0 0x50000000 0x10000000
+ 0x5 0x0 0x60000000 0x10000000>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible = "microchip,sam9x60-nand-controller";
+ ecc-engine = <&pmecc>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
+
+ sdmmc0: sdio-host@80000000 {
+ compatible = "microchip,sam9x60-sdhci";
+ reg = <0x80000000 0x300>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
+ assigned-clock-rates = <100000000>;
+ status = "disabled";
+ };
+
+ sdmmc1: sdio-host@90000000 {
+ compatible = "microchip,sam9x60-sdhci";
+ reg = <0x90000000 0x300>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+ assigned-clock-rates = <100000000>;
+ status = "disabled";
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ flx4: flexcom@f0000000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf0000000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf0000000 0x800>;
+ status = "disabled";
+ };
+
+ flx5: flexcom@f0004000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf0004000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf0004000 0x800>;
+ status = "disabled";
+ };
+
+ dma0: dma-controller@f0008000 {
+ compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
+ reg = <0xf0008000 0x1000>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <1>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+ clock-names = "dma_clk";
+ };
+
+ ssc: ssc@f0010000 {
+ compatible = "atmel,at91sam9g45-ssc";
+ reg = <0xf0010000 0x4000>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(38))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(39))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
+ clock-names = "pclk";
+ status = "disabled";
+ };
+
+ qspi: spi@f0014000 {
+ compatible = "microchip,sam9x60-qspi";
+ reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(26))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(27))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
+ clock-names = "pclk", "qspick";
+ atmel,pmc = <&pmc>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s: i2s@f001c000 {
+ compatible = "microchip,sam9x60-i2smcc";
+ reg = <0xf001c000 0x100>;
+ interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(36))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(37))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
+ clock-names = "pclk", "gclk";
+ status = "disabled";
+ };
+
+ flx11: flexcom@f0020000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf0020000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf0020000 0x800>;
+ status = "disabled";
+ };
+
+ flx12: flexcom@f0024000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf0024000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf0024000 0x800>;
+ status = "disabled";
+ };
+
+ pit64b: timer@f0028000 {
+ compatible = "microchip,sam9x60-pit64b";
+ reg = <0xf0028000 0x100>;
+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
+ clock-names = "pclk", "gclk";
+ };
+
+ sha: sha@f002c000 {
+ compatible = "atmel,at91sam9g46-sha";
+ reg = <0xf002c000 0x100>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(34))>;
+ dma-names = "tx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+ clock-names = "sha_clk";
+ status = "okay";
+ };
+
+ trng: trng@f0030000 {
+ compatible = "microchip,sam9x60-trng";
+ reg = <0xf0030000 0x100>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+ status = "okay";
+ };
+
+ aes: aes@f0034000 {
+ compatible = "atmel,at91sam9g46-aes";
+ reg = <0xf0034000 0x100>;
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(32))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(33))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+ clock-names = "aes_clk";
+ status = "okay";
+ };
+
+ tdes: tdes@f0038000 {
+ compatible = "atmel,at91sam9g46-tdes";
+ reg = <0xf0038000 0x100>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(31))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(30))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+ clock-names = "tdes_clk";
+ status = "okay";
+ };
+
+ classd: classd@f003c000 {
+ compatible = "atmel,sama5d2-classd";
+ reg = <0xf003c000 0x100>;
+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(35))>;
+ dma-names = "tx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
+ clock-names = "pclk", "gclk";
+ status = "disabled";
+ };
+
+ can0: can@f8000000 {
+ compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+ reg = <0xf8000000 0x300>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
+ clock-names = "can_clk";
+ status = "disabled";
+ };
+
+ can1: can@f8004000 {
+ compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
+ reg = <0xf8004000 0x300>;
+ interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
+ clock-names = "can_clk";
+ status = "disabled";
+ };
+
+ tcb0: timer@f8008000 {
+ compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xf8008000 0x100>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
+ clock-names = "t0_clk", "slow_clk";
+ };
+
+ tcb1: timer@f800c000 {
+ compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xf800c000 0x100>;
+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
+ clock-names = "t0_clk", "slow_clk";
+ };
+
+ flx6: flexcom@f8010000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8010000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8010000 0x800>;
+ status = "disabled";
+ };
+
+ flx7: flexcom@f8014000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8014000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8014000 0x800>;
+ status = "disabled";
+ };
+
+ flx8: flexcom@f8018000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8018000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8018000 0x800>;
+ status = "disabled";
+ };
+
+ flx0: flexcom@f801c000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf801c000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf801c000 0x800>;
+ status = "disabled";
+ };
+
+ flx1: flexcom@f8020000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8020000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8020000 0x800>;
+ status = "disabled";
+ };
+
+ flx2: flexcom@f8024000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8024000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8024000 0x800>;
+ status = "disabled";
+ };
+
+ flx3: flexcom@f8028000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8028000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8028000 0x800>;
+ status = "disabled";
+ };
+
+ macb0: ethernet@f802c000 {
+ compatible = "cdns,sam9x60-macb", "cdns,macb";
+ reg = <0xf802c000 0x1000>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+
+ macb1: ethernet@f8030000 {
+ compatible = "cdns,sam9x60-macb", "cdns,macb";
+ reg = <0xf8030000 0x1000>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
+ clock-names = "hclk", "pclk";
+ status = "disabled";
+ };
+
+ pwm0: pwm@f8034000 {
+ compatible = "microchip,sam9x60-pwm";
+ reg = <0xf8034000 0x300>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
+ #pwm-cells = <3>;
+ status="disabled";
+ };
+
+ hlcdc: hlcdc@f8038000 {
+ compatible = "microchip,sam9x60-hlcdc";
+ reg = <0xf8038000 0x4000>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
+ clock-names = "periph_clk","sys_clk", "slow_clk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ status = "disabled";
+
+ hlcdc-display-controller {
+ compatible = "atmel,hlcdc-display-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ };
+
+ hlcdc_pwm: hlcdc-pwm {
+ compatible = "atmel,hlcdc-pwm";
+ #pwm-cells = <3>;
+ };
+ };
+
+ flx9: flexcom@f8040000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8040000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8040000 0x800>;
+ status = "disabled";
+ };
+
+ flx10: flexcom@f8044000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xf8044000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xf8044000 0x800>;
+ status = "disabled";
+ };
+
+ isi: isi@f8048000 {
+ compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
+ reg = <0xf8048000 0x100>;
+ interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
+ clock-names = "isi_clk";
+ status = "disabled";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ adc: adc@f804c000 {
+ compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
+ reg = <0xf804c000 0x100>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ clock-names = "adc_clk";
+ dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
+ dma-names = "rx";
+ atmel,min-sample-rate-hz = <200000>;
+ atmel,max-sample-rate-hz = <20000000>;
+ atmel,startup-time-ms = <4>;
+ atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ sfr: sfr@f8050000 {
+ compatible = "microchip,sam9x60-sfr", "syscon";
+ reg = <0xf8050000 0x100>;
+ };
+
+ matrix: matrix@ffffde00 {
+ compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
+ reg = <0xffffde00 0x200>;
+ };
+
+ pmecc: ecc-engine@ffffe000 {
+ compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+ reg = <0xffffe000 0x300>,
+ <0xffffe600 0x100>;
+ };
+
+ mpddrc: mpddrc@ffffe800 {
+ compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
+ reg = <0xffffe800 0x200>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+ clock-names = "ddrck", "mpddr";
+ };
+
+ smc: smc@ffffea00 {
+ compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffea00 0x100>;
+ };
+
+ aic: interrupt-controller@fffff100 {
+ compatible = "microchip,sam9x60-aic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xfffff100 0x100>;
+ atmel,external-irqs = <31>;
+ };
+
+ dbgu: serial@fffff200 {
+ compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+ reg = <0xfffff200 0x200>;
+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(28))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(29))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
+ clock-names = "usart";
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@fffff400 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+ ranges = <0xfffff400 0xfffff400 0x800>;
+
+ /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
+ atmel,mux-mask = <
+ /* A B C */
+ 0xffffffff 0xffe03fff 0xef00019d /* pioA */
+ 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
+ 0xffffffff 0xffffffff 0xf83fffff /* pioC */
+ 0x003fffff 0x003f8000 0x00000000 /* pioD */
+ >;
+
+ pioA: gpio@fffff400 {
+ compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+ };
+
+ pioB: gpio@fffff600 {
+ compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-lines = <26>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
+ };
+
+ pioC: gpio@fffff800 {
+ compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+ };
+
+ pioD: gpio@fffffa00 {
+ compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-lines = <22>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+ };
+ };
+
+ pmc: pmc@fffffc00 {
+ compatible = "microchip,sam9x60-pmc", "syscon";
+ reg = <0xfffffc00 0x200>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ #clock-cells = <2>;
+ clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+ clock-names = "td_slck", "md_slck", "main_xtal";
+ };
+
+ reset_controller: rstc@fffffe00 {
+ compatible = "microchip,sam9x60-rstc";
+ reg = <0xfffffe00 0x10>;
+ clocks = <&clk32k 0>;
+ };
+
+ shutdown_controller: shdwc@fffffe10 {
+ compatible = "microchip,sam9x60-shdwc";
+ reg = <0xfffffe10 0x10>;
+ clocks = <&clk32k 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,wakeup-rtc-timer;
+ atmel,wakeup-rtt-timer;
+ status = "disabled";
+ };
+
+ rtt: rtt@fffffe20 {
+ compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
+ reg = <0xfffffe20 0x20>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k 0>;
+ };
+
+ pit: timer@fffffe40 {
+ compatible = "atmel,at91sam9260-pit";
+ reg = <0xfffffe40 0x10>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+ };
+
+ clk32k: sckc@fffffe50 {
+ compatible = "microchip,sam9x60-sckc";
+ reg = <0xfffffe50 0x4>;
+ clocks = <&slow_xtal>;
+ #clock-cells = <1>;
+ };
+
+ gpbr: syscon@fffffe60 {
+ compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
+ reg = <0xfffffe60 0x10>;
+ };
+
+ rtc: rtc@fffffea8 {
+ compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
+ reg = <0xfffffea8 0x100>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k 0>;
+ };
+
+ watchdog: watchdog@ffffff80 {
+ compatible = "microchip,sam9x60-wdt";
+ reg = <0xffffff80 0x24>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k 0>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index b05bab5..2c49524 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -21,10 +21,6 @@
aliases {
serial0 = &uart1;
serial1 = &uart3;
- tcb0 = &tcb0;
- tcb1 = &tcb1;
- i2s0 = &i2s0;
- i2s1 = &i2s1;
};
cpus {
@@ -76,7 +72,7 @@
};
};
- memory {
+ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x20000000>;
};
@@ -98,6 +94,9 @@
ns_sram: sram@200000 {
compatible = "mmio-sram";
reg = <0x00200000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00200000 0x20000>;
};
ahb {
@@ -110,11 +109,13 @@
compatible = "mmio-sram";
no-memory-wc;
reg = <0x00100000 0x2400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00100000 0x2400>;
+
};
usb0: gadget@300000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "atmel,sama5d3-udc";
reg = <0x00300000 0x100000
0xfc02c000 0x400>;
@@ -122,124 +123,6 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
-
- ep@0 {
- reg = <0>;
- atmel,fifo-size = <64>;
- atmel,nb-banks = <1>;
- };
-
- ep@1 {
- reg = <1>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@2 {
- reg = <2>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@3 {
- reg = <3>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@4 {
- reg = <4>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@5 {
- reg = <5>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@6 {
- reg = <6>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@7 {
- reg = <7>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@8 {
- reg = <8>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@9 {
- reg = <9>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@10 {
- reg = <10>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@11 {
- reg = <11>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@12 {
- reg = <12>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@13 {
- reg = <13>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@14 {
- reg = <14>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@15 {
- reg = <15>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
};
usb1: ohci@400000 {
@@ -300,6 +183,8 @@
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
clock-names = "hclock", "multclk", "baseclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
+ assigned-clock-rates = <480000000>;
status = "disabled";
};
@@ -309,6 +194,8 @@
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
clock-names = "hclock", "multclk", "baseclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
+ assigned-clock-rates = <480000000>;
status = "disabled";
};
@@ -495,23 +382,23 @@
};
tcb0: timer@f800c000 {
- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+ compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>;
- clock-names = "t0_clk", "slow_clk";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>;
+ clock-names = "t0_clk", "gclk", "slow_clk";
};
tcb1: timer@f8010000 {
- compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
+ compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf8010000 0x100>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>;
- clock-names = "t0_clk", "slow_clk";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>;
+ clock-names = "t0_clk", "gclk", "slow_clk";
};
hsmc: hsmc@f8014000 {
@@ -615,6 +502,7 @@
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
#pwm-cells = <3>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+ status = "disabled";
};
sfr: sfr@f8030000 {
@@ -630,6 +518,66 @@
#size-cells = <1>;
ranges = <0x0 0xf8034000 0x800>;
status = "disabled";
+
+ uart5: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ clock-names = "usart";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(12))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi2: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(12))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(12))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx1: flexcom@f8038000 {
@@ -640,6 +588,66 @@
#size-cells = <1>;
ranges = <0x0 0xf8038000 0x800>;
status = "disabled";
+
+ uart6: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+ clock-names = "usart";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(13))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(14))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi3: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(13))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(14))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(13))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(14))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
securam: sram@f8044000 {
@@ -690,8 +698,8 @@
#clock-cells = <0>;
};
- rtc@f80480b0 {
- compatible = "atmel,at91rm9200-rtc";
+ rtc: rtc@f80480b0 {
+ compatible = "atmel,sama5d2-rtc";
reg = <0xf80480b0 0x30>;
interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
@@ -790,6 +798,66 @@
#size-cells = <1>;
ranges = <0x0 0xfc010000 0x800>;
status = "disabled";
+
+ uart7: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
+ clock-names = "usart";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(15))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(16))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi4: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(15))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(16))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(15))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(16))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx3: flexcom@fc014000 {
@@ -800,6 +868,67 @@
#size-cells = <1>;
ranges = <0x0 0xfc014000 0x800>;
status = "disabled";
+
+ uart8: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
+ clock-names = "usart";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(17))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(18))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi5: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(17))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(18))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(17))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(18))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
};
flx4: flexcom@fc018000 {
@@ -810,6 +939,66 @@
#size-cells = <1>;
ranges = <0x0 0xfc018000 0x800>;
status = "disabled";
+
+ uart9: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
+ clock-names = "usart";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(19))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(20))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi6: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
+ clock-names = "spi_clk";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(19))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(20))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(19))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(20))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
trng@fc01c000 {
@@ -885,9 +1074,12 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
};
- secumod@fc040000 {
+ pioBU: secumod@fc040000 {
compatible = "atmel,sama5d2-secumod", "syscon";
reg = <0xfc040000 0x100>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
};
tdes@fc044000 {
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 203d40b..86137f8 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -55,7 +55,7 @@
interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
};
- memory {
+ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x8000000>;
};
@@ -83,6 +83,9 @@
sram: sram@300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00300000 0x20000>;
};
ahb {
@@ -108,7 +111,7 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
clock-names = "mci_clk";
};
@@ -123,7 +126,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
- clocks = <&spi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -137,7 +140,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- clocks = <&ssc0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
clock-names = "pclk";
status = "disabled";
};
@@ -148,7 +151,7 @@
#size-cells = <0>;
reg = <0xf0010000 0x100>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
@@ -159,11 +162,14 @@
dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
<&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
dma-names = "tx", "rx";
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
status = "disabled";
};
@@ -174,11 +180,14 @@
dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
<&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
dma-names = "tx", "rx";
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&pioC 26 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioC 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
status = "disabled";
};
@@ -191,7 +200,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0>;
- clocks = <&usart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
clock-names = "usart";
status = "disabled";
};
@@ -205,7 +214,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1>;
- clocks = <&usart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "usart";
status = "disabled";
};
@@ -216,7 +225,7 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&uart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "usart";
status = "disabled";
};
@@ -226,7 +235,7 @@
reg = <0xf002c000 0x300>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
#pwm-cells = <3>;
- clocks = <&pwm_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
status = "disabled";
};
@@ -236,7 +245,7 @@
interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isi_data_0_7>;
- clocks = <&isi_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
clock-names = "isi_clk";
status = "disabled";
port {
@@ -261,7 +270,7 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&mci1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "mci_clk";
};
@@ -276,7 +285,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&spi1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
clock-names = "spi_clk";
status = "disabled";
};
@@ -290,7 +299,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
- clocks = <&ssc1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
clock-names = "pclk";
status = "disabled";
};
@@ -317,7 +326,7 @@
&pinctrl_adc0_ad10
&pinctrl_adc0_ad11
>;
- clocks = <&adc_clk>,
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 29>,
<&adc_op_clk>;
clock-names = "adc_clk", "adc_op_clk";
atmel,adc-channels-used = <0xfff>;
@@ -357,11 +366,14 @@
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
<&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
dma-names = "tx", "rx";
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ sda-gpios = <&pioA 18 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&twi2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
status = "disabled";
};
@@ -374,7 +386,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart2>;
- clocks = <&usart2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "usart";
status = "disabled";
};
@@ -388,7 +400,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3>;
- clocks = <&usart3_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
clock-names = "usart";
status = "disabled";
};
@@ -399,7 +411,7 @@
interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
dma-names = "tx";
- clocks = <&sha_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
clock-names = "sha_clk";
};
@@ -410,7 +422,7 @@
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
<&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
dma-names = "tx", "rx";
- clocks = <&aes_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
clock-names = "aes_clk";
};
@@ -421,7 +433,7 @@
dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
<&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
dma-names = "tx", "rx";
- clocks = <&tdes_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
clock-names = "tdes_clk";
};
@@ -429,14 +441,14 @@
compatible = "atmel,at91sam9g45-trng";
reg = <0xf8040000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&trng_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
};
hsmc: hsmc@ffffc000 {
compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
reg = <0xffffc000 0x1000>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
- clocks = <&hsmc_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -453,7 +465,7 @@
reg = <0xffffe600 0x200>;
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
- clocks = <&dma0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
clock-names = "dma_clk";
};
@@ -462,14 +474,14 @@
reg = <0xffffe800 0x200>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <2>;
- clocks = <&dma1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
clock-names = "dma_clk";
};
ramc0: ramc@ffffea00 {
compatible = "atmel,sama5d3-ddramc";
reg = <0xffffea00 0x200>;
- clocks = <&ddrck>, <&mpddr_clk>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>;
clock-names = "ddrck", "mpddr";
};
@@ -482,7 +494,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
- clocks = <&dbgu_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
clock-names = "usart";
status = "disabled";
};
@@ -639,6 +651,12 @@
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
};
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ atmel,pins =
+ <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
};
i2c1 {
@@ -647,6 +665,12 @@
<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
};
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ atmel,pins =
+ <AT91_PIOC 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOC 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
};
i2c2 {
@@ -655,6 +679,12 @@
<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
};
+
+ pinctrl_i2c2_gpio: i2c2-gpio {
+ atmel,pins =
+ <AT91_PIOA 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOA 19 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
};
isi {
@@ -940,7 +970,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioA_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
};
pioB: gpio@fffff400 {
@@ -951,7 +981,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioB_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
};
pioC: gpio@fffff600 {
@@ -962,7 +992,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioC_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
};
pioD: gpio@fffff800 {
@@ -973,7 +1003,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioD_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
};
pioE: gpio@fffffa00 {
@@ -984,7 +1014,7 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- clocks = <&pioE_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
};
};
@@ -992,353 +1022,9 @@
compatible = "atmel,sama5d3-pmc", "syscon";
reg = <0xfffffc00 0x120>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
-
- main_rc_osc: main_rc_osc {
- compatible = "atmel,at91sam9x5-clk-main-rc-osc";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MOSCRCS>;
- clock-frequency = <12000000>;
- clock-accuracy = <50000000>;
- };
-
- main_osc: main_osc {
- compatible = "atmel,at91rm9200-clk-main-osc";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MOSCS>;
- clocks = <&main_xtal>;
- };
-
- main: mainck {
- compatible = "atmel,at91sam9x5-clk-main";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MOSCSELS>;
- clocks = <&main_rc_osc &main_osc>;
- };
-
- plla: pllack {
- compatible = "atmel,sama5d3-clk-pll";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_LOCKA>;
- clocks = <&main>;
- reg = <0>;
- atmel,clk-input-range = <8000000 50000000>;
- #atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
- };
-
- plladiv: plladivck {
- compatible = "atmel,at91sam9x5-clk-plldiv";
- #clock-cells = <0>;
- clocks = <&plla>;
- };
-
- utmi: utmick {
- compatible = "atmel,at91sam9x5-clk-utmi";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_LOCKU>;
- clocks = <&main>;
- };
-
- mck: masterck {
- compatible = "atmel,at91sam9x5-clk-master";
- #clock-cells = <0>;
- interrupt-parent = <&pmc>;
- interrupts = <AT91_PMC_MCKRDY>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
- atmel,clk-output-range = <0 166000000>;
- atmel,clk-divisors = <1 2 4 3>;
- };
-
- usb: usbck {
- compatible = "atmel,at91sam9x5-clk-usb";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- prog: progck {
- compatible = "atmel,at91sam9x5-clk-programmable";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&pmc>;
- clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
-
- prog0: prog0 {
- #clock-cells = <0>;
- reg = <0>;
- interrupts = <AT91_PMC_PCKRDY(0)>;
- };
-
- prog1: prog1 {
- #clock-cells = <0>;
- reg = <1>;
- interrupts = <AT91_PMC_PCKRDY(1)>;
- };
-
- prog2: prog2 {
- #clock-cells = <0>;
- reg = <2>;
- interrupts = <AT91_PMC_PCKRDY(2)>;
- };
- };
-
- smd: smdclk {
- compatible = "atmel,at91sam9x5-clk-smd";
- #clock-cells = <0>;
- clocks = <&plladiv>, <&utmi>;
- };
-
- systemck {
- compatible = "atmel,at91rm9200-clk-system";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ddrck: ddrck {
- #clock-cells = <0>;
- reg = <2>;
- clocks = <&mck>;
- };
-
- smdck: smdck {
- #clock-cells = <0>;
- reg = <4>;
- clocks = <&smd>;
- };
-
- uhpck: uhpck {
- #clock-cells = <0>;
- reg = <6>;
- clocks = <&usb>;
- };
-
- udpck: udpck {
- #clock-cells = <0>;
- reg = <7>;
- clocks = <&usb>;
- };
-
- pck0: pck0 {
- #clock-cells = <0>;
- reg = <8>;
- clocks = <&prog0>;
- };
-
- pck1: pck1 {
- #clock-cells = <0>;
- reg = <9>;
- clocks = <&prog1>;
- };
-
- pck2: pck2 {
- #clock-cells = <0>;
- reg = <10>;
- clocks = <&prog2>;
- };
- };
-
- periphck {
- compatible = "atmel,at91sam9x5-clk-peripheral";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&mck>;
-
- dbgu_clk: dbgu_clk {
- #clock-cells = <0>;
- reg = <2>;
- };
-
- hsmc_clk: hsmc_clk {
- #clock-cells = <0>;
- reg = <5>;
- };
-
- pioA_clk: pioA_clk {
- #clock-cells = <0>;
- reg = <6>;
- };
-
- pioB_clk: pioB_clk {
- #clock-cells = <0>;
- reg = <7>;
- };
-
- pioC_clk: pioC_clk {
- #clock-cells = <0>;
- reg = <8>;
- };
-
- pioD_clk: pioD_clk {
- #clock-cells = <0>;
- reg = <9>;
- };
-
- pioE_clk: pioE_clk {
- #clock-cells = <0>;
- reg = <10>;
- };
-
- usart0_clk: usart0_clk {
- #clock-cells = <0>;
- reg = <12>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- usart1_clk: usart1_clk {
- #clock-cells = <0>;
- reg = <13>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- usart2_clk: usart2_clk {
- #clock-cells = <0>;
- reg = <14>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- usart3_clk: usart3_clk {
- #clock-cells = <0>;
- reg = <15>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- uart0_clk: uart0_clk {
- #clock-cells = <0>;
- reg = <16>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- twi0_clk: twi0_clk {
- reg = <18>;
- #clock-cells = <0>;
- atmel,clk-output-range = <0 41500000>;
- };
-
- twi1_clk: twi1_clk {
- #clock-cells = <0>;
- reg = <19>;
- atmel,clk-output-range = <0 41500000>;
- };
-
- twi2_clk: twi2_clk {
- #clock-cells = <0>;
- reg = <20>;
- atmel,clk-output-range = <0 41500000>;
- };
-
- mci0_clk: mci0_clk {
- #clock-cells = <0>;
- reg = <21>;
- };
-
- mci1_clk: mci1_clk {
- #clock-cells = <0>;
- reg = <22>;
- };
-
- spi0_clk: spi0_clk {
- #clock-cells = <0>;
- reg = <24>;
- atmel,clk-output-range = <0 166000000>;
- };
-
- spi1_clk: spi1_clk {
- #clock-cells = <0>;
- reg = <25>;
- atmel,clk-output-range = <0 166000000>;
- };
-
- tcb0_clk: tcb0_clk {
- #clock-cells = <0>;
- reg = <26>;
- atmel,clk-output-range = <0 166000000>;
- };
-
- pwm_clk: pwm_clk {
- #clock-cells = <0>;
- reg = <28>;
- };
-
- adc_clk: adc_clk {
- #clock-cells = <0>;
- reg = <29>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- dma0_clk: dma0_clk {
- #clock-cells = <0>;
- reg = <30>;
- };
-
- dma1_clk: dma1_clk {
- #clock-cells = <0>;
- reg = <31>;
- };
-
- uhphs_clk: uhphs_clk {
- #clock-cells = <0>;
- reg = <32>;
- };
-
- udphs_clk: udphs_clk {
- #clock-cells = <0>;
- reg = <33>;
- };
-
- isi_clk: isi_clk {
- #clock-cells = <0>;
- reg = <37>;
- };
-
- ssc0_clk: ssc0_clk {
- #clock-cells = <0>;
- reg = <38>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- ssc1_clk: ssc1_clk {
- #clock-cells = <0>;
- reg = <39>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- sha_clk: sha_clk {
- #clock-cells = <0>;
- reg = <42>;
- };
-
- aes_clk: aes_clk {
- #clock-cells = <0>;
- reg = <43>;
- };
-
- tdes_clk: tdes_clk {
- #clock-cells = <0>;
- reg = <44>;
- };
-
- trng_clk: trng_clk {
- #clock-cells = <0>;
- reg = <45>;
- };
-
- fuse_clk: fuse_clk {
- #clock-cells = <0>;
- reg = <48>;
- };
-
- mpddr_clk: mpddr_clk {
- #clock-cells = <0>;
- reg = <49>;
- };
- };
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
};
reset_controller: rstc@fffffe00 {
@@ -1357,7 +1043,7 @@
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe30 0xf>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
watchdog: watchdog@fffffe40 {
@@ -1390,130 +1076,26 @@
compatible = "mmio-sram";
no-memory-wc;
reg = <0x200000 0x2400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x200000 0x2400>;
};
usb0: gadget@500000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "atmel,sama5d3-udc";
reg = <0x00500000 0x100000
0xf8030000 0x4000>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&udphs_clk>, <&utmi>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
-
- ep@0 {
- reg = <0>;
- atmel,fifo-size = <64>;
- atmel,nb-banks = <1>;
- };
-
- ep@1 {
- reg = <1>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@2 {
- reg = <2>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@3 {
- reg = <3>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- };
-
- ep@4 {
- reg = <4>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- };
-
- ep@5 {
- reg = <5>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- };
-
- ep@6 {
- reg = <6>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- };
-
- ep@7 {
- reg = <7>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- };
-
- ep@8 {
- reg = <8>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- };
-
- ep@9 {
- reg = <9>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- };
-
- ep@10 {
- reg = <10>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- };
-
- ep@11 {
- reg = <11>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- };
-
- ep@12 {
- reg = <12>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- };
-
- ep@13 {
- reg = <13>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- };
-
- ep@14 {
- reg = <14>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- };
-
- ep@15 {
- reg = <15>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- };
};
usb1: ohci@600000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
@@ -1522,7 +1104,7 @@
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
- clocks = <&utmi>, <&uhphs_clk>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 32>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
@@ -1538,7 +1120,7 @@
0x1 0x0 0x40000000 0x10000000
0x2 0x0 0x50000000 0x10000000
0x3 0x0 0x60000000 0x10000000>;
- clocks = <&mck>;
+ clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
index 2470dd3..9ac29bf 100644
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -31,29 +31,13 @@
};
- pmc: pmc@fffffc00 {
- periphck {
- can0_clk: can0_clk {
- #clock-cells = <0>;
- reg = <40>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- can1_clk: can1_clk {
- #clock-cells = <0>;
- reg = <41>;
- atmel,clk-output-range = <0 83000000>;
- };
- };
- };
-
can0: can@f000c000 {
compatible = "atmel,at91sam9x5-can";
reg = <0xf000c000 0x300>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
- clocks = <&can0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
clock-names = "can_clk";
status = "disabled";
};
@@ -64,7 +48,7 @@
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
- clocks = <&can1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
clock-names = "can_clk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
index 9aef414..4522610 100644
--- a/arch/arm/boot/dts/sama5d3_emac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -31,12 +31,6 @@
};
pmc: pmc@fffffc00 {
- periphck {
- macb1_clk: macb1_clk {
- #clock-cells = <0>;
- reg = <35>;
- };
- };
};
macb1: ethernet@f802c000 {
@@ -45,7 +39,7 @@
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb1_rmii>;
- clocks = <&macb1_clk>, <&macb1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_PERIPHERAL 35>;
clock-names = "hclk", "pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
index 3667765..884df7a 100644
--- a/arch/arm/boot/dts/sama5d3_gmac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -63,22 +63,13 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- macb0_clk: macb0_clk {
- #clock-cells = <0>;
- reg = <34>;
- };
- };
- };
-
macb0: ethernet@f0028000 {
compatible = "atmel,sama5d3-gem";
reg = <0xf0028000 0x100>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
- clocks = <&macb0_clk>, <&macb0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_PERIPHERAL 34>;
clock-names = "hclk", "pclk";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
index 2cf046c..308d2fc 100644
--- a/arch/arm/boot/dts/sama5d3_lcd.dtsi
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -16,7 +16,7 @@
compatible = "atmel,sama5d3-hlcdc";
reg = <0xf0030000 0x2000>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
status = "disabled";
@@ -192,23 +192,6 @@
};
};
};
-
- pmc: pmc@fffffc00 {
- periphck {
- lcdc_clk: lcdc_clk {
- #clock-cells = <0>;
- reg = <36>;
- };
- };
-
- systemck {
- lcdck: lcdck {
- #clock-cells = <0>;
- reg = <3>;
- clocks = <&mck>;
- };
- };
- };
};
};
};
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
index 3c83c1c..7141ee9 100644
--- a/arch/arm/boot/dts/sama5d3_mci2.dtsi
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -30,15 +30,6 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- mci2_clk: mci2_clk {
- #clock-cells = <0>;
- reg = <23>;
- };
- };
- };
-
mmc2: mmc@f8004000 {
compatible = "atmel,hsmci";
reg = <0xf8004000 0x600>;
@@ -47,7 +38,7 @@
dma-names = "rxtx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
- clocks = <&mci2_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
clock-names = "mci_clk";
status = "disabled";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
index 215802b..2b18c5c 100644
--- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -17,23 +17,13 @@
ahb {
apb {
- pmc: pmc@fffffc00 {
- periphck {
- tcb1_clk: tcb1_clk {
- #clock-cells = <0>;
- reg = <27>;
- atmel,clk-output-range = <0 166000000>;
- };
- };
- };
-
tcb1: timer@f8014000 {
compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf8014000 0x100>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb1_clk>, <&clk32k>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&clk32k>;
clock-names = "t0_clk", "slow_clk";
};
};
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index cb62adb..a3eaba9 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -36,29 +36,13 @@
};
};
- pmc: pmc@fffffc00 {
- periphck {
- uart0_clk: uart0_clk {
- #clock-cells = <0>;
- reg = <16>;
- atmel,clk-output-range = <0 83000000>;
- };
-
- uart1_clk: uart1_clk {
- #clock-cells = <0>;
- reg = <17>;
- atmel,clk-output-range = <0 83000000>;
- };
- };
- };
-
uart0: serial@f0024000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xf0024000 0x100>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
- clocks = <&uart0_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
clock-names = "usart";
status = "disabled";
};
@@ -69,7 +53,7 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- clocks = <&uart1_clk>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
clock-names = "usart";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 65566e4..3843356 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -14,7 +14,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
index 9d25636..5579c95 100644
--- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
@@ -12,7 +12,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x20000000>;
};
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 35031bb..a499de8 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -46,7 +46,7 @@
wm8904: wm8904@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
- clocks = <&pck0>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "mclk";
};
};
@@ -60,9 +60,9 @@
resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
/* use pck1 for the master clock of ov2640 */
- clocks = <&pck1>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 9>;
clock-names = "xvclk";
- assigned-clocks = <&pck1>;
+ assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>;
assigned-clock-rates = <25000000>;
port {
diff --git a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
index 8a6916a..fa9e5e2 100644
--- a/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
@@ -45,7 +45,7 @@
wm8904: wm8904@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
- clocks = <&pck0>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 8>;
clock-names = "mclk";
};
};
@@ -59,9 +59,9 @@
resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
/* use pck1 for the master clock of ov2640 */
- clocks = <&pck1>;
+ clocks = <&pmc PMC_TYPE_SYSTEM 9>;
clock-names = "xvclk";
- assigned-clocks = <&pck1>;
+ assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>;
assigned-clock-rates = <25000000>;
port {
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index a4cef07..e5c2c52 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -53,7 +53,7 @@
};
};
- memory {
+ memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x20000000>;
};
@@ -81,6 +81,9 @@
ns_sram: sram@210000 {
compatible = "mmio-sram";
reg = <0x00210000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00210000 0x10000>;
};
ahb {
@@ -93,11 +96,12 @@
compatible = "mmio-sram";
no-memory-wc;
reg = <0x100000 0x2400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x100000 0x2400>;
};
usb0: gadget@400000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "atmel,sama5d3-udc";
reg = <0x00400000 0x100000
0xfc02c000 0x4000>;
@@ -105,124 +109,6 @@
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
clock-names = "pclk", "hclk";
status = "disabled";
-
- ep@0 {
- reg = <0>;
- atmel,fifo-size = <64>;
- atmel,nb-banks = <1>;
- };
-
- ep@1 {
- reg = <1>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@2 {
- reg = <2>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <3>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@3 {
- reg = <3>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@4 {
- reg = <4>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@5 {
- reg = <5>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@6 {
- reg = <6>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@7 {
- reg = <7>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-dma;
- atmel,can-isoc;
- };
-
- ep@8 {
- reg = <8>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@9 {
- reg = <9>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@10 {
- reg = <10>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@11 {
- reg = <11>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@12 {
- reg = <12>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@13 {
- reg = <13>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@14 {
- reg = <14>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
-
- ep@15 {
- reg = <15>;
- atmel,fifo-size = <1024>;
- atmel,nb-banks = <2>;
- atmel,can-isoc;
- };
};
usb1: ohci@500000 {
@@ -458,8 +344,11 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(3))>;
dma-names = "tx", "rx";
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
@@ -477,8 +366,11 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(5))>;
dma-names = "tx", "rx";
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
@@ -519,8 +411,11 @@
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
| AT91_XDMAC_DT_PERID(7))>;
dma-names = "tx", "rx";
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
@@ -884,7 +779,7 @@
};
rtc@fc0686b0 {
- compatible = "atmel,at91rm9200-rtc";
+ compatible = "atmel,sama5d4-rtc";
reg = <0xfc0686b0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k>;
@@ -1122,6 +1017,12 @@
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ atmel,pins =
+ <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
};
i2c1 {
@@ -1130,6 +1031,12 @@
<AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */
AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
};
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ atmel,pins =
+ <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
};
i2c2 {
@@ -1138,6 +1045,12 @@
<AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
};
+
+ pinctrl_i2c2_gpio: i2c2-gpio {
+ atmel,pins =
+ <AT91_PIOB 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOB 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
};
isi {
diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
new file mode 100644
index 0000000..3cc9a23
--- /dev/null
+++ b/arch/arm/boot/dts/sd5203.dts
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 Hisilicon Limited.
+ *
+ * DTS file for Hisilicon SD5203 Board
+ */
+
+/dts-v1/;
+
+/ {
+ model = "Hisilicon SD5203";
+ compatible = "H836ASDJ", "hisilicon,sd5203";
+ interrupt-parent = <&vic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0 {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ reg = <0x0>;
+ };
+ };
+
+ memory@30000000 {
+ device_type = "memory";
+ reg = <0x30000000 0x8000000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges;
+
+ vic: interrupt-controller@10130000 {
+ compatible = "snps,dw-apb-ictl";
+ reg = <0x10130000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ refclk125mhz: refclk125mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ timer0: timer@16002000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x16002000 0x1000>;
+ interrupts = <4>;
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ timer1: timer@16003000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x16003000 0x1000>;
+ interrupts = <5>;
+ clocks = <&refclk125mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ uart0: serial@1600d000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x1600d000 0x1000>;
+ bus_id = "uart0";
+ clocks = <&refclk125mhz>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <17>;
+ };
+
+ uart1: serial@1600c000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x1600c000 0x1000>;
+ clocks = <&refclk125mhz>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index 1916f31..5a8d92a 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -25,12 +25,9 @@
cpus {
cpu@0 {
cpu0-supply = <&vdd_dvfs>;
- operating-points = <
- /* kHz uV */
- 1196000 1315000
- 598000 1175000
- 398667 1065000
- >;
+ operating-points = <1196000 1315000>, /* kHz uV */
+ < 598000 1175000>,
+ < 398667 1065000>;
voltage-tolerance = <1>; /* 1% */
};
};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 3383699..30c67ac 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -39,11 +39,18 @@
};
};
+ timer@f0000200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xf0000200 0x100>;
+ interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&periph_clk>;
+ };
+
timer@f0000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf0000600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
- clocks = <&twd_clk>;
+ clocks = <&periph_clk>;
};
gic: interrupt-controller@f0001000 {
@@ -92,7 +99,7 @@
};
cmt1: timer@e6138000 {
- compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
+ compatible = "renesas,sh73a0-cmt1";
reg = <0xe6138000 0x200>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
@@ -110,14 +117,14 @@
<0xe6900020 1>,
<0xe6900040 1>,
<0xe6900060 1>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
@@ -132,14 +139,14 @@
<0xe6900024 1>,
<0xe6900044 1>,
<0xe6900064 1>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
@@ -154,14 +161,14 @@
<0xe6900028 1>,
<0xe6900048 1>,
<0xe6900068 1>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
@@ -176,14 +183,14 @@
<0xe690002c 1>,
<0xe690004c 1>,
<0xe690006c 1>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
power-domains = <&pd_a4s>;
control-parent;
@@ -194,10 +201,10 @@
#size-cells = <0>;
compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
reg = <0xe6820000 0x425>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -208,10 +215,10 @@
#size-cells = <0>;
compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
reg = <0xe6822000 0x425>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -222,10 +229,10 @@
#size-cells = <0>;
compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
reg = <0xe6824000 0x425>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -236,10 +243,10 @@
#size-cells = <0>;
compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
reg = <0xe6826000 0x425>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
power-domains = <&pd_a3sp>;
status = "disabled";
@@ -250,10 +257,10 @@
#size-cells = <0>;
compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
reg = <0xe6828000 0x425>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
power-domains = <&pd_c5>;
status = "disabled";
@@ -262,8 +269,8 @@
mmcif: mmc@e6bd0000 {
compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
reg = <0xe6bd0000 0x100>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
power-domains = <&pd_a3sp>;
reg-io-width = <4>;
@@ -314,12 +321,12 @@
status = "disabled";
};
- sdhi0: sd@ee100000 {
+ sdhi0: mmc@ee100000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee100000 0x100>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
power-domains = <&pd_a3sp>;
cap-sd-highspeed;
@@ -327,11 +334,11 @@
};
/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
- sdhi1: sd@ee120000 {
+ sdhi1: mmc@ee120000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee120000 0x100>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
power-domains = <&pd_a3sp>;
disable-wp;
@@ -339,11 +346,11 @@
status = "disabled";
};
- sdhi2: sd@ee140000 {
+ sdhi2: mmc@ee140000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee140000 0x100>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
power-domains = <&pd_a3sp>;
disable-wp;
@@ -441,7 +448,7 @@
status = "disabled";
};
- pfc: pin-controller@e6050000 {
+ pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;
@@ -577,6 +584,7 @@
compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
reg = <0xec230000 0x400>;
interrupts = <GIC_SPI 146 0x4>;
+ clocks = <&mstp3_clks SH73A0_CLK_FSI>;
power-domains = <&pd_a4mp>;
status = "disabled";
};
@@ -612,19 +620,25 @@
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
};
extcki_clk: extcki {
compatible = "fixed-clock";
#clock-cells = <0>;
+ /* This value can be overridden by the board. */
+ clock-frequency = <0>;
};
fsiack_clk: fsiack {
compatible = "fixed-clock";
#clock-cells = <0>;
+ /* This value can be overridden by the board. */
clock-frequency = <0>;
};
fsibck_clk: fsibck {
compatible = "fixed-clock";
#clock-cells = <0>;
+ /* This value can be overridden by the board. */
clock-frequency = <0>;
};
@@ -812,7 +826,7 @@
clock-div = <13>;
clock-mult = <1>;
};
- twd_clk: twd {
+ periph_clk: periph {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks SH73A0_CLK_Z>;
#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4510308..0b021ee 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -531,6 +531,7 @@
reg = <0xff400000 0x100000>;
resets = <&rst LWHPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
+ status = "disabled";
};
fpga_bridge1: fpga_bridge@ff500000 {
@@ -538,6 +539,21 @@
reg = <0xff500000 0x10000>;
resets = <&rst HPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
+ status = "disabled";
+ };
+
+ fpga_bridge2: fpga-bridge@ff600000 {
+ compatible = "altr,socfpga-fpga2hps-bridge";
+ reg = <0xff600000 0x100000>;
+ resets = <&rst FPGA2HPS_RESET>;
+ clocks = <&l4_main_clk>;
+ status = "disabled";
+ };
+
+ fpga_bridge3: fpga-bridge@ffc25080 {
+ compatible = "altr,socfpga-fpga2sdram-bridge";
+ reg = <0xffc25080 0x4>;
+ status = "disabled";
};
fpgamgr0: fpgamgr@ff706000 {
@@ -813,6 +829,7 @@
num-cs = <4>;
clocks = <&spi_m_clk>;
resets = <&rst SPIM0_RESET>;
+ reset-names = "spi";
status = "disabled";
};
@@ -825,6 +842,7 @@
num-cs = <4>;
clocks = <&spi_m_clk>;
resets = <&rst SPIM1_RESET>;
+ reset-names = "spi";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index f261a33..0013ec3 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -431,8 +431,8 @@
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
- clocks = <&l4_mp_clk>;
- clock-names = "stmmaceth";
+ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
+ clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
snps,axi-config = <&socfpga_axi_setup>;
@@ -451,8 +451,8 @@
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
- clocks = <&l4_mp_clk>;
- clock-names = "stmmaceth";
+ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
+ clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
snps,axi-config = <&socfpga_axi_setup>;
@@ -471,8 +471,8 @@
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
- clocks = <&l4_mp_clk>;
- clock-names = "stmmaceth";
+ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
+ clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
snps,axi-config = <&socfpga_axi_setup>;
@@ -613,6 +613,7 @@
/*32bit_access;*/
clocks = <&spi_m_clk>;
resets = <&rst SPIM0_RESET>;
+ reset-names = "spi";
status = "disabled";
};
@@ -628,6 +629,7 @@
rx-dma-channel = <&pdma 17>;
clocks = <&spi_m_clk>;
resets = <&rst SPIM1_RESET>;
+ reset-names = "spi";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 0efbecc..7edebe2 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -162,6 +162,11 @@
compatible = "ltc2977";
reg = <0x5c>;
};
+
+ temp@4c {
+ compatible = "maxim,max1619";
+ reg = <0x4c>;
+ };
};
&uart1 {
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
index 9bd9e04..9aa897b 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
@@ -16,11 +16,11 @@
partition@0 {
label = "Boot and fpga data";
- reg = <0x0 0x1C00000>;
+ reg = <0x0 0x02000000>;
};
partition@1c00000 {
label = "Root Filesystem - JFFS2";
- reg = <0x1C00000 0x6400000>;
+ reg = <0x02000000 0x06000000>;
};
};
};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
index b4c0a76..2a74552 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts
@@ -12,14 +12,14 @@
flash0: n25q00@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00aa";
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
- cdns,read-delay = <4>;
+ cdns,read-delay = <3>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 90e676e..1b02d46 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -119,7 +119,7 @@
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q256a";
+ compatible = "micron,n25q256a", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 6f138b2..51bb436 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -124,7 +124,7 @@
flash0: n25q00@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00";
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index c155ff0..cae9ddd 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -169,7 +169,7 @@
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00";
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
index 8d5d399..ca18b95 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
@@ -80,7 +80,7 @@
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q256a";
+ compatible = "micron,n25q256a", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
m25p,fast-read;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
index 99a7175..3f7aa7b 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
@@ -116,7 +116,7 @@
flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q512a";
+ compatible = "micron,n25q512a", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index a060718..25874e1 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -224,7 +224,7 @@
n25q128@0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q128";
+ compatible = "micron,n25q128", "jedec,spi-nor";
reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;
@@ -241,7 +241,7 @@
n25q00@1 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00";
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
reg = <1>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index f187da4..c87b881 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -43,7 +43,7 @@
0 7 0x04>;
};
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xed000000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index f266b7b..cc88ebe 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -47,7 +47,7 @@
};
gmac: eth@e0800000 {
- compatible = "st,spear600-gmac";
+ compatible = "snps,dwmac-3.40a";
reg = <0xe0800000 0x8000>;
interrupts = <23 22>;
interrupt-names = "macirq", "eth_wake_irq";
diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi
index 55fff4d..16d5036 100644
--- a/arch/arm/boot/dts/ste-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-ab8500.dtsi
@@ -6,6 +6,20 @@
#include <dt-bindings/clock/ste-ab8500.h>
/ {
+ /* Essential housekeeping hardware monitors */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&gpadc 0x02>, /* Battery temperature */
+ <&gpadc 0x03>, /* Main charger voltage */
+ <&gpadc 0x08>, /* Main battery voltage */
+ <&gpadc 0x09>, /* VBUS */
+ <&gpadc 0x0a>, /* Main charger current */
+ <&gpadc 0x0b>, /* USB charger current */
+ <&gpadc 0x0c>, /* Backup battery voltage */
+ <&gpadc 0x0d>, /* Die temperature */
+ <&gpadc 0x12>; /* Crystal temperature */
+ };
+
soc {
prcmu@80157000 {
ab8500 {
@@ -20,7 +34,7 @@
#clock-cells = <1>;
};
- ab8500_gpio: ab8500-gpio {
+ ab8500_gpio: ab8500-gpiocontroller {
compatible = "stericsson,ab8500-gpio";
gpio-controller;
#gpio-cells = <2>;
@@ -28,17 +42,89 @@
ab8500-rtc {
compatible = "stericsson,ab8500-rtc";
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH
- 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "60S", "ALARM";
};
- ab8500-gpadc {
+ gpadc: ab8500-gpadc {
compatible = "stericsson,ab8500-gpadc";
- interrupts = <32 IRQ_TYPE_LEVEL_HIGH
- 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
+ <39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "HW_CONV_END", "SW_CONV_END";
vddadc-supply = <&ab8500_ldo_tvout_reg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ /* GPADC channels */
+ bat_ctrl: channel@01 {
+ reg = <0x01>;
+ };
+ btemp_ball: channel@02 {
+ reg = <0x02>;
+ };
+ main_charger_v: channel@03 {
+ reg = <0x03>;
+ };
+ acc_detect1: channel@04 {
+ reg = <0x04>;
+ };
+ acc_detect2: channel@05 {
+ reg = <0x05>;
+ };
+ adc_aux1: channel@06 {
+ reg = <0x06>;
+ };
+ adc_aux2: channel@07 {
+ reg = <0x07>;
+ };
+ main_batt_v: channel@08 {
+ reg = <0x08>;
+ };
+ vbus_v: channel@09 {
+ reg = <0x09>;
+ };
+ main_charger_c: channel@0a {
+ reg = <0x0a>;
+ };
+ usb_charger_c: channel@0b {
+ reg = <0x0b>;
+ };
+ bk_bat_v: channel@0c {
+ reg = <0x0c>;
+ };
+ die_temp: channel@0d {
+ reg = <0x0d>;
+ };
+ usb_id: channel@0e {
+ reg = <0x0e>;
+ };
+ xtal_temp: channel@12 {
+ reg = <0x12>;
+ };
+ vbat_true_meas: channel@13 {
+ reg = <0x13>;
+ };
+ bat_ctrl_and_ibat: channel@1c {
+ reg = <0x1c>;
+ };
+ vbat_meas_and_ibat: channel@1d {
+ reg = <0x1d>;
+ };
+ vbat_true_meas_and_ibat: channel@1e {
+ reg = <0x1e>;
+ };
+ bat_temp_and_ibat: channel@1f {
+ reg = <0x1f>;
+ };
+ };
+
+ ab8500_temp {
+ compatible = "stericsson,abx500-temp";
+ io-channels = <&gpadc 0x06>,
+ <&gpadc 0x07>;
+ io-channel-name = "aux1", "aux2";
};
ab8500_battery: ab8500_battery {
@@ -49,17 +135,31 @@
ab8500_fg {
compatible = "stericsson,ab8500-fg";
battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x08>;
+ io-channel-name = "main_bat_v";
};
ab8500_btemp {
compatible = "stericsson,ab8500-btemp";
battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x02>,
+ <&gpadc 0x01>;
+ io-channel-name = "btemp_ball",
+ "bat_ctrl";
};
ab8500_charger {
compatible = "stericsson,ab8500-charger";
battery = <&ab8500_battery>;
vddadc-supply = <&ab8500_ldo_tvout_reg>;
+ io-channels = <&gpadc 0x03>,
+ <&gpadc 0x0a>,
+ <&gpadc 0x09>,
+ <&gpadc 0x0b>;
+ io-channel-name = "main_charger_v",
+ "main_charger_c",
+ "vbus_v",
+ "usb_charger_c";
};
ab8500_chargalg {
@@ -69,13 +169,13 @@
ab8500_usb {
compatible = "stericsson,ab8500-usb";
- interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
- 96 IRQ_TYPE_LEVEL_HIGH
- 14 IRQ_TYPE_LEVEL_HIGH
- 15 IRQ_TYPE_LEVEL_HIGH
- 79 IRQ_TYPE_LEVEL_HIGH
- 74 IRQ_TYPE_LEVEL_HIGH
- 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <90 IRQ_TYPE_LEVEL_HIGH>,
+ <96 IRQ_TYPE_LEVEL_HIGH>,
+ <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>,
+ <74 IRQ_TYPE_LEVEL_HIGH>,
+ <75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ID_WAKEUP_R",
"ID_WAKEUP_F",
"VBUS_DET_F",
@@ -92,8 +192,8 @@
ab8500-ponkey {
compatible = "stericsson,ab8500-poweron-key";
- interrupts = <6 IRQ_TYPE_LEVEL_HIGH
- 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
};
@@ -101,7 +201,19 @@
compatible = "stericsson,ab8500-sysctrl";
};
- ab8500-pwm {
+ ab8500-pwm-1 {
+ compatible = "stericsson,ab8500-pwm";
+ clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
+ clock-names = "intclk";
+ };
+
+ ab8500-pwm-2 {
+ compatible = "stericsson,ab8500-pwm";
+ clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
+ clock-names = "intclk";
+ };
+
+ ab8500-pwm-3 {
compatible = "stericsson,ab8500-pwm";
clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
clock-names = "intclk";
@@ -214,13 +326,13 @@
mcde@a0350000 {
vana-supply = <&ab8500_ldo_ana_reg>;
- dsi@a0351000 {
+ dsi-controller@a0351000 {
vana-supply = <&ab8500_ldo_ana_reg>;
};
- dsi@a0352000 {
+ dsi-controller@a0352000 {
vana-supply = <&ab8500_ldo_ana_reg>;
};
- dsi@a0353000 {
+ dsi-controller@a0353000 {
vana-supply = <&ab8500_ldo_ana_reg>;
};
};
diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi
new file mode 100644
index 0000000..8d2cda0
--- /dev/null
+++ b/arch/arm/boot/dts/ste-ab8505.dtsi
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2012 Linaro Ltd
+ */
+
+#include <dt-bindings/clock/ste-ab8500.h>
+
+/ {
+ /* Essential housekeeping hardware monitors */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&gpadc 0x02>, /* Battery temperature */
+ <&gpadc 0x08>, /* Main battery voltage */
+ <&gpadc 0x09>, /* VBUS */
+ <&gpadc 0x0b>, /* Charger current */
+ <&gpadc 0x0c>; /* Backup battery voltage */
+ };
+
+ soc {
+ prcmu@80157000 {
+ ab8505 {
+ compatible = "stericsson,ab8505";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ab8500_clock: clock-controller {
+ compatible = "stericsson,ab8500-clk";
+ #clock-cells = <1>;
+ };
+
+ ab8505_gpio: ab8505-gpiocontroller {
+ compatible = "stericsson,ab8505-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ab8500-rtc {
+ compatible = "stericsson,ab8500-rtc";
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "60S", "ALARM";
+ };
+
+ gpadc: ab8500-gpadc {
+ compatible = "stericsson,ab8500-gpadc";
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH
+ 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "HW_CONV_END", "SW_CONV_END";
+ vddadc-supply = <&ab8500_ldo_adc_reg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ /* GPADC channels */
+ bat_ctrl: channel@01 {
+ reg = <0x01>;
+ };
+ btemp_ball: channel@02 {
+ reg = <0x02>;
+ };
+ acc_detect1: channel@04 {
+ reg = <0x04>;
+ };
+ acc_detect2: channel@05 {
+ reg = <0x05>;
+ };
+ adc_aux1: channel@06 {
+ reg = <0x06>;
+ };
+ adc_aux2: channel@07 {
+ reg = <0x07>;
+ };
+ main_batt_v: channel@08 {
+ reg = <0x08>;
+ };
+ vbus_v: channel@09 {
+ reg = <0x09>;
+ };
+ charger_c: channel@0b {
+ reg = <0x0b>;
+ };
+ bk_bat_v: channel@0c {
+ reg = <0x0c>;
+ };
+ usb_id: channel@0e {
+ reg = <0x0e>;
+ };
+ };
+
+ ab8500_battery: ab8500_battery {
+ status = "disabled";
+ thermistor-on-batctrl;
+ };
+
+ ab8500_fg {
+ status = "disabled";
+ compatible = "stericsson,ab8500-fg";
+ battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x08>;
+ io-channel-name = "main_bat_v";
+ };
+
+ ab8500_btemp {
+ status = "disabled";
+ compatible = "stericsson,ab8500-btemp";
+ battery = <&ab8500_battery>;
+ io-channels = <&gpadc 0x02>,
+ <&gpadc 0x01>;
+ io-channel-name = "btemp_ball",
+ "bat_ctrl";
+ };
+
+ ab8500_charger {
+ status = "disabled";
+ compatible = "stericsson,ab8500-charger";
+ battery = <&ab8500_battery>;
+ vddadc-supply = <&ab8500_ldo_adc_reg>;
+ io-channels = <&gpadc 0x09>,
+ <&gpadc 0x0b>;
+ io-channel-name = "vbus_v",
+ "usb_charger_c";
+ };
+
+ ab8500_chargalg {
+ status = "disabled";
+ compatible = "stericsson,ab8500-chargalg";
+ battery = <&ab8500_battery>;
+ };
+
+ ab8500_usb: ab8500_usb {
+ compatible = "stericsson,ab8500-usb";
+ interrupts = <90 IRQ_TYPE_LEVEL_HIGH>,
+ <96 IRQ_TYPE_LEVEL_HIGH>,
+ <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>,
+ <74 IRQ_TYPE_LEVEL_HIGH>,
+ <75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ID_WAKEUP_R",
+ "ID_WAKEUP_F",
+ "VBUS_DET_F",
+ "VBUS_DET_R",
+ "USB_LINK_STATUS",
+ "USB_ADP_PROBE_PLUG",
+ "USB_ADP_PROBE_UNPLUG";
+ vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
+ v-ape-supply = <&db8500_vape_reg>;
+ musb_1v8-supply = <&db8500_vsmps2_reg>;
+ clocks = <&prcmu_clk PRCMU_SYSCLK>;
+ clock-names = "sysclk";
+ };
+
+ ab8500-ponkey {
+ compatible = "stericsson,ab8500-poweron-key";
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
+ };
+
+ ab8500-sysctrl {
+ compatible = "stericsson,ab8500-sysctrl";
+ };
+
+ ab8500-pwm {
+ compatible = "stericsson,ab8500-pwm";
+ clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
+ clock-names = "intclk";
+ };
+
+ ab8500-debugfs {
+ compatible = "stericsson,ab8500-debug";
+ };
+
+ codec: ab8500-codec {
+ compatible = "stericsson,ab8500-codec";
+
+ V-AUD-supply = <&ab8500_ldo_audio_reg>;
+ V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
+ V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
+
+ clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
+ clock-names = "audioclk";
+
+ stericsson,earpeice-cmv = <950>; /* Units in mV. */
+ };
+
+ ab8505-regulators {
+ compatible = "stericsson,ab8505-regulator";
+
+ ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux4_reg: ab8500_ldo_aux4 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux5_reg: ab8500_ldo_aux5 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <2790000>;
+ };
+
+ ab8500_ldo_aux6_reg: ab8500_ldo_aux6 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <2790000>;
+ };
+
+ // supply for v-intcore12; VINTCORE12 LDO
+ ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ // supply for gpadc; ADC LDO
+ ab8500_ldo_adc_reg: ab8500_ldo_adc {
+ };
+
+ // supply for ab8500-vaudio; VAUDIO LDO
+ ab8500_ldo_audio_reg: ab8500_ldo_audio {
+ };
+
+ // supply for v-anamic1 VAMIC1 LDO
+ ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
+ };
+
+ // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
+ ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
+ };
+
+ // supply for v-aux8; VAUX8 LDO
+ ab8500_ldo_aux8_reg: ab8500_ldo_aux8 {
+ };
+
+ // supply for U8500 CSI/DSI; VANA LDO
+ ab8500_ldo_ana_reg: ab8500_ldo_ana {
+ };
+ };
+ };
+ };
+
+ sound {
+ stericsson,audio-codec = <&codec>;
+ clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
+ clock-names = "sysclk", "ulpclk", "intclk";
+ };
+
+ mcde@a0350000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+
+ dsi-controller@a0351000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ dsi-controller@a0352000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ dsi-controller@a0353000 {
+ vana-supply = <&ab8500_ldo_ana_reg>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-db8500.dtsi b/arch/arm/boot/dts/ste-db8500.dtsi
new file mode 100644
index 0000000..344d298
--- /dev/null
+++ b/arch/arm/boot/dts/ste-db8500.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "ste-dbx5x0.dtsi"
+
+/ {
+ cpus {
+ cpu@300 {
+ /* cpufreq controls */
+ operating-points = <998400 0
+ 800000 0
+ 400000 0
+ 200000 0>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* Modem trace memory */
+ ram@06000000 {
+ reg = <0x06000000 0x00f00000>;
+ no-map;
+ };
+
+ /* Modem shared memory */
+ ram@06f00000 {
+ reg = <0x06f00000 0x00100000>;
+ no-map;
+ };
+
+ /* Modem private memory */
+ ram@07000000 {
+ reg = <0x07000000 0x01000000>;
+ no-map;
+ };
+
+ /*
+ * Initial Secure Software ISSW memory
+ *
+ * This is probably only used if the kernel tries
+ * to actually call into trustzone to run secure
+ * applications, which the mainline kernel probably
+ * will not do on this old chipset. But you can never
+ * be too careful, so reserve this memory anyway.
+ */
+ ram@17f00000 {
+ reg = <0x17f00000 0x00100000>;
+ no-map;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-db8520.dtsi b/arch/arm/boot/dts/ste-db8520.dtsi
new file mode 100644
index 0000000..287804e
--- /dev/null
+++ b/arch/arm/boot/dts/ste-db8520.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "ste-dbx5x0.dtsi"
+
+/ {
+ cpus {
+ cpu@300 {
+ /* cpufreq controls */
+ operating-points = <1152000 0
+ 800000 0
+ 400000 0
+ 200000 0>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* Modem trace memory */
+ ram@06000000 {
+ reg = <0x06000000 0x00f00000>;
+ no-map;
+ };
+
+ /* Modem shared memory */
+ ram@06f00000 {
+ reg = <0x06f00000 0x00100000>;
+ no-map;
+ };
+
+ /* Modem private memory */
+ ram@07000000 {
+ reg = <0x07000000 0x01000000>;
+ no-map;
+ };
+
+ /*
+ * Initial Secure Software ISSW memory
+ *
+ * This is probably only used if the kernel tries
+ * to actually call into trustzone to run secure
+ * applications, which the mainline kernel probably
+ * will not do on this old chipset. But you can never
+ * be too careful, so reserve this memory anyway.
+ */
+ ram@17f00000 {
+ reg = <0x17f00000 0x00100000>;
+ no-map;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-db9500.dtsi b/arch/arm/boot/dts/ste-db9500.dtsi
new file mode 100644
index 0000000..0afff70
--- /dev/null
+++ b/arch/arm/boot/dts/ste-db9500.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "ste-dbx5x0.dtsi"
+
+/ {
+ cpus {
+ cpu@300 {
+ /* cpufreq controls */
+ operating-points = <1152000 0
+ 800000 0
+ 400000 0
+ 200000 0>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /*
+ * Initial Secure Software ISSW memory
+ *
+ * This is probably only used if the kernel tries
+ * to actually call into trustzone to run secure
+ * applications, which the mainline kernel probably
+ * will not do on this old chipset. But you can never
+ * be too careful, so reserve this memory anyway.
+ */
+ ram@17f00000 {
+ reg = <0x17f00000 0x00100000>;
+ no-map;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
new file mode 100644
index 0000000..7bf7a2d
--- /dev/null
+++ b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2013 Linaro Ltd.
+ */
+
+#include "ste-nomadik-pinctrl.dtsi"
+
+&pinctrl {
+ /* Settings for all UART default and sleep states */
+ uart0 {
+ u0_a_1_default: u0_a_1_default {
+ default_mux {
+ function = "u0";
+ groups = "u0_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+ ste,config = <&in_pu>;
+ };
+ default_cfg2 {
+ pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
+ ste,config = <&out_hi>;
+ };
+ };
+
+ u0_a_1_sleep: u0_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO1_AJ3"; /* RTS */
+ ste,config = <&slpm_out_hi_wkup_pdis>;
+ };
+ sleep_cfg3 {
+ pins = "GPIO3_AH3"; /* TXD */
+ ste,config = <&slpm_out_wkup_pdis>;
+ };
+ };
+ };
+
+ uart1 {
+ u1rxtx_a_1_default: u1rxtx_a_1_default {
+ default_mux {
+ function = "u1";
+ groups = "u1rxtx_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO4_AH6"; /* RXD */
+ ste,config = <&in_pu>;
+ };
+ default_cfg2 {
+ pins = "GPIO5_AG6"; /* TXD */
+ ste,config = <&out_hi>;
+ };
+ };
+
+ u1rxtx_a_1_sleep: u1rxtx_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO4_AH6"; /* RXD */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO5_AG6"; /* TXD */
+ ste,config = <&slpm_out_wkup_pdis>;
+ };
+ };
+
+ u1ctsrts_a_1_default: u1ctsrts_a_1_default {
+ default_mux {
+ function = "u1";
+ groups = "u1ctsrts_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO6_AF6"; /* CTS */
+ ste,config = <&in_pu>;
+ };
+ default_cfg2 {
+ pins = "GPIO7_AG5"; /* RTS */
+ ste,config = <&out_hi>;
+ };
+ };
+
+ u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO6_AF6"; /* CTS */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO7_AG5"; /* RTS */
+ ste,config = <&slpm_out_hi_wkup_pdis>;
+ };
+ };
+ };
+
+ uart2 {
+ u2rxtx_c_1_default: u2rxtx_c_1_default {
+ default_mux {
+ function = "u2";
+ groups = "u2rxtx_c_1";
+ };
+ default_cfg1 {
+ pins = "GPIO29_W2"; /* RXD */
+ ste,config = <&in_pu>;
+ };
+ default_cfg2 {
+ pins = "GPIO30_W3"; /* TXD */
+ ste,config = <&out_hi>;
+ };
+ };
+
+ u2rxtx_c_1_sleep: u2rxtx_c_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO29_W2"; /* RXD */
+ ste,config = <&in_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO30_W3"; /* TXD */
+ ste,config = <&out_wkup_pdis>;
+ };
+ };
+ };
+
+ /* Settings for all I2C default and sleep states */
+ i2c0 {
+ i2c0_a_1_default: i2c0_a_1_default {
+ default_mux {
+ function = "i2c0";
+ groups = "i2c0_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
+ ste,config = <&in_nopull>;
+ };
+ };
+
+ i2c0_a_1_sleep: i2c0_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ i2c1 {
+ i2c1_b_2_default: i2c1_b_2_default {
+ default_mux {
+ function = "i2c1";
+ groups = "i2c1_b_2";
+ };
+ default_cfg1 {
+ pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
+ ste,config = <&in_nopull>;
+ };
+ };
+
+ i2c1_b_2_sleep: i2c1_b_2_sleep {
+ sleep_cfg1 {
+ pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ i2c2 {
+ i2c2_b_2_default: i2c2_b_2_default {
+ default_mux {
+ function = "i2c2";
+ groups = "i2c2_b_2";
+ };
+ default_cfg1 {
+ pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
+ ste,config = <&in_nopull>;
+ };
+ };
+
+ i2c2_b_2_sleep: i2c2_b_2_sleep {
+ sleep_cfg1 {
+ pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ i2c3 {
+ i2c3_c_2_default: i2c3_c_2_default {
+ default_mux {
+ function = "i2c3";
+ groups = "i2c3_c_2";
+ };
+ default_cfg1 {
+ pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
+ ste,config = <&in_nopull>;
+ };
+ };
+
+ i2c3_c_2_sleep: i2c3_c_2_sleep {
+ sleep_cfg1 {
+ pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ /*
+ * Activating I2C4 will conflict with UART1 about the same pins so do not
+ * enable I2C4 and UART1 at the same time.
+ */
+ i2c4 {
+ i2c4_b_1_default: i2c4_b_1_default {
+ default_mux {
+ function = "i2c4";
+ groups = "i2c4_b_1";
+ };
+ default_cfg1 {
+ pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
+ ste,config = <&in_nopull>;
+ };
+ };
+
+ i2c4_b_1_sleep: i2c4_b_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ /* Settings for all MMC/SD/SDIO default and sleep states */
+ sdi0 {
+ /* This is the external SD card slot, 4 bits wide */
+ mc0_a_1_default: mc0_a_1_default {
+ default_mux {
+ function = "mc0";
+ groups = "mc0_a_1";
+ };
+ default_cfg1 {
+ pins =
+ "GPIO18_AC2", /* CMDDIR */
+ "GPIO19_AC1", /* DAT0DIR */
+ "GPIO20_AB4"; /* DAT2DIR */
+ ste,config = <&out_hi>;
+ };
+ default_cfg2 {
+ pins = "GPIO22_AA3"; /* FBCLK */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg3 {
+ pins = "GPIO23_AA4"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg4 {
+ pins =
+ "GPIO24_AB2", /* CMD */
+ "GPIO25_Y4", /* DAT0 */
+ "GPIO26_Y2", /* DAT1 */
+ "GPIO27_AA2", /* DAT2 */
+ "GPIO28_AA1"; /* DAT3 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc0_a_1_sleep: mc0_a_1_sleep {
+ sleep_cfg1 {
+ pins =
+ "GPIO18_AC2", /* CMDDIR */
+ "GPIO19_AC1", /* DAT0DIR */
+ "GPIO20_AB4"; /* DAT2DIR */
+ ste,config = <&slpm_out_hi_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins =
+ "GPIO22_AA3", /* FBCLK */
+ "GPIO24_AB2", /* CMD */
+ "GPIO25_Y4", /* DAT0 */
+ "GPIO26_Y2", /* DAT1 */
+ "GPIO27_AA2", /* DAT2 */
+ "GPIO28_AA1"; /* DAT3 */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ sleep_cfg3 {
+ pins = "GPIO23_AA4"; /* CLK */
+ ste,config = <&slpm_out_lo_wkup_pdis>;
+ };
+ };
+
+ mc0_a_2_default: mc0_a_2_default {
+ default_mux {
+ function = "mc0";
+ groups = "mc0_a_2";
+ };
+ default_cfg1 {
+ pins = "GPIO22_AA3"; /* FBCLK */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg2 {
+ pins = "GPIO23_AA4"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg3 {
+ pins =
+ "GPIO24_AB2", /* CMD */
+ "GPIO25_Y4", /* DAT0 */
+ "GPIO26_Y2", /* DAT1 */
+ "GPIO27_AA2", /* DAT2 */
+ "GPIO28_AA1"; /* DAT3 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc0_a_2_sleep: mc0_a_2_sleep {
+ sleep_cfg1 {
+ pins =
+ "GPIO22_AA3", /* FBCLK */
+ "GPIO24_AB2", /* CMD */
+ "GPIO25_Y4", /* DAT0 */
+ "GPIO26_Y2", /* DAT1 */
+ "GPIO27_AA2", /* DAT2 */
+ "GPIO28_AA1"; /* DAT3 */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO23_AA4"; /* CLK */
+ ste,config = <&slpm_out_lo_wkup_pdis>;
+ };
+ };
+ };
+
+ sdi1 {
+ /* This is the WLAN SDIO 4 bits wide */
+ mc1_a_1_default: mc1_a_1_default {
+ default_mux {
+ function = "mc1";
+ groups = "mc1_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO208_AH16"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg2 {
+ pins = "GPIO209_AG15"; /* FBCLK */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg3 {
+ pins =
+ "GPIO210_AJ15", /* CMD */
+ "GPIO211_AG14", /* DAT0 */
+ "GPIO212_AF13", /* DAT1 */
+ "GPIO213_AG13", /* DAT2 */
+ "GPIO214_AH15"; /* DAT3 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc1_a_1_sleep: mc1_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO208_AH16"; /* CLK */
+ ste,config = <&slpm_out_lo_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins =
+ "GPIO209_AG15", /* FBCLK */
+ "GPIO210_AJ15", /* CMD */
+ "GPIO211_AG14", /* DAT0 */
+ "GPIO212_AF13", /* DAT1 */
+ "GPIO213_AG13", /* DAT2 */
+ "GPIO214_AH15"; /* DAT3 */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+
+ mc1_a_2_default: mc1_a_2_default {
+ default_mux {
+ function = "mc1";
+ groups = "mc1_a_2";
+ };
+ default_cfg1 {
+ pins = "GPIO208_AH16"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg2 {
+ pins =
+ "GPIO210_AJ15", /* CMD */
+ "GPIO211_AG14", /* DAT0 */
+ "GPIO212_AF13", /* DAT1 */
+ "GPIO213_AG13", /* DAT2 */
+ "GPIO214_AH15"; /* DAT3 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc1_a_2_sleep: mc1_a_2_sleep {
+ sleep_cfg1 {
+ pins = "GPIO208_AH16"; /* CLK */
+ ste,config = <&slpm_out_lo_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins =
+ "GPIO210_AJ15", /* CMD */
+ "GPIO211_AG14", /* DAT0 */
+ "GPIO212_AF13", /* DAT1 */
+ "GPIO213_AG13", /* DAT2 */
+ "GPIO214_AH15"; /* DAT3 */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ sdi2 {
+ /* This is the eMMC 8 bits wide, usually PoP eMMC */
+ mc2_a_1_default: mc2_a_1_default {
+ default_mux {
+ function = "mc2";
+ groups = "mc2_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO128_A5"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg2 {
+ pins = "GPIO130_C8"; /* FBCLK */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg3 {
+ pins =
+ "GPIO129_B4", /* CMD */
+ "GPIO131_A12", /* DAT0 */
+ "GPIO132_C10", /* DAT1 */
+ "GPIO133_B10", /* DAT2 */
+ "GPIO134_B9", /* DAT3 */
+ "GPIO135_A9", /* DAT4 */
+ "GPIO136_C7", /* DAT5 */
+ "GPIO137_A7", /* DAT6 */
+ "GPIO138_C5"; /* DAT7 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc2_a_1_sleep: mc2_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO128_A5"; /* CLK */
+ ste,config = <&out_lo_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins =
+ "GPIO130_C8", /* FBCLK */
+ "GPIO129_B4"; /* CMD */
+ ste,config = <&in_wkup_pdis_en>;
+ };
+ sleep_cfg3 {
+ pins =
+ "GPIO131_A12", /* DAT0 */
+ "GPIO132_C10", /* DAT1 */
+ "GPIO133_B10", /* DAT2 */
+ "GPIO134_B9", /* DAT3 */
+ "GPIO135_A9", /* DAT4 */
+ "GPIO136_C7", /* DAT5 */
+ "GPIO137_A7", /* DAT6 */
+ "GPIO138_C5"; /* DAT7 */
+ ste,config = <&in_wkup_pdis>;
+ };
+ };
+ };
+
+ sdi4 {
+ /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
+ mc4_a_1_default: mc4_a_1_default {
+ default_mux {
+ function = "mc4";
+ groups = "mc4_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO203_AE23"; /* CLK */
+ ste,config = <&out_lo>;
+ };
+ default_cfg2 {
+ pins = "GPIO202_AF25"; /* FBCLK */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg3 {
+ pins =
+ "GPIO201_AF24", /* CMD */
+ "GPIO200_AH26", /* DAT0 */
+ "GPIO199_AH23", /* DAT1 */
+ "GPIO198_AG25", /* DAT2 */
+ "GPIO197_AH24", /* DAT3 */
+ "GPIO207_AJ23", /* DAT4 */
+ "GPIO206_AG24", /* DAT5 */
+ "GPIO205_AG23", /* DAT6 */
+ "GPIO204_AF23"; /* DAT7 */
+ ste,config = <&in_pu>;
+ };
+ };
+
+ mc4_a_1_sleep: mc4_a_1_sleep {
+ sleep_cfg1 {
+ pins = "GPIO203_AE23"; /* CLK */
+ ste,config = <&out_lo_wkup_pdis>;
+ };
+ sleep_cfg2 {
+ pins =
+ "GPIO202_AF25", /* FBCLK */
+ "GPIO201_AF24", /* CMD */
+ "GPIO200_AH26", /* DAT0 */
+ "GPIO199_AH23", /* DAT1 */
+ "GPIO198_AG25", /* DAT2 */
+ "GPIO197_AH24", /* DAT3 */
+ "GPIO207_AJ23", /* DAT4 */
+ "GPIO206_AG24", /* DAT5 */
+ "GPIO205_AG23", /* DAT6 */
+ "GPIO204_AF23"; /* DAT7 */
+ ste,config = <&slpm_in_wkup_pdis>;
+ };
+ };
+ };
+
+ /*
+ * Multi-rate serial ports (MSPs) - MSP3 output is internal and
+ * cannot be muxed onto any pins.
+ */
+ msp0 {
+ msp0txrxtfstck_a_1_default: msp0txrxtfstck_a_1_default {
+ default_msp0_mux {
+ function = "msp0";
+ groups = "msp0txrx_a_1", "msp0tfstck_a_1";
+ };
+ default_msp0_cfg {
+ pins =
+ "GPIO12_AC4", /* TXD */
+ "GPIO15_AC3", /* RXD */
+ "GPIO13_AF3", /* TFS */
+ "GPIO14_AE3"; /* TCK */
+ ste,config = <&in_nopull>;
+ };
+ };
+ };
+
+ msp1 {
+ msp1txrx_a_1_default: msp1txrx_a_1_default {
+ default_mux {
+ function = "msp1";
+ groups = "msp1txrx_a_1", "msp1_a_1";
+ };
+ default_cfg1 {
+ pins = "GPIO33_AF2";
+ ste,config = <&out_lo>;
+ };
+ default_cfg2 {
+ pins =
+ "GPIO34_AE1",
+ "GPIO35_AE2",
+ "GPIO36_AG2";
+ ste,config = <&in_nopull>;
+ };
+ };
+ };
+
+ msp2 {
+ msp2_a_1_default: msp2_a_1_default {
+ /* MSP2 usually used for HDMI audio */
+ default_mux {
+ function = "msp2";
+ groups = "msp2_a_1";
+ };
+ default_cfg1 {
+ pins =
+ "GPIO193_AH27", /* TXD */
+ "GPIO194_AF27", /* TCK */
+ "GPIO195_AG28"; /* TFS */
+ ste,config = <&in_pd>;
+ };
+ default_cfg2 {
+ pins = "GPIO196_AG26"; /* RXD */
+ ste,config = <&out_lo>;
+ };
+ };
+ };
+
+ musb {
+ usb_a_1_default: usb_a_1_default {
+ default_mux {
+ function = "usb";
+ groups = "usb_a_1";
+ };
+ default_cfg1 {
+ pins =
+ "GPIO256_AF28", /* NXT */
+ "GPIO258_AD29", /* XCLK */
+ "GPIO259_AC29", /* DIR */
+ "GPIO260_AD28", /* DAT7 */
+ "GPIO261_AD26", /* DAT6 */
+ "GPIO262_AE26", /* DAT5 */
+ "GPIO263_AG29", /* DAT4 */
+ "GPIO264_AE27", /* DAT3 */
+ "GPIO265_AD27", /* DAT2 */
+ "GPIO266_AC28", /* DAT1 */
+ "GPIO267_AC27"; /* DAT0 */
+ ste,config = <&in_nopull>;
+ };
+ default_cfg2 {
+ pins = "GPIO257_AE29"; /* STP */
+ ste,config = <&out_hi>;
+ };
+ };
+
+ usb_a_1_sleep: usb_a_1_sleep {
+ sleep_cfg1 {
+ pins =
+ "GPIO256_AF28", /* NXT */
+ "GPIO258_AD29", /* XCLK */
+ "GPIO259_AC29"; /* DIR */
+ ste,config = <&slpm_wkup_pdis_en>;
+ };
+ sleep_cfg2 {
+ pins = "GPIO257_AE29"; /* STP */
+ ste,config = <&slpm_out_hi_wkup_pdis>;
+ };
+ sleep_cfg3 {
+ pins =
+ "GPIO260_AD28", /* DAT7 */
+ "GPIO261_AD26", /* DAT6 */
+ "GPIO262_AE26", /* DAT5 */
+ "GPIO263_AG29", /* DAT4 */
+ "GPIO264_AE27", /* DAT3 */
+ "GPIO265_AD27", /* DAT2 */
+ "GPIO266_AC28", /* DAT1 */
+ "GPIO267_AC27"; /* DAT0 */
+ ste,config = <&slpm_in_wkup_pdis_en>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index bda454d..05fd544 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -14,6 +14,22 @@
#address-cells = <1>;
#size-cells = <1>;
+ /* This stablilizes the device enumeration */
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ };
+
chosen {
};
@@ -36,11 +52,6 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x300>;
- /* cpufreq controls */
- operating-points = <998400 0
- 800000 0
- 400000 0
- 200000 0>;
clocks = <&prcmu_clk PRCMU_ARMSS>;
clock-names = "cpu";
clock-latency = <20000>;
@@ -93,7 +104,7 @@
soc {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "stericsson,db8500";
+ compatible = "stericsson,db8500", "simple-bus";
interrupt-parent = <&intc>;
ranges;
@@ -249,7 +260,7 @@
reg = <0x80150000 0x2000>;
};
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xa0412000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
@@ -324,7 +335,7 @@
};
rtc@80154000 {
- compatible = "arm,rtc-pl031", "arm,primecell";
+ compatible = "arm,pl031", "arm,primecell";
reg = <0x80154000 0x1000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -638,7 +649,7 @@
};
};
- i2c@80004000 {
+ i2c0: i2c@80004000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80004000 0x1000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@@ -651,9 +662,11 @@
clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
clock-names = "i2cclk", "apb_pclk";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- i2c@80122000 {
+ i2c1: i2c@80122000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80122000 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -667,9 +680,11 @@
clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
clock-names = "i2cclk", "apb_pclk";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- i2c@80128000 {
+ i2c2: i2c@80128000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80128000 0x1000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -683,9 +698,11 @@
clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
clock-names = "i2cclk", "apb_pclk";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- i2c@80110000 {
+ i2c3: i2c@80110000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x80110000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@@ -699,9 +716,11 @@
clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
clock-names = "i2cclk", "apb_pclk";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- i2c@8012a000 {
+ i2c4: i2c@8012a000 {
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
reg = <0x8012a000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
@@ -715,9 +734,11 @@
clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
clock-names = "i2cclk", "apb_pclk";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@80002000 {
+ ssp0: spi@80002000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80002000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -729,9 +750,11 @@
<&dma 8 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@80003000 {
+ ssp1: spi@80003000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80003000 0x1000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
@@ -743,9 +766,11 @@
<&dma 9 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@8011a000 {
+ spi0: spi@8011a000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x8011a000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -758,9 +783,11 @@
<&dma 0 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@80112000 {
+ spi1: spi@80112000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80112000 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
@@ -773,9 +800,11 @@
<&dma 35 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@80111000 {
+ spi2: spi@80111000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80111000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -788,9 +817,11 @@
<&dma 33 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- spi@80129000 {
+ spi3: spi@80129000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x80129000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
@@ -803,9 +834,11 @@
<&dma 40 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx";
power-domains = <&pm_domains DOMAIN_VAPE>;
+
+ status = "disabled";
};
- ux500_serial0: uart@80120000 {
+ serial0: uart@80120000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80120000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
@@ -820,7 +853,7 @@
status = "disabled";
};
- ux500_serial1: uart@80121000 {
+ serial1: uart@80121000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80121000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -835,7 +868,7 @@
status = "disabled";
};
- ux500_serial2: uart@80007000 {
+ serial2: uart@80007000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80007000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -1064,7 +1097,7 @@
ranges;
status = "disabled";
- dsi0: dsi@a0351000 {
+ dsi0: dsi-controller@a0351000 {
compatible = "ste,mcde-dsi";
reg = <0xa0351000 0x1000>;
clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
@@ -1072,7 +1105,7 @@
#address-cells = <1>;
#size-cells = <0>;
};
- dsi1: dsi@a0352000 {
+ dsi1: dsi-controller@a0352000 {
compatible = "ste,mcde-dsi";
reg = <0xa0352000 0x1000>;
clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
@@ -1080,7 +1113,7 @@
#address-cells = <1>;
#size-cells = <0>;
};
- dsi2: dsi@a0353000 {
+ dsi2: dsi-controller@a0353000 {
compatible = "ste,mcde-dsi";
reg = <0xa0353000 0x1000>;
/* This DSI port only has the Low Power / Energy Save clock */
diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi
index 4946743..3ccb7b5 100644
--- a/arch/arm/boot/dts/ste-href-ab8500.dtsi
+++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi
@@ -9,7 +9,7 @@
soc {
prcmu@80157000 {
ab8500 {
- ab8500-gpio {
+ ab8500-gpiocontroller {
/* Hog a few default settings */
pinctrl-names = "default";
pinctrl-0 = <&gpio2_default_mode>,
diff --git a/arch/arm/boot/dts/ste-href-ab8505.dtsi b/arch/arm/boot/dts/ste-href-ab8505.dtsi
deleted file mode 100644
index 95cf38a..0000000
--- a/arch/arm/boot/dts/ste-href-ab8505.dtsi
+++ /dev/null
@@ -1,234 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2014 Linaro Ltd.
- */
-
-/ {
- soc {
- prcmu@80157000 {
- ab8505 {
- ab8505-gpio {
- /* Hog a few default settings */
- pinctrl-names = "default";
- pinctrl-0 = <&gpio2_default_mode>,
- <&gpio10_default_mode>,
- <&gpio11_default_mode>,
- <&gpio13_default_mode>,
- <&gpio34_default_mode>,
- <&gpio50_default_mode>,
- <&pwm_default_mode>,
- <&adi2_default_mode>,
- <&modsclsda_default_mode>,
- <&resethw_default_mode>,
- <&service_default_mode>;
-
- /*
- * Pins 2, 10, 11, 13, 34 and 50
- * are muxed in as GPIO, and configured as INPUT PULL DOWN
- */
- gpio2 {
- gpio2_default_mode: gpio2_default {
- default_mux {
- function = "gpio";
- groups = "gpio2_a_1";
- };
- default_cfg {
- pins = "GPIO2_R5";
- input-enable;
- bias-pull-down;
- };
- };
- };
- gpio10 {
- gpio10_default_mode: gpio10_default {
- default_mux {
- function = "gpio";
- groups = "gpio10_d_1";
- };
- default_cfg {
- pins = "GPIO10_B16";
- input-enable;
- bias-pull-down;
- };
- };
- };
- gpio11 {
- gpio11_default_mode: gpio11_default {
- default_mux {
- function = "gpio";
- groups = "gpio11_d_1";
- };
- default_cfg {
- pins = "GPIO11_B17";
- input-enable;
- bias-pull-down;
- };
- };
- };
- gpio13 {
- gpio13_default_mode: gpio13_default {
- default_mux {
- function = "gpio";
- groups = "gpio13_d_1";
- };
- default_cfg {
- pins = "GPIO13_D17";
- input-enable;
- bias-disable;
- };
- };
- };
- gpio34 {
- gpio34_default_mode: gpio34_default {
- default_mux {
- function = "gpio";
- groups = "gpio34_a_1";
- };
- default_cfg {
- pins = "GPIO34_H14";
- input-enable;
- bias-pull-down;
- };
- };
- };
- gpio50 {
- gpio50_default_mode: gpio50_default {
- default_mux {
- function = "gpio";
- groups = "gpio50_d_1";
- };
- default_cfg {
- pins = "GPIO50_L4";
- input-enable;
- bias-disable;
- };
- };
- };
- /* This sets up the PWM pin 14 */
- pwm {
- pwm_default_mode: pwm_default {
- default_mux {
- function = "pwmout";
- groups = "pwmout1_d_1";
- };
- default_cfg {
- pins = "GPIO14_C16";
- input-enable;
- bias-pull-down;
- };
- };
- };
- /* This sets up audio interface 2 */
- adi2 {
- adi2_default_mode: adi2_default {
- default_mux {
- function = "adi2";
- groups = "adi2_d_1";
- };
- default_cfg {
- pins = "GPIO17_P2",
- "GPIO18_N3",
- "GPIO19_T1",
- "GPIO20_P3";
- input-enable;
- bias-pull-down;
- };
- };
- };
- /* Modem I2C setup (SCL and SDA pins) */
- modsclsda {
- modsclsda_default_mode: modsclsda_default {
- default_mux {
- function = "modsclsda";
- groups = "modsclsda_d_1";
- };
- default_cfg {
- pins = "GPIO40_J15",
- "GPIO41_J14";
- input-enable;
- bias-pull-down;
- };
- };
- };
- resethw {
- resethw_default_mode: resethw_default {
- default_mux {
- function = "resethw";
- groups = "resethw_d_1";
- };
- default_cfg {
- pins = "GPIO52_D16";
- input-enable;
- bias-pull-down;
- };
- };
- };
- service {
- service_default_mode: service_default {
- default_mux {
- function = "service";
- groups = "service_d_1";
- };
- default_cfg {
- pins = "GPIO53_D15";
- input-enable;
- bias-pull-down;
- };
- };
- };
- /*
- * Clock output pins associated with regulators.
- */
- sysclkreq2 {
- sysclkreq2_default_mode: sysclkreq2_default {
- default_mux {
- function = "sysclkreq";
- groups = "sysclkreq2_d_1";
- };
- default_cfg {
- pins = "GPIO1_N4";
- input-enable;
- bias-disable;
- };
- };
- sysclkreq2_sleep_mode: sysclkreq2_sleep {
- default_mux {
- function = "gpio";
- groups = "gpio1_a_1";
- };
- default_cfg {
- pins = "GPIO1_N4";
- input-enable;
- bias-pull-down;
- };
- };
- };
- sysclkreq4 {
- sysclkreq4_default_mode: sysclkreq4_default {
- default_mux {
- function = "sysclkreq";
- groups = "sysclkreq4_d_1";
- };
- default_cfg {
- pins = "GPIO3_P5";
- input-enable;
- bias-disable;
- };
- };
- sysclkreq4_sleep_mode: sysclkreq4_sleep {
- default_mux {
- function = "gpio";
- groups = "gpio3_a_1";
- };
- default_cfg {
- pins = "GPIO3_P5";
- input-enable;
- bias-pull-down;
- };
- };
- };
- };
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
index 2c382d2..434fa6b 100644
--- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -3,212 +3,11 @@
* Copyright 2013 Linaro Ltd.
*/
-#include "ste-nomadik-pinctrl.dtsi"
+#include "ste-dbx5x0-pinctrl.dtsi"
/ {
soc {
pinctrl {
- /* Settings for all UART default and sleep states */
- uart0 {
- uart0_default_mode: uart0_default {
- default_mux {
- function = "u0";
- groups = "u0_a_1";
- };
- default_cfg1 {
- pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
- ste,config = <&in_pu>;
- };
-
- default_cfg2 {
- pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
- ste,config = <&out_hi>;
- };
- };
-
- uart0_sleep_mode: uart0_sleep {
- sleep_cfg1 {
- pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
- ste,config = <&slpm_in_wkup_pdis>;
- };
-
- sleep_cfg2 {
- pins = "GPIO1_AJ3"; /* RTS */
- ste,config = <&slpm_out_hi_wkup_pdis>;
- };
-
- sleep_cfg3 {
- pins = "GPIO3_AH3"; /* TXD */
- ste,config = <&slpm_out_wkup_pdis>;
- };
- };
- };
-
- uart1 {
- uart1_default_mode: uart1_default {
- default_mux {
- function = "u1";
- groups = "u1rxtx_a_1";
- };
- default_cfg1 {
- pins = "GPIO4_AH6"; /* RXD */
- ste,config = <&in_pu>;
- };
-
- default_cfg2 {
- pins = "GPIO5_AG6"; /* TXD */
- ste,config = <&out_hi>;
- };
- };
-
- uart1_sleep_mode: uart1_sleep {
- sleep_cfg1 {
- pins = "GPIO4_AH6"; /* RXD */
- ste,config = <&slpm_in_wkup_pdis>;
- };
-
- sleep_cfg2 {
- pins = "GPIO5_AG6"; /* TXD */
- ste,config = <&slpm_out_wkup_pdis>;
- };
- };
- };
-
- uart2 {
- uart2_default_mode: uart2_default {
- default_mux {
- function = "u2";
- groups = "u2rxtx_c_1";
- };
- default_cfg1 {
- pins = "GPIO29_W2"; /* RXD */
- ste,config = <&in_pu>;
- };
-
- default_cfg2 {
- pins = "GPIO30_W3"; /* TXD */
- ste,config = <&out_hi>;
- };
- };
-
- uart2_sleep_mode: uart2_sleep {
- sleep_cfg1 {
- pins = "GPIO29_W2"; /* RXD */
- ste,config = <&in_wkup_pdis>;
- };
-
- sleep_cfg2 {
- pins = "GPIO30_W3"; /* TXD */
- ste,config = <&out_wkup_pdis>;
- };
- };
- };
-
- /* Settings for all I2C default and sleep states */
- i2c0 {
- i2c0_default_mode: i2c_default {
- default_mux {
- function = "i2c0";
- groups = "i2c0_a_1";
- };
- default_cfg1 {
- pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
- ste,config = <&in_pu>;
- };
- };
-
- i2c0_sleep_mode: i2c_sleep {
- sleep_cfg1 {
- pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- i2c1 {
- i2c1_default_mode: i2c_default {
- default_mux {
- function = "i2c1";
- groups = "i2c1_b_2";
- };
- default_cfg1 {
- pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
- ste,config = <&in_pu>;
- };
- };
-
- i2c1_sleep_mode: i2c_sleep {
- sleep_cfg1 {
- pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- i2c2 {
- i2c2_default_mode: i2c_default {
- default_mux {
- function = "i2c2";
- groups = "i2c2_b_2";
- };
- default_cfg1 {
- pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
- ste,config = <&in_pu>;
- };
- };
-
- i2c2_sleep_mode: i2c_sleep {
- sleep_cfg1 {
- pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- i2c3 {
- i2c3_default_mode: i2c_default {
- default_mux {
- function = "i2c3";
- groups = "i2c3_c_2";
- };
- default_cfg1 {
- pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
- ste,config = <&in_pu>;
- };
- };
-
- i2c3_sleep_mode: i2c_sleep {
- sleep_cfg1 {
- pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- /*
- * Activating I2C4 will conflict with UART1 about the same pins so do not
- * enable I2C4 and UART1 at the same time.
- */
- i2c4 {
- i2c4_default_mode: i2c_default {
- default_mux {
- function = "i2c4";
- groups = "i2c4_b_1";
- };
- default_cfg1 {
- pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
- ste,config = <&in_pu>;
- };
- };
-
- i2c4_sleep_mode: i2c_sleep {
- sleep_cfg1 {
- pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
/* Settings for all SPI default and sleep states */
spi2 {
spi2_default_mode: spi_default {
@@ -270,335 +69,6 @@
};
};
- /* Settings for all MMC/SD/SDIO default and sleep states */
- sdi0 {
- /* This is the external SD card slot, 4 bits wide */
- sdi0_default_mode: sdi0_default {
- default_mux {
- function = "mc0";
- groups = "mc0_a_1";
- };
- default_cfg1 {
- pins =
- "GPIO18_AC2", /* CMDDIR */
- "GPIO19_AC1", /* DAT0DIR */
- "GPIO20_AB4"; /* DAT2DIR */
- ste,config = <&out_hi>;
- };
- default_cfg2 {
- pins = "GPIO22_AA3"; /* FBCLK */
- ste,config = <&in_nopull>;
- };
- default_cfg3 {
- pins = "GPIO23_AA4"; /* CLK */
- ste,config = <&out_lo>;
- };
- default_cfg4 {
- pins =
- "GPIO24_AB2", /* CMD */
- "GPIO25_Y4", /* DAT0 */
- "GPIO26_Y2", /* DAT1 */
- "GPIO27_AA2", /* DAT2 */
- "GPIO28_AA1"; /* DAT3 */
- ste,config = <&in_pu>;
- };
- };
-
- sdi0_sleep_mode: sdi0_sleep {
- sleep_cfg1 {
- pins =
- "GPIO18_AC2", /* CMDDIR */
- "GPIO19_AC1", /* DAT0DIR */
- "GPIO20_AB4"; /* DAT2DIR */
- ste,config = <&slpm_out_hi_wkup_pdis>;
- };
- sleep_cfg2 {
- pins =
- "GPIO22_AA3", /* FBCLK */
- "GPIO24_AB2", /* CMD */
- "GPIO25_Y4", /* DAT0 */
- "GPIO26_Y2", /* DAT1 */
- "GPIO27_AA2", /* DAT2 */
- "GPIO28_AA1"; /* DAT3 */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- sleep_cfg3 {
- pins = "GPIO23_AA4"; /* CLK */
- ste,config = <&slpm_out_lo_wkup_pdis>;
- };
- };
- };
-
- sdi1 {
- /* This is the WLAN SDIO 4 bits wide */
- sdi1_default_mode: sdi1_default {
- default_mux {
- function = "mc1";
- groups = "mc1_a_1";
- };
- default_cfg1 {
- pins = "GPIO208_AH16"; /* CLK */
- ste,config = <&out_lo>;
- };
- default_cfg2 {
- pins = "GPIO209_AG15"; /* FBCLK */
- ste,config = <&in_nopull>;
- };
- default_cfg3 {
- pins =
- "GPIO210_AJ15", /* CMD */
- "GPIO211_AG14", /* DAT0 */
- "GPIO212_AF13", /* DAT1 */
- "GPIO213_AG13", /* DAT2 */
- "GPIO214_AH15"; /* DAT3 */
- ste,config = <&in_pu>;
- };
- };
-
- sdi1_sleep_mode: sdi1_sleep {
- sleep_cfg1 {
- pins = "GPIO208_AH16"; /* CLK */
- ste,config = <&slpm_out_lo_wkup_pdis>;
- };
- sleep_cfg2 {
- pins =
- "GPIO209_AG15", /* FBCLK */
- "GPIO210_AJ15", /* CMD */
- "GPIO211_AG14", /* DAT0 */
- "GPIO212_AF13", /* DAT1 */
- "GPIO213_AG13", /* DAT2 */
- "GPIO214_AH15"; /* DAT3 */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- sdi2 {
- /* This is the eMMC 8 bits wide, usually PoP eMMC */
- sdi2_default_mode: sdi2_default {
- default_mux {
- function = "mc2";
- groups = "mc2_a_1";
- };
- default_cfg1 {
- pins = "GPIO128_A5"; /* CLK */
- ste,config = <&out_lo>;
- };
- default_cfg2 {
- pins = "GPIO130_C8"; /* FBCLK */
- ste,config = <&in_nopull>;
- };
- default_cfg3 {
- pins =
- "GPIO129_B4", /* CMD */
- "GPIO131_A12", /* DAT0 */
- "GPIO132_C10", /* DAT1 */
- "GPIO133_B10", /* DAT2 */
- "GPIO134_B9", /* DAT3 */
- "GPIO135_A9", /* DAT4 */
- "GPIO136_C7", /* DAT5 */
- "GPIO137_A7", /* DAT6 */
- "GPIO138_C5"; /* DAT7 */
- ste,config = <&in_pu>;
- };
- };
-
- sdi2_sleep_mode: sdi2_sleep {
- sleep_cfg1 {
- pins = "GPIO128_A5"; /* CLK */
- ste,config = <&out_lo_wkup_pdis>;
- };
- sleep_cfg2 {
- pins =
- "GPIO130_C8", /* FBCLK */
- "GPIO129_B4"; /* CMD */
- ste,config = <&in_wkup_pdis_en>;
- };
- sleep_cfg3 {
- pins =
- "GPIO131_A12", /* DAT0 */
- "GPIO132_C10", /* DAT1 */
- "GPIO133_B10", /* DAT2 */
- "GPIO134_B9", /* DAT3 */
- "GPIO135_A9", /* DAT4 */
- "GPIO136_C7", /* DAT5 */
- "GPIO137_A7", /* DAT6 */
- "GPIO138_C5"; /* DAT7 */
- ste,config = <&in_wkup_pdis>;
- };
- };
- };
-
- sdi4 {
- /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
- sdi4_default_mode: sdi4_default {
- default_mux {
- function = "mc4";
- groups = "mc4_a_1";
- };
- default_cfg1 {
- pins = "GPIO203_AE23"; /* CLK */
- ste,config = <&out_lo>;
- };
- default_cfg2 {
- pins = "GPIO202_AF25"; /* FBCLK */
- ste,config = <&in_nopull>;
- };
- default_cfg3 {
- pins =
- "GPIO201_AF24", /* CMD */
- "GPIO200_AH26", /* DAT0 */
- "GPIO199_AH23", /* DAT1 */
- "GPIO198_AG25", /* DAT2 */
- "GPIO197_AH24", /* DAT3 */
- "GPIO207_AJ23", /* DAT4 */
- "GPIO206_AG24", /* DAT5 */
- "GPIO205_AG23", /* DAT6 */
- "GPIO204_AF23"; /* DAT7 */
- ste,config = <&in_pu>;
- };
- };
-
- sdi4_sleep_mode: sdi4_sleep {
- sleep_cfg1 {
- pins = "GPIO203_AE23"; /* CLK */
- ste,config = <&out_lo_wkup_pdis>;
- };
- sleep_cfg2 {
- pins =
- "GPIO202_AF25", /* FBCLK */
- "GPIO201_AF24", /* CMD */
- "GPIO200_AH26", /* DAT0 */
- "GPIO199_AH23", /* DAT1 */
- "GPIO198_AG25", /* DAT2 */
- "GPIO197_AH24", /* DAT3 */
- "GPIO207_AJ23", /* DAT4 */
- "GPIO206_AG24", /* DAT5 */
- "GPIO205_AG23", /* DAT6 */
- "GPIO204_AF23"; /* DAT7 */
- ste,config = <&slpm_in_wkup_pdis>;
- };
- };
- };
-
- /*
- * Multi-rate serial ports (MSPs) - MSP3 output is internal and
- * cannot be muxed onto any pins.
- */
- msp0 {
- msp0_default_mode: msp0_default {
- default_msp0_mux {
- function = "msp0";
- groups = "msp0txrx_a_1", "msp0tfstck_a_1";
- };
- default_msp0_cfg {
- pins =
- "GPIO12_AC4", /* TXD */
- "GPIO15_AC3", /* RXD */
- "GPIO13_AF3", /* TFS */
- "GPIO14_AE3"; /* TCK */
- ste,config = <&in_nopull>;
- };
- };
- };
-
- msp1 {
- msp1_default_mode: msp1_default {
- default_mux {
- function = "msp1";
- groups = "msp1txrx_a_1", "msp1_a_1";
- };
- default_cfg1 {
- pins = "GPIO33_AF2";
- ste,config = <&out_lo>;
- };
- default_cfg2 {
- pins =
- "GPIO34_AE1",
- "GPIO35_AE2",
- "GPIO36_AG2";
- ste,config = <&in_nopull>;
- };
-
- };
- };
-
- msp2 {
- msp2_default_mode: msp2_default {
- /* MSP2 usually used for HDMI audio */
- default_mux {
- function = "msp2";
- groups = "msp2_a_1";
- };
- default_cfg1 {
- pins =
- "GPIO193_AH27", /* TXD */
- "GPIO194_AF27", /* TCK */
- "GPIO195_AG28"; /* TFS */
- ste,config = <&in_pd>;
- };
- default_cfg2 {
- pins = "GPIO196_AG26"; /* RXD */
- ste,config = <&out_lo>;
- };
- };
- };
-
-
- musb {
- musb_default_mode: musb_default {
- default_mux {
- function = "usb";
- groups = "usb_a_1";
- };
- default_cfg1 {
- pins =
- "GPIO256_AF28", /* NXT */
- "GPIO258_AD29", /* XCLK */
- "GPIO259_AC29", /* DIR */
- "GPIO260_AD28", /* DAT7 */
- "GPIO261_AD26", /* DAT6 */
- "GPIO262_AE26", /* DAT5 */
- "GPIO263_AG29", /* DAT4 */
- "GPIO264_AE27", /* DAT3 */
- "GPIO265_AD27", /* DAT2 */
- "GPIO266_AC28", /* DAT1 */
- "GPIO267_AC27"; /* DAT0 */
- ste,config = <&in_nopull>;
- };
- default_cfg2 {
- pins = "GPIO257_AE29"; /* STP */
- ste,config = <&out_hi>;
- };
- };
-
- musb_sleep_mode: musb_sleep {
- sleep_cfg1 {
- pins =
- "GPIO256_AF28", /* NXT */
- "GPIO258_AD29", /* XCLK */
- "GPIO259_AC29"; /* DIR */
- ste,config = <&slpm_wkup_pdis_en>;
- };
- sleep_cfg2 {
- pins = "GPIO257_AE29"; /* STP */
- ste,config = <&slpm_out_hi_wkup_pdis>;
- };
- sleep_cfg3 {
- pins =
- "GPIO260_AD28", /* DAT7 */
- "GPIO261_AD26", /* DAT6 */
- "GPIO262_AE26", /* DAT5 */
- "GPIO263_AG29", /* DAT4 */
- "GPIO264_AE27", /* DAT3 */
- "GPIO265_AD27", /* DAT2 */
- "GPIO266_AC28", /* DAT1 */
- "GPIO267_AC27"; /* DAT0 */
- ste,config = <&slpm_in_wkup_pdis_en>;
- };
- };
- };
-
mcde {
lcd_default_mode: lcd_default {
default_mux1 {
diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi
index e32d0c3..b8fd8f1 100644
--- a/arch/arm/boot/dts/ste-href-stuib.dtsi
+++ b/arch/arm/boot/dts/ste-href-stuib.dtsi
@@ -199,7 +199,7 @@
mcde@a0350000 {
status = "okay";
- dsi@a0351000 {
+ dsi-controller@a0351000 {
panel {
compatible = "samsung,s6d16d0";
reg = <0>;
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi
new file mode 100644
index 0000000..de82b9d
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree for the TVK1281618 R2 UIB
+ */
+
+#include "ste-href-tvk1281618.dtsi"
+
+/ {
+ soc {
+ i2c@80128000 {
+ lsm303dlh@18 {
+ /* Accelerometer */
+ compatible = "st,lsm303dlh-accel";
+ st,drdy-int-pin = <1>;
+ drive-open-drain;
+ reg = <0x18>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_tvk_mode>;
+ /*
+ * These interrupts cannot be used: the other component
+ * ST-Micro L3D4200D gyro that is connected to the same lines
+ * cannot set its DRDY line to open drain, so it cannot be
+ * shared with other peripherals. The should be defined for
+ * the falling edge if they could be wired together.
+ *
+ * interrupts-extended =
+ * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
+ * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
+ */
+ };
+ lsm303dlh@1e {
+ /* Magnetometer */
+ compatible = "st,lsm303dlh-magn";
+ reg = <0x1e>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ /*
+ * These interrupts cannot be used: the other component
+ * ST-Micro L3D4200D gyro that is connected to the same lines
+ * cannot set its DRDY line to open drain, so it cannot be
+ * shared with other peripherals. The should be defined for
+ * the falling edge if they could be wired together.
+ *
+ * interrupts-extended =
+ * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
+ * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
+ */
+ };
+ lis331dl@1c {
+ /* Accelerometer */
+ compatible = "st,lis331dl-accel";
+ st,drdy-int-pin = <1>;
+ reg = <0x1c>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_tvk_mode>;
+ interrupt-parent = <&gpio2>;
+ /* INT2 would need to be open drain */
+ interrupts = <18 IRQ_TYPE_EDGE_RISING>,
+ <19 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+ mcde@a0350000 {
+ status = "okay";
+
+ dsi-controller@a0351000 {
+ panel {
+ compatible = "samsung,s6d16d0";
+ reg = <0>;
+ vdd1-supply = <&ab8500_ldo_aux1_reg>;
+ reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi
new file mode 100644
index 0000000..457bdda
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree for the TVK1281618 R2 UIB
+ */
+
+#include "ste-href-tvk1281618.dtsi"
+
+/ {
+ soc {
+ i2c@80128000 {
+ accelerometer@19 {
+ compatible = "st,lsm303dlhc-accel";
+ st,drdy-int-pin = <1>;
+ reg = <0x19>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <18 IRQ_TYPE_EDGE_RISING>,
+ <19 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_tvk_mode>;
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
+ };
+ magnetometer@1e {
+ compatible = "st,lsm303dlm-magn";
+ st,drdy-int-pin = <1>;
+ reg = <0x1e>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ // This interrupt is not properly working with the driver
+ // interrupt-parent = <&gpio1>;
+ // interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&magn_tvk_mode>;
+ };
+ gyroscope@68 {
+ /* Gyroscope */
+ compatible = "st,l3g4200d-gyro";
+ reg = <0x68>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ };
+ pressure@5c {
+ /* Barometer/pressure sensor */
+ compatible = "st,lps001wp-press";
+ reg = <0x5c>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&db8500_vsmps2_reg>;
+ };
+ };
+
+ mcde@a0350000 {
+ status = "okay";
+
+ dsi-controller@a0351000 {
+ panel {
+ compatible = "sony,acx424akp";
+ reg = <0>;
+ vddi-supply = <&ab8500_ldo_aux1_reg>;
+ reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+ };
+
+ pinctrl {
+ accelerometer {
+ accel_tvk_mode: accel_tvk {
+ /* Accelerometer interrupt lines 1 & 2 */
+ tvk_cfg {
+ pins = "GPIO82_C1", "GPIO83_D3";
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ };
+ magnetometer {
+ magn_tvk_mode: magn_tvk {
+ /* GPIO 32 used for DRDY, pull this down */
+ tvk_cfg {
+ pins = "GPIO32_V2";
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
index 3bafd26..e1dbfae 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -2,7 +2,7 @@
/*
* Copyright 2012 ST-Ericsson AB
*
- * Device Tree for the TVK1281618 UIB
+ * Device Tree for the TVK1281618 family of UIBs
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -81,62 +81,8 @@
};
};
};
- /* Sensors mounted on this board variant */
+ /* Sensors mounted on all board variants */
i2c@80128000 {
- lsm303dlh@18 {
- /* Accelerometer */
- compatible = "st,lsm303dlh-accel";
- st,drdy-int-pin = <1>;
- drive-open-drain;
- reg = <0x18>;
- vdd-supply = <&ab8500_ldo_aux1_reg>;
- vddio-supply = <&db8500_vsmps2_reg>;
- pinctrl-names = "default";
- pinctrl-0 = <&accel_tvk_mode>;
- /*
- * These interrupts cannot be used: the other component
- * ST-Micro L3D4200D gyro that is connected to the same lines
- * cannot set its DRDY line to open drain, so it cannot be
- * shared with other peripherals. The should be defined for
- * the falling edge if they could be wired together.
- *
- * interrupts-extended =
- * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
- * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
- */
- };
- lsm303dlh@1e {
- /* Magnetometer */
- compatible = "st,lsm303dlh-magn";
- reg = <0x1e>;
- vdd-supply = <&ab8500_ldo_aux1_reg>;
- vddio-supply = <&db8500_vsmps2_reg>;
- /*
- * These interrupts cannot be used: the other component
- * ST-Micro L3D4200D gyro that is connected to the same lines
- * cannot set its DRDY line to open drain, so it cannot be
- * shared with other peripherals. The should be defined for
- * the falling edge if they could be wired together.
- *
- * interrupts-extended =
- * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
- * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
- */
- };
- lis331dl@1c {
- /* Accelerometer */
- compatible = "st,lis331dl-accel";
- st,drdy-int-pin = <1>;
- reg = <0x1c>;
- vdd-supply = <&ab8500_ldo_aux1_reg>;
- vddio-supply = <&db8500_vsmps2_reg>;
- pinctrl-names = "default";
- pinctrl-0 = <&accel_tvk_mode>;
- interrupt-parent = <&gpio2>;
- /* INT2 would need to be open drain */
- interrupts = <18 IRQ_TYPE_EDGE_RISING>,
- <19 IRQ_TYPE_EDGE_RISING>;
- };
ak8974@f {
/* Magnetometer */
compatible = "asahi-kasei,ak8974";
@@ -268,18 +214,5 @@
};
};
};
-
- mcde@a0350000 {
- status = "okay";
-
- dsi@a0351000 {
- panel {
- compatible = "samsung,s6d16d0";
- reg = <0>;
- vdd1-supply = <&ab8500_ldo_aux1_reg>;
- reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
- };
- };
- };
};
};
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 4f6acbd..3586b5d 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -4,7 +4,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
-#include "ste-dbx5x0.dtsi"
+#include <dt-bindings/leds/common.h>
#include "ste-href-family-pinctrl.dtsi"
/ {
@@ -16,58 +16,69 @@
soc {
uart@80120000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart0_default_mode>;
- pinctrl-1 = <&uart0_sleep_mode>;
+ pinctrl-0 = <&u0_a_1_default>;
+ pinctrl-1 = <&u0_a_1_sleep>;
status = "okay";
};
/* This UART is unused and thus left disabled */
uart@80121000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart1_default_mode>;
- pinctrl-1 = <&uart1_sleep_mode>;
+ pinctrl-0 = <&u1rxtx_a_1_default>;
+ pinctrl-1 = <&u1rxtx_a_1_sleep>;
};
uart@80007000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart2_default_mode>;
- pinctrl-1 = <&uart2_sleep_mode>;
+ pinctrl-0 = <&u2rxtx_c_1_default>;
+ pinctrl-1 = <&u2rxtx_c_1_sleep>;
status = "okay";
};
i2c@80004000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c0_default_mode>;
- pinctrl-1 = <&i2c0_sleep_mode>;
+ pinctrl-0 = <&i2c0_a_1_default>;
+ pinctrl-1 = <&i2c0_a_1_sleep>;
+ status = "okay";
};
i2c@80122000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c1_default_mode>;
- pinctrl-1 = <&i2c1_sleep_mode>;
+ pinctrl-0 = <&i2c1_b_2_default>;
+ pinctrl-1 = <&i2c1_b_2_sleep>;
+ status = "okay";
};
i2c@80128000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c2_default_mode>;
- pinctrl-1 = <&i2c2_sleep_mode>;
+ pinctrl-0 = <&i2c2_b_2_default>;
+ pinctrl-1 = <&i2c2_b_2_sleep>;
+ status = "okay";
lp5521@33 {
compatible = "national,lp5521";
reg = <0x33>;
label = "lp5521_pri";
clock-mode = /bits/ 8 <2>;
- chan0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ chan@0 {
+ reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
linux,default-trigger = "heartbeat";
};
- chan1 {
+ chan@1 {
+ reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
- chan2 {
+ chan@2 {
+ reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
};
lp5521@34 {
@@ -75,17 +86,25 @@
reg = <0x34>;
label = "lp5521_sec";
clock-mode = /bits/ 8 <2>;
- chan0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ chan@0 {
+ reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
- chan1 {
+ chan@1 {
+ reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
- chan2 {
+ chan@2 {
+ reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
};
bh1780@29 {
@@ -96,8 +115,9 @@
i2c@80110000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c3_default_mode>;
- pinctrl-1 = <&i2c3_sleep_mode>;
+ pinctrl-0 = <&i2c3_c_2_default>;
+ pinctrl-1 = <&i2c3_c_2_sleep>;
+ status = "okay";
};
/* ST6G3244ME level translator for 1.8/2.9 V */
@@ -132,8 +152,8 @@
vmmc-supply = <&ab8500_ldo_aux3_reg>;
vqmmc-supply = <&vmmci>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi0_default_mode>;
- pinctrl-1 = <&sdi0_sleep_mode>;
+ pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>;
+ pinctrl-1 = <&mc0_a_1_sleep>;
status = "okay";
};
@@ -145,8 +165,8 @@
bus-width = <4>;
non-removable;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi1_default_mode>;
- pinctrl-1 = <&sdi1_sleep_mode>;
+ pinctrl-0 = <&mc1_a_1_default>;
+ pinctrl-1 = <&mc1_a_1_sleep>;
status = "okay";
};
@@ -160,8 +180,8 @@
non-removable;
vmmc-supply = <&db8500_vsmps2_reg>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi2_default_mode>;
- pinctrl-1 = <&sdi2_sleep_mode>;
+ pinctrl-0 = <&mc2_a_1_default>;
+ pinctrl-1 = <&mc2_a_1_sleep>;
status = "okay";
};
@@ -175,27 +195,27 @@
non-removable;
vmmc-supply = <&ab8500_ldo_aux2_reg>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi4_default_mode>;
- pinctrl-1 = <&sdi4_sleep_mode>;
+ pinctrl-0 = <&mc4_a_1_default>;
+ pinctrl-1 = <&mc4_a_1_sleep>;
status = "okay";
};
msp0: msp@80123000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp0_default_mode>;
+ pinctrl-0 = <&msp0txrxtfstck_a_1_default>;
status = "okay";
};
msp1: msp@80124000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp1_default_mode>;
+ pinctrl-0 = <&msp1txrx_a_1_default>;
status = "okay";
};
msp2: msp@80117000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp2_default_mode>;
+ pinctrl-0 = <&msp2_a_1_default>;
};
msp3: msp@80125000 {
@@ -204,13 +224,13 @@
prcmu@80157000 {
ab8500 {
- ab8500-gpio {
+ ab8500-gpiocontroller {
};
ab8500_usb {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&musb_default_mode>;
- pinctrl-1 = <&musb_sleep_mode>;
+ pinctrl-0 = <&usb_a_1_default>;
+ pinctrl-1 = <&usb_a_1_sleep>;
};
ab8500-regulators {
@@ -257,6 +277,14 @@
};
};
+ pinctrl {
+ sdi0 {
+ sdi0_default_mode: sdi0_default {
+ /* Some boards set additional settings here */
+ };
+ };
+ };
+
mcde@a0350000 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_default_mode>;
diff --git a/arch/arm/boot/dts/ste-href520-tvk.dts b/arch/arm/boot/dts/ste-href520-tvk.dts
new file mode 100644
index 0000000..f8c0c1e
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href520-tvk.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree for the HREF520 version with the TVK1281618 UIB
+ */
+
+/dts-v1/;
+#include "ste-db8520.dtsi"
+#include "ste-hrefv60plus.dtsi"
+#include "ste-href-tvk1281618-r3.dtsi"
+
+/ {
+ model = "ST-Ericsson HREF520 and TVK1281618 UIB";
+ compatible = "st-ericsson,href520", "st-ericsson,u8500";
+
+ soc {
+ vmmci: regulator-gpio {
+ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ enable-gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts
index b78be5f..8ce6b72 100644
--- a/arch/arm/boot/dts/ste-hrefprev60-stuib.dts
+++ b/arch/arm/boot/dts/ste-hrefprev60-stuib.dts
@@ -4,8 +4,7 @@
*/
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "ste-db8500.dtsi"
#include "ste-hrefprev60.dtsi"
#include "ste-href-stuib.dtsi"
@@ -13,13 +12,6 @@
model = "ST-Ericsson HREF (pre-v60) and ST UIB";
compatible = "st-ericsson,mop500", "st-ericsson,u8500";
- /* This stablilizes the serial port enumeration */
- aliases {
- serial0 = &ux500_serial0;
- serial1 = &ux500_serial1;
- serial2 = &ux500_serial2;
- };
-
soc {
/* Reset line for the BU21013 touchscreen */
i2c@80110000 {
diff --git a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts b/arch/arm/boot/dts/ste-hrefprev60-tvk.dts
index 60eed26..142f547 100644
--- a/arch/arm/boot/dts/ste-hrefprev60-tvk.dts
+++ b/arch/arm/boot/dts/ste-hrefprev60-tvk.dts
@@ -4,17 +4,11 @@
*/
/dts-v1/;
+#include "ste-db8500.dtsi"
#include "ste-hrefprev60.dtsi"
-#include "ste-href-tvk1281618.dtsi"
+#include "ste-href-tvk1281618-r2.dtsi"
/ {
model = "ST-Ericsson HREF (pre-v60) and TVK1281618 UIB";
compatible = "st-ericsson,mop500", "st-ericsson,u8500";
-
- /* This stablilizes the serial port enumeration */
- aliases {
- serial0 = &ux500_serial0;
- serial1 = &ux500_serial1;
- serial2 = &ux500_serial2;
- };
};
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index a036def..115495d 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -5,7 +5,6 @@
* Device Tree for the HREF+ prior to the v60 variant.
*/
-#include "ste-dbx5x0.dtsi"
#include "ste-href-ab8500.dtsi"
#include "ste-href.dtsi"
@@ -58,6 +57,7 @@
*/
pinctrl-names = "default";
pinctrl-0 = <&ssp0_hrefprev60_mode>;
+ status = "okay";
};
// External Micro SD slot
diff --git a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts
index 9be513a..1316886 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts
+++ b/arch/arm/boot/dts/ste-hrefv60plus-stuib.dts
@@ -6,8 +6,7 @@
*/
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "ste-db8500.dtsi"
#include "ste-hrefv60plus.dtsi"
#include "ste-href-stuib.dtsi"
@@ -15,13 +14,6 @@
model = "ST-Ericsson HREF (v60+) and ST UIB";
compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
- /* This stablilizes the serial port enumeration */
- aliases {
- serial0 = &ux500_serial0;
- serial1 = &ux500_serial1;
- serial2 = &ux500_serial2;
- };
-
soc {
/* Reset line for the BU21013 touchscreen */
i2c@80110000 {
diff --git a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts b/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts
index 73ea310..5d4b824 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts
+++ b/arch/arm/boot/dts/ste-hrefv60plus-tvk.dts
@@ -6,17 +6,11 @@
*/
/dts-v1/;
+#include "ste-db8500.dtsi"
#include "ste-hrefv60plus.dtsi"
-#include "ste-href-tvk1281618.dtsi"
+#include "ste-href-tvk1281618-r2.dtsi"
/ {
model = "ST-Ericsson HREF (v60+) and TVK1281618 UIB";
compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
-
- /* This stablilizes the serial port enumeration */
- aliases {
- serial0 = &ux500_serial0;
- serial1 = &ux500_serial1;
- serial2 = &ux500_serial2;
- };
};
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index aece8eb..05b4fbb 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -3,7 +3,6 @@
* Copyright 2012 ST-Ericsson AB
*/
-#include "ste-dbx5x0.dtsi"
#include "ste-href-ab8500.dtsi"
#include "ste-href.dtsi"
diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
index 5673a11..bfdb5d9 100644
--- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
@@ -25,6 +25,11 @@
ste,output = <OUTPUT_LOW>;
};
+ gpio_in_nopull: gpio_input_nopull {
+ ste,gpio = <GPIOMODE_ENABLED>;
+ ste,input = <INPUT_NOPULL>;
+ };
+
gpio_in_pu: gpio_input_pull_up {
ste,gpio = <GPIOMODE_ENABLED>;
ste,input = <INPUT_PULLUP>;
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index e7178a6..42abea3 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -15,7 +15,7 @@
<0x08000000 0x04000000>;
};
- L2: l2-cache {
+ L2: cache-controller {
compatible = "arm,l210-cache";
reg = <0x10210000 0x1000>;
interrupt-parent = <&vica>;
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index efbc446..f6e0d71 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -4,7 +4,7 @@
*/
/dts-v1/;
-#include "ste-dbx5x0.dtsi"
+#include "ste-db9500.dtsi"
#include "ste-href-ab8500.dtsi"
#include "ste-href-family-pinctrl.dtsi"
@@ -12,13 +12,6 @@
model = "Calao Systems Snowball platform with device tree";
compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
- /* This stablilizes the serial port enumeration */
- aliases {
- serial0 = &ux500_serial0;
- serial1 = &ux500_serial1;
- serial2 = &ux500_serial2;
- };
-
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>;
@@ -156,19 +149,19 @@
msp0: msp@80123000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp0_default_mode>;
+ pinctrl-0 = <&msp0txrxtfstck_a_1_default>;
status = "okay";
};
msp1: msp@80124000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp1_default_mode>;
+ pinctrl-0 = <&msp1txrx_a_1_default>;
status = "okay";
};
msp2: msp@80117000 {
pinctrl-names = "default";
- pinctrl-0 = <&msp2_default_mode>;
+ pinctrl-0 = <&msp2_a_1_default>;
};
msp3: msp@80125000 {
@@ -238,8 +231,8 @@
vmmc-supply = <&ab8500_ldo_aux3_reg>;
vqmmc-supply = <&vmmci>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi0_default_mode>;
- pinctrl-1 = <&sdi0_sleep_mode>;
+ pinctrl-0 = <&mc0_a_1_default &sdi0_default_mode>;
+ pinctrl-1 = <&mc0_a_1_sleep>;
/* GPIO218 MMC_CD */
cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>;
@@ -253,8 +246,8 @@
max-frequency = <100000000>;
bus-width = <4>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi1_default_mode>;
- pinctrl-1 = <&sdi1_sleep_mode>;
+ pinctrl-0 = <&mc1_a_1_default>;
+ pinctrl-1 = <&mc1_a_1_sleep>;
status = "okay";
};
@@ -263,7 +256,7 @@
sdi2_per3@80005000 {
arm,primecell-periphid = <0x10480180>;
pinctrl-names = "default";
- pinctrl-0 = <&sdi2_sleep_mode>;
+ pinctrl-0 = <&mc2_a_1_sleep>;
status = "okay";
};
@@ -276,49 +269,52 @@
cap-mmc-highspeed;
vmmc-supply = <&ab8500_ldo_aux2_reg>;
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdi4_default_mode>;
- pinctrl-1 = <&sdi4_sleep_mode>;
+ pinctrl-0 = <&mc4_a_1_default>;
+ pinctrl-1 = <&mc4_a_1_sleep>;
status = "okay";
};
uart@80120000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart0_default_mode>;
- pinctrl-1 = <&uart0_sleep_mode>;
+ pinctrl-0 = <&u0_a_1_default>;
+ pinctrl-1 = <&u0_a_1_sleep>;
status = "okay";
};
/* This UART is unused and thus left disabled */
uart@80121000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart1_default_mode>;
- pinctrl-1 = <&uart1_sleep_mode>;
+ pinctrl-0 = <&u1rxtx_a_1_default>;
+ pinctrl-1 = <&u1rxtx_a_1_sleep>;
};
uart@80007000 {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&uart2_default_mode>;
- pinctrl-1 = <&uart2_sleep_mode>;
+ pinctrl-0 = <&u2rxtx_c_1_default>;
+ pinctrl-1 = <&u2rxtx_c_1_sleep>;
status = "okay";
};
i2c@80004000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c0_default_mode>;
- pinctrl-1 = <&i2c0_sleep_mode>;
+ pinctrl-0 = <&i2c0_a_1_default>;
+ pinctrl-1 = <&i2c0_a_1_sleep>;
+ status = "okay";
};
i2c@80122000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c1_default_mode>;
- pinctrl-1 = <&i2c1_sleep_mode>;
+ pinctrl-0 = <&i2c1_b_2_default>;
+ pinctrl-1 = <&i2c1_b_2_sleep>;
+ status = "okay";
};
i2c@80128000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c2_default_mode>;
- pinctrl-1 = <&i2c2_sleep_mode>;
+ pinctrl-0 = <&i2c2_b_2_default>;
+ pinctrl-1 = <&i2c2_b_2_sleep>;
+ status = "okay";
lsm303dlh@18 {
/* Accelerometer */
compatible = "st,lsm303dlh-accel";
@@ -367,22 +363,20 @@
i2c@80110000 {
pinctrl-names = "default","sleep";
- pinctrl-0 = <&i2c3_default_mode>;
- pinctrl-1 = <&i2c3_sleep_mode>;
+ pinctrl-0 = <&i2c3_c_2_default>;
+ pinctrl-1 = <&i2c3_c_2_sleep>;
+ status = "okay";
};
spi@80002000 {
pinctrl-names = "default";
pinctrl-0 = <&ssp0_snowball_mode>;
+ status = "okay";
};
prcmu@80157000 {
- cpufreq {
- status = "okay";
- };
-
ab8500 {
- ab8500-gpio {
+ ab8500-gpiocontroller {
/*
* AB8500 GPIOs are numbered starting from 1, so the first
* index 0 is what in the datasheet is called "GPIO1", and
@@ -406,8 +400,8 @@
ab8500_usb {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&musb_default_mode>;
- pinctrl-1 = <&musb_sleep_mode>;
+ pinctrl-0 = <&usb_a_1_default>;
+ pinctrl-1 = <&usb_a_1_sleep>;
};
ext_regulators: ab8500-ext-regulators {
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts
new file mode 100644
index 0000000..aed1f2d
--- /dev/null
+++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts
@@ -0,0 +1,657 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "ste-db8500.dtsi"
+#include "ste-ab8505.dtsi"
+#include "ste-dbx5x0-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/*
+ * Note: This device tree cannot be booted directly with the Samsung bootloader.
+ * You need an intermediate, device-tree compatible bootloader
+ * that locks the L2 cache. Otherwise the kernel will crash after decompression.
+ *
+ * There is a port of (mainline) U-Boot, see
+ * https://wiki.postmarketos.org/wiki/ST-Ericsson_NovaThor_U8500#U-Boot
+ */
+/ {
+ model = "Samsung Galaxy S III mini (GT-I8190)";
+ compatible = "samsung,golden", "st-ericsson,u8500";
+
+ chosen {
+ stdout-path = &serial2;
+ };
+
+ i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio2 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_gpio_0_default>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchkey@20 {
+ compatible = "coreriver,tc360-touchkey";
+ reg = <0x20>;
+ vdd-supply = <&ab8500_ldo_aux4_reg>;
+ vcc-supply = <&ab8500_ldo_aux6_reg>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchkey_default>;
+ linux,keycodes = <KEY_MENU KEY_BACK>;
+ };
+ };
+
+ i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_gpio_1_default>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ magnetometer@c {
+ compatible = "alps,hscdtd008a";
+ reg = <0x0c>;
+
+ avdd-supply = <&ab8500_ldo_aux1_reg>;
+ dvdd-supply = <&ab8500_ldo_aux8_reg>;
+ };
+ };
+
+ soc {
+ /* External Micro SD card slot */
+ sdi0_per1@80126000 {
+ status = "okay";
+
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <100000000>;
+ bus-width = <4>;
+
+ non-removable;
+ /*
+ * Unfortunately, there is no way to enable the UHS
+ * modes due to a limitation of the SD level translator:
+ * It will either translate to 2.9V or disconnect the
+ * DATA lines, so switching to 1.8V signal voltage fails.
+ */
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ st,sig-pin-fbclk;
+ full-pwr-cycle;
+
+ vmmc-supply = <&ab8500_ldo_aux3_reg>;
+ vqmmc-supply = <&sd_level_translator>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc0_a_2_default>;
+ pinctrl-1 = <&mc0_a_2_sleep>;
+ };
+
+ /* WLAN SDIO */
+ sdi1_per2@80118000 {
+ status = "okay";
+
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <50000000>;
+ bus-width = <4>;
+
+ non-removable;
+ cap-sd-highspeed;
+
+ vmmc-supply = <&wl_reg_on>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc1_a_2_default>;
+ pinctrl-1 = <&mc1_a_2_sleep>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+
+ /* GPIO216 (WLAN_HOST_WAKE) */
+ interrupt-parent = <&gpio6>;
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "host-wake";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_default>;
+ };
+ };
+
+ /* eMMC */
+ sdi2_per3@80005000 {
+ status = "okay";
+
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <100000000>;
+ bus-width = <8>;
+
+ non-removable;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+
+ vmmc-supply = <&vmem_3v3>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc2_a_1_default>;
+ pinctrl-1 = <&mc2_a_1_sleep>;
+ };
+
+ /* BT UART */
+ uart@80120000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u0_a_1_default>;
+ pinctrl-1 = <&u0_a_1_sleep>;
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ /* GPIO222 (BT_VREG_ON) */
+ shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
+ /* GPIO199 (BT_WAKE) */
+ device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ /* GPIO97 (BT_HOST_WAKE) */
+ host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bluetooth_default>;
+ };
+ };
+
+ /* GPF UART */
+ uart@80121000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>;
+ pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>;
+ };
+
+ /* Debugging console UART */
+ uart@80007000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u2rxtx_c_1_default>;
+ pinctrl-1 = <&u2rxtx_c_1_sleep>;
+ };
+
+ i2c@80004000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c0_a_1_default>;
+ pinctrl-1 = <&i2c0_a_1_sleep>;
+
+ proximity@44 {
+ compatible = "sharp,gp2ap002s00f";
+ reg = <0x44>;
+
+ /* GPIO146 (PS_INT) */
+ interrupt-parent = <&gpio4>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vio-supply = <&ab8500_ldo_aux8_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&proximity_default>;
+
+ sharp,proximity-far-hysteresis = <0x40>;
+ sharp,proximity-close-hysteresis = <0x0f>;
+ };
+ };
+
+ i2c@80128000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_b_2_default>;
+ pinctrl-1 = <&i2c2_b_2_sleep>;
+
+ imu@68 {
+ compatible = "invensense,mpu6050";
+ reg = <0x68>;
+
+ /* GPIO206 (ACC_INT) */
+ interrupt-parent = <&gpio6>;
+ interrupts = <14 IRQ_TYPE_EDGE_RISING>;
+
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&ab8500_ldo_aux8_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&imu_default>;
+ };
+ };
+
+ i2c@80110000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c3_c_2_default>;
+ pinctrl-1 = <&i2c3_c_2_sleep>;
+
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+
+ /* GPIO218 (TSP_INT_1V8) */
+ interrupt-parent = <&gpio6>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tsp_default>;
+ };
+ };
+
+ prcmu@80157000 {
+ ab8505 {
+ ab8500_usb {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usb_a_1_default>;
+ pinctrl-1 = <&usb_a_1_sleep>;
+ };
+
+ ab8505-regulators {
+ ab8500_ldo_aux1 {
+ regulator-name = "sensor_3v";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ab8500_ldo_aux2 {
+ regulator-name = "vreg_tsp_a3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on; /* FIXME */
+ };
+
+ ab8500_ldo_aux3 {
+ regulator-name = "vdd_tf_2v91";
+ };
+
+ ab8500_ldo_aux4 {
+ regulator-name = "key_led_3.3v";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux5 {
+ regulator-name = "vreg_tsp_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on; /* FIXME */
+ };
+
+ ab8500_ldo_aux6 {
+ regulator-name = "touch_key_2.2v";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ ab8500_ldo_aux8 {
+ regulator-name = "sensor_1v8";
+ };
+ };
+ };
+ };
+
+ mcde@a0350000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dsi_default_mode>;
+
+ dsi-controller@a0351000 {
+ panel@0 {
+ compatible = "samsung,s6e63m0";
+ reg = <0>;
+ max-brightness = <15>;
+ vdd3-supply = <&panel_reg_3v0>;
+ vci-supply = <&panel_reg_1v8>;
+ reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ /* ESD (electrostatic discharge) detection interrupt */
+ interrupt-parent = <&gpio2>;
+ interrupts = <18 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "esd";
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_default_mode>;
+ };
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_default>;
+
+ label = "GPIO Buttons";
+
+ volume-up {
+ label = "Volume Up";
+ /* GPIO67 (VOL_UP) */
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ /* GPIO92 (VOL_DOWN) */
+ gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ home {
+ label = "Home";
+ /* GPIO91 (HOME_KEY) */
+ gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOMEPAGE>;
+ };
+ };
+
+ vibrator {
+ compatible = "gpio-vibrator";
+ /* GPIO195 (MOT_EN) */
+ enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_default>;
+ };
+
+ /* External LDO for eMMC */
+ vmem_3v3: regulator-vmem {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vmem_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ startup-delay-us = <200>;
+
+ /* GPIO223 (MEM_LDO_EN) */
+ gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mem_ldo_default>;
+ };
+
+ /* TI TXS0206-29 level translator for 2.9 V */
+ sd_level_translator: regulator-sd-level-translator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "sd-level-translator";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+
+ startup-delay-us = <200>;
+
+ /* GPIO87 (TXS0206-29_EN) */
+ gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_level_translator_default>;
+ };
+
+ /*
+ * WL_REG_ON takes WLAN out of reset and enables the internal regulators.
+ * The voltage specified here is only used to determine the OCR mask,
+ * the BCM chip is actually connected directly to VBAT.
+ */
+ wl_reg_on: regulator-wl-reg-on {
+ compatible = "regulator-fixed";
+
+ regulator-name = "wl-reg-on";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ startup-delay-us = <100000>;
+
+ /* GPIO215 (WLAN_EN) */
+ gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en_default>;
+ };
+
+ /* MIC5366 GPIO-controlled regulator */
+ panel_reg_1v8: regulator-panel-1v8 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "panel-fixed-supply";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ /* GPIO219 */
+ gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>;
+
+ startup-delay-us = <200>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_reg_default_mode>;
+ };
+
+ /* MIC5366 GPIO-controlled regulator */
+ panel_reg_3v0: regulator-panel-3v0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "panel-fixed-supply";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ /* GPIO219 */
+ gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>;
+
+ startup-delay-us = <200>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_reg_default_mode>;
+ };
+};
+
+&pinctrl {
+ gpio-keys {
+ gpio_keys_default: gpio_keys_default {
+ golden_cfg1 {
+ pins = "GPIO67", /* VOL_UP */
+ "GPIO91", /* HOME_KEY */
+ "GPIO92"; /* VOL_DOWN */
+ ste,config = <&gpio_in_pu>;
+ };
+ };
+ };
+
+ i2c-gpio-0 {
+ i2c_gpio_0_default: i2c_gpio_0 {
+ golden_cfg1 {
+ pins = "GPIO77", /* TOUCHKEY_SCL */
+ "GPIO78"; /* TOUCHKEY_SDA */
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+
+ i2c-gpio-1 {
+ i2c_gpio_1_default: i2c_gpio_1 {
+ golden_cfg1 {
+ pins = "GPIO151", /* COMP_SCL */
+ "GPIO152"; /* COMP_SDA */
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+
+ touchkey {
+ touchkey_default: touchkey_default {
+ golden_cfg1 {
+ pins = "GPIO79"; /* TOUCHKEY_INT */
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+
+ sdi0 {
+ sd_level_translator_default: sd_level_translator_default {
+ golden_cfg1 {
+ pins = "GPIO87_B3"; /* TXS0206-29_EN */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+
+ sdi2 {
+ mem_ldo_default: mem_ldo_default {
+ golden_cfg1 {
+ pins = "GPIO223_AH9"; /* MEM_LDO_EN */
+ ste,config = <&gpio_out_hi>;
+ };
+ };
+ };
+
+ mcde {
+ dsi_default_mode: dsi_default {
+ default_mux1 {
+ /* Mux in VSI0 used for DSI TE */
+ function = "lcd";
+ groups =
+ "lcdvsi0_a_1"; /* VSI0 for LCD */
+ };
+ default_cfg1 {
+ pins =
+ "GPIO68_E1"; /* VSI0 */
+ ste,config = <&in_nopull>;
+ };
+ };
+ };
+
+ display {
+ display_default_mode: display_default {
+ golden_cfg1 {
+ pins = "GPIO139_C9"; /* MIPI_DSI0_RESET_N */
+ ste,config = <&gpio_out_lo>;
+ };
+ golden_cfg2 {
+ pins = "GPIO82_C1"; /* LDI_ESD_DET */
+ ste,config = <&gpio_in_pu>;
+ };
+ };
+ panel_reg_default_mode: panel_reg_default {
+ golden_cfg1 {
+ pins = "GPIO219_AG10"; /* LCD_PWR_EN */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+
+ proximity {
+ proximity_default: proximity_default {
+ golden_cfg1 {
+ pins = "GPIO146_D13"; /* PS_INT */
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+
+ imu {
+ imu_default: imu_default {
+ golden_cfg1 {
+ pins = "GPIO206_AG24"; /* ACC_INT */
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ };
+
+ tsp {
+ tsp_default: tsp_default {
+ golden_cfg1 {
+ pins = "GPIO218_AH11"; /* TSP_INT_1V8 */
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+
+ wlan {
+ wlan_default: wlan_default {
+ golden_cfg1 {
+ pins = "GPIO216_AG12"; /* WLAN_HOST_WAKE */
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+
+ wlan_en_default: wlan_en_default {
+ golden_cfg1 {
+ pins = "GPIO215_AH13"; /* WLAN_EN */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+
+ bluetooth {
+ bluetooth_default: bluetooth_default {
+ golden_cfg1 {
+ pins = "GPIO199_AH23", /* BT_WAKE */
+ "GPIO222_AJ9"; /* BT_VREG_ON */
+ ste,config = <&gpio_out_lo>;
+ };
+ golden_cfg2 {
+ pins = "GPIO97_D9"; /* BT_HOST_WAKE */
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+
+ vibrator {
+ vibrator_default: vibrator_default {
+ golden_cfg1 {
+ pins = "GPIO195_AG28"; /* MOT_EN */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+};
+
+&ab8505_gpio {
+ /* Hog a few default settings */
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_default>;
+
+ gpio {
+ gpio_default: gpio_default {
+ golden_mux {
+ /* Change unused pins to GPIO mode */
+ function = "gpio";
+ groups = "gpio3_a_1", /* default: SysClkReq4 */
+ "gpio14_a_1"; /* default: PWMOut1 */
+ };
+ golden_cfg1 {
+ pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4";
+ bias-disable;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts
new file mode 100644
index 0000000..446d93c
--- /dev/null
+++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts
@@ -0,0 +1,609 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Devicetree for the Samsung XCover 2 GT-S7710 also known as Skomer.
+ */
+
+/dts-v1/;
+#include "ste-db8500.dtsi"
+#include "ste-ab8505.dtsi"
+#include "ste-dbx5x0-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "Samsung XCover 2 (GT-S7710)";
+ compatible = "samsung,skomer", "st-ericsson,u8500";
+
+ chosen {
+ stdout-path = &serial2;
+ };
+
+ /* TI TXS0206 level translator for 2.9 V */
+ sd_level_translator: regulator-gpio {
+ compatible = "regulator-fixed";
+
+ /* GPIO87 EN */
+ gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ regulator-name = "sd-level-translator";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-type = "voltage";
+
+ startup-delay-us = <200>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_level_translator_default>;
+ };
+
+ /* External LDO MIC5366-3.3YMT for eMMC */
+ ldo_3v3_reg: regulator-gpio-ldo-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "en-3v3-fixed-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio6 31 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <5000>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_ldo_en_default_mode>;
+ };
+
+ wlan_en: regulator-gpio-wlan-en {
+ compatible = "regulator-fixed";
+ regulator-name = "wl-reg-on";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ startup-delay-us = <200000>;
+ /* GPIO215 WLAN_EN */
+ gpio = <&gpio6 23 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_en_default_mode>;
+ };
+
+ vibrator {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_default>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_default_mode>;
+
+ button-home {
+ linux,code = <KEY_HOME>;
+ label = "HOME";
+ /* GPIO91 */
+ gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
+ };
+ button-volup {
+ linux,code = <KEY_VOLUMEUP>;
+ label = "VOL+";
+ /* GPIO67 */
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ };
+ button-voldown {
+ linux,code = <KEY_VOLUMEDOWN>;
+ label = "VOL-";
+ /* GPIO92 */
+ gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+ };
+ button-menu {
+ linux,code = <KEY_MENU>;
+ label = "MENU";
+ /* GPIO204 */
+ gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
+ };
+ button-back {
+ linux,code = <KEY_BACK>;
+ label = "BACK";
+ /* GPIO205 */
+ gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ ktd253: backlight {
+ compatible = "kinetic,ktd253";
+ /* GPIO 69 */
+ enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ /* Default to 13/32 brightness */
+ default-brightness = <13>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_backlight_default_mode>;
+ };
+
+ i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio4 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio4 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_gpio_0_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* TODO: this should be used by the NCP6914 Camera power management unit */
+ };
+
+ i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_gpio_1_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ magnetometer@c {
+ compatible = "alps,hscdtd008a";
+ reg = <0x0c>;
+ avdd-supply = <&ab8500_ldo_aux1_reg>;
+ dvdd-supply = <&ab8500_ldo_aux8_reg>;
+ };
+ };
+
+ soc {
+ // External Micro SD slot
+ sdi0_per1@80126000 {
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <100000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ /* All direction control is used */
+ st,sig-pin-fbclk;
+ full-pwr-cycle;
+ vmmc-supply = <&ab8500_ldo_aux3_reg>;
+ vqmmc-supply = <&sd_level_translator>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc0_a_1_default>;
+ pinctrl-1 = <&mc0_a_1_sleep>;
+ status = "okay";
+ };
+
+ // WLAN SDIO channel
+ sdi1_per2@80118000 {
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ non-removable;
+ cap-sd-highspeed;
+ vmmc-supply = <&wlan_en>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc1_a_2_default>;
+ pinctrl-1 = <&mc1_a_2_sleep>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ /* GPIO216 WL_HOST_WAKE */
+ interrupt-parent = <&gpio6>;
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "host-wake";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_default_mode>;
+ };
+ };
+
+ // eMMC
+ sdi2_per3@80005000 {
+ arm,primecell-periphid = <0x10480180>;
+ max-frequency = <100000000>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ vmmc-supply = <&ldo_3v3_reg>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mc2_a_1_default>;
+ pinctrl-1 = <&mc2_a_1_sleep>;
+
+ status = "okay";
+ };
+
+ /* GBF (Bluetooth) UART */
+ uart@80120000 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u0_a_1_default>;
+ pinctrl-1 = <&u0_a_1_sleep>;
+ status = "okay";
+
+ /* FIXME: not quite working yet, probably needs regulators */
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bluetooth_default_mode>;
+ };
+ };
+
+ /* GPF UART */
+ uart@80121000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>;
+ pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>;
+ };
+
+ /* Debugging console UART connected to AB8505 USB */
+ uart@80007000 {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&u2rxtx_c_1_default>;
+ pinctrl-1 = <&u2rxtx_c_1_sleep>;
+ };
+
+ prcmu@80157000 {
+ ab8505 {
+ ab8500_usb {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usb_a_1_default>;
+ pinctrl-1 = <&usb_a_1_sleep>;
+ };
+
+ ab8505-regulators {
+ ab8500_ldo_aux1 {
+ /* Used for VDD for sensors */
+ regulator-name = "AUX1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux2 {
+ /* Supplies the Cypress TMA140 touchscreen only with 3.0V */
+ regulator-name = "AUX2";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ab8500_ldo_aux3 {
+ /* Used for voltage for external MMC/SD card */
+ regulator-name = "AUX3";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ab8500_ldo_aux4 {
+ regulator-name = "AUX4";
+ /* Hammer to 3.0V for the display */
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ab8500_ldo_aux5 {
+ regulator-name = "AUX5";
+ /* Intended for 1V8 for touchscreen but actually left unused */
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <2790000>;
+ };
+
+ ab8500_ldo_aux6 {
+ regulator-name = "AUX6";
+ /* Hammer to 1.8V for the display */
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ab8500_ldo_aux8 {
+ /* Mostly VIO for sensors */
+ regulator-name = "AUX8";
+ };
+ };
+ };
+ };
+
+ /* I2C0 */
+ i2c@80004000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c0_a_1_default>;
+ pinctrl-1 = <&i2c0_a_1_sleep>;
+
+ proximity@44 {
+ compatible = "sharp,gp2ap002s00f";
+ clock-frequency = <400000>;
+ reg = <0x44>;
+
+ interrupt-parent = <&gpio4>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vio-supply = <&ab8500_ldo_aux8_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gp2ap002_skomer_default>;
+ sharp,proximity-far-hysteresis = /bits/ 8 <0x2f>;
+ sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>;
+ };
+ };
+
+
+ /* I2C2 */
+ i2c@80128000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_b_2_default>;
+ pinctrl-1 = <&i2c2_b_2_sleep>;
+
+ accel@18 {
+ compatible = "bosch,bma254";
+ clock-frequency = <400000>;
+ reg = <0x18>;
+
+ /* GPIO224 used as "smart alert" interrupt */
+ interrupt-parent = <&gpio7>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+
+ mount-matrix = "0", "-1", "0",
+ "1", "0", "0",
+ "0", "0", "1";
+ vdd-supply = <&ab8500_ldo_aux1_reg>;
+ vddio-supply = <&ab8500_ldo_aux8_reg>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bma254_skomer_default>;
+ };
+ };
+
+ /* I2C3 */
+ i2c@80110000 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c3_c_2_default>;
+ pinctrl-1 = <&i2c3_c_2_sleep>;
+
+ /* Cypress CY8CTMA140 touchscreen */
+ touchscreen@20 {
+ compatible = "cypress,cy8ctma140";
+ clock-frequency = <400000>;
+ reg = <0x20>;
+
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ touchscreen-max-pressure = <255>;
+
+ /* GPIO218 for IRQ */
+ interrupt-parent = <&gpio6>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+
+ /* VDD is "digital supply" nominally 1.71-3.6V */
+ vdd-supply = <&ab8500_ldo_aux2_reg>;
+ /* VCPIN is "analog supply", 2.7-3.6 V */
+ vcpin-supply = <&ab8500_ldo_aux2_reg>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tma140_skomer_default>;
+ };
+ };
+
+ mcde@a0350000 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dsi_default_mode>;
+
+ dsi-controller@a0351000 {
+ panel {
+ /* NT35510-based Hydis HVA40WV1 */
+ compatible = "hydis,hva40wv1", "novatek,nt35510";
+ reg = <0>;
+ /* v_lcd_3v0 2.3-4.8V */
+ vdd-supply = <&ab8500_ldo_aux4_reg>;
+ /* v_lcd_1v8 1.65-3.3V */
+ vddi-supply = <&ab8500_ldo_aux6_reg>;
+ /* GPIO 139 */
+ reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_default_mode>;
+ backlight = <&ktd253>;
+ };
+ };
+ };
+ };
+};
+
+&pinctrl {
+ /*
+ * This extends the MC0 default config to include DAT32DIR
+ * which is used by this machine. If we don't do this the
+ * SD card does not work.
+ */
+ sdi0 {
+ mc0_a_1_default {
+ default_mux {
+ function = "mc0";
+ /* This machine uses the DAT31 pin */
+ groups = "mc0_a_1", "mc0dat31dir_a_1";
+ };
+ default_cfg5 {
+ pins = "GPIO21_AB3"; /* DAT31DIR */
+ ste,config = <&out_hi>;
+ };
+ };
+ };
+
+ mcde {
+ dsi_default_mode: dsi_default {
+ default_mux1 {
+ /* Mux in VSI0 used for DSI TE */
+ function = "lcd";
+ groups = "lcdvsi0_a_1"; /* VSI0 for LCD */
+ };
+ default_cfg1 {
+ pins = "GPIO68_E1"; /* VSI0 */
+ ste,config = <&in_nopull>;
+ };
+ };
+ };
+
+ /* Two GPIO lines used by the display */
+ display {
+ display_default_mode: display_default {
+ skomer_cfg1 {
+ /*
+ * OLED DETECT or check_pba, this appears to be high
+ * on "PBA" which I guess is "prototype board A".
+ */
+ pins = "GPIO93_B7";
+ ste,config = <&gpio_in_nopull>;
+ };
+ skomer_cfg2 {
+ pins = "GPIO139_C9";
+ /*
+ * MIPI_DSI0_RESET_N resets the display, leave high
+ * (de-asserted) so we only assert reset explicitly
+ * from the display driver.
+ */
+ ste,config = <&gpio_out_hi>;
+ };
+ };
+ };
+ backlight {
+ gpio_backlight_default_mode: backlight_default {
+ skomer_cfg1 {
+ pins = "GPIO69_E2"; /* LCD_BL_CTRL */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+ /* GPIO that enables the 2.9V SD card level translator */
+ sd-level-translator {
+ sd_level_translator_default: sd_level_translator_default {
+ /* level shifter on GPIO87 */
+ skomer_cfg1 {
+ pins = "GPIO87_B3";
+ ste,config = <&gpio_out_hi>;
+ };
+ };
+ };
+ /* GPIO that enables the LDO regulator for the eMMC */
+ emmc-ldo {
+ emmc_ldo_en_default_mode: emmc_ldo_default {
+ /* LDO enable on GPIO223 */
+ skomer_cfg1 {
+ pins = "GPIO223_AH9";
+ ste,config = <&gpio_out_hi>;
+ };
+ };
+ };
+ /* GPIO keys */
+ gpio-keys {
+ gpio_keys_default_mode: gpio_keys_default {
+ skomer_cfg1 {
+ pins = "GPIO67_G2", /* VOL UP */
+ "GPIO91_B6", /* HOME */
+ "GPIO92_D6", /* VOL DOWN */
+ "GPIO204_AF23", /* MENU */
+ "GPIO205_AG23"; /* BACK */
+ ste,config = <&gpio_in_pu>;
+ };
+ };
+ };
+ /* Interrupt line for BMA254 */
+ bma254 {
+ bma254_skomer_default: bma254_skomer {
+ skomer_cfg1 {
+ pins = "GPIO224_AG9";
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ };
+ /* Interrupt line for light/proximity sensor GP2AP002 */
+ gp2ap002 {
+ gp2ap002_skomer_default: gp2ap002_skomer {
+ skomer_cfg1 {
+ pins = "GPIO146_D13";
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+ /* GPIO-based I2C bus for NCP6914 */
+ i2c-gpio-0 {
+ i2c_gpio_0_default: i2c_gpio_0 {
+ skomer_cfg1 {
+ pins = "GPIO143_D12", "GPIO144_B13";
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+ /* GPIO-based I2C bus for ALPS HSCD compass */
+ i2c-gpio-1 {
+ i2c_gpio_1_default: i2c_gpio_1 {
+ skomer_cfg1 {
+ pins = "GPIO151_B17", "GPIO152_D16";
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+ wlan {
+ wlan_default_mode: wlan_default {
+ skomer_cfg1 {
+ pins = "GPIO216_AG12";
+ ste,config = <&gpio_in_pd>;
+ };
+ };
+ wlan_en_default_mode: wlan_en_default {
+ skomer_cfg2 {
+ pins = "GPIO215_AH13";
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+ bluetooth {
+ bluetooth_default_mode: bluetooth_default {
+ skomer_cfg1 {
+ pins = "GPIO199_AH23", "GPIO222_AJ9";
+ ste,config = <&gpio_out_lo>;
+ };
+ skomer_cfg2 {
+ pins = "GPIO97_D9";
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+ vibrator {
+ vibrator_default: vibrator_default {
+ skomer_cfg1 {
+ pins = "GPIO195_AG28"; /* MOT_EN */
+ ste,config = <&gpio_out_lo>;
+ };
+ };
+ };
+ /* Interrupt line for the Cypress TMA140 touchscreen */
+ touchscreen {
+ tma140_skomer_default: tma140_skomer {
+ skomer_cfg1 {
+ pins = "GPIO218_AH11";
+ ste,config = <&gpio_in_nopull>;
+ };
+ };
+ };
+};
+
+&ab8505_gpio {
+ /* Hog a few default settings */
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_default>;
+
+ gpio {
+ gpio_default: gpio_default {
+ skomer_mux {
+ /* Change unused pins to GPIO mode */
+ function = "gpio";
+ groups = "gpio3_a_1", /* default: SysClkReq4 */
+ "gpio14_a_1"; /* default: PWMOut1 */
+ };
+ skomer_cfg1 {
+ pins = "GPIO11_B17", "GPIO13_D17", "GPIO50_L4";
+ bias-disable;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 7c36c37..23a1746 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -767,20 +767,6 @@
<&clk_s_c0_flexgen CLK_ETH_PHY>;
};
- rng10: rng@8a89000 {
- compatible = "st,rng";
- reg = <0x08a89000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
- };
-
- rng11: rng@8a8a000 {
- compatible = "st,rng";
- reg = <0x08a8a000 0x1000>;
- clocks = <&clk_sysin>;
- status = "okay";
- };
-
mailbox0: mailbox@8f00000 {
compatible = "st,stih407-mailbox";
reg = <0x8f00000 0x1000>;
diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
index 4fbd8e9..e2bb597 100644
--- a/arch/arm/boot/dts/stih410-b2260.dts
+++ b/arch/arm/boot/dts/stih410-b2260.dts
@@ -178,9 +178,6 @@
phy-mode = "rgmii";
pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
- snps,phy-bus-name = "stmmac";
- snps,phy-bus-id = <0>;
- snps,phy-addr = <0>;
snps,reset-gpio = <&pio0 7 0>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
index 8341132..a05e227 100644
--- a/arch/arm/boot/dts/stih418.dtsi
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -50,7 +50,7 @@
ohci0: usb@9a03c00 {
compatible = "st,st-ohci-300x";
reg = <0x9a03c00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
<&softreset STIH407_USB2_PORT0_SOFTRESET>;
@@ -62,7 +62,7 @@
ehci0: usb@9a03e00 {
compatible = "st,st-ehci-300x";
reg = <0x9a03e00 0x100>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
@@ -76,7 +76,7 @@
ohci1: usb@9a83c00 {
compatible = "st,st-ohci-300x";
reg = <0x9a83c00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
<&softreset STIH407_USB2_PORT1_SOFTRESET>;
@@ -88,7 +88,7 @@
ehci1: usb@9a83e00 {
compatible = "st,st-ehci-300x";
reg = <0x9a83e00 0x100>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 4f45e71..8b0ead4 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -60,7 +60,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@00000000 {
device_type = "memory";
reg = <0x00000000 0x2000000>;
};
@@ -95,19 +95,26 @@
regulator-max-microvolt = <3300000>;
};
+ vdd_panel: vdd-panel {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
leds {
compatible = "gpio-leds";
- green {
+ led-green {
gpios = <&gpiog 6 1>;
linux,default-trigger = "heartbeat";
};
- orange {
+ led-orange {
gpios = <&gpiog 7 1>;
};
- red {
+ led-red {
gpios = <&gpiog 10 1>;
};
- blue {
+ led-blue {
gpios = <&gpiog 12 1>;
};
};
@@ -136,6 +143,7 @@
panel_rgb: panel-rgb {
compatible = "ampire,am-480272h3tmqw-t01h";
+ power-supply = <&vdd_panel>;
status = "okay";
port {
panel_in_rgb: endpoint {
@@ -230,9 +238,8 @@
<dc {
status = "okay";
- pinctrl-0 = <<dc_pins>;
+ pinctrl-0 = <<dc_pins_a>;
pinctrl-names = "default";
- dma-ranges;
port {
ltdc_out_rgb: endpoint {
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts
index 8d64b52..327613f 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -55,7 +55,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x2000000>;
};
@@ -66,17 +66,17 @@
leds {
compatible = "gpio-leds";
- green {
+ led-green {
gpios = <&gpiof 10 1>;
linux,default-trigger = "heartbeat";
};
- orange {
+ led-orange {
gpios = <&stmfx_pinctrl 17 1>;
};
- red {
+ led-red {
gpios = <&gpiob 7 1>;
};
- blue {
+ led-blue {
gpios = <&stmfx_pinctrl 19 1>;
};
};
@@ -93,7 +93,6 @@
joystick {
compatible = "gpio-keys";
- #size-cells = <0>;
pinctrl-0 = <&joystick_pins>;
pinctrl-names = "default";
button-0 {
@@ -164,7 +163,7 @@
interrupts = <8 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&gpioi>;
- stmfx_pinctrl: stmfx-pin-controller {
+ stmfx_pinctrl: pinctrl {
compatible = "st,stmfx-0300-pinctrl";
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index 3520289..4774163 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -163,7 +163,7 @@
st,bank-name = "GPIOK";
};
- usart1_pins_a: usart1@0 {
+ usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
@@ -176,7 +176,7 @@
};
};
- usart3_pins_a: usart3@0 {
+ usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
bias-disable;
@@ -189,7 +189,7 @@
};
};
- usbotg_fs_pins_a: usbotg_fs@0 {
+ usbotg_fs_pins_a: usbotg-fs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
@@ -200,7 +200,7 @@
};
};
- usbotg_fs_pins_b: usbotg_fs@1 {
+ usbotg_fs_pins_b: usbotg-fs-1 {
pins {
pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
<STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
@@ -211,7 +211,7 @@
};
};
- usbotg_hs_pins_a: usbotg_hs@0 {
+ usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
@@ -231,7 +231,7 @@
};
};
- ethernet_mii: mii@0 {
+ ethernet_mii: mii-0 {
pins {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
@@ -251,13 +251,13 @@
};
};
- adc3_in8_pin: adc@200 {
+ adc3_in8_pin: adc-200 {
pins {
pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
};
};
- pwm1_pins: pwm@1 {
+ pwm1_pins: pwm1-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
<STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
@@ -265,14 +265,14 @@
};
};
- pwm3_pins: pwm@3 {
+ pwm3_pins: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
<STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
};
};
- i2c1_pins: i2c1@0 {
+ i2c1_pins: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
<STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
@@ -282,7 +282,7 @@
};
};
- ltdc_pins: ltdc@0 {
+ ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
@@ -316,7 +316,86 @@
};
};
- dcmi_pins: dcmi@0 {
+ ltdc_pins_b: ltdc-1 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 6, AF14)>,
+ /* LCD_HSYNC */
+ <STM32_PINMUX('A', 4, AF14)>,
+ /* LCD_VSYNC */
+ <STM32_PINMUX('G', 7, AF14)>,
+ /* LCD_CLK */
+ <STM32_PINMUX('C', 10, AF14)>,
+ /* LCD_R2 */
+ <STM32_PINMUX('B', 0, AF9)>,
+ /* LCD_R3 */
+ <STM32_PINMUX('A', 11, AF14)>,
+ /* LCD_R4 */
+ <STM32_PINMUX('A', 12, AF14)>,
+ /* LCD_R5 */
+ <STM32_PINMUX('B', 1, AF9)>,
+ /* LCD_R6*/
+ <STM32_PINMUX('G', 6, AF14)>,
+ /* LCD_R7 */
+ <STM32_PINMUX('A', 6, AF14)>,
+ /* LCD_G2 */
+ <STM32_PINMUX('G', 10, AF9)>,
+ /* LCD_G3 */
+ <STM32_PINMUX('B', 10, AF14)>,
+ /* LCD_G4 */
+ <STM32_PINMUX('D', 6, AF14)>,
+ /* LCD_B2 */
+ <STM32_PINMUX('G', 11, AF14)>,
+ /* LCD_B3*/
+ <STM32_PINMUX('B', 11, AF14)>,
+ /* LCD_G5 */
+ <STM32_PINMUX('C', 7, AF14)>,
+ /* LCD_G6 */
+ <STM32_PINMUX('D', 3, AF14)>,
+ /* LCD_G7 */
+ <STM32_PINMUX('G', 12, AF9)>,
+ /* LCD_B4 */
+ <STM32_PINMUX('A', 3, AF14)>,
+ /* LCD_B5 */
+ <STM32_PINMUX('B', 8, AF14)>,
+ /* LCD_B6 */
+ <STM32_PINMUX('B', 9, AF14)>,
+ /* LCD_B7 */
+ <STM32_PINMUX('F', 10, AF14)>;
+ /* LCD_DE */
+ slew-rate = <2>;
+ };
+ };
+
+ spi5_pins: spi5-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF5)>,
+ /* SPI5_CLK */
+ <STM32_PINMUX('F', 9, AF5)>;
+ /* SPI5_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 8, AF5)>;
+ /* SPI5_MISO */
+ bias-disable;
+ };
+ };
+
+ i2c3_pins: i2c3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 9, AF4)>,
+ /* I2C3_SDA */
+ <STM32_PINMUX('A', 8, AF4)>;
+ /* I2C3_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <3>;
+ };
+ };
+
+ dcmi_pins: dcmi-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
<STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
@@ -339,7 +418,7 @@
};
};
- sdio_pins: sdio_pins@0 {
+ sdio_pins: sdio-pins-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
@@ -352,7 +431,7 @@
};
};
- sdio_pins_od: sdio_pins_od@0 {
+ sdio_pins_od: sdio-pins-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 49ae2d7..6435e09 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -49,6 +49,8 @@
#include "stm32f429.dtsi"
#include "stm32f429-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "STMicroelectronics STM32F429i-DISCO board";
@@ -59,7 +61,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@90000000 {
device_type = "memory";
reg = <0x90000000 0x800000>;
};
@@ -70,10 +72,10 @@
leds {
compatible = "gpio-leds";
- red {
+ led-red {
gpios = <&gpiog 14 0>;
};
- green {
+ led-green {
gpios = <&gpiog 13 0>;
linux,default-trigger = "heartbeat";
};
@@ -106,12 +108,103 @@
status = "okay";
};
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ stmpe811@41 {
+ compatible = "st,stmpe811";
+ reg = <0x41>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpioa>;
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+ /* ADC converstion time: 80 clocks */
+ st,sample-time = <4>;
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ /* 8 sample average control */
+ st,ave-ctrl = <3>;
+ /* 7 length fractional part in z */
+ st,fraction-z = <7>;
+ /*
+ * 50 mA typical 80 mA max touchscreen drivers
+ * current limit value
+ */
+ st,i-drive = <1>;
+ /* 1 ms panel driver settling time */
+ st,settling = <3>;
+ /* 5 ms touch detect interrupt delay */
+ st,touch-det-delay = <5>;
+ };
+
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ /* forbid to use ADC channels 3-0 (touch) */
+ st,norequest-mask = <0x0F>;
+ };
+ };
+};
+
+<dc {
+ status = "okay";
+ pinctrl-0 = <<dc_pins_b>;
+ pinctrl-names = "default";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
+
&rtc {
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSI>;
status = "okay";
};
+&spi5 {
+ status = "okay";
+ pinctrl-0 = <&spi5_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>;
+
+ l3gd20: l3gd20@0 {
+ compatible = "st,l3gd20-gyro";
+ spi-max-frequency = <10000000>;
+ st,drdy-int-pin = <2>;
+ interrupt-parent = <&gpioa>;
+ interrupts = <1 IRQ_TYPE_EDGE_RISING>,
+ <2 IRQ_TYPE_EDGE_RISING>;
+ reg = <0>;
+ status = "okay";
+ };
+
+ display: display@1{
+ /* Connect panel-ilitek-9341 to ltdc */
+ compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341";
+ reg = <1>;
+ spi-3wire;
+ spi-max-frequency = <10000000>;
+ dc-gpios = <&gpiod 13 0>;
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <<dc_out_rgb>;
+ };
+ };
+ };
+};
+
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index dd41342..0dc5fa9 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -80,7 +80,7 @@
};
soc {
- romem: nvmem@1fff7800 {
+ romem: efuse@1fff7800 {
compatible = "st,stm32f4-otp";
reg = <0x1fff7800 0x400>;
#address-cells = <1>;
@@ -314,12 +314,10 @@
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
- clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
interrupts = <17 1>;
- interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
@@ -399,6 +397,18 @@
status = "disabled";
};
+ i2c3: i2c@40005c00 {
+ compatible = "st,stm32f4-i2c";
+ reg = <0x40005c00 0x400>;
+ interrupts = <72>,
+ <73>;
+ resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
+ clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
dac: dac@40007400 {
compatible = "st,stm32f4-dac-core";
reg = <0x40007400 0x400>;
@@ -411,14 +421,14 @@
dac1: dac@1 {
compatible = "st,stm32-dac";
- #io-channels-cells = <1>;
+ #io-channel-cells = <1>;
reg = <1>;
status = "disabled";
};
dac2: dac@2 {
compatible = "st,stm32-dac";
- #io-channels-cells = <1>;
+ #io-channel-cells = <1>;
reg = <2>;
status = "disabled";
};
@@ -583,8 +593,8 @@
status = "disabled";
};
- syscfg: system-config@40013800 {
- compatible = "syscon";
+ syscfg: syscon@40013800 {
+ compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
};
@@ -653,6 +663,9 @@
reg = <0x40015000 0x400>;
interrupts = <85>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
+ dmas = <&dma2 3 2 0x400 0x0>,
+ <&dma2 4 2 0x400 0x0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -667,7 +680,7 @@
};
pwrcfg: power-config@40007000 {
- compatible = "syscon";
+ compatible = "st,stm32-power-config", "syscon";
reg = <0x40007000 0x400>;
};
@@ -781,7 +794,6 @@
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
- interrupts = <80>;
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
};
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 0ce4501..8c982ae 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -60,7 +60,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@00000000 {
device_type = "memory";
reg = <0x00000000 0x1000000>;
};
@@ -89,17 +89,17 @@
leds {
compatible = "gpio-leds";
- green {
+ led-green {
gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
- orange {
+ led-orange {
gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
};
- red {
+ led-red {
gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
};
- blue {
+ led-blue {
gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
};
};
@@ -172,7 +172,6 @@
};
<dc {
- dma-ranges;
status = "okay";
port {
diff --git a/arch/arm/boot/dts/stm32f469.dtsi b/arch/arm/boot/dts/stm32f469.dtsi
index 5ae5213..be002e8 100644
--- a/arch/arm/boot/dts/stm32f469.dtsi
+++ b/arch/arm/boot/dts/stm32f469.dtsi
@@ -8,7 +8,6 @@
dsi: dsi@40016c00 {
compatible = "st,stm32-dsi";
reg = <0x40016c00 0x800>;
- interrupts = <92>;
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
reset-names = "apb";
clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
index 9314128..fe4cfda 100644
--- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
@@ -127,7 +127,7 @@
st,bank-name = "GPIOK";
};
- cec_pins_a: cec@0 {
+ cec_pins_a: cec-0 {
pins {
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
slew-rate = <0>;
@@ -136,7 +136,7 @@
};
};
- usart1_pins_a: usart1@0 {
+ usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
@@ -149,7 +149,7 @@
};
};
- usart1_pins_b: usart1@1 {
+ usart1_pins_b: usart1-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
@@ -162,7 +162,7 @@
};
};
- i2c1_pins_b: i2c1@0 {
+ i2c1_pins_b: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
@@ -172,7 +172,7 @@
};
};
- usbotg_hs_pins_a: usbotg-hs@0 {
+ usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
@@ -192,7 +192,7 @@
};
};
- usbotg_hs_pins_b: usbotg-hs@1 {
+ usbotg_hs_pins_b: usbotg-hs-1 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
@@ -212,7 +212,7 @@
};
};
- usbotg_fs_pins_a: usbotg-fs@0 {
+ usbotg_fs_pins_a: usbotg-fs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
@@ -223,7 +223,7 @@
};
};
- sdio_pins_a: sdio_pins_a@0 {
+ sdio_pins_a: sdio-pins-a-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
@@ -236,7 +236,7 @@
};
};
- sdio_pins_od_a: sdio_pins_od_a@0 {
+ sdio_pins_od_a: sdio-pins-od-a-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
@@ -254,7 +254,7 @@
};
};
- sdio_pins_b: sdio_pins_b@0 {
+ sdio_pins_b: sdio-pins-b-0 {
pins {
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
@@ -267,7 +267,7 @@
};
};
- sdio_pins_od_b: sdio_pins_od_b@0 {
+ sdio_pins_od_b: sdio-pins-od-b-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts
index 0ba9c5b..569d23c 100644
--- a/arch/arm/boot/dts/stm32f746-disco.dts
+++ b/arch/arm/boot/dts/stm32f746-disco.dts
@@ -55,7 +55,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x800000>;
};
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 60680fc..d49e481 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -296,12 +296,10 @@
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
- clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
interrupts = <17 1>;
- interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
@@ -493,8 +491,8 @@
status = "disabled";
};
- syscfg: system-config@40013800 {
- compatible = "syscon";
+ syscfg: syscon@40013800 {
+ compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
};
@@ -557,7 +555,7 @@
};
pwrcfg: power-config@40007000 {
- compatible = "syscon";
+ compatible = "st,stm32-power-config", "syscon";
reg = <0x40007000 0x400>;
};
@@ -579,7 +577,7 @@
assigned-clock-rates = <1000000>;
};
- dma1: dma@40026000 {
+ dma1: dma-controller@40026000 {
compatible = "st,stm32-dma";
reg = <0x40026000 0x400>;
interrupts = <11>,
@@ -595,7 +593,7 @@
status = "disabled";
};
- dma2: dma@40026400 {
+ dma2: dma-controller@40026400 {
compatible = "st,stm32-dma";
reg = <0x40026400 0x400>;
interrupts = <56>,
diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
index a4284b7..be943b7 100644
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -55,7 +55,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x1000000>;
};
@@ -66,11 +66,11 @@
leds {
compatible = "gpio-leds";
- green {
+ led-green {
gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
- red {
+ led-red {
gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index e44e7ba..fa5dcb6 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -163,7 +163,7 @@
#interrupt-cells = <2>;
};
- i2c1_pins_a: i2c1@0 {
+ i2c1_pins_a: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
<STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
@@ -173,7 +173,7 @@
};
};
- ethernet_rmii: rmii@0 {
+ ethernet_rmii: rmii-0 {
pins {
pinmux = <STM32_PINMUX('G', 11, AF11)>,
<STM32_PINMUX('G', 13, AF11)>,
@@ -256,7 +256,7 @@
};
};
- usart1_pins: usart1@0 {
+ usart1_pins: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
bias-disable;
@@ -269,7 +269,7 @@
};
};
- usart2_pins: usart2@0 {
+ usart2_pins: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
bias-disable;
@@ -282,7 +282,7 @@
};
};
- usbotg_hs_pins_a: usbotg-hs@0 {
+ usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
<STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 82a234c..1579707 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -110,6 +110,7 @@
compatible = "st,stm32h7-spi";
reg = <0x40003800 0x400>;
interrupts = <36>;
+ resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
clocks = <&rcc SPI2_CK>;
status = "disabled";
@@ -121,12 +122,13 @@
compatible = "st,stm32h7-spi";
reg = <0x40003c00 0x400>;
interrupts = <51>;
+ resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
clocks = <&rcc SPI3_CK>;
status = "disabled";
};
usart2: serial@40004400 {
- compatible = "st,stm32f7-uart";
+ compatible = "st,stm32h7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
status = "disabled";
@@ -180,21 +182,21 @@
dac1: dac@1 {
compatible = "st,stm32-dac";
- #io-channels-cells = <1>;
+ #io-channel-cells = <1>;
reg = <1>;
status = "disabled";
};
dac2: dac@2 {
compatible = "st,stm32-dac";
- #io-channels-cells = <1>;
+ #io-channel-cells = <1>;
reg = <2>;
status = "disabled";
};
};
usart1: serial@40011000 {
- compatible = "st,stm32f7-uart";
+ compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
status = "disabled";
@@ -207,6 +209,7 @@
compatible = "st,stm32h7-spi";
reg = <0x40013000 0x400>;
interrupts = <35>;
+ resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
clocks = <&rcc SPI1_CK>;
status = "disabled";
};
@@ -217,6 +220,7 @@
compatible = "st,stm32h7-spi";
reg = <0x40013400 0x400>;
interrupts = <84>;
+ resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
clocks = <&rcc SPI4_CK>;
status = "disabled";
};
@@ -227,11 +231,12 @@
compatible = "st,stm32h7-spi";
reg = <0x40015000 0x400>;
interrupts = <85>;
+ resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
clocks = <&rcc SPI5_CK>;
status = "disabled";
};
- dma1: dma@40020000 {
+ dma1: dma-controller@40020000 {
compatible = "st,stm32-dma";
reg = <0x40020000 0x400>;
interrupts = <11>,
@@ -249,7 +254,7 @@
status = "disabled";
};
- dma2: dma@40020400 {
+ dma2: dma-controller@40020400 {
compatible = "st,stm32-dma";
reg = <0x40020400 0x400>;
interrupts = <56>,
@@ -329,7 +334,17 @@
status = "disabled";
};
- mdma1: dma@52000000 {
+ ltdc: display-controller@50001000 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x50001000 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
+ clocks = <&rcc LTDC_CK>;
+ clock-names = "lcd";
+ status = "disabled";
+ };
+
+ mdma1: dma-controller@52000000 {
compatible = "st,stm32h7-mdma";
reg = <0x52000000 0x1000>;
interrupts = <122>;
@@ -361,8 +376,8 @@
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
};
- syscfg: system-config@58000400 {
- compatible = "syscon";
+ syscfg: syscon@58000400 {
+ compatible = "st,stm32-syscfg", "syscon";
reg = <0x58000400 0x400>;
};
@@ -372,6 +387,7 @@
compatible = "st,stm32h7-spi";
reg = <0x58001400 0x400>;
interrupts = <86>;
+ resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
clocks = <&rcc SPI6_CK>;
status = "disabled";
};
@@ -483,7 +499,6 @@
assigned-clock-parents = <&rcc LSE_CK>;
interrupt-parent = <&exti>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "alarm";
st,syscfg = <&pwrcfg 0x00 0x100>;
status = "disabled";
};
@@ -498,7 +513,7 @@
};
pwrcfg: power-config@58024800 {
- compatible = "syscon";
+ compatible = "st,stm32-power-config", "syscon";
reg = <0x58024800 0x400>;
};
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts
index 3acd2e9..e446d31 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -53,7 +53,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@d0000000 {
device_type = "memory";
reg = <0xd0000000 0x2000000>;
};
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
index e4d3c58..8f39817 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -53,7 +53,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@d0000000 {
device_type = "memory";
reg = <0xd0000000 0x2000000>;
};
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
new file mode 100644
index 0000000..ccf66ad
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -0,0 +1,1988 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+&pinctrl {
+ adc1_in6_pins_a: adc1-in6-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
+ };
+ };
+
+ adc12_ain_pins_a: adc12-ain-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
+ <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
+ <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
+ <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
+ };
+ };
+
+ adc12_ain_pins_b: adc12-ain-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
+ <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */
+ };
+ };
+
+ adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
+ <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
+ };
+ };
+
+ cec_pins_a: cec-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, AF4)>;
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ cec_sleep_pins_a: cec-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
+ };
+ };
+
+ cec_pins_b: cec-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, AF5)>;
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ cec_sleep_pins_b: cec-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
+ };
+ };
+
+ dac_ch1_pins_a: dac-ch1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+ };
+ };
+
+ dac_ch2_pins_a: dac-ch2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+ };
+ };
+
+ dcmi_pins_a: dcmi-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
+ bias-disable;
+ };
+ };
+
+ dcmi_sleep_pins_a: dcmi-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
+ <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
+ <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
+ <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
+ <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
+ };
+ };
+
+ ethernet0_rgmii_pins_a: rgmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+ };
+ };
+
+ ethernet0_rgmii_pins_b: rgmii-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+ };
+ };
+
+ ethernet0_rgmii_pins_c: rgmii-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
+ <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
+ <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
+ <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
+ <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
+ <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
+ };
+ };
+
+ ethernet0_rmii_pins_a: rmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
+ <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
+ };
+ };
+
+ fmc_pins_a: fmc-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
+ <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
+ <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
+ <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
+ <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
+ bias-pull-up;
+ };
+ };
+
+ fmc_sleep_pins_a: fmc-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
+ <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
+ <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
+ <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
+ <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
+ <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
+ <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
+ <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
+ <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
+ <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
+ <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
+ <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
+ };
+ };
+
+ i2c1_pins_a: i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_sleep_pins_a: i2c1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
+ i2c1_pins_b: i2c1-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c1_sleep_pins_b: i2c1-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
+ <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
+ };
+ };
+
+ i2c2_pins_a: i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_sleep_pins_a: i2c2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c2_pins_b1: i2c2-1 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_sleep_pins_b1: i2c2-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c2_pins_c: i2c2-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_pins_sleep_c: i2c2-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+
+ i2c5_pins_a: i2c5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
+ <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_a: i2c5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
+ <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
+
+ };
+ };
+
+ i2c5_pins_b: i2c5-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */
+ <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c5_sleep_pins_b: i2c5-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */
+ <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */
+ };
+ };
+
+ i2s2_pins_a: i2s2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ i2s2_sleep_pins_a: i2s2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
+ <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
+ };
+ };
+
+ ltdc_pins_a: ltdc-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ ltdc_sleep_pins_a: ltdc-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
+ ltdc_pins_b: ltdc-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
+ <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ ltdc_sleep_pins_b: ltdc-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
+ <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
+ <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
+ <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
+ <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
+ <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
+ <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
+ ltdc_pins_c: ltdc-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */
+ <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */
+ <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */
+ <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */
+ <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */
+ <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
+ <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */
+ <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */
+ <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */
+ <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */
+ <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */
+ <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */
+ <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
+ <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */
+ <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */
+ <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */
+ <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
+ <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */
+ <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */
+ <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
+ <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ ltdc_sleep_pins_c: ltdc-sleep-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */
+ <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */
+ <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */
+ <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */
+ <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */
+ <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */
+ <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */
+ <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */
+ <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
+ <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */
+ <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */
+ <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */
+ <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */
+ <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */
+ <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */
+ <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
+ <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */
+ <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */
+ };
+ };
+
+ ltdc_pins_d: ltdc-3 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */
+ <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */
+ <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ ltdc_sleep_pins_d: ltdc-sleep-3 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
+ <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
+ m_can1_pins_a: m-can1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ m_can1_sleep_pins_a: m_can1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
+ <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
+ };
+ };
+
+ m_can1_pins_b: m-can1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ m_can1_sleep_pins_b: m_can1-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
+ <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
+ };
+ };
+
+ m_can2_pins_a: m-can2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
+ bias-disable;
+ };
+ };
+
+ m_can2_sleep_pins_a: m_can2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
+ <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
+ };
+ };
+
+ pwm1_pins_a: pwm1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
+ <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
+ <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm1_sleep_pins_a: pwm1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
+ <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
+ <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
+ };
+ };
+
+ pwm2_pins_a: pwm2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm2_sleep_pins_a: pwm2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
+ };
+ };
+
+ pwm3_pins_a: pwm3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm3_sleep_pins_a: pwm3-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
+ };
+ };
+
+ pwm3_pins_b: pwm3-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm3_sleep_pins_b: pwm3-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */
+ };
+ };
+
+ pwm4_pins_a: pwm4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
+ <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm4_sleep_pins_a: pwm4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
+ <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
+ };
+ };
+
+ pwm4_pins_b: pwm4-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm4_sleep_pins_b: pwm4-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
+ };
+ };
+
+ pwm5_pins_a: pwm5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm5_sleep_pins_a: pwm5-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
+ };
+ };
+
+ pwm5_pins_b: pwm5-1 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */
+ <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */
+ <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm5_sleep_pins_b: pwm5-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */
+ <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */
+ <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */
+ };
+ };
+
+ pwm8_pins_a: pwm8-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm8_sleep_pins_a: pwm8-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
+ };
+ };
+
+ pwm12_pins_a: pwm12-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm12_sleep_pins_a: pwm12-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
+ };
+ };
+
+ qspi_clk_pins_a: qspi-clk-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
+ };
+ };
+
+ qspi_bk1_pins_a: qspi-bk1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
+ <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
+ };
+ };
+
+ qspi_bk2_pins_a: qspi-bk2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
+ <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
+ <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
+ };
+ };
+
+ sai2a_pins_a: sai2a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai2a_sleep_pins_a: sai2a-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
+ <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
+ };
+ };
+
+ sai2a_pins_b: sai2a-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
+ <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai2a_sleep_pins_b: sai2a-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
+ <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
+ <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
+ };
+ };
+
+ sai2a_pins_c: sai2a-2 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
+ <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai2a_sleep_pins_c: sai2a-2 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
+ <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
+ <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */
+ };
+ };
+
+ sai2b_pins_a: sai2b-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai2b_sleep_pins_a: sai2b-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
+ <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
+ <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
+ };
+ };
+
+ sai2b_pins_b: sai2b-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai2b_sleep_pins_b: sai2b-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
+ };
+ };
+
+ sai2b_pins_c: sai2b-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai2b_sleep_pins_c: sai2b-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
+ };
+ };
+
+ sai4a_pins_a: sai4a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sai4a_sleep_pins_a: sai4a-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
+ };
+ };
+
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
+
+ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2{
+ pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+ bias-pull-up;
+ };
+ };
+
+ sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
+ };
+ };
+
+ sdmmc1_dir_pins_b: sdmmc1-dir-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2{
+ pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
+ bias-pull-up;
+ };
+ };
+
+ sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
+ };
+ };
+
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ sdmmc2_b4_pins_b: sdmmc2-b4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
+ sdmmc2_d47_pins_b: sdmmc2-d47-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
+ sdmmc2_d47_pins_c: sdmmc2-d47-2 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
+ sdmmc2_d47_pins_d: sdmmc2-d47-3 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
+ sdmmc3_b4_pins_a: sdmmc3-b4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
+ <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
+ };
+ };
+
+ sdmmc3_b4_pins_b: sdmmc3-b4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
+ <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
+ <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
+ <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
+ };
+ };
+
+ spdifrx_pins_a: spdifrx-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
+ bias-disable;
+ };
+ };
+
+ spdifrx_sleep_pins_a: spdifrx-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
+ };
+ };
+
+ spi2_pins_a: spi2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */
+ <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
+ bias-disable;
+ };
+ };
+
+ uart4_pins_a: uart4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_idle_pins_a: uart4-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_sleep_pins_a: uart4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
+ };
+ };
+
+ uart4_pins_b: uart4-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_pins_c: uart4-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_pins_a: uart7-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
+ <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
+ <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
+ bias-disable;
+ };
+ };
+
+ uart7_pins_b: uart7-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_pins_c: uart7-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_idle_pins_c: uart7-idle-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
+ bias-disable;
+ };
+ };
+
+ uart7_sleep_pins_c: uart7-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */
+ <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */
+ };
+ };
+
+ uart8_pins_a: uart8-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
+ bias-disable;
+ };
+ };
+
+ uart8_rtscts_pins_a: uart8rtscts-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */
+ <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */
+ bias-disable;
+ };
+ };
+
+ spi4_pins_a: spi4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
+ <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
+ bias-disable;
+ };
+ };
+
+ usart2_pins_a: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_a: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
+
+ usart2_pins_b: usart2-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
+ <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
+ <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_b: usart2-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
+
+ usart2_pins_c: usart2-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_c: usart2-idle-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_c: usart2-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
+ <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
+ };
+ };
+
+ usart3_pins_a: usart3-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
+ bias-disable;
+ };
+ };
+
+ usart3_pins_b: usart3-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
+ <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart3_idle_pins_b: usart3-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
+ bias-disable;
+ };
+ };
+
+ usart3_sleep_pins_b: usart3-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+ <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
+ };
+ };
+
+ usart3_pins_c: usart3-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
+ <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
+ bias-disable;
+ };
+ };
+
+ usart3_idle_pins_c: usart3-idle-2 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
+ bias-disable;
+ };
+ };
+
+ usart3_sleep_pins_c: usart3-sleep-2 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
+ <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
+ <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
+ <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
+ };
+ };
+
+ usbotg_hs_pins_a: usbotg-hs-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
+ };
+ };
+
+ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
+ <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
+ };
+ };
+};
+
+&pinctrl_z {
+ i2c2_pins_b2: i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_sleep_pins_b2: i2c2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
+ };
+ };
+
+ i2c4_pins_a: i2c4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c4_sleep_pins_a: i2c4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
+ <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
+ };
+ };
+
+ spi1_pins_a: spi1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
+ <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
+ bias-disable;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
similarity index 80%
rename from arch/arm/boot/dts/stm32mp157c.dtsi
rename to arch/arm/boot/dts/stm32mp151.dtsi
index eca469a..7a0ef01 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -17,22 +17,22 @@
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
+ clock-frequency = <650000000>;
device_type = "cpu";
reg = <0>;
};
+ };
- cpu1: cpu@1 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <1>;
- };
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ interrupt-parent = <&intc>;
};
psci {
- compatible = "arm,psci";
+ compatible = "arm,psci-1.0";
method = "smc";
- cpu_off = <0x84000002>;
- cpu_on = <0x84000003>;
};
intc: interrupt-controller@a0021000 {
@@ -148,6 +148,11 @@
reg = <1>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
timers3: timer@40001000 {
@@ -177,6 +182,11 @@
reg = <2>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
timers4: timer@40002000 {
@@ -204,6 +214,11 @@
reg = <3>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
timers5: timer@40003000 {
@@ -233,6 +248,11 @@
reg = <4>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
timers6: timer@40004000 {
@@ -460,7 +480,7 @@
};
i2c1: i2c@40012000 {
- compatible = "st,stm32f7-i2c";
+ compatible = "st,stm32mp15-i2c";
reg = <0x40012000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
@@ -469,11 +489,13 @@
resets = <&rcc I2C1_R>;
#address-cells = <1>;
#size-cells = <0>;
+ st,syscfg-fmp = <&syscfg 0x4 0x1>;
+ wakeup-source;
status = "disabled";
};
i2c2: i2c@40013000 {
- compatible = "st,stm32f7-i2c";
+ compatible = "st,stm32mp15-i2c";
reg = <0x40013000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
@@ -482,11 +504,13 @@
resets = <&rcc I2C2_R>;
#address-cells = <1>;
#size-cells = <0>;
+ st,syscfg-fmp = <&syscfg 0x4 0x2>;
+ wakeup-source;
status = "disabled";
};
i2c3: i2c@40014000 {
- compatible = "st,stm32f7-i2c";
+ compatible = "st,stm32mp15-i2c";
reg = <0x40014000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
@@ -495,11 +519,13 @@
resets = <&rcc I2C3_R>;
#address-cells = <1>;
#size-cells = <0>;
+ st,syscfg-fmp = <&syscfg 0x4 0x4>;
+ wakeup-source;
status = "disabled";
};
i2c5: i2c@40015000 {
- compatible = "st,stm32f7-i2c";
+ compatible = "st,stm32mp15-i2c";
reg = <0x40015000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
@@ -508,6 +534,8 @@
resets = <&rcc I2C5_R>;
#address-cells = <1>;
#size-cells = <0>;
+ st,syscfg-fmp = <&syscfg 0x4 0x10>;
+ wakeup-source;
status = "disabled";
};
@@ -531,14 +559,14 @@
dac1: dac@1 {
compatible = "st,stm32-dac";
- #io-channels-cells = <1>;
+ #io-channel-cells = <1>;
reg = <1>;
status = "disabled";
};
dac2: dac@2 {
compatible = "st,stm32-dac";
- #io-channels-cells = <1>;
+ #io-channel-cells = <1>;
reg = <2>;
status = "disabled";
};
@@ -589,6 +617,11 @@
reg = <0>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
timers8: timer@44001000 {
@@ -620,6 +653,11 @@
reg = <7>;
status = "disabled";
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ status = "disabled";
+ };
};
usart6: serial@44003000 {
@@ -773,7 +811,7 @@
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x1c>;
+ reg = <0x4 0x20>;
clocks = <&rcc SAI1_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 87 0x400 0x01>;
@@ -783,7 +821,7 @@
sai1b: audio-controller@4400a024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x1c>;
+ reg = <0x24 0x20>;
clocks = <&rcc SAI1_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 88 0x400 0x01>;
@@ -804,7 +842,7 @@
sai2a: audio-controller@4400b004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
- reg = <0x4 0x1c>;
+ reg = <0x4 0x20>;
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 89 0x400 0x01>;
@@ -814,7 +852,7 @@
sai2b: audio-controller@4400b024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x1c>;
+ reg = <0x24 0x20>;
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 90 0x400 0x01>;
@@ -835,7 +873,7 @@
sai3a: audio-controller@4400c004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
- reg = <0x04 0x1c>;
+ reg = <0x04 0x20>;
clocks = <&rcc SAI3_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 113 0x400 0x01>;
@@ -845,7 +883,7 @@
sai3b: audio-controller@4400c024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x1c>;
+ reg = <0x24 0x20>;
clocks = <&rcc SAI3_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 114 0x400 0x01>;
@@ -923,33 +961,7 @@
};
};
- m_can1: can@4400e000 {
- compatible = "bosch,m_can";
- reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-
- m_can2: can@4400f000 {
- compatible = "bosch,m_can";
- reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
- reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-
- dma1: dma@48000000 {
+ dma1: dma-controller@48000000 {
compatible = "st,stm32-dma";
reg = <0x48000000 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
@@ -961,12 +973,13 @@
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc DMA1>;
+ resets = <&rcc DMA1_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
};
- dma2: dma@48001000 {
+ dma2: dma-controller@48001000 {
compatible = "st,stm32-dma";
reg = <0x48001000 0x400>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
@@ -978,6 +991,7 @@
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc DMA2>;
+ resets = <&rcc DMA2_R>;
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
@@ -991,6 +1005,7 @@
dma-masters = <&dma1 &dma2>;
dma-channels = <16>;
clocks = <&rcc DMAMUX>;
+ resets = <&rcc DMAMUX_R>;
};
adc: adc@48003000 {
@@ -1030,8 +1045,23 @@
};
};
+ sdmmc3: sdmmc@48004000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x10153180>;
+ reg = <0x48004000 0x400>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC3_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC3_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
+ };
+
usbotg_hs: usb-otg@49000000 {
- compatible = "snps,dwc2";
+ compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x10000>;
clocks = <&rcc USBO_K>;
clock-names = "otg";
@@ -1042,6 +1072,7 @@
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
dr_mode = "otg";
+ usb33d-supply = <&usb33>;
status = "disabled";
};
@@ -1079,6 +1110,34 @@
#reset-cells = <1>;
};
+ pwr_regulators: pwr@50001000 {
+ compatible = "st,stm32mp1,pwr-reg";
+ reg = <0x50001000 0x10>;
+
+ reg11: reg11 {
+ regulator-name = "reg11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
+
+ reg18: reg18 {
+ regulator-name = "reg18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ usb33: usb33 {
+ regulator-name = "usb33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
+ pwr_mcu: pwr_mcu@50001014 {
+ compatible = "st,stm32mp151-pwr-mcu", "syscon";
+ reg = <0x50001014 0x4>;
+ };
+
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp1-exti", "syscon";
interrupt-controller;
@@ -1191,7 +1250,7 @@
sai4a: audio-controller@50027004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
- reg = <0x04 0x1c>;
+ reg = <0x04 0x20>;
clocks = <&rcc SAI4_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 99 0x400 0x01>;
@@ -1201,7 +1260,7 @@
sai4b: audio-controller@50027024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
- reg = <0x24 0x1c>;
+ reg = <0x24 0x20>;
clocks = <&rcc SAI4_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 100 0x400 0x01>;
@@ -1219,15 +1278,6 @@
status = "disabled";
};
- cryp1: cryp@54001000 {
- compatible = "st,stm32mp1-cryp";
- reg = <0x54001000 0x400>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
- status = "disabled";
- };
-
hash1: hash@54002000 {
compatible = "st,stm32f756-hash";
reg = <0x54002000 0x400>;
@@ -1248,33 +1298,49 @@
status = "disabled";
};
- mdma1: dma@58000000 {
+ mdma1: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc MDMA>;
+ resets = <&rcc MDMA_R>;
#dma-cells = <5>;
dma-channels = <32>;
dma-requests = <48>;
};
- fmc: nand-controller@58002000 {
- compatible = "st,stm32mp15-fmc2";
- reg = <0x58002000 0x1000>,
- <0x80000000 0x1000>,
- <0x88010000 0x1000>,
- <0x88020000 0x1000>,
- <0x81000000 0x1000>,
- <0x89010000 0x1000>,
- <0x89020000 0x1000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
- <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
- <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
- dma-names = "tx", "rx", "ecc";
+ fmc: memory-controller@58002000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp1-fmc2-ebi";
+ reg = <0x58002000 0x1000>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
+
+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+ <4 0 0x80000000 0x10000000>; /* NAND */
+
+ nand-controller@4,0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32mp1-fmc2-nfc";
+ reg = <4 0x00000000 0x1000>,
+ <4 0x08010000 0x1000>,
+ <4 0x08020000 0x1000>,
+ <4 0x01000000 0x1000>,
+ <4 0x09010000 0x1000>,
+ <4 0x09020000 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+ <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+ <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+ dma-names = "tx", "rx", "ecc";
+ status = "disabled";
+ };
};
qspi: spi@58003000 {
@@ -1287,6 +1353,8 @@
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
@@ -1295,13 +1363,29 @@
arm,primecell-periphid = <0x10153180>;
reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
+ interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
+ status = "disabled";
+ };
+
+ sdmmc2: sdmmc@58007000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x10153180>;
+ reg = <0x58007000 0x1000>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&rcc SDMMC2_K>;
+ clock-names = "apb_pclk";
+ resets = <&rcc SDMMC2_R>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
+ status = "disabled";
};
crc1: crc@58009000 {
@@ -1320,16 +1404,17 @@
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
- "ethstp",
- "syscfg-clk";
+ "eth-ck",
+ "ethstp";
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
- <&rcc ETHSTP>,
- <&rcc SYSCFG>;
+ <&rcc ETHCK_K>,
+ <&rcc ETHSTP>;
st,syscon = <&syscfg 0x4>;
snps,mixed-burst;
snps,pbl = <2>;
+ snps,en-tx-lpi-clockgating;
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
status = "disabled";
@@ -1360,26 +1445,6 @@
status = "disabled";
};
- gpu: gpu@59000000 {
- compatible = "vivante,gc";
- reg = <0x59000000 0x800>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc GPU>, <&rcc GPU_K>;
- clock-names = "bus" ,"core";
- resets = <&rcc GPU_R>;
- status = "disabled";
- };
-
- dsi: dsi@5a000000 {
- compatible = "st,stm32-dsi";
- reg = <0x5a000000 0x800>;
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
- clock-names = "pclk", "ref", "px_clk";
- resets = <&rcc DSI_R>;
- reset-names = "apb";
- status = "disabled";
- };
-
ltdc: display-controller@5a001000 {
compatible = "st,stm32-ltdc";
reg = <0x5a001000 0x400>;
@@ -1389,6 +1454,11 @@
clock-names = "lcd";
resets = <&rcc LTDC_R>;
status = "disabled";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
iwdg2: watchdog@5a002000 {
@@ -1442,7 +1512,7 @@
};
i2c4: i2c@5c002000 {
- compatible = "st,stm32f7-i2c";
+ compatible = "st,stm32mp15-i2c";
reg = <0x5c002000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
@@ -1451,6 +1521,8 @@
resets = <&rcc I2C4_R>;
#address-cells = <1>;
#size-cells = <0>;
+ st,syscfg-fmp = <&syscfg 0x4 0x8>;
+ wakeup-source;
status = "disabled";
};
@@ -1463,7 +1535,7 @@
status = "disabled";
};
- bsec: nvmem@5c005000 {
+ bsec: efuse@5c005000 {
compatible = "st,stm32mp15-bsec";
reg = <0x5c005000 0x400>;
#address-cells = <1>;
@@ -1477,7 +1549,7 @@
};
i2c6: i2c@5c009000 {
- compatible = "st,stm32f7-i2c";
+ compatible = "st,stm32mp15-i2c";
reg = <0x5c009000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
@@ -1486,14 +1558,174 @@
resets = <&rcc I2C6_R>;
#address-cells = <1>;
#size-cells = <0>;
+ st,syscfg-fmp = <&syscfg 0x4 0x20>;
+ wakeup-source;
status = "disabled";
};
+
+ /*
+ * Break node order to solve dependency probe issue between
+ * pinctrl and exti.
+ */
+ pinctrl: pin-controller@50002000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp157-pinctrl";
+ ranges = <0 0x50002000 0xa400>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&exti 0x60 0xff>;
+ pins-are-numbered;
+
+ gpioa: gpio@50002000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&rcc GPIOA>;
+ st,bank-name = "GPIOA";
+ status = "disabled";
+ };
+
+ gpiob: gpio@50003000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&rcc GPIOB>;
+ st,bank-name = "GPIOB";
+ status = "disabled";
+ };
+
+ gpioc: gpio@50004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&rcc GPIOC>;
+ st,bank-name = "GPIOC";
+ status = "disabled";
+ };
+
+ gpiod: gpio@50005000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x400>;
+ clocks = <&rcc GPIOD>;
+ st,bank-name = "GPIOD";
+ status = "disabled";
+ };
+
+ gpioe: gpio@50006000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x400>;
+ clocks = <&rcc GPIOE>;
+ st,bank-name = "GPIOE";
+ status = "disabled";
+ };
+
+ gpiof: gpio@50007000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x400>;
+ clocks = <&rcc GPIOF>;
+ st,bank-name = "GPIOF";
+ status = "disabled";
+ };
+
+ gpiog: gpio@50008000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x400>;
+ clocks = <&rcc GPIOG>;
+ st,bank-name = "GPIOG";
+ status = "disabled";
+ };
+
+ gpioh: gpio@50009000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x400>;
+ clocks = <&rcc GPIOH>;
+ st,bank-name = "GPIOH";
+ status = "disabled";
+ };
+
+ gpioi: gpio@5000a000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x400>;
+ clocks = <&rcc GPIOI>;
+ st,bank-name = "GPIOI";
+ status = "disabled";
+ };
+
+ gpioj: gpio@5000b000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x9000 0x400>;
+ clocks = <&rcc GPIOJ>;
+ st,bank-name = "GPIOJ";
+ status = "disabled";
+ };
+
+ gpiok: gpio@5000c000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa000 0x400>;
+ clocks = <&rcc GPIOK>;
+ st,bank-name = "GPIOK";
+ status = "disabled";
+ };
+ };
+
+ pinctrl_z: pin-controller-z@54004000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp157-z-pinctrl";
+ ranges = <0 0x54004000 0x400>;
+ pins-are-numbered;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&exti 0x60 0xff>;
+
+ gpioz: gpio@54004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&rcc GPIOZ>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ status = "disabled";
+ };
+ };
};
- mlahb {
- compatible = "simple-bus";
+ mlahb: ahb {
+ compatible = "st,mlahb", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ ranges;
dma-ranges = <0x00000000 0x38000000 0x10000>,
<0x10000000 0x10000000 0x60000>,
<0x30000000 0x30000000 0x60000>;
@@ -1506,6 +1738,7 @@
resets = <&rcc MCU_R>;
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
st,syscfg-tz = <&rcc 0x000 0x1>;
+ st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi
new file mode 100644
index 0000000..1c1889b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp153.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp151.dtsi"
+
+/ {
+ cpus {
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ clock-frequency = <650000000>;
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ arm-pmu {
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+
+ soc {
+ m_can1: can@4400e000 {
+ compatible = "bosch,m_can";
+ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
+
+ m_can2: can@4400f000 {
+ compatible = "bosch,m_can";
+ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts
new file mode 100644
index 0000000..02a3913
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ *
+ * DHCOM STM32MP1 variant:
+ * DHCM-STM32MP153C-C065-R102-F0819-SPI-E2-CAN2-RTC-I-01D2
+ * DHCOM PCB number: 587-200 or newer
+ * DRC02 PCB number: 568-100 or newer
+ */
+/dts-v1/;
+
+#include "stm32mp153.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15xx-dhcom-som.dtsi"
+#include "stm32mp15xx-dhcom-drc02.dtsi"
+
+/ {
+ model = "DH electronics STM32MP153C DHCOM DRC02";
+ compatible = "dh,stm32mp153c-dhcom-drc02", "dh,stm32mp153c-dhcom-som",
+ "st,stm32mp153";
+};
+
+&m_can1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_a>;
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
+ status = "okay";
+};
+
+&m_can2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can2_pins_a>;
+ pinctrl-1 = <&m_can2_sleep_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
deleted file mode 100644
index 0a3a7d6..0000000
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ /dev/null
@@ -1,925 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
- * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
- */
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
-
-/ {
- soc {
- pinctrl: pin-controller@50002000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp157-pinctrl";
- ranges = <0 0x50002000 0xa400>;
- interrupt-parent = <&exti>;
- st,syscfg = <&exti 0x60 0xff>;
- pins-are-numbered;
-
- gpioa: gpio@50002000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x0 0x400>;
- clocks = <&rcc GPIOA>;
- st,bank-name = "GPIOA";
- status = "disabled";
- };
-
- gpiob: gpio@50003000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x1000 0x400>;
- clocks = <&rcc GPIOB>;
- st,bank-name = "GPIOB";
- status = "disabled";
- };
-
- gpioc: gpio@50004000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x2000 0x400>;
- clocks = <&rcc GPIOC>;
- st,bank-name = "GPIOC";
- status = "disabled";
- };
-
- gpiod: gpio@50005000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x3000 0x400>;
- clocks = <&rcc GPIOD>;
- st,bank-name = "GPIOD";
- status = "disabled";
- };
-
- gpioe: gpio@50006000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x4000 0x400>;
- clocks = <&rcc GPIOE>;
- st,bank-name = "GPIOE";
- status = "disabled";
- };
-
- gpiof: gpio@50007000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x5000 0x400>;
- clocks = <&rcc GPIOF>;
- st,bank-name = "GPIOF";
- status = "disabled";
- };
-
- gpiog: gpio@50008000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x6000 0x400>;
- clocks = <&rcc GPIOG>;
- st,bank-name = "GPIOG";
- status = "disabled";
- };
-
- gpioh: gpio@50009000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x7000 0x400>;
- clocks = <&rcc GPIOH>;
- st,bank-name = "GPIOH";
- status = "disabled";
- };
-
- gpioi: gpio@5000a000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x8000 0x400>;
- clocks = <&rcc GPIOI>;
- st,bank-name = "GPIOI";
- status = "disabled";
- };
-
- gpioj: gpio@5000b000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x9000 0x400>;
- clocks = <&rcc GPIOJ>;
- st,bank-name = "GPIOJ";
- status = "disabled";
- };
-
- gpiok: gpio@5000c000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xa000 0x400>;
- clocks = <&rcc GPIOK>;
- st,bank-name = "GPIOK";
- status = "disabled";
- };
-
- cec_pins_a: cec-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, AF4)>;
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- cec_pins_sleep_a: cec-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
- };
- };
-
- cec_pins_b: cec-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, AF5)>;
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- cec_pins_sleep_b: cec-sleep-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
- };
- };
-
- dcmi_pins_a: dcmi-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
- <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
- <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
- <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
- <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
- bias-disable;
- };
- };
-
- dcmi_sleep_pins_a: dcmi-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
- <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
- <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
- <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
- <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
- <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
- <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
- <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
- <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
- <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
- <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
- <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
- <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
- <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
- <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
- };
- };
-
- ethernet0_rgmii_pins_a: rgmii-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
- bias-disable;
- };
- };
-
- ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
- <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
- <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
- <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
- <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
- <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
- <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
- <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
- <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
- <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
- <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
- <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
- <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
- <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
- <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
- };
- };
-
- fmc_pins_a: fmc-0 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
- <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
- <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
- <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
- <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
- bias-pull-up;
- };
- };
-
- fmc_sleep_pins_a: fmc-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
- <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
- <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
- <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
- <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
- <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
- <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
- <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
- <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
- <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
- <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
- <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
- <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
- <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
- };
- };
-
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c1_pins_sleep_a: i2c1-1 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
- };
- };
-
- i2c1_pins_b: i2c1-2 {
- pins {
- pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c1_pins_sleep_b: i2c1-3 {
- pins {
- pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
- <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
- };
- };
-
- i2c2_pins_a: i2c2-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_pins_sleep_a: i2c2-1 {
- pins {
- pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
- <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
- };
- };
-
- i2c2_pins_b1: i2c2-2 {
- pins {
- pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_pins_sleep_b1: i2c2-3 {
- pins {
- pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
- };
- };
-
- i2c5_pins_a: i2c5-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
- <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c5_pins_sleep_a: i2c5-1 {
- pins {
- pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
- <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
-
- };
- };
-
- i2s2_pins_a: i2s2-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
- <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
- <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- i2s2_pins_sleep_a: i2s2-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
- <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
- <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
- };
- };
-
- ltdc_pins_a: ltdc-a-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
- <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- ltdc_pins_sleep_a: ltdc-a-1 {
- pins {
- pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
- <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
- <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
- <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
- <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
- <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
- <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
- <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
- <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
- <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
- <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
- <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
- <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
- <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
- <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
- <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
- <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
- <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
- <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
- <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
- <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
- <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
- <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
- <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
- <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
- };
- };
-
- ltdc_pins_b: ltdc-b-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
- <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
- <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
- <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
- <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
- <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
- <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- ltdc_pins_sleep_b: ltdc-b-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
- <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
- <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
- <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
- <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
- <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
- <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
- <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
- <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
- <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
- <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
- <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
- <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
- <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
- <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
- <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
- <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
- <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
- <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
- <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
- <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
- <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
- <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
- <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
- <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
- <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
- <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
- <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
- };
- };
-
- m_can1_pins_a: m-can1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
- slew-rate = <1>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
- bias-disable;
- };
- };
-
- m_can1_sleep_pins_a: m_can1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
- <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
- };
- };
-
- pwm2_pins_a: pwm2-0 {
- pins {
- pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm8_pins_a: pwm8-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- pwm12_pins_a: pwm12-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
- bias-pull-down;
- drive-push-pull;
- slew-rate = <0>;
- };
- };
-
- qspi_clk_pins_a: qspi-clk-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
- bias-disable;
- drive-push-pull;
- slew-rate = <3>;
- };
- };
-
- qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
- };
- };
-
- qspi_bk1_pins_a: qspi-bk1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
- <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
- <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
- <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
- <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
- };
- };
-
- qspi_bk2_pins_a: qspi-bk2-0 {
- pins1 {
- pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
- };
-
- qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
- <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
- <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
- <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
- <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
- };
- };
-
- sai2a_pins_a: sai2a-0 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
- <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
- <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai2a_sleep_pins_a: sai2a-1 {
- pins {
- pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
- <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
- <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
- <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
- };
- };
-
- sai2b_pins_a: sai2b-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
- <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
- <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_a: sai2b-1 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
- <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
- <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
- <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
- };
- };
-
- sai2b_pins_b: sai2b-2 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
- bias-disable;
- };
- };
-
- sai2b_sleep_pins_b: sai2b-3 {
- pins {
- pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
- };
- };
-
- sai4a_pins_a: sai4a-0 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
- slew-rate = <0>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sai4a_sleep_pins_a: sai4a-1 {
- pins {
- pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
- };
- };
-
- sdmmc1_b4_pins_a: sdmmc1-b4-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- };
-
- sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
- pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
- slew-rate = <3>;
- drive-push-pull;
- bias-disable;
- };
- pins2{
- pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
- slew-rate = <3>;
- drive-open-drain;
- bias-disable;
- };
- };
-
- sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
- <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
- <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
- <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
- <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
- <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
- };
- };
-
- sdmmc1_dir_pins_a: sdmmc1-dir-0 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
- slew-rate = <3>;
- drive-push-pull;
- bias-pull-up;
- };
- pins2{
- pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
- bias-pull-up;
- };
- };
-
- sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
- pins {
- pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
- <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
- <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
- <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
- };
- };
-
- spdifrx_pins_a: spdifrx-0 {
- pins {
- pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
- bias-disable;
- };
- };
-
- spdifrx_sleep_pins_a: spdifrx-1 {
- pins {
- pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
- };
- };
-
- uart4_pins_a: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_pins_b: uart4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart7_pins_a: uart7-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
- <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
- <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
- bias-disable;
- };
- };
- };
-
- pinctrl_z: pin-controller-z@54004000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stm32mp157-z-pinctrl";
- ranges = <0 0x54004000 0x400>;
- pins-are-numbered;
- interrupt-parent = <&exti>;
- st,syscfg = <&exti 0x60 0xff>;
-
- gpioz: gpio@54004000 {
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0 0x400>;
- clocks = <&rcc GPIOZ>;
- st,bank-name = "GPIOZ";
- st,bank-ioport = <11>;
- status = "disabled";
- };
-
- i2c2_pins_b2: i2c2-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c2_pins_sleep_b2: i2c2-1 {
- pins {
- pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
- };
- };
-
- i2c4_pins_a: i2c4-0 {
- pins {
- pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
- <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
- bias-disable;
- drive-open-drain;
- slew-rate = <0>;
- };
- };
-
- i2c4_pins_sleep_a: i2c4-1 {
- pins {
- pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
- <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
- };
- };
-
- spi1_pins_a: spi1-0 {
- pins1 {
- pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
- <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
- bias-disable;
- };
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/stm32mp157.dtsi b/arch/arm/boot/dts/stm32mp157.dtsi
new file mode 100644
index 0000000..54e73cc
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32mp153.dtsi"
+
+/ {
+ soc {
+ gpu: gpu@59000000 {
+ compatible = "vivante,gc";
+ reg = <0x59000000 0x800>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc GPU>, <&rcc GPU_K>;
+ clock-names = "bus" ,"core";
+ resets = <&rcc GPU_R>;
+ };
+
+ dsi: dsi@5a000000 {
+ compatible = "st,stm32-dsi";
+ reg = <0x5a000000 0x800>;
+ clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
+ clock-names = "pclk", "ref", "px_clk";
+ resets = <&rcc DSI_R>;
+ reset-names = "apb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-avenger96.dts
index 7b8c3f2..8a6eaca 100644
--- a/arch/arm/boot/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/boot/dts/stm32mp157a-avenger96.dts
@@ -2,323 +2,10 @@
/*
* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
-#include "stm32mp157c.dtsi"
-#include "stm32mp157xac-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-/ {
- model = "Arrow Electronics STM32MP157A Avenger96 board";
- compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
-
- aliases {
- ethernet0 = ðernet0;
- mmc0 = &sdmmc1;
- serial0 = &uart4;
- serial1 = &uart7;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@c0000000 {
- device_type = "memory";
- reg = <0xc0000000 0x40000000>;
- };
-
- led {
- compatible = "gpio-leds";
- led1 {
- label = "green:user1";
- gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led2 {
- label = "green:user2";
- gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
-
- led3 {
- label = "green:user3";
- gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc1";
- default-state = "off";
- };
-
- led4 {
- label = "green:user3";
- gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- default-state = "off";
- panic-indicator;
- };
-
- led5 {
- label = "yellow:wifi";
- gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tx";
- default-state = "off";
- };
-
- led6 {
- label = "blue:bt";
- gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "bluetooth-power";
- default-state = "off";
- };
- };
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
-
- phy0: ethernet-phy@7 {
- reg = <7>;
- };
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_b>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-};
-
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- st,main-control-register = <0x04>;
- st,vin-control-register = <0xc0>;
- st,usb-control-register = <0x30>;
-
- regulators {
- compatible = "st,stpmic1-regulators";
-
- ldo1-supply = <&v3v3>;
- ldo2-supply = <&v3v3>;
- ldo3-supply = <&vdd_ddr>;
- ldo5-supply = <&v3v3>;
- ldo6-supply = <&v3v3>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- st,mask_reset;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- vdda: ldo1 {
- regulator-name = "vdda";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO1 0>;
- interrupt-parent = <&pmic>;
- };
-
- v2v8: ldo2 {
- regulator-name = "v2v8";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- interrupts = <IT_CURLIM_LDO2 0>;
- interrupt-parent = <&pmic>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- interrupts = <IT_CURLIM_LDO4 0>;
- interrupt-parent = <&pmic>;
- };
-
- vdd_sd: ldo5 {
- regulator-name = "vdd_sd";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- interrupt-parent = <&pmic>;
- regulator-boot-on;
- };
-
- v1v8: ldo6 {
- regulator-name = "v1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- interrupts = <IT_CURLIM_LDO6 0>;
- interrupt-parent = <&pmic>;
- regulator-enable-ramp-delay = <300000>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- interrupt-parent = <&pmic>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- interrupt-parent = <&pmic>;
- regulator-active-discharge;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- interrupt-parent = <&pmic>;
- regulator-active-discharge;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
- interrupt-names = "onkey-falling", "onkey-rising";
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,sig-dir;
- st,neg-edge;
- st,use-ckin;
- bus-width = <4>;
- vmmc-supply = <&vdd_sd>;
- status = "okay";
-};
-
-&uart4 {
- /* On Low speed expansion header */
- label = "LS-UART1";
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_b>;
- status = "okay";
-};
-
-&uart7 {
- /* On Low speed expansion header */
- label = "LS-UART0";
- pinctrl-names = "default";
- pinctrl-0 = <&uart7_pins_a>;
- status = "okay";
-};
+/* This DT is here only for backward compatibility */
+#include "stm32mp157a-dhcor-avenger96.dts"
diff --git a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts
new file mode 100644
index 0000000..2e3c9fb
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ *
+ * DHCOR STM32MP1 variant:
+ * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG
+ * DHCOR PCB number: 586-100 or newer
+ * Avenger96 PCB number: 588-200 or newer
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15xx-dhcor-som.dtsi"
+#include "stm32mp15xx-dhcor-avenger96.dtsi"
+
+/ {
+ model = "Arrow Electronics STM32MP157A Avenger96 board";
+ compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som",
+ "st,stm32mp157";
+};
+
+&m_can1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_b>;
+ pinctrl-1 = <&m_can1_sleep_pins_b>;
+ status = "disabled";
+};
+
+&m_can2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can2_pins_a>;
+ pinctrl-1 = <&m_can2_sleep_pins_a>;
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts
index 0615d1c..4c8be9c 100644
--- a/arch/arm/boot/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts
@@ -6,10 +6,10 @@
/dts-v1/;
-#include "stm32mp157c.dtsi"
-#include "stm32mp157xac-pinctrl.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
+#include "stm32mp157.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include "stm32mp15xx-dkx.dtsi"
/ {
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
@@ -18,434 +18,11 @@
aliases {
ethernet0 = ðernet0;
serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
-
- memory@c0000000 {
- reg = <0xc0000000 0x20000000>;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mcuram2: mcuram2@10000000 {
- compatible = "shared-dma-pool";
- reg = <0x10000000 0x40000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@10040000 {
- compatible = "shared-dma-pool";
- reg = <0x10040000 0x1000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@10041000 {
- compatible = "shared-dma-pool";
- reg = <0x10041000 0x1000>;
- no-map;
- };
-
- vdev0buffer: vdev0buffer@10042000 {
- compatible = "shared-dma-pool";
- reg = <0x10042000 0x4000>;
- no-map;
- };
-
- mcuram: mcuram@30000000 {
- compatible = "shared-dma-pool";
- reg = <0x30000000 0x40000>;
- no-map;
- };
-
- retram: retram@38000000 {
- compatible = "shared-dma-pool";
- reg = <0x38000000 0x10000>;
- no-map;
- };
-
- gpu_reserved: gpu@d4000000 {
- reg = <0xd4000000 0x4000000>;
- no-map;
- };
- };
-
- led {
- compatible = "gpio-leds";
- blue {
- label = "heartbeat";
- gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-
- sound {
- compatible = "audio-graph-card";
- label = "STM32MP1-DK";
- routing =
- "Playback" , "MCLK",
- "Capture" , "MCLK",
- "MICL" , "Mic Bias";
- dais = <&sai2a_port &sai2b_port>;
- status = "okay";
- };
-};
-
-&cec {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&cec_pins_b>;
- pinctrl-1 = <&cec_pins_sleep_b>;
- status = "okay";
-};
-
-ðernet0 {
- status = "okay";
- pinctrl-0 = <ðernet0_rgmii_pins_a>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
- pinctrl-names = "default", "sleep";
- phy-mode = "rgmii-id";
- max-speed = <1000>;
- phy-handle = <&phy0>;
-
- mdio0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
- };
-};
-
-&gpu {
- contiguous-area = <&gpu_reserved>;
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c1_pins_a>;
- pinctrl-1 = <&i2c1_pins_sleep_a>;
- i2c-scl-rising-time-ns = <100>;
- i2c-scl-falling-time-ns = <7>;
- status = "okay";
- /delete-property/dmas;
- /delete-property/dma-names;
-
- hdmi-transmitter@39 {
- compatible = "sil,sii9022";
- reg = <0x39>;
- iovcc-supply = <&v3v3_hdmi>;
- cvcc12-supply = <&v1v2_hdmi>;
- reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpiog>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-1 = <<dc_pins_sleep_a>;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- sii9022_in: endpoint {
- remote-endpoint = <<dc_ep0_out>;
- };
- };
- };
- };
-
- cs42l51: cs42l51@4a {
- compatible = "cirrus,cs42l51";
- reg = <0x4a>;
- #sound-dai-cells = <0>;
- VL-supply = <&v3v3>;
- VD-supply = <&v1v8_audio>;
- VA-supply = <&v1v8_audio>;
- VAHP-supply = <&v1v8_audio>;
- reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
- clocks = <&sai2a>;
- clock-names = "MCLK";
- status = "okay";
-
- cs42l51_port: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cs42l51_tx_endpoint: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&sai2a_endpoint>;
- frame-master;
- bitclock-master;
- };
-
- cs42l51_rx_endpoint: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&sai2b_endpoint>;
- frame-master;
- bitclock-master;
- };
- };
- };
-};
-
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_pins_a>;
- i2c-scl-rising-time-ns = <185>;
- i2c-scl-falling-time-ns = <20>;
- status = "okay";
- /* spare dmas for other usage */
- /delete-property/dmas;
- /delete-property/dma-names;
-
- pmic: stpmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- status = "okay";
-
- regulators {
- compatible = "st,stpmic1-regulators";
- ldo1-supply = <&v3v3>;
- ldo3-supply = <&vdd_ddr>;
- ldo6-supply = <&v3v3>;
- pwr_sw1-supply = <&bst_out>;
- pwr_sw2-supply = <&bst_out>;
-
- vddcore: buck1 {
- regulator-name = "vddcore";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd_ddr: buck2 {
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- st,mask-reset;
- regulator-initial-mode = <0>;
- regulator-over-current-protection;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-over-current-protection;
- regulator-initial-mode = <0>;
- };
-
- v1v8_audio: ldo1 {
- regulator-name = "v1v8_audio";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO1 0>;
- };
-
- v3v3_hdmi: ldo2 {
- regulator-name = "v3v3_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO2 0>;
- };
-
- vtt_ddr: ldo3 {
- regulator-name = "vtt_ddr";
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <750000>;
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- vdd_usb: ldo4 {
- regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- interrupts = <IT_CURLIM_LDO4 0>;
- };
-
- vdda: ldo5 {
- regulator-name = "vdda";
- regulator-min-microvolt = <2900000>;
- regulator-max-microvolt = <2900000>;
- interrupts = <IT_CURLIM_LDO5 0>;
- regulator-boot-on;
- };
-
- v1v2_hdmi: ldo6 {
- regulator-name = "v1v2_hdmi";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- interrupts = <IT_CURLIM_LDO6 0>;
- };
-
- vref_ddr: vref_ddr {
- regulator-name = "vref_ddr";
- regulator-always-on;
- regulator-over-current-protection;
- };
-
- bst_out: boost {
- regulator-name = "bst_out";
- interrupts = <IT_OCP_BOOST 0>;
- };
-
- vbus_otg: pwr_sw1 {
- regulator-name = "vbus_otg";
- interrupts = <IT_OCP_OTG 0>;
- };
-
- vbus_sw: pwr_sw2 {
- regulator-name = "vbus_sw";
- interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
- };
- };
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
- status = "okay";
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- status = "disabled";
- };
- };
-};
-
-&ipcc {
- status = "okay";
-};
-
-&iwdg2 {
- timeout-sec = <32>;
- status = "okay";
-};
-
-<dc {
- status = "okay";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ltdc_ep0_out: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&sii9022_in>;
- };
- };
-};
-
-&m4_rproc {
- memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
- <&vdev0vring1>, <&vdev0buffer>;
- mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
- mbox-names = "vq0", "vq1", "shutdown";
- interrupt-parent = <&exti>;
- interrupts = <68 1>;
- status = "okay";
-};
-
-&rng1 {
- status = "okay";
-};
-
-&rtc {
- status = "okay";
-};
-
-&sai2 {
- clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
- clock-names = "pclk", "x8k", "x11k";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
- pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
- status = "okay";
-
- sai2a: audio-controller@4400b004 {
- #clock-cells = <0>;
- dma-names = "tx";
- clocks = <&rcc SAI2_K>;
- clock-names = "sai_ck";
- status = "okay";
-
- sai2a_port: port {
- sai2a_endpoint: endpoint {
- remote-endpoint = <&cs42l51_tx_endpoint>;
- format = "i2s";
- mclk-fs = <256>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <32>;
- };
- };
- };
-
- sai2b: audio-controller@4400b024 {
- dma-names = "rx";
- st,sync = <&sai2a 2>;
- clocks = <&rcc SAI2_K>, <&sai2a>;
- clock-names = "sai_ck", "MCLK";
- status = "okay";
-
- sai2b_port: port {
- sai2b_endpoint: endpoint {
- remote-endpoint = <&cs42l51_rx_endpoint>;
- format = "i2s";
- mclk-fs = <256>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <32>;
- };
- };
- };
-};
-
-&sdmmc1 {
- pinctrl-names = "default", "opendrain", "sleep";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
- pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- broken-cd;
- st,neg-edge;
- bus-width = <4>;
- vmmc-supply = <&v3v3>;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_pins_a>;
- status = "okay";
};
diff --git a/arch/arm/boot/dts/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/stm32mp157a-iot-box.dts
new file mode 100644
index 0000000..70f394b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-iot-box.dts
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Manivannan Sadhasivam
+ */
+
+/dts-v1/;
+#include "stm32mp157a-stinger96.dtsi"
+
+/ {
+ model = "Shiratech STM32MP157A IoT Box";
+ compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157";
+
+ wlan_pwr: regulator-wlan {
+ compatible = "regulator-fixed";
+
+ regulator-name = "wl-reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&i2c2 {
+ ccs811@5b {
+ compatible = "ams,ccs811";
+ reg = <0x5b>;
+ wakeup-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
+ };
+};
+
+/* WiFi */
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_b>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
+ broken-cd;
+ non-removable;
+ st,neg-edge;
+ bus-width = <1>;
+ vmmc-supply = <&wlan_pwr>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+/* Bluetooth */
+&uart4 {
+ /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */
+ /delete-property/st,hw-flow-ctrl;
+ cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ bluetooth {
+ shutdown-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <115200>;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dts b/arch/arm/boot/dts/stm32mp157a-stinger96.dts
new file mode 100644
index 0000000..249a538
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Manivannan Sadhasivam
+ */
+
+/dts-v1/;
+#include "stm32mp157a-stinger96.dtsi"
+
+/ {
+ model = "Shiratech STM32MP157A Stinger96 board";
+ compatible = "shiratech,stm32mp157a-stinger96", "st,stm32mp157";
+};
diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
new file mode 100644
index 0000000..4dd138d
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Manivannan Sadhasivam
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ aliases {
+ mmc0 = &sdmmc1;
+ serial0 = &uart4;
+ serial1 = &uart7;
+ serial2 = &usart2;
+ spi0 = &spi4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x10000000>;
+ };
+
+ led {
+ compatible = "gpio-leds";
+
+ led1 {
+ label = "green:user1";
+ gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "green:user2";
+ gpios = <&gpioh 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "green:user3";
+ gpios = <&gpioh 2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "green:user4";
+ gpios = <&gpiof 12 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ panic-indicator;
+ };
+ };
+
+ sd_switch: regulator-sd_switch {
+ compatible = "regulator-gpio";
+ regulator-name = "sd_switch";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-type = "voltage";
+ regulator-always-on;
+
+ gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1>,
+ <2900000 0x0>;
+ };
+};
+
+/* Only headless mode is supported */
+&gpu {
+ status = "disabled";
+};
+
+/* LS-I2C0 */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ i2c-scl-rising-time-ns = <1000>;
+ i2c-scl-falling-time-ns = <300>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+
+ ldo1-supply = <&v3v3>;
+ ldo2-supply = <&v3v3>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo5-supply = <&v3v3>;
+ ldo6-supply = <&v3v3>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ vdda: ldo1 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ v2v9: ldo2 {
+ regulator-name = "v2v9";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdd_sd: ldo5 {
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ regulator-boot-on;
+ };
+
+ v1v8: ldo6 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ regulator-active-discharge = <1>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
+ broken-cd;
+ disable-wp;
+ st,sig-dir;
+ st,neg-edge;
+ st,use-ckin;
+ bus-width = <4>;
+ vmmc-supply = <&vdd_sd>;
+ vqmmc-supply = <&sd_switch>;
+ status = "okay";
+};
+
+/* LS-SPI0 */
+&spi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi4_pins_a>;
+ cs-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+/* BG96 */
+&usart2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usart2_pins_b>;
+ pinctrl-1 = <&usart2_sleep_pins_b>;
+ st,hw-flow-ctrl;
+ status = "okay";
+};
+
+/* LS-UART0 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_c>;
+ st,hw-flow-ctrl;
+ status = "okay";
+};
+
+/* Debug console */
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_b>;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ phy-names = "usb";
+ status = "okay";
+};
+
+&usbotg_hs {
+ dr_mode = "peripheral";
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ phy-names = "usb2-phy";
+ phys = <&usbphyc_port1 0>;
+ vbus-supply = <&vbus_otg>;
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts
new file mode 100644
index 0000000..d3b8138
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
+ *
+ * DHCOM STM32MP1 variant:
+ * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2
+ * DHCOM PCB number: 587-200 or newer
+ * PDK2 PCB number: 516-400 or newer
+ */
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15xx-dhcom-som.dtsi"
+#include "stm32mp15xx-dhcom-pdk2.dtsi"
+
+/ {
+ model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)";
+ compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som",
+ "st,stm32mp157";
+};
+
+&m_can1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_a>;
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts
index 20ea601..0456365 100644
--- a/arch/arm/boot/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
@@ -6,31 +6,34 @@
/dts-v1/;
-#include "stm32mp157a-dk1.dts"
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include "stm32mp15xx-dkx.dtsi"
/ {
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
- reg18: reg18 {
- compatible = "regulator-fixed";
- regulator-name = "reg18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
+ aliases {
+ ethernet0 = ðernet0;
+ serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
+ serial3 = &usart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
};
};
&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
status = "okay";
phy-dsi-supply = <®18>;
ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
port@0 {
reg = <0>;
dsi_in: endpoint {
@@ -61,16 +64,34 @@
};
};
+&i2c1 {
+ touchscreen@38 {
+ compatible = "focaltech,ft6236";
+ reg = <0x38>;
+ interrupts = <2 2>;
+ interrupt-parent = <&gpiof>;
+ interrupt-controller;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ status = "okay";
+ };
+};
+
<dc {
status = "okay";
port {
- #address-cells = <1>;
- #size-cells = <0>;
-
ltdc_ep1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in>;
};
};
};
+
+&usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_c>;
+ pinctrl-1 = <&usart2_sleep_pins_c>;
+ pinctrl-2 = <&usart2_idle_pins_c>;
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
index 1d426ea..2e77cce 100644
--- a/arch/arm/boot/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -5,8 +5,10 @@
*/
/dts-v1/;
-#include "stm32mp157c.dtsi"
-#include "stm32mp157xaa-pinctrl.dtsi"
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
@@ -74,22 +76,6 @@
serial0 = &uart4;
};
- reg11: reg11 {
- compatible = "regulator-fixed";
- regulator-name = "reg11";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- reg18: reg18 {
- compatible = "regulator-fixed";
- regulator-name = "reg18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";
regulator-name = "sd_switch";
@@ -100,7 +86,45 @@
gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
- states = <1800000 0x1 2900000 0x0>;
+ states = <1800000 0x1>,
+ <2900000 0x0>;
+ };
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&adc {
+ /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
+ pinctrl-0 = <&adc1_in6_pins_a>;
+ pinctrl-names = "default";
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vdda>;
+ status = "disabled";
+ adc1: adc@0 {
+ st,adc-channels = <0 1 6>;
+ /* 16.5 ck_cycles sampling time */
+ st,min-sample-time-nsecs = <400>;
+ status = "okay";
+ };
+};
+
+&dac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
+ vref-supply = <&vdda>;
+ status = "disabled";
+ dac1: dac@1 {
+ status = "okay";
+ };
+ dac2: dac@2 {
+ status = "okay";
};
};
@@ -110,14 +134,15 @@
&gpu {
contiguous-area = <&gpu_reserved>;
- status = "okay";
};
&i2c4 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_pins_a>;
+ pinctrl-1 = <&i2c4_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
@@ -133,17 +158,24 @@
regulators {
compatible = "st,stpmic1-regulators";
+ buck1-supply = <&vin>;
+ buck2-supply = <&vin>;
+ buck3-supply = <&vin>;
+ buck4-supply = <&vin>;
ldo1-supply = <&v3v3>;
ldo2-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
+ ldo4-supply = <&vin>;
ldo5-supply = <&v3v3>;
ldo6-supply = <&v3v3>;
+ vref_ddr-supply = <&vin>;
+ boost-supply = <&vin>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
vddcore: buck1 {
regulator-name = "vddcore";
- regulator-min-microvolt = <800000>;
+ regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
@@ -202,8 +234,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@@ -225,7 +255,6 @@
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
- regulator-over-current-protection;
};
bst_out: boost {
@@ -241,7 +270,7 @@
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
@@ -279,6 +308,11 @@
status = "okay";
};
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
&rng1 {
status = "okay";
};
@@ -292,13 +326,34 @@
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
- broken-cd;
+ cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
st,sig-dir;
st,neg-edge;
st,use-ckin;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&sd_switch>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&vdd>;
+ mmc-ddr-3_3v;
status = "okay";
};
@@ -313,11 +368,17 @@
};
&uart4 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
status = "okay";
};
+&usbotg_hs {
+ vbus-supply = <&vbus_otg>;
+};
+
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <®11>;
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 91fc0a3..a55e80c 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -19,6 +19,7 @@
aliases {
serial0 = &uart4;
+ serial1 = &usart3;
ethernet0 = ðernet0;
};
@@ -32,7 +33,6 @@
joystick {
compatible = "gpio-keys";
- #size-cells = <0>;
pinctrl-0 = <&joystick_pins>;
pinctrl-names = "default";
button-0 {
@@ -99,15 +99,10 @@
};
&dsi {
- #address-cells = <1>;
- #size-cells = <0>;
phy-dsi-supply = <®18>;
status = "okay";
ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
port@0 {
reg = <0>;
dsi_in: endpoint {
@@ -142,7 +137,7 @@
ðernet0 {
status = "okay";
pinctrl-0 = <ðernet0_rgmii_pins_a>;
- pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
+ pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
@@ -163,20 +158,23 @@
pinctrl-0 = <&fmc_pins_a>;
pinctrl-1 = <&fmc_sleep_pins_a>;
status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- nand@0 {
- reg = <0>;
- nand-on-flash-bbt;
- #address-cells = <1>;
- #size-cells = <1>;
+ nand-controller@4,0 {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
};
};
&i2c2 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_pins_a>;
+ pinctrl-1 = <&i2c2_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
@@ -211,7 +209,7 @@
interrupt-parent = <&gpioi>;
vdd-supply = <&v3v3>;
- stmfx_pinctrl: stmfx-pin-controller {
+ stmfx_pinctrl: pinctrl {
compatible = "st,stmfx-0300-pinctrl";
gpio-controller;
#gpio-cells = <2>;
@@ -219,7 +217,7 @@
#interrupt-cells = <2>;
gpio-ranges = <&stmfx_pinctrl 0 0 24>;
- joystick_pins: joystick {
+ joystick_pins: joystick-pins {
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
bias-pull-down;
};
@@ -228,8 +226,9 @@
};
&i2c5 {
- pinctrl-names = "default";
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_pins_a>;
+ pinctrl-1 = <&i2c5_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
@@ -239,9 +238,6 @@
status = "okay";
port {
- #address-cells = <1>;
- #size-cells = <0>;
-
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&dsi_in>;
@@ -284,6 +280,18 @@
};
};
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "disabled";
+};
+
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
@@ -297,7 +305,8 @@
status = "disabled";
pwm {
pinctrl-0 = <&pwm2_pins_a>;
- pinctrl-names = "default";
+ pinctrl-1 = <&pwm2_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
status = "okay";
};
timer@1 {
@@ -311,7 +320,8 @@
status = "disabled";
pwm {
pinctrl-0 = <&pwm8_pins_a>;
- pinctrl-names = "default";
+ pinctrl-1 = <&pwm8_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
status = "okay";
};
timer@7 {
@@ -325,7 +335,8 @@
status = "disabled";
pwm {
pinctrl-0 = <&pwm12_pins_a>;
- pinctrl-names = "default";
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
status = "okay";
};
timer@11 {
@@ -333,14 +344,28 @@
};
};
+&usart3 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart3_pins_b>;
+ pinctrl-1 = <&usart3_sleep_pins_b>;
+ pinctrl-2 = <&usart3_idle_pins_b>;
+ /*
+ * HW flow control USART3_RTS is optional, and isn't default wired to
+ * the connector. SB23 needs to be soldered in order to use it, and R77
+ * (ETH_CLK) should be removed.
+ */
+ uart-has-rtscts;
+ status = "disabled";
+};
+
&usbh_ehci {
phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
&usbotg_hs {
- dr_mode = "peripheral";
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
status = "okay";
diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
new file mode 100644
index 0000000..1e5333f
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
+/*
+ * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2020 Ahmad Fatoum, Pengutronix
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xx-osd32.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Linux Automation MC-1 board";
+ compatible = "lxa,stm32mp157c-mc1", "st,stm32mp157";
+
+ aliases {
+ ethernet0 = ðernet0;
+ mmc0 = &sdmmc1;
+ mmc1 = &sdmmc2;
+ serial0 = &uart4;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&backlight_pwm 1 100000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 31 63 95 127 159 191 223 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_5v2>; /* 3V3_BACKLIGHT */
+ };
+
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ led-act {
+ compatible = "gpio-leds";
+
+ led-green {
+ label = "mc1:green:act";
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ led-rgb {
+ compatible = "pwm-leds";
+
+ led-red {
+ label = "mc1:red:rgb";
+ pwms = <&leds_pwm 1 1000000 0>;
+ max-brightness = <255>;
+ active-low;
+ };
+
+ led-green {
+ label = "mc1:green:rgb";
+ pwms = <&leds_pwm 2 1000000 0>;
+ max-brightness = <255>;
+ active-low;
+ };
+
+ led-blue {
+ label = "mc1:blue:rgb";
+ pwms = <&leds_pwm 3 1000000 0>;
+ max-brightness = <255>;
+ active-low;
+ };
+ };
+
+ panel: panel {
+ compatible = "edt,etm0700g0edh6", "simple-panel";
+ backlight = <&backlight>;
+ enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_3v3>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+ };
+
+ reg_3v3: regulator_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&v3v3>;
+ };
+
+ /* supplied by either debug board or PoE */
+ reg_5v2: regulator_5v2 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V2";
+ regulator-min-microvolt = <5200000>;
+ regulator-max-microvolt = <5200000>;
+ regulator-always-on;
+ };
+};
+
+ðernet0 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <ðernet0_rgmii_pins_b>;
+ pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio0 {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@3 { /* KSZ9031RN */
+ reg = <3>;
+ reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */
+ interrupt-parent = <&gpioa>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <300>;
+ micrel,force-master;
+ };
+ };
+};
+
+&gpioz {
+ gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", "",
+ "HWID4", "HWID5";
+};
+
+&i2c5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_b>;
+ pinctrl-1 = <&i2c5_sleep_pins_b>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ interrupt-parent = <&gpiod>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; /* TOUCH_INT# */
+ vcc-supply = <®_3v3>;
+ reg = <0x38>;
+ reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; /* TOUCH_RESET# */
+ touchscreen-size-x = <1792>;
+ touchscreen-size-y = <1024>;
+ wakeup-source;
+ };
+};
+
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_c>;
+ pinctrl-1 = <<dc_sleep_pins_c>;
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+ };
+};
+
+&pmic {
+ regulators {
+ buck4-supply = <®_5v2>; /* VIN */
+ ldo2-supply = <®_5v2>; /* PMIC_LDO25IN */
+ ldo5-supply = <®_5v2>; /* PMIC_LDO25IN */
+ boost-supply = <®_5v2>; /* PMIC_BSTIN */
+ pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ bus-width = <4>;
+ cd-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ no-1-8-v;
+ st,neg-edge;
+ vmmc-supply = <®_3v3>;
+ status = "okay";
+};
+
+&sdmmc1_b4_pins_a {
+ /*
+ * board lacks external pull-ups on SDMMC lines. Class 10 SD refuses to
+ * work, thus enable internal pull-ups.
+ */
+ pins1 {
+ /delete-property/ bias-disable;
+ bias-pull-up;
+ };
+ pins2 {
+ /delete-property/ bias-disable;
+ bias-pull-up;
+ };
+};
+
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>;
+ bus-width = <8>;
+ mmc-ddr-3_3v;
+ no-1-8-v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <®_3v3>;
+ status = "okay";
+};
+
+&timers3 {
+ status = "okay";
+
+ backlight_pwm: pwm {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pwm3_pins_b>;
+ pinctrl-1 = <&pwm3_sleep_pins_b>;
+ status = "okay";
+ };
+};
+
+&timers5 {
+ status = "okay";
+
+ leds_pwm: pwm {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pwm5_pins_b>;
+ pinctrl-1 = <&pwm5_sleep_pins_b>;
+ status = "okay";
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
new file mode 100644
index 0000000..2d94610
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ model = "Seeed Studio Odyssey-STM32MP157C SOM";
+ compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mcuram2: mcuram2@10000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@10040000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x1000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@10041000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10041000 0x1000>;
+ no-map;
+ };
+
+ vdev0buffer: vdev0buffer@10042000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x4000>;
+ no-map;
+ };
+
+ mcuram: mcuram@30000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram: retram@38000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+
+ gpu_reserved: gpu@d4000000 {
+ reg = <0xd4000000 0x4000000>;
+ no-map;
+ };
+ };
+
+ led {
+ compatible = "gpio-leds";
+ led-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+ ldo1-supply = <&v3v3>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo6-supply = <&v3v3>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ v1v8_audio: ldo1 {
+ regulator-name = "v1v8_audio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ v3v3_hdmi: ldo2 {
+ regulator-name = "v3v3_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdda: ldo5 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ regulator-boot-on;
+ };
+
+ v1v2_hdmi: ldo6 {
+ regulator-name = "v1v2_hdmi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+};
+
+&ipcc {
+ status = "okay";
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&m4_rproc {
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>;
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ interrupt-parent = <&exti>;
+ interrupts = <68 1>;
+ status = "okay";
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&vdd>;
+ mmc-ddr-3_3v;
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
new file mode 100644
index 0000000..be1dd5e
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-odyssey-som.dtsi"
+
+/ {
+ model = "Seeed Studio Odyssey-STM32MP157C Board";
+ compatible = "seeed,stm32mp157c-odyssey",
+ "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
+
+ aliases {
+ ethernet0 = ðernet0;
+ serial0 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ðernet0 {
+ status = "okay";
+ pinctrl-0 = <ðernet0_rgmii_pins_a>;
+ pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii-id";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+ assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>;
+ assigned-clock-parents = <&rcc PLL4_P>;
+ assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
+ st,eth-clk-sel;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@7 { /* KSZ9031RN */
+ reg = <7>;
+ reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <300>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <100>;
+ i2c-scl-falling-time-ns = <7>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi
deleted file mode 100644
index 875adf5..0000000
--- a/arch/arm/boot/dts/stm32mp157xaa-pinctrl.dtsi
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
- */
-
-#include "stm32mp157-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller@50002000 {
- st,package = <STM32MP_PKG_AA>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@5000a000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 128 16>;
- };
-
- gpioj: gpio@5000b000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 144 16>;
- };
-
- gpiok: gpio@5000c000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl 0 160 8>;
- };
- };
-
- pinctrl_z: pin-controller-z@54004000 {
- st,package = <STM32MP_PKG_AA>;
-
- gpioz: gpio@54004000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl_z 0 400 8>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi
deleted file mode 100644
index 961fa12..0000000
--- a/arch/arm/boot/dts/stm32mp157xab-pinctrl.dtsi
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
- */
-
-#include "stm32mp157-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller@50002000 {
- st,package = <STM32MP_PKG_AB>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <6>;
- gpio-ranges = <&pinctrl 6 86 6>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl 6 102 10>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <2>;
- gpio-ranges = <&pinctrl 0 112 2>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi
deleted file mode 100644
index 26600f1..0000000
--- a/arch/arm/boot/dts/stm32mp157xac-pinctrl.dtsi
+++ /dev/null
@@ -1,78 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
- */
-
-#include "stm32mp157-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller@50002000 {
- st,package = <STM32MP_PKG_AC>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 80 16>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 96 16>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 112 16>;
- };
-
- gpioi: gpio@5000a000 {
- status = "okay";
- ngpios = <12>;
- gpio-ranges = <&pinctrl 0 128 12>;
- };
- };
-
- pinctrl_z: pin-controller-z@54004000 {
- st,package = <STM32MP_PKG_AC>;
-
- gpioz: gpio@54004000 {
- status = "okay";
- ngpios = <8>;
- gpio-ranges = <&pinctrl_z 0 400 8>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi
deleted file mode 100644
index 910113f..0000000
--- a/arch/arm/boot/dts/stm32mp157xad-pinctrl.dtsi
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
- * Author: Alexandre Torgue <alexandre.torgue@st.com>
- */
-
-#include "stm32mp157-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller@50002000 {
- st,package = <STM32MP_PKG_AD>;
-
- gpioa: gpio@50002000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 0 16>;
- };
-
- gpiob: gpio@50003000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 16 16>;
- };
-
- gpioc: gpio@50004000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 32 16>;
- };
-
- gpiod: gpio@50005000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 48 16>;
- };
-
- gpioe: gpio@50006000 {
- status = "okay";
- ngpios = <16>;
- gpio-ranges = <&pinctrl 0 64 16>;
- };
-
- gpiof: gpio@50007000 {
- status = "okay";
- ngpios = <6>;
- gpio-ranges = <&pinctrl 6 86 6>;
- };
-
- gpiog: gpio@50008000 {
- status = "okay";
- ngpios = <10>;
- gpio-ranges = <&pinctrl 6 102 10>;
- };
-
- gpioh: gpio@50009000 {
- status = "okay";
- ngpios = <2>;
- gpio-ranges = <&pinctrl 0 112 2>;
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/stm32mp15xc.dtsi
new file mode 100644
index 0000000..b06a55a
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xc.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+/ {
+ soc {
+ cryp1: cryp@54001000 {
+ compatible = "st,stm32mp1-cryp";
+ reg = <0x54001000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi
new file mode 100644
index 0000000..e4d287d
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ aliases {
+ serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart8;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&adc {
+ status = "disabled";
+};
+
+&dac {
+ status = "disabled";
+};
+
+&gpiob {
+ /*
+ * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
+ * GPIO line, however the STM32 UART driver assumes RX happens
+ * during TX anyway and that it only controls drive enable DE
+ * line. Hence, the RX is always enabled here.
+ */
+ rs485-rx-en {
+ gpio-hog;
+ gpios = <8 0>;
+ output-low;
+ line-name = "rs485-rx-en";
+ };
+};
+
+&gpiod {
+ gpio-line-names = "", "", "", "",
+ "", "", "", "",
+ "", "", "", "Out1",
+ "Out2", "", "", "";
+};
+
+&gpioi {
+ gpio-line-names = "In1", "", "", "",
+ "", "", "", "",
+ "In2", "", "", "",
+ "", "", "", "";
+
+ /*
+ * NOTE: The USB Hub on the DRC02 needs a reset signal to be
+ * pulled high in order to be detected by the USB Controller.
+ * This signal should be handled by USB power sequencing in
+ * order to reset the Hub when USB bus is powered down, but
+ * so far there is no such functionality.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <2 0>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c4 {
+ touchscreen@49 {
+ status = "disabled";
+ };
+};
+
+&i2c5 { /* TP7/TP8 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&sdmmc3 {
+ /*
+ * On DRC02, the SoM does not have SDIO WiFi. The pins
+ * are used for on-board microSD slot instead.
+ */
+ /delete-property/broken-cd;
+ cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
+ disable-wp;
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>;
+ cs-gpios = <&gpioz 3 0>;
+ /* Use PIO for the display */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled"; /* Enable once there is display driver */
+ /*
+ * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
+ * also connected to the display board connector.
+ */
+};
+
+&usart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usart3_pins_a>;
+ status = "okay";
+};
+
+/*
+ * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
+ * however the STM32MP1 pinmux cannot map them to UART4 .
+ */
+
+&uart8 { /* RS485 */
+ linux,rs485-enabled-at-boot-time;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8_pins_a>;
+ rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
new file mode 100644
index 0000000..fd0cd10
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ aliases {
+ serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart8;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clk_ext_audio_codec: clock-codec {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ display_bl: display-bl {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
+ default-brightness-level = <8>;
+ enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ /*
+ * The EXTi IRQ line 3 is shared with ethernet,
+ * so mark this as polled GPIO key.
+ */
+ button-0 {
+ label = "TA1-GPIO-A";
+ linux,code = <KEY_A>;
+ gpios = <&gpiof 3 GPIO_ACTIVE_LOW>;
+ };
+
+ /*
+ * The EXTi IRQ line 6 is shared with touchscreen,
+ * so mark this as polled GPIO key.
+ */
+ button-1 {
+ label = "TA2-GPIO-B";
+ linux,code = <KEY_B>;
+ gpios = <&gpiod 6 GPIO_ACTIVE_LOW>;
+ };
+
+ /*
+ * The EXTi IRQ line 0 is shared with PMIC,
+ * so mark this as polled GPIO key.
+ */
+ button-2 {
+ label = "TA3-GPIO-C";
+ linux,code = <KEY_C>;
+ gpios = <&gpiog 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-3 {
+ label = "TA4-GPIO-D";
+ linux,code = <KEY_D>;
+ gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+ };
+
+ led {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "green:led5";
+ gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ status = "disabled";
+ };
+
+ led-1 {
+ label = "green:led6";
+ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-2 {
+ label = "green:led7";
+ gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-3 {
+ label = "green:led8";
+ gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ panel {
+ compatible = "edt,etm0700g0edh6";
+ backlight = <&display_bl>;
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcd_display_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ routing =
+ "MIC_IN", "Capture",
+ "Capture", "Mic Bias",
+ "Playback", "HP_OUT";
+ dais = <&sai2a_port &sai2b_port>;
+ status = "okay";
+ };
+};
+
+&cec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cec_pins_a>;
+ status = "okay";
+};
+
+&i2c2 { /* Header X22 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+};
+
+&i2c5 { /* Header X21 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clk_ext_audio_codec>;
+ VDDA-supply = <&v3v3>;
+ VDDIO-supply = <&vdd>;
+
+ sgtl5000_port: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgtl5000_tx_endpoint: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&sai2a_endpoint>;
+ frame-master = <&sgtl5000_tx_endpoint>;
+ bitclock-master = <&sgtl5000_tx_endpoint>;
+ };
+
+ sgtl5000_rx_endpoint: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&sai2b_endpoint>;
+ frame-master = <&sgtl5000_rx_endpoint>;
+ bitclock-master = <&sgtl5000_rx_endpoint>;
+ };
+ };
+
+ };
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&gpioc>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
+ };
+};
+
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_b>;
+ pinctrl-1 = <<dc_sleep_pins_b>;
+ status = "okay";
+
+ port {
+ lcd_display_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
+};
+
+&sai2 {
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "x8k", "x11k";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>;
+ pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>;
+ status = "okay";
+
+ sai2a: audio-controller@4400b004 {
+ #clock-cells = <0>;
+ dma-names = "tx";
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ status = "okay";
+
+ sai2a_port: port {
+ sai2a_endpoint: endpoint {
+ remote-endpoint = <&sgtl5000_tx_endpoint>;
+ format = "i2s";
+ mclk-fs = <512>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+ };
+ };
+
+ sai2b: audio-controller@4400b024 {
+ dma-names = "rx";
+ st,sync = <&sai2a 2>;
+ clocks = <&rcc SAI2_K>, <&sai2a>;
+ clock-names = "sai_ck", "MCLK";
+ status = "okay";
+
+ sai2b_port: port {
+ sai2b_endpoint: endpoint {
+ remote-endpoint = <&sgtl5000_rx_endpoint>;
+ format = "i2s";
+ mclk-fs = <512>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <16>;
+ };
+ };
+ };
+};
+
+&timers2 {
+ /* spare dmas for other usage (un-delete to enable pwm capture) */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "okay";
+ pwm2: pwm {
+ pinctrl-0 = <&pwm2_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ timer@1 {
+ status = "okay";
+ };
+};
+
+&usart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usart3_pins_a>;
+ status = "okay";
+};
+
+&uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ dr_mode = "otg";
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ phy-names = "usb2-phy";
+ phys = <&usbphyc_port1 0>;
+ vbus-supply = <&vbus_otg>;
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
new file mode 100644
index 0000000..000af71
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
@@ -0,0 +1,406 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
+ */
+
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxaa-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ aliases {
+ ethernet0 = ðernet0;
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xC0000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mcuram2: mcuram2@10000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@10040000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x1000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@10041000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10041000 0x1000>;
+ no-map;
+ };
+
+ vdev0buffer: vdev0buffer@10042000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x4000>;
+ no-map;
+ };
+
+ mcuram: mcuram@30000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram: retram@38000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+ };
+
+ ethernet_vio: vioregulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vio";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd>;
+ };
+};
+
+&adc {
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vdda>;
+ status = "okay";
+
+ adc1: adc@0 {
+ st,min-sample-time-nsecs = <5000>;
+ st,adc-channels = <0>;
+ status = "okay";
+ };
+
+ adc2: adc@100 {
+ st,adc-channels = <1>;
+ st,min-sample-time-nsecs = <5000>;
+ status = "okay";
+ };
+};
+
+&dac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
+ vref-supply = <&vdda>;
+ status = "okay";
+
+ dac1: dac@1 {
+ status = "okay";
+ };
+ dac2: dac@2 {
+ status = "okay";
+ };
+};
+
+&dts {
+ status = "okay";
+};
+
+ðernet0 {
+ status = "okay";
+ pinctrl-0 = <ðernet0_rmii_pins_a>;
+ pinctrl-1 = <ðernet0_rmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0>;
+ st,eth-ref-clk-sel;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ /* LAN8710Ai */
+ compatible = "ethernet-phy-id0007.c0f0",
+ "ethernet-phy-ieee802.3-c22";
+ clocks = <&rcc ETHCK_K>;
+ reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500>;
+ reset-deassert-us = <500>;
+ smsc,disable-energy-detect;
+ interrupt-parent = <&gpioi>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ rtc@32 {
+ compatible = "microcrystal,rv8803";
+ reg = <0x32>;
+ };
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+ ldo1-supply = <&v3v3>;
+ ldo2-supply = <&v3v3>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo5-supply = <&v3v3>;
+ ldo6-supply = <&v3v3>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ vdda: ldo1 {
+ regulator-name = "vdda";
+ regulator-always-on;
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ v2v8: ldo2 {
+ regulator-name = "v2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdd_sd: ldo5 {
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ regulator-boot-on;
+ };
+
+ v1v8: ldo6 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+
+ touchscreen@49 {
+ compatible = "ti,tsc2004";
+ reg = <0x49>;
+ vio-supply = <&v3v3>;
+ interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&ipcc {
+ status = "okay";
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&m4_rproc {
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>;
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ interrupt-parent = <&exti>;
+ interrupts = <68 1>;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
+ cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,sig-dir;
+ st,neg-edge;
+ st,use-ckin;
+ bus-width = <4>;
+ vmmc-supply = <&vdd_sd>;
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&v3v3>;
+ mmc-ddr-3_3v;
+ status = "okay";
+};
+
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&v3v3>;
+ mmc-ddr-3_3v;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
new file mode 100644
index 0000000..944d38b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ */
+
+/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */
+#include "stm32mp15xx-dhcor-io1v8.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = ðernet0;
+ mmc0 = &sdmmc1;
+ serial0 = &uart4;
+ serial1 = &uart7;
+ serial2 = &usart2;
+ spi0 = &qspi;
+ };
+
+ /* XTal Q1 */
+ cec_clock: clk-cec-fixed {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&adv7513_out>;
+ };
+ };
+ };
+
+ led {
+ compatible = "gpio-leds";
+ led1 {
+ label = "green:user0";
+ gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "green:user1";
+ gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led3 {
+ label = "green:user2";
+ gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+
+ led4 {
+ label = "green:user3";
+ gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "none";
+ default-state = "off";
+ panic-indicator;
+ };
+ };
+
+ sd_switch: regulator-sd_switch {
+ compatible = "regulator-gpio";
+ regulator-name = "sd_switch";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-type = "voltage";
+ regulator-always-on;
+
+ gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0>;
+ states = <1800000 0x1>,
+ <2900000 0x0>;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "STM32MP1-AV96-HDMI";
+ dais = <&sai2a_port>;
+ status = "okay";
+ };
+
+ wlan_pwr: regulator-wlan {
+ compatible = "regulator-fixed";
+
+ regulator-name = "wl-reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&adc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc12_ain_pins_b>;
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdda>;
+ vref-supply = <&vdda>;
+ status = "okay";
+
+ adc1: adc@0 {
+ st,adc-channels = <0 1 6>;
+ st,min-sample-time-nsecs = <5000>;
+ status = "okay";
+ };
+
+ adc2: adc@100 {
+ st,adc-channels = <0 1 2>;
+ st,min-sample-time-nsecs = <5000>;
+ status = "okay";
+ };
+};
+
+ðernet0 {
+ status = "okay";
+ pinctrl-0 = <ðernet0_rgmii_pins_c>;
+ pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <1000>;
+
+ phy0: ethernet-phy@7 {
+ reg = <7>;
+
+ rxc-skew-ps = <1500>;
+ rxdv-skew-ps = <540>;
+ rxd0-skew-ps = <420>;
+ rxd1-skew-ps = <420>;
+ rxd2-skew-ps = <420>;
+ rxd3-skew-ps = <420>;
+
+ txc-skew-ps = <1440>;
+ txen-skew-ps = <540>;
+ txd0-skew-ps = <420>;
+ txd1-skew-ps = <420>;
+ txd2-skew-ps = <420>;
+ txd3-skew-ps = <420>;
+ };
+ };
+};
+
+&i2c1 { /* X6 I2C1 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_b>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&i2c2 { /* X6 I2C2 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_c>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&i2c4 {
+ hdmi-transmitter@3d {
+ compatible = "adi,adv7513";
+ reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
+ reg-names = "main", "edid", "cec", "packet";
+ clocks = <&cec_clock>;
+ clock-names = "cec";
+
+ avdd-supply = <&v3v3>;
+ dvdd-supply = <&v3v3>;
+ pvdd-supply = <&v3v3>;
+ dvdd-3v-supply = <&v3v3>;
+ bgvdd-supply = <&v3v3>;
+
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpiog>;
+
+ status = "okay";
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7513_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7513_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ adv7513_i2s0: endpoint {
+ remote-endpoint = <&sai2a_endpoint>;
+ };
+ };
+ };
+ };
+};
+
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_d>;
+ pinctrl-1 = <<dc_sleep_pins_d>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&adv7513_in>;
+ };
+ };
+};
+
+&sai2 {
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai2a_pins_c>;
+ pinctrl-1 = <&sai2a_sleep_pins_c>;
+ clock-names = "pclk", "x8k", "x11k";
+ status = "okay";
+
+ sai2a: audio-controller@4400b004 {
+ #clock-cells = <0>;
+ dma-names = "tx";
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ status = "okay";
+
+ sai2a_port: port {
+ sai2a_endpoint: endpoint {
+ remote-endpoint = <&adv7513_i2s0>;
+ format = "i2s";
+ mclk-fs = <256>;
+ };
+ };
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
+ cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,sig-dir;
+ st,neg-edge;
+ st,use-ckin;
+ bus-width = <4>;
+ vmmc-supply = <&vdd_sd>;
+ vqmmc-supply = <&sd_switch>;
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&vdd_io>;
+ status = "okay";
+};
+
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_b>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
+ broken-cd;
+ non-removable;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&wlan_pwr>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ cs-gpios = <&gpioi 0 0>;
+ status = "disabled";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+};
+
+&uart4 {
+ /* On Low speed expansion header */
+ label = "LS-UART1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_b>;
+ status = "okay";
+};
+
+&uart7 {
+ /* On Low speed expansion header */
+ label = "LS-UART0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* Bluetooth */
+&usart2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_sleep_pins_a>;
+ st,hw-flow-ctrl;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <3000000>;
+ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ phy-names = "usb";
+ status = "okay";
+};
+
+&usbotg_hs {
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ phy-names = "usb2-phy";
+ phys = <&usbphyc_port1 0>;
+ status = "okay";
+ vbus-supply = <&vbus_otg>;
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi
new file mode 100644
index 0000000..7517231
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ */
+
+/ {
+ /* Enpirion EP3A8LQI U2 on the DHCOR */
+ vdd_io: regulator-buck-io {
+ compatible = "regulator-fixed";
+ regulator-name = "buck-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd>;
+ };
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd_io>;
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
new file mode 100644
index 0000000..5af3214
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ * Copyright (C) 2020 Marek Vasut <marex@denx.de>
+ */
+
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ aliases {
+ spi0 = &qspi;
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x40000000>;
+ };
+};
+
+&dts {
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+
+ ldo1-supply = <&v3v3>;
+ ldo2-supply = <&v3v3>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo5-supply = <&v3v3>;
+ ldo6-supply = <&v3v3>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ vdda: ldo1 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ v2v8: ldo2 {
+ regulator-name = "v2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdd_sd: ldo5 {
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ regulator-boot-on;
+ };
+
+ v1v8: ldo6 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ regulator-enable-ramp-delay = <300000>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ regulator-active-discharge = <1>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
+ reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <50000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
new file mode 100644
index 0000000..47df8ac
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
@@ -0,0 +1,674 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mcuram2: mcuram2@10000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@10040000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x1000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@10041000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10041000 0x1000>;
+ no-map;
+ };
+
+ vdev0buffer: vdev0buffer@10042000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x4000>;
+ no-map;
+ };
+
+ mcuram: mcuram@30000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram: retram@38000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+
+ gpu_reserved: gpu@d4000000 {
+ reg = <0xd4000000 0x4000000>;
+ no-map;
+ };
+ };
+
+ led {
+ compatible = "gpio-leds";
+ led-blue {
+ label = "heartbeat";
+ gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "STM32MP1-DK";
+ routing =
+ "Playback" , "MCLK",
+ "Capture" , "MCLK",
+ "MICL" , "Mic Bias";
+ dais = <&sai2a_port &sai2b_port &i2s2_port>;
+ status = "okay";
+ };
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&adc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdd>;
+ vref-supply = <&vrefbuf>;
+ status = "disabled";
+ adc1: adc@0 {
+ /*
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+ * 5 * (56 + 47kOhms) * 5pF => 2.5us.
+ * Use arbitrary margin here (e.g. 5us).
+ */
+ st,min-sample-time-nsecs = <5000>;
+ /* AIN connector, USB Type-C CC1 & CC2 */
+ st,adc-channels = <0 1 6 13 18 19>;
+ status = "okay";
+ };
+ adc2: adc@100 {
+ /* AIN connector, USB Type-C CC1 & CC2 */
+ st,adc-channels = <0 1 2 6 18 19>;
+ st,min-sample-time-nsecs = <5000>;
+ status = "okay";
+ };
+};
+
+&cec {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cec_pins_b>;
+ pinctrl-1 = <&cec_sleep_pins_b>;
+ status = "okay";
+};
+
+&dts {
+ status = "okay";
+};
+
+ðernet0 {
+ status = "okay";
+ pinctrl-0 = <ðernet0_rgmii_pins_a>;
+ pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rgmii-id";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gpu {
+ contiguous-area = <&gpu_reserved>;
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <100>;
+ i2c-scl-falling-time-ns = <7>;
+ status = "okay";
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ hdmi-transmitter@39 {
+ compatible = "sil,sii9022";
+ reg = <0x39>;
+ iovcc-supply = <&v3v3_hdmi>;
+ cvcc12-supply = <&v1v2_hdmi>;
+ reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpiog>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ sii9022_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ sii9022_tx_endpoint: endpoint {
+ remote-endpoint = <&i2s2_endpoint>;
+ };
+ };
+ };
+ };
+
+ cs42l51: cs42l51@4a {
+ compatible = "cirrus,cs42l51";
+ reg = <0x4a>;
+ #sound-dai-cells = <0>;
+ VL-supply = <&v3v3>;
+ VD-supply = <&v1v8_audio>;
+ VA-supply = <&v1v8_audio>;
+ VAHP-supply = <&v1v8_audio>;
+ reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
+ clocks = <&sai2a>;
+ clock-names = "MCLK";
+ status = "okay";
+
+ cs42l51_port: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cs42l51_tx_endpoint: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&sai2a_endpoint>;
+ frame-master = <&cs42l51_tx_endpoint>;
+ bitclock-master = <&cs42l51_tx_endpoint>;
+ };
+
+ cs42l51_rx_endpoint: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&sai2b_endpoint>;
+ frame-master = <&cs42l51_rx_endpoint>;
+ bitclock-master = <&cs42l51_rx_endpoint>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c4_pins_a>;
+ pinctrl-1 = <&i2c4_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+ buck1-supply = <&vin>;
+ buck2-supply = <&vin>;
+ buck3-supply = <&vin>;
+ buck4-supply = <&vin>;
+ ldo1-supply = <&v3v3>;
+ ldo2-supply = <&vin>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo4-supply = <&vin>;
+ ldo5-supply = <&vin>;
+ ldo6-supply = <&v3v3>;
+ vref_ddr-supply = <&vin>;
+ boost-supply = <&vin>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ v1v8_audio: ldo1 {
+ regulator-name = "v1v8_audio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ v3v3_hdmi: ldo2 {
+ regulator-name = "v3v3_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdda: ldo5 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ regulator-boot-on;
+ };
+
+ v1v2_hdmi: ldo6 {
+ regulator-name = "v1v2_hdmi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_pins_a>;
+ pinctrl-1 = <&i2c5_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ clock-frequency = <400000>;
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+};
+
+&i2s2 {
+ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "i2sclk", "x8k", "x11k";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2s2_pins_a>;
+ pinctrl-1 = <&i2s2_sleep_pins_a>;
+ status = "okay";
+
+ i2s2_port: port {
+ i2s2_endpoint: endpoint {
+ remote-endpoint = <&sii9022_tx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ };
+ };
+};
+
+&ipcc {
+ status = "okay";
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_a>;
+ pinctrl-1 = <<dc_sleep_pins_a>;
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
+
+&m4_rproc {
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>;
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ interrupt-parent = <&exti>;
+ interrupts = <68 1>;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sai2 {
+ clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "x8k", "x11k";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
+ pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
+ status = "okay";
+
+ sai2a: audio-controller@4400b004 {
+ #clock-cells = <0>;
+ dma-names = "tx";
+ clocks = <&rcc SAI2_K>;
+ clock-names = "sai_ck";
+ status = "okay";
+
+ sai2a_port: port {
+ sai2a_endpoint: endpoint {
+ remote-endpoint = <&cs42l51_tx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ };
+ };
+ };
+
+ sai2b: audio-controller@4400b024 {
+ dma-names = "rx";
+ st,sync = <&sai2a 2>;
+ clocks = <&rcc SAI2_K>, <&sai2a>;
+ clock-names = "sai_ck", "MCLK";
+ status = "okay";
+
+ sai2b_port: port {
+ sai2b_endpoint: endpoint {
+ remote-endpoint = <&cs42l51_rx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ };
+ };
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "okay";
+};
+
+&sdmmc3 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc3_b4_pins_a>;
+ pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
+ broken-cd;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "disabled";
+};
+
+&timers1 {
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm1_pins_a>;
+ pinctrl-1 = <&pwm1_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@0 {
+ status = "okay";
+ };
+};
+
+&timers3 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm3_pins_a>;
+ pinctrl-1 = <&pwm3_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@2 {
+ status = "okay";
+ };
+};
+
+&timers4 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
+ pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@3 {
+ status = "okay";
+ };
+};
+
+&timers5 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm5_pins_a>;
+ pinctrl-1 = <&pwm5_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@4 {
+ status = "okay";
+ };
+};
+
+&timers6 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ timer@5 {
+ status = "okay";
+ };
+};
+
+&timers12 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm12_pins_a>;
+ pinctrl-1 = <&pwm12_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+ timer@11 {
+ status = "okay";
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins_a>;
+ pinctrl-1 = <&uart4_sleep_pins_a>;
+ pinctrl-2 = <&uart4_idle_pins_a>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart7_pins_c>;
+ pinctrl-1 = <&uart7_sleep_pins_c>;
+ pinctrl-2 = <&uart7_idle_pins_c>;
+ status = "disabled";
+};
+
+&usart3 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart3_pins_c>;
+ pinctrl-1 = <&usart3_sleep_pins_c>;
+ pinctrl-2 = <&usart3_idle_pins_c>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ status = "okay";
+};
+
+&usbotg_hs {
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ usb-role-switch;
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+ vdda1v1-supply = <®11>;
+ vdda1v8-supply = <®18>;
+};
+
+&vrefbuf {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ vdda-supply = <&vdd>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
new file mode 100644
index 0000000..6706d83
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
+/*
+ * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2020 Ahmad Fatoum, Pengutronix
+ */
+
+#include "stm32mp15-pinctrl.dtsi"
+
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mcuram2: mcuram2@10000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@10040000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x1000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@10041000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10041000 0x1000>;
+ no-map;
+ };
+
+ vdev0buffer: vdev0buffer@10042000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x4000>;
+ no-map;
+ };
+
+ mcuram: mcuram@30000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram: retram@38000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+ };
+
+ reg_sip_eeprom: regulator_eeprom {
+ compatible = "regulator-fixed";
+ regulator-name = "sip_eeprom";
+ regulator-always-on;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c4_pins_a>;
+ pinctrl-1 = <&i2c4_sleep_pins_a>;
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+
+ ldo1-supply = <&v3v3>;
+ ldo6-supply = <&v3v3>;
+ pwr_sw1-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ v1v8_audio: ldo1 {
+ regulator-name = "v1v8_audio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO1 0>;
+
+ };
+
+ v3v3_hdmi: ldo2 {
+ regulator-name = "v3v3_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO2 0>;
+
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdda: ldo5 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ regulator-boot-on;
+ };
+
+ v1v2_hdmi: ldo6 {
+ regulator-name = "v1v2_hdmi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ interrupts = <IT_CURLIM_LDO6 0>;
+
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ regulator-active-discharge = <1>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ };
+
+ pmic_watchdog: watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+
+ sip_eeprom: eeprom@50 {
+ compatible = "atmel,24c32";
+ vcc-supply = <®_sip_eeprom>;
+ reg = <0x50>;
+ };
+};
+
+&ipcc {
+ status = "okay";
+};
+
+&m4_rproc {
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>;
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ interrupt-parent = <&exti>;
+ interrupts = <68 1>;
+ status = "okay";
+};
+
+&rng1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi
new file mode 100644
index 0000000..04f7a43
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xxaa-pinctrl.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AA>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@5000a000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@5000b000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@5000c000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+};
+
+&pinctrl_z {
+ st,package = <STM32MP_PKG_AA>;
+
+ gpioz: gpio@54004000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi
new file mode 100644
index 0000000..328dad1
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xxab-pinctrl.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AB>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <6>;
+ gpio-ranges = <&pinctrl 6 86 6>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl 6 102 10>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <2>;
+ gpio-ranges = <&pinctrl 0 112 2>;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi
new file mode 100644
index 0000000..7eaa245
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xxac-pinctrl.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AC>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio@5000a000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ st,package = <STM32MP_PKG_AC>;
+
+ gpioz: gpio@54004000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi
new file mode 100644
index 0000000..b63e207
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp15xxad-pinctrl.dtsi
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AD>;
+
+ gpioa: gpio@50002000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@50003000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@50004000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio@50005000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@50006000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@50007000 {
+ status = "okay";
+ ngpios = <6>;
+ gpio-ranges = <&pinctrl 6 86 6>;
+ };
+
+ gpiog: gpio@50008000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl 6 102 10>;
+ };
+
+ gpioh: gpio@50009000 {
+ status = "okay";
+ ngpios = <2>;
+ gpio-ranges = <&pinctrl 0 112 2>;
+ };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 8692b11..af8ab73 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -133,6 +144,20 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 2265ca2..1c5a666 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -624,6 +624,16 @@
status = "disabled";
};
+ csi1: csi@1c1d000 {
+ compatible = "allwinner,sun4i-a10-csi1";
+ reg = <0x01c1d000 0x1000>;
+ interrupts = <43>;
+ clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+ clock-names = "bus", "ram";
+ resets = <&ccu RST_CSI1>;
+ status = "disabled";
+ };
+
spi3: spi@1c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
@@ -670,6 +680,31 @@
function = "can";
};
+ /omit-if-no-ref/
+ csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+ pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+ "PG6", "PG7", "PG8", "PG9", "PG10",
+ "PG11";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+ pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+ "PH5", "PH6", "PH7", "PH8", "PH9",
+ "PH10", "PH11", "PH12", "PH13", "PH14",
+ "PH15", "PH16", "PH17", "PH18", "PH19",
+ "PH20", "PH21", "PH22", "PH23", "PH24",
+ "PH25", "PH26", "PH27";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_clk_pg_pin: csi1-clk-pg-pin {
+ pins = "PG1";
+ function = "csi1";
+ };
+
emac_pins: emac0-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 7033a12..d6bb82c 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -130,7 +130,7 @@
&i2c1 {
status = "okay";
- at24@50 {
+ eeprom@50 {
compatible = "atmel,24c16";
pagesize = <16>;
reg = <0x50>;
diff --git a/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts
new file mode 100644
index 0000000..e9ef97c
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a13-pocketbook-touch-lux-3.dts
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright 2019 Ondrej Jirman <megous@megous.com>
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "PocketBook Touch Lux 3";
+ compatible = "pocketbook,touch-lux-3", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ enable-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */
+ default-state = "on";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ label = "GPIO Keys";
+
+ key-right {
+ label = "Right";
+ linux,code = <KEY_RIGHT>;
+ gpios = <&pio 6 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG9 */
+ };
+
+ key-left {
+ label = "Left";
+ linux,code = <KEY_LEFT>;
+ gpios = <&pio 6 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG10 */
+ };
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-1v8-nor-ctp";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pio 2 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_1v8_nor: regulator-nor {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-nor";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pio 2 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_1v8>;
+ regulator-always-on;
+ };
+
+ reg_1v8_ctp: regulator-ctp {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-ctp";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pio 2 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_1v8>;
+ };
+
+ reg_3v3_mmc0: regulator-mmc0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-mmc0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 4 4 GPIO_ACTIVE_LOW>; /* PE4 */
+ vin-supply = <®_vcc3v3>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* Touchpanel is connected here. */
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button-200 {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button-400 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_3v3_mmc0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_4bit_pc_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+ /* We need this otherwise the LDO3 would overload */
+ regulator-soft-start;
+ regulator-ramp-delay = <1600>;
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>;
+ status = "okay";
+
+ epd_flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "macronix,mx25u4033", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pg_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_ldo3>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index fd31da8..c2b4fbf 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -185,7 +185,9 @@
mbus: dram-controller@1c01000 {
compatible = "allwinner,sun5i-a13-mbus";
reg = <0x01c01000 0x1000>;
- clocks = <&ccu 99>;
+ clocks = <&ccu CLK_MBUS>;
+ #address-cells = <1>;
+ #size-cells = <1>;
dma-ranges = <0x00000000 0x40000000 0x20000000>;
#interconnect-cells = <1>;
};
@@ -275,6 +277,7 @@
compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <44>;
+ dmas = <&dma SUN4I_DMA_DEDICATED 14>;
resets = <&ccu RST_LCD>;
reset-names = "lcd";
clocks = <&ccu CLK_AHB_LCD>,
@@ -770,9 +773,6 @@
interconnect-names = "dma-mem";
status = "disabled";
- assigned-clocks = <&ccu CLK_DE_BE>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ac76380..f3425a6 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -285,14 +285,19 @@
compatible = "allwinner,sun6i-a31-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_AHB1_LCD0>;
- reset-names = "lcd";
+ dmas = <&dma 11>;
+ resets = <&ccu RST_AHB1_LCD0>,
+ <&ccu RST_AHB1_LVDS>;
+ reset-names = "lcd",
+ "lvds";
clocks = <&ccu CLK_AHB1_LCD0>,
<&ccu CLK_LCD0_CH0>,
- <&ccu CLK_LCD0_CH1>;
+ <&ccu CLK_LCD0_CH1>,
+ <&ccu 15>;
clock-names = "ahb",
"tcon-ch0",
- "tcon-ch1";
+ "tcon-ch1",
+ "lvds-alt";
clock-output-names = "tcon0-pixel-clock";
#clock-cells = <0>;
@@ -334,14 +339,18 @@
compatible = "allwinner,sun6i-a31-tcon";
reg = <0x01c0d000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_AHB1_LCD1>;
- reset-names = "lcd";
+ dmas = <&dma 12>;
+ resets = <&ccu RST_AHB1_LCD1>,
+ <&ccu RST_AHB1_LVDS>;
+ reset-names = "lcd", "lvds";
clocks = <&ccu CLK_AHB1_LCD1>,
<&ccu CLK_LCD1_CH0>,
- <&ccu CLK_LCD1_CH1>;
+ <&ccu CLK_LCD1_CH1>,
+ <&ccu 15>;
clock-names = "ahb",
"tcon-ch0",
- "tcon-ch1";
+ "tcon-ch1",
+ "lvds-alt";
clock-output-names = "tcon1-pixel-clock";
#clock-cells = <0>;
@@ -469,7 +478,6 @@
<&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
resets = <&ccu RST_AHB1_HDMI>;
- reset-names = "ahb";
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
dmas = <&dma 13>, <&dma 13>, <&dma 14>;
status = "disabled";
@@ -1131,9 +1139,6 @@
"ram";
resets = <&ccu RST_AHB1_BE1>;
- assigned-clocks = <&ccu CLK_BE1>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1177,9 +1182,6 @@
"ram";
resets = <&ccu RST_AHB1_DRC1>;
- assigned-clocks = <&ccu CLK_IEP_DRC1>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1223,9 +1225,6 @@
"ram";
resets = <&ccu RST_AHB1_BE0>;
- assigned-clocks = <&ccu CLK_BE0>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1266,9 +1265,6 @@
"ram";
resets = <&ccu RST_AHB1_DRC0>;
- assigned-clocks = <&ccu CLK_IEP_DRC0>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts b/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts
new file mode 100644
index 0000000..da5a2ee
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-linutronix-testbox-v2.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2020 Linutronix GmbH
+ * Author: Benedikt Spranger <b.spranger@linutronix.de>
+ */
+
+/dts-v1/;
+#include "sun7i-a20-lamobo-r1.dts"
+
+/ {
+ model = "Lamobo R1";
+ compatible = "linutronix,testbox-v2", "lamobo,lamobo-r1", "allwinner,sun7i-a20";
+
+ leds {
+ led-opto1 {
+ label = "lamobo_r1:opto:powerswitch";
+ gpios = <&pio 7 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-opto2 {
+ label = "lamobo_r1:opto:relay";
+ gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ status = "okay";
+ };
+
+ atecc508a@60 {
+ compatible = "atmel,atecc508a";
+ reg = <0x60>;
+ };
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can_ph_pins>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts
new file mode 100644
index 0000000..033cab3
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime-emmc.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+#include "sun7i-a20-olinuxino-lime.dts"
+
+/ {
+ model = "Olimex A20-OLinuXino-LIME-eMMC";
+ compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20";
+
+ mmc2_pwrseq: pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mmc2 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ mmc-pwrseq = <&mmc2_pwrseq>;
+ status = "okay";
+
+ emmc: emmc@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
index 9ba6277..488933b 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -112,7 +112,7 @@
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy-handle = <&phy1>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 1f8b45f..6d6a379 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -47,6 +47,7 @@
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/clock/sun7i-a20-ccu.h>
#include <dt-bindings/reset/sun4i-a10-ccu.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
interrupt-parent = <&gic>;
@@ -404,11 +405,12 @@
};
tcon0: lcd-controller@1c0c000 {
- compatible = "allwinner,sun7i-a20-tcon";
+ compatible = "allwinner,sun7i-a20-tcon0",
+ "allwinner,sun7i-a20-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_TCON0>;
- reset-names = "lcd";
+ resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
+ reset-names = "lcd", "lvds";
clocks = <&ccu CLK_AHB_LCD0>,
<&ccu CLK_TCON0_CH0>,
<&ccu CLK_TCON0_CH1>;
@@ -454,7 +456,8 @@
};
tcon1: lcd-controller@1c0d000 {
- compatible = "allwinner,sun7i-a20-tcon";
+ compatible = "allwinner,sun7i-a20-tcon1",
+ "allwinner,sun7i-a20-tcon";
reg = <0x01c0d000 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ccu RST_TCON1>;
@@ -729,6 +732,17 @@
status = "disabled";
};
+ csi1: csi@1c1d000 {
+ compatible = "allwinner,sun7i-a20-csi1",
+ "allwinner,sun4i-a10-csi1";
+ reg = <0x01c1d000 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+ clock-names = "bus", "ram";
+ resets = <&ccu RST_CSI1>;
+ status = "disabled";
+ };
+
spi3: spi@1c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
@@ -803,6 +817,31 @@
};
/omit-if-no-ref/
+ csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+ pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+ "PG6", "PG7", "PG8", "PG9", "PG10",
+ "PG11";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+ pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+ "PH5", "PH6", "PH7", "PH8", "PH9",
+ "PH10", "PH11", "PH12", "PH13", "PH14",
+ "PH15", "PH16", "PH17", "PH18", "PH19",
+ "PH20", "PH21", "PH22", "PH23", "PH24",
+ "PH25", "PH26", "PH27";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_clk_pg_pin: csi1-clk-pg-pin {
+ pins = "PG1";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
emac_pa_pins: emac-pa-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
@@ -896,6 +935,20 @@
};
/omit-if-no-ref/
+ lcd_lvds0_pins: lcd-lvds0-pins {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ "PD5", "PD6", "PD7", "PD8", "PD9";
+ function = "lvds0";
+ };
+
+ /omit-if-no-ref/
+ lcd_lvds1_pins: lcd-lvds1-pins {
+ pins = "PD10", "PD11", "PD12", "PD13", "PD14",
+ "PD15", "PD16", "PD17", "PD18", "PD19";
+ function = "lvds1";
+ };
+
+ /omit-if-no-ref/
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index f292f96..c1362d0 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -182,14 +182,19 @@
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma 12>;
clocks = <&ccu CLK_BUS_LCD>,
- <&ccu CLK_LCD_CH0>;
+ <&ccu CLK_LCD_CH0>,
+ <&ccu 13>;
clock-names = "ahb",
- "tcon-ch0";
+ "tcon-ch0",
+ "lvds-alt";
clock-output-names = "tcon-pixel-clock";
#clock-cells = <0>;
- resets = <&ccu RST_BUS_LCD>;
- reset-names = "lcd";
+ resets = <&ccu RST_BUS_LCD>,
+ <&ccu RST_BUS_LVDS>;
+ reset-names = "lcd",
+ "lvds";
status = "disabled";
ports {
@@ -679,9 +684,6 @@
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_BUS_DRC>;
- assigned-clocks = <&ccu CLK_DRC>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
index 3d78169..a1953b2 100644
--- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
+++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
@@ -194,8 +194,8 @@
"Headphone", "Headphone Jack";
/* Board level routing. First 2 routes copied from SoC level */
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
"HP", "HPCOM",
"Headphone Jack", "HP",
"MIC1", "Microphone Jack",
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 1532a0e..46f4242 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -46,7 +46,7 @@
#include <dt-bindings/thermal/thermal.h>
/ {
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
@@ -164,7 +164,7 @@
io-channels = <&ths>;
};
- mali_opp_table: gpu-opp-table {
+ mali_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-144000000 {
@@ -189,8 +189,8 @@
simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right";
+ "Left DAC", "DACL",
+ "Right DAC", "DACR";
status = "disabled";
simple-audio-card,cpu {
@@ -215,7 +215,7 @@
};
crypto: crypto-engine@1c15000 {
- compatible = "allwinner,sun4i-a10-crypto";
+ compatible = "allwinner,sun8i-a33-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
@@ -372,8 +372,6 @@
"ram", "sat";
resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
reset-names = "be", "sat";
- assigned-clocks = <&ccu CLK_DE_BE>;
- assigned-clock-rates = <300000000>;
};
&ccu {
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 6bf93e5..bfc9bb2 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -164,6 +164,22 @@
status = "okay";
};
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5x06";
+ reg = <0x38>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PL7 */
+ reset-gpios = <&pio 3 5 GPIO_ACTIVE_LOW>; /* PD5 */
+ vcc-supply = <®_ldo_io0>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <600>;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
status = "okay";
@@ -477,7 +493,6 @@
};
&usb_otg {
- dr_mode = "otg";
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 4e485e4..a746e44 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -50,6 +50,7 @@
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
@@ -71,7 +72,7 @@
#cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
clocks = <&ccu CLK_C0CPUX>;
@@ -82,7 +83,7 @@
#cooling-cells = <2>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
clocks = <&ccu CLK_C0CPUX>;
@@ -93,7 +94,7 @@
#cooling-cells = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
clocks = <&ccu CLK_C0CPUX>;
@@ -115,7 +116,7 @@
#cooling-cells = <2>;
};
- cpu@101 {
+ cpu101: cpu@101 {
compatible = "arm,cortex-a7";
device_type = "cpu";
clocks = <&ccu CLK_C1CPUX>;
@@ -126,7 +127,7 @@
#cooling-cells = <2>;
};
- cpu@102 {
+ cpu102: cpu@102 {
compatible = "arm,cortex-a7";
device_type = "cpu";
clocks = <&ccu CLK_C1CPUX>;
@@ -137,7 +138,7 @@
#cooling-cells = <2>;
};
- cpu@103 {
+ cpu103: cpu@103 {
compatible = "arm,cortex-a7";
device_type = "cpu";
clocks = <&ccu CLK_C1CPUX>;
@@ -199,7 +200,7 @@
status = "disabled";
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-cluster0 {
compatible = "operating-points-v2";
opp-shared;
@@ -252,7 +253,7 @@
};
};
- cpu1_opp_table: opp_table1 {
+ cpu1_opp_table: opp-table-cluster1 {
compatible = "operating-points-v2";
opp-shared;
@@ -323,6 +324,17 @@
#reset-cells = <1>;
};
+ rotate: rotate@1020000 {
+ compatible = "allwinner,sun8i-a83t-de2-rotate";
+ reg = <0x1020000 0x10000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&display_clocks CLK_BUS_ROT>,
+ <&display_clocks CLK_ROT>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_ROT>;
+ };
+
mixer0: mixer@1100000 {
compatible = "allwinner,sun8i-a83t-de2-mixer-0";
reg = <0x01100000 0x100000>;
@@ -581,6 +593,31 @@
sid: eeprom@1c14000 {
compatible = "allwinner,sun8i-a83t-sid";
reg = <0x1c14000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ths_calibration: thermal-sensor-calibration@34 {
+ reg = <0x34 8>;
+ };
+ };
+
+ crypto: crypto@1c15000 {
+ compatible = "allwinner,sun8i-a83t-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_SS>;
+ clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
+ clock-names = "bus", "mod";
+ };
+
+ msgbox: mailbox@1c17000 {
+ compatible = "allwinner,sun8i-a83t-msgbox",
+ "allwinner,sun6i-a31-msgbox";
+ reg = <0x01c17000 0x1000>;
+ clocks = <&ccu CLK_BUS_MSGBOX>;
+ resets = <&ccu RST_BUS_MSGBOX>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
};
usb_otg: usb@1c19000 {
@@ -990,10 +1027,10 @@
reg = <0x01c30000 0x104>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
- resets = <&ccu 13>;
- reset-names = "stmmaceth";
- clocks = <&ccu 27>;
+ clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
status = "disabled";
mdio: mdio {
@@ -1086,7 +1123,7 @@
compatible = "allwinner,sun8i-a83t-r-ccu";
reg = <0x01f01400 0x400>;
clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
- <&ccu 6>;
+ <&ccu CLK_PLL_PERIPH>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -1156,5 +1193,82 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ ths: thermal-sensor@1f04000 {
+ compatible = "allwinner,sun8i-a83t-ths";
+ reg = <0x01f04000 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu0_hot: cpu-hot {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_very_hot: cpu-very-hot {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-hot-limit {
+ trip = <&cpu0_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1_thermal: cpu1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 1>;
+
+ trips {
+ cpu1_hot: cpu-hot {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_very_hot: cpu-very-hot {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-hot-limit {
+ trip = <&cpu1_hot>;
+ cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 2>;
+ };
};
};
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index ac9e26b..45a2444 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -143,6 +143,7 @@
};
&ir {
+ linux,rc-map-name = "rc-tanix-tx3mini";
pinctrl-names = "default";
pinctrl-0 = <&r_ir_rx_pin>;
status = "okay";
diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts
new file mode 100644
index 0000000..02fbe00
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * DTS for Emlid Neutis N5 Dev board.
+ *
+ * Copyright (C) 2019 Georgii Staroselskii <georgiii.staroselskii@emlid.com>
+ */
+
+/dts-v1/;
+
+#include "sun8i-h3-emlid-neutis-n5h3.dtsi"
+
+/ {
+ model = "Emlid Neutis N5H3 Developer board";
+ compatible = "emlid,neutis-n5h3-devboard",
+ "emlid,neutis-n5h3",
+ "allwinner,sun8i-h3";
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ gpios-states = <0x1>;
+ states = <1100000 0x0>, <1300000 0x1>;
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&codec {
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi
new file mode 100644
index 0000000..eedd5da
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * DTSI for Emlid Neutis N5 SoM.
+ *
+ * Copyright (C) 2019 Georgii Staroselskii <georgii.staroselskii@emlid.com>
+ */
+
+/dts-v1/;
+
+#include "sun8i-h3.dtsi"
+#include <arm/sunxi-h3-h5-emlid-neutis.dtsi>
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
new file mode 100644
index 0000000..6b14927
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Karl Palsson <karlp@tweak.net.au>
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "FriendlyARM NanoPi Duo2";
+ compatible = "friendlyarm,nanopi-duo2", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "nanopi:red:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ default-state = "on";
+ };
+
+ status {
+ label = "nanopi:green:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+
+ k1 {
+ label = "k1";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */
+ };
+ };
+
+ reg_vdd_cpux: vdd-cpux-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <50>; /* 4ms */
+
+ enable-active-high;
+ enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ gpios-states = <0x1>;
+ states = <1100000 0>, <1300000 1>;
+ };
+
+ reg_vcc_dram: vcc-dram {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-dram";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ vin-supply = <®_vcc5v0>;
+ };
+
+ reg_vdd_sys: vdd-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-sys";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ vin-supply = <®_vcc5v0>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
+ };
+
+};
+
+&cpu0 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+ vmmc-supply = <®_vcc3v3>;
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ sdio_wifi: sdio_wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+®_usb0_vbus {
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>, <&uart2_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <®_vcc3v3>;
+ vddio-supply = <®_vcc3v3>;
+ device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
+ host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
+ shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
+ };
+};
+
+&usb_otg {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index 97f4978..d05fa67 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -85,7 +85,7 @@
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <®_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts
index b8f46e2..251bbab 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts
@@ -70,6 +70,21 @@
};
};
+ leds {
+ compatible = "gpio-leds";
+
+ pwr {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
reg_vcc3v3: vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
@@ -88,6 +103,10 @@
status = "okay";
};
+&ehci0 {
+ status = "okay";
+};
+
&hdmi {
status = "okay";
};
@@ -132,8 +151,27 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pa_pins>;
status = "okay";
};
+
+&usb_otg {
+ /*
+ * According to schematics CN1 MicroUSB port can be used to take
+ * external 5V to power up the board VBUS. On the contrary CN1 MicroUSB
+ * port cannot provide power externally even if the board is powered
+ * via GPIO pins. It thus makes sense to force peripheral mode.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 6056f20..ae4f933 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -41,9 +41,10 @@
*/
#include "sunxi-h3-h5.dtsi"
+#include <dt-bindings/thermal/thermal.h>
/ {
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
@@ -111,6 +112,26 @@
};
};
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+
+ opp-120000000 {
+ opp-hz = /bits/ 64 <120000000>;
+ };
+
+ opp-312000000 {
+ opp-hz = /bits/ 64 <312000000>;
+ };
+
+ opp-432000000 {
+ opp-hz = /bits/ 64 <432000000>;
+ };
+
+ opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ };
+ };
+
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
@@ -129,6 +150,19 @@
};
soc {
+ deinterlace: deinterlace@1400000 {
+ compatible = "allwinner,sun8i-h3-deinterlace";
+ reg = <0x01400000 0x20000>;
+ clocks = <&ccu CLK_BUS_DEINTERLACE>,
+ <&ccu CLK_DEINTERLACE>,
+ <&ccu CLK_DRAM_DEINTERLACE>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_DEINTERLACE>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&mbus 9>;
+ interconnect-names = "dma-mem";
+ };
+
syscon: system-control@1c00000 {
compatible = "allwinner,sun8i-h3-system-control";
reg = <0x01c00000 0x1000>;
@@ -162,6 +196,15 @@
allwinner,sram = <&ve_sram 1>;
};
+ crypto: crypto@1c15000 {
+ compatible = "allwinner,sun8i-h3-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CE>;
+ };
+
mali: gpu@1c40000 {
compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;
@@ -182,9 +225,51 @@
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
clock-names = "bus", "core";
resets = <&ccu RST_BUS_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
+ };
- assigned-clocks = <&ccu CLK_GPU>;
- assigned-clock-rates = <384000000>;
+ ths: thermal-sensor@1c25000 {
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x400>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_THS>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "mod";
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu_hot_trip: cpu-hot {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_very_hot_trip: cpu-very-hot {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-hot-limit {
+ trip = <&cpu_hot_trip>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
};
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 7db8950..a6a1087 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -164,6 +164,10 @@
#include "axp22x.dtsi"
+&ir0 {
+ status = "okay";
+};
+
&mmc0 {
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 3394026..7907569 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -44,8 +44,10 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/reset/sun8i-r40-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
#address-cells = <1>;
@@ -78,25 +80,25 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
@@ -109,6 +111,22 @@
status = "disabled";
};
+ thermal-zones {
+ cpu_thermal: cpu0-thermal {
+ /* milliseconds */
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 0>;
+ };
+
+ gpu_thermal: gpu-thermal {
+ /* milliseconds */
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 1>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -172,6 +190,29 @@
};
};
+ syscon: system-control@1c00000 {
+ compatible = "allwinner,sun8i-r40-system-control",
+ "allwinner,sun4i-a10-system-control";
+ reg = <0x01c00000 0x30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@1d00000 {
+ compatible = "mmio-sram";
+ reg = <0x01d00000 0xd0000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x01d00000 0xd0000>;
+
+ ve_sram: sram-section@0 {
+ compatible = "allwinner,sun8i-r40-sram-c1",
+ "allwinner,sun4i-a10-sram-c1";
+ reg = <0x000000 0x80000>;
+ };
+ };
+ };
+
nmi_intc: interrupt-controller@1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
@@ -180,6 +221,69 @@
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
+ dma: dma-controller@1c02000 {
+ compatible = "allwinner,sun8i-r40-dma",
+ "allwinner,sun50i-a64-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>;
+ dma-channels = <16>;
+ dma-requests = <31>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
+ spi0: spi@1c05000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@1c06000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ csi0: csi@1c09000 {
+ compatible = "allwinner,sun8i-r40-csi0",
+ "allwinner,sun7i-a20-csi0";
+ reg = <0x01c09000 0x1000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI0>;
+ clock-names = "bus", "isp", "ram";
+ resets = <&ccu RST_BUS_CSI0>;
+ interconnects = <&mbus 5>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+ };
+
+ video-codec@1c0e000 {
+ compatible = "allwinner,sun8i-r40-video-engine";
+ reg = <0x01c0e000 0x1000>;
+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+ <&ccu CLK_DRAM_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_BUS_VE>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ allwinner,sram = <&ve_sram 1>;
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun8i-r40-mmc",
"allwinner,sun50i-a64-mmc";
@@ -266,6 +370,28 @@
#phy-cells = <1>;
};
+ crypto: crypto@1c15000 {
+ compatible = "allwinner,sun8i-r40-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CE>;
+ };
+
+ spi2: spi@1c17000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c17000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ahci: sata@1c18000 {
compatible = "allwinner,sun8i-r40-ahci";
reg = <0x01c18000 0x1000>;
@@ -322,6 +448,19 @@
status = "disabled";
};
+ spi3: spi@1c1f000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c1f000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c20000 0x400>;
@@ -356,6 +495,20 @@
function = "clk_out_a";
};
+ /omit-if-no-ref/
+ csi0_8bits_pins: csi0-8bits-pins {
+ pins = "PE0", "PE2", "PE3", "PE4", "PE5",
+ "PE6", "PE7", "PE8", "PE9", "PE10",
+ "PE11";
+ function = "csi0";
+ };
+
+ /omit-if-no-ref/
+ csi0_mclk_pin: csi0-mclk-pin {
+ pins = "PE1";
+ function = "csi0";
+ };
+
gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
@@ -374,6 +527,36 @@
function = "i2c0";
};
+ i2c1_pins: i2c1-pins {
+ pins = "PB18", "PB19";
+ function = "i2c1";
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins = "PB20", "PB21";
+ function = "i2c2";
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins = "PI0", "PI1";
+ function = "i2c3";
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins = "PI2", "PI3";
+ function = "i2c4";
+ };
+
+ ir0_pins: ir0-pins {
+ pins = "PB4";
+ function = "ir0";
+ };
+
+ ir1_pins: ir1-pins {
+ pins = "PB23";
+ function = "ir1";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
@@ -399,6 +582,36 @@
bias-pull-up;
};
+ /omit-if-no-ref/
+ spi0_pc_pins: spi0-pc-pins {
+ pins = "PC0", "PC1", "PC2";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi0_cs0_pc_pin: spi0-cs0-pc-pin {
+ pins = "PC23";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi1_pi_pins: spi1-pi-pins {
+ pins = "PI17", "PI18", "PI19";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ spi1_cs0_pi_pin: spi1-cs0-pi-pin {
+ pins = "PI16";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ spi1_cs1_pi_pin: spi1-cs1-pi-pin {
+ pins = "PI15";
+ function = "spi1";
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
@@ -422,6 +635,43 @@
clocks = <&osc24M>;
};
+ ir0: ir@1c21800 {
+ compatible = "allwinner,sun8i-r40-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x01c21800 0x400>;
+ pinctrl-0 = <&ir0_pins>;
+ pinctrl-names = "default";
+ clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
+ clock-names = "apb", "ir";
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_IR0>;
+ status = "disabled";
+ };
+
+ ir1: ir@1c21c00 {
+ compatible = "allwinner,sun8i-r40-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x01c21c00 0x400>;
+ pinctrl-0 = <&ir1_pins>;
+ pinctrl-names = "default";
+ clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
+ clock-names = "apb", "ir";
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_IR1>;
+ status = "disabled";
+ };
+
+ ths: thermal-sensor@1c24c00 {
+ compatible = "allwinner,sun8i-r40-ths";
+ reg = <0x01c24c00 0x100>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "mod";
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_THS>;
+ /* TODO: add nvmem-cells for calibration */
+ #thermal-sensor-cells = <1>;
+ };
+
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
@@ -529,6 +779,8 @@
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -540,6 +792,8 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -551,6 +805,8 @@
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
resets = <&ccu RST_BUS_I2C3>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -562,11 +818,35 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C4>;
resets = <&ccu RST_BUS_I2C4>;
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
+ mali: gpu@1c40000 {
+ compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+ };
+
gmac: ethernet@1c50000 {
compatible = "allwinner,sun8i-r40-gmac";
syscon = <&ccu>;
@@ -586,6 +866,16 @@
};
};
+ mbus: dram-controller@1c62000 {
+ compatible = "allwinner,sun8i-r40-mbus";
+ reg = <0x01c62000 0x1000>;
+ clocks = <&ccu 155>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x00000000 0x40000000 0x80000000>;
+ #interconnect-cells = <1>;
+ };
+
tcon_top: tcon-top@1c70000 {
compatible = "allwinner,sun8i-r40-tcon-top";
reg = <0x01c70000 0x1000>;
@@ -708,7 +998,7 @@
compatible = "allwinner,sun8i-r40-tcon-tv";
reg = <0x01c73000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
+ clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV0>;
reset-names = "lcd";
@@ -751,7 +1041,7 @@
compatible = "allwinner,sun8i-r40-tcon-tv";
reg = <0x01c74000 0x1000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
+ clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV1>;
reset-names = "lcd";
@@ -793,7 +1083,7 @@
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
+ <0x01c82000 0x2000>,
<0x01c84000 0x2000>,
<0x01c86000 0x2000>;
interrupt-controller;
@@ -838,7 +1128,7 @@
compatible = "allwinner,sun8i-r40-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
- <&ccu 7>, <&ccu 16>;
+ <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
clock-names = "bus", "mod", "pll-0", "pll-1";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";
@@ -846,6 +1136,15 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
new file mode 100644
index 0000000..4aa0ee8
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2019 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+/dts-v1/;
+#include "sun8i-v3.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "PineCube IP Camera";
+ compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ label = "pine64:ir:led1";
+ gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
+ };
+
+ led2 {
+ label = "pine64:ir:led2";
+ gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */
+ };
+ };
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_vcc_wifi: vcc-wifi {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */
+ vin-supply = <®_dcdc3>;
+ startup-delay-us = <200000>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&csi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi1_8bit_pins>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_ep: endpoint {
+ remote-endpoint = <&ov5640_ep>;
+ bus-width = <8>;
+ hsync-active = <1>; /* Active high */
+ vsync-active = <0>; /* Active low */
+ data-active = <1>; /* Active high */
+ pclk-sample = <1>; /* Rising */
+ };
+ };
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp203",
+ "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pe_pins>;
+ status = "okay";
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi1_mclk_pin>;
+ clocks = <&ccu CLK_CSI1_MCLK>;
+ clock-names = "xclk";
+
+ AVDD-supply = <®_ldo3>;
+ DOVDD-supply = <®_ldo3>;
+ DVDD-supply = <®_ldo4>;
+ reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */
+ powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */
+
+ port {
+ ov5640_ep: endpoint {
+ remote-endpoint = <&csi1_ep>;
+ bus-width = <8>;
+ hsync-active = <1>; /* Active high */
+ vsync-active = <0>; /* Active low */
+ data-active = <1>; /* Active high */
+ pclk-sample = <1>; /* Rising */
+ };
+ };
+ };
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button-200 {
+ label = "Setup";
+ linux,code = <KEY_SETUP>;
+ channel = <0>;
+ voltage = <190000>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_dcdc3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc_wifi>;
+ vqmmc-supply = <®_dcdc3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ vcc-pd-supply = <®_dcdc3>;
+ vcc-pe-supply = <®_ldo3>;
+};
+
+#include "axp209.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-sys-cpu-ephy";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "avdd-dovdd-2v8-csi";
+ regulator-soft-start;
+ regulator-ramp-delay = <1600>;
+};
+
+®_ldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dvdd-1v8-csi";
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q128", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi
index 6ae8645..ca4672e 100644
--- a/arch/arm/boot/dts/sun8i-v3.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3.dtsi
@@ -9,6 +9,19 @@
compatible = "allwinner,sun8i-v3-ccu";
};
+&emac {
+ /delete-property/ phy-handle;
+ /delete-property/ phy-mode;
+};
+
+&mdio_mux {
+ external_mdio: mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
&pio {
compatible = "allwinner,sun8i-v3-pinctrl";
};
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 50c32cf..89abd4c 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -43,12 +43,28 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer-lcd {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "mixer0-lcd0";
+ clocks = <&display_clocks CLK_MIXER0>,
+ <&ccu CLK_TCON0>;
+ status = "disabled";
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -123,8 +139,6 @@
clock-names = "bus",
"mod";
resets = <&display_clocks 0>;
- assigned-clocks = <&display_clocks 6>;
- assigned-clock-rates = <150000000>;
ports {
#address-cells = <1>;
@@ -140,6 +154,15 @@
};
};
+ syscon: system-control@1c00000 {
+ compatible = "allwinner,sun8i-v3s-system-control",
+ "allwinner,sun8i-h3-system-control";
+ reg = <0x01c00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
+
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun8i-v3s-tcon";
reg = <0x01c0c000 0x1000>;
@@ -236,6 +259,17 @@
#size-cells = <0>;
};
+ crypto@1c15000 {
+ compatible = "allwinner,sun8i-v3s-crypto",
+ "allwinner,sun8i-a33-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_CE>;
+ reset-names = "ahb";
+ };
+
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-h3-musb";
reg = <0x01c19000 0x0400>;
@@ -294,16 +328,41 @@
interrupt-controller;
#interrupt-cells = <3>;
+ /omit-if-no-ref/
+ csi1_8bit_pins: csi1-8bit-pins {
+ pins = "PE0", "PE2", "PE3", "PE8", "PE9",
+ "PE10", "PE11", "PE12", "PE13", "PE14",
+ "PE15";
+ function = "csi";
+ };
+
+ /omit-if-no-ref/
+ csi1_mclk_pin: csi1-mclk-pin {
+ pins = "PE1";
+ function = "csi";
+ };
+
i2c0_pins: i2c0-pins {
pins = "PB6", "PB7";
function = "i2c0";
};
+ /omit-if-no-ref/
+ i2c1_pe_pins: i2c1-pe-pins {
+ pins = "PE21", "PE22";
+ function = "i2c1";
+ };
+
uart0_pb_pins: uart0-pb-pins {
pins = "PB8", "PB9";
function = "uart0";
};
+ uart2_pins: uart2-pins {
+ pins = "PB0", "PB1";
+ function = "uart2";
+ };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
@@ -379,6 +438,8 @@
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
status = "disabled";
};
@@ -406,6 +467,49 @@
#size-cells = <0>;
};
+ emac: ethernet@1c30000 {
+ compatible = "allwinner,sun8i-v3s-emac";
+ syscon = <&syscon>;
+ reg = <0x01c30000 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ status = "disabled";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+
+ mdio_mux: mdio-mux {
+ compatible = "allwinner,sun8i-h3-mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio-parent-bus = <&mdio>;
+ /* Only one MDIO is usable at the time */
+ internal_mdio: mdio@1 {
+ compatible = "allwinner,sun8i-h3-mdio-internal";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+ };
+ };
+
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
@@ -420,6 +524,18 @@
#size-cells = <0>;
};
+ csi1: camera@1cb4000 {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb4000 0x3000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI1_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index b9b6fb0..ce4fa67 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -387,16 +387,16 @@
usbphy2: phy@a01800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a01800 0x4>;
- clocks = <&usb_clocks CLK_USB1_HSIC>,
+ clocks = <&usb_clocks CLK_USB1_PHY>,
<&usb_clocks CLK_USB_HSIC>,
- <&usb_clocks CLK_USB1_PHY>;
- clock-names = "hsic_480M",
+ <&usb_clocks CLK_USB1_HSIC>;
+ clock-names = "phy",
"hsic_12M",
- "phy";
- resets = <&usb_clocks RST_USB1_HSIC>,
- <&usb_clocks RST_USB1_PHY>;
- reset-names = "hsic",
- "phy";
+ "hsic_480M";
+ resets = <&usb_clocks RST_USB1_PHY>,
+ <&usb_clocks RST_USB1_HSIC>;
+ reset-names = "phy",
+ "hsic";
status = "disabled";
#phy-cells = <0>;
/* usb1 is always used with HSIC */
@@ -429,16 +429,16 @@
usbphy3: phy@a02800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a02800 0x4>;
- clocks = <&usb_clocks CLK_USB2_HSIC>,
+ clocks = <&usb_clocks CLK_USB2_PHY>,
<&usb_clocks CLK_USB_HSIC>,
- <&usb_clocks CLK_USB2_PHY>;
- clock-names = "hsic_480M",
+ <&usb_clocks CLK_USB2_HSIC>;
+ clock-names = "phy",
"hsic_12M",
- "phy";
- resets = <&usb_clocks RST_USB2_HSIC>,
- <&usb_clocks RST_USB2_PHY>;
- reset-names = "hsic",
- "phy";
+ "hsic_480M";
+ resets = <&usb_clocks RST_USB2_PHY>,
+ <&usb_clocks RST_USB2_HSIC>;
+ reset-names = "phy",
+ "hsic";
status = "disabled";
#phy-cells = <0>;
};
@@ -457,6 +457,15 @@
reg = <0x01700000 0x100>;
};
+ crypto: crypto@1c02000 {
+ compatible = "allwinner,sun9i-a80-crypto";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_SS>;
+ clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
+ clock-names = "bus", "mod";
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c0f000 0x1000>;
@@ -521,9 +530,7 @@
compatible = "allwinner,sun9i-a80-mmc-config-clk";
reg = <0x01c13000 0x10>;
clocks = <&ccu CLK_BUS_MMC>;
- clock-names = "ahb";
resets = <&ccu RST_BUS_MMC>;
- reset-names = "ahb";
#clock-cells = <1>;
#reset-cells = <1>;
clock-output-names = "mmc0_config", "mmc1_config",
@@ -871,8 +878,12 @@
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
clock-names = "ahb", "tcon-ch0";
- resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
- reset-names = "lcd", "edp";
+ resets = <&ccu RST_BUS_LCD0>,
+ <&ccu RST_BUS_EDP>,
+ <&ccu RST_BUS_LVDS>;
+ reset-names = "lcd",
+ "edp",
+ "lvds";
clock-output-names = "tcon0-pixel-clock";
#clock-cells = <0>;
@@ -947,6 +958,7 @@
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x06000ca0 0x20>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
pio: pinctrl@6000800 {
@@ -1154,6 +1166,7 @@
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x08001000 0x20>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
prcm@8001400 {
diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
new file mode 100644
index 0000000..fc67e30
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * DTSI for Emlid Neutis SoMs.
+ *
+ * Copyright (C) 2019 Georgii Staroselskii <georgii.staroselskii@emlid.com>
+ */
+
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
+ post-power-on-delay-ms = <200>;
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+®_usb0_vbus {
+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ status = "okay";
+};
+
+
+&de {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 5 IRQ_TYPE_LEVEL_LOW>; /* PL5 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <®_vcc3v3>;
+ vddio-supply = <®_vcc3v3>;
+ shutdown-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+ device-wakeup-gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "LINEIN", "Line In",
+ "MIC1", "Mic",
+ "MIC2", "Mic",
+ "Mic", "MBIAS";
+};
+
+&i2c0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index b3141c9..22d533d 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -109,6 +109,7 @@
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ dma-ranges;
ranges;
display_clocks: clock@1000000 {
@@ -230,6 +231,22 @@
sid: eeprom@1c14000 {
/* compatible is in per SoC .dtsi file */
reg = <0x1c14000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ths_calibration: thermal-sensor-calibration@34 {
+ reg = <0x34 4>;
+ };
+ };
+
+ msgbox: mailbox@1c17000 {
+ compatible = "allwinner,sun8i-h3-msgbox",
+ "allwinner,sun6i-a31-msgbox";
+ reg = <0x01c17000 0x1000>;
+ clocks = <&ccu CLK_BUS_MSGBOX>;
+ resets = <&ccu RST_BUS_MSGBOX>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
};
usb_otg: usb@1c19000 {
@@ -478,6 +495,11 @@
function = "uart2";
};
+ uart2_rts_cts_pins: uart2-rts-cts-pins {
+ pins = "PA2", "PA3";
+ function = "uart2";
+ };
+
uart3_pins: uart3-pins {
pins = "PA13", "PA14";
function = "uart3";
@@ -544,6 +566,16 @@
};
};
+ mbus: dram-controller@1c62000 {
+ compatible = "allwinner,sun8i-h3-mbus";
+ reg = <0x01c62000 0x1000>;
+ clocks = <&ccu CLK_MBUS>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x00000000 0x40000000 0xc0000000>;
+ #interconnect-cells = <1>;
+ };
+
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
@@ -797,7 +829,7 @@
compatible = "allwinner,sun8i-h3-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
- <&ccu 6>;
+ <&ccu CLK_PLL_VIDEO>;
clock-names = "bus", "mod", "pll-0";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";
@@ -817,7 +849,8 @@
r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-h3-r-ccu";
reg = <0x01f01400 0x100>;
- clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 9>;
+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+ <&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -871,6 +904,21 @@
pins = "PL0", "PL1";
function = "s_i2c";
};
+
+ r_pwm_pin: r-pwm-pin {
+ pins = "PL10";
+ function = "s_pwm";
+ };
+ };
+
+ r_pwm: pwm@1f03800 {
+ compatible = "allwinner,sun8i-h3-pwm";
+ reg = <0x01f03800 0x8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_pwm_pin>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
};
};
};
diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
index 19b3b23..c44fd72 100644
--- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
+++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
@@ -128,6 +128,18 @@
cpu-supply = <®_vdd_cpux>;
};
+&cpu1 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu2 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu3 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
&de {
status = "okay";
};
diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi
new file mode 100644
index 0000000..204fba3
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2019 Chen-Yu Tsai <wens@csie.org>
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status_led {
+ label = "librecomputer:blue:status";
+ gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
+ };
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_vcc5v0>;
+ };
+
+ /* This represents the board's 5V input */
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_vcc_dram: vcc-dram {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-dram";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_vcc5v0>;
+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ enable-active-high;
+ };
+
+ reg_vcc_io: vcc-io {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-io";
+ /* This is simply a MOSFET switch */
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_vcc3v3>;
+ gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
+ };
+
+ reg_vcc_usbwifi: vcc-usbwifi {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-usbwifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_vcc5v0>;
+ gpio = <&pio 6 4 GPIO_ACTIVE_HIGH>; /* PG4 */
+ enable-active-high;
+ };
+
+ reg_vdd_cpux: vdd-cpux {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpux";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_vcc5v0>;
+ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ enable-active-high;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu1 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu2 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu3 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc_io>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&pio {
+ vcc-pa-supply = <®_vcc_io>;
+ vcc-pc-supply = <®_vcc_io>;
+ vcc-pd-supply = <®_vcc_io>;
+ vcc-pe-supply = <®_vcc_io>;
+ vcc-pf-supply = <®_vcc_io>;
+ vcc-pg-supply = <®_vcc_io>;
+};
+
+&r_pio {
+ vcc-pl-supply = <®_vcc3v3>;
+};
+
+&spi0 {
+ status = "okay";
+
+ spiflash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc_usbwifi>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi
index ff72a8e..d584da3 100644
--- a/arch/arm/boot/dts/tango4-common.dtsi
+++ b/arch/arm/boot/dts/tango4-common.dtsi
@@ -51,7 +51,7 @@
};
};
- l2cc: l2-cache-controller@20100000 {
+ l2cc: cache-controller@20100000 {
compatible = "arm,pl310-cache";
reg = <0x20100000 0x1000>;
cache-level = <2>;
@@ -85,7 +85,7 @@
};
uart: serial@10700 {
- compatible = "ralink,rt2880-uart";
+ compatible = "ralink,rt2880-uart", "ns16550a";
reg = <0x10700 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <7372800>;
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 97a5c35..c04162d 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -46,8 +46,7 @@
avdd-dsi-csi-supply = <&avdd_1v2_reg>;
panel@0 {
- compatible = "panasonic,vvx10f004b00",
- "simple-panel";
+ compatible = "panasonic,vvx10f004b00";
reg = <0>;
power-supply = <&avdd_lcd_reg>;
@@ -770,7 +769,6 @@
battery: smart-battery@b {
compatible = "ti,bq20z45", "sbs,sbs-battery";
reg = <0xb>;
- battery-name = "battery";
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <100>;
power-supplies = <&charger>;
@@ -1110,14 +1108,14 @@
};
};
- sdhci@78000400 {
+ mmc@78000400 {
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};
- sdhci@78000600 {
+ mmc@78000600 {
bus-width = <8>;
status = "okay";
non-removable;
@@ -1153,17 +1151,10 @@
default-brightness-level = <6>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-keys {
@@ -1195,83 +1186,70 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_ac_bat_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_ac_bat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- vdd_ac_bat_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_ac_bat";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ dvdd_ts_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "dvdd_ts";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
+ };
- dvdd_ts_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "dvdd_ts";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
- };
+ usb1_vbus_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&tps65090_dcdc1_reg>;
+ };
- usb1_vbus_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "usb1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
- gpio-open-drain;
- vin-supply = <&tps65090_dcdc1_reg>;
- };
+ usb3_vbus_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&tps65090_dcdc1_reg>;
+ };
- usb3_vbus_reg: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "usb2_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
- gpio-open-drain;
- vin-supply = <&tps65090_dcdc1_reg>;
- };
+ vdd_hdmi_reg: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_hdmi_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&tps65090_dcdc1_reg>;
+ };
- vdd_hdmi_reg: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "vdd_hdmi_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&tps65090_dcdc1_reg>;
- };
+ vdd_cam_1v8_reg: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_cam_1v8_reg";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ gpio = <&palmas_gpio 6 0>;
+ };
- vdd_cam_1v8_reg: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "vdd_cam_1v8_reg";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- enable-active-high;
- gpio = <&palmas_gpio 6 0>;
- };
-
- vdd_5v0_hdmi: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "VDD_5V0_HDMI_CON";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&tps65090_dcdc1_reg>;
- };
+ vdd_5v0_hdmi: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0_HDMI_CON";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&tps65090_dcdc1_reg>;
};
sound {
@@ -1296,7 +1274,13 @@
clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
<&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA114_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA114_CLK_EXTERN1>;
};
};
diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts
index 3d38355..0796017 100644
--- a/arch/arm/boot/dts/tegra114-roth.dts
+++ b/arch/arm/boot/dts/tegra114-roth.dts
@@ -37,7 +37,7 @@
dsi@54300000 {
status = "okay";
- vdd-supply = <&vdd_1v2_ap>;
+ avdd-dsi-csi-supply = <&vdd_1v2_ap>;
panel@0 {
compatible = "lg,lh500wx1-sd03";
@@ -962,7 +962,7 @@
};
/* SD card */
- sdhci@78000400 {
+ mmc@78000400 {
status = "okay";
bus-width = <4>;
vqmmc-supply = <&vddio_sdmmc3>;
@@ -971,7 +971,7 @@
};
/* eMMC */
- sdhci@78000600 {
+ mmc@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -1016,17 +1016,10 @@
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-keys {
@@ -1052,76 +1045,64 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ lcd_bl_en: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd_bl_en";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
- lcd_bl_en: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "lcd_bl_en";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- };
+ vdd_lcd: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_lcd_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vdd_1v8>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ };
- vdd_lcd: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vdd_lcd_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vdd_1v8>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
- regulator-boot-on;
- };
+ regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v8_ts";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>;
+ regulator-boot-on;
+ };
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "vdd_1v8_ts";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>;
- regulator-boot-on;
- };
+ regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_ts";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ };
- regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "vdd_3v3_ts";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
- regulator-boot-on;
- };
+ regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v8_com";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vdd_1v8>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ };
- regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "vdd_1v8_com";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vdd_1v8>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
- regulator-boot-on;
- };
-
- regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "vdd_3v3_com";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vdd_3v3_sys>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
- regulator-always-on;
- regulator-boot-on;
- };
+ regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_com";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_3v3_sys>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
};
};
diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts
index bfdd1bf..745d234 100644
--- a/arch/arm/boot/dts/tegra114-tn7.dts
+++ b/arch/arm/boot/dts/tegra114-tn7.dts
@@ -37,7 +37,7 @@
dsi@54300000 {
status = "okay";
- vdd-supply = <&vdd_1v2_ap>;
+ avdd-dsi-csi-supply = <&vdd_1v2_ap>;
panel@0 {
compatible = "lg,ld070wx3-sl01";
@@ -242,7 +242,7 @@
};
/* eMMC */
- sdhci@78000600 {
+ mmc@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -273,17 +273,10 @@
power-supply = <&lcd_bl_en>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-keys {
@@ -309,44 +302,35 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ /* FIXME: output of BQ24192 */
+ vs_sys: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VS_SYS";
+ regulator-min-microvolt = <4200000>;
+ regulator-max-microvolt = <4200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- /* FIXME: output of BQ24192 */
- vs_sys: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "VS_SYS";
- regulator-min-microvolt = <4200000>;
- regulator-max-microvolt = <4200000>;
- regulator-always-on;
- regulator-boot-on;
- };
+ lcd_bl_en: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_LCD_BL";
+ regulator-min-microvolt = <16500000>;
+ regulator-max-microvolt = <16500000>;
+ gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vs_sys>;
+ regulator-boot-on;
+ };
- lcd_bl_en: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "VDD_LCD_BL";
- regulator-min-microvolt = <16500000>;
- regulator-max-microvolt = <16500000>;
- gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vs_sys>;
- regulator-boot-on;
- };
-
- vdd_lcd: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "VD_LCD_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_1v8>;
- regulator-boot-on;
- };
+ vdd_lcd: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VD_LCD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_1v8>;
+ regulator-boot-on;
};
};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 0d7a632..fb99b3e 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra114-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra114";
@@ -17,11 +18,13 @@
};
host1x@50000000 {
- compatible = "nvidia,tegra114-host1x", "simple-bus";
+ compatible = "nvidia,tegra114-host1x";
reg = <0x50000000 0x00028000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+ interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
+ clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
iommus = <&mc TEGRA_SWGROUP_HC>;
@@ -32,7 +35,7 @@
ranges = <0x54000000 0x54000000 0x01000000>;
gr2d@54140000 {
- compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
+ compatible = "nvidia,tegra114-gr2d";
reg = <0x54140000 0x00040000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_GR2D>;
@@ -43,7 +46,7 @@
};
gr3d@54180000 {
- compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
+ compatible = "nvidia,tegra114-gr3d";
reg = <0x54180000 0x00040000>;
clocks = <&tegra_car TEGRA114_CLK_GR3D>;
resets = <&tegra_car 24>;
@@ -53,7 +56,7 @@
};
dc@54200000 {
- compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+ compatible = "nvidia,tegra114-dc";
reg = <0x54200000 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_DISP1>,
@@ -72,7 +75,7 @@
};
dc@54240000 {
- compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
+ compatible = "nvidia,tegra114-dc";
reg = <0x54240000 0x00040000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_DISP2>,
@@ -252,14 +255,14 @@
apbmisc@70000800 {
compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
- reg = <0x70000800 0x64 /* Chip revision */
- 0x70000008 0x04>; /* Strapping options */
+ reg = <0x70000800 0x64>, /* Chip revision */
+ <0x70000008 0x04>; /* Strapping options */
};
pinmux: pinmux@70000868 {
compatible = "nvidia,tegra114-pinmux";
- reg = <0x70000868 0x148 /* Pad control registers */
- 0x70003000 0x40c>; /* Mux registers */
+ reg = <0x70000868 0x148>, /* Pad control registers */
+ <0x70003000 0x40c>; /* Mux registers */
};
/*
@@ -514,11 +517,12 @@
status = "disabled";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
fuse@7000f800 {
@@ -642,41 +646,45 @@
#nvidia,mipi-calibrate-cells = <1>;
};
- sdhci@78000000 {
- compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
+ mmc@78000000 {
+ compatible = "nvidia,tegra114-sdhci";
reg = <0x78000000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
+ clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@78000200 {
- compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
+ mmc@78000200 {
+ compatible = "nvidia,tegra114-sdhci";
reg = <0x78000200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
+ clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@78000400 {
- compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
+ mmc@78000400 {
+ compatible = "nvidia,tegra114-sdhci";
reg = <0x78000400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
+ clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@78000600 {
- compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
+ mmc@78000600 {
+ compatible = "nvidia,tegra114-sdhci";
reg = <0x78000600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
+ clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
@@ -696,7 +704,8 @@
phy1: usb-phy@7d000000 {
compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
- reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
+ reg = <0x7d000000 0x4000>,
+ <0x7d000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA114_CLK_USBD>,
<&tegra_car TEGRA114_CLK_PLL_U>,
@@ -704,6 +713,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 22>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
@@ -732,7 +742,8 @@
phy3: usb-phy@7d008000 {
compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
- reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
+ reg = <0x7d008000 0x4000>,
+ <0x7d000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA114_CLK_USB3>,
<&tegra_car TEGRA114_CLK_PLL_U>,
@@ -740,6 +751,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 59>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
index d18eaf4..3240145 100644
--- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
@@ -84,7 +84,7 @@
};
};
- emc@7001b000 {
+ external-memory-controller@7001b000 {
emc-timings-1 {
nvidia,ram-code = <1>;
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
index ceb3f63..28c29b6 100644
--- a/arch/arm/boot/dts/tegra124-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -130,7 +130,7 @@
};
/* Apalis MMC1 */
- sdhci@700b0000 {
+ mmc@700b0000 {
status = "okay";
bus-width = <4>;
/* MMC1_CD# */
@@ -139,7 +139,7 @@
};
/* Apalis SD1 */
- sdhci@700b0400 {
+ mmc@700b0400 {
status = "okay";
bus-width = <4>;
/* SD1_CD# */
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
index 826b776..f3afde4 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
@@ -132,7 +132,7 @@
};
/* Apalis MMC1 */
- sdhci@700b0000 {
+ mmc@700b0000 {
status = "okay";
bus-width = <4>;
/* MMC1_CD# */
@@ -141,7 +141,7 @@
};
/* Apalis SD1 */
- sdhci@700b0400 {
+ mmc@700b0400 {
status = "okay";
bus-width = <4>;
/* SD1_CD# */
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index 0462ed2..1e30fa4 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -40,7 +40,7 @@
phy-names = "pcie-0";
status = "okay";
- pcie@0 {
+ ethernet@0,0 {
reg = <0 0 0 0 0>;
local-mac-address = [00 00 00 00 00 00];
};
@@ -1562,6 +1562,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <®_module_3v3_audio>;
VDDD-supply = <®_1v8_vddio>;
VDDIO-supply = <®_1v8_vddio>;
@@ -1916,7 +1917,7 @@
};
/* eMMC */
- sdhci@700b0600 {
+ mmc@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -2009,8 +2010,14 @@
nvidia,audio-codec = <&sgtl5000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA124_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA124_CLK_EXTERN1>;
};
thermal-zones {
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index d1e8593..608896f 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -39,7 +39,7 @@
phy-names = "pcie-0";
status = "okay";
- pcie@0 {
+ ethernet@0,0 {
reg = <0 0 0 0 0>;
local-mac-address = [00 00 00 00 00 00];
};
@@ -1555,6 +1555,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <®_module_3v3_audio>;
VDDD-supply = <®_1v8_vddio>;
VDDIO-supply = <®_1v8_vddio>;
@@ -1908,7 +1909,7 @@
};
/* eMMC */
- sdhci@700b0600 {
+ mmc@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -2001,8 +2002,14 @@
nvidia,audio-codec = <&sgtl5000>;
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA124_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA124_CLK_EXTERN1>;
};
thermal-zones {
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
index 784a529..861d3f2 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
@@ -79,7 +79,7 @@
};
};
- emc@7001b000 {
+ external-memory-controller@7001b000 {
emc-timings-3 {
nvidia,ram-code = <3>;
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index d5fd642..414cd1c 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1785,7 +1785,7 @@
/* Micro A/B */
usb2-0 {
status = "okay";
- mode = "otg";
+ mode = "host";
};
/* Mini PCIe */
@@ -1810,7 +1810,7 @@
};
/* SD card */
- sdhci@700b0400 {
+ mmc@700b0400 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
@@ -1820,7 +1820,7 @@
};
/* eMMC */
- sdhci@700b0600 {
+ mmc@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -1868,17 +1868,10 @@
vbus-supply = <&vdd_usb3_vbus>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
cpus {
@@ -1899,145 +1892,127 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_mux: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "+VDD_MUX";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- vdd_mux: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "+VDD_MUX";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- };
+ vdd_5v0_sys: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_5v0_sys: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "+5V_SYS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_mux>;
- };
+ vdd_3v3_sys: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_SYS";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_3v3_sys: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "+3.3V_SYS";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_mux>;
- };
+ vdd_3v3_run: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_RUN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
- vdd_3v3_run: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "+3.3V_RUN";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
- };
+ vdd_3v3_hdmi: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_3v3_run>;
+ };
- vdd_3v3_hdmi: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vdd_3v3_run>;
- };
+ vdd_usb1_vbus: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "+USB0_VBUS_SW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_usb1_vbus: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "+USB0_VBUS_SW";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_usb3_vbus: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_USB_HS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_usb3_vbus: regulator@8 {
- compatible = "regulator-fixed";
- reg = <8>;
- regulator-name = "+5V_USB_HS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_3v3_lp0: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_LP0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
- vdd_3v3_lp0: regulator@10 {
- compatible = "regulator-fixed";
- reg = <10>;
- regulator-name = "+3.3V_LP0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
- };
+ vdd_hdmi_pll: regulator@8 {
+ compatible = "regulator-fixed";
+ regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+ vin-supply = <&vdd_1v05_run>;
+ };
- vdd_hdmi_pll: regulator@11 {
- compatible = "regulator-fixed";
- reg = <11>;
- regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
- vin-supply = <&vdd_1v05_run>;
- };
+ vdd_5v0_hdmi: regulator@9 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_HDMI_CON";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_5v0_hdmi: regulator@12 {
- compatible = "regulator-fixed";
- reg = <12>;
- regulator-name = "+5V_HDMI_CON";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
+ /* Molex power connector */
+ vdd_5v0_sata: regulator@10 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_SATA";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- /* Molex power connector */
- vdd_5v0_sata: regulator@13 {
- compatible = "regulator-fixed";
- reg = <13>;
- regulator-name = "+5V_SATA";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
-
- vdd_12v0_sata: regulator@14 {
- compatible = "regulator-fixed";
- reg = <14>;
- regulator-name = "+12V_SATA";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_mux>;
- };
+ vdd_12v0_sata: regulator@11 {
+ compatible = "regulator-fixed";
+ regulator-name = "+12V_SATA";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_mux>;
};
sound {
@@ -2058,8 +2033,14 @@
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA124_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA124_CLK_EXTERN1>;
};
thermal-zones {
diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
index 9af21fe..c91647d 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
@@ -1,5 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/ {
+ apbmisc@70000800 {
+ nvidia,long-ram-code;
+ };
+
clock@60006000 {
emc-timings-1 {
nvidia,ram-code = <1>;
@@ -52,7 +56,154 @@
clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
clock-names = "emc-parent";
};
- /* TODO: Add 528MHz frequency */
+ timing-528000000 {
+ clock-frequency = <528000000>;
+ nvidia,parent-clock-frequency = <528000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+ clock-names = "emc-parent";
+ };
+ timing-600000000 {
+ clock-frequency = <600000000>;
+ nvidia,parent-clock-frequency = <600000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
+ clock-names = "emc-parent";
+ };
+ timing-792000000 {
+ clock-frequency = <792000000>;
+ nvidia,parent-clock-frequency = <792000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+ clock-names = "emc-parent";
+ };
+ };
+
+ emc-timings-4 {
+ nvidia,ram-code = <4>;
+
+ timing-12750000 {
+ clock-frequency = <12750000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-20400000 {
+ clock-frequency = <20400000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-40800000 {
+ clock-frequency = <40800000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-68000000 {
+ clock-frequency = <68000000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-102000000 {
+ clock-frequency = <102000000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-204000000 {
+ clock-frequency = <204000000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-300000000 {
+ clock-frequency = <300000000>;
+ nvidia,parent-clock-frequency = <600000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
+ clock-names = "emc-parent";
+ };
+ timing-396000000 {
+ clock-frequency = <396000000>;
+ nvidia,parent-clock-frequency = <792000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
+ clock-names = "emc-parent";
+ };
+ timing-528000000 {
+ clock-frequency = <528000000>;
+ nvidia,parent-clock-frequency = <528000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+ clock-names = "emc-parent";
+ };
+ timing-600000000 {
+ clock-frequency = <600000000>;
+ nvidia,parent-clock-frequency = <600000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
+ clock-names = "emc-parent";
+ };
+ timing-792000000 {
+ clock-frequency = <792000000>;
+ nvidia,parent-clock-frequency = <792000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+ clock-names = "emc-parent";
+ };
+ };
+
+ emc-timings-6 {
+ nvidia,ram-code = <6>;
+
+ timing-12750000 {
+ clock-frequency = <12750000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-20400000 {
+ clock-frequency = <20400000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-40800000 {
+ clock-frequency = <40800000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-68000000 {
+ clock-frequency = <68000000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-102000000 {
+ clock-frequency = <102000000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-204000000 {
+ clock-frequency = <204000000>;
+ nvidia,parent-clock-frequency = <408000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "emc-parent";
+ };
+ timing-300000000 {
+ clock-frequency = <300000000>;
+ nvidia,parent-clock-frequency = <600000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
+ clock-names = "emc-parent";
+ };
+ timing-396000000 {
+ clock-frequency = <396000000>;
+ nvidia,parent-clock-frequency = <792000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
+ clock-names = "emc-parent";
+ };
+ timing-528000000 {
+ clock-frequency = <528000000>;
+ nvidia,parent-clock-frequency = <528000000>;
+ clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+ clock-names = "emc-parent";
+ };
timing-600000000 {
clock-frequency = <600000000>;
nvidia,parent-clock-frequency = <600000000>;
@@ -68,7 +219,7 @@
};
};
- emc@7001b000 {
+ external-memory-controller@7001b000 {
emc-timings-1 {
nvidia,ram-code = <1>;
@@ -94,149 +245,149 @@
nvidia,emc-zcal-interval = <0x00000000>;
nvidia,emc-configuration = <
- 0x00000000
- 0x00000003
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000004
- 0x0000000a
- 0x00000003
- 0x0000000b
- 0x00000000
- 0x00000000
- 0x00000003
- 0x00000003
- 0x00000000
- 0x00000006
- 0x00000006
- 0x00000006
- 0x00000002
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00010000
- 0x00000003
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000004
- 0x0000000c
- 0x0000000d
- 0x0000000f
- 0x00000060
- 0x00000000
- 0x00000018
- 0x00000002
- 0x00000002
- 0x00000001
- 0x00000000
- 0x00000007
- 0x0000000f
- 0x00000005
- 0x00000005
- 0x00000004
- 0x00000005
- 0x00000004
- 0x00000000
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00000064
- 0x00000000
- 0x00000000
- 0x00000000
- 0x106aa298
- 0x002c00a0
- 0x00008000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x000fc000
- 0x000fc000
- 0x000fc000
- 0x000fc000
- 0x0000fc00
- 0x0000fc00
- 0x0000fc00
- 0x0000fc00
- 0x10000280
- 0x00000000
- 0x00111111
- 0x00000000
- 0x00000000
- 0x77ffc081
- 0x00000303
- 0x81f1f108
- 0x07070004
- 0x0000003f
- 0x016eeeee
- 0x51451400
- 0x00514514
- 0x00514514
- 0x51451400
- 0x0000003f
- 0x00000007
- 0x00000000
- 0x00000042
- 0x000c000c
- 0x00000000
- 0x00000003
- 0x0000f2f3
- 0x800001c5
- 0x0000000a
+ 0x00000000 /* EMC_RC */
+ 0x00000003 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000000 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000060 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000005 /* EMC_TXSR */
+ 0x00000005 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000000 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000064 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000007 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
>;
};
@@ -262,149 +413,149 @@
nvidia,emc-zcal-interval = <0x00000000>;
nvidia,emc-configuration = <
- 0x00000000
- 0x00000005
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000004
- 0x0000000a
- 0x00000003
- 0x0000000b
- 0x00000000
- 0x00000000
- 0x00000003
- 0x00000003
- 0x00000000
- 0x00000006
- 0x00000006
- 0x00000006
- 0x00000002
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00010000
- 0x00000003
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000004
- 0x0000000c
- 0x0000000d
- 0x0000000f
- 0x0000009a
- 0x00000000
- 0x00000026
- 0x00000002
- 0x00000002
- 0x00000001
- 0x00000000
- 0x00000007
- 0x0000000f
- 0x00000006
- 0x00000006
- 0x00000004
- 0x00000005
- 0x00000004
- 0x00000000
- 0x00000000
- 0x00000005
- 0x00000005
- 0x000000a0
- 0x00000000
- 0x00000000
- 0x00000000
- 0x106aa298
- 0x002c00a0
- 0x00008000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x000fc000
- 0x000fc000
- 0x000fc000
- 0x000fc000
- 0x0000fc00
- 0x0000fc00
- 0x0000fc00
- 0x0000fc00
- 0x10000280
- 0x00000000
- 0x00111111
- 0x00000000
- 0x00000000
- 0x77ffc081
- 0x00000303
- 0x81f1f108
- 0x07070004
- 0x0000003f
- 0x016eeeee
- 0x51451400
- 0x00514514
- 0x00514514
- 0x51451400
- 0x0000003f
- 0x0000000b
- 0x00000000
- 0x00000042
- 0x000c000c
- 0x00000000
- 0x00000003
- 0x0000f2f3
- 0x8000023a
- 0x0000000a
+ 0x00000000 /* EMC_RC */
+ 0x00000005 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000000 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x0000009a /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000006 /* EMC_TXSR */
+ 0x00000006 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000000 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x000000a0 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x0000000b /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
>;
};
@@ -430,149 +581,149 @@
nvidia,emc-zcal-interval = <0x00000000>;
nvidia,emc-configuration = <
- 0x00000001
- 0x0000000a
- 0x00000000
- 0x00000001
- 0x00000000
- 0x00000004
- 0x0000000a
- 0x00000003
- 0x0000000b
- 0x00000000
- 0x00000000
- 0x00000003
- 0x00000003
- 0x00000000
- 0x00000006
- 0x00000006
- 0x00000006
- 0x00000002
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00010000
- 0x00000003
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000004
- 0x0000000c
- 0x0000000d
- 0x0000000f
- 0x00000134
- 0x00000000
- 0x0000004d
- 0x00000002
- 0x00000002
- 0x00000001
- 0x00000000
- 0x00000008
- 0x0000000f
- 0x0000000c
- 0x0000000c
- 0x00000004
- 0x00000005
- 0x00000004
- 0x00000000
- 0x00000000
- 0x00000005
- 0x00000005
- 0x0000013f
- 0x00000000
- 0x00000000
- 0x00000000
- 0x106aa298
- 0x002c00a0
- 0x00008000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x000fc000
- 0x000fc000
- 0x000fc000
- 0x000fc000
- 0x0000fc00
- 0x0000fc00
- 0x0000fc00
- 0x0000fc00
- 0x10000280
- 0x00000000
- 0x00111111
- 0x00000000
- 0x00000000
- 0x77ffc081
- 0x00000303
- 0x81f1f108
- 0x07070004
- 0x0000003f
- 0x016eeeee
- 0x51451400
- 0x00514514
- 0x00514514
- 0x51451400
- 0x0000003f
- 0x00000015
- 0x00000000
- 0x00000042
- 0x000c000c
- 0x00000000
- 0x00000003
- 0x0000f2f3
- 0x80000370
- 0x0000000a
+ 0x00000001 /* EMC_RC */
+ 0x0000000a /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000001 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000134 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000008 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x0000000c /* EMC_TXSR */
+ 0x0000000c /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000000 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x0000013f /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000015 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
>;
};
@@ -598,149 +749,149 @@
nvidia,emc-zcal-interval = <0x00000000>;
nvidia,emc-configuration = <
- 0x00000003
- 0x00000011
- 0x00000000
- 0x00000002
- 0x00000000
- 0x00000004
- 0x0000000a
- 0x00000003
- 0x0000000b
- 0x00000000
- 0x00000000
- 0x00000003
- 0x00000003
- 0x00000000
- 0x00000006
- 0x00000006
- 0x00000006
- 0x00000002
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00010000
- 0x00000003
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000004
- 0x0000000c
- 0x0000000d
- 0x0000000f
- 0x00000202
- 0x00000000
- 0x00000080
- 0x00000002
- 0x00000002
- 0x00000001
- 0x00000000
- 0x0000000f
- 0x0000000f
- 0x00000013
- 0x00000013
- 0x00000004
- 0x00000005
- 0x00000004
- 0x00000001
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00000213
- 0x00000000
- 0x00000000
- 0x00000000
- 0x106aa298
- 0x002c00a0
- 0x00008000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x000fc000
- 0x000fc000
- 0x000fc000
- 0x000fc000
- 0x0000fc00
- 0x0000fc00
- 0x0000fc00
- 0x0000fc00
- 0x10000280
- 0x00000000
- 0x00111111
- 0x00000000
- 0x00000000
- 0x77ffc081
- 0x00000303
- 0x81f1f108
- 0x07070004
- 0x0000003f
- 0x016eeeee
- 0x51451400
- 0x00514514
- 0x00514514
- 0x51451400
- 0x0000003f
- 0x00000022
- 0x00000000
- 0x00000042
- 0x000c000c
- 0x00000000
- 0x00000003
- 0x0000f2f3
- 0x8000050e
- 0x0000000a
+ 0x00000003 /* EMC_RC */
+ 0x00000011 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000002 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000202 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x0000000f /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000013 /* EMC_TXSR */
+ 0x00000013 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000001 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000213 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000022 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
>;
};
@@ -766,149 +917,149 @@
nvidia,emc-zcal-interval = <0x00000000>;
nvidia,emc-configuration = <
- 0x00000004
- 0x0000001a
- 0x00000000
- 0x00000003
- 0x00000001
- 0x00000004
- 0x0000000a
- 0x00000003
- 0x0000000b
- 0x00000001
- 0x00000001
- 0x00000003
- 0x00000003
- 0x00000000
- 0x00000006
- 0x00000006
- 0x00000006
- 0x00000002
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00010000
- 0x00000003
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000004
- 0x0000000c
- 0x0000000d
- 0x0000000f
- 0x00000304
- 0x00000000
- 0x000000c1
- 0x00000002
- 0x00000002
- 0x00000001
- 0x00000000
- 0x00000018
- 0x0000000f
- 0x0000001c
- 0x0000001c
- 0x00000004
- 0x00000005
- 0x00000004
- 0x00000003
- 0x00000000
- 0x00000005
- 0x00000005
- 0x0000031c
- 0x00000000
- 0x00000000
- 0x00000000
- 0x106aa298
- 0x002c00a0
- 0x00008000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x000fc000
- 0x000fc000
- 0x000fc000
- 0x000fc000
- 0x0000fc00
- 0x0000fc00
- 0x0000fc00
- 0x0000fc00
- 0x10000280
- 0x00000000
- 0x00111111
- 0x00000000
- 0x00000000
- 0x77ffc081
- 0x00000303
- 0x81f1f108
- 0x07070004
- 0x0000003f
- 0x016eeeee
- 0x51451400
- 0x00514514
- 0x00514514
- 0x51451400
- 0x0000003f
- 0x00000033
- 0x00000000
- 0x00000042
- 0x000c000c
- 0x00000000
- 0x00000003
- 0x0000f2f3
- 0x80000713
- 0x0000000a
+ 0x00000004 /* EMC_RC */
+ 0x0000001a /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000003 /* EMC_RAS */
+ 0x00000001 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000001 /* EMC_RD_RCD */
+ 0x00000001 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000304 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000018 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x0000001c /* EMC_TXSR */
+ 0x0000001c /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000003 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x0000031c /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000033 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
>;
};
@@ -934,149 +1085,149 @@
nvidia,emc-zcal-interval = <0x00020000>;
nvidia,emc-configuration = <
- 0x00000009
- 0x00000035
- 0x00000000
- 0x00000007
- 0x00000002
- 0x00000005
- 0x0000000a
- 0x00000003
- 0x0000000b
- 0x00000002
- 0x00000002
- 0x00000003
- 0x00000003
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00000006
- 0x00000002
- 0x00000000
- 0x00000004
- 0x00000006
- 0x00010000
- 0x00000003
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000003
- 0x0000000d
- 0x0000000f
- 0x00000011
- 0x00000607
- 0x00000000
- 0x00000181
- 0x00000002
- 0x00000002
- 0x00000001
- 0x00000000
- 0x00000032
- 0x0000000f
- 0x00000038
- 0x00000038
- 0x00000004
- 0x00000005
- 0x00000004
- 0x00000007
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00000638
- 0x00000000
- 0x00000000
- 0x00000000
- 0x106aa298
- 0x002c00a0
- 0x00008000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00064000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00004000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00090000
- 0x00090000
- 0x00094000
- 0x00094000
- 0x00009400
- 0x00009000
- 0x00009000
- 0x00009000
- 0x10000280
- 0x00000000
- 0x00111111
- 0x00000000
- 0x00000000
- 0x77ffc081
- 0x00000303
- 0x81f1f108
- 0x07070004
- 0x0000003f
- 0x016eeeee
- 0x51451400
- 0x00514514
- 0x00514514
- 0x51451400
- 0x0000003f
- 0x00000066
- 0x00000000
- 0x00000100
- 0x000c000c
- 0x00000000
- 0x00000003
- 0x0000d2b3
- 0x80000d22
- 0x0000000a
+ 0x00000009 /* EMC_RC */
+ 0x00000035 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000007 /* EMC_RAS */
+ 0x00000002 /* EMC_RP */
+ 0x00000005 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000002 /* EMC_RD_RCD */
+ 0x00000002 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000004 /* EMC_EINPUT */
+ 0x00000006 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000003 /* EMC_QRST */
+ 0x0000000d /* EMC_QSAFE */
+ 0x0000000f /* EMC_RDV */
+ 0x00000011 /* EMC_RDV_MASK */
+ 0x00000607 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000032 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000038 /* EMC_TXSR */
+ 0x00000038 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000007 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000638 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00090000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00090000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00094000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00094000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00009400 /* EMC_DLL_XFORM_DQ4 */
+ 0x00009000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00009000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00009000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000066 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000d2b3 /* EMC_CFG_PIPE */
+ 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
>;
};
@@ -1102,149 +1253,149 @@
nvidia,emc-zcal-interval = <0x00020000>;
nvidia,emc-configuration = <
- 0x0000000d
- 0x0000004c
- 0x00000000
- 0x00000009
- 0x00000003
- 0x00000004
- 0x00000008
- 0x00000002
- 0x00000009
- 0x00000003
- 0x00000003
- 0x00000002
- 0x00000002
- 0x00000000
- 0x00000003
- 0x00000003
- 0x00000005
- 0x00000002
- 0x00000000
- 0x00000002
- 0x00000007
- 0x00020000
- 0x00000003
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000001
- 0x0000000e
- 0x00000010
- 0x00000012
- 0x000008e4
- 0x00000000
- 0x00000239
- 0x00000001
- 0x00000008
- 0x00000001
- 0x00000000
- 0x0000004a
- 0x0000000e
- 0x00000051
- 0x00000200
- 0x00000004
- 0x00000005
- 0x00000004
- 0x00000009
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00000924
- 0x00000000
- 0x00000000
- 0x00000000
- 0x104ab098
- 0x002c00a0
- 0x00008000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00098000
- 0x00098000
- 0x00000000
- 0x00098000
- 0x00098000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00060000
- 0x00060000
- 0x00060000
- 0x00060000
- 0x00006000
- 0x00006000
- 0x00006000
- 0x00006000
- 0x10000280
- 0x00000000
- 0x00111111
- 0x00000000
- 0x00000000
- 0x77ffc081
- 0x00000101
- 0x81f1f108
- 0x07070004
- 0x00000000
- 0x016eeeee
- 0x51451420
- 0x00514514
- 0x00514514
- 0x51451400
- 0x0000003f
- 0x00000096
- 0x00000000
- 0x00000100
- 0x0174000c
- 0x00000000
- 0x00000003
- 0x000052a3
- 0x800012d7
- 0x00000009
+ 0x0000000d /* EMC_RC */
+ 0x0000004c /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000009 /* EMC_RAS */
+ 0x00000003 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x00000008 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x00000009 /* EMC_W2P */
+ 0x00000003 /* EMC_RD_RCD */
+ 0x00000003 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000003 /* EMC_WDV */
+ 0x00000003 /* EMC_WDV_MASK */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000002 /* EMC_EINPUT */
+ 0x00000007 /* EMC_EINPUT_DURATION */
+ 0x00020000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000001 /* EMC_QRST */
+ 0x0000000e /* EMC_QSAFE */
+ 0x00000010 /* EMC_RDV */
+ 0x00000012 /* EMC_RDV_MASK */
+ 0x000008e4 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001 /* EMC_PDEX2WR */
+ 0x00000008 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x0000004a /* EMC_AR2PDEN */
+ 0x0000000e /* EMC_RW2PDEN */
+ 0x00000051 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000009 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000924 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00030000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ4 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000096 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x0174000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000052a3 /* EMC_CFG_PIPE */
+ 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x00000009 /* EMC_QPOP */
>;
};
@@ -1270,149 +1421,317 @@
nvidia,emc-zcal-interval = <0x00020000>;
nvidia,emc-configuration = <
- 0x00000012
- 0x00000065
- 0x00000000
- 0x0000000c
- 0x00000004
- 0x00000005
- 0x00000008
- 0x00000002
- 0x0000000a
- 0x00000004
- 0x00000004
- 0x00000002
- 0x00000002
- 0x00000000
- 0x00000003
- 0x00000003
- 0x00000005
- 0x00000002
- 0x00000000
- 0x00000001
- 0x00000008
- 0x00020000
- 0x00000003
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x0000000f
- 0x00000010
- 0x00000012
- 0x00000bd1
- 0x00000000
- 0x000002f4
- 0x00000001
- 0x00000008
- 0x00000001
- 0x00000000
- 0x00000063
- 0x0000000f
- 0x0000006b
- 0x00000200
- 0x00000004
- 0x00000005
- 0x00000004
- 0x0000000d
- 0x00000000
- 0x00000005
- 0x00000005
- 0x00000c11
- 0x00000000
- 0x00000000
- 0x00000000
- 0x104ab098
- 0x002c00a0
- 0x00008000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00030000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00070000
- 0x00070000
- 0x00000000
- 0x00070000
- 0x00070000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00048000
- 0x00048000
- 0x00048000
- 0x00048000
- 0x00004800
- 0x00004800
- 0x00004800
- 0x00004800
- 0x10000280
- 0x00000000
- 0x00111111
- 0x00000000
- 0x00000000
- 0x77ffc081
- 0x00000101
- 0x81f1f108
- 0x07070004
- 0x00000000
- 0x016eeeee
- 0x51451420
- 0x00514514
- 0x00514514
- 0x51451400
- 0x0000003f
- 0x000000c6
- 0x00000000
- 0x00000100
- 0x015b000c
- 0x00000000
- 0x00000003
- 0x000052a3
- 0x8000188b
- 0x00000009
+ 0x00000012 /* EMC_RC */
+ 0x00000065 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x0000000c /* EMC_RAS */
+ 0x00000004 /* EMC_RP */
+ 0x00000005 /* EMC_R2W */
+ 0x00000008 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x0000000a /* EMC_W2P */
+ 0x00000004 /* EMC_RD_RCD */
+ 0x00000004 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000003 /* EMC_WDV */
+ 0x00000003 /* EMC_WDV_MASK */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000001 /* EMC_EINPUT */
+ 0x00000008 /* EMC_EINPUT_DURATION */
+ 0x00020000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000000 /* EMC_QRST */
+ 0x0000000f /* EMC_QSAFE */
+ 0x00000010 /* EMC_RDV */
+ 0x00000012 /* EMC_RDV_MASK */
+ 0x00000bd1 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001 /* EMC_PDEX2WR */
+ 0x00000008 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000063 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x0000006b /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x0000000d /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000c11 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00030000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x000000c6 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x015b000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000052a3 /* EMC_CFG_PIPE */
+ 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */
+ 0x00000009 /* EMC_QPOP */
+ >;
+ };
+
+ timing-528000000 {
+ clock-frequency = <528000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73300000>;
+ nvidia,emc-cfg-2 = <0x0000089d>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80000941>;
+ nvidia,emc-mrs-wait-cnt = <0x013a000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0123133d>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x00000018 /* EMC_RC */
+ 0x00000088 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000011 /* EMC_RAS */
+ 0x00000006 /* EMC_RP */
+ 0x00000006 /* EMC_R2W */
+ 0x00000009 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x0000000d /* EMC_W2P */
+ 0x00000006 /* EMC_RD_RCD */
+ 0x00000006 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000003 /* EMC_WDV */
+ 0x00000003 /* EMC_WDV_MASK */
+ 0x00000007 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000002 /* EMC_EINPUT */
+ 0x00000009 /* EMC_EINPUT_DURATION */
+ 0x00040000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000001 /* EMC_QRST */
+ 0x00000010 /* EMC_QSAFE */
+ 0x00000013 /* EMC_RDV */
+ 0x00000015 /* EMC_RDV_MASK */
+ 0x00000fd6 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x0000000b /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000084 /* EMC_AR2PDEN */
+ 0x00000012 /* EMC_RW2PDEN */
+ 0x0000008f /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000013 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000006 /* EMC_TCLKSTABLE */
+ 0x00000006 /* EMC_TCLKSTOP */
+ 0x00001017 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0xe01200b1 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0000000a /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS8 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS9 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS10 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS11 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS12 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS13 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS14 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x013a000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000042a0 /* EMC_CFG_PIPE */
+ 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000b /* EMC_QPOP */
>;
};
@@ -1438,149 +1757,149 @@
nvidia,emc-zcal-interval = <0x00020000>;
nvidia,emc-configuration = <
- 0x0000001c
- 0x0000009a
- 0x00000000
- 0x00000013
- 0x00000007
- 0x00000007
- 0x0000000b
- 0x00000003
- 0x00000010
- 0x00000007
- 0x00000007
- 0x00000002
- 0x00000002
- 0x00000000
- 0x00000005
- 0x00000005
- 0x0000000a
- 0x00000002
- 0x00000000
- 0x00000003
- 0x0000000b
- 0x00070000
- 0x00000003
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000002
- 0x00000012
- 0x00000016
- 0x00000018
- 0x00001208
- 0x00000000
- 0x00000482
- 0x00000002
- 0x0000000d
- 0x00000001
- 0x00000000
- 0x00000096
- 0x00000015
- 0x000000a2
- 0x00000200
- 0x00000004
- 0x00000005
- 0x00000004
- 0x00000015
- 0x00000000
- 0x00000006
- 0x00000006
- 0x00001249
- 0x00000000
- 0x00000000
- 0x00000000
- 0x104ab098
- 0xe00e00b1
- 0x00008000
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00048000
- 0x00048000
- 0x00000000
- 0x00048000
- 0x00048000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000004
- 0x00000004
- 0x00000002
- 0x00000005
- 0x00000006
- 0x00000003
- 0x00000006
- 0x00000005
- 0x00000004
- 0x00000004
- 0x00000002
- 0x00000005
- 0x00000006
- 0x00000003
- 0x00000006
- 0x00000005
- 0x0000000e
- 0x0000000e
- 0x0000000e
- 0x0000000e
- 0x0000000e
- 0x0000000e
- 0x0000000e
- 0x0000000e
- 0x100002a0
- 0x00000000
- 0x00111111
- 0x00000000
- 0x00000000
- 0x77ffc085
- 0x00000101
- 0x81f1f108
- 0x07070004
- 0x00000000
- 0x016eeeee
- 0x51451420
- 0x00514514
- 0x00514514
- 0x51451400
- 0x0606003f
- 0x00000000
- 0x00000000
- 0x00000100
- 0x0128000c
- 0x00000000
- 0x00000003
- 0x000040a0
- 0x800024aa
- 0x0000000e
+ 0x0000001c /* EMC_RC */
+ 0x0000009a /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000013 /* EMC_RAS */
+ 0x00000007 /* EMC_RP */
+ 0x00000007 /* EMC_R2W */
+ 0x0000000b /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x00000010 /* EMC_W2P */
+ 0x00000007 /* EMC_RD_RCD */
+ 0x00000007 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_WDV_MASK */
+ 0x0000000a /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000003 /* EMC_EINPUT */
+ 0x0000000b /* EMC_EINPUT_DURATION */
+ 0x00070000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000002 /* EMC_QRST */
+ 0x00000012 /* EMC_QSAFE */
+ 0x00000016 /* EMC_RDV */
+ 0x00000018 /* EMC_RDV_MASK */
+ 0x00001208 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x0000000d /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000096 /* EMC_AR2PDEN */
+ 0x00000015 /* EMC_RW2PDEN */
+ 0x000000a2 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000015 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000006 /* EMC_TCLKSTABLE */
+ 0x00000006 /* EMC_TCLKSTOP */
+ 0x00001249 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0xe00e00b1 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0000000a /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS8 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS9 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS10 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS11 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS12 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS13 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS14 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x0128000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000040a0 /* EMC_CFG_PIPE */
+ 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000e /* EMC_QPOP */
>;
};
@@ -1606,152 +1925,3855 @@
nvidia,emc-zcal-interval = <0x00020000>;
nvidia,emc-configuration = <
- 0x00000025
- 0x000000cc
- 0x00000000
- 0x0000001a
- 0x00000009
- 0x00000008
- 0x0000000d
- 0x00000004
- 0x00000013
- 0x00000009
- 0x00000009
- 0x00000003
- 0x00000002
- 0x00000000
- 0x00000006
- 0x00000006
- 0x0000000b
- 0x00000002
- 0x00000000
- 0x00000002
- 0x0000000d
- 0x00080000
- 0x00000004
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000001
- 0x00000014
- 0x00000018
- 0x0000001a
- 0x000017e2
- 0x00000000
- 0x000005f8
- 0x00000003
- 0x00000011
- 0x00000001
- 0x00000000
- 0x000000c6
- 0x00000018
- 0x000000d6
- 0x00000200
- 0x00000005
- 0x00000006
- 0x00000005
- 0x0000001d
- 0x00000000
- 0x00000008
- 0x00000008
- 0x00001822
- 0x00000000
- 0x80000005
- 0x00000000
- 0x104ab198
- 0xe00700b1
- 0x00008000
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000005
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00034000
- 0x00034000
- 0x00000000
- 0x00034000
- 0x00034000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000000
- 0x00000008
- 0x00000008
- 0x00000005
- 0x00000009
- 0x00000009
- 0x00000007
- 0x00000009
- 0x00000008
- 0x00000008
- 0x00000008
- 0x00000005
- 0x00000009
- 0x00000009
- 0x00000007
- 0x00000009
- 0x00000008
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x0000000a
- 0x100002a0
- 0x00000000
- 0x00111111
- 0x00000000
- 0x00000000
- 0x77ffc085
- 0x00000101
- 0x81f1f108
- 0x07070004
- 0x00000000
- 0x016eeeee
- 0x61861820
- 0x00514514
- 0x00514514
- 0x61861800
- 0x0606003f
- 0x00000000
- 0x00000000
- 0x00000100
- 0x00f8000c
- 0x00000007
- 0x00000004
- 0x00004080
- 0x80003012
- 0x0000000f
+ 0x00000025 /* EMC_RC */
+ 0x000000cc /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x0000001a /* EMC_RAS */
+ 0x00000009 /* EMC_RP */
+ 0x00000008 /* EMC_R2W */
+ 0x0000000d /* EMC_W2R */
+ 0x00000004 /* EMC_R2P */
+ 0x00000013 /* EMC_W2P */
+ 0x00000009 /* EMC_RD_RCD */
+ 0x00000009 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x0000000b /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000002 /* EMC_EINPUT */
+ 0x0000000d /* EMC_EINPUT_DURATION */
+ 0x00080000 /* EMC_PUTERM_EXTRA */
+ 0x00000004 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000001 /* EMC_QRST */
+ 0x00000014 /* EMC_QSAFE */
+ 0x00000018 /* EMC_RDV */
+ 0x0000001a /* EMC_RDV_MASK */
+ 0x000017e2 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000003 /* EMC_PDEX2WR */
+ 0x00000011 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x000000c6 /* EMC_AR2PDEN */
+ 0x00000018 /* EMC_RW2PDEN */
+ 0x000000d6 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000005 /* EMC_TCKE */
+ 0x00000006 /* EMC_TCKESR */
+ 0x00000005 /* EMC_TPD */
+ 0x0000001d /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000008 /* EMC_TCLKSTABLE */
+ 0x00000008 /* EMC_TCLKSTOP */
+ 0x00001822 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x80000005 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab198 /* EMC_FBIO_CFG5 */
+ 0xe00700b1 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00000005 /* EMC_DLL_XFORM_DQS0 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS1 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS2 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS3 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS4 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS5 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS6 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS8 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS9 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS10 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS11 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS12 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS13 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS14 */
+ 0x00000005 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00034000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00034000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00034000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00034000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x61861820 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x61861800 /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x00f8000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000007 /* EMC_CTT */
+ 0x00000004 /* EMC_CTT_DURATION */
+ 0x00004080 /* EMC_CFG_PIPE */
+ 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000f /* EMC_QPOP */
+ >;
+ };
+ };
+
+ emc-timings-4 {
+ nvidia,ram-code = <4>;
+
+ timing-12750000 {
+ clock-frequency = <12750000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x000008c5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100003>;
+ nvidia,emc-mode-2 = <0x00200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00000000>;
+
+ nvidia,emc-configuration = <
+ 0x00000000 /* EMC_RC */
+ 0x00000004 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000000 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000060 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000005 /* EMC_TXSR */
+ 0x00000005 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000000 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000064 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ4 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000007 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
>;
};
+ timing-20400000 {
+ clock-frequency = <20400000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x000008c5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100003>;
+ nvidia,emc-mode-2 = <0x00200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00000000>;
+
+ nvidia,emc-configuration = <
+ 0x00000000 /* EMC_RC */
+ 0x00000007 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000000 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x0000009a /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000008 /* EMC_TXSR */
+ 0x00000008 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000000 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x000000a0 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ4 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x0000000b /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-40800000 {
+ clock-frequency = <40800000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x000008c5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100003>;
+ nvidia,emc-mode-2 = <0x00200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00000000>;
+
+ nvidia,emc-configuration = <
+ 0x00000001 /* EMC_RC */
+ 0x0000000e /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000001 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000134 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x0000000c /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x0000000f /* EMC_TXSR */
+ 0x0000000f /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000000 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x0000013f /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ4 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000015 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-68000000 {
+ clock-frequency = <68000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x000008c5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100003>;
+ nvidia,emc-mode-2 = <0x00200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00000000>;
+
+ nvidia,emc-configuration = <
+ 0x00000003 /* EMC_RC */
+ 0x00000017 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000002 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000202 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000015 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000019 /* EMC_TXSR */
+ 0x00000019 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000001 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000213 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ4 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000022 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x000008c5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100003>;
+ nvidia,emc-mode-2 = <0x00200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00000000>;
+
+ nvidia,emc-configuration = <
+ 0x00000004 /* EMC_RC */
+ 0x00000023 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000003 /* EMC_RAS */
+ 0x00000001 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000001 /* EMC_RD_RCD */
+ 0x00000001 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000304 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000021 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000025 /* EMC_TXSR */
+ 0x00000025 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000003 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x0000031c /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ4 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00008000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000033 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x0000088d>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100003>;
+ nvidia,emc-mode-2 = <0x00200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x00000009 /* EMC_RC */
+ 0x00000047 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000006 /* EMC_RAS */
+ 0x00000002 /* EMC_RP */
+ 0x00000005 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000002 /* EMC_RD_RCD */
+ 0x00000002 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000004 /* EMC_EINPUT */
+ 0x00000006 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000003 /* EMC_QRST */
+ 0x0000000d /* EMC_QSAFE */
+ 0x0000000f /* EMC_RDV */
+ 0x00000011 /* EMC_RDV_MASK */
+ 0x00000607 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000044 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x0000004a /* EMC_TXSR */
+ 0x0000004a /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000007 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000638 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00090000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00090000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00094000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00094000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00009400 /* EMC_DLL_XFORM_DQ4 */
+ 0x00009000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00009000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00009000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000066 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000d2b3 /* EMC_CFG_PIPE */
+ 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-300000000 {
+ clock-frequency = <300000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73340000>;
+ nvidia,emc-cfg-2 = <0x000008d5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100002>;
+ nvidia,emc-mode-2 = <0x00200000>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00000321>;
+ nvidia,emc-mrs-wait-cnt = <0x0117000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x0000000d /* EMC_RC */
+ 0x00000067 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000009 /* EMC_RAS */
+ 0x00000003 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x00000008 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x00000009 /* EMC_W2P */
+ 0x00000003 /* EMC_RD_RCD */
+ 0x00000003 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000003 /* EMC_WDV */
+ 0x00000003 /* EMC_WDV_MASK */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000002 /* EMC_EINPUT */
+ 0x00000007 /* EMC_EINPUT_DURATION */
+ 0x00020000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000001 /* EMC_QRST */
+ 0x0000000e /* EMC_QSAFE */
+ 0x00000010 /* EMC_RDV */
+ 0x00000012 /* EMC_RDV_MASK */
+ 0x000008e4 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001 /* EMC_PDEX2WR */
+ 0x00000008 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000065 /* EMC_AR2PDEN */
+ 0x0000000e /* EMC_RW2PDEN */
+ 0x0000006c /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000009 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000924 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00030000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ4 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000096 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x0117000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000052a3 /* EMC_CFG_PIPE */
+ 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x00000009 /* EMC_QPOP */
+ >;
+ };
+
+ timing-396000000 {
+ clock-frequency = <396000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73340000>;
+ nvidia,emc-cfg-2 = <0x00000895>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100002>;
+ nvidia,emc-mode-2 = <0x00200000>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00000521>;
+ nvidia,emc-mrs-wait-cnt = <0x00f5000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+ nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x00000011 /* EMC_RC */
+ 0x00000089 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x0000000c /* EMC_RAS */
+ 0x00000004 /* EMC_RP */
+ 0x00000005 /* EMC_R2W */
+ 0x00000008 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x0000000a /* EMC_W2P */
+ 0x00000004 /* EMC_RD_RCD */
+ 0x00000004 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000003 /* EMC_WDV */
+ 0x00000003 /* EMC_WDV_MASK */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000001 /* EMC_EINPUT */
+ 0x00000008 /* EMC_EINPUT_DURATION */
+ 0x00020000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000000 /* EMC_QRST */
+ 0x0000000f /* EMC_QSAFE */
+ 0x00000010 /* EMC_RDV */
+ 0x00000012 /* EMC_RDV_MASK */
+ 0x00000bd1 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001 /* EMC_PDEX2WR */
+ 0x00000008 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000087 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x0000008f /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x0000000d /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000c11 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00030000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x000000c6 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x00f5000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000052a3 /* EMC_CFG_PIPE */
+ 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */
+ 0x00000009 /* EMC_QPOP */
+ >;
+ };
+
+ timing-528000000 {
+ clock-frequency = <528000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73300000>;
+ nvidia,emc-cfg-2 = <0x0000089d>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100002>;
+ nvidia,emc-mode-2 = <0x00200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00000941>;
+ nvidia,emc-mrs-wait-cnt = <0x00c8000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0123133d>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x00000018 /* EMC_RC */
+ 0x000000b7 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000010 /* EMC_RAS */
+ 0x00000006 /* EMC_RP */
+ 0x00000006 /* EMC_R2W */
+ 0x00000009 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x0000000d /* EMC_W2P */
+ 0x00000006 /* EMC_RD_RCD */
+ 0x00000006 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000003 /* EMC_WDV */
+ 0x00000003 /* EMC_WDV_MASK */
+ 0x00000007 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000002 /* EMC_EINPUT */
+ 0x00000009 /* EMC_EINPUT_DURATION */
+ 0x00040000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000001 /* EMC_QRST */
+ 0x00000010 /* EMC_QSAFE */
+ 0x00000013 /* EMC_RDV */
+ 0x00000015 /* EMC_RDV_MASK */
+ 0x00000fd6 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x0000000b /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x000000b4 /* EMC_AR2PDEN */
+ 0x00000012 /* EMC_RW2PDEN */
+ 0x000000bf /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000013 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000006 /* EMC_TCLKSTABLE */
+ 0x00000006 /* EMC_TCLKSTOP */
+ 0x00001017 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0xe01200b1 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0000000a /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS8 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS9 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS10 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS11 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS12 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS13 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS14 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x00c8000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000042a0 /* EMC_CFG_PIPE */
+ 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000b /* EMC_QPOP */
+ >;
+ };
+
+ timing-600000000 {
+ clock-frequency = <600000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73300000>;
+ nvidia,emc-cfg-2 = <0x0000089d>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100002>;
+ nvidia,emc-mode-2 = <0x00200010>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00000b61>;
+ nvidia,emc-mrs-wait-cnt = <0x00b0000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0121113d>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x0000001b /* EMC_RC */
+ 0x000000d0 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000013 /* EMC_RAS */
+ 0x00000007 /* EMC_RP */
+ 0x00000007 /* EMC_R2W */
+ 0x0000000b /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x00000010 /* EMC_W2P */
+ 0x00000007 /* EMC_RD_RCD */
+ 0x00000007 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_WDV_MASK */
+ 0x0000000a /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000003 /* EMC_EINPUT */
+ 0x0000000b /* EMC_EINPUT_DURATION */
+ 0x00070000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000002 /* EMC_QRST */
+ 0x00000012 /* EMC_QSAFE */
+ 0x00000016 /* EMC_RDV */
+ 0x00000018 /* EMC_RDV_MASK */
+ 0x00001208 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x0000000d /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x000000cc /* EMC_AR2PDEN */
+ 0x00000015 /* EMC_RW2PDEN */
+ 0x000000d8 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000015 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000006 /* EMC_TCLKSTABLE */
+ 0x00000006 /* EMC_TCLKSTOP */
+ 0x00001249 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0xe00e00b1 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0000000a /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS8 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS9 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS10 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS11 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS12 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS13 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS14 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x00b0000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000040a0 /* EMC_CFG_PIPE */
+ 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000e /* EMC_QPOP */
+ >;
+ };
+
+ timing-792000000 {
+ clock-frequency = <792000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73300000>;
+ nvidia,emc-cfg-2 = <0x0080089d>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x00100002>;
+ nvidia,emc-mode-2 = <0x00200418>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x00000d71>;
+ nvidia,emc-mrs-wait-cnt = <0x006f000e>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x00000024 /* EMC_RC */
+ 0x00000114 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000019 /* EMC_RAS */
+ 0x0000000a /* EMC_RP */
+ 0x00000008 /* EMC_R2W */
+ 0x0000000d /* EMC_W2R */
+ 0x00000004 /* EMC_R2P */
+ 0x00000013 /* EMC_W2P */
+ 0x0000000a /* EMC_RD_RCD */
+ 0x0000000a /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x0000000b /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000002 /* EMC_EINPUT */
+ 0x0000000d /* EMC_EINPUT_DURATION */
+ 0x00080000 /* EMC_PUTERM_EXTRA */
+ 0x00000004 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000001 /* EMC_QRST */
+ 0x00000014 /* EMC_QSAFE */
+ 0x00000018 /* EMC_RDV */
+ 0x0000001a /* EMC_RDV_MASK */
+ 0x000017e2 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000003 /* EMC_PDEX2WR */
+ 0x00000011 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x0000010d /* EMC_AR2PDEN */
+ 0x00000018 /* EMC_RW2PDEN */
+ 0x0000011e /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000005 /* EMC_TCKE */
+ 0x00000006 /* EMC_TCKESR */
+ 0x00000005 /* EMC_TPD */
+ 0x0000001d /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000008 /* EMC_TCLKSTABLE */
+ 0x00000008 /* EMC_TCLKSTOP */
+ 0x00001822 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x80000005 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab198 /* EMC_FBIO_CFG5 */
+ 0xe00700b1 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x007fc007 /* EMC_DLL_XFORM_DQS0 */
+ 0x007fc008 /* EMC_DLL_XFORM_DQS1 */
+ 0x007f400c /* EMC_DLL_XFORM_DQS2 */
+ 0x007fc007 /* EMC_DLL_XFORM_DQS3 */
+ 0x007f4006 /* EMC_DLL_XFORM_DQS4 */
+ 0x007f8004 /* EMC_DLL_XFORM_DQS5 */
+ 0x007f8005 /* EMC_DLL_XFORM_DQS6 */
+ 0x007f8004 /* EMC_DLL_XFORM_DQS7 */
+ 0x007fc007 /* EMC_DLL_XFORM_DQS8 */
+ 0x007fc008 /* EMC_DLL_XFORM_DQS9 */
+ 0x007f400c /* EMC_DLL_XFORM_DQS10 */
+ 0x007fc007 /* EMC_DLL_XFORM_DQS11 */
+ 0x007f4006 /* EMC_DLL_XFORM_DQS12 */
+ 0x007f8004 /* EMC_DLL_XFORM_DQS13 */
+ 0x007f8005 /* EMC_DLL_XFORM_DQS14 */
+ 0x007f8004 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00034000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00034000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00034000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00034000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x61861820 /* EMC_XM2DQSPADCTRL3 */
+ 0x00492492 /* EMC_XM2DQSPADCTRL4 */
+ 0x00492492 /* EMC_XM2DQSPADCTRL5 */
+ 0x61861800 /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x006f000e /* EMC_MRS_WAIT_CNT2 */
+ 0x00000007 /* EMC_CTT */
+ 0x00000004 /* EMC_CTT_DURATION */
+ 0x00004080 /* EMC_CFG_PIPE */
+ 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000f /* EMC_QPOP */
+ >;
+ };
+ };
+
+ emc-timings-6 {
+ nvidia,ram-code = <6>;
+
+ timing-12750000 {
+ clock-frequency = <12750000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x000008c5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00000000>;
+
+ nvidia,emc-configuration = <
+ 0x00000000 /* EMC_RC */
+ 0x00000003 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000000 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000060 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000005 /* EMC_TXSR */
+ 0x00000005 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000000 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000064 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000007 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-20400000 {
+ clock-frequency = <20400000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x000008c5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00000000>;
+
+ nvidia,emc-configuration = <
+ 0x00000000 /* EMC_RC */
+ 0x00000005 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000000 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x0000009a /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000026 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000006 /* EMC_TXSR */
+ 0x00000006 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000000 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x000000a0 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x0000000b /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x8000023a /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-40800000 {
+ clock-frequency = <40800000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x000008c5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00000000>;
+
+ nvidia,emc-configuration = <
+ 0x00000001 /* EMC_RC */
+ 0x0000000a /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000001 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000134 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x0000004d /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000008 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x0000000c /* EMC_TXSR */
+ 0x0000000c /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000000 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x0000013f /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000015 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x80000370 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-68000000 {
+ clock-frequency = <68000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x000008c5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00000000>;
+
+ nvidia,emc-configuration = <
+ 0x00000003 /* EMC_RC */
+ 0x00000011 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000002 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000202 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000080 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x0000000f /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000013 /* EMC_TXSR */
+ 0x00000013 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000001 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000213 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000022 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x8000050e /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x000008c5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00000000>;
+
+ nvidia,emc-configuration = <
+ 0x00000004 /* EMC_RC */
+ 0x0000001a /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000003 /* EMC_RAS */
+ 0x00000001 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000001 /* EMC_RD_RCD */
+ 0x00000001 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000005 /* EMC_EINPUT */
+ 0x00000005 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000c /* EMC_QSAFE */
+ 0x0000000d /* EMC_RDV */
+ 0x0000000f /* EMC_RDV_MASK */
+ 0x00000304 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000000c1 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000018 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x0000001c /* EMC_TXSR */
+ 0x0000001c /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000003 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x0000031c /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000033 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000042 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000f2f3 /* EMC_CFG_PIPE */
+ 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000008>;
+ nvidia,emc-cfg = <0x73240000>;
+ nvidia,emc-cfg-2 = <0x0000088d>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-mrs-wait-cnt = <0x000c000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x00000009 /* EMC_RC */
+ 0x00000035 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000007 /* EMC_RAS */
+ 0x00000002 /* EMC_RP */
+ 0x00000005 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000002 /* EMC_RD_RCD */
+ 0x00000002 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000003 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_WDV_MASK */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000004 /* EMC_EINPUT */
+ 0x00000006 /* EMC_EINPUT_DURATION */
+ 0x00010000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000003 /* EMC_QRST */
+ 0x0000000d /* EMC_QSAFE */
+ 0x0000000f /* EMC_RDV */
+ 0x00000011 /* EMC_RDV_MASK */
+ 0x00000607 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000032 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000038 /* EMC_TXSR */
+ 0x00000038 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000007 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000638 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x106aa298 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00064000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00064000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00004000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00090000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00090000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00094000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00094000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00009400 /* EMC_DLL_XFORM_DQ4 */
+ 0x00009000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00009000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00009000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000303 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000066 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x0000d2b3 /* EMC_CFG_PIPE */
+ 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a /* EMC_QPOP */
+ >;
+ };
+
+ timing-300000000 {
+ clock-frequency = <300000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73340000>;
+ nvidia,emc-cfg-2 = <0x000008d5>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80000321>;
+ nvidia,emc-mrs-wait-cnt = <0x0174000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+ nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x0000000d /* EMC_RC */
+ 0x0000004c /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000009 /* EMC_RAS */
+ 0x00000003 /* EMC_RP */
+ 0x00000004 /* EMC_R2W */
+ 0x00000008 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x00000009 /* EMC_W2P */
+ 0x00000003 /* EMC_RD_RCD */
+ 0x00000003 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000003 /* EMC_WDV */
+ 0x00000003 /* EMC_WDV_MASK */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000002 /* EMC_EINPUT */
+ 0x00000007 /* EMC_EINPUT_DURATION */
+ 0x00020000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000001 /* EMC_QRST */
+ 0x0000000e /* EMC_QSAFE */
+ 0x00000010 /* EMC_RDV */
+ 0x00000012 /* EMC_RDV_MASK */
+ 0x000008e4 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000239 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001 /* EMC_PDEX2WR */
+ 0x00000008 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x0000004a /* EMC_AR2PDEN */
+ 0x0000000e /* EMC_RW2PDEN */
+ 0x00000051 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000009 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000924 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00030000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00098000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00060000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ4 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ5 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ6 */
+ 0x00006000 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000096 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x0174000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000052a3 /* EMC_CFG_PIPE */
+ 0x800012d7 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x00000009 /* EMC_QPOP */
+ >;
+ };
+
+ timing-396000000 {
+ clock-frequency = <396000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73340000>;
+ nvidia,emc-cfg-2 = <0x00000895>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80000521>;
+ nvidia,emc-mrs-wait-cnt = <0x015b000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+ nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x00000012 /* EMC_RC */
+ 0x00000065 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x0000000c /* EMC_RAS */
+ 0x00000004 /* EMC_RP */
+ 0x00000005 /* EMC_R2W */
+ 0x00000008 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x0000000a /* EMC_W2P */
+ 0x00000004 /* EMC_RD_RCD */
+ 0x00000004 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000003 /* EMC_WDV */
+ 0x00000003 /* EMC_WDV_MASK */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000001 /* EMC_EINPUT */
+ 0x00000008 /* EMC_EINPUT_DURATION */
+ 0x00020000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000000 /* EMC_QRST */
+ 0x0000000f /* EMC_QSAFE */
+ 0x00000010 /* EMC_RDV */
+ 0x00000012 /* EMC_RDV_MASK */
+ 0x00000bd1 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000002f4 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001 /* EMC_PDEX2WR */
+ 0x00000008 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000063 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x0000006b /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x0000000d /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000005 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000c11 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0x002c00a0 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00030000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS8 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS9 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS10 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS11 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS12 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS13 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS14 */
+ 0x00030000 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00070000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ3 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ4 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ5 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ6 */
+ 0x00004800 /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f /* EMC_DSR_VTTGEN_DRV */
+ 0x000000c6 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x015b000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000052a3 /* EMC_CFG_PIPE */
+ 0x8000188b /* EMC_DYN_SELF_REF_CONTROL */
+ 0x00000009 /* EMC_QPOP */
+ >;
+ };
+
+ timing-528000000 {
+ clock-frequency = <528000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73300000>;
+ nvidia,emc-cfg-2 = <0x0000089d>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80000941>;
+ nvidia,emc-mrs-wait-cnt = <0x013a000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0123133d>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x00000018 /* EMC_RC */
+ 0x00000088 /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000011 /* EMC_RAS */
+ 0x00000006 /* EMC_RP */
+ 0x00000006 /* EMC_R2W */
+ 0x00000009 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x0000000d /* EMC_W2P */
+ 0x00000006 /* EMC_RD_RCD */
+ 0x00000006 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000003 /* EMC_WDV */
+ 0x00000003 /* EMC_WDV_MASK */
+ 0x00000007 /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000002 /* EMC_EINPUT */
+ 0x00000009 /* EMC_EINPUT_DURATION */
+ 0x00040000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000001 /* EMC_QRST */
+ 0x00000010 /* EMC_QSAFE */
+ 0x00000013 /* EMC_RDV */
+ 0x00000015 /* EMC_RDV_MASK */
+ 0x00000fd6 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000003f5 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x0000000b /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000084 /* EMC_AR2PDEN */
+ 0x00000012 /* EMC_RW2PDEN */
+ 0x0000008f /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000013 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000006 /* EMC_TCLKSTABLE */
+ 0x00000006 /* EMC_TCLKSTOP */
+ 0x00001017 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0xe01200b1 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0000000a /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS8 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS9 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS10 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS11 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS12 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS13 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS14 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00050000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000001 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000001 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x013a000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000042a0 /* EMC_CFG_PIPE */
+ 0x80002062 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000b /* EMC_QPOP */
+ >;
+ };
+
+ timing-600000000 {
+ clock-frequency = <600000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73300000>;
+ nvidia,emc-cfg-2 = <0x0000089d>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200010>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80000b61>;
+ nvidia,emc-mrs-wait-cnt = <0x0128000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0121113d>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x0000001c /* EMC_RC */
+ 0x0000009a /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x00000013 /* EMC_RAS */
+ 0x00000007 /* EMC_RP */
+ 0x00000007 /* EMC_R2W */
+ 0x0000000b /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x00000010 /* EMC_W2P */
+ 0x00000007 /* EMC_RD_RCD */
+ 0x00000007 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_WDV_MASK */
+ 0x0000000a /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000003 /* EMC_EINPUT */
+ 0x0000000b /* EMC_EINPUT_DURATION */
+ 0x00070000 /* EMC_PUTERM_EXTRA */
+ 0x00000003 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000002 /* EMC_QRST */
+ 0x00000012 /* EMC_QSAFE */
+ 0x00000016 /* EMC_RDV */
+ 0x00000018 /* EMC_RDV_MASK */
+ 0x00001208 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000482 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x0000000d /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000096 /* EMC_AR2PDEN */
+ 0x00000015 /* EMC_RW2PDEN */
+ 0x000000a2 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000005 /* EMC_TCKESR */
+ 0x00000004 /* EMC_TPD */
+ 0x00000015 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000006 /* EMC_TCLKSTABLE */
+ 0x00000006 /* EMC_TCLKSTOP */
+ 0x00001249 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab098 /* EMC_FBIO_CFG5 */
+ 0xe00e00b1 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0000000a /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS8 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS9 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS10 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS11 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS12 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS13 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS14 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00048000 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000004 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000002 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000003 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000006 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420 /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514 /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400 /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x0128000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000 /* EMC_CTT */
+ 0x00000003 /* EMC_CTT_DURATION */
+ 0x000040a0 /* EMC_CFG_PIPE */
+ 0x800024aa /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000e /* EMC_QPOP */
+ >;
+ };
+
+ timing-792000000 {
+ clock-frequency = <792000000>;
+
+ nvidia,emc-auto-cal-config = <0xa1430000>;
+ nvidia,emc-auto-cal-config2 = <0x00000000>;
+ nvidia,emc-auto-cal-config3 = <0x00000000>;
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-bgbias-ctl0 = <0x00000000>;
+ nvidia,emc-cfg = <0x73300000>;
+ nvidia,emc-cfg-2 = <0x0080089d>;
+ nvidia,emc-ctt-term-ctrl = <0x00000802>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200418>;
+ nvidia,emc-mode-4 = <0x00000000>;
+ nvidia,emc-mode-reset = <0x80000d71>;
+ nvidia,emc-mrs-wait-cnt = <0x00f8000c>;
+ nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+ nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+ nvidia,emc-zcal-cnt-long = <0x00000042>;
+ nvidia,emc-zcal-interval = <0x00020000>;
+
+ nvidia,emc-configuration = <
+ 0x00000025 /* EMC_RC */
+ 0x000000cc /* EMC_RFC */
+ 0x00000000 /* EMC_RFC_SLR */
+ 0x0000001a /* EMC_RAS */
+ 0x00000009 /* EMC_RP */
+ 0x00000008 /* EMC_R2W */
+ 0x0000000d /* EMC_W2R */
+ 0x00000004 /* EMC_R2P */
+ 0x00000013 /* EMC_W2P */
+ 0x00000009 /* EMC_RD_RCD */
+ 0x00000009 /* EMC_WR_RCD */
+ 0x00000004 /* EMC_RRD */
+ 0x00000002 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000006 /* EMC_WDV */
+ 0x00000006 /* EMC_WDV_MASK */
+ 0x0000000b /* EMC_QUSE */
+ 0x00000002 /* EMC_QUSE_WIDTH */
+ 0x00000000 /* EMC_IBDLY */
+ 0x00000002 /* EMC_EINPUT */
+ 0x0000000d /* EMC_EINPUT_DURATION */
+ 0x00080000 /* EMC_PUTERM_EXTRA */
+ 0x00000004 /* EMC_PUTERM_WIDTH */
+ 0x00000000 /* EMC_PUTERM_ADJ */
+ 0x00000000 /* EMC_CDB_CNTL_1 */
+ 0x00000000 /* EMC_CDB_CNTL_2 */
+ 0x00000000 /* EMC_CDB_CNTL_3 */
+ 0x00000001 /* EMC_QRST */
+ 0x00000014 /* EMC_QSAFE */
+ 0x00000018 /* EMC_RDV */
+ 0x0000001a /* EMC_RDV_MASK */
+ 0x000017e2 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000005f8 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000003 /* EMC_PDEX2WR */
+ 0x00000011 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x000000c6 /* EMC_AR2PDEN */
+ 0x00000018 /* EMC_RW2PDEN */
+ 0x000000d6 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000005 /* EMC_TCKE */
+ 0x00000006 /* EMC_TCKESR */
+ 0x00000005 /* EMC_TPD */
+ 0x0000001d /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000008 /* EMC_TCLKSTABLE */
+ 0x00000008 /* EMC_TCLKSTOP */
+ 0x00001822 /* EMC_TREFBW */
+ 0x00000000 /* EMC_FBIO_CFG6 */
+ 0x80000005 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x104ab198 /* EMC_FBIO_CFG5 */
+ 0xe00700b1 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00000009 /* EMC_DLL_XFORM_DQS0 */
+ 0x00000009 /* EMC_DLL_XFORM_DQS1 */
+ 0x00000009 /* EMC_DLL_XFORM_DQS2 */
+ 0x00000007 /* EMC_DLL_XFORM_DQS3 */
+ 0x00000006 /* EMC_DLL_XFORM_DQS4 */
+ 0x00000006 /* EMC_DLL_XFORM_DQS5 */
+ 0x007fc009 /* EMC_DLL_XFORM_DQS6 */
+ 0x00000006 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000009 /* EMC_DLL_XFORM_DQS8 */
+ 0x00000009 /* EMC_DLL_XFORM_DQS9 */
+ 0x00000009 /* EMC_DLL_XFORM_DQS10 */
+ 0x00000007 /* EMC_DLL_XFORM_DQS11 */
+ 0x00000006 /* EMC_DLL_XFORM_DQS12 */
+ 0x00000007 /* EMC_DLL_XFORM_DQS13 */
+ 0x00000009 /* EMC_DLL_XFORM_DQS14 */
+ 0x00000007 /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00034002 /* EMC_DLL_XFORM_ADDR0 */
+ 0x00034002 /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
+ 0x00034002 /* EMC_DLL_XFORM_ADDR3 */
+ 0x00034002 /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000007 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000005 /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000007 /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000009 /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000008 /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000e /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0 /* EMC_XM2CMDPADCTRL */
+ 0x00000000 /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111 /* EMC_XM2CMDPADCTRL5 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085 /* EMC_XM2CLKPADCTRL */
+ 0x00000101 /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x07070004 /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
+ 0x61861820 /* EMC_XM2DQSPADCTRL3 */
+ 0x004d34d3 /* EMC_XM2DQSPADCTRL4 */
+ 0x004d34d3 /* EMC_XM2DQSPADCTRL5 */
+ 0x61861800 /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000 /* EMC_TXDSRVTTGEN */
+ 0x00000000 /* EMC_FBIO_SPARE */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x00f8000c /* EMC_MRS_WAIT_CNT2 */
+ 0x00000007 /* EMC_CTT */
+ 0x00000004 /* EMC_CTT_DURATION */
+ 0x00004080 /* EMC_CFG_PIPE */
+ 0x80003012 /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000f /* EMC_QPOP */
+ >;
+ };
};
};
@@ -1759,30 +5781,29 @@
emc-timings-1 {
nvidia,ram-code = <1>;
-
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
- 0x40040001
- 0x8000000a
- 0x00000001
- 0x00000001
- 0x00000002
- 0x00000000
- 0x00000002
- 0x00000001
- 0x00000002
- 0x00000008
- 0x00000003
- 0x00000002
- 0x00000003
- 0x00000006
- 0x06030203
- 0x000a0402
- 0x77e30303
- 0x70000f03
- 0x001f0000
+ 0x40040001 /* MC_EMEM_ARB_CFG */
+ 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
+ 0x77e30303 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
@@ -1790,25 +5811,25 @@
clock-frequency = <20400000>;
nvidia,emem-configuration = <
- 0x40020001
- 0x80000012
- 0x00000001
- 0x00000001
- 0x00000002
- 0x00000000
- 0x00000002
- 0x00000001
- 0x00000002
- 0x00000008
- 0x00000003
- 0x00000002
- 0x00000003
- 0x00000006
- 0x06030203
- 0x000a0402
- 0x76230303
- 0x70000f03
- 0x001f0000
+ 0x40020001 /* MC_EMEM_ARB_CFG */
+ 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
+ 0x76230303 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
@@ -1816,25 +5837,25 @@
clock-frequency = <40800000>;
nvidia,emem-configuration = <
- 0xa0000001
- 0x80000017
- 0x00000001
- 0x00000001
- 0x00000002
- 0x00000000
- 0x00000002
- 0x00000001
- 0x00000002
- 0x00000008
- 0x00000003
- 0x00000002
- 0x00000003
- 0x00000006
- 0x06030203
- 0x000a0402
- 0x74a30303
- 0x70000f03
- 0x001f0000
+ 0xa0000001 /* MC_EMEM_ARB_CFG */
+ 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
+ 0x74a30303 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
@@ -1842,25 +5863,25 @@
clock-frequency = <68000000>;
nvidia,emem-configuration = <
- 0x00000001
- 0x8000001e
- 0x00000001
- 0x00000001
- 0x00000002
- 0x00000000
- 0x00000002
- 0x00000001
- 0x00000002
- 0x00000008
- 0x00000003
- 0x00000002
- 0x00000003
- 0x00000006
- 0x06030203
- 0x000a0402
- 0x74230403
- 0x70000f03
- 0x001f0000
+ 0x00000001 /* MC_EMEM_ARB_CFG */
+ 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
+ 0x74230403 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
@@ -1868,25 +5889,25 @@
clock-frequency = <102000000>;
nvidia,emem-configuration = <
- 0x08000001
- 0x80000026
- 0x00000001
- 0x00000001
- 0x00000003
- 0x00000000
- 0x00000002
- 0x00000001
- 0x00000002
- 0x00000008
- 0x00000003
- 0x00000002
- 0x00000003
- 0x00000006
- 0x06030203
- 0x000a0403
- 0x73c30504
- 0x70000f03
- 0x001f0000
+ 0x08000001 /* MC_EMEM_ARB_CFG */
+ 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */
+ 0x73c30504 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
@@ -1894,25 +5915,25 @@
clock-frequency = <204000000>;
nvidia,emem-configuration = <
- 0x01000003
- 0x80000040
- 0x00000001
- 0x00000001
- 0x00000005
- 0x00000002
- 0x00000004
- 0x00000001
- 0x00000002
- 0x00000008
- 0x00000003
- 0x00000002
- 0x00000004
- 0x00000006
- 0x06040203
- 0x000a0405
- 0x73840a06
- 0x70000f03
- 0x001f0000
+ 0x01000003 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */
+ 0x73840a06 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
@@ -1920,25 +5941,25 @@
clock-frequency = <300000000>;
nvidia,emem-configuration = <
- 0x08000004
- 0x80000040
- 0x00000001
- 0x00000002
- 0x00000007
- 0x00000004
- 0x00000005
- 0x00000001
- 0x00000002
- 0x00000007
- 0x00000002
- 0x00000002
- 0x00000004
- 0x00000006
- 0x06040202
- 0x000b0607
- 0x77450e08
- 0x70000f03
- 0x001f0000
+ 0x08000004 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */
+ 0x77450e08 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
@@ -1946,25 +5967,51 @@
clock-frequency = <396000000>;
nvidia,emem-configuration = <
- 0x0f000005
- 0x80000040
- 0x00000001
- 0x00000002
- 0x00000009
- 0x00000005
- 0x00000007
- 0x00000001
- 0x00000002
- 0x00000008
- 0x00000002
- 0x00000002
- 0x00000004
- 0x00000006
- 0x06040202
- 0x000d0709
- 0x7586120a
- 0x70000f03
- 0x001f0000
+ 0x0f000005 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
+ 0x7586120a /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-528000000 {
+ clock-frequency = <528000000>;
+
+ nvidia,emem-configuration = <
+ 0x0f000007 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RP */
+ 0x0000000d /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06050202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x0010090d /* MC_EMEM_ARB_DA_COVERS */
+ 0x7428180e /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
@@ -1972,25 +6019,25 @@
clock-frequency = <600000000>;
nvidia,emem-configuration = <
- 0x00000009
- 0x80000040
- 0x00000003
- 0x00000004
- 0x0000000e
- 0x00000009
- 0x0000000b
- 0x00000001
- 0x00000003
- 0x0000000b
- 0x00000002
- 0x00000002
- 0x00000005
- 0x00000007
- 0x07050202
- 0x00130b0e
- 0x73a91b0f
- 0x70000f03
- 0x001f0000
+ 0x00000009 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
+ 0x0000000e /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x07050202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */
+ 0x73a91b0f /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
@@ -1998,25 +6045,605 @@
clock-frequency = <792000000>;
nvidia,emem-configuration = <
- 0x0e00000b
- 0x80000040
- 0x00000004
- 0x00000005
- 0x00000013
- 0x0000000c
- 0x0000000f
- 0x00000002
- 0x00000003
- 0x0000000c
- 0x00000002
- 0x00000002
- 0x00000006
- 0x00000008
- 0x08060202
- 0x00160d13
- 0x734c2414
- 0x70000f02
- 0x001f0000
+ 0x0e00000b /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
+ 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x08060202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
+ 0x734c2414 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f02 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+ };
+
+ emc-timings-4 {
+ nvidia,ram-code = <4>;
+
+ timing-12750000 {
+ clock-frequency = <12750000>;
+
+ nvidia,emem-configuration = <
+ 0x40040001 /* MC_EMEM_ARB_CFG */
+ 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
+ 0x77e30303 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-20400000 {
+ clock-frequency = <20400000>;
+
+ nvidia,emem-configuration = <
+ 0x40020001 /* MC_EMEM_ARB_CFG */
+ 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
+ 0x77430303 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-40800000 {
+ clock-frequency = <40800000>;
+
+ nvidia,emem-configuration = <
+ 0xa0000001 /* MC_EMEM_ARB_CFG */
+ 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
+ 0x75e30303 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-68000000 {
+ clock-frequency = <68000000>;
+
+ nvidia,emem-configuration = <
+ 0x00000001 /* MC_EMEM_ARB_CFG */
+ 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
+ 0x75430403 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = <
+ 0x08000001 /* MC_EMEM_ARB_CFG */
+ 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
+ 0x74e30504 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = <
+ 0x01000003 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0504 /* MC_EMEM_ARB_DA_COVERS */
+ 0x74a40a05 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-300000000 {
+ clock-frequency = <300000000>;
+
+ nvidia,emem-configuration = <
+ 0x08000004 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */
+ 0x77450e08 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-396000000 {
+ clock-frequency = <396000000>;
+
+ nvidia,emem-configuration = <
+ 0x0f000005 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
+ 0x7586120a /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-528000000 {
+ clock-frequency = <528000000>;
+
+ nvidia,emem-configuration = <
+ 0x0f000007 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RP */
+ 0x0000000c /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06050202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x0010090c /* MC_EMEM_ARB_DA_COVERS */
+ 0x7488180d /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-600000000 {
+ clock-frequency = <600000000>;
+
+ nvidia,emem-configuration = <
+ 0x00000009 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
+ 0x0000000e /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x07050202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */
+ 0x74691b0f /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-792000000 {
+ clock-frequency = <792000000>;
+
+ nvidia,emem-configuration = <
+ 0x0e00000b /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
+ 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x08060202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x00170e13 /* MC_EMEM_ARB_DA_COVERS */
+ 0x746c2414 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f02 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+ };
+
+ emc-timings-6 {
+ nvidia,ram-code = <6>;
+
+ timing-12750000 {
+ clock-frequency = <12750000>;
+
+ nvidia,emem-configuration = <
+ 0x40040001 /* MC_EMEM_ARB_CFG */
+ 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
+ 0x77e30303 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-20400000 {
+ clock-frequency = <20400000>;
+
+ nvidia,emem-configuration = <
+ 0x40020001 /* MC_EMEM_ARB_CFG */
+ 0x80000012 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
+ 0x76230303 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-40800000 {
+ clock-frequency = <40800000>;
+
+ nvidia,emem-configuration = <
+ 0xa0000001 /* MC_EMEM_ARB_CFG */
+ 0x80000017 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
+ 0x74a30303 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-68000000 {
+ clock-frequency = <68000000>;
+
+ nvidia,emem-configuration = <
+ 0x00000001 /* MC_EMEM_ARB_CFG */
+ 0x8000001e /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
+ 0x74230403 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = <
+ 0x08000001 /* MC_EMEM_ARB_CFG */
+ 0x80000026 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0403 /* MC_EMEM_ARB_DA_COVERS */
+ 0x73c30504 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = <
+ 0x01000003 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040203 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0405 /* MC_EMEM_ARB_DA_COVERS */
+ 0x73840a06 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-300000000 {
+ clock-frequency = <300000000>;
+
+ nvidia,emem-configuration = <
+ 0x08000004 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000b0607 /* MC_EMEM_ARB_DA_COVERS */
+ 0x77450e08 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-396000000 {
+ clock-frequency = <396000000>;
+
+ nvidia,emem-configuration = <
+ 0x0f000005 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000009 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
+ 0x7586120a /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-528000000 {
+ clock-frequency = <528000000>;
+
+ nvidia,emem-configuration = <
+ 0x0f000007 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RP */
+ 0x0000000d /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000009 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06050202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x0010090d /* MC_EMEM_ARB_DA_COVERS */
+ 0x7428180e /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-600000000 {
+ clock-frequency = <600000000>;
+
+ nvidia,emem-configuration = <
+ 0x00000009 /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
+ 0x0000000e /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000009 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000b /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x07050202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x00130b0e /* MC_EMEM_ARB_DA_COVERS */
+ 0x73a91b0f /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-792000000 {
+ clock-frequency = <792000000>;
+
+ nvidia,emem-configuration = <
+ 0x0e00000b /* MC_EMEM_ARB_CFG */
+ 0x80000040 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000013 /* MC_EMEM_ARB_TIMING_RC */
+ 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x08060202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
+ 0x734c2414 /* MC_EMEM_ARB_MISC0 */
+ 0x70000f02 /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
};
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
index d97791b..fdc1d64 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -13,14 +13,18 @@
"google,nyan-big-rev1", "google,nyan-big-rev0",
"google,nyan-big", "google,nyan", "nvidia,tegra124";
- panel: panel {
- compatible = "auo,b133xtn01";
-
- backlight = <&backlight>;
- ddc-i2c-bus = <&dpaux>;
+ host1x@50000000 {
+ dpaux@545c0000 {
+ aux-bus {
+ panel: panel {
+ compatible = "auo,b133xtn01";
+ backlight = <&backlight>;
+ };
+ };
+ };
};
- sdhci@700b0400 { /* SD Card on this bus */
+ mmc@700b0400 { /* SD Card on this bus */
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
index c7c31d4..d2beea0 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
@@ -68,7 +68,7 @@
};
};
- emc@7001b000 {
+ external-memory-controller@7001b000 {
emc-timings-1 {
nvidia,ram-code = <1>;
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
index 2a029ee..abdf445 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
@@ -15,11 +15,15 @@
"google,nyan-blaze-rev0", "google,nyan-blaze",
"google,nyan", "nvidia,tegra124";
- panel: panel {
- compatible = "samsung,ltn140at29-301";
-
- backlight = <&backlight>;
- ddc-i2c-bus = <&dpaux>;
+ host1x@50000000 {
+ dpaux@545c0000 {
+ aux-bus {
+ panel: panel {
+ compatible = "samsung,ltn140at29-301";
+ backlight = <&backlight>;
+ };
+ };
+ };
};
sound {
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index 3b10f47..5f71add 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -48,6 +48,9 @@
sor@54540000 {
status = "okay";
+ avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>;
+ vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>;
+
nvidia,dpaux = <&dpaux>;
nvidia,panel = <&panel>;
};
@@ -495,7 +498,7 @@
reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
};
- sdhci@700b0000 { /* WiFi/BT on this bus */
+ mmc@700b0000 { /* WiFi/BT on this bus */
status = "okay";
bus-width = <4>;
no-1-8-v;
@@ -506,7 +509,7 @@
keep-power-in-suspend;
};
- sdhci@700b0400 { /* SD Card on this bus */
+ mmc@700b0400 { /* SD Card on this bus */
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
@@ -515,7 +518,7 @@
vqmmc-supply = <&vddio_sdmmc3>;
};
- sdhci@700b0600 { /* eMMC on this bus */
+ mmc@700b0600 { /* eMMC on this bus */
status = "okay";
bus-width = <8>;
no-1-8-v;
@@ -579,17 +582,10 @@
256>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
cpus {
@@ -619,157 +615,138 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_mux: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "+VDD_MUX";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- vdd_mux: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "+VDD_MUX";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- };
+ vdd_5v0_sys: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_5v0_sys: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "+5V_SYS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_mux>;
- };
+ vdd_3v3_sys: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_SYS";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_3v3_sys: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "+3.3V_SYS";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_mux>;
- };
+ vdd_3v3_run: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_RUN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
- vdd_3v3_run: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "+3.3V_RUN";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
- };
+ vdd_3v3_hdmi: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_3v3_run>;
+ };
- vdd_3v3_hdmi: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vdd_3v3_run>;
- };
+ vdd_led: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "+VDD_LED";
+ gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_led: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "+VDD_LED";
- gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_mux>;
- };
+ vdd_5v0_ts: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_VDD_TS_SW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_5v0_ts: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "+5V_VDD_TS_SW";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_usb1_vbus: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_USB_HS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_usb1_vbus: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "+5V_USB_HS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_usb3_vbus: regulator@8 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_USB_SS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_usb3_vbus: regulator@8 {
- compatible = "regulator-fixed";
- reg = <8>;
- regulator-name = "+5V_USB_SS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_3v3_panel: regulator@9 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_PANEL";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_run>;
+ };
- vdd_3v3_panel: regulator@9 {
- compatible = "regulator-fixed";
- reg = <9>;
- regulator-name = "+3.3V_PANEL";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_run>;
- };
+ vdd_3v3_lp0: regulator@10 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_LP0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ /*
+ * TODO: find a way to wire this up with the USB EHCI
+ * controllers so that it can be enabled on demand.
+ */
+ regulator-always-on;
+ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
- vdd_3v3_lp0: regulator@10 {
- compatible = "regulator-fixed";
- reg = <10>;
- regulator-name = "+3.3V_LP0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- /*
- * TODO: find a way to wire this up with the USB EHCI
- * controllers so that it can be enabled on demand.
- */
- regulator-always-on;
- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
- };
+ vdd_hdmi_pll: regulator@11 {
+ compatible = "regulator-fixed";
+ regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+ vin-supply = <&vdd_1v05_run>;
+ };
- vdd_hdmi_pll: regulator@11 {
- compatible = "regulator-fixed";
- reg = <11>;
- regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
- vin-supply = <&vdd_1v05_run>;
- };
-
- vdd_5v0_hdmi: regulator@12 {
- compatible = "regulator-fixed";
- reg = <12>;
- regulator-name = "+5V_HDMI_CON";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_5v0_hdmi: regulator@12 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_HDMI_CON";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
};
sound {
@@ -788,9 +765,15 @@
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA124_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+ assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA124_CLK_EXTERN1>;
+
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
nvidia,mic-det-gpios =
<&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 5d5e6e1..84e2d24 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -38,6 +38,9 @@
sor@54540000 {
status = "okay";
+ avdd-io-hdmi-dp-supply = <&vdd_1v05_run>;
+ vdd-hdmi-dp-pll-supply = <&vdd_3v3_run>;
+
nvidia,dpaux = <&dpaux>;
nvidia,panel = <&panel>;
};
@@ -45,6 +48,13 @@
dpaux@545c0000 {
vdd-supply = <&vdd_3v3_panel>;
status = "okay";
+
+ aux-bus {
+ panel: panel {
+ compatible = "lg,lp129qe";
+ backlight = <&backlight>;
+ };
+ };
};
};
@@ -999,7 +1009,7 @@
};
};
- sdhci@700b0400 {
+ mmc@700b0400 {
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
@@ -1008,7 +1018,7 @@
vqmmc-supply = <&vddio_sdmmc3>;
};
- sdhci@700b0600 {
+ mmc@700b0600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -1058,17 +1068,10 @@
default-brightness-level = <6>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-keys {
@@ -1083,166 +1086,140 @@
};
};
- panel: panel {
- compatible = "lg,lp129qe", "simple-panel";
-
- backlight = <&backlight>;
- ddc-i2c-bus = <&dpaux>;
+ vdd_mux: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "+VDD_MUX";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_5v0_sys: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_mux: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "+VDD_MUX";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- };
+ vdd_3v3_sys: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_SYS";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_5v0_sys: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "+5V_SYS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_mux>;
- };
+ vdd_3v3_run: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_RUN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
- vdd_3v3_sys: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "+3.3V_SYS";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&vdd_mux>;
- };
+ vdd_3v3_hdmi: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_3v3_run>;
+ };
- vdd_3v3_run: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "+3.3V_RUN";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
- };
+ vdd_led: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "+VDD_LED";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_mux>;
+ };
- vdd_3v3_hdmi: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vdd_3v3_run>;
- };
+ vdd_5v0_ts: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_VDD_TS_SW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_led: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "+VDD_LED";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_mux>;
- };
+ vdd_usb1_vbus: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_USB_HS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_5v0_ts: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "+5V_VDD_TS_SW";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_usb3_vbus: regulator@8 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_USB_SS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_sys>;
+ };
- vdd_usb1_vbus: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "+5V_USB_HS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_3v3_panel: regulator@9 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_PANEL";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_run>;
+ };
- vdd_usb3_vbus: regulator@8 {
- compatible = "regulator-fixed";
- reg = <8>;
- regulator-name = "+5V_USB_SS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_3v3_lp0: regulator@10 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3.3V_LP0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ /*
+ * TODO: find a way to wire this up with the USB EHCI
+ * controllers so that it can be enabled on demand.
+ */
+ regulator-always-on;
+ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
- vdd_3v3_panel: regulator@9 {
- compatible = "regulator-fixed";
- reg = <9>;
- regulator-name = "+3.3V_PANEL";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_run>;
- };
+ vdd_hdmi_pll: regulator@11 {
+ compatible = "regulator-fixed";
+ regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+ vin-supply = <&vdd_1v05_run>;
+ };
- vdd_3v3_lp0: regulator@10 {
- compatible = "regulator-fixed";
- reg = <10>;
- regulator-name = "+3.3V_LP0";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- /*
- * TODO: find a way to wire this up with the USB EHCI
- * controllers so that it can be enabled on demand.
- */
- regulator-always-on;
- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_3v3_sys>;
- };
-
- vdd_hdmi_pll: regulator@11 {
- compatible = "regulator-fixed";
- reg = <11>;
- regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
- vin-supply = <&vdd_1v05_run>;
- };
-
- vdd_5v0_hdmi: regulator@12 {
- compatible = "regulator-fixed";
- reg = <12>;
- regulator-name = "+5V_HDMI_CON";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_sys>;
- };
+ vdd_5v0_hdmi: regulator@12 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5V_HDMI_CON";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
};
sound {
@@ -1263,8 +1240,14 @@
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA124_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA124_CLK_EXTERN1>;
};
};
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index b113e47..64f488b 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/tegra124-car.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra124";
@@ -21,9 +22,9 @@
pcie@1003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
- reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
- 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
- 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
+ reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
+ <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
+ <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
@@ -37,11 +38,11 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
- 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
- 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
- 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
- 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
+ ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
+ <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
+ <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
+ <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
+ <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
clocks = <&tegra_car TEGRA124_CLK_PCIE>,
<&tegra_car TEGRA124_CLK_AFI>,
@@ -84,11 +85,13 @@
};
host1x@50000000 {
- compatible = "nvidia,tegra124-host1x", "simple-bus";
+ compatible = "nvidia,tegra124-host1x";
reg = <0x0 0x50000000 0x0 0x00034000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+ interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
+ clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
iommus = <&mc TEGRA_SWGROUP_HC>;
@@ -102,9 +105,8 @@
compatible = "nvidia,tegra124-dc";
reg = <0x0 0x54200000 0x0 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_DISP1>,
- <&tegra_car TEGRA124_CLK_PLL_P>;
- clock-names = "dc", "parent";
+ clocks = <&tegra_car TEGRA124_CLK_DISP1>;
+ clock-names = "dc";
resets = <&tegra_car 27>;
reset-names = "dc";
@@ -117,9 +119,8 @@
compatible = "nvidia,tegra124-dc";
reg = <0x0 0x54240000 0x0 0x00040000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_DISP2>,
- <&tegra_car TEGRA124_CLK_PLL_P>;
- clock-names = "dc", "parent";
+ clocks = <&tegra_car TEGRA124_CLK_DISP2>;
+ clock-names = "dc";
resets = <&tegra_car 26>;
reset-names = "dc";
@@ -157,10 +158,11 @@
reg = <0x0 0x54540000 0x0 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SOR0>,
+ <&tegra_car TEGRA124_CLK_SOR0_OUT>,
<&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
<&tegra_car TEGRA124_CLK_PLL_DP>,
<&tegra_car TEGRA124_CLK_CLK_M>;
- clock-names = "sor", "parent", "dp", "safe";
+ clock-names = "sor", "out", "parent", "dp", "safe";
resets = <&tegra_car 182>;
reset-names = "sor";
status = "disabled";
@@ -176,6 +178,11 @@
resets = <&tegra_car 181>;
reset-names = "dpaux";
status = "disabled";
+
+ i2c-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};
@@ -594,11 +601,12 @@
clocks = <&tegra_car TEGRA124_CLK_RTC>;
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra124-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
fuse@7000f800 {
@@ -619,11 +627,14 @@
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
+ #reset-cells = <1>;
};
- emc: emc@7001b000 {
+ emc: external-memory-controller@7001b000 {
compatible = "nvidia,tegra124-emc";
reg = <0x0 0x7001b000 0x0 0x1000>;
+ clocks = <&tegra_car TEGRA124_CLK_EMC>;
+ clock-names = "emc";
nvidia,memory-controller = <&mc>;
};
@@ -674,8 +685,8 @@
<&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_SS>,
- <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
+ <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
<&tegra_car TEGRA124_CLK_PLL_U_480M>,
@@ -683,7 +694,7 @@
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "xusb_host", "xusb_host_src",
"xusb_falcon_src", "xusb_ss",
- "xusb_ss_div2", "xusb_ss_src",
+ "xusb_ss_src", "xusb_ss_div2",
"xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
resets = <&tegra_car 89>, <&tegra_car 156>,
@@ -828,41 +839,45 @@
};
};
- sdhci@700b0000 {
+ mmc@700b0000 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
+ clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@700b0200 {
+ mmc@700b0200 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
+ clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@700b0400 {
+ mmc@700b0400 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
+ clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@700b0600 {
+ mmc@700b0600 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
+ clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
@@ -880,8 +895,8 @@
soctherm: thermal-sensor@700e2000 {
compatible = "nvidia,tegra124-soctherm";
- reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
- 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
+ reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
+ <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
reg-names = "soctherm-reg", "car-reg";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
@@ -1051,6 +1066,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 22>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
@@ -1088,6 +1104,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
@@ -1124,6 +1141,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 59>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
new file mode 100644
index 0000000..5dbfb83
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -0,0 +1,1429 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include "tegra20.dtsi"
+#include "tegra20-cpu-opp.dtsi"
+#include "tegra20-cpu-opp-microvolt.dtsi"
+
+/ {
+ model = "Acer Iconia Tab A500";
+ compatible = "acer,picasso", "nvidia,tegra20";
+
+ aliases {
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc3; /* MicroSD */
+ mmc2 = &sdmmc1; /* WiFi */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ serial0 = &uartd; /* Docking station */
+ serial1 = &uartc; /* Bluetooth */
+ serial2 = &uartb; /* GPS */
+ };
+
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ */
+ chosen {};
+
+ memory@0 {
+ reg = <0x00000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ramoops@2ffe0000 {
+ compatible = "ramoops";
+ reg = <0x2ffe0000 0x10000>; /* 64kB */
+ console-size = <0x8000>; /* 32kB */
+ record-size = <0x400>; /* 1kB */
+ ecc-size = <16>;
+ };
+
+ linux,cma@30000000 {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x30000000 0x10000000>;
+ size = <0x10000000>; /* 256MiB */
+ linux,cma-default;
+ reusable;
+ };
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ port@0 {
+ lcd_output: endpoint {
+ remote-endpoint = <&lvds_encoder_input>;
+ bus-width = <18>;
+ };
+ };
+ };
+ };
+
+ hdmi@54280000 {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+ hdmi-supply = <&vdd_5v0_sys>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+ GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ pinmux@70000014 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata";
+ nvidia,function = "ide";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ atc {
+ nvidia,pins = "atc";
+ nvidia,function = "nand";
+ };
+ atd {
+ nvidia,pins = "atd", "ate", "gmb", "spia",
+ "spib", "spic";
+ nvidia,function = "gmi";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp", "lm1";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+ nvidia,function = "vi";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gmc {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+ gmd {
+ nvidia,pins = "gmd";
+ nvidia,function = "sflash";
+ };
+ gpu {
+ nvidia,pins = "gpu";
+ nvidia,function = "pwm";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uartb";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+ "lsdi", "lvp0";
+ nvidia,function = "rsvd4";
+ };
+ ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lpp", "lsc0",
+ "lsc1", "lsck", "lsda", "lspi", "lvp1",
+ "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc", "spdi", "spdo", "uac";
+ nvidia,function = "rsvd2";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
+ nvidia,function = "sdio3";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxd {
+ nvidia,pins = "slxd";
+ nvidia,function = "spdif";
+ };
+ spid {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd",
+ "cdev1", "cdev2", "csus", "dap1",
+ "dap4", "dte", "dtf", "gma", "gmc",
+ "gme", "gpu", "gpu7", "gpv", "i2cp",
+ "irrx", "irtx", "pta", "rm",
+ "sdc", "sdd", "slxc", "slxd", "slxk",
+ "spdi", "spdo", "uac", "uad", "uda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_ate {
+ nvidia,pins = "ate", "dap2", "dap3",
+ "gmd", "owc", "spia", "spib", "spic",
+ "spid", "spie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "gmb", "slxa", "spig",
+ "spih";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_dte {
+ nvidia,pins = "spif";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+ "lpw1", "lsck", "lsda", "lsdi",
+ "lvp0";
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_kbca {
+ nvidia,pins = "kbca", "kbcc", "kbcd",
+ "kbce", "kbcf", "sdio1", "uaa",
+ "uab", "uca", "ucb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ };
+ conf_ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0", "lpp",
+ "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
+ "lvp1", "lvs", "pmc", "sdb";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+ drive_ddc {
+ nvidia,pins = "drive_ddc",
+ "drive_vi1",
+ "drive_sdio1";
+ nvidia,pull-up-strength = <31>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ drive_dbg {
+ nvidia,pins = "drive_dbg",
+ "drive_vi2",
+ "drive_at1",
+ "drive_ao1";
+ nvidia,pull-up-strength = <31>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ };
+
+ state_i2cmux_ddc: pinmux_i2cmux_ddc {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+
+ state_i2cmux_pta: pinmux_i2cmux_pta {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "i2c2";
+ };
+ };
+
+ state_i2cmux_idle: pinmux_i2cmux_idle {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+ };
+
+ tegra_i2s1: i2s@70002800 {
+ status = "okay";
+ };
+
+ uartb: serial@70006040 {
+ compatible = "nvidia,tegra20-hsuart";
+ /* GPS BCM4751 */
+ };
+
+ uartc: serial@70006200 {
+ compatible = "nvidia,tegra20-hsuart";
+ status = "okay";
+
+ /* Azurewave AW-NH665 BCM4329B1 */
+ bluetooth {
+ compatible = "brcm,bcm4329-bt";
+
+ /* PLLP 216MHz / 16 / 4 */
+ max-speed = <3375000>;
+
+ clocks = <&rtc_32k_wifi>;
+ clock-names = "txco";
+
+ vbat-supply = <&vdd_3v3_sys>;
+ vddio-supply = <&vdd_1v8_sys>;
+
+ device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ uartd: serial@70006300 {
+ /* Docking station */
+ };
+
+ i2c@7000c000 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ wm8903: audio-codec@1a {
+ compatible = "wlf,wm8903";
+ reg = <0x1a>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-cfg = <
+ 0x0000 /* MIC_LR_OUT# GPIO, output, low */
+ 0x0000 /* FM2018-enable GPIO, output, low */
+ 0x0000 /* Speaker-enable GPIO, output, low */
+ 0x0200 /* Interrupt, output */
+ 0x01a0 /* BCLK, input, active high */
+ >;
+
+ AVDD-supply = <&vdd_1v8_sys>;
+ CPVDD-supply = <&vdd_1v8_sys>;
+ DBVDD-supply = <&vdd_1v8_sys>;
+ DCVDD-supply = <&vdd_1v8_sys>;
+ };
+
+ touchscreen@4c {
+ compatible = "atmel,maxtouch";
+ reg = <0x4c>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+
+ vdda-supply = <&vdd_3v3_sys>;
+ vdd-supply = <&vdd_3v3_sys>;
+ };
+
+ gyroscope@68 {
+ compatible = "invensense,mpu3050";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&vdd_3v3_sys>;
+ vlogic-supply = <&vdd_1v8_sys>;
+
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "-1";
+
+ i2c-gate {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@f {
+ compatible = "kionix,kxtf9";
+ reg = <0x0f>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
+
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "-1";
+ };
+ };
+ };
+ };
+
+ i2c@7000c400 {
+ clock-frequency = <10000>;
+ status = "okay";
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-parent = <&{/i2c@7000c400}>;
+
+ pinctrl-names = "ddc", "pta", "idle";
+ pinctrl-0 = <&state_i2cmux_ddc>;
+ pinctrl-1 = <&state_i2cmux_pta>;
+ pinctrl-2 = <&state_i2cmux_idle>;
+
+ hdmi_ddc: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ panel_ddc: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ i2c@7000d000 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ magnetometer@c {
+ compatible = "ak,ak8975";
+ reg = <0x0c>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&vdd_3v3_sys>;
+ vid-supply = <&vdd_1v8_sys>;
+
+ mount-matrix = "1", "0", "0",
+ "0", "-1", "0",
+ "0", "0", "-1";
+ };
+
+ pmic: pmic@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_sys>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ sys_reg: sys {
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ vdd_core: sm0 {
+ regulator-name = "vdd_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
+ regulator-coupled-max-spread = <170000 550000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ nvidia,tegra-core-regulator;
+ };
+
+ vdd_cpu: sm1 {
+ regulator-name = "vdd_sm1,vdd_cpu";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1125000>;
+ regulator-coupled-with = <&vdd_core &rtc_vdd>;
+ regulator-coupled-max-spread = <550000 550000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ nvidia,tegra-cpu-regulator;
+ };
+
+ sm2_reg: sm2 {
+ regulator-name = "vdd_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ /* LDO0 is not connected to anything */
+
+ ldo1 {
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ rtc_vdd: ldo2 {
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-coupled-with = <&vdd_core &vdd_cpu>;
+ regulator-coupled-max-spread = <170000 550000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ nvidia,tegra-rtc-regulator;
+ };
+
+ ldo3 {
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcore_emmc: ldo5 {
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ avdd_vdac_reg: ldo6 {
+ regulator-name = "vdd_ldo6,avdd_vdac";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ hdmi_vdd_reg: ldo7 {
+ regulator-name = "vdd_ldo7,avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ hdmi_pll_reg: ldo8 {
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo9 {
+ regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo_rtc {
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ nct1008: temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+ vcc-supply = <&vdd_3v3_sys>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ pmc@7000e400 {
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <1>;
+ nvidia,cpu-pwr-good-time = <2000>;
+ nvidia,cpu-pwr-off-time = <100>;
+ nvidia,core-pwr-good-time = <3845 3845>;
+ nvidia,core-pwr-off-time = <458>;
+ nvidia,sys-clock-req-active-high;
+ };
+
+ usb@c5000000 {
+ compatible = "nvidia,tegra20-udc";
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ usb-phy@c5000000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ nvidia,xcvr-setup-use-fuses;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
+ usb@c5008000 {
+ status = "okay";
+ };
+
+ usb-phy@c5008000 {
+ status = "okay";
+ nvidia,xcvr-setup-use-fuses;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ vbus-supply = <&vdd_5v0_sys>;
+ };
+
+ brcm_wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+
+ clocks = <&rtc_32k_wifi>;
+ clock-names = "ext_clock";
+
+ reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <300>;
+ power-off-delay-us = <300>;
+ };
+
+ sdmmc1: mmc@c8000000 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+ assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+ assigned-clock-rates = <50000000>;
+
+ max-frequency = <50000000>;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ non-removable;
+
+ mmc-pwrseq = <&brcm_wifi_pwrseq>;
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+
+ /* Azurewave AW-NH611 BCM4329 */
+ wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+ };
+
+ sdmmc3: mmc@c8000400 {
+ status = "okay";
+ bus-width = <4>;
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+ };
+
+ sdmmc4: mmc@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+ non-removable;
+ };
+
+ mains: ac-adapter-detect {
+ compatible = "gpio-charger";
+ charger-type = "mains";
+ gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_3v3_sys>;
+ pwms = <&pwm 2 41667>;
+
+ brightness-levels = <7 255>;
+ num-interpolated-steps = <248>;
+ default-brightness-level = <20>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "tps658621-out32k";
+ };
+
+ /*
+ * This standalone onboard fixed-clock always-ON 32KHz
+ * oscillator is used as a reference clock-source by the
+ * Azurewave WiFi/BT module.
+ */
+ rtc_32k_wifi: clock@1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "kk3270032";
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu@1 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ display-panel {
+ compatible = "auo,b101ew05", "panel-lvds";
+
+ ddc-i2c-bus = <&panel_ddc>;
+ power-supply = <&vdd_pnl>;
+ backlight = <&backlight>;
+
+ width-mm = <218>;
+ height-mm = <135>;
+
+ data-mapping = "jeida-18";
+
+ panel-timing {
+ clock-frequency = <71200000>;
+ hactive = <1280>;
+ vactive = <800>;
+ hfront-porch = <8>;
+ hback-porch = <18>;
+ hsync-len = <184>;
+ vsync-len = <3>;
+ vfront-porch = <4>;
+ vback-porch = <8>;
+ };
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&lvds_encoder_output>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ rotation-lock {
+ label = "Rotate-lock";
+ gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
+ linux,code = <SW_ROTATE_LOCK>;
+ linux,input-type = <EV_SW>;
+ debounce-interval = <10>;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ haptic-feedback {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
+ vcc-supply = <&vdd_3v3_sys>;
+ };
+
+ lvds-encoder {
+ compatible = "ti,sn75lvds83", "lvds-encoder";
+
+ powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_encoder_input: endpoint {
+ remote-endpoint = <&lcd_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_encoder_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+ };
+
+ vdd_5v0_sys: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_3v3_sys: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_vs";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_1v8_sys: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v8_vs";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_pnl: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <300000>;
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-wm8903-picasso",
+ "nvidia,tegra-audio-wm8903";
+ nvidia,model = "Acer Iconia Tab A500 WM8903";
+
+ nvidia,audio-routing =
+ "Headphone Jack", "HPOUTR",
+ "Headphone Jack", "HPOUTL",
+ "Int Spk", "LINEOUTL",
+ "Int Spk", "LINEOUTR",
+ "Mic Jack", "MICBIAS",
+ "IN2L", "Mic Jack",
+ "IN2R", "Mic Jack",
+ "IN1L", "Int Mic",
+ "IN1R", "Int Mic";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&wm8903>;
+
+ nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
+ nvidia,headset;
+
+ clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+ <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA20_CLK_CDEV1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+ };
+
+ thermal-zones {
+ nct1008-local {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <0>; /* milliseconds */
+
+ thermal-sensors = <&nct1008 0>;
+ };
+
+ nct1008-remote {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct1008 1>;
+
+ trips {
+ trip0: cpu-alert0 {
+ /* start throttling at 50C */
+ temperature = <50000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ trip1: cpu-crit {
+ /* shut down at 60C */
+ temperature = <60000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ memory-controller@7000f400 {
+ nvidia,use-ram-code;
+
+ emc-tables@0 {
+ nvidia,ram-code = <0>; /* elpida-8gb */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ emc-table@25000 {
+ reg = <25000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <25000>;
+ nvidia,emc-registers = <0x00000002 0x00000006
+ 0x00000003 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000004
+ 0x00000003 0x00000008 0x0000000b 0x0000004d
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000068 0x00000000 0x00000003
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x00070000 0x00000000 0x00000000 0x00000003
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@50000 {
+ reg = <50000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <50000>;
+ nvidia,emc-registers = <0x00000003 0x00000007
+ 0x00000003 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x0000009f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000007
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x000000d0 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x00070000 0x00000000 0x00000000 0x00000005
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@75000 {
+ reg = <75000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <75000>;
+ nvidia,emc-registers = <0x00000005 0x0000000a
+ 0x00000004 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x000000ff
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x0000000b
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000138 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x00070000 0x00000000 0x00000000 0x00000007
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@150000 {
+ reg = <150000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <150000>;
+ nvidia,emc-registers = <0x00000009 0x00000014
+ 0x00000007 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x0000021f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000015
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000270 0x00000000 0x00000001
+ 0x00000000 0x00000000 0x00000282 0xa07c04ae
+ 0x007dd510 0x00000000 0x00000000 0x0000000e
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@300000 {
+ reg = <300000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <300000>;
+ nvidia,emc-registers = <0x00000012 0x00000027
+ 0x0000000d 0x00000006 0x00000007 0x00000005
+ 0x00000003 0x00000009 0x00000006 0x00000006
+ 0x00000003 0x00000003 0x00000002 0x00000006
+ 0x00000003 0x00000009 0x0000000c 0x0000045f
+ 0x00000000 0x00000004 0x00000004 0x00000006
+ 0x00000008 0x00000001 0x0000000e 0x0000002a
+ 0x00000003 0x0000000f 0x00000007 0x00000005
+ 0x00000002 0x000004e1 0x00000005 0x00000002
+ 0x00000000 0x00000000 0x00000282 0xe059048b
+ 0x007e1510 0x00000000 0x00000000 0x0000001b
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+
+ emc-tables@1 {
+ nvidia,ram-code = <1>; /* elpida-4gb */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ emc-table@25000 {
+ reg = <25000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <25000>;
+ nvidia,emc-registers = <0x00000002 0x00000006
+ 0x00000003 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000004
+ 0x00000003 0x00000008 0x0000000b 0x0000004d
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000068 0x00000000 0x00000003
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x0007c000 0x00000000 0x00000000 0x00000003
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@50000 {
+ reg = <50000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <50000>;
+ nvidia,emc-registers = <0x00000003 0x00000007
+ 0x00000003 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x0000009f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000007
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x000000d0 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x0007c000 0x00000000 0x00000000 0x00000005
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@75000 {
+ reg = <75000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <75000>;
+ nvidia,emc-registers = <0x00000005 0x0000000a
+ 0x00000004 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x000000ff
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x0000000b
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000138 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x0007c000 0x00000000 0x00000000 0x00000007
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@150000 {
+ reg = <150000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <150000>;
+ nvidia,emc-registers = <0x00000009 0x00000014
+ 0x00000007 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x0000021f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000015
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000270 0x00000000 0x00000001
+ 0x00000000 0x00000000 0x00000282 0xa07c04ae
+ 0x007e4010 0x00000000 0x00000000 0x0000000e
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@300000 {
+ reg = <300000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <300000>;
+ nvidia,emc-registers = <0x00000012 0x00000027
+ 0x0000000d 0x00000006 0x00000007 0x00000005
+ 0x00000003 0x00000009 0x00000006 0x00000006
+ 0x00000003 0x00000003 0x00000002 0x00000006
+ 0x00000003 0x00000009 0x0000000c 0x0000045f
+ 0x00000000 0x00000004 0x00000004 0x00000006
+ 0x00000008 0x00000001 0x0000000e 0x0000002a
+ 0x00000003 0x0000000f 0x00000007 0x00000005
+ 0x00000002 0x000004e1 0x00000005 0x00000002
+ 0x00000000 0x00000000 0x00000282 0xe059048b
+ 0x007e0010 0x00000000 0x00000000 0x0000001b
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+
+ emc-tables@2 {
+ nvidia,ram-code = <2>; /* hynix-8gb */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ emc-table@25000 {
+ reg = <25000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <25000>;
+ nvidia,emc-registers = <0x00000002 0x00000006
+ 0x00000003 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000004
+ 0x00000003 0x00000008 0x0000000b 0x0000004d
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000068 0x00000000 0x00000003
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x00070000 0x00000000 0x00000000 0x00000003
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@50000 {
+ reg = <50000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <50000>;
+ nvidia,emc-registers = <0x00000003 0x00000007
+ 0x00000003 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x0000009f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000007
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x000000d0 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x00070000 0x00000000 0x00000000 0x00000005
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@75000 {
+ reg = <75000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <75000>;
+ nvidia,emc-registers = <0x00000005 0x0000000a
+ 0x00000004 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x000000ff
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x0000000b
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000138 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x00070000 0x00000000 0x00000000 0x00000007
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@150000 {
+ reg = <150000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <150000>;
+ nvidia,emc-registers = <0x00000009 0x00000014
+ 0x00000007 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x0000021f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000015
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000270 0x00000000 0x00000001
+ 0x00000000 0x00000000 0x00000282 0xa07c04ae
+ 0x007dd010 0x00000000 0x00000000 0x0000000e
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@300000 {
+ reg = <300000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <300000>;
+ nvidia,emc-registers = <0x00000012 0x00000027
+ 0x0000000d 0x00000006 0x00000007 0x00000005
+ 0x00000003 0x00000009 0x00000006 0x00000006
+ 0x00000003 0x00000003 0x00000002 0x00000006
+ 0x00000003 0x00000009 0x0000000c 0x0000045f
+ 0x00000000 0x00000004 0x00000004 0x00000006
+ 0x00000008 0x00000001 0x0000000e 0x0000002a
+ 0x00000003 0x0000000f 0x00000007 0x00000005
+ 0x00000002 0x000004e1 0x00000005 0x00000002
+ 0x00000000 0x00000000 0x00000282 0xe059048b
+ 0x007e2010 0x00000000 0x00000000 0x0000001b
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+
+ emc-tables@3 {
+ nvidia,ram-code = <3>; /* hynix-4gb */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ emc-table@25000 {
+ reg = <25000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <25000>;
+ nvidia,emc-registers = <0x00000002 0x00000006
+ 0x00000003 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000004
+ 0x00000003 0x00000008 0x0000000b 0x0000004d
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000004
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000068 0x00000000 0x00000003
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x0007c000 0x00000000 0x00000000 0x00000003
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@50000 {
+ reg = <50000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <50000>;
+ nvidia,emc-registers = <0x00000003 0x00000007
+ 0x00000003 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x0000009f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000007
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x000000d0 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x0007c000 0x00078000 0x00000000 0x00000005
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@75000 {
+ reg = <75000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <75000>;
+ nvidia,emc-registers = <0x00000005 0x0000000a
+ 0x00000004 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x000000ff
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x0000000b
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000138 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000282 0xa0ae04ae
+ 0x0007c000 0x00000000 0x00000000 0x00000007
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@150000 {
+ reg = <150000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <150000>;
+ nvidia,emc-registers = <0x00000009 0x00000014
+ 0x00000007 0x00000003 0x00000006 0x00000004
+ 0x00000002 0x00000009 0x00000003 0x00000003
+ 0x00000002 0x00000002 0x00000002 0x00000005
+ 0x00000003 0x00000008 0x0000000b 0x0000021f
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000008 0x00000001 0x0000000a 0x00000015
+ 0x00000003 0x00000008 0x00000004 0x00000006
+ 0x00000002 0x00000270 0x00000000 0x00000001
+ 0x00000000 0x00000000 0x00000282 0xa07c04ae
+ 0x007e4010 0x00000000 0x00000000 0x0000000e
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@300000 {
+ reg = <300000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <300000>;
+ nvidia,emc-registers = <0x00000012 0x00000027
+ 0x0000000d 0x00000006 0x00000007 0x00000005
+ 0x00000003 0x00000009 0x00000006 0x00000006
+ 0x00000003 0x00000003 0x00000002 0x00000006
+ 0x00000003 0x00000009 0x0000000c 0x0000045f
+ 0x00000000 0x00000004 0x00000004 0x00000006
+ 0x00000008 0x00000001 0x0000000e 0x0000002a
+ 0x00000003 0x0000000f 0x00000007 0x00000005
+ 0x00000002 0x000004e1 0x00000005 0x00000002
+ 0x00000000 0x00000000 0x00000282 0xe059048b
+ 0x007e0010 0x00000000 0x00000000 0x0000001b
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
index 3c0f268..a05fb38 100644
--- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
@@ -183,7 +183,7 @@
};
/* SD/MMC */
- sdhci@c8000600 {
+ mmc@c8000600 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
@@ -223,7 +223,7 @@
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
- compatible = "edt,et057090dhu", "simple-panel";
+ compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <®_3v3>;
};
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index d8004d6..425494b 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -171,7 +171,7 @@
};
/* SD/MMC */
- sdhci@c8000600 {
+ mmc@c8000600 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
@@ -205,7 +205,7 @@
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
- compatible = "edt,et057090dhu", "simple-panel";
+ compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <®_3v3>;
};
diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi
new file mode 100644
index 0000000..6f3e8c5
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ cpu0_opp_table: cpu_opp_table0 {
+ opp@216000000,750 {
+ opp-microvolt = <750000 750000 1125000>;
+ };
+
+ opp@216000000,800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@312000000,750 {
+ opp-microvolt = <750000 750000 1125000>;
+ };
+
+ opp@312000000,800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@456000000,750 {
+ opp-microvolt = <750000 750000 1125000>;
+ };
+
+ opp@456000000,800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@456000000,825 {
+ opp-microvolt = <825000 825000 1125000>;
+ };
+
+ opp@608000000,750 {
+ opp-microvolt = <750000 750000 1125000>;
+ };
+
+ opp@608000000,800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@608000000,825 {
+ opp-microvolt = <825000 825000 1125000>;
+ };
+
+ opp@608000000,850 {
+ opp-microvolt = <850000 850000 1125000>;
+ };
+
+ opp@608000000,900 {
+ opp-microvolt = <900000 900000 1125000>;
+ };
+
+ opp@760000000,775 {
+ opp-microvolt = <775000 775000 1125000>;
+ };
+
+ opp@760000000,800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@760000000,850 {
+ opp-microvolt = <850000 850000 1125000>;
+ };
+
+ opp@760000000,875 {
+ opp-microvolt = <875000 875000 1125000>;
+ };
+
+ opp@760000000,900 {
+ opp-microvolt = <900000 900000 1125000>;
+ };
+
+ opp@760000000,975 {
+ opp-microvolt = <975000 975000 1125000>;
+ };
+
+ opp@816000000,800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@816000000,850 {
+ opp-microvolt = <850000 850000 1125000>;
+ };
+
+ opp@816000000,875 {
+ opp-microvolt = <875000 875000 1125000>;
+ };
+
+ opp@816000000,950 {
+ opp-microvolt = <950000 950000 1125000>;
+ };
+
+ opp@816000000,1000 {
+ opp-microvolt = <1000000 1000000 1125000>;
+ };
+
+ opp@912000000,850 {
+ opp-microvolt = <850000 850000 1125000>;
+ };
+
+ opp@912000000,900 {
+ opp-microvolt = <900000 900000 1125000>;
+ };
+
+ opp@912000000,925 {
+ opp-microvolt = <925000 925000 1125000>;
+ };
+
+ opp@912000000,950 {
+ opp-microvolt = <950000 950000 1125000>;
+ };
+
+ opp@912000000,1000 {
+ opp-microvolt = <1000000 1000000 1125000>;
+ };
+
+ opp@912000000,1050 {
+ opp-microvolt = <1050000 1050000 1125000>;
+ };
+
+ opp@1000000000,875 {
+ opp-microvolt = <875000 875000 1125000>;
+ };
+
+ opp@1000000000,900 {
+ opp-microvolt = <900000 900000 1125000>;
+ };
+
+ opp@1000000000,950 {
+ opp-microvolt = <950000 950000 1125000>;
+ };
+
+ opp@1000000000,975 {
+ opp-microvolt = <975000 975000 1125000>;
+ };
+
+ opp@1000000000,1000 {
+ opp-microvolt = <1000000 1000000 1125000>;
+ };
+
+ opp@1000000000,1025 {
+ opp-microvolt = <1025000 1025000 1125000>;
+ };
+
+ opp@1000000000,1100 {
+ opp-microvolt = <1100000 1100000 1125000>;
+ };
+
+ opp@1200000000,1000 {
+ opp-microvolt = <1000000 1000000 1125000>;
+ };
+
+ opp@1200000000,1050 {
+ opp-microvolt = <1050000 1050000 1125000>;
+ };
+
+ opp@1200000000,1100 {
+ opp-microvolt = <1100000 1100000 1125000>;
+ };
+
+ opp@1200000000,1125 {
+ opp-microvolt = <1125000 1125000 1125000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi
new file mode 100644
index 0000000..702a635
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ cpu0_opp_table: cpu_opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@216000000,750 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x0F 0x0003>;
+ opp-hz = /bits/ 64 <216000000>;
+ };
+
+ opp@216000000,800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x0F 0x0004>;
+ opp-hz = /bits/ 64 <216000000>;
+ };
+
+ opp@312000000,750 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x0F 0x0003>;
+ opp-hz = /bits/ 64 <312000000>;
+ };
+
+ opp@312000000,800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x0F 0x0004>;
+ opp-hz = /bits/ 64 <312000000>;
+ };
+
+ opp@456000000,750 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x0C 0x0003>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@456000000,800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0006>, <0x04 0x0004>,
+ <0x08 0x0004>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@456000000,825 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@608000000,750 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0003>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@608000000,800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0006>, <0x08 0x0004>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@608000000,825 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0001>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@608000000,850 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0006>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@608000000,900 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@760000000,775 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0003>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000,800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0004>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000,850 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0006>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000,875 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0001>, <0x02 0x0002>,
+ <0x01 0x0004>, <0x02 0x0004>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000,900 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0002>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000,975 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@816000000,800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0007>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@816000000,850 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0002>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@816000000,875 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0005>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@816000000,950 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0006>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@816000000,1000 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@912000000,850 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0007>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000,900 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0002>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000,925 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0001>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000,950 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>,
+ <0x04 0x0004>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000,1000 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0002>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000,1050 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@1000000000,875 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0007>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000,900 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0002>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000,950 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0004>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000,975 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0001>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000,1000 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x02 0x0006>, <0x01 0x0004>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000,1025 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0002>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000,1100 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1200000000,1000 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0004>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000,1050 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0004>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000,1100 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x02 0x0004>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000,1125 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0004>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 1d96d92..ae4312e 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -613,7 +613,7 @@
status = "okay";
};
- sdhci@c8000200 {
+ mmc@c8000200 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
@@ -621,7 +621,7 @@
bus-width = <4>;
};
- sdhci@c8000600 {
+ mmc@c8000600 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
@@ -640,17 +640,10 @@
default-brightness-level = <6>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-keys {
@@ -665,7 +658,7 @@
};
panel: panel {
- compatible = "auo,b101aw03", "simple-panel";
+ compatible = "auo,b101aw03";
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
@@ -673,79 +666,66 @@
backlight = <&backlight>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- vdd_5v0_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+ };
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vdd_1v5";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
- };
+ regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "vdd_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ pci_vdd_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v05";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- pci_vdd_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "vdd_1v05";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vdd_pnl_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_pnl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vdd_pnl_reg: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "vdd_pnl";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vdd_bl_reg: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vdd_bl_reg: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "vdd_bl";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vdd_5v0_hdmi: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "VDDIO_HDMI";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_reg>;
- };
+ vdd_5v0_hdmi: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_HDMI";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_reg>;
};
sound {
@@ -768,7 +748,7 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
- GPIO_ACTIVE_HIGH>;
+ GPIO_ACTIVE_LOW>;
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
GPIO_ACTIVE_HIGH>;
nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index cda5448..b31c9bc 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -57,9 +57,9 @@
};
panel: panel {
- compatible = "innolux,n156bge-l21", "simple-panel";
+ compatible = "innolux,n156bge-l21";
- power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>;
+ power-supply = <&vdd_1v8_reg>; // <&vdd_3v3_reg>;
enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
@@ -84,7 +84,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
@@ -92,44 +92,38 @@
clock-names = "pll_a", "pll_a_out0", "mclk";
};
- regulators {
- vcc_24v_reg: regulator@100 {
- compatible = "regulator-fixed";
- reg = <100>;
- regulator-name = "vcc_24v";
- regulator-min-microvolt = <24000000>;
- regulator-max-microvolt = <24000000>;
- regulator-always-on;
- };
+ vcc_24v_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_24v";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ regulator-always-on;
+ };
- vdd_5v0_reg: regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
- regulator-name = "vdd_5v0";
- vin-supply = <&vcc_24v_reg>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ vdd_5v0_reg: regulator@101 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ vin-supply = <&vcc_24v_reg>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- vdd_3v3_reg: regulator@102 {
- compatible = "regulator-fixed";
- reg = <102>;
- regulator-name = "vdd_3v3";
- vin-supply = <&vcc_24v_reg>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
+ vdd_3v3_reg: regulator@102 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ vin-supply = <&vcc_24v_reg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
- vdd_1v8_reg: regulator@103 {
- compatible = "regulator-fixed";
- reg = <103>;
- regulator-name = "vdd_1v8";
- vin-supply = <&vdd_3v3_reg>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
+ vdd_1v8_reg: regulator@103 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v8";
+ vin-supply = <&vdd_3v3_reg>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
};
};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 8861e09..ada2bed 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -3,6 +3,8 @@
#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
+#include "tegra20-cpu-opp.dtsi"
+#include "tegra20-cpu-opp-microvolt.dtsi"
/ {
model = "Toshiba AC100 / Dynabook AZ";
@@ -309,6 +311,52 @@
reset-names = "i2c";
};
+ memory-controller@7000f400 {
+ nvidia,use-ram-code;
+
+ emc-tables@0 {
+ nvidia,ram-code = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ emc-table@166500 {
+ reg = <166500>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <166500>;
+ nvidia,emc-registers = <0x0000000a 0x00000016
+ 0x00000008 0x00000003 0x00000004 0x00000004
+ 0x00000002 0x0000000c 0x00000003 0x00000003
+ 0x00000002 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x000004df
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000003 0x00000001 0x0000000a 0x000000c8
+ 0x00000003 0x00000006 0x00000004 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xe03b0323
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@333000 {
+ reg = <333000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <333000>;
+ nvidia,emc-registers = <0x00000018 0x00000033
+ 0x00000012 0x00000004 0x00000004 0x00000005
+ 0x00000003 0x0000000c 0x00000006 0x00000006
+ 0x00000003 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x00000bff
+ 0x00000000 0x00000003 0x00000003 0x00000006
+ 0x00000006 0x00000001 0x00000011 0x000000c8
+ 0x00000003 0x0000000e 0x00000007 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xf0440303
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+ };
+
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
@@ -337,18 +385,26 @@
regulator-always-on;
};
- sm0 {
+ core_vdd_reg: sm0 {
regulator-name = "+1.2vs_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
+ regulator-max-microvolt = <1225000>;
+ regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
+ regulator-coupled-max-spread = <170000 450000>;
regulator-always-on;
+
+ nvidia,tegra-core-regulator;
};
- sm1 {
+ cpu_vdd_reg: sm1 {
regulator-name = "+1.0vs_sm1,vdd_cpu";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
+ regulator-coupled-max-spread = <450000 450000>;
regulator-always-on;
+
+ nvidia,tegra-cpu-regulator;
};
sm2_reg: sm2 {
@@ -367,10 +423,15 @@
regulator-always-on;
};
- ldo2 {
+ rtc_vdd_reg: ldo2 {
regulator-name = "+1.2vs_ldo2,vdd_rtc";
regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
+ regulator-max-microvolt = <1225000>;
+ regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
+ regulator-coupled-max-spread = <170000 450000>;
+ regulator-always-on;
+
+ nvidia,tegra-rtc-regulator;
};
ldo3 {
@@ -482,7 +543,7 @@
status = "okay";
};
- sdhci@c8000000 {
+ mmc@c8000000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
@@ -490,7 +551,7 @@
bus-width = <4>;
};
- sdhci@c8000600 {
+ mmc@c8000600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -508,17 +569,10 @@
backlight-boot-off;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-keys {
@@ -535,7 +589,7 @@
gpio-leds {
compatible = "gpio-leds";
- wifi {
+ led-0 {
label = "wifi-led";
gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
linux,default-trigger = "rfkill0";
@@ -543,7 +597,7 @@
};
panel: panel {
- compatible = "samsung,ltn101nt05", "simple-panel";
+ compatible = "samsung,ltn101nt05";
ddc-i2c-bus = <&lvds_ddc>;
power-supply = <&vdd_pnl_reg>;
@@ -552,30 +606,22 @@
backlight = <&backlight>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ p5valw_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "+5valw";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- p5valw_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "+5valw";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vdd_pnl_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "+3VS,vdd_pnl";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vdd_pnl_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "+3VS,vdd_pnl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
sound {
@@ -603,4 +649,16 @@
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&cpu_vdd_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@1 {
+ cpu-supply = <&cpu_vdd_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 429e460..5811b70 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -52,7 +52,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
@@ -60,44 +60,38 @@
clock-names = "pll_a", "pll_a_out0", "mclk";
};
- regulators {
- vcc_24v_reg: regulator@100 {
- compatible = "regulator-fixed";
- reg = <100>;
- regulator-name = "vcc_24v";
- regulator-min-microvolt = <24000000>;
- regulator-max-microvolt = <24000000>;
- regulator-always-on;
- };
+ vcc_24v_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_24v";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ regulator-always-on;
+ };
- vdd_5v0_reg: regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
- regulator-name = "vdd_5v0";
- vin-supply = <&vcc_24v_reg>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ vdd_5v0_reg: regulator@101 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ vin-supply = <&vcc_24v_reg>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- vdd_3v3_reg: regulator@102 {
- compatible = "regulator-fixed";
- reg = <102>;
- regulator-name = "vdd_3v3";
- vin-supply = <&vcc_24v_reg>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
+ vdd_3v3_reg: regulator@102 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ vin-supply = <&vcc_24v_reg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
- vdd_1v8_reg: regulator@103 {
- compatible = "regulator-fixed";
- reg = <103>;
- regulator-name = "vdd_1v8";
- vin-supply = <&vdd_3v3_reg>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
+ vdd_1v8_reg: regulator@103 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v8";
+ vin-supply = <&vdd_3v3_reg>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
};
};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index f914416..92d494b 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -394,10 +394,10 @@
#size-cells = <0>;
smart-battery@b {
- compatible = "ti,bq20z75", "smart-battery-1.1";
+ compatible = "ti,bq20z75", "sbs,sbs-battery";
reg = <0xb>;
- ti,i2c-retry-count = <2>;
- ti,poll-retry-count = <10>;
+ sbs,i2c-retry-count = <2>;
+ sbs,poll-retry-count = <10>;
};
};
};
@@ -760,14 +760,14 @@
status = "okay";
};
- sdhci@c8000000 {
+ mmc@c8000000 {
status = "okay";
power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
- sdhci@c8000400 {
+ mmc@c8000400 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
@@ -775,7 +775,7 @@
bus-width = <4>;
};
- sdhci@c8000600 {
+ mmc@c8000600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -792,17 +792,10 @@
default-brightness-level = <6>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-keys {
@@ -826,7 +819,7 @@
};
panel: panel {
- compatible = "chunghwa,claa101wa01a", "simple-panel";
+ compatible = "chunghwa,claa101wa01a";
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
@@ -835,81 +828,68 @@
ddc-i2c-bus = <&lvds_ddc>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- vdd_5v0_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+ };
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vdd_1v5";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
- };
+ regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "vdd_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vbus_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_vbus_wup1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- vbus_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "vdd_vbus_wup1";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
- regulator-always-on;
- regulator-boot-on;
- };
+ vdd_pnl_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_pnl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vdd_pnl_reg: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "vdd_pnl";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vdd_bl_reg: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vdd_bl_reg: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "vdd_bl";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vdd_hdmi: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "VDDIO_HDMI";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- vin-supply = <&vdd_5v0_reg>;
- };
+ vdd_hdmi: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_HDMI";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_5v0_reg>;
};
sound {
@@ -931,7 +911,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 394a6b4..dd4d506 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -495,40 +495,25 @@
status = "okay";
};
- sdhci@c8000600 {
+ mmc@c8000600 {
cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
- regulators {
- compatible = "simple-bus";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- pci_vdd_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vdd_1v05";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- gpio = <&pmic 2 0>;
- enable-active-high;
- };
+ pci_vdd_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v05";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&pmic 2 0>;
+ enable-active-high;
};
};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 4dec277..10ff09d 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -61,7 +61,7 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
- GPIO_ACTIVE_HIGH>;
+ GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
@@ -69,44 +69,38 @@
clock-names = "pll_a", "pll_a_out0", "mclk";
};
- regulators {
- vcc_24v_reg: regulator@100 {
- compatible = "regulator-fixed";
- reg = <100>;
- regulator-name = "vcc_24v";
- regulator-min-microvolt = <24000000>;
- regulator-max-microvolt = <24000000>;
- regulator-always-on;
- };
+ vcc_24v_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_24v";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ regulator-always-on;
+ };
- vdd_5v0_reg: regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
- regulator-name = "vdd_5v0";
- vin-supply = <&vcc_24v_reg>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ vdd_5v0_reg: regulator@101 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ vin-supply = <&vcc_24v_reg>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- vdd_3v3_reg: regulator@102 {
- compatible = "regulator-fixed";
- reg = <102>;
- regulator-name = "vdd_3v3";
- vin-supply = <&vcc_24v_reg>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
+ vdd_3v3_reg: regulator@102 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ vin-supply = <&vcc_24v_reg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
- vdd_1v8_reg: regulator@103 {
- compatible = "regulator-fixed";
- reg = <103>;
- regulator-name = "vdd_1v8";
- vin-supply = <&vdd_3v3_reg>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
+ vdd_1v8_reg: regulator@103 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v8";
+ vin-supply = <&vdd_3v3_reg>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
};
};
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 3e5ac09..4bc87bc 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -3,6 +3,7 @@
#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
+#include "tegra20-cpu-opp.dtsi"
/ {
model = "Compulab TrimSlice board";
@@ -365,30 +366,23 @@
status = "okay";
};
- sdhci@c8000000 {
+ mmc@c8000000 {
status = "okay";
broken-cd;
bus-width = <4>;
};
- sdhci@c8000600 {
+ mmc@c8000600 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-keys {
@@ -407,58 +401,47 @@
gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ hdmi_vdd_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
- hdmi_vdd_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "avdd_hdmi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
+ hdmi_pll_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
- hdmi_pll_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "avdd_hdmi_pll";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
+ vbus_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
- vbus_reg: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "usb1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
- regulator-always-on;
- regulator-boot-on;
- };
+ pci_clk_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "pci_clk";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
- pci_clk_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "pci_clk";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- pci_vdd_reg: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "pci_vdd";
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- regulator-always-on;
- };
+ pci_vdd_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "pci_vdd";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
};
sound {
@@ -471,4 +454,14 @@
<&tegra_car TEGRA20_CLK_CDEV1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
+
+ cpus {
+ cpu0: cpu@0 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@1 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index f44551e..fe400fb 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -3,6 +3,7 @@
#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"
+#include "tegra20-cpu-opp.dtsi"
/ {
model = "NVIDIA Tegra20 Ventana evaluation board";
@@ -554,14 +555,14 @@
status = "okay";
};
- sdhci@c8000000 {
+ mmc@c8000000 {
status = "okay";
power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
- sdhci@c8000400 {
+ mmc@c8000400 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
@@ -569,7 +570,7 @@
bus-width = <4>;
};
- sdhci@c8000600 {
+ mmc@c8000600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -586,16 +587,19 @@
default-brightness-level = <6>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
+ cpus {
+ cpu0: cpu@0 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@1 {
+ operating-points-v2 = <&cpu0_opp_table>;
};
};
@@ -611,7 +615,7 @@
};
panel: panel {
- compatible = "chunghwa,claa101wa01a", "simple-panel";
+ compatible = "chunghwa,claa101wa01a";
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
@@ -620,58 +624,47 @@
ddc-i2c-bus = <&lvds_ddc>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- vdd_5v0_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+ };
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "vdd_1v5";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
- };
+ regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "vdd_1v2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vdd_pnl_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_pnl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
- vdd_pnl_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "vdd_pnl";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vdd_bl_reg: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "vdd_bl";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vdd_bl_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
sound {
@@ -693,7 +686,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
GPIO_ACTIVE_HIGH>;
nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8c942e6..72a4211 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra20-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra20";
@@ -16,25 +17,27 @@
reg = <0 0>;
};
- iram@40000000 {
+ sram@40000000 {
compatible = "mmio-sram";
reg = <0x40000000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40000000 0x40000>;
- vde_pool: vde@400 {
+ vde_pool: sram@400 {
reg = <0x400 0x3fc00>;
pool;
};
};
host1x@50000000 {
- compatible = "nvidia,tegra20-host1x", "simple-bus";
+ compatible = "nvidia,tegra20-host1x";
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+ interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+ clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
@@ -153,7 +156,9 @@
dsi@54300000 {
compatible = "nvidia,tegra20-dsi";
reg = <0x54300000 0x00040000>;
- clocks = <&tegra_car TEGRA20_CLK_DSI>;
+ clocks = <&tegra_car TEGRA20_CLK_DSI>,
+ <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
status = "disabled";
@@ -171,8 +176,8 @@
intc: interrupt-controller@50041000 {
compatible = "arm,cortex-a9-gic";
- reg = <0x50041000 0x1000
- 0x50040100 0x0100>;
+ reg = <0x50041000 0x1000>,
+ <0x50040100 0x0100>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&intc>;
@@ -271,15 +276,15 @@
vde@6001a000 {
compatible = "nvidia,tegra20-vde";
- reg = <0x6001a000 0x1000 /* Syntax Engine */
- 0x6001b000 0x1000 /* Video Bitstream Engine */
- 0x6001c000 0x100 /* Macroblock Engine */
- 0x6001c200 0x100 /* Post-processing Engine */
- 0x6001c400 0x100 /* Motion Compensation Engine */
- 0x6001c600 0x100 /* Transform Engine */
- 0x6001c800 0x100 /* Pixel prediction block */
- 0x6001ca00 0x100 /* Video DMA */
- 0x6001d800 0x300>; /* Video frame controls */
+ reg = <0x6001a000 0x1000>, /* Syntax Engine */
+ <0x6001b000 0x1000>, /* Video Bitstream Engine */
+ <0x6001c000 0x100>, /* Macroblock Engine */
+ <0x6001c200 0x100>, /* Post-processing Engine */
+ <0x6001c400 0x100>, /* Motion Compensation Engine */
+ <0x6001c600 0x100>, /* Transform Engine */
+ <0x6001c800 0x100>, /* Pixel prediction block */
+ <0x6001ca00 0x100>, /* Video DMA */
+ <0x6001d800 0x300>; /* Video frame controls */
reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
"tfe", "ppb", "vdma", "frameid";
iram = <&vde_pool>; /* IRAM region */
@@ -294,16 +299,16 @@
apbmisc@70000800 {
compatible = "nvidia,tegra20-apbmisc";
- reg = <0x70000800 0x64 /* Chip revision */
- 0x70000008 0x04>; /* Strapping options */
+ reg = <0x70000800 0x64>, /* Chip revision */
+ <0x70000008 0x04>; /* Strapping options */
};
pinmux: pinmux@70000014 {
compatible = "nvidia,tegra20-pinmux";
- reg = <0x70000014 0x10 /* Tri-state registers */
- 0x70000080 0x20 /* Mux registers */
- 0x700000a0 0x14 /* Pull-up/down registers */
- 0x70000868 0xa8>; /* Pad control registers */
+ reg = <0x70000014 0x10>, /* Tri-state registers */
+ <0x70000080 0x20>, /* Mux registers */
+ <0x700000a0 0x14>, /* Pull-up/down registers */
+ <0x70000868 0xa8>; /* Pad control registers */
};
das@70000c00 {
@@ -608,17 +613,18 @@
status = "disabled";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
mc: memory-controller@7000f000 {
compatible = "nvidia,tegra20-mc-gart";
- reg = <0x7000f000 0x400 /* controller registers */
- 0x58000000 0x02000000>; /* GART aperture */
+ reg = <0x7000f000 0x00000400>, /* controller registers */
+ <0x58000000 0x02000000>; /* GART aperture */
clocks = <&tegra_car TEGRA20_CLK_MC>;
clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
@@ -647,12 +653,12 @@
pcie@80003000 {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
- reg = <0x80003000 0x00000800 /* PADS registers */
- 0x80003800 0x00000200 /* AFI registers */
- 0x90000000 0x10000000>; /* configuration space */
+ reg = <0x80003000 0x00000800>, /* PADS registers */
+ <0x80003800 0x00000200>, /* AFI registers */
+ <0x90000000 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
- GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
@@ -663,11 +669,11 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
- 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
- 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
- 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
+ ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
+ <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
+ <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */
+ <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
+ <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
clocks = <&tegra_car TEGRA20_CLK_PEX>,
<&tegra_car TEGRA20_CLK_AFI>,
@@ -724,7 +730,8 @@
phy1: usb-phy@c5000000 {
compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
+ reg = <0xc5000000 0x4000>,
+ <0xc5000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA20_CLK_USBD>,
<&tegra_car TEGRA20_CLK_PLL_U>,
@@ -733,6 +740,7 @@
clock-names = "reg", "pll_u", "timer", "utmi-pads";
resets = <&tegra_car 22>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,has-legacy-mode;
nvidia,hssync-start-delay = <9>;
nvidia,idle-wait-delay = <17>;
@@ -767,6 +775,7 @@
clock-names = "reg", "pll_u", "ulpi-link";
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
status = "disabled";
};
@@ -784,7 +793,8 @@
phy3: usb-phy@c5008000 {
compatible = "nvidia,tegra20-usb-phy";
- reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
+ reg = <0xc5008000 0x4000>,
+ <0xc5000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA20_CLK_USB3>,
<&tegra_car TEGRA20_CLK_PLL_U>,
@@ -793,6 +803,7 @@
clock-names = "reg", "pll_u", "timer", "utmi-pads";
resets = <&tegra_car 59>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <9>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
@@ -803,41 +814,45 @@
status = "disabled";
};
- sdhci@c8000000 {
+ mmc@c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+ clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@c8000200 {
+ mmc@c8000200 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
+ clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@c8000400 {
+ mmc@c8000400 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
+ clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@c8000600 {
+ mmc@c8000600 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
+ clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
@@ -851,12 +866,14 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ clocks = <&tegra_car TEGRA20_CLK_CCLK>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ clocks = <&tegra_car TEGRA20_CLK_CCLK>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 749fc6d..9f653ef 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -120,7 +120,7 @@
};
/* Apalis SD1 */
- sdhci@78000000 {
+ mmc@78000000 {
status = "okay";
bus-width = <4>;
/* SD1_CD# */
@@ -129,7 +129,7 @@
};
/* Apalis MMC1 */
- sdhci@78000400 {
+ mmc@78000400 {
status = "okay";
bus-width = <8>;
/* MMC1_CD# */
@@ -195,7 +195,7 @@
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
- compatible = "edt,et057090dhu", "simple-panel";
+ compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <®_3v3>;
};
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
index 0be50e8..86e138e 100644
--- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
@@ -121,7 +121,7 @@
};
/* Apalis SD1 */
- sdhci@78000000 {
+ mmc@78000000 {
status = "okay";
bus-width = <4>;
/* SD1_CD# */
@@ -130,7 +130,7 @@
};
/* Apalis MMC1 */
- sdhci@78000400 {
+ mmc@78000400 {
status = "okay";
bus-width = <8>;
/* MMC1_CD# */
@@ -196,7 +196,7 @@
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
- compatible = "edt,et057090dhu", "simple-panel";
+ compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <®_3v3>;
};
@@ -248,8 +248,8 @@
regulator-max-microvolt = <3300000>;
regulator-type = "voltage";
gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0
- 3300000 0x1>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
startup-delay-us = <100000>;
vin-supply = <&vddio_sdmmc_1v8_reg>;
};
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
index 02f8126..6a3a72f 100644
--- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
@@ -37,7 +37,7 @@
status = "okay";
nvidia,num-lanes = <1>;
- pcie@0 {
+ ethernet@0,0 {
reg = <0 0 0 0 0>;
local-mac-address = [00 00 00 00 00 00];
};
@@ -855,6 +855,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <®_module_3v3_audio>;
VDDD-supply = <®_1v8_vio>;
VDDIO-supply = <®_module_3v3>;
@@ -994,11 +995,17 @@
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+ /* ADC converstion time: 80 clocks */
+ st,sample-time = <4>;
stmpe_touchscreen {
compatible = "st,stmpe-ts";
- /* 3.25 MHz ADC clock speed */
- st,adc-freq = <1>;
/* 8 sample average control */
st,ave-ctrl = <3>;
/* 7 length fractional part in z */
@@ -1008,17 +1015,17 @@
* current limit value
*/
st,i-drive = <1>;
- /* 12-bit ADC */
- st,mod-12b = <1>;
- /* internal ADC reference */
- st,ref-sel = <0>;
- /* ADC converstion time: 80 clocks */
- st,sample-time = <4>;
/* 1 ms panel driver settling time */
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
};
+
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ /* forbid to use ADC channels 3-0 (touch) */
+ st,norequest-mask = <0x0F>;
+ };
};
/*
@@ -1106,7 +1113,7 @@
};
/* eMMC */
- sdhci@78000600 {
+ mmc@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -1183,7 +1190,13 @@
nvidia,audio-codec = <&sgtl5000>;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA30_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 7f112f1..6544ce7 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -36,7 +36,7 @@
status = "okay";
nvidia,num-lanes = <1>;
- pcie@0 {
+ ethernet@0,0 {
reg = <0 0 0 0 0>;
local-mac-address = [00 00 00 00 00 00];
};
@@ -846,6 +846,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <®_module_3v3_audio>;
VDDD-supply = <®_1v8_vio>;
VDDIO-supply = <®_module_3v3>;
@@ -976,11 +977,17 @@
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+ /* ADC converstion time: 80 clocks */
+ st,sample-time = <4>;
stmpe_touchscreen {
compatible = "st,stmpe-ts";
- /* 3.25 MHz ADC clock speed */
- st,adc-freq = <1>;
/* 8 sample average control */
st,ave-ctrl = <3>;
/* 7 length fractional part in z */
@@ -990,17 +997,17 @@
* current limit value
*/
st,i-drive = <1>;
- /* 12-bit ADC */
- st,mod-12b = <1>;
- /* internal ADC reference */
- st,ref-sel = <0>;
- /* ADC converstion time: 80 clocks */
- st,sample-time = <4>;
/* 1 ms panel driver settling time */
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
};
+
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ /* forbid to use ADC channels 3-0 (touch) */
+ st,norequest-mask = <0x0F>;
+ };
};
/*
@@ -1088,7 +1095,7 @@
};
/* eMMC */
- sdhci@78000600 {
+ mmc@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -1165,7 +1172,13 @@
nvidia,audio-codec = <&sgtl5000>;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA30_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts
new file mode 100644
index 0000000..a25b856
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi"
+#include "tegra30-asus-nexus7-grouper.dtsi"
+
+/ {
+ model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565";
+};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts
new file mode 100644
index 0000000..06ef13e
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-nexus7-grouper-ti-pmic.dtsi"
+#include "tegra30-asus-nexus7-grouper.dtsi"
+
+/ {
+ model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269";
+};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
new file mode 100644
index 0000000..88ca03f
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -0,0 +1,1280 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/power/summit,smb347-charger.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include "tegra30.dtsi"
+#include "tegra30-cpu-opp.dtsi"
+#include "tegra30-cpu-opp-microvolt.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc3; /* WiFi */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ serial1 = &uartc; /* Bluetooth */
+ serial2 = &uartb; /* GPS */
+ };
+
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ */
+ chosen {};
+
+ memory@80000000 {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma@80000000 {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x80000000 0x30000000>;
+ size = <0x10000000>; /* 256MiB */
+ linux,cma-default;
+ reusable;
+ };
+
+ ramoops@bfdf0000 {
+ compatible = "ramoops";
+ reg = <0xbfdf0000 0x10000>; /* 64kB */
+ console-size = <0x8000>; /* 32kB */
+ record-size = <0x400>; /* 1kB */
+ ecc-size = <16>;
+ };
+
+ trustzone@bfe00000 {
+ reg = <0xbfe00000 0x200000>;
+ no-map;
+ };
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ port@0 {
+ lcd_output: endpoint {
+ remote-endpoint = <&lvds_encoder_input>;
+ bus-width = <24>;
+ };
+ };
+ };
+ };
+ };
+
+ gpio@6000d000 {
+ init-mode {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+
+ init-low-power-mode {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ };
+
+ pinmux@70000868 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ clk_32k_out_pa0 {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "blink";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart3_cts_n_pa1 {
+ nvidia,pins = "uart3_cts_n_pa1",
+ "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2",
+ "dap2_sclk_pa3",
+ "dap2_din_pa4",
+ "dap2_dout_pa5";
+ nvidia,function = "i2s1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7",
+ "sdmmc3_dat3_pb4",
+ "sdmmc3_dat2_pb5",
+ "sdmmc3_dat1_pb6",
+ "sdmmc3_dat0_pb7",
+ "sdmmc3_dat4_pd1",
+ "sdmmc3_dat6_pd3",
+ "sdmmc3_dat7_pd4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_a17_pb0 {
+ nvidia,pins = "gmi_a17_pb0",
+ "gmi_a18_pb1";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_pwr0_pb2 {
+ nvidia,pins = "lcd_pwr0_pb2",
+ "lcd_pwr1_pc1",
+ "lcd_m1_pw1";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd_pclk_pb3 {
+ nvidia,pins = "lcd_pclk_pb3",
+ "lcd_d0_pe0",
+ "lcd_d1_pe1",
+ "lcd_d2_pe2",
+ "lcd_d3_pe3",
+ "lcd_d4_pe4",
+ "lcd_d5_pe5",
+ "lcd_d6_pe6",
+ "lcd_d7_pe7",
+ "lcd_d8_pf0",
+ "lcd_d9_pf1",
+ "lcd_d10_pf2",
+ "lcd_d11_pf3",
+ "lcd_d12_pf4",
+ "lcd_d13_pf5",
+ "lcd_d14_pf6",
+ "lcd_d15_pf7",
+ "lcd_de_pj1",
+ "lcd_hsync_pj3",
+ "lcd_vsync_pj4",
+ "lcd_d16_pm0",
+ "lcd_d17_pm1",
+ "lcd_d18_pm2",
+ "lcd_d19_pm3",
+ "lcd_d20_pm4",
+ "lcd_d21_pm5",
+ "lcd_d22_pm6",
+ "lcd_d23_pm7",
+ "lcd_cs0_n_pn4",
+ "lcd_sdout_pn5",
+ "lcd_dc0_pn6",
+ "lcd_cs1_n_pw0",
+ "lcd_sdin_pz2",
+ "lcd_sck_pz4";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart3_rts_n_pc0 {
+ nvidia,pins = "uart3_rts_n_pc0",
+ "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_txd_pc2 {
+ nvidia,pins = "uart2_txd_pc2",
+ "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_rxd_pc3 {
+ nvidia,pins = "uart2_rxd_pc3",
+ "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gen1_i2c_scl_pc4 {
+ nvidia,pins = "gen1_i2c_scl_pc4",
+ "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs4_n_pk2",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad12_ph4 {
+ nvidia,pins = "gmi_ad12_ph4",
+ "gmi_cs0_n_pj0",
+ "gmi_cs1_n_pj2",
+ "gmi_cs2_n_pk3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat5_pd0 {
+ nvidia,pins = "sdmmc3_dat5_pd0";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad0_pg0 {
+ nvidia,pins = "gmi_ad0_pg0",
+ "gmi_ad1_pg1",
+ "gmi_ad14_ph6",
+ "pu1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad2_pg2 {
+ nvidia,pins = "gmi_ad2_pg2",
+ "gmi_ad3_pg3",
+ "gmi_ad6_pg6",
+ "gmi_ad7_pg7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad4_pg4 {
+ nvidia,pins = "gmi_ad4_pg4",
+ "gmi_ad5_pg5";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_ad8_ph0 {
+ nvidia,pins = "gmi_ad8_ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad9_ph1 {
+ nvidia,pins = "gmi_ad9_ph1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad10_ph2 {
+ nvidia,pins = "gmi_ad10_ph2";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad11_ph3 {
+ nvidia,pins = "gmi_ad11_ph3";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad13_ph5 {
+ nvidia,pins = "gmi_ad13_ph5",
+ "gmi_wr_n_pi0",
+ "gmi_oe_n_pi1",
+ "gmi_adv_n_pk0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_ad15_ph7 {
+ nvidia,pins = "gmi_ad15_ph7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_dqs_pi2 {
+ nvidia,pins = "gmi_dqs_pi2",
+ "pu2",
+ "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_rst_n_pi4 {
+ nvidia,pins = "gmi_rst_n_pi4";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_iordy_pi5 {
+ nvidia,pins = "gmi_iordy_pi5";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs7_n_pi6 {
+ nvidia,pins = "gmi_cs7_n_pi6",
+ "gmi_clk_pk1";
+ nvidia,function = "nand";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_a16_pj7 {
+ nvidia,pins = "gmi_a16_pj7",
+ "gmi_a19_pk7";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_out_pk5 {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_in_pk6 {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap1_fs_pn0 {
+ nvidia,pins = "dap1_fs_pn0",
+ "dap1_din_pn1",
+ "dap1_dout_pn2",
+ "dap1_sclk_pn3";
+ nvidia,function = "i2s0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ hdmi_int_pn7 {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "hdmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_data7_po0 {
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data3_po4 {
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_fs_pp0 {
+ nvidia,pins = "dap3_fs_pp0";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_fs_pp4 {
+ nvidia,pins = "dap4_fs_pp4",
+ "dap4_din_pp5",
+ "dap4_dout_pp6",
+ "dap4_sclk_pp7";
+ nvidia,function = "i2s3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0",
+ "kb_col1_pq1",
+ "kb_row1_pr1";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col2_pq2 {
+ nvidia,pins = "kb_col2_pq2",
+ "kb_col3_pq3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_col4_pq4 {
+ nvidia,pins = "kb_col4_pq4",
+ "kb_col5_pq5",
+ "kb_col7_pq7",
+ "kb_row2_pr2",
+ "kb_row4_pr4",
+ "kb_row5_pr5",
+ "kb_row14_ps6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row6_pr6 {
+ nvidia,pins = "kb_row6_pr6",
+ "kb_row8_ps0",
+ "kb_row9_ps1",
+ "kb_row10_ps2";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row11_ps3 {
+ nvidia,pins = "kb_row11_ps3",
+ "kb_row12_ps4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5",
+ "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_cmd_pt7 {
+ nvidia,pins = "sdmmc4_cmd_pt7",
+ "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu0 {
+ nvidia,pins = "pu0",
+ "pu6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ jtag_rtck_pu7 {
+ nvidia,pins = "jtag_rtck_pu7";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pv0 {
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4",
+ "ddc_sda_pv5";
+ nvidia,function = "i2c4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ crt_hsync_pv6 {
+ nvidia,pins = "crt_hsync_pv6",
+ "crt_vsync_pv7";
+ nvidia,function = "crt";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_cs1_n_pw2 {
+ nvidia,pins = "spi2_cs1_n_pw2",
+ "spi2_miso_px1",
+ "spi2_sck_px2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk1_out_pw4 {
+ nvidia,pins = "clk1_out_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_out_pw5 {
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "extperiph2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_cs0_n_px3 {
+ nvidia,pins = "spi2_cs0_n_px3";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_mosi_px4 {
+ nvidia,pins = "spi1_mosi_px4",
+ "spi1_cs0_n_px6";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0",
+ "ulpi_dir_py1";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc1_dat3_py4 {
+ nvidia,pins = "sdmmc1_dat3_py4",
+ "sdmmc1_dat2_py5",
+ "sdmmc1_dat1_py6",
+ "sdmmc1_dat0_py7",
+ "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_wr_n_pz3 {
+ nvidia,pins = "lcd_wr_n_pz3";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sys_clk_req_pz5 {
+ nvidia,pins = "sys_clk_req_pz5";
+ nvidia,function = "sysclk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pwr_i2c_scl_pz6 {
+ nvidia,pins = "pwr_i2c_scl_pz6",
+ "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ pbb0 {
+ nvidia,pins = "pbb0",
+ "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_i2c_scl_pbb1 {
+ nvidia,pins = "cam_i2c_scl_pbb1",
+ "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ pbb3 {
+ nvidia,pins = "pbb3";
+ nvidia,function = "vgp3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pbb7 {
+ nvidia,pins = "pbb7",
+ "pcc2";
+ nvidia,function = "i2s4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ cam_mclk_pcc0 {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_rst_n_pcc3 {
+ nvidia,pins = "sdmmc4_rst_n_pcc3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_req_pcc5 {
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_l2_rst_n_pcc6 {
+ nvidia,pins = "pex_l2_rst_n_pcc6",
+ "pex_l2_clkreq_n_pcc7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pex_wake_n_pdd3 {
+ nvidia,pins = "pex_wake_n_pdd3",
+ "pex_l2_prsnt_n_pdd7";
+ nvidia,function = "pcie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk3_out_pee0 {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk1_req_pee2 {
+ nvidia,pins = "clk1_req_pee2";
+ nvidia,function = "dap";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ hdmi_cec_pee3 {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+ owr {
+ nvidia,pins = "owr";
+ nvidia,function = "owr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ drive_dap1 {
+ nvidia,pins = "drive_dap1",
+ "drive_dap2",
+ "drive_dbg",
+ "drive_at5",
+ "drive_gme",
+ "drive_ddc",
+ "drive_ao1",
+ "drive_uart3";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,pull-up-strength = <31>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1",
+ "drive_sdio3";
+ nvidia,high-speed-mode = <0>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <46>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
+ };
+ drive_gma {
+ nvidia,pins = "drive_gma",
+ "drive_gmb",
+ "drive_gmc",
+ "drive_gmd";
+ nvidia,pull-down-strength = <9>;
+ nvidia,pull-up-strength = <9>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ };
+ };
+
+ uartb: serial@70006040 {
+ compatible = "nvidia,tegra30-hsuart";
+ /* GPS BCM4751 */
+ };
+
+ uartc: serial@70006200 {
+ compatible = "nvidia,tegra30-hsuart";
+ status = "okay";
+
+ nvidia,adjust-baud-rates = <0 9600 100>,
+ <9600 115200 200>,
+ <1000000 4000000 136>;
+
+ /* Azurewave AW-NH665 BCM4330B1 */
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+
+ max-speed = <4000000>;
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "txco";
+
+ vbat-supply = <&vdd_3v3_sys>;
+ vddio-supply = <&vdd_1v8>;
+
+ device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ i2c@7000c400 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@10 {
+ compatible ="elan,ektf3624";
+ reg = <0x10>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
+
+ vcc33-supply = <&vcc_3v3_ts>;
+ vccio-supply = <&vcc_3v3_ts>;
+
+ touchscreen-size-x = <2112>;
+ touchscreen-size-y = <1280>;
+ touchscreen-swapped-x-y;
+ touchscreen-inverted-x;
+ };
+ };
+
+ i2c@7000c500 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ compass@e {
+ compatible = "asahi-kasei,ak8974";
+ reg = <0x0e>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(W, 0) IRQ_TYPE_EDGE_RISING>;
+
+ avdd-supply = <&vdd_3v3_sys>;
+ dvdd-supply = <&vdd_1v8>;
+
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
+ };
+
+ light-sensor@1c {
+ compatible = "dynaimage,al3010";
+ reg = <0x1c>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
+
+ vdd-supply = <&vdd_3v3_sys>;
+ };
+
+ accelerometer@68 {
+ compatible = "invensense,mpu6050";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&vdd_3v3_sys>;
+ vddio-supply = <&vdd_1v8>;
+
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
+ };
+ };
+
+ i2c@7000d000 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ rt5640: audio-codec@1c {
+ compatible = "realtek,rt5640";
+ reg = <0x1c>;
+
+ realtek,dmic1-data-pin = <1>;
+ };
+
+ nct72: temperature-sensor@4c {
+ compatible = "onnn,nct1008";
+ reg = <0x4c>;
+ vcc-supply = <&vdd_3v3_sys>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ fuel-gauge@55 {
+ compatible = "ti,bq27541";
+ reg = <0x55>;
+ power-supplies = <&power_supply>;
+ monitored-battery = <&battery_cell>;
+ };
+
+ power_supply: charger@6a {
+ compatible = "summit,smb347";
+ reg = <0x6a>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>;
+
+ summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>;
+ summit,enable-usb-charging;
+
+ monitored-battery = <&battery_cell>;
+ };
+ };
+
+ pmc@7000e400 {
+ status = "okay";
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <1>;
+ nvidia,cpu-pwr-good-time = <2000>;
+ nvidia,cpu-pwr-off-time = <200>;
+ nvidia,core-pwr-good-time = <3845 3845>;
+ nvidia,core-pwr-off-time = <0>;
+ nvidia,core-power-req-active-high;
+ nvidia,sys-clock-req-active-high;
+ };
+
+ ahub@70080000 {
+ i2s@70080400 {
+ status = "okay";
+ };
+ };
+
+ brcm_wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+
+ clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
+ clock-names = "ext_clock";
+
+ reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <300>;
+ power-off-delay-us = <300>;
+ };
+
+ sdmmc3: mmc@78000400 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
+ assigned-clock-rates = <50000000>;
+
+ max-frequency = <50000000>;
+ keep-power-in-suspend;
+ bus-width = <4>;
+ non-removable;
+
+ mmc-pwrseq = <&brcm_wifi_pwrseq>;
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_1v8>;
+
+ /* Azurewave AW-NH665 BCM4330 */
+ wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host-wake";
+ };
+ };
+
+ sdmmc4: mmc@78000600 {
+ status = "okay";
+ bus-width = <8>;
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_1v8>;
+ non-removable;
+ };
+
+ usb@7d000000 {
+ compatible = "nvidia,tegra30-udc";
+ status = "okay";
+ dr_mode = "peripheral";
+ };
+
+ usb-phy@7d000000 {
+ status = "okay";
+ dr_mode = "peripheral";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ power-supply = <&vdd_5v0_sys>;
+ pwms = <&pwm 0 50000>;
+
+ brightness-levels = <1 255>;
+ num-interpolated-steps = <254>;
+ default-brightness-level = <15>;
+ };
+
+ battery_cell: battery-cell {
+ compatible = "simple-battery";
+ constant-charge-current-max-microamp = <1800000>;
+ operating-range-celsius = <0 45>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic-oscillator";
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu@1 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@2 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@3 {
+ cpu-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ display-panel {
+ compatible = "hydis,hv070wx2-1e0", "chunghwa,claa070wp03xg",
+ "panel-lvds";
+
+ power-supply = <&vdd_pnl>;
+ backlight = <&backlight>;
+
+ width-mm = <94>;
+ height-mm = <150>;
+ rotation = <180>;
+
+ data-mapping = "jeida-24";
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&lvds_encoder_output>;
+ };
+ };
+ };
+
+ firmware {
+ trusted-foundations {
+ compatible = "tlm,trusted-foundations";
+ tlm,version-major = <0x0>;
+ tlm,version-minor = <0x0>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ hall-sensor {
+ label = "Lid";
+ gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ debounce-interval = <500>;
+ wakeup-event-action = <EV_ACT_DEASSERTED>;
+ wakeup-source;
+ };
+
+ power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <10>;
+ wakeup-event-action = <EV_ACT_ASSERTED>;
+ wakeup-source;
+ };
+ };
+
+ lvds-encoder {
+ compatible = "ti,sn75lvds83", "lvds-encoder";
+
+ powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_encoder_input: endpoint {
+ remote-endpoint = <&lcd_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_encoder_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+ };
+
+ vdd_5v0_sys: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_3v3_sys: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ vdd_pnl: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <300000>;
+ gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+
+ vcc_3v3_ts: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "ldo_s-1167_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v0_sys>;
+ };
+
+ sound {
+ compatible = "nvidia,tegra-audio-rt5640-grouper",
+ "nvidia,tegra-audio-rt5640";
+ nvidia,model = "ASUS Google Nexus 7 ALC5642";
+
+ nvidia,audio-routing =
+ "Headphones", "HPOR",
+ "Headphones", "HPOL",
+ "Speakers", "SPORP",
+ "Speakers", "SPORN",
+ "Speakers", "SPOLP",
+ "Speakers", "SPOLN",
+ "DMIC1", "Mic Jack";
+
+ nvidia,i2s-controller = <&tegra_i2s1>;
+ nvidia,audio-codec = <&rt5640>;
+
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+
+ clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+ <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+ clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
+ };
+
+ thermal-zones {
+ nct72-local {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <0>; /* milliseconds */
+
+ thermal-sensors = <&nct72 0>;
+ };
+
+ nct72-remote {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&nct72 1>;
+
+ trips {
+ trip0: cpu-alert0 {
+ /* start throttling at 50C */
+ temperature = <50000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ trip1: cpu-crit {
+ /* shut down at 60C */
+ temperature = <60000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
new file mode 100644
index 0000000..b25b3fa
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/max77620.h>
+
+/ {
+ i2c@7000d000 {
+ pmic: pmic@3c {
+ compatible = "maxim,max77663";
+ reg = <0x3c>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ system-power-controller;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&max77620_default>;
+
+ max77620_default: pinmux {
+ gpio4 {
+ pins = "gpio4";
+ function = "32k-out1";
+ };
+ };
+
+ cpu-pwr-req {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+
+ fps {
+ fps0 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+ };
+
+ fps1 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
+ };
+
+ fps2 {
+ maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+ };
+ };
+
+ regulators {
+ in-sd0-supply = <&vdd_5v0_sys>;
+ in-sd1-supply = <&vdd_5v0_sys>;
+ in-sd2-supply = <&vdd_5v0_sys>;
+ in-sd3-supply = <&vdd_5v0_sys>;
+ in-sd4-supply = <&vdd_5v0_sys>;
+
+ in-ldo0-1-supply = <&vdd_1v35>;
+ in-ldo2-supply = <&vdd_3v3_sys>;
+ in-ldo3-5-supply = <&vdd_3v3_sys>;
+ in-ldo4-6-supply = <&vdd_5v0_sys>;
+ in-ldo7-8-supply = <&vdd_1v35>;
+
+ vdd_cpu: sd0 {
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-coupled-with = <&vdd_core>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ nvidia,tegra-cpu-regulator;
+ };
+
+ vdd_core: sd1 {
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-coupled-with = <&vdd_cpu>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ nvidia,tegra-core-regulator;
+ };
+
+ vdd_1v8: sd2 {
+ regulator-name = "vdd_gen1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_1v35: sd3 {
+ regulator-name = "vdd_ddr3l_1v35";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo0 {
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo2 {
+ regulator-name = "vdd_ddr_rx";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcore_emmc: ldo3 {
+ regulator-name = "vcore_emmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-always-on;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo5 {
+ regulator-name = "vdd_camera";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo6 {
+ regulator-name = "vddio_sdmmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo7 {
+ regulator-name = "avdd_dsi_csi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo8 {
+ regulator-name = "avdd_pll";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+ };
+
+ vdd_3v3_sys: regulator@1 {
+ gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&vdd_3v3_sys>;
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi
new file mode 100644
index 0000000..bc0f6f2
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi
@@ -0,0 +1,1565 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ memory-controller@7000f000 {
+ emc-timings-0 {
+ nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = <
+ 0x00020001 /* MC_EMEM_ARB_CFG */
+ 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
+ 0x74830303 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = <
+ 0x00010001 /* MC_EMEM_ARB_CFG */
+ 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
+ 0x73430303 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = <
+ 0x00000001 /* MC_EMEM_ARB_CFG */
+ 0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
+ 0x72830504 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = <
+ 0x00000003 /* MC_EMEM_ARB_CFG */
+ 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
+ 0x72440a06 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emem-configuration = <
+ 0x00000005 /* MC_EMEM_ARB_CFG */
+ 0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000b0608 /* MC_EMEM_ARB_DA_COVERS */
+ 0x70850f09 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emem-configuration = <
+ 0x0000000a /* MC_EMEM_ARB_CFG */
+ 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000010 /* MC_EMEM_ARB_TIMING_RC */
+ 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
+ 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+ };
+
+ emc-timings-1 {
+ nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emem-configuration = <
+ 0x00020001 /* MC_EMEM_ARB_CFG */
+ 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
+ 0x74830303 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emem-configuration = <
+ 0x00010001 /* MC_EMEM_ARB_CFG */
+ 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
+ 0x73430303 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emem-configuration = <
+ 0x00000001 /* MC_EMEM_ARB_CFG */
+ 0xc0000030 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
+ 0x72830504 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emem-configuration = <
+ 0x00000003 /* MC_EMEM_ARB_CFG */
+ 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000005 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06020102 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
+ 0x72440a06 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emem-configuration = <
+ 0x00000005 /* MC_EMEM_ARB_CFG */
+ 0xc000003d /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000007 /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x000b0608 /* MC_EMEM_ARB_DA_COVERS */
+ 0x70850f09 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emem-configuration = <
+ 0x0000000a /* MC_EMEM_ARB_CFG */
+ 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000010 /* MC_EMEM_ARB_TIMING_RC */
+ 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
+ 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
+ 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
+ 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
+ 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
+ >;
+ };
+ };
+ };
+
+ memory-controller@7000f400 {
+ emc-timings-0 {
+ nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x00000001 /* EMC_RC */
+ 0x00000004 /* EMC_RFC */
+ 0x00000000 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000002 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000b /* EMC_RDV */
+ 0x000000c0 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000005 /* EMC_TXSR */
+ 0x00000005 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000001 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x000000c7 /* EMC_TREFBW */
+ 0x00000006 /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00004288 /* EMC_FBIO_CFG5 */
+ 0x007800a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800211c /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x08000168 /* EMC_XM2QUSEPADCTRL */
+ 0x08000000 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00000000 /* EMC_ZCAL_INTERVAL */
+ 0x00000040 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff00 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x00000002 /* EMC_RC */
+ 0x00000008 /* EMC_RFC */
+ 0x00000001 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000002 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000b /* EMC_RDV */
+ 0x00000181 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000009 /* EMC_TXSR */
+ 0x00000009 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000002 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x0000018e /* EMC_TREFBW */
+ 0x00000006 /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00004288 /* EMC_FBIO_CFG5 */
+ 0x007800a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800211c /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x08000168 /* EMC_XM2QUSEPADCTRL */
+ 0x08000000 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00000000 /* EMC_ZCAL_INTERVAL */
+ 0x00000040 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff00 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x00000005 /* EMC_RC */
+ 0x00000010 /* EMC_RFC */
+ 0x00000003 /* EMC_RAS */
+ 0x00000001 /* EMC_RP */
+ 0x00000002 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000001 /* EMC_RD_RCD */
+ 0x00000001 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000b /* EMC_RDV */
+ 0x00000303 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000012 /* EMC_TXSR */
+ 0x00000012 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000004 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x0000031c /* EMC_TREFBW */
+ 0x00000006 /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00004288 /* EMC_FBIO_CFG5 */
+ 0x007800a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800211c /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x08000168 /* EMC_XM2QUSEPADCTRL */
+ 0x08000000 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00000000 /* EMC_ZCAL_INTERVAL */
+ 0x00000040 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff00 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x0000000a /* EMC_RC */
+ 0x00000020 /* EMC_RFC */
+ 0x00000007 /* EMC_RAS */
+ 0x00000002 /* EMC_RP */
+ 0x00000002 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000002 /* EMC_RD_RCD */
+ 0x00000002 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000b /* EMC_RDV */
+ 0x00000607 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000023 /* EMC_TXSR */
+ 0x00000023 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000007 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000638 /* EMC_TREFBW */
+ 0x00000006 /* EMC_QUSE_EXTRA */
+ 0x00000006 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00004288 /* EMC_FBIO_CFG5 */
+ 0x004400a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00080000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800211c /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x08000168 /* EMC_XM2QUSEPADCTRL */
+ 0x08000000 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00020000 /* EMC_ZCAL_INTERVAL */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff00 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-reset = <0x80000321>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = <
+ 0x0000000f /* EMC_RC */
+ 0x00000034 /* EMC_RFC */
+ 0x0000000a /* EMC_RAS */
+ 0x00000003 /* EMC_RP */
+ 0x00000003 /* EMC_R2W */
+ 0x00000008 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x00000009 /* EMC_W2P */
+ 0x00000003 /* EMC_RD_RCD */
+ 0x00000003 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000004 /* EMC_WDV */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000c /* EMC_RDV */
+ 0x000009e9 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001 /* EMC_PDEX2WR */
+ 0x00000008 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000e /* EMC_RW2PDEN */
+ 0x00000039 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x0000000a /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000a2a /* EMC_TREFBW */
+ 0x00000000 /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00007088 /* EMC_FBIO_CFG5 */
+ 0x002600a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800013d /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f508 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x080001e8 /* EMC_XM2QUSEPADCTRL */
+ 0x08000021 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00020000 /* EMC_ZCAL_INTERVAL */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x018b000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff89 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200018>;
+ nvidia,emc-mode-reset = <0x80000b71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x0000001f /* EMC_RC */
+ 0x00000069 /* EMC_RFC */
+ 0x00000017 /* EMC_RAS */
+ 0x00000007 /* EMC_RP */
+ 0x00000005 /* EMC_R2W */
+ 0x0000000c /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x00000011 /* EMC_W2P */
+ 0x00000007 /* EMC_RD_RCD */
+ 0x00000007 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000007 /* EMC_WDV */
+ 0x0000000b /* EMC_QUSE */
+ 0x00000009 /* EMC_QRST */
+ 0x0000000b /* EMC_QSAFE */
+ 0x00000011 /* EMC_RDV */
+ 0x00001412 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x0000000e /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x0000000c /* EMC_AR2PDEN */
+ 0x00000016 /* EMC_RW2PDEN */
+ 0x00000072 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000005 /* EMC_TCKE */
+ 0x00000015 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000006 /* EMC_TCLKSTABLE */
+ 0x00000007 /* EMC_TCLKSTOP */
+ 0x00001453 /* EMC_TREFBW */
+ 0x0000000c /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00005088 /* EMC_FBIO_CFG5 */
+ 0xf00b0191 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00000008 /* EMC_DLL_XFORM_DQS0 */
+ 0x00000008 /* EMC_DLL_XFORM_DQS1 */
+ 0x00000008 /* EMC_DLL_XFORM_DQS2 */
+ 0x00000008 /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0600013d /* EMC_XM2DQSPADCTRL2 */
+ 0x22220000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f501 /* EMC_XM2COMPPADCTRL */
+ 0x07077404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x080001e8 /* EMC_XM2QUSEPADCTRL */
+ 0x0a000021 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00020000 /* EMC_ZCAL_INTERVAL */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x0156000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xf8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff49 /* EMC_CFG_RSV */
+ >;
+ };
+ };
+
+ emc-timings-1 {
+ nvidia,ram-code = <1>; /* Hynix H5TC2G83CFR */
+
+ timing-25500000 {
+ clock-frequency = <25500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x00000001 /* EMC_RC */
+ 0x00000004 /* EMC_RFC */
+ 0x00000000 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000002 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000b /* EMC_RDV */
+ 0x000000c0 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000005 /* EMC_TXSR */
+ 0x00000005 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000001 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x000000c7 /* EMC_TREFBW */
+ 0x00000006 /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00004288 /* EMC_FBIO_CFG5 */
+ 0x007800a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800211c /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x08000168 /* EMC_XM2QUSEPADCTRL */
+ 0x08000000 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00000000 /* EMC_ZCAL_INTERVAL */
+ 0x00000040 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff00 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-51000000 {
+ clock-frequency = <51000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x00000002 /* EMC_RC */
+ 0x00000008 /* EMC_RFC */
+ 0x00000001 /* EMC_RAS */
+ 0x00000000 /* EMC_RP */
+ 0x00000002 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000000 /* EMC_RD_RCD */
+ 0x00000000 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000b /* EMC_RDV */
+ 0x00000181 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000009 /* EMC_TXSR */
+ 0x00000009 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000002 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x0000018e /* EMC_TREFBW */
+ 0x00000006 /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00004288 /* EMC_FBIO_CFG5 */
+ 0x007800a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800211c /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x08000168 /* EMC_XM2QUSEPADCTRL */
+ 0x08000000 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00000000 /* EMC_ZCAL_INTERVAL */
+ 0x00000040 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff00 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-102000000 {
+ clock-frequency = <102000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x00000005 /* EMC_RC */
+ 0x00000010 /* EMC_RFC */
+ 0x00000003 /* EMC_RAS */
+ 0x00000001 /* EMC_RP */
+ 0x00000002 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000001 /* EMC_RD_RCD */
+ 0x00000001 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000b /* EMC_RDV */
+ 0x00000303 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000012 /* EMC_TXSR */
+ 0x00000012 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000004 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x0000031c /* EMC_TREFBW */
+ 0x00000006 /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00004288 /* EMC_FBIO_CFG5 */
+ 0x007800a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS3 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS4 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS5 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS6 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800211c /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x08000168 /* EMC_XM2QUSEPADCTRL */
+ 0x08000000 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00000000 /* EMC_ZCAL_INTERVAL */
+ 0x00000040 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff00 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-204000000 {
+ clock-frequency = <204000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100003>;
+ nvidia,emc-mode-2 = <0x80200008>;
+ nvidia,emc-mode-reset = <0x80001221>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-dyn-self-ref;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x0000000a /* EMC_RC */
+ 0x00000020 /* EMC_RFC */
+ 0x00000007 /* EMC_RAS */
+ 0x00000002 /* EMC_RP */
+ 0x00000002 /* EMC_R2W */
+ 0x0000000a /* EMC_W2R */
+ 0x00000005 /* EMC_R2P */
+ 0x0000000b /* EMC_W2P */
+ 0x00000002 /* EMC_RD_RCD */
+ 0x00000002 /* EMC_WR_RCD */
+ 0x00000003 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000005 /* EMC_WDV */
+ 0x00000005 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000b /* EMC_RDV */
+ 0x00000607 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x00000002 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000f /* EMC_RW2PDEN */
+ 0x00000023 /* EMC_TXSR */
+ 0x00000023 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x00000007 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000638 /* EMC_TREFBW */
+ 0x00000006 /* EMC_QUSE_EXTRA */
+ 0x00000006 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00004288 /* EMC_FBIO_CFG5 */
+ 0x004400a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00080000 /* EMC_DLL_XFORM_DQS0 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS1 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS2 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00080000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00080000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800211c /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f108 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x08000168 /* EMC_XM2QUSEPADCTRL */
+ 0x08000000 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00020000 /* EMC_ZCAL_INTERVAL */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x000c000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff00 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-reset = <0x80000321>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = <
+ 0x0000000f /* EMC_RC */
+ 0x00000034 /* EMC_RFC */
+ 0x0000000a /* EMC_RAS */
+ 0x00000003 /* EMC_RP */
+ 0x00000003 /* EMC_R2W */
+ 0x00000008 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x00000009 /* EMC_W2P */
+ 0x00000003 /* EMC_RD_RCD */
+ 0x00000003 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000004 /* EMC_WDV */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000c /* EMC_RDV */
+ 0x000009e9 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001 /* EMC_PDEX2WR */
+ 0x00000008 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000e /* EMC_RW2PDEN */
+ 0x00000039 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x0000000a /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000a2a /* EMC_TREFBW */
+ 0x00000000 /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00007088 /* EMC_FBIO_CFG5 */
+ 0x002600a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0600013d /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f508 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x080001e8 /* EMC_XM2QUSEPADCTRL */
+ 0x08000021 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00020000 /* EMC_ZCAL_INTERVAL */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x018b000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xf8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff89 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200018>;
+ nvidia,emc-mode-reset = <0x80000b71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x00000020 /* EMC_RC */
+ 0x0000006a /* EMC_RFC */
+ 0x00000017 /* EMC_RAS */
+ 0x00000007 /* EMC_RP */
+ 0x00000005 /* EMC_R2W */
+ 0x0000000c /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x00000011 /* EMC_W2P */
+ 0x00000007 /* EMC_RD_RCD */
+ 0x00000007 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000007 /* EMC_WDV */
+ 0x0000000a /* EMC_QUSE */
+ 0x00000009 /* EMC_QRST */
+ 0x0000000b /* EMC_QSAFE */
+ 0x00000011 /* EMC_RDV */
+ 0x00001412 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x0000000e /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x0000000c /* EMC_AR2PDEN */
+ 0x00000016 /* EMC_RW2PDEN */
+ 0x00000072 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000005 /* EMC_TCKE */
+ 0x00000015 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000006 /* EMC_TCLKSTABLE */
+ 0x00000007 /* EMC_TCLKSTOP */
+ 0x00001453 /* EMC_TREFBW */
+ 0x0000000b /* EMC_QUSE_EXTRA */
+ 0x00000006 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00005088 /* EMC_FBIO_CFG5 */
+ 0xf00b0191 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0000000a /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0400013d /* EMC_XM2DQSPADCTRL2 */
+ 0x22220000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f501 /* EMC_XM2COMPPADCTRL */
+ 0x07077404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x080001e8 /* EMC_XM2QUSEPADCTRL */
+ 0x0a000021 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00020000 /* EMC_ZCAL_INTERVAL */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x0155000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff49 /* EMC_CFG_RSV */
+ >;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
new file mode 100644
index 0000000..215e497
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ i2c@7000d000 {
+ pmic: pmic@2d {
+ compatible = "ti,tps65911";
+ reg = <0x2d>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
+ ti,system-power-controller;
+ ti,sleep-keep-ck32k;
+ ti,sleep-enable;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ vcc1-supply = <&vdd_5v0_sys>;
+ vcc2-supply = <&vdd_5v0_sys>;
+ vcc3-supply = <&vdd_1v8>;
+ vcc4-supply = <&vdd_5v0_sys>;
+ vcc5-supply = <&vdd_5v0_sys>;
+ vcc6-supply = <&vdd2_reg>;
+ vcc7-supply = <&vdd_5v0_sys>;
+ vccio-supply = <&vdd_5v0_sys>;
+
+ regulators {
+ vdd1 {
+ regulator-name = "vddio_ddr_1v2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,regulator-ext-sleep-control = <8>;
+ };
+
+ vdd2_reg: vdd2 {
+ regulator-name = "vdd2_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_cpu: vddctrl {
+ regulator-name = "vdd_cpu,vdd_sys";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-coupled-with = <&vdd_core>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+ regulator-always-on;
+ ti,regulator-ext-sleep-control = <1>;
+
+ nvidia,tegra-cpu-regulator;
+ };
+
+ vdd_1v8: vio {
+ regulator-name = "vdd_1v8_gen";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcore_emmc: ldo1 {
+ regulator-name = "vdd_pexa,vdd_pexb";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo2 {
+ regulator-name = "vdd_sata,avdd_plle";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ /* LDO3 is not connected to anything */
+
+ ldo4 {
+ regulator-name = "vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo5 {
+ regulator-name = "vddio_sdmmc,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo6 {
+ regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo7 {
+ regulator-name = "vdd_pllm,x,u,a_p_c_s";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,regulator-ext-sleep-control = <8>;
+ };
+
+ ldo8 {
+ regulator-name = "vdd_ddr_hs";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ ti,regulator-ext-sleep-control = <8>;
+ };
+ };
+ };
+
+ vdd_core: core-regulator@60 {
+ compatible = "ti,tps62361";
+ reg = <0x60>;
+
+ regulator-name = "tps62361-vout";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-coupled-with = <&vdd_cpu>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ti,enable-vout-discharge;
+ ti,vsel0-state-high;
+ ti,vsel1-state-high;
+
+ nvidia,tegra-core-regulator;
+ };
+ };
+
+ vdd_3v3_sys: regulator@1 {
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi
new file mode 100644
index 0000000..a044dbd
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "tegra30-asus-nexus7-grouper-common.dtsi"
+#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
+
+/ {
+ compatible = "asus,grouper", "nvidia,tegra30";
+
+ display-panel {
+ panel-timing {
+ clock-frequency = <68000000>;
+ hactive = <800>;
+ vactive = <1280>;
+ hfront-porch = <24>;
+ hback-porch = <32>;
+ hsync-len = <24>;
+ vsync-len = <1>;
+ vfront-porch = <5>;
+ vback-porch = <32>;
+ };
+ };
+
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_dc1_pd2 {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_cs2_n_pw3 {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_sck_px5 {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_miso_px7 {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row15_ps7 {
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row3_pr3 {
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row13_ps5 {
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs4_n_pk2",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gmi_cs6_n_pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+
+ i2c@7000c500 {
+ nfc@28 {
+ compatible = "nxp,pn544-i2c";
+ reg = <0x28>;
+ clock-frequency = <100000>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts
new file mode 100644
index 0000000..f1c63fe
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi"
+#include "tegra30-asus-nexus7-tilapia.dtsi"
+
+/ {
+ model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565";
+};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi
new file mode 100644
index 0000000..9169de3
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
+
+/ {
+ /*
+ * Tilapia's memory timings are pretty much the same as the Grouper's
+ * ones. There are few minor tunings made for a higher clock rates,
+ * these differentiating timings are overridden here for Tilapia.
+ */
+
+ memory-controller@7000f400 {
+ emc-timings-0 {
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200018>;
+ nvidia,emc-mode-reset = <0x80000b71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x0000001f /* EMC_RC */
+ 0x00000069 /* EMC_RFC */
+ 0x00000017 /* EMC_RAS */
+ 0x00000007 /* EMC_RP */
+ 0x00000005 /* EMC_R2W */
+ 0x0000000c /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x00000011 /* EMC_W2P */
+ 0x00000007 /* EMC_RD_RCD */
+ 0x00000007 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000007 /* EMC_WDV */
+ 0x0000000b /* EMC_QUSE */
+ 0x00000009 /* EMC_QRST */
+ 0x0000000b /* EMC_QSAFE */
+ 0x00000011 /* EMC_RDV */
+ 0x00001412 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x0000000e /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x0000000c /* EMC_AR2PDEN */
+ 0x00000016 /* EMC_RW2PDEN */
+ 0x00000072 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000005 /* EMC_TCKE */
+ 0x00000015 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000006 /* EMC_TCLKSTABLE */
+ 0x00000007 /* EMC_TCLKSTOP */
+ 0x00001453 /* EMC_TREFBW */
+ 0x0000000c /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00005088 /* EMC_FBIO_CFG5 */
+ 0xf00b0191 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00000008 /* EMC_DLL_XFORM_DQS0 */
+ 0x00000008 /* EMC_DLL_XFORM_DQS1 */
+ 0x00000008 /* EMC_DLL_XFORM_DQS2 */
+ 0x00000008 /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000c /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800013d /* EMC_XM2DQSPADCTRL2 */
+ 0x22220000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f501 /* EMC_XM2COMPPADCTRL */
+ 0x07077404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x080001e8 /* EMC_XM2QUSEPADCTRL */
+ 0x08000021 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00020000 /* EMC_ZCAL_INTERVAL */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x0156000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff49 /* EMC_CFG_RSV */
+ >;
+ };
+ };
+
+ emc-timings-1 {
+ timing-333500000 {
+ clock-frequency = <333500000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200000>;
+ nvidia,emc-mode-reset = <0x80000321>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+
+ nvidia,emc-configuration = <
+ 0x0000000f /* EMC_RC */
+ 0x00000034 /* EMC_RFC */
+ 0x0000000a /* EMC_RAS */
+ 0x00000003 /* EMC_RP */
+ 0x00000003 /* EMC_R2W */
+ 0x00000008 /* EMC_W2R */
+ 0x00000002 /* EMC_R2P */
+ 0x00000009 /* EMC_W2P */
+ 0x00000003 /* EMC_RD_RCD */
+ 0x00000003 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000004 /* EMC_WDV */
+ 0x00000006 /* EMC_QUSE */
+ 0x00000004 /* EMC_QRST */
+ 0x0000000a /* EMC_QSAFE */
+ 0x0000000c /* EMC_RDV */
+ 0x000009e9 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001 /* EMC_PDEX2WR */
+ 0x00000008 /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x00000007 /* EMC_AR2PDEN */
+ 0x0000000e /* EMC_RW2PDEN */
+ 0x00000039 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000004 /* EMC_TCKE */
+ 0x0000000a /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000004 /* EMC_TCLKSTABLE */
+ 0x00000005 /* EMC_TCLKSTOP */
+ 0x00000a2a /* EMC_TREFBW */
+ 0x00000000 /* EMC_QUSE_EXTRA */
+ 0x00000004 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00007088 /* EMC_FBIO_CFG5 */
+ 0x002600a4 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS0 */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS1 */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS2 */
+ 0x0003c000 /* EMC_DLL_XFORM_DQS3 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS4 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS5 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS6 */
+ 0x00014000 /* EMC_DLL_XFORM_DQS7 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ0 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ1 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ2 */
+ 0x00048000 /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800013d /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f508 /* EMC_XM2COMPPADCTRL */
+ 0x05057404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x080001e8 /* EMC_XM2QUSEPADCTRL */
+ 0x08000021 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00020000 /* EMC_ZCAL_INTERVAL */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x018b000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff89 /* EMC_CFG_RSV */
+ >;
+ };
+
+ timing-667000000 {
+ clock-frequency = <667000000>;
+
+ nvidia,emc-auto-cal-interval = <0x001fffff>;
+ nvidia,emc-mode-1 = <0x80100002>;
+ nvidia,emc-mode-2 = <0x80200018>;
+ nvidia,emc-mode-reset = <0x80000b71>;
+ nvidia,emc-zcal-cnt-long = <0x00000040>;
+ nvidia,emc-cfg-periodic-qrst;
+
+ nvidia,emc-configuration = <
+ 0x00000020 /* EMC_RC */
+ 0x0000006a /* EMC_RFC */
+ 0x00000017 /* EMC_RAS */
+ 0x00000007 /* EMC_RP */
+ 0x00000005 /* EMC_R2W */
+ 0x0000000c /* EMC_W2R */
+ 0x00000003 /* EMC_R2P */
+ 0x00000011 /* EMC_W2P */
+ 0x00000007 /* EMC_RD_RCD */
+ 0x00000007 /* EMC_WR_RCD */
+ 0x00000002 /* EMC_RRD */
+ 0x00000001 /* EMC_REXT */
+ 0x00000000 /* EMC_WEXT */
+ 0x00000007 /* EMC_WDV */
+ 0x0000000a /* EMC_QUSE */
+ 0x00000009 /* EMC_QRST */
+ 0x0000000b /* EMC_QSAFE */
+ 0x00000011 /* EMC_RDV */
+ 0x00001412 /* EMC_REFRESH */
+ 0x00000000 /* EMC_BURST_REFRESH_NUM */
+ 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002 /* EMC_PDEX2WR */
+ 0x0000000e /* EMC_PDEX2RD */
+ 0x00000001 /* EMC_PCHG2PDEN */
+ 0x00000000 /* EMC_ACT2PDEN */
+ 0x0000000c /* EMC_AR2PDEN */
+ 0x00000016 /* EMC_RW2PDEN */
+ 0x00000072 /* EMC_TXSR */
+ 0x00000200 /* EMC_TXSRDLL */
+ 0x00000005 /* EMC_TCKE */
+ 0x00000015 /* EMC_TFAW */
+ 0x00000000 /* EMC_TRPAB */
+ 0x00000006 /* EMC_TCLKSTABLE */
+ 0x00000007 /* EMC_TCLKSTOP */
+ 0x00001453 /* EMC_TREFBW */
+ 0x0000000b /* EMC_QUSE_EXTRA */
+ 0x00000006 /* EMC_FBIO_CFG6 */
+ 0x00000000 /* EMC_ODT_WRITE */
+ 0x00000000 /* EMC_ODT_READ */
+ 0x00005088 /* EMC_FBIO_CFG5 */
+ 0xf00b0191 /* EMC_CFG_DIG_DLL */
+ 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00000008 /* EMC_DLL_XFORM_DQS0 */
+ 0x00000008 /* EMC_DLL_XFORM_DQS1 */
+ 0x00000008 /* EMC_DLL_XFORM_DQS2 */
+ 0x00000008 /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a /* EMC_DLL_XFORM_DQS7 */
+ 0x00018000 /* EMC_DLL_XFORM_QUSE0 */
+ 0x00018000 /* EMC_DLL_XFORM_QUSE1 */
+ 0x00018000 /* EMC_DLL_XFORM_QUSE2 */
+ 0x00018000 /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000a /* EMC_DLL_XFORM_DQ3 */
+ 0x000002a0 /* EMC_XM2CMDPADCTRL */
+ 0x0800013d /* EMC_XM2DQSPADCTRL2 */
+ 0x22220000 /* EMC_XM2DQPADCTRL2 */
+ 0x77fff884 /* EMC_XM2CLKPADCTRL */
+ 0x01f1f501 /* EMC_XM2COMPPADCTRL */
+ 0x07077404 /* EMC_XM2VTTGENPADCTRL */
+ 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
+ 0x080001e8 /* EMC_XM2QUSEPADCTRL */
+ 0x0c000021 /* EMC_XM2DQSPADCTRL3 */
+ 0x00000802 /* EMC_CTT_TERM_CTRL */
+ 0x00020000 /* EMC_ZCAL_INTERVAL */
+ 0x00000100 /* EMC_ZCAL_WAIT_CNT */
+ 0x0155000c /* EMC_MRS_WAIT_CNT */
+ 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
+ 0x00000000 /* EMC_CTT */
+ 0x00000000 /* EMC_CTT_DURATION */
+ 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
+ 0xe8000000 /* EMC_FBIO_SPARE */
+ 0xff00ff49 /* EMC_CFG_RSV */
+ >;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
new file mode 100644
index 0000000..e3da89f
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "tegra30-asus-nexus7-grouper-common.dtsi"
+#include "tegra30-asus-nexus7-tilapia-memory-timings.dtsi"
+
+/ {
+ compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30";
+
+ display-panel {
+ enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>;
+
+ panel-timing {
+ clock-frequency = <81750000>;
+ hactive = <800>;
+ vactive = <1280>;
+ hfront-porch = <64>;
+ hback-porch = <128>;
+ hsync-len = <64>;
+ vsync-len = <1>;
+ vfront-porch = <5>;
+ vback-porch = <2>;
+ };
+ };
+
+ gpio@6000d000 {
+ init-mode-3g {
+ gpio-hog;
+ gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(U, 5) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(U, 3) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(N, 1) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(N, 2) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(N, 0) GPIO_ACTIVE_HIGH>,
+ <TEGRA_GPIO(N, 3) GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+
+ pinmux@70000868 {
+ state_default: pinmux {
+ lcd_dc1_pd2 {
+ nvidia,pins = "lcd_dc1_pd2";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ lcd_pwr2_pc6 {
+ nvidia,pins = "lcd_pwr2_pc6";
+ nvidia,function = "displaya";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_cs2_n_pw3 {
+ nvidia,pins = "spi2_cs2_n_pw3";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_din_pp1 {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi1_sck_px5 {
+ nvidia,pins = "spi1_sck_px5";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pu5 {
+ nvidia,pins = "pu5";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ spi1_miso_px7 {
+ nvidia,pins = "spi1_miso_px7";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spi2_mosi_px0 {
+ nvidia,pins = "spi2_mosi_px0";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_req_pee1 {
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "dev3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_stp_py3 {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row7_pr7 {
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row15_ps7 {
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_sclk_pp3 {
+ nvidia,pins = "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row3_pr3 {
+ nvidia,pins = "kb_row3_pr3",
+ "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ kb_row13_ps5 {
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_wp_n_pc7 {
+ nvidia,pins = "gmi_wp_n_pc7",
+ "gmi_wait_pi7",
+ "gmi_cs4_n_pk2",
+ "gmi_cs3_n_pk4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gmi_cs6_n_pi3 {
+ nvidia,pins = "gmi_cs6_n_pi3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+
+ i2c@7000c500 {
+ proximity-sensor@28 {
+ compatible = "microchip,cap1106";
+ reg = <0x28>;
+
+ /*
+ * Binding doesn't support specifying linux,input-type
+ * and this results in unwanted key-presses handled by
+ * applications, hence keep it disabled for now.
+ */
+ status = "disabled";
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(R, 3) IRQ_TYPE_LEVEL_HIGH>;
+
+ linux,keycodes = <KEY_RESERVED>,
+ <KEY_RESERVED>,
+ <KEY_RESERVED>,
+ <KEY_RESERVED>,
+ <KEY_RESERVED>,
+ <SW_FRONT_PROXIMITY>;
+ };
+
+ nfc@2a {
+ compatible = "nxp,pn544-i2c";
+ reg = <0x2a>;
+
+ clock-frequency = <100000>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index a3b0f35..e0624b7 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -2,6 +2,8 @@
/dts-v1/;
#include "tegra30.dtsi"
+#include "tegra30-cpu-opp.dtsi"
+#include "tegra30-cpu-opp-microvolt.dtsi"
/ {
model = "NVIDIA Tegra30 Beaver evaluation board";
@@ -1806,9 +1808,14 @@
vddctrl_reg: vddctrl {
regulator-name = "vdd_cpu,vdd_sys";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-coupled-with = <&core_vdd_reg>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
regulator-always-on;
+
+ nvidia,tegra-cpu-regulator;
};
vio_reg: vio {
@@ -1868,17 +1875,22 @@
};
};
- tps62361@60 {
+ core_vdd_reg: tps62361@60 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
+ regulator-coupled-with = <&vddctrl_reg>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
+
+ nvidia,tegra-core-regulator;
};
};
@@ -1910,7 +1922,7 @@
};
};
- sdhci@78000000 {
+ mmc@78000000 {
status = "okay";
vqmmc-supply = <&ldo5_reg>;
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -1919,7 +1931,7 @@
bus-width = <4>;
};
- sdhci@78000600 {
+ mmc@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -1953,17 +1965,10 @@
status = "okay";
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
gpio-leds {
@@ -1979,118 +1984,103 @@
};
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_5v_in_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v_in";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- vdd_5v_in_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_5v_in";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ chargepump_5v_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "chargepump_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+ };
- chargepump_5v_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "chargepump_5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- enable-active-high;
- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
- };
+ ddr_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
- ddr_reg: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vdd_5v_in_reg>;
- };
+ vdd_5v_sata_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v_sata";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
- vdd_5v_sata_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "vdd_5v_sata";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
- vin-supply = <&vdd_5v_in_reg>;
- };
+ usb1_vbus_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
- usb1_vbus_reg: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "usb1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
- gpio-open-drain;
- vin-supply = <&vdd_5v_in_reg>;
- };
+ usb3_vbus_reg: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
- usb3_vbus_reg: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "usb3_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
- gpio-open-drain;
- vin-supply = <&vdd_5v_in_reg>;
- };
+ sys_3v3_reg: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "sys_3v3,vdd_3v3_alw";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vdd_5v_in_reg>;
+ };
- sys_3v3_reg: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "sys_3v3,vdd_3v3_alw";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vdd_5v_in_reg>;
- };
+ sys_3v3_pexs_reg: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "sys_3v3_pexs";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
- sys_3v3_pexs_reg: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "sys_3v3_pexs";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
- vin-supply = <&sys_3v3_reg>;
- };
-
- vdd_5v0_hdmi: regulator@8 {
- compatible = "regulator-fixed";
- reg = <8>;
- regulator-name = "+VDD_5V_HDMI";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- vin-supply = <&sys_3v3_reg>;
- };
+ vdd_5v0_hdmi: regulator@8 {
+ compatible = "regulator-fixed";
+ regulator-name = "+VDD_5V_HDMI";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&sys_3v3_reg>;
};
sound {
@@ -2111,7 +2101,35 @@
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA30_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@1 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@2 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu@3 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
};
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index a02ec50..4899e05 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -9,87 +9,75 @@
model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
- sdhci@78000400 {
+ mmc@78000400 {
status = "okay";
power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ ddr_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ };
- ddr_reg: regulator@100 {
- compatible = "regulator-fixed";
- reg = <100>;
- regulator-name = "vdd_ddr";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
- };
+ sys_3v3_reg: regulator@101 {
+ compatible = "regulator-fixed";
+ regulator-name = "sys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ };
- sys_3v3_reg: regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
- regulator-name = "sys_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
- };
+ usb1_vbus_reg: regulator@102 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
- usb1_vbus_reg: regulator@102 {
- compatible = "regulator-fixed";
- reg = <102>;
- regulator-name = "usb1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_reg>;
- };
+ usb3_vbus_reg: regulator@103 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
- usb3_vbus_reg: regulator@103 {
- compatible = "regulator-fixed";
- reg = <103>;
- regulator-name = "usb3_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_reg>;
- };
+ vdd_5v0_reg: regulator@104 {
+ compatible = "regulator-fixed";
+ regulator-name = "5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+ };
- vdd_5v0_reg: regulator@104 {
- compatible = "regulator-fixed";
- reg = <104>;
- regulator-name = "5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_bl_reg: regulator@105 {
- compatible = "regulator-fixed";
- reg = <105>;
- regulator-name = "vdd_bl";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
- };
+ vdd_bl_reg: regulator@105 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index 4dbd4af..c1c0ca6 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -2,6 +2,8 @@
/dts-v1/;
#include "tegra30-cardhu.dtsi"
+#include "tegra30-cpu-opp.dtsi"
+#include "tegra30-cpu-opp-microvolt.dtsi"
/* This dts file support the cardhu A04 and later versions of board */
@@ -9,98 +11,131 @@
model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
- sdhci@78000400 {
+ mmc@78000400 {
status = "okay";
power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
keep-power-in-suspend;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ ddr_reg: regulator@100 {
+ compatible = "regulator-fixed";
+ regulator-name = "ddr";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ };
- ddr_reg: regulator@100 {
- compatible = "regulator-fixed";
- regulator-name = "ddr";
- reg = <100>;
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ sys_3v3_reg: regulator@101 {
+ compatible = "regulator-fixed";
+ regulator-name = "sys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ usb1_vbus_reg: regulator@102 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ usb3_vbus_reg: regulator@103 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
+ };
+
+ vdd_5v0_reg: regulator@104 {
+ compatible = "regulator-fixed";
+ regulator-name = "5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_bl_reg: regulator@105 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_bl2_reg: regulator@106 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_bl2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
+ };
+
+ i2c@7000d000 {
+ pmic: tps65911@2d {
+ regulators {
+ vddctrl_reg: vddctrl {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1125000>;
+ regulator-coupled-with = <&vddcore_reg>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+
+ nvidia,tegra-cpu-regulator;
+ };
+ };
};
- sys_3v3_reg: regulator@101 {
- compatible = "regulator-fixed";
- reg = <101>;
- regulator-name = "sys_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ vddcore_reg: tps62361@60 {
+ regulator-coupled-with = <&vddctrl_reg>;
+ regulator-coupled-max-spread = <300000>;
+ regulator-max-step-microvolt = <100000>;
+
+ nvidia,tegra-core-regulator;
+ };
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
- usb1_vbus_reg: regulator@102 {
- compatible = "regulator-fixed";
- reg = <102>;
- regulator-name = "usb1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_reg>;
+ cpu@1 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
- usb3_vbus_reg: regulator@103 {
- compatible = "regulator-fixed";
- reg = <103>;
- regulator-name = "usb3_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_reg>;
+ cpu@2 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
- vdd_5v0_reg: regulator@104 {
- compatible = "regulator-fixed";
- reg = <104>;
- regulator-name = "5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
- };
-
- vdd_bl_reg: regulator@105 {
- compatible = "regulator-fixed";
- reg = <105>;
- regulator-name = "vdd_bl";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
- };
-
- vdd_bl2_reg: regulator@106 {
- compatible = "regulator-fixed";
- reg = <106>;
- regulator-name = "vdd_bl2";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
+ cpu@3 {
+ cpu-supply = <&vddctrl_reg>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
};
};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 7ce61ed..57aead7 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -384,7 +384,7 @@
};
};
- sdhci@78000000 {
+ mmc@78000000 {
status = "okay";
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
@@ -392,7 +392,7 @@
bus-width = <4>;
};
- sdhci@78000600 {
+ mmc@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -418,21 +418,14 @@
default-brightness-level = <6>;
};
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk32k_in: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
panel: panel {
- compatible = "chunghwa,claa101wb01", "simple-panel";
+ compatible = "chunghwa,claa101wb01";
ddc-i2c-bus = <&panelddc>;
power-supply = <&vdd_pnl1_reg>;
@@ -441,158 +434,139 @@
backlight = <&backlight>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
+ vdd_ac_bat_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_ac_bat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
- vdd_ac_bat_reg: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "vdd_ac_bat";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
+ cam_1v8_reg: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&vio_reg>;
+ };
- cam_1v8_reg: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "cam_1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
- vin-supply = <&vio_reg>;
- };
+ cp_5v_reg: regulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
+ };
- cp_5v_reg: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "cp_5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- enable-active-high;
- gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
- };
+ emmc_3v3_reg: regulator@3 {
+ compatible = "regulator-fixed";
+ regulator-name = "emmc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
- emmc_3v3_reg: regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "emmc_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
- vin-supply = <&sys_3v3_reg>;
- };
+ modem_3v3_reg: regulator@4 {
+ compatible = "regulator-fixed";
+ regulator-name = "modem_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
+ };
- modem_3v3_reg: regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "modem_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
- };
+ pex_hvdd_3v3_reg: regulator@5 {
+ compatible = "regulator-fixed";
+ regulator-name = "pex_hvdd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
- pex_hvdd_3v3_reg: regulator@5 {
- compatible = "regulator-fixed";
- reg = <5>;
- regulator-name = "pex_hvdd_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
- vin-supply = <&sys_3v3_reg>;
- };
+ vdd_cam1_ldo_reg: regulator@6 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_cam1_ldo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
- vdd_cam1_ldo_reg: regulator@6 {
- compatible = "regulator-fixed";
- reg = <6>;
- regulator-name = "vdd_cam1_ldo";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
- vin-supply = <&sys_3v3_reg>;
- };
+ vdd_cam2_ldo_reg: regulator@7 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_cam2_ldo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
- vdd_cam2_ldo_reg: regulator@7 {
- compatible = "regulator-fixed";
- reg = <7>;
- regulator-name = "vdd_cam2_ldo";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
- vin-supply = <&sys_3v3_reg>;
- };
+ vdd_cam3_ldo_reg: regulator@8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_cam3_ldo";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
- vdd_cam3_ldo_reg: regulator@8 {
- compatible = "regulator-fixed";
- reg = <8>;
- regulator-name = "vdd_cam3_ldo";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
- vin-supply = <&sys_3v3_reg>;
- };
+ vdd_com_reg: regulator@9 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_com";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
- vdd_com_reg: regulator@9 {
- compatible = "regulator-fixed";
- reg = <9>;
- regulator-name = "vdd_com";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
- vin-supply = <&sys_3v3_reg>;
- };
+ vdd_fuse_3v3_reg: regulator@10 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_fuse_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
- vdd_fuse_3v3_reg: regulator@10 {
- compatible = "regulator-fixed";
- reg = <10>;
- regulator-name = "vdd_fuse_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
- vin-supply = <&sys_3v3_reg>;
- };
+ vdd_pnl1_reg: regulator@11 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_pnl1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
+ vin-supply = <&sys_3v3_reg>;
+ };
- vdd_pnl1_reg: regulator@11 {
- compatible = "regulator-fixed";
- reg = <11>;
- regulator-name = "vdd_pnl1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
- vin-supply = <&sys_3v3_reg>;
- };
-
- vdd_vid_reg: regulator@12 {
- compatible = "regulator-fixed";
- reg = <12>;
- regulator-name = "vddio_vid";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
- gpio-open-drain;
- vin-supply = <&vdd_5v0_reg>;
- };
+ vdd_vid_reg: regulator@12 {
+ compatible = "regulator-fixed";
+ regulator-name = "vddio_vid";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
+ gpio-open-drain;
+ vin-supply = <&vdd_5v0_reg>;
};
sound {
@@ -615,12 +589,18 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
- GPIO_ACTIVE_HIGH>;
+ GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA30_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
};
gpio-keys {
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
index 5965150..7d4a6ca 100644
--- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -98,7 +98,7 @@
};
/* SD/MMC */
- sdhci@78000200 {
+ mmc@78000200 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
@@ -159,7 +159,7 @@
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
- compatible = "edt,et057090dhu", "simple-panel";
+ compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <®_3v3>;
};
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 35af03c..e36aa3c 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -527,7 +527,7 @@
};
/* Colibri USBH_OC */
- spi2-cs2-n-pw3, {
+ spi2-cs2-n-pw3 {
nvidia,pins = "spi2_cs2_n_pw3";
nvidia,function = "spi2_alt";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -723,6 +723,7 @@
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <®_module_3v3_audio>;
VDDD-supply = <®_1v8_vio>;
VDDIO-supply = <®_module_3v3>;
@@ -845,11 +846,18 @@
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+ /* ADC converstion time: 80 clocks */
+ st,sample-time = <4>;
+ /* forbid to use ADC channels 3-0 (touch) */
stmpe_touchscreen {
compatible = "st,stmpe-ts";
- /* 3.25 MHz ADC clock speed */
- st,adc-freq = <1>;
/* 8 sample average control */
st,ave-ctrl = <3>;
/* 7 length fractional part in z */
@@ -859,17 +867,16 @@
* current limit value
*/
st,i-drive = <1>;
- /* 12-bit ADC */
- st,mod-12b = <1>;
- /* internal ADC reference */
- st,ref-sel = <0>;
- /* ADC converstion time: 80 clocks */
- st,sample-time = <4>;
/* 1 ms panel driver settling time */
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
};
+
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ st,norequest-mask = <0x0F>;
+ };
};
/*
@@ -927,7 +934,7 @@
};
/* eMMC */
- sdhci@78000600 {
+ mmc@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
@@ -1024,8 +1031,14 @@
nvidia,audio-codec = <&sgtl5000>;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
- <&tegra_car TEGRA30_CLK_EXTERN1>;
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
clock-names = "pll_a", "pll_a_out0", "mclk";
+
+ assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
+ <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+
+ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+ <&tegra_car TEGRA30_CLK_EXTERN1>;
};
};
diff --git a/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi
new file mode 100644
index 0000000..1be715d
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ cpu0_opp_table: cpu_opp_table0 {
+ opp@51000000,800 {
+ opp-microvolt = <800000 800000 1250000>;
+ };
+
+ opp@51000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@51000000,912 {
+ opp-microvolt = <912000 912000 1250000>;
+ };
+
+ opp@102000000,800 {
+ opp-microvolt = <800000 800000 1250000>;
+ };
+
+ opp@102000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@102000000,912 {
+ opp-microvolt = <912000 912000 1250000>;
+ };
+
+ opp@204000000,800 {
+ opp-microvolt = <800000 800000 1250000>;
+ };
+
+ opp@204000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@204000000,912 {
+ opp-microvolt = <912000 912000 1250000>;
+ };
+
+ opp@312000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@312000000,912 {
+ opp-microvolt = <912000 912000 1250000>;
+ };
+
+ opp@340000000,800 {
+ opp-microvolt = <800000 800000 1250000>;
+ };
+
+ opp@340000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@370000000,800 {
+ opp-microvolt = <800000 800000 1250000>;
+ };
+
+ opp@456000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@456000000,912 {
+ opp-microvolt = <912000 912000 1250000>;
+ };
+
+ opp@475000000,800 {
+ opp-microvolt = <800000 800000 1250000>;
+ };
+
+ opp@475000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@608000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@608000000,912 {
+ opp-microvolt = <912000 912000 1250000>;
+ };
+
+ opp@620000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@640000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@640000000,900 {
+ opp-microvolt = <900000 900000 1250000>;
+ };
+
+ opp@760000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@760000000,900 {
+ opp-microvolt = <900000 900000 1250000>;
+ };
+
+ opp@760000000,912 {
+ opp-microvolt = <912000 912000 1250000>;
+ };
+
+ opp@760000000,975 {
+ opp-microvolt = <975000 975000 1250000>;
+ };
+
+ opp@816000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@816000000,912 {
+ opp-microvolt = <912000 912000 1250000>;
+ };
+
+ opp@860000000,850 {
+ opp-microvolt = <850000 850000 1250000>;
+ };
+
+ opp@860000000,900 {
+ opp-microvolt = <900000 900000 1250000>;
+ };
+
+ opp@860000000,975 {
+ opp-microvolt = <975000 975000 1250000>;
+ };
+
+ opp@860000000,1000 {
+ opp-microvolt = <1000000 1000000 1250000>;
+ };
+
+ opp@910000000,900 {
+ opp-microvolt = <900000 900000 1250000>;
+ };
+
+ opp@1000000000,900 {
+ opp-microvolt = <900000 900000 1250000>;
+ };
+
+ opp@1000000000,975 {
+ opp-microvolt = <975000 975000 1250000>;
+ };
+
+ opp@1000000000,1000 {
+ opp-microvolt = <1000000 1000000 1250000>;
+ };
+
+ opp@1000000000,1025 {
+ opp-microvolt = <1025000 1025000 1250000>;
+ };
+
+ opp@1100000000,900 {
+ opp-microvolt = <900000 900000 1250000>;
+ };
+
+ opp@1100000000,975 {
+ opp-microvolt = <975000 975000 1250000>;
+ };
+
+ opp@1100000000,1000 {
+ opp-microvolt = <1000000 1000000 1250000>;
+ };
+
+ opp@1100000000,1025 {
+ opp-microvolt = <1025000 1025000 1250000>;
+ };
+
+ opp@1100000000,1075 {
+ opp-microvolt = <1075000 1075000 1250000>;
+ };
+
+ opp@1150000000,975 {
+ opp-microvolt = <975000 975000 1250000>;
+ };
+
+ opp@1200000000,975 {
+ opp-microvolt = <975000 975000 1250000>;
+ };
+
+ opp@1200000000,1000 {
+ opp-microvolt = <1000000 1000000 1250000>;
+ };
+
+ opp@1200000000,1025 {
+ opp-microvolt = <1025000 1025000 1250000>;
+ };
+
+ opp@1200000000,1050 {
+ opp-microvolt = <1050000 1050000 1250000>;
+ };
+
+ opp@1200000000,1075 {
+ opp-microvolt = <1075000 1075000 1250000>;
+ };
+
+ opp@1200000000,1100 {
+ opp-microvolt = <1100000 1100000 1250000>;
+ };
+
+ opp@1300000000,1000 {
+ opp-microvolt = <1000000 1000000 1250000>;
+ };
+
+ opp@1300000000,1025 {
+ opp-microvolt = <1025000 1025000 1250000>;
+ };
+
+ opp@1300000000,1050 {
+ opp-microvolt = <1050000 1050000 1250000>;
+ };
+
+ opp@1300000000,1075 {
+ opp-microvolt = <1075000 1075000 1250000>;
+ };
+
+ opp@1300000000,1100 {
+ opp-microvolt = <1100000 1100000 1250000>;
+ };
+
+ opp@1300000000,1125 {
+ opp-microvolt = <1125000 1125000 1250000>;
+ };
+
+ opp@1300000000,1150 {
+ opp-microvolt = <1150000 1150000 1250000>;
+ };
+
+ opp@1300000000,1175 {
+ opp-microvolt = <1175000 1175000 1250000>;
+ };
+
+ opp@1400000000,1100 {
+ opp-microvolt = <1100000 1100000 1250000>;
+ };
+
+ opp@1400000000,1125 {
+ opp-microvolt = <1125000 1125000 1250000>;
+ };
+
+ opp@1400000000,1150 {
+ opp-microvolt = <1150000 1150000 1250000>;
+ };
+
+ opp@1400000000,1175 {
+ opp-microvolt = <1175000 1175000 1250000>;
+ };
+
+ opp@1400000000,1237 {
+ opp-microvolt = <1237000 1237000 1250000>;
+ };
+
+ opp@1500000000,1125 {
+ opp-microvolt = <1125000 1125000 1250000>;
+ };
+
+ opp@1500000000,1150 {
+ opp-microvolt = <1150000 1150000 1250000>;
+ };
+
+ opp@1500000000,1200 {
+ opp-microvolt = <1200000 1200000 1250000>;
+ };
+
+ opp@1500000000,1237 {
+ opp-microvolt = <1237000 1237000 1250000>;
+ };
+
+ opp@1600000000,1212 {
+ opp-microvolt = <1212000 1212000 1250000>;
+ };
+
+ opp@1600000000,1237 {
+ opp-microvolt = <1237000 1237000 1250000>;
+ };
+
+ opp@1700000000,1212 {
+ opp-microvolt = <1212000 1212000 1250000>;
+ };
+
+ opp@1700000000,1237 {
+ opp-microvolt = <1237000 1237000 1250000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30-cpu-opp.dtsi b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi
new file mode 100644
index 0000000..0f71350
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cpu-opp.dtsi
@@ -0,0 +1,496 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ cpu0_opp_table: cpu_opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@51000000,800 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x31FE>;
+ opp-hz = /bits/ 64 <51000000>;
+ };
+
+ opp@51000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0C01>;
+ opp-hz = /bits/ 64 <51000000>;
+ };
+
+ opp@51000000,912 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0200>;
+ opp-hz = /bits/ 64 <51000000>;
+ };
+
+ opp@102000000,800 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x31FE>;
+ opp-hz = /bits/ 64 <102000000>;
+ };
+
+ opp@102000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0C01>;
+ opp-hz = /bits/ 64 <102000000>;
+ };
+
+ opp@102000000,912 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0200>;
+ opp-hz = /bits/ 64 <102000000>;
+ };
+
+ opp@204000000,800 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x31FE>;
+ opp-hz = /bits/ 64 <204000000>;
+ };
+
+ opp@204000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0C01>;
+ opp-hz = /bits/ 64 <204000000>;
+ };
+
+ opp@204000000,912 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0200>;
+ opp-hz = /bits/ 64 <204000000>;
+ };
+
+ opp@312000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0C00>;
+ opp-hz = /bits/ 64 <312000000>;
+ };
+
+ opp@312000000,912 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0200>;
+ opp-hz = /bits/ 64 <312000000>;
+ };
+
+ opp@340000000,800 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0192>;
+ opp-hz = /bits/ 64 <340000000>;
+ };
+
+ opp@340000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x0F 0x0001>;
+ opp-hz = /bits/ 64 <340000000>;
+ };
+
+ opp@370000000,800 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1E 0x306C>;
+ opp-hz = /bits/ 64 <370000000>;
+ };
+
+ opp@456000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0C00>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@456000000,912 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0200>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@475000000,800 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1E 0x31FE>;
+ opp-hz = /bits/ 64 <475000000>;
+ };
+
+ opp@475000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x0F 0x0001>, <0x01 0x0002>,
+ <0x01 0x0010>, <0x01 0x0080>,
+ <0x01 0x0100>;
+ opp-hz = /bits/ 64 <475000000>;
+ };
+
+ opp@608000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0400>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@608000000,912 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0200>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@620000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1E 0x306C>;
+ opp-hz = /bits/ 64 <620000000>;
+ };
+
+ opp@640000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x0F 0x0001>, <0x02 0x0002>,
+ <0x04 0x0002>, <0x08 0x0002>,
+ <0x02 0x0010>, <0x04 0x0010>,
+ <0x08 0x0010>, <0x02 0x0080>,
+ <0x04 0x0080>, <0x08 0x0080>,
+ <0x10 0x0080>, <0x02 0x0100>,
+ <0x04 0x0100>, <0x08 0x0100>,
+ <0x10 0x0100>;
+ opp-hz = /bits/ 64 <640000000>;
+ };
+
+ opp@640000000,900 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0192>;
+ opp-hz = /bits/ 64 <640000000>;
+ };
+
+ opp@760000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1E 0x3461>, <0x08 0x0002>,
+ <0x08 0x0004>, <0x08 0x0008>,
+ <0x08 0x0010>, <0x08 0x0080>,
+ <0x10 0x0080>, <0x08 0x0100>,
+ <0x10 0x0100>, <0x01 0x0400>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000,900 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>,
+ <0x04 0x0002>, <0x02 0x0004>,
+ <0x04 0x0004>, <0x02 0x0008>,
+ <0x04 0x0008>, <0x02 0x0010>,
+ <0x04 0x0010>, <0x02 0x0080>,
+ <0x04 0x0080>, <0x02 0x0100>,
+ <0x04 0x0100>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000,912 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0200>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000,975 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0192>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@816000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0400>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@816000000,912 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x1F 0x0200>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@860000000,850 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x0C 0x0001>;
+ opp-hz = /bits/ 64 <860000000>;
+ };
+
+ opp@860000000,900 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>,
+ <0x08 0x0002>, <0x04 0x0004>,
+ <0x08 0x0004>, <0x04 0x0008>,
+ <0x08 0x0008>, <0x04 0x0010>,
+ <0x08 0x0010>, <0x04 0x0080>,
+ <0x08 0x0080>, <0x10 0x0080>,
+ <0x04 0x0100>, <0x08 0x0100>,
+ <0x10 0x0100>;
+ opp-hz = /bits/ 64 <860000000>;
+ };
+
+ opp@860000000,975 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0001>, <0x02 0x0002>,
+ <0x02 0x0004>, <0x02 0x0008>,
+ <0x02 0x0010>, <0x02 0x0080>,
+ <0x02 0x0100>;
+ opp-hz = /bits/ 64 <860000000>;
+ };
+
+ opp@860000000,1000 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0192>;
+ opp-hz = /bits/ 64 <860000000>;
+ };
+
+ opp@910000000,900 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x18 0x3060>;
+ opp-hz = /bits/ 64 <910000000>;
+ };
+
+ opp@1000000000,900 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x0C 0x0001>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000,975 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x03 0x0001>, <0x04 0x0002>,
+ <0x08 0x0002>, <0x04 0x0004>,
+ <0x08 0x0004>, <0x04 0x0008>,
+ <0x08 0x0008>, <0x04 0x0010>,
+ <0x08 0x0010>, <0x04 0x0080>,
+ <0x08 0x0080>, <0x10 0x0080>,
+ <0x04 0x0100>, <0x08 0x0100>,
+ <0x10 0x0100>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000,1000 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x02 0x019E>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000,1025 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0192>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1100000000,900 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x08 0x0001>;
+ opp-hz = /bits/ 64 <1100000000>;
+ };
+
+ opp@1100000000,975 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x06 0x0001>, <0x08 0x0002>,
+ <0x08 0x0004>, <0x08 0x0008>,
+ <0x08 0x0010>, <0x08 0x0080>,
+ <0x10 0x0080>, <0x08 0x0100>,
+ <0x10 0x0100>;
+ opp-hz = /bits/ 64 <1100000000>;
+ };
+
+ opp@1100000000,1000 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0001>, <0x04 0x0002>,
+ <0x04 0x0004>, <0x04 0x0008>,
+ <0x04 0x0010>, <0x04 0x0080>,
+ <0x04 0x0100>;
+ opp-hz = /bits/ 64 <1100000000>;
+ };
+
+ opp@1100000000,1025 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x02 0x019E>;
+ opp-hz = /bits/ 64 <1100000000>;
+ };
+
+ opp@1100000000,1075 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0192>;
+ opp-hz = /bits/ 64 <1100000000>;
+ };
+
+ opp@1150000000,975 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x18 0x3060>;
+ opp-hz = /bits/ 64 <1150000000>;
+ };
+
+ opp@1200000000,975 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x08 0x0001>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000,1000 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>,
+ <0x08 0x0004>, <0x08 0x0008>,
+ <0x08 0x0010>, <0x08 0x0080>,
+ <0x10 0x0080>, <0x08 0x0100>,
+ <0x10 0x0100>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000,1025 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x02 0x0001>, <0x04 0x0002>,
+ <0x04 0x0004>, <0x04 0x0008>,
+ <0x04 0x0010>, <0x04 0x0080>,
+ <0x04 0x0100>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000,1050 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x02 0x019E>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000,1075 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0001>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000,1100 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0192>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1300000000,1000 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x08 0x0001>, <0x10 0x0080>,
+ <0x10 0x0100>;
+ opp-hz = /bits/ 64 <1300000000>;
+ };
+
+ opp@1300000000,1025 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x04 0x0001>, <0x08 0x0002>,
+ <0x08 0x0080>, <0x08 0x0100>;
+ opp-hz = /bits/ 64 <1300000000>;
+ };
+
+ opp@1300000000,1050 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x12 0x3061>, <0x04 0x0002>,
+ <0x08 0x0004>, <0x08 0x0008>,
+ <0x08 0x0010>, <0x08 0x0020>,
+ <0x08 0x0040>, <0x04 0x0080>,
+ <0x04 0x0100>, <0x08 0x1000>,
+ <0x08 0x2000>;
+ opp-hz = /bits/ 64 <1300000000>;
+ };
+
+ opp@1300000000,1075 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x02 0x0182>, <0x04 0x0004>,
+ <0x04 0x0008>, <0x04 0x0010>;
+ opp-hz = /bits/ 64 <1300000000>;
+ };
+
+ opp@1300000000,1100 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x02 0x001C>;
+ opp-hz = /bits/ 64 <1300000000>;
+ };
+
+ opp@1300000000,1125 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0001>;
+ opp-hz = /bits/ 64 <1300000000>;
+ };
+
+ opp@1300000000,1150 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0182>;
+ opp-hz = /bits/ 64 <1300000000>;
+ };
+
+ opp@1300000000,1175 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0010>;
+ opp-hz = /bits/ 64 <1300000000>;
+ };
+
+ opp@1400000000,1100 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x18 0x307C>;
+ opp-hz = /bits/ 64 <1400000000>;
+ };
+
+ opp@1400000000,1125 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x04 0x000C>;
+ opp-hz = /bits/ 64 <1400000000>;
+ };
+
+ opp@1400000000,1150 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x02 0x000C>, <0x04 0x0010>;
+ opp-hz = /bits/ 64 <1400000000>;
+ };
+
+ opp@1400000000,1175 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x02 0x0010>;
+ opp-hz = /bits/ 64 <1400000000>;
+ };
+
+ opp@1400000000,1237 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0010>;
+ opp-hz = /bits/ 64 <1400000000>;
+ };
+
+ opp@1500000000,1125 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x08 0x0010>, <0x10 0x0020>,
+ <0x10 0x0040>, <0x10 0x1000>,
+ <0x10 0x2000>;
+ opp-hz = /bits/ 64 <1500000000>;
+ };
+
+ opp@1500000000,1150 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x04 0x0010>, <0x08 0x0020>,
+ <0x08 0x0040>, <0x08 0x1000>,
+ <0x08 0x2000>;
+ opp-hz = /bits/ 64 <1500000000>;
+ };
+
+ opp@1500000000,1200 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x02 0x0010>;
+ opp-hz = /bits/ 64 <1500000000>;
+ };
+
+ opp@1500000000,1237 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x01 0x0010>;
+ opp-hz = /bits/ 64 <1500000000>;
+ };
+
+ opp@1600000000,1212 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x10 0x3060>;
+ opp-hz = /bits/ 64 <1600000000>;
+ };
+
+ opp@1600000000,1237 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x08 0x3060>;
+ opp-hz = /bits/ 64 <1600000000>;
+ };
+
+ opp@1700000000,1212 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x10 0x3060>;
+ opp-hz = /bits/ 64 <1700000000>;
+ };
+
+ opp@1700000000,1237 {
+ clock-latency-ns = <100000>;
+ opp-supported-hw = <0x08 0x3060>;
+ opp-hz = /bits/ 64 <1700000000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index e074258..aeae8c0 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/memory/tegra30-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra30";
@@ -19,12 +20,12 @@
pcie@3000 {
compatible = "nvidia,tegra30-pcie";
device_type = "pci";
- reg = <0x00003000 0x00000800 /* PADS registers */
- 0x00003800 0x00000200 /* AFI registers */
- 0x10000000 0x10000000>; /* configuration space */
+ reg = <0x00003000 0x00000800>, /* PADS registers */
+ <0x00003800 0x00000200>, /* AFI registers */
+ <0x10000000 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
- GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
@@ -35,12 +36,12 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
- 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
- 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
- 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
- 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
- 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
+ ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
+ <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
+ <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
+ <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
+ <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
+ <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
clocks = <&tegra_car TEGRA30_CLK_PCIE>,
<&tegra_car TEGRA30_CLK_AFI>,
@@ -96,25 +97,27 @@
};
};
- iram@40000000 {
+ sram@40000000 {
compatible = "mmio-sram";
reg = <0x40000000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40000000 0x40000>;
- vde_pool: vde@400 {
+ vde_pool: sram@400 {
reg = <0x400 0x3fc00>;
pool;
};
};
host1x@50000000 {
- compatible = "nvidia,tegra30-host1x", "simple-bus";
+ compatible = "nvidia,tegra30-host1x";
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+ interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
+ clock-names = "host1x";
resets = <&tegra_car 28>;
reset-names = "host1x";
iommus = <&mc TEGRA_SWGROUP_HC>;
@@ -182,8 +185,8 @@
gr3d@54180000 {
compatible = "nvidia,tegra30-gr3d";
reg = <0x54180000 0x00040000>;
- clocks = <&tegra_car TEGRA30_CLK_GR3D
- &tegra_car TEGRA30_CLK_GR3D2>;
+ clocks = <&tegra_car TEGRA30_CLK_GR3D>,
+ <&tegra_car TEGRA30_CLK_GR3D2>;
clock-names = "3d", "3d2";
resets = <&tegra_car 24>,
<&tegra_car 98>;
@@ -194,7 +197,7 @@
};
dc@54200000 {
- compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
+ compatible = "nvidia,tegra30-dc";
reg = <0x54200000 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_DISP1>,
@@ -254,11 +257,24 @@
dsi@54300000 {
compatible = "nvidia,tegra30-dsi";
reg = <0x54300000 0x00040000>;
- clocks = <&tegra_car TEGRA30_CLK_DSIA>;
+ clocks = <&tegra_car TEGRA30_CLK_DSIA>,
+ <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
status = "disabled";
};
+
+ dsi@54400000 {
+ compatible = "nvidia,tegra30-dsi";
+ reg = <0x54400000 0x00040000>;
+ clocks = <&tegra_car TEGRA30_CLK_DSIB>,
+ <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "parent";
+ resets = <&tegra_car 84>;
+ reset-names = "dsi";
+ status = "disabled";
+ };
};
timer@50040600 {
@@ -272,8 +288,8 @@
intc: interrupt-controller@50041000 {
compatible = "arm,cortex-a9-gic";
- reg = <0x50041000 0x1000
- 0x50040100 0x0100>;
+ reg = <0x50041000 0x1000>,
+ <0x50040100 0x0100>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&intc>;
@@ -403,15 +419,15 @@
vde@6001a000 {
compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
- reg = <0x6001a000 0x1000 /* Syntax Engine */
- 0x6001b000 0x1000 /* Video Bitstream Engine */
- 0x6001c000 0x100 /* Macroblock Engine */
- 0x6001c200 0x100 /* Post-processing Engine */
- 0x6001c400 0x100 /* Motion Compensation Engine */
- 0x6001c600 0x100 /* Transform Engine */
- 0x6001c800 0x100 /* Pixel prediction block */
- 0x6001ca00 0x100 /* Video DMA */
- 0x6001d800 0x400>; /* Video frame controls */
+ reg = <0x6001a000 0x1000>, /* Syntax Engine */
+ <0x6001b000 0x1000>, /* Video Bitstream Engine */
+ <0x6001c000 0x100>, /* Macroblock Engine */
+ <0x6001c200 0x100>, /* Post-processing Engine */
+ <0x6001c400 0x100>, /* Motion Compensation Engine */
+ <0x6001c600 0x100>, /* Transform Engine */
+ <0x6001c800 0x100>, /* Pixel prediction block */
+ <0x6001ca00 0x100>, /* Video DMA */
+ <0x6001d800 0x400>; /* Video frame controls */
reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
"tfe", "ppb", "vdma", "frameid";
iram = <&vde_pool>; /* IRAM region */
@@ -422,18 +438,19 @@
clocks = <&tegra_car TEGRA30_CLK_VDE>;
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
+ iommus = <&mc TEGRA_SWGROUP_VDE>;
};
apbmisc@70000800 {
compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
- reg = <0x70000800 0x64 /* Chip revision */
- 0x70000008 0x04>; /* Strapping options */
+ reg = <0x70000800 0x64>, /* Chip revision */
+ <0x70000008 0x04>; /* Strapping options */
};
pinmux: pinmux@70000868 {
compatible = "nvidia,tegra30-pinmux";
- reg = <0x70000868 0xd4 /* Pad control registers */
- 0x70003000 0x3e4>; /* Mux registers */
+ reg = <0x70000868 0x0d4>, /* Pad control registers */
+ <0x70003000 0x3e4>; /* Mux registers */
};
/*
@@ -713,11 +730,12 @@
status = "disabled";
};
- pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
};
mc: memory-controller@7000f000 {
@@ -732,6 +750,15 @@
#reset-cells = <1>;
};
+ memory-controller@7000f400 {
+ compatible = "nvidia,tegra30-emc";
+ reg = <0x7000f400 0x400>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_EMC>;
+
+ nvidia,memory-controller = <&mc>;
+ };
+
fuse@7000f800 {
compatible = "nvidia,tegra30-efuse";
reg = <0x7000f800 0x400>;
@@ -758,8 +785,8 @@
ahub@70080000 {
compatible = "nvidia,tegra30-ahub";
- reg = <0x70080000 0x200
- 0x70080200 0x100>;
+ reg = <0x70080000 0x200>,
+ <0x70080200 0x100>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
<&tegra_car TEGRA30_CLK_APBIF>;
@@ -839,41 +866,45 @@
};
};
- sdhci@78000000 {
- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+ mmc@78000000 {
+ compatible = "nvidia,tegra30-sdhci";
reg = <0x78000000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
+ clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@78000200 {
- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+ mmc@78000200 {
+ compatible = "nvidia,tegra30-sdhci";
reg = <0x78000200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
+ clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@78000400 {
- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+ mmc@78000400 {
+ compatible = "nvidia,tegra30-sdhci";
reg = <0x78000400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+ clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
};
- sdhci@78000600 {
- compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+ mmc@78000600 {
+ compatible = "nvidia,tegra30-sdhci";
reg = <0x78000600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
+ clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
@@ -894,7 +925,8 @@
phy1: usb-phy@7d000000 {
compatible = "nvidia,tegra30-usb-phy";
- reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
+ reg = <0x7d000000 0x4000>,
+ <0x7d000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA30_CLK_USBD>,
<&tegra_car TEGRA30_CLK_PLL_U>,
@@ -902,6 +934,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 22>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <9>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
@@ -931,7 +964,8 @@
phy2: usb-phy@7d004000 {
compatible = "nvidia,tegra30-usb-phy";
- reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
+ reg = <0x7d004000 0x4000>,
+ <0x7d000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA30_CLK_USB2>,
<&tegra_car TEGRA30_CLK_PLL_U>,
@@ -939,6 +973,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <9>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
@@ -967,7 +1002,8 @@
phy3: usb-phy@7d008000 {
compatible = "nvidia,tegra30-usb-phy";
- reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
+ reg = <0x7d008000 0x4000>,
+ <0x7d000000 0x4000>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA30_CLK_USB3>,
<&tegra_car TEGRA30_CLK_PLL_U>,
@@ -975,6 +1011,7 @@
clock-names = "reg", "pll_u", "utmi-pads";
resets = <&tegra_car 59>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
nvidia,hssync-start-delay = <0>;
nvidia,idle-wait-delay = <17>;
nvidia,elastic-limit = <16>;
@@ -997,24 +1034,28 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
+ clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
+ clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
};
};
diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi
index dd6957b..70e5635 100644
--- a/arch/arm/boot/dts/tny_a9260_common.dtsi
+++ b/arch/arm/boot/dts/tny_a9260_common.dtsi
@@ -10,7 +10,7 @@
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
index 2820635..62b7d9f 100644
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -15,7 +15,7 @@
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
diff --git a/arch/arm/boot/dts/twl6030_omap4.dtsi b/arch/arm/boot/dts/twl6030_omap4.dtsi
index fc498d0..5730e46 100644
--- a/arch/arm/boot/dts/twl6030_omap4.dtsi
+++ b/arch/arm/boot/dts/twl6030_omap4.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
&twl {
diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts
index f2d060f..c46c2e8 100644
--- a/arch/arm/boot/dts/uniphier-ld4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts
@@ -20,7 +20,7 @@
aliases {
serial0 = &serial0;
- serial1 = &serial1;
+ serial1 = &serialsc;
serial2 = &serial2;
serial3 = &serial3;
i2c0 = &i2c0;
@@ -39,6 +39,10 @@
interrupts = <1 8>;
};
+&serialsc {
+ interrupts = <1 8>;
+};
+
&serial0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 58cd4e8..b52957c 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -51,7 +51,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
@@ -67,6 +67,8 @@
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 39 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
@@ -245,7 +247,7 @@
#dma-cells = <1>;
};
- sd: sdhc@5a400000 {
+ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
@@ -265,7 +267,7 @@
sd-uhs-sdr50;
};
- emmc: sdhc@5a500000 {
+ emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
@@ -375,7 +377,7 @@
interrupt-controller;
};
- aidet: aidet@61830000 {
+ aidet: interrupt-controller@61830000 {
compatible = "socionext,uniphier-ld4-aidet";
reg = <0x61830000 0x200>;
interrupt-controller;
@@ -398,7 +400,7 @@
};
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -410,7 +412,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
index 60994b6..5bc7fe1 100644
--- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
@@ -22,6 +22,7 @@
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
+ serial3 = &serialsc;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -29,6 +30,7 @@
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ ethernet0 = ð
};
memory@80000000 {
@@ -41,6 +43,10 @@
interrupts = <4 8>;
};
+&serialsc {
+ interrupts = <4 8>;
+};
+
&serial0 {
status = "okay";
};
@@ -75,7 +81,7 @@
};
&mdio {
- ethphy: ethphy@0 {
+ ethphy: ethernet-phy@0 {
reg = <0>;
};
};
diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
index 1fee5ff..c0fd029 100644
--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
@@ -106,6 +106,16 @@
function = "i2c4";
};
+ pinctrl_i2c5: i2c5 {
+ groups = "i2c5";
+ function = "i2c5";
+ };
+
+ pinctrl_i2c6: i2c6 {
+ groups = "i2c6";
+ function = "i2c6";
+ };
+
pinctrl_nand: nand {
groups = "nand";
function = "nand";
@@ -116,6 +126,11 @@
function = "nand";
};
+ pinctrl_pcie: pcie {
+ groups = "pcie";
+ function = "pcie";
+ };
+
pinctrl_sd: sd {
groups = "sd";
function = "sd";
diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts
index 92cc48d..27ff2b7 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts
@@ -26,6 +26,7 @@
i2c3 = &i2c3;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ ethernet0 = ð
};
memory@80000000 {
@@ -86,7 +87,7 @@
};
&mdio {
- ethphy: ethphy@1 {
+ ethphy: ethernet-phy@1 {
reg = <1>;
};
};
diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts
index 854f2eb..3b9b613 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts
@@ -22,13 +22,14 @@
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
- serial3 = &serial3;
+ serial3 = &serialsc;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ ethernet0 = ð
};
memory@80000000 {
@@ -41,6 +42,10 @@
interrupts = <2 8>;
};
+&serialsc {
+ interrupts = <2 8>;
+};
+
&serial0 {
status = "okay";
};
@@ -83,7 +88,7 @@
};
&mdio {
- ethphy: ethphy@0 {
+ ethphy: ethernet-phy@0 {
reg = <0>;
};
};
diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
index dda1a2f..7b6faf2 100644
--- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
@@ -25,6 +25,7 @@
i2c3 = &i2c3;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ ethernet0 = ð
};
memory@80000000 {
@@ -81,7 +82,7 @@
};
&mdio {
- ethphy: ethphy@1 {
+ ethphy: ethernet-phy@1 {
reg = <1>;
};
};
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index 7f64e5a..a53b73e 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -59,7 +59,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
@@ -75,6 +75,8 @@
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 39 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
@@ -279,7 +281,7 @@
#dma-cells = <1>;
};
- sd: sdhc@5a400000 {
+ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
@@ -299,7 +301,7 @@
sd-uhs-sdr50;
};
- emmc: sdhc@5a500000 {
+ emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
@@ -317,7 +319,7 @@
non-removable;
};
- sd1: sdhc@5a600000 {
+ sd1: mmc@5a600000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a600000 0x200>;
@@ -426,7 +428,15 @@
};
};
- aidet: aidet@5fc20000 {
+ xdmac: dma-controller@5fc10000 {
+ compatible = "socionext,uniphier-xdmac";
+ reg = <0x5fc10000 0x5300>;
+ interrupts = <0 188 4>;
+ dma-channels = <16>;
+ #dma-cells = <2>;
+ };
+
+ aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-pro4-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
@@ -588,7 +598,7 @@
};
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -600,7 +610,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index eff7471..3525125 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -131,7 +131,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
@@ -144,7 +144,7 @@
next-level-cache = <&l3>;
};
- l3: l3-cache@500c8000 {
+ l3: cache-controller@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
@@ -160,6 +160,8 @@
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 39 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
@@ -171,11 +173,13 @@
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 216 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&peri_clk 11>;
- resets = <&peri_rst 11>;
+ clocks = <&peri_clk 11>; /* common with spi0 */
+ resets = <&peri_rst 12>;
};
serial0: serial@54006800 {
@@ -408,7 +412,15 @@
};
};
- aidet: aidet@5fc20000 {
+ xdmac: dma-controller@5fc10000 {
+ compatible = "socionext,uniphier-xdmac";
+ reg = <0x5fc10000 0x5300>;
+ interrupts = <0 188 4>;
+ dma-channels = <16>;
+ #dma-cells = <2>;
+ };
+
+ aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-pro5-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
@@ -453,7 +465,185 @@
};
};
- nand: nand@68000000 {
+ usb0: usb@65a00000 {
+ compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+ status = "disabled";
+ reg = <0x65a00000 0xcd00>;
+ interrupt-names = "host";
+ interrupts = <0 134 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clock-names = "ref", "bus_early", "suspend";
+ clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+ resets = <&usb0_rst 15>;
+ phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
+ dr_mode = "host";
+ };
+
+ usb-glue@65b00000 {
+ compatible = "socionext,uniphier-pro5-dwc3-glue",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65b00000 0x400>;
+
+ usb0_rst: reset@0 {
+ compatible = "socionext,uniphier-pro5-usb3-reset";
+ reg = <0x0 0x4>;
+ #reset-cells = <1>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 14>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 14>;
+ };
+
+ usb0_vbus0: regulator@100 {
+ compatible = "socionext,uniphier-pro5-usb3-regulator";
+ reg = <0x100 0x10>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 14>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 14>;
+ };
+
+ usb0_hsphy0: hs-phy@280 {
+ compatible = "socionext,uniphier-pro5-usb3-hsphy";
+ reg = <0x280 0x10>;
+ #phy-cells = <0>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 14>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 14>;
+ vbus-supply = <&usb0_vbus0>;
+ };
+
+ usb0_ssphy0: ss-phy@380 {
+ compatible = "socionext,uniphier-pro5-usb3-ssphy";
+ reg = <0x380 0x10>;
+ #phy-cells = <0>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 14>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 14>;
+ vbus-supply = <&usb0_vbus0>;
+ };
+ };
+
+ usb1: usb@65c00000 {
+ compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+ status = "disabled";
+ reg = <0x65c00000 0xcd00>;
+ interrupt-names = "host";
+ interrupts = <0 137 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
+ clock-names = "ref", "bus_early", "suspend";
+ clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+ resets = <&usb1_rst 15>;
+ phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
+ dr_mode = "host";
+ };
+
+ usb-glue@65d00000 {
+ compatible = "socionext,uniphier-pro5-dwc3-glue",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65d00000 0x400>;
+
+ usb1_rst: reset@0 {
+ compatible = "socionext,uniphier-pro5-usb3-reset";
+ reg = <0x0 0x4>;
+ #reset-cells = <1>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 15>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 15>;
+ };
+
+ usb1_vbus0: regulator@100 {
+ compatible = "socionext,uniphier-pro5-usb3-regulator";
+ reg = <0x100 0x10>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 15>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 15>;
+ };
+
+ usb1_vbus1: regulator@110 {
+ compatible = "socionext,uniphier-pro5-usb3-regulator";
+ reg = <0x110 0x10>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 15>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 15>;
+ };
+
+ usb1_hsphy0: hs-phy@280 {
+ compatible = "socionext,uniphier-pro5-usb3-hsphy";
+ reg = <0x280 0x10>;
+ #phy-cells = <0>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 15>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 15>;
+ vbus-supply = <&usb1_vbus0>;
+ };
+
+ usb1_hsphy1: hs-phy@290 {
+ compatible = "socionext,uniphier-pro5-usb3-hsphy";
+ reg = <0x290 0x10>;
+ #phy-cells = <0>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 15>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 15>;
+ vbus-supply = <&usb1_vbus1>;
+ };
+
+ usb1_ssphy0: ss-phy@380 {
+ compatible = "socionext,uniphier-pro5-usb3-ssphy";
+ reg = <0x380 0x10>;
+ #phy-cells = <0>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 15>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 15>;
+ vbus-supply = <&usb1_vbus0>;
+ };
+ };
+
+ pcie_ep: pcie-ep@66000000 {
+ compatible = "socionext,uniphier-pro5-pcie-ep",
+ "snps,dw-pcie-ep";
+ status = "disabled";
+ reg-names = "dbi", "dbi2", "link", "addr_space";
+ reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
+ <0x66010000 0x10000>, <0x67000000 0x400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 24>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 24>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ num-lanes = <4>;
+ phy-names = "pcie-phy";
+ phys = <&pcie_phy>;
+ };
+
+ pcie_phy: phy@66038000 {
+ compatible = "socionext,uniphier-pro5-pcie-phy";
+ reg = <0x66038000 0x4000>;
+ #phy-cells = <0>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 24>;
+ reset-names = "gio", "link";
+ resets = <&sys_rst 12>, <&sys_rst 24>;
+ };
+
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -465,10 +655,11 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
- emmc: sdhc@68400000 {
+ emmc: mmc@68400000 {
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68400000 0x800>;
@@ -484,7 +675,7 @@
non-removable;
};
- sd: sdhc@68800000 {
+ sd: mmc@68800000 {
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68800000 0x800>;
diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
index e27fd4f..759384b 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
@@ -26,6 +26,7 @@
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ ethernet0 = ð
};
memory@80000000 {
@@ -86,7 +87,7 @@
};
&mdio {
- ethphy: ethphy@1 {
+ ethphy: ethernet-phy@1 {
reg = <1>;
};
};
diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
index 23fe42b..7e08a45 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
@@ -24,6 +24,7 @@
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
+ ethernet0 = ð
};
memory@80000000 {
@@ -87,7 +88,7 @@
};
&mdio {
- ethphy: ethphy@1 {
+ ethphy: ethernet-phy@1 {
reg = <1>;
};
};
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 60a588c..e81e593 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -157,7 +157,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
@@ -173,6 +173,8 @@
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 39 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
@@ -184,11 +186,13 @@
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 216 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- clocks = <&peri_clk 11>;
- resets = <&peri_rst 11>;
+ clocks = <&peri_clk 12>;
+ resets = <&peri_rst 12>;
};
serial0: serial@54006800 {
@@ -446,7 +450,7 @@
};
};
- emmc: sdhc@5a000000 {
+ emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a000000 0x800>;
@@ -462,7 +466,7 @@
non-removable;
};
- sd: sdhc@5a400000 {
+ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
@@ -508,7 +512,15 @@
};
};
- aidet: aidet@5fc20000 {
+ xdmac: dma-controller@5fc10000 {
+ compatible = "socionext,uniphier-xdmac";
+ reg = <0x5fc10000 0x5300>;
+ interrupts = <0 188 4>;
+ dma-channels = <16>;
+ #dma-cells = <2>;
+ };
+
+ aidet: interrupt-controller@5fc20000 {
compatible = "socionext,uniphier-pxs2-aidet";
reg = <0x5fc20000 0x200>;
interrupt-controller;
@@ -761,7 +773,7 @@
};
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5b";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -773,7 +785,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
index 04e60c2..a118976 100644
--- a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
+++ b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
@@ -7,7 +7,7 @@
&i2c0 {
eeprom@50 {
- compatible = "microchip,24lc128";
+ compatible = "microchip,24lc128", "atmel,24c128";
reg = <0x50>;
pagesize = <64>;
};
diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts
index cf9ea0b..6db949e 100644
--- a/arch/arm/boot/dts/uniphier-sld8-ref.dts
+++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts
@@ -20,7 +20,7 @@
aliases {
serial0 = &serial0;
- serial1 = &serial1;
+ serial1 = &serialsc;
serial2 = &serial2;
serial3 = &serial3;
i2c0 = &i2c0;
@@ -39,6 +39,10 @@
interrupts = <0 8>;
};
+&serialsc {
+ interrupts = <0 8>;
+};
+
&serial0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index cbebb6e..96a766d 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -51,7 +51,7 @@
ranges;
interrupt-parent = <&intc>;
- l2: l2-cache@500c0000 {
+ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
@@ -67,6 +67,8 @@
compatible = "socionext,uniphier-scssi";
status = "disabled";
reg = <0x54006000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 39 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
@@ -249,7 +251,7 @@
#dma-cells = <1>;
};
- sd: sdhc@5a400000 {
+ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
@@ -269,7 +271,7 @@
sd-uhs-sdr50;
};
- emmc: sdhc@5a500000 {
+ emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
@@ -379,7 +381,7 @@
interrupt-controller;
};
- aidet: aidet@61830000 {
+ aidet: interrupt-controller@61830000 {
compatible = "socionext,uniphier-sld8-aidet";
reg = <0x61830000 0x200>;
interrupt-controller;
@@ -402,7 +404,7 @@
};
};
- nand: nand@68000000 {
+ nand: nand-controller@68000000 {
compatible = "socionext,uniphier-denali-nand-v5a";
status = "disabled";
reg-names = "nand_data", "denali_reg";
@@ -414,7 +416,8 @@
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
- resets = <&sys_rst 2>;
+ reset-names = "nand", "reg";
+ resets = <&sys_rst 2>, <&sys_rst 2>;
};
};
};
diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi
index bf441c2..444802f 100644
--- a/arch/arm/boot/dts/uniphier-support-card.dtsi
+++ b/arch/arm/boot/dts/uniphier-support-card.dtsi
@@ -8,26 +8,19 @@
&system_bus {
status = "okay";
ranges = <1 0x00000000 0x42000000 0x02000000>;
+ interrupt-parent = <&gpio>;
- support_card: support-card@1,1f00000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 1 0x01f00000 0x00100000>;
- interrupt-parent = <&gpio>;
+ ethsc: ethernet@1,1f00000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <1 0x01f00000 0x1000>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ };
- ethsc: ethernet@0 {
- compatible = "smsc,lan9118", "smsc,lan9115";
- reg = <0x00000000 0x1000>;
- phy-mode = "mii";
- reg-io-width = <4>;
- };
-
- serialsc: uart@b0000 {
- compatible = "ns16550a";
- reg = <0x000b0000 0x20>;
- clock-frequency = <12288000>;
- reg-shift = <1>;
- };
+ serialsc: serial@1,1fb0000 {
+ compatible = "ns16550a";
+ reg = <1 0x01fb0000 0x20>;
+ clock-frequency = <12288000>;
+ reg-shift = <1>;
};
};
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts
index ec8cd86..6cfa839 100644
--- a/arch/arm/boot/dts/usb_a9260.dts
+++ b/arch/arm/boot/dts/usb_a9260.dts
@@ -16,7 +16,7 @@
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index e7a705f..8a0cfbf 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -15,7 +15,7 @@
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi
index adbe750..7d10b36 100644
--- a/arch/arm/boot/dts/usb_a9g20_common.dtsi
+++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi
@@ -14,7 +14,7 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@20000000 {
reg = <0x20000000 0x4000000>;
};
diff --git a/arch/arm/boot/dts/versatile-ab-ib2.dts b/arch/arm/boot/dts/versatile-ab-ib2.dts
index 5890cb9..c577ff4 100644
--- a/arch/arm/boot/dts/versatile-ab-ib2.dts
+++ b/arch/arm/boot/dts/versatile-ab-ib2.dts
@@ -10,7 +10,7 @@
model = "ARM Versatile AB + IB2 board";
/* Special IB2 control register */
- ib2_syscon@27000000 {
+ syscon@27000000 {
compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd";
reg = <0x27000000 0x4>;
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index ce64bfb..4f7220b 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -19,8 +19,89 @@
*/
/ {
- smb@8000000 {
- motherboard {
+ v2m_fixed_3v3: fixed-regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ v2m_clk24mhz: clk24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "v2m:clk24mhz";
+ };
+
+ v2m_refclk1mhz: refclk1mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000>;
+ clock-output-names = "v2m:refclk1mhz";
+ };
+
+ v2m_refclk32khz: refclk32khz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "v2m:refclk32khz";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-1 {
+ label = "v2m:green:user1";
+ gpios = <&v2m_led_gpios 0 0>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-2 {
+ label = "v2m:green:user2";
+ gpios = <&v2m_led_gpios 1 0>;
+ linux,default-trigger = "disk-activity";
+ };
+
+ led-3 {
+ label = "v2m:green:user3";
+ gpios = <&v2m_led_gpios 2 0>;
+ linux,default-trigger = "cpu0";
+ };
+
+ led-4 {
+ label = "v2m:green:user4";
+ gpios = <&v2m_led_gpios 3 0>;
+ linux,default-trigger = "cpu1";
+ };
+
+ led-5 {
+ label = "v2m:green:user5";
+ gpios = <&v2m_led_gpios 4 0>;
+ linux,default-trigger = "cpu2";
+ };
+
+ led-6 {
+ label = "v2m:green:user6";
+ gpios = <&v2m_led_gpios 5 0>;
+ linux,default-trigger = "cpu3";
+ };
+
+ led-7 {
+ label = "v2m:green:user7";
+ gpios = <&v2m_led_gpios 6 0>;
+ linux,default-trigger = "cpu4";
+ };
+
+ led-8 {
+ label = "v2m:green:user8";
+ gpios = <&v2m_led_gpios 7 0>;
+ linux,default-trigger = "cpu5";
+ };
+ };
+
+ bus@8000000 {
+ motherboard-bus {
model = "V2M-P1";
arm,hbi = <0x190>;
arm,vexpress,site = <0>;
@@ -66,7 +147,7 @@
port1-otg;
};
- iofpga@300000000 {
+ iofpga-bus@300000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -162,7 +243,7 @@
clock-names = "KMIREFCLK", "apb_pclk";
};
- v2m_serial0: uart@90000 {
+ v2m_serial0: serial@90000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
@@ -170,7 +251,7 @@
clock-names = "uartclk", "apb_pclk";
};
- v2m_serial1: uart@a0000 {
+ v2m_serial1: serial@a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
@@ -178,7 +259,7 @@
clock-names = "uartclk", "apb_pclk";
};
- v2m_serial2: uart@b0000 {
+ v2m_serial2: serial@b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
@@ -186,7 +267,7 @@
clock-names = "uartclk", "apb_pclk";
};
- v2m_serial3: uart@c0000 {
+ v2m_serial3: serial@c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
@@ -199,7 +280,7 @@
reg = <0x0f0000 0x1000>;
interrupts = <0>;
clocks = <&v2m_refclk32khz>, <&smbclk>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
};
v2m_timer01: timer@110000 {
@@ -281,159 +362,78 @@
};
};
};
- };
- v2m_fixed_3v3: fixed-regulator-0 {
- compatible = "regulator-fixed";
- regulator-name = "3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
+ mcc {
+ compatible = "arm,vexpress,config-bus";
+ arm,vexpress,config-bridge = <&v2m_sysreg>;
- v2m_clk24mhz: clk24mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "v2m:clk24mhz";
- };
+ oscclk0 {
+ /* MCC static memory clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 0>;
+ freq-range = <25000000 60000000>;
+ #clock-cells = <0>;
+ clock-output-names = "v2m:oscclk0";
+ };
- v2m_refclk1mhz: refclk1mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000>;
- clock-output-names = "v2m:refclk1mhz";
- };
+ v2m_oscclk1: oscclk1 {
+ /* CLCD clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 1>;
+ freq-range = <23750000 65000000>;
+ #clock-cells = <0>;
+ clock-output-names = "v2m:oscclk1";
+ };
- v2m_refclk32khz: refclk32khz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "v2m:refclk32khz";
- };
+ v2m_oscclk2: oscclk2 {
+ /* IO FPGA peripheral clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 2>;
+ freq-range = <24000000 24000000>;
+ #clock-cells = <0>;
+ clock-output-names = "v2m:oscclk2";
+ };
- leds {
- compatible = "gpio-leds";
+ volt-vio {
+ /* Logic level voltage */
+ compatible = "arm,vexpress-volt";
+ arm,vexpress-sysreg,func = <2 0>;
+ regulator-name = "VIO";
+ regulator-always-on;
+ label = "VIO";
+ };
- user1 {
- label = "v2m:green:user1";
- gpios = <&v2m_led_gpios 0 0>;
- linux,default-trigger = "heartbeat";
- };
+ temp-mcc {
+ /* MCC internal operating temperature */
+ compatible = "arm,vexpress-temp";
+ arm,vexpress-sysreg,func = <4 0>;
+ label = "MCC";
+ };
- user2 {
- label = "v2m:green:user2";
- gpios = <&v2m_led_gpios 1 0>;
- linux,default-trigger = "mmc0";
- };
+ reset {
+ compatible = "arm,vexpress-reset";
+ arm,vexpress-sysreg,func = <5 0>;
+ };
- user3 {
- label = "v2m:green:user3";
- gpios = <&v2m_led_gpios 2 0>;
- linux,default-trigger = "cpu0";
- };
+ muxfpga {
+ compatible = "arm,vexpress-muxfpga";
+ arm,vexpress-sysreg,func = <7 0>;
+ };
- user4 {
- label = "v2m:green:user4";
- gpios = <&v2m_led_gpios 3 0>;
- linux,default-trigger = "cpu1";
- };
+ shutdown {
+ compatible = "arm,vexpress-shutdown";
+ arm,vexpress-sysreg,func = <8 0>;
+ };
- user5 {
- label = "v2m:green:user5";
- gpios = <&v2m_led_gpios 4 0>;
- linux,default-trigger = "cpu2";
- };
+ reboot {
+ compatible = "arm,vexpress-reboot";
+ arm,vexpress-sysreg,func = <9 0>;
+ };
- user6 {
- label = "v2m:green:user6";
- gpios = <&v2m_led_gpios 5 0>;
- linux,default-trigger = "cpu3";
- };
-
- user7 {
- label = "v2m:green:user7";
- gpios = <&v2m_led_gpios 6 0>;
- linux,default-trigger = "cpu4";
- };
-
- user8 {
- label = "v2m:green:user8";
- gpios = <&v2m_led_gpios 7 0>;
- linux,default-trigger = "cpu5";
- };
- };
-
- mcc {
- compatible = "arm,vexpress,config-bus";
- arm,vexpress,config-bridge = <&v2m_sysreg>;
-
- oscclk0 {
- /* MCC static memory clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 0>;
- freq-range = <25000000 60000000>;
- #clock-cells = <0>;
- clock-output-names = "v2m:oscclk0";
- };
-
- v2m_oscclk1: oscclk1 {
- /* CLCD clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 1>;
- freq-range = <23750000 65000000>;
- #clock-cells = <0>;
- clock-output-names = "v2m:oscclk1";
- };
-
- v2m_oscclk2: oscclk2 {
- /* IO FPGA peripheral clock */
- compatible = "arm,vexpress-osc";
- arm,vexpress-sysreg,func = <1 2>;
- freq-range = <24000000 24000000>;
- #clock-cells = <0>;
- clock-output-names = "v2m:oscclk2";
- };
-
- volt-vio {
- /* Logic level voltage */
- compatible = "arm,vexpress-volt";
- arm,vexpress-sysreg,func = <2 0>;
- regulator-name = "VIO";
- regulator-always-on;
- label = "VIO";
- };
-
- temp-mcc {
- /* MCC internal operating temperature */
- compatible = "arm,vexpress-temp";
- arm,vexpress-sysreg,func = <4 0>;
- label = "MCC";
- };
-
- reset {
- compatible = "arm,vexpress-reset";
- arm,vexpress-sysreg,func = <5 0>;
- };
-
- muxfpga {
- compatible = "arm,vexpress-muxfpga";
- arm,vexpress-sysreg,func = <7 0>;
- };
-
- shutdown {
- compatible = "arm,vexpress-shutdown";
- arm,vexpress-sysreg,func = <8 0>;
- };
-
- reboot {
- compatible = "arm,vexpress-reboot";
- arm,vexpress-sysreg,func = <9 0>;
- };
-
- dvimode {
- compatible = "arm,vexpress-dvimode";
- arm,vexpress-sysreg,func = <11 0>;
+ dvimode {
+ compatible = "arm,vexpress-dvimode";
+ arm,vexpress-sysreg,func = <11 0>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index 2e29d77..659dcf4 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -19,7 +19,7 @@
*/
/ {
- smb@4000000 {
+ bus@40000000 {
motherboard {
model = "V2M-P1";
arm,hbi = <0x190>;
@@ -198,7 +198,7 @@
reg = <0x0f000 0x1000>;
interrupts = <0>;
clocks = <&v2m_refclk32khz>, <&smbclk>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
};
v2m_timer01: timer@11000 {
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 0dc4277..e63c5c0 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -87,8 +87,8 @@
status = "disabled";
reg = <0 0x2b060000 0 0x1000>;
interrupts = <0 98 4>;
- clocks = <&sys_pll>;
- clock-names = "apb_pclk";
+ clocks = <&sys_pll>, <&sys_pll>;
+ clock-names = "wdog_clk", "apb_pclk";
};
gic: interrupt-controller@2c001000 {
@@ -236,7 +236,7 @@
};
};
- smb@8000000 {
+ bus@8000000 {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 1de0a65..012d40a 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -128,7 +128,7 @@
reg = <0 0x2a490000 0 0x1000>;
interrupts = <0 98 4>;
clocks = <&oscclk6a>, <&oscclk6a>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
};
hdlcd@2b000000 {
@@ -608,7 +608,7 @@
};
};
- smb: smb@8000000 {
+ smb: bus@8000000 {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index d5b47d5..7aa64ae 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -206,7 +206,7 @@
};
};
- smb: smb@8000000 {
+ smb: bus@8000000 {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index d796efa..1317f0f 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -122,8 +122,8 @@
reg = <0x100e4000 0x1000>;
interrupts = <0 48 4>,
<0 49 4>;
- clocks = <&oscclk2>, <&oscclk2>;
- clock-names = "timclk", "apb_pclk";
+ clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -132,7 +132,7 @@
reg = <0x100e5000 0x1000>;
interrupts = <0 51 4>;
clocks = <&oscclk2>, <&oscclk2>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
};
scu@1e000000 {
@@ -295,7 +295,7 @@
};
};
- smb: smb@4000000 {
+ smb: bus@40000000 {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index e2da122..c12a1b8 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2014-2020 Toradex
*/
/ {
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index b6a1eee..cc1e069 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -1,42 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014 Toradex AG
+ * Copyright 2014-2020 Toradex
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/ {
@@ -129,8 +94,11 @@
&i2c0 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&nfc {
@@ -308,6 +276,13 @@
>;
};
+ pinctrl_i2c0_gpio: i2c0gpiogrp {
+ fsl,pins = <
+ VF610_PAD_PTB14__GPIO_36 0x37ff
+ VF610_PAD_PTB15__GPIO_37 0x37ff
+ >;
+ };
+
pinctrl_nfc: nfcgrp {
fsl,pins = <
VF610_PAD_PTD23__NF_IO7 0x28df
diff --git a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
index 0769989..088964f 100644
--- a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2014-2020 Toradex
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi
index 237b024..8af7ed5 100644
--- a/arch/arm/boot/dts/vf500-colibri.dtsi
+++ b/arch/arm/boot/dts/vf500-colibri.dtsi
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2014-2020 Toradex
*/
#include "vf500.dtsi"
@@ -44,7 +8,7 @@
/ {
model = "Toradex Colibri VF50 COM";
- compatible = "toradex,vf610-colibri_vf50", "fsl,vf500";
+ compatible = "toradex,vf500-colibri_vf50", "fsl,vf500";
memory@80000000 {
device_type = "memory";
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index b0ec475..0c0dd44 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -23,7 +23,7 @@
};
soc {
- aips-bus@40000000 {
+ bus@40000000 {
intc: interrupt-controller@40003000 {
compatible = "arm,cortex-a9-gic";
@@ -43,7 +43,7 @@
};
};
- aips-bus@40080000 {
+ bus@40080000 {
pmu@40089000 {
compatible = "arm,cortex-a5-pmu";
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/vf610-bk4.dts
index 0f3870d..830c854 100644
--- a/arch/arm/boot/dts/vf610-bk4.dts
+++ b/arch/arm/boot/dts/vf610-bk4.dts
@@ -259,24 +259,28 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
+ /delete-property/dma-names;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
+ /delete-property/dma-names;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ /delete-property/dma-names;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
+ /delete-property/dma-names;
status = "okay";
};
diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
index ef9b4d6..fb661e8 100644
--- a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2014-2020 Toradex
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi
index 05c9a39..607cec2 100644
--- a/arch/arm/boot/dts/vf610-colibri.dtsi
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -1,42 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
- * Copyright 2014 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2014-2020 Toradex
*/
#include "vf610.dtsi"
diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts
index 2873224..96495d9 100644
--- a/arch/arm/boot/dts/vf610-zii-cfu1.dts
+++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts
@@ -71,6 +71,14 @@
los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
};
+
+ supply-voltage-monitor {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 8>, /* 28VDC_IN */
+ <&adc0 9>, /* +3.3V */
+ <&adc1 8>, /* VCC_1V5 */
+ <&adc1 9>; /* VCC_1V2 */
+ };
};
&adc0 {
@@ -150,6 +158,8 @@
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
+ clock-frequency = <12500000>;
+ suppress-preamble;
status = "okay";
switch0: switch0@0 {
@@ -162,7 +172,6 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
- reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
@@ -216,6 +225,7 @@
compatible = "nxp,pca9554";
reg = <0x22>;
gpio-controller;
+ #gpio-cells = <2>;
};
lm75@48 {
@@ -346,7 +356,6 @@
pinctrl_switch: switch-grp {
fsl,pins = <
VF610_PAD_PTB28__GPIO_98 0x3061
- VF610_PAD_PTE2__GPIO_107 0x1042
>;
};
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
index 48086c5..6f1e0f0 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
@@ -323,11 +323,6 @@
};
&i2c0 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>;
- status = "okay";
-
gpio5: io-expander@20 {
compatible = "nxp,pca9554";
reg = <0x20>;
@@ -350,11 +345,6 @@
};
&i2c2 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
tca9548@70 {
compatible = "nxp,pca9548";
pinctrl-0 = <&pinctrl_i2c_mux_reset>;
@@ -416,6 +406,9 @@
};
};
+&mdio1 {
+ clock-frequency = <5000000>;
+};
&iomuxc {
pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
index 778e02c..de79dcf 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
@@ -164,7 +164,7 @@
port@9 {
reg = <9>;
label = "sff2";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff2>;
};
diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi
index a1b4cce..f8299f3 100644
--- a/arch/arm/boot/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi
@@ -84,6 +84,14 @@
regulator-boot-on;
gpio = <&gpio0 6 0>;
};
+
+ supply-voltage-monitor {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 8>, /* VCC_1V5 */
+ <&adc0 9>, /* VCC_1V8 */
+ <&adc1 8>, /* VCC_1V0 */
+ <&adc1 9>; /* VCC_1V2 */
+ };
};
&adc0 {
@@ -129,6 +137,8 @@
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
+ clock-frequency = <12500000>;
+ suppress-preamble;
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
index c8ebb23..040a1f8 100644
--- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
+++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts
@@ -183,15 +183,10 @@
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
- reg = <1>;
- label = "internal_j9";
- };
-
port@2 {
reg = <2>;
label = "eth_fc_1000_2";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff1>;
};
@@ -199,7 +194,7 @@
port@3 {
reg = <3>;
label = "eth_fc_1000_3";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff2>;
};
@@ -207,7 +202,7 @@
port@4 {
reg = <4>;
label = "eth_fc_1000_4";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff3>;
};
@@ -215,7 +210,7 @@
port@5 {
reg = <5>;
label = "eth_fc_1000_5";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff4>;
};
@@ -223,7 +218,7 @@
port@6 {
reg = <6>;
label = "eth_fc_1000_6";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff5>;
};
@@ -231,7 +226,7 @@
port@7 {
reg = <7>;
label = "eth_fc_1000_7";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff6>;
};
@@ -239,7 +234,7 @@
port@9 {
reg = <9>;
label = "eth_fc_1000_1";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff0>;
};
@@ -271,15 +266,10 @@
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
- reg = <1>;
- label = "internal_j8";
- };
-
port@2 {
reg = <2>;
label = "eth_fc_1000_8";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff7>;
};
@@ -287,7 +277,7 @@
port@3 {
reg = <3>;
label = "eth_fc_1000_9";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff8>;
};
@@ -295,7 +285,7 @@
port@4 {
reg = <4>;
label = "eth_fc_1000_10";
- phy-mode = "sgmii";
+ phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sff9>;
};
@@ -417,7 +407,7 @@
pinctrl-0 = <&pinctrl_dspi1>;
status = "okay";
- spi-flash@0 {
+ flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -430,7 +420,7 @@
};
};
- spi-flash@1 {
+ flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
@@ -519,7 +509,7 @@
#gpio-cells = <2>;
};
- lm75@48 {
+ temp-sensor@48 {
compatible = "national,lm75";
reg = <0x48>;
};
@@ -534,7 +524,7 @@
reg = <0x52>;
};
- ds1682@6b {
+ elapsed-time-recorder@6b {
compatible = "dallas,ds1682";
reg = <0x6b>;
};
@@ -546,7 +536,12 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- adt7411@4a {
+ watchdog@38 {
+ compatible = "zii,rave-wdt";
+ reg = <0x38>;
+ };
+
+ adc@4a {
compatible = "adi,adt7411";
reg = <0x4a>;
};
@@ -558,7 +553,7 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
- gpio9: sx1503q@20 {
+ gpio9: io-expander@20 {
compatible = "semtech,sx1503q";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sx1503_20>;
@@ -569,12 +564,12 @@
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
};
- lm75@4e {
+ temp-sensor@4e {
compatible = "national,lm75";
reg = <0x4e>;
};
- lm75@4f {
+ temp-sensor@4f {
compatible = "national,lm75";
reg = <0x4f>;
};
@@ -586,17 +581,17 @@
reg = <0x23>;
};
- adt7411@4a {
+ adc@4a {
compatible = "adi,adt7411";
reg = <0x4a>;
};
- at24c08@54 {
+ eeprom@54 {
compatible = "atmel,24c08";
reg = <0x54>;
};
- tca9548@70 {
+ i2c-mux@70 {
compatible = "nxp,pca9548";
pinctrl-names = "default";
#address-cells = <1>;
@@ -635,7 +630,7 @@
};
};
- tca9548@71 {
+ i2c-mux@71 {
compatible = "nxp,pca9548";
pinctrl-names = "default";
reg = <0x71>;
@@ -689,7 +684,6 @@
linux,rs485-enabled-at-boot-time;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- rs485-rts-delay = <0 200>;
status = "okay";
};
@@ -697,7 +691,6 @@
linux,rs485-enabled-at-boot-time;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
- rs485-rts-delay = <0 200>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts
index 77e1484..6c6ec46 100644
--- a/arch/arm/boot/dts/vf610-zii-spb4.dts
+++ b/arch/arm/boot/dts/vf610-zii-spb4.dts
@@ -42,6 +42,14 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ supply-voltage-monitor {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 8>, /* 28V_SW */
+ <&adc0 9>, /* +3.3V */
+ <&adc1 8>, /* VCC_1V5 */
+ <&adc1 9>; /* VCC_1V2 */
+ };
};
&adc0 {
@@ -111,6 +119,8 @@
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
+ clock-frequency = <12500000>;
+ suppress-preamble;
status = "okay";
switch0: switch0@0 {
@@ -119,7 +129,6 @@
pinctrl-names = "default";
reg = <0>;
eeprom-length = <65536>;
- reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
@@ -199,6 +208,18 @@
};
};
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ watchdog@38 {
+ compatible = "zii,rave-wdt";
+ reg = <0x38>;
+ };
+};
+
&snvsrtc {
status = "disabled";
};
@@ -304,7 +325,6 @@
pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
fsl,pins = <
- VF610_PAD_PTE2__GPIO_107 0x31c2
VF610_PAD_PTB28__GPIO_98 0x219d
>;
};
@@ -316,6 +336,13 @@
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ VF610_PAD_PTB16__I2C1_SCL 0x37ff
+ VF610_PAD_PTB17__I2C1_SDA 0x37ff
+ >;
+ };
+
pinctrl_leds_debug: pinctrl-leds-debug {
fsl,pins = <
VF610_PAD_PTD3__GPIO_82 0x31c2
diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
index 847c585..73fdace 100644
--- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
+++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
@@ -46,6 +46,14 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ supply-voltage-monitor {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 8>, /* 12V_MAIN */
+ <&adc0 9>, /* +3.3V */
+ <&adc1 8>, /* VCC_1V5 */
+ <&adc1 9>; /* VCC_1V2 */
+ };
};
&adc0 {
@@ -73,6 +81,8 @@
non-removable;
no-1-8-v;
keep-power-in-suspend;
+ no-sdio;
+ no-sd;
status = "okay";
};
@@ -80,6 +90,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
bus-width = <4>;
+ no-sdio;
status = "okay";
};
@@ -97,6 +108,8 @@
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
+ clock-frequency = <12500000>;
+ suppress-preamble;
status = "okay";
switch0: switch0@0 {
@@ -105,7 +118,6 @@
pinctrl-names = "default";
reg = <0>;
eeprom-length = <65536>;
- reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
@@ -280,7 +292,6 @@
pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
fsl,pins = <
- VF610_PAD_PTE2__GPIO_107 0x31c2
VF610_PAD_PTB28__GPIO_98 0x219d
>;
};
diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
index 453fce8..fe600ab 100644
--- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
+++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
@@ -46,6 +46,14 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ supply-voltage-monitor {
+ compatible = "iio-hwmon";
+ io-channels = <&adc0 8>, /* 12V_MAIN */
+ <&adc0 9>, /* +3.3V */
+ <&adc1 8>, /* VCC_1V5 */
+ <&adc1 9>; /* VCC_1V2 */
+ };
};
&adc0 {
@@ -125,6 +133,8 @@
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
+ clock-frequency = <12500000>;
+ suppress-preamble;
status = "okay";
switch0: switch0@0 {
@@ -133,7 +143,6 @@
pinctrl-names = "default";
reg = <0>;
eeprom-length = <65536>;
- reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
@@ -218,6 +227,18 @@
};
};
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ watchdog@38 {
+ compatible = "zii,rave-wdt";
+ reg = <0x38>;
+ };
+};
+
&snvsrtc {
status = "disabled";
};
@@ -311,7 +332,6 @@
pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
fsl,pins = <
- VF610_PAD_PTE2__GPIO_107 0x31c2
VF610_PAD_PTB28__GPIO_98 0x219d
>;
};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 7fd3981..956182d 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -10,7 +10,7 @@
};
&aips0 {
- L2: l2-cache@40006000 {
+ L2: cache-controller@40006000 {
compatible = "arm,pl310-cache";
reg = <0x40006000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/vf610m4-colibri.dts
index d4bc0e3..2c2db47 100644
--- a/arch/arm/boot/dts/vf610m4-colibri.dts
+++ b/arch/arm/boot/dts/vf610m4-colibri.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Device tree for Colibri VF61 Cortex-M4 support
*
* Copyright (C) 2015 Stefan Agner
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index fa24806..2259d11 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -59,7 +59,7 @@
interrupt-parent = <&mscm_ir>;
ranges;
- aips0: aips-bus@40000000 {
+ aips0: bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -471,7 +471,7 @@
};
};
- aips1: aips-bus@40080000 {
+ aips1: bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -729,6 +729,28 @@
dma-names = "rx","tx";
status = "disabled";
};
+
+ crypto: crypto@400f0000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x400f0000 0x9000>;
+ ranges = <0 0x400f0000 0x9000>;
+ clocks = <&clks VF610_CLK_CAAM>;
+ clock-names = "ipg";
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
};
};
};
diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi
index afd98de..f378c66 100644
--- a/arch/arm/boot/dts/zx296702.dtsi
+++ b/arch/arm/boot/dts/zx296702.dtsi
@@ -58,7 +58,7 @@
clocks = <&topclk ZX296702_A9_PERIPHCLK>;
};
- l2cc: l2-cache-controller@c00000 {
+ l2cc: cache-controller@c00000 {
compatible = "arm,pl310-cache";
reg = <0x00c00000 0x1000>;
cache-unified;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index ca6425a..db3899b 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -59,6 +59,39 @@
regulator-always-on;
};
+ replicator {
+ compatible = "arm,coresight-static-replicator";
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port@0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&etb_in_port>;
+ };
+ };
+ };
+ in-ports {
+ /* replicator input port */
+ port {
+ replicator_in_port0: endpoint {
+ remote-endpoint = <&funnel_out_port>;
+ };
+ };
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <1>;
@@ -365,5 +398,107 @@
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
+
+ etb@f8801000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0xf8801000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ etb_in_port: endpoint {
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+ };
+
+ tpiu@f8803000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0xf8803000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ in-ports {
+ port {
+ tpiu_in_port: endpoint {
+ remote-endpoint = <&replicator_out_port0>;
+ };
+ };
+ };
+ };
+
+ funnel@f8804000 {
+ compatible = "arm,coresight-static-funnel", "arm,primecell";
+ reg = <0xf8804000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+
+ /* funnel output ports */
+ out-ports {
+ port {
+ funnel_out_port: endpoint {
+ remote-endpoint =
+ <&replicator_in_port0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel input ports */
+ port@0 {
+ reg = <0>;
+ funnel0_in_port0: endpoint {
+ remote-endpoint = <&ptm0_out_port>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel0_in_port1: endpoint {
+ remote-endpoint = <&ptm1_out_port>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel0_in_port2: endpoint {
+ };
+ };
+ /* The other input ports are not connect to anything */
+ };
+ };
+
+ ptm@f889c000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0xf889c000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ cpu = <&cpu0>;
+ out-ports {
+ port {
+ ptm0_out_port: endpoint {
+ remote-endpoint = <&funnel0_in_port0>;
+ };
+ };
+ };
+ };
+
+ ptm@f889d000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0xf889d000 0x1000>;
+ clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
+ clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
+ cpu = <&cpu1>;
+ out-ports {
+ port {
+ ptm1_out_port: endpoint {
+ remote-endpoint = <&funnel0_in_port1>;
+ };
+ };
+ };
+ };
};
};
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 219a260..8cd574b 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -12,7 +12,6 @@
obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
obj-$(CONFIG_CPU_V7) += secure_cntvoff.o
-obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
CFLAGS_REMOVE_mcpm_entry.o = -pg
AFLAGS_mcpm_head.o := -march=armv7-a
diff --git a/arch/arm/common/bL_switcher.c b/arch/arm/common/bL_switcher.c
index 746e1fc..9a9aa53 100644
--- a/arch/arm/common/bL_switcher.c
+++ b/arch/arm/common/bL_switcher.c
@@ -270,12 +270,11 @@
static int bL_switcher_thread(void *arg)
{
struct bL_thread *t = arg;
- struct sched_param param = { .sched_priority = 1 };
int cluster;
bL_switch_completion_handler completer;
void *completer_cookie;
- sched_setscheduler_nocheck(current, SCHED_FIFO, ¶m);
+ sched_set_fifo_low(current);
complete(&t->started);
do {
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index f4b719b..7996c04 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -24,7 +24,8 @@
#include <linux/slab.h>
#include <linux/page-flags.h>
#include <linux/device.h>
-#include <linux/dma-mapping.h>
+#include <linux/dma-direct.h>
+#include <linux/dma-map-ops.h>
#include <linux/dmapool.h>
#include <linux/list.h>
#include <linux/scatterlist.h>
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
deleted file mode 100644
index 9ec740c..0000000
--- a/arch/arm/common/it8152.c
+++ /dev/null
@@ -1,352 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/common/it8152.c
- *
- * Copyright Compulab Ltd, 2002-2007
- * Mike Rapoport <mike@compulab.co.il>
- *
- * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
- * (see this file for respective copyrights)
- *
- * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
- * and demux code.
- */
-
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/ptrace.h>
-#include <linux/interrupt.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/export.h>
-
-#include <asm/mach/pci.h>
-#include <asm/hardware/it8152.h>
-
-#define MAX_SLOTS 21
-
-static void it8152_mask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
- if (irq >= IT8152_LD_IRQ(0)) {
- __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
- (1 << (irq - IT8152_LD_IRQ(0)))),
- IT8152_INTC_LDCNIMR);
- } else if (irq >= IT8152_LP_IRQ(0)) {
- __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
- (1 << (irq - IT8152_LP_IRQ(0)))),
- IT8152_INTC_LPCNIMR);
- } else if (irq >= IT8152_PD_IRQ(0)) {
- __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
- (1 << (irq - IT8152_PD_IRQ(0)))),
- IT8152_INTC_PDCNIMR);
- }
-}
-
-static void it8152_unmask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
- if (irq >= IT8152_LD_IRQ(0)) {
- __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
- ~(1 << (irq - IT8152_LD_IRQ(0)))),
- IT8152_INTC_LDCNIMR);
- } else if (irq >= IT8152_LP_IRQ(0)) {
- __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
- ~(1 << (irq - IT8152_LP_IRQ(0)))),
- IT8152_INTC_LPCNIMR);
- } else if (irq >= IT8152_PD_IRQ(0)) {
- __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
- ~(1 << (irq - IT8152_PD_IRQ(0)))),
- IT8152_INTC_PDCNIMR);
- }
-}
-
-static struct irq_chip it8152_irq_chip = {
- .name = "it8152",
- .irq_ack = it8152_mask_irq,
- .irq_mask = it8152_mask_irq,
- .irq_unmask = it8152_unmask_irq,
-};
-
-void it8152_init_irq(void)
-{
- int irq;
-
- __raw_writel((0xffff), IT8152_INTC_PDCNIMR);
- __raw_writel((0), IT8152_INTC_PDCNIRR);
- __raw_writel((0xffff), IT8152_INTC_LPCNIMR);
- __raw_writel((0), IT8152_INTC_LPCNIRR);
- __raw_writel((0xffff), IT8152_INTC_LDCNIMR);
- __raw_writel((0), IT8152_INTC_LDCNIRR);
-
- for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
- irq_set_chip_and_handler(irq, &it8152_irq_chip,
- handle_level_irq);
- irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
- }
-}
-
-void it8152_irq_demux(struct irq_desc *desc)
-{
- int bits_pd, bits_lp, bits_ld;
- int i;
-
- while (1) {
- /* Read all */
- bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
- bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
- bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
-
- /* Ack */
- __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
- __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
- __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
-
- if (!(bits_ld | bits_lp | bits_pd)) {
- /* Re-read to guarantee, that there was a moment of
- time, when they all three were 0. */
- bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
- bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
- bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
- if (!(bits_ld | bits_lp | bits_pd))
- return;
- }
-
- bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
- while (bits_pd) {
- i = __ffs(bits_pd);
- generic_handle_irq(IT8152_PD_IRQ(i));
- bits_pd &= ~(1 << i);
- }
-
- bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
- while (bits_lp) {
- i = __ffs(bits_lp);
- generic_handle_irq(IT8152_LP_IRQ(i));
- bits_lp &= ~(1 << i);
- }
-
- bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
- while (bits_ld) {
- i = __ffs(bits_ld);
- generic_handle_irq(IT8152_LD_IRQ(i));
- bits_ld &= ~(1 << i);
- }
- }
-}
-
-/* mapping for on-chip devices */
-int __init it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
- (dev->device == PCI_DEVICE_ID_ITE_8152)) {
- if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
- return IT8152_AUDIO_INT;
- if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
- return IT8152_USB_INT;
- if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
- return IT8152_CDMA_INT;
- }
-
- return 0;
-}
-
-static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
- unsigned int devfn)
-{
- unsigned long addr = 0;
-
- if (bus->number == 0) {
- if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
- addr = (devfn << 8);
- } else
- addr = (bus->number << 16) | (devfn << 8);
-
- return addr;
-}
-
-static int it8152_pci_read_config(struct pci_bus *bus,
- unsigned int devfn, int where,
- int size, u32 *value)
-{
- unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
- u32 v;
- int shift;
-
- shift = (where & 3);
-
- __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
- v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift)));
-
- *value = v;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int it8152_pci_write_config(struct pci_bus *bus,
- unsigned int devfn, int where,
- int size, u32 value)
-{
- unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
- u32 v, vtemp, mask = 0;
- int shift;
-
- if (size == 1)
- mask = 0xff;
- if (size == 2)
- mask = 0xffff;
-
- shift = (where & 3);
-
- __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
- vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
-
- if (mask)
- vtemp &= ~(mask << (8 * shift));
- else
- vtemp = 0;
-
- v = (value << (8 * shift));
- __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
- __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops it8152_ops = {
- .read = it8152_pci_read_config,
- .write = it8152_pci_write_config,
-};
-
-static struct resource it8152_io = {
- .name = "IT8152 PCI I/O region",
- .flags = IORESOURCE_IO,
-};
-
-static struct resource it8152_mem = {
- .name = "IT8152 PCI memory region",
- .start = 0x10000000,
- .end = 0x13e00000,
- .flags = IORESOURCE_MEM,
-};
-
-/*
- * The following functions are needed for DMA bouncing.
- * ITE8152 chip can address up to 64MByte, so all the devices
- * connected to ITE8152 (PCI and USB) should have limited DMA window
- */
-static int it8152_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
-{
- dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
- __func__, dma_addr, size);
- return (dma_addr + size - PHYS_OFFSET) >= SZ_64M;
-}
-
-/*
- * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
- * other devices.
- */
-static int it8152_pci_platform_notify(struct device *dev)
-{
- if (dev_is_pci(dev)) {
- if (dev->dma_mask)
- *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
- dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
- dmabounce_register_dev(dev, 2048, 4096, it8152_needs_bounce);
- }
- return 0;
-}
-
-static int it8152_pci_platform_notify_remove(struct device *dev)
-{
- if (dev_is_pci(dev))
- dmabounce_unregister_dev(dev);
-
- return 0;
-}
-
-int dma_set_coherent_mask(struct device *dev, u64 mask)
-{
- if (mask >= PHYS_OFFSET + SZ_64M - 1)
- return 0;
-
- return -EIO;
-}
-
-int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
-{
- /*
- * FIXME: use pci_ioremap_io to remap the IO space here and
- * move over to the generic io.h implementation.
- * This requires solving the same problem for PXA PCMCIA
- * support.
- */
- it8152_io.start = (unsigned long)IT8152_IO_BASE + 0x12000;
- it8152_io.end = (unsigned long)IT8152_IO_BASE + 0x12000 + 0x100000;
-
- sys->mem_offset = 0x10000000;
- sys->io_offset = (unsigned long)IT8152_IO_BASE;
-
- if (request_resource(&ioport_resource, &it8152_io)) {
- printk(KERN_ERR "PCI: unable to allocate IO region\n");
- goto err0;
- }
- if (request_resource(&iomem_resource, &it8152_mem)) {
- printk(KERN_ERR "PCI: unable to allocate memory region\n");
- goto err1;
- }
-
- pci_add_resource_offset(&sys->resources, &it8152_io, sys->io_offset);
- pci_add_resource_offset(&sys->resources, &it8152_mem, sys->mem_offset);
-
- if (platform_notify || platform_notify_remove) {
- printk(KERN_ERR "PCI: Can't use platform_notify\n");
- goto err2;
- }
-
- platform_notify = it8152_pci_platform_notify;
- platform_notify_remove = it8152_pci_platform_notify_remove;
-
- return 1;
-
-err2:
- release_resource(&it8152_io);
-err1:
- release_resource(&it8152_mem);
-err0:
- return -EBUSY;
-}
-
-/* ITE bridge requires setting latency timer to avoid early bus access
- termination by PCI bus master devices
-*/
-void pcibios_set_master(struct pci_dev *dev)
-{
- u8 lat;
-
- /* no need to update on-chip OHCI controller */
- if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
- (dev->device == PCI_DEVICE_ID_ITE_8152) &&
- ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
- return;
-
- pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
- if (lat < 16)
- lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
- else if (lat > pcibios_max_latency)
- lat = pcibios_max_latency;
- else
- return;
- printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
- pci_name(dev), lat);
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
-}
-
-
-EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 947ef79..f89c1ea 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -22,7 +22,7 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
-#include <linux/dma-mapping.h>
+#include <linux/dma-map-ops.h>
#include <linux/clk.h>
#include <linux/io.h>
@@ -302,10 +302,13 @@
break;
}
- if (i == 8)
+ if (i == 8) {
pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n",
d->irq);
- return i == 8 ? -1 : 0;
+ return 0;
+ }
+
+ return 1;
}
static int sa1111_type_irq(struct irq_data *d, unsigned int flags)
diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig
index 622436f..4e49d6c 100644
--- a/arch/arm/configs/am200epdkit_defconfig
+++ b/arch/arm/configs/am200epdkit_defconfig
@@ -3,7 +3,6 @@
CONFIG_SYSVIPC=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_EPOLL is not set
# CONFIG_SHMEM is not set
# CONFIG_VM_EVENT_COUNTERS is not set
@@ -11,8 +10,6 @@
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_PXA=y
CONFIG_ARCH_GUMSTIX=y
CONFIG_PCCARD=y
diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig
index 1857df9..58d293b 100644
--- a/arch/arm/configs/aspeed_g4_defconfig
+++ b/arch/arm/configs/aspeed_g4_defconfig
@@ -132,10 +132,12 @@
CONFIG_HW_RANDOM_TIMERIOMEM=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA9541=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_ASPEED=y
CONFIG_I2C_FSI=y
+CONFIG_SPI=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_ASPEED=y
@@ -158,7 +160,8 @@
CONFIG_SENSORS_W83773G=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ASPEED=y
CONFIG_DRM=y
@@ -185,6 +188,12 @@
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_MMC=y
+# CONFIG_PWRSEQ_EMMC is not set
+# CONFIG_PWRSEQ_SIMPLE is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ASPEED=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
@@ -216,7 +225,6 @@
CONFIG_FSI_MASTER_HUB=y
CONFIG_FSI_MASTER_AST_CF=y
CONFIG_FSI_SCOM=y
-CONFIG_FSI_SBEFIFO=y
CONFIG_FANOTIFY=y
CONFIG_OVERLAY_FS=y
CONFIG_TMPFS=y
@@ -231,7 +239,6 @@
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_HARDENED_USERCOPY=y
CONFIG_FORTIFY_SOURCE=y
-# CONFIG_CRYPTO_ECHAINIV is not set
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_USER_API_HASH=y
@@ -247,14 +254,14 @@
CONFIG_DEBUG_INFO_DWARF4=y
CONFIG_GDB_SCRIPTS=y
CONFIG_STRIP_ASM_SYMS=y
+CONFIG_SCHED_STACK_END_CHECK=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_TIMEOUT=-1
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_DETECT_HUNG_TASK is not set
CONFIG_WQ_WATCHDOG=y
-CONFIG_PANIC_ON_OOPS=y
-CONFIG_PANIC_TIMEOUT=-1
# CONFIG_SCHED_DEBUG is not set
-CONFIG_SCHED_STACK_END_CHECK=y
CONFIG_FUNCTION_TRACER=y
-# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_DEBUG_WX=y
CONFIG_DEBUG_USER=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
diff --git a/arch/arm/configs/aspeed_g5_defconfig b/arch/arm/configs/aspeed_g5_defconfig
index b87508c..047975e 100644
--- a/arch/arm/configs/aspeed_g5_defconfig
+++ b/arch/arm/configs/aspeed_g5_defconfig
@@ -128,6 +128,8 @@
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_GPIO_POLLED=y
# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_IBM_PANEL=y
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
@@ -147,14 +149,17 @@
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
CONFIG_I2C_MUX_PCA9541=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_ASPEED=y
CONFIG_I2C_FSI=y
+CONFIG_I2C_SLAVE=y
CONFIG_SPI=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_ASPEED=y
+CONFIG_GPIO_ASPEED_SGPIO=y
CONFIG_W1=y
CONFIG_W1_MASTER_GPIO=y
CONFIG_W1_SLAVE_THERM=y
@@ -174,7 +179,8 @@
CONFIG_SENSORS_W83773G=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ASPEED=y
CONFIG_DRM=y
@@ -237,8 +243,10 @@
CONFIG_FSI_MASTER_GPIO=y
CONFIG_FSI_MASTER_HUB=y
CONFIG_FSI_MASTER_AST_CF=y
+CONFIG_FSI_MASTER_ASPEED=y
CONFIG_FSI_SCOM=y
CONFIG_FSI_SBEFIFO=y
+CONFIG_FSI_OCC=y
CONFIG_FANOTIFY=y
CONFIG_OVERLAY_FS=y
CONFIG_TMPFS=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 309c55a..4a0ba2a 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -7,17 +7,14 @@
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MULTI_V4T=y
CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_AT91=y
CONFIG_SOC_AT91RM9200=y
CONFIG_SOC_AT91SAM9=y
+CONFIG_SOC_SAM9X60=y
+# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
CONFIG_AEABI=y
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -26,6 +23,9 @@
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
CONFIG_KEXEC=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
@@ -36,13 +36,7 @@
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
CONFIG_IPV6_SIT_6RD=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
@@ -56,6 +50,7 @@
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_BLK_DEV_LOOP=y
@@ -68,8 +63,8 @@
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
-CONFIG_MACB=y
# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_MACB=y
CONFIG_DM9000=y
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
@@ -81,10 +76,12 @@
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_DAVICOM_PHY=y
CONFIG_MICREL_PHY=y
-CONFIG_RTL8187=m
CONFIG_LIBERTAS=m
CONFIG_LIBERTAS_SDIO=m
CONFIG_LIBERTAS_SPI=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
CONFIG_RT2X00=m
CONFIG_RT2500USB=m
CONFIG_RT73USB=m
@@ -92,15 +89,10 @@
CONFIG_RT2800USB_RT53XX=y
CONFIG_RT2800USB_RT55XX=y
CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RTL8187=m
CONFIG_RTL8192CU=m
# CONFIG_RTLWIFI_DEBUG is not set
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_MWIFIEX_USB=m
CONFIG_INPUT_POLLDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
@@ -109,6 +101,7 @@
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
# CONFIG_SERIO is not set
CONFIG_LEGACY_PTY_COUNT=4
CONFIG_SERIAL_ATMEL=y
@@ -118,25 +111,26 @@
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_ATMEL=y
-CONFIG_POWER_SUPPLY=y
+CONFIG_SPI_ATMEL_QUADSPI=y
CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC is not set
+CONFIG_POWER_SUPPLY=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_AT91SAM9X_WATCHDOG=y
+CONFIG_SAMA5D4_WATCHDOG=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
CONFIG_MFD_ATMEL_HLCDC=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_SOC_CAMERA=y
CONFIG_VIDEO_ATMEL_ISI=y
-CONFIG_SOC_CAMERA_OV2640=m
CONFIG_DRM=y
CONFIG_DRM_ATMEL_HLCDC=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_FB_ATMEL=y
-# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_ATMEL_LCDC=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
@@ -149,6 +143,9 @@
CONFIG_SND_AT91_SOC_SAM9G20_WM8731=y
CONFIG_SND_ATMEL_SOC_WM8904=y
CONFIG_SND_AT91_SOC_SAM9X5_WM8731=y
+CONFIG_SND_ATMEL_SOC_CLASSD=y
+CONFIG_SND_SOC_MIKROE_PROTO=m
+CONFIG_SND_MCHP_SOC_I2S_MCC=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_EHCI_HCD=y
@@ -164,6 +161,9 @@
CONFIG_USB_ATMEL_USBA=y
CONFIG_USB_G_SERIAL=y
CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_AT91=y
CONFIG_MMC_ATMELMCI=y
CONFIG_MMC_SPI=y
CONFIG_NEW_LEDS=y
@@ -180,9 +180,12 @@
CONFIG_RTC_DRV_AT91SAM9=y
CONFIG_DMADEVICES=y
CONFIG_AT_HDMAC=y
+CONFIG_AT_XDMAC=y
+CONFIG_MICROCHIP_PIT64B=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_IIO=y
CONFIG_AT91_ADC=y
+CONFIG_AT91_SAMA5D2_ADC=y
CONFIG_PWM=y
CONFIG_PWM_ATMEL=y
CONFIG_PWM_ATMEL_HLCDC_PWM=y
@@ -199,12 +202,6 @@
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_FS=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_USER=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
@@ -214,3 +211,9 @@
CONFIG_FONT_8x8=y
CONFIG_FONT_ACORN_8x8=y
CONFIG_FONT_MINI_4x6=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/axm55xx_defconfig b/arch/arm/configs/axm55xx_defconfig
index 31bfe16..4607521 100644
--- a/arch/arm/configs/axm55xx_defconfig
+++ b/arch/arm/configs/axm55xx_defconfig
@@ -20,13 +20,11 @@
CONFIG_SCHED_AUTOGROUP=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ARCH_AXXIA=y
CONFIG_GPIO_PCA953X=y
CONFIG_ARM_LPAE=y
@@ -238,5 +236,3 @@
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_VIRTUALIZATION=y
-CONFIG_KVM=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index 519ff58..44ff9cd 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -72,6 +72,7 @@
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_NETDEVICES=y
+CONFIG_BCMGENET=y
CONFIG_USB_LAN78XX=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC95XX=y
@@ -96,9 +97,14 @@
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_RASPBERRYPI_HWMON=m
CONFIG_THERMAL=y
+CONFIG_BCM2711_THERMAL=y
CONFIG_BCM2835_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_BCM2835_WDT=y
+CONFIG_MFD_SYSCON=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_DRM=y
@@ -178,6 +184,7 @@
CONFIG_STACK_TRACER=y
CONFIG_FUNCTION_PROFILER=y
CONFIG_TEST_KSTRTOX=y
+CONFIG_DEBUG_FS=y
CONFIG_KGDB=y
CONFIG_KGDB_KDB=y
CONFIG_STRICT_DEVMEM=y
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index c255dab..63a153f 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -7,7 +7,6 @@
CONFIG_SLOB=y
CONFIG_JUMP_LABEL=y
CONFIG_PARTITION_ADVANCED=y
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_CLPS711X=y
CONFIG_ARCH_AUTCPU12=y
CONFIG_ARCH_CDB89712=y
diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig
deleted file mode 100644
index fa997ae..0000000
--- a/arch/arm/configs/cm_x2xx_defconfig
+++ /dev/null
@@ -1,173 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_ARMCORE=y
-CONFIG_PCI=y
-CONFIG_PCCARD=m
-CONFIG_YENTA=m
-# CONFIG_YENTA_O2 is not set
-# CONFIG_YENTA_RICOH is not set
-# CONFIG_YENTA_ENE_TUNE is not set
-# CONFIG_YENTA_TOSHIBA is not set
-CONFIG_PCMCIA_PXA2XX=m
-CONFIG_NO_HZ=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=1f03 mem=32M"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_APM_EMULATION=m
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_BNEP=m
-CONFIG_BT_HIDP=m
-CONFIG_LIB80211=m
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PXA2XX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_GPIO=m
-CONFIG_MTD_NAND_CM_X270=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_ATA=m
-# CONFIG_SATA_PMP is not set
-CONFIG_PATA_PCMCIA=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-CONFIG_DM9000_DEBUGLEVEL=1
-CONFIG_NET_PCI=y
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_PXA27x=m
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_UCB1400=m
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=16
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_PXA=y
-CONFIG_SPI=y
-CONFIG_SPI_PXA2XX=m
-# CONFIG_HWMON is not set
-CONFIG_UCB1400_CORE=m
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-CONFIG_FB_PXA_PARAMETERS=y
-CONFIG_FB_MBX=m
-# CONFIG_LCD_CLASS_DEVICE is not set
-# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_PCI is not set
-CONFIG_SND_PXA2XX_AC97=m
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-# CONFIG_SND_PCMCIA is not set
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=m
-CONFIG_MMC_PXA=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_V3020=y
-CONFIG_RTC_DRV_PXA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_VFAT_FS=m
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_FRAME_WARN=0
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig
index 89df0a5..66a80b4 100644
--- a/arch/arm/configs/cns3420vb_defconfig
+++ b/arch/arm/configs/cns3420vb_defconfig
@@ -17,7 +17,7 @@
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
-CONFIG_IOSCHED_CFQ=m
+CONFIG_IOSCHED_BFQ=m
CONFIG_ARCH_MULTI_V6=y
#CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_CNS3XXX=y
diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig
index 446134c..0dae3b1 100644
--- a/arch/arm/configs/colibri_pxa300_defconfig
+++ b/arch/arm/configs/colibri_pxa300_defconfig
@@ -43,7 +43,6 @@
CONFIG_USB_MON=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_PXA=y
CONFIG_EXT3_FS=y
CONFIG_NFS_FS=y
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index e6df11e..36384fd 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -7,8 +7,6 @@
# CONFIG_BASE_FULL is not set
# CONFIG_EPOLL is not set
CONFIG_SLOB=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SA1100=y
CONFIG_SA1100_COLLIE=y
CONFIG_PCCARD=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 231f897..e849367 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -15,8 +15,6 @@
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V7=n
CONFIG_ARCH_MULTI_V5=y
@@ -160,7 +158,7 @@
CONFIG_VIDEO_ADV7343=m
CONFIG_DRM=m
CONFIG_DRM_TILCDC=m
-CONFIG_DRM_DUMB_VGA_DAC=m
+CONFIG_DRM_SIMPLE_BRIDGE=m
CONFIG_DRM_TINYDRM=m
CONFIG_TINYDRM_ST7586=m
CONFIG_FB=y
diff --git a/arch/arm/configs/efm32_defconfig b/arch/arm/configs/efm32_defconfig
index 10ea925..46213f0 100644
--- a/arch/arm/configs/efm32_defconfig
+++ b/arch/arm/configs/efm32_defconfig
@@ -12,8 +12,6 @@
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
# CONFIG_MMU is not set
CONFIG_ARM_SINGLE_ARMV7M=y
CONFIG_ARCH_EFM32=y
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig
deleted file mode 100644
index d08f020..0000000
--- a/arch/arm/configs/em_x270_defconfig
+++ /dev/null
@@ -1,178 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_PXA=y
-CONFIG_MACH_EM_X270=y
-CONFIG_MACH_EXEDA=y
-CONFIG_NO_HZ=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=1f03 mem=32M"
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_APM_EMULATION=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_BT=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_BNEP=m
-CONFIG_BT_HIDP=m
-CONFIG_BT_HCIBTUSB=m
-CONFIG_LIB80211=m
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PXA2XX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-CONFIG_DM9000_DEBUGLEVEL=1
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_APMPOWER=y
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_PXA27x=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_DA9034 is not set
-CONFIG_TOUCHSCREEN_WM97XX=m
-# CONFIG_TOUCHSCREEN_WM9705 is not set
-# CONFIG_TOUCHSCREEN_WM9713 is not set
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=16
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_PXA=y
-CONFIG_SPI=y
-CONFIG_SPI_PXA2XX=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_BATTERY_DA9030=y
-# CONFIG_HWMON is not set
-CONFIG_PMIC_DA903X=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DA903X=y
-CONFIG_FB=y
-CONFIG_FB_PXA=y
-CONFIG_FB_PXA_PARAMETERS=y
-CONFIG_FB_MBX=m
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_TDO24M=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_DA903X=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=m
-CONFIG_SND_PXA2XX_SOC=m
-CONFIG_SND_PXA2XX_SOC_EM_X270=m
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=m
-CONFIG_MMC_PXA=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_DA903X=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_V3020=y
-CONFIG_RTC_DRV_PXA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_VFAT_FS=m
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_FRAME_WARN=0
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index ef2d2a8..cd16fb6 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -11,7 +11,6 @@
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_EP93XX=y
CONFIG_CRUNCH=y
CONFIG_MACH_ADSSPHERE=y
diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig
index 56452fa..046f4dc 100644
--- a/arch/arm/configs/eseries_pxa_defconfig
+++ b/arch/arm/configs/eseries_pxa_defconfig
@@ -9,8 +9,6 @@
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_PXA=y
CONFIG_ARCH_PXA_ESERIES=y
# CONFIG_ARM_THUMB is not set
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 34d4acb..cf82c9d 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -8,6 +8,7 @@
CONFIG_ARCH_EXYNOS=y
CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y
CONFIG_SMP=y
+CONFIG_SCHED_MC=y
CONFIG_BIG_LITTLE=y
CONFIG_NR_CPUS=8
CONFIG_HIGHMEM=y
@@ -17,6 +18,7 @@
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
+CONFIG_ENERGY_MODEL=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
@@ -67,6 +69,7 @@
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_ATH3K=y
CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_AG6XX=y
CONFIG_BT_HCIUART_MRVL=y
CONFIG_BT_HCIBCM203X=m
@@ -76,8 +79,8 @@
CONFIG_BT_MRVL=m
CONFIG_BT_MRVL_SDIO=m
CONFIG_BT_ATH3K=m
-CONFIG_CFG80211=y
-CONFIG_MAC80211=y
+CONFIG_CFG80211=m
+CONFIG_MAC80211=m
CONFIG_MAC80211_LEDS=y
CONFIG_NFC=y
CONFIG_NFC_DIGITAL=m
@@ -92,7 +95,7 @@
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
@@ -111,11 +114,13 @@
CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC75XX=y
CONFIG_USB_NET_SMSC95XX=y
+CONFIG_BRCMFMAC=m
CONFIG_MWIFIEX=m
CONFIG_MWIFIEX_SDIO=m
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_SAMSUNG=y
+CONFIG_KEYBOARD_TM2_TOUCHKEY=y
CONFIG_KEYBOARD_CROS_EC=y
# CONFIG_MOUSE_PS2 is not set
CONFIG_MOUSE_CYAPA=y
@@ -129,6 +134,7 @@
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
CONFIG_HW_RANDOM=y
CONFIG_TCG_TPM=y
CONFIG_TCG_TIS_I2C_INFINEON=y
@@ -156,10 +162,13 @@
CONFIG_SENSORS_PWM_FAN=y
CONFIG_SENSORS_INA2XX=y
CONFIG_CPU_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_S3C2410_WATCHDOG=y
-CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_DEV=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CROS_EC=y
CONFIG_MFD_MAX14577=y
CONFIG_MFD_MAX77686=y
CONFIG_MFD_MAX77693=y
@@ -182,11 +191,14 @@
CONFIG_REGULATOR_S5M8767=y
CONFIG_REGULATOR_TPS65090=y
CONFIG_REGULATOR_WM8994=y
-CONFIG_MEDIA_SUPPORT=m
-CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_CEC_SUPPORT=y
+CONFIG_CEC_SAMSUNG_S5P=m
+CONFIG_MEDIA_SUPPORT=m
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
@@ -201,8 +213,8 @@
CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
CONFIG_V4L_TEST_DRIVERS=y
CONFIG_VIDEO_VIVID=m
-CONFIG_CEC_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_SAMSUNG_S5P_CEC=m
+CONFIG_VIDEO_S5K6A3=m
+CONFIG_VIDEO_S5C73M3=m
CONFIG_DRM=y
CONFIG_DRM_EXYNOS=y
CONFIG_DRM_EXYNOS_FIMD=y
@@ -232,6 +244,7 @@
CONFIG_SND_SOC_SMDK_WM8994_PCM=y
CONFIG_SND_SOC_SNOW=y
CONFIG_SND_SOC_ODROID=y
+CONFIG_SND_SOC_ARNDALE=y
CONFIG_SND_SIMPLE_CARD=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
@@ -274,6 +287,7 @@
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=y
+CONFIG_LEDS_AAT1290=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_MAX77693=y
@@ -297,6 +311,7 @@
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y
+CONFIG_EXYNOS5422_DMC=y
CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y
CONFIG_EXTCON=y
CONFIG_EXTCON_MAX14577=y
@@ -317,9 +332,12 @@
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CRAMFS=y
+CONFIG_SQUASHFS=y
CONFIG_ROMFS_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
index 4e28771..81665b7 100644
--- a/arch/arm/configs/ezx_defconfig
+++ b/arch/arm/configs/ezx_defconfig
@@ -14,7 +14,6 @@
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_PXA=y
CONFIG_PXA_EZX=y
CONFIG_NO_HZ=y
@@ -237,8 +236,6 @@
# CONFIG_MEDIA_TUNER_MXL5007T is not set
# CONFIG_MEDIA_TUNER_MC44S803 is not set
# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_MT9M111=y
CONFIG_VIDEO_PXA27x=y
# CONFIG_V4L_USB_DRIVERS is not set
CONFIG_RADIO_TEA5764=y
diff --git a/arch/arm/configs/gemini_defconfig b/arch/arm/configs/gemini_defconfig
index f012e81..d2d5f1c 100644
--- a/arch/arm/configs/gemini_defconfig
+++ b/arch/arm/configs/gemini_defconfig
@@ -2,28 +2,36 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_USER_NS=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_MULTI_V4=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_GEMINI=y
-CONFIG_PCI=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
-CONFIG_CMA=y
CONFIG_CMDLINE="console=ttyS0,115200n8"
CONFIG_KEXEC=y
-CONFIG_BINFMT_MISC=y
CONFIG_PM=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BINFMT_MISC=y
+CONFIG_CMA=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_INET=y
+CONFIG_BRIDGE=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_NET_DSA=y
+CONFIG_VLAN_8021Q=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+CONFIG_PCI=y
CONFIG_DEVTMPFS=y
CONFIG_MTD=y
+CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
@@ -40,10 +48,12 @@
CONFIG_ATA=y
CONFIG_PATA_FTIDE010=y
CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_NET_DSA_REALTEK_SMI=y
CONFIG_GEMINI_ETHERNET=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_GPIO=y
-CONFIG_REALTEK_PHY=y
+CONFIG_MARVELL_PHY=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
@@ -69,7 +79,9 @@
CONFIG_LOGO=y
CONFIG_USB=y
CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
CONFIG_USB_FOTG210_HCD=y
+CONFIG_USB_UHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
index 4d91e41..c02b3e4 100644
--- a/arch/arm/configs/h3600_defconfig
+++ b/arch/arm/configs/h3600_defconfig
@@ -5,8 +5,6 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SA1100=y
CONFIG_SA1100_H3600=y
CONFIG_PCCARD=y
diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig
index 3946c60..f5a338f 100644
--- a/arch/arm/configs/h5000_defconfig
+++ b/arch/arm/configs/h5000_defconfig
@@ -10,7 +10,6 @@
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_PXA=y
CONFIG_MACH_H5000=y
CONFIG_AEABI=y
diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
index 770469f..ae15a2a 100644
--- a/arch/arm/configs/imote2_defconfig
+++ b/arch/arm/configs/imote2_defconfig
@@ -13,7 +13,6 @@
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_PXA=y
CONFIG_MACH_INTELMOTE2=y
CONFIG_NO_HZ=y
@@ -218,8 +217,6 @@
# CONFIG_MEDIA_TUNER_MXL5007T is not set
# CONFIG_MEDIA_TUNER_MC44S803 is not set
# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_MT9M111=y
CONFIG_VIDEO_PXA27x=y
# CONFIG_V4L_USB_DRIVERS is not set
# CONFIG_RADIO_ADAPTERS is not set
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 2b2d617..bb70acc 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -20,9 +20,9 @@
CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_IMX27_VISSTRIM_M10=y
CONFIG_MACH_PCA100=y
-CONFIG_MACH_IMX27_DT=y
CONFIG_SOC_IMX1=y
CONFIG_SOC_IMX25=y
+CONFIG_SOC_IMX27=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
@@ -32,8 +32,6 @@
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -95,6 +93,7 @@
CONFIG_SPI_IMX=y
CONFIG_SPI_SPIDEV=y
CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_MXC=y
CONFIG_W1=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_SLAVE_THERM=y
@@ -112,7 +111,6 @@
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_SOC_CAMERA=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_CODA=y
CONFIG_FB=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index dabb804..221f5c3 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -15,20 +15,8 @@
# CONFIG_COMPAT_BRK is not set
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_MXC=y
-CONFIG_MACH_MX31LILLY=y
-CONFIG_MACH_MX31LITE=y
-CONFIG_MACH_PCM037=y
-CONFIG_MACH_PCM037_EET=y
-CONFIG_MACH_MX31_3DS=y
-CONFIG_MACH_MX31MOBOARD=y
-CONFIG_MACH_QONG=y
-CONFIG_MACH_ARMADILLO5X0=y
-CONFIG_MACH_KZM_ARM11_01=y
-CONFIG_MACH_IMX31_DT=y
-CONFIG_MACH_IMX35_DT=y
-CONFIG_MACH_PCM043=y
-CONFIG_MACH_MX35_3DS=y
-CONFIG_MACH_VPR200=y
+CONFIG_SOC_IMX31=y
+CONFIG_SOC_IMX35=y
CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX51=y
CONFIG_SOC_IMX53=y
@@ -179,8 +167,13 @@
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
+CONFIG_TOUCHSCREEN_AD7879=y
+CONFIG_TOUCHSCREEN_AD7879_I2C=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_DA9052=y
CONFIG_TOUCHSCREEN_EGALAX=y
CONFIG_TOUCHSCREEN_GOODIX=y
+CONFIG_TOUCHSCREEN_ILI210X=y
CONFIG_TOUCHSCREEN_MAX11801=y
CONFIG_TOUCHSCREEN_IMX6UL_TSC=y
CONFIG_TOUCHSCREEN_EDT_FT5X06=y
@@ -212,6 +205,10 @@
CONFIG_SPI_GPIO=y
CONFIG_SPI_IMX=y
CONFIG_SPI_FSL_DSPI=y
+CONFIG_PINCTRL_IMX8MM=y
+CONFIG_PINCTRL_IMX8MN=y
+CONFIG_PINCTRL_IMX8MP=y
+CONFIG_PINCTRL_IMX8MQ=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_SIOX=m
CONFIG_GPIO_MAX732X=y
@@ -220,6 +217,7 @@
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_STMPE=y
CONFIG_GPIO_74X164=y
+CONFIG_GPIO_MXC=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
@@ -236,6 +234,7 @@
CONFIG_DA9063_WATCHDOG=m
CONFIG_RN5T618_WATCHDOG=y
CONFIG_IMX2_WDT=y
+CONFIG_IMX7ULP_WDT=y
CONFIG_MFD_DA9052_I2C=y
CONFIG_MFD_DA9062=y
CONFIG_MFD_DA9063=y
@@ -265,7 +264,6 @@
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_MUX=y
-CONFIG_SOC_CAMERA=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_CODA=m
CONFIG_VIDEO_IMX_PXP=y
@@ -280,6 +278,7 @@
CONFIG_DRM_PANEL_LVDS=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
+CONFIG_DRM_TI_TFP410=y
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_CEC=y
CONFIG_DRM_IMX=y
@@ -321,6 +320,7 @@
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_ACM=m
CONFIG_USB_STORAGE=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
@@ -335,7 +335,7 @@
CONFIG_USB_MXS_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_FSL_USB2=y
-CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS=y
CONFIG_USB_CONFIGFS_SERIAL=y
CONFIG_USB_CONFIGFS_ACM=y
CONFIG_USB_CONFIGFS_OBEX=y
@@ -387,6 +387,7 @@
CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MXC=y
CONFIG_RTC_DRV_MXC_V2=y
+CONFIG_RTC_DRV_RC5T619=y
CONFIG_RTC_DRV_SNVS=y
CONFIG_DMADEVICES=y
CONFIG_FSL_EDMA=y
@@ -397,9 +398,15 @@
CONFIG_STAGING_MEDIA=y
CONFIG_VIDEO_IMX_MEDIA=y
CONFIG_COMMON_CLK_PWM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MQ=y
+CONFIG_SOC_IMX8M=y
CONFIG_IIO=y
CONFIG_MMA8452=y
CONFIG_IMX7D_ADC=y
+CONFIG_RN5T618_ADC=y
CONFIG_VF610_ADC=y
CONFIG_SENSORS_ISL29018=y
CONFIG_MAG3110=y
@@ -440,6 +447,8 @@
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="cp437"
CONFIG_NLS_CODEPAGE_437=y
diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
index 2f0a762..b06e537 100644
--- a/arch/arm/configs/integrator_defconfig
+++ b/arch/arm/configs/integrator_defconfig
@@ -1,13 +1,11 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_MULTI_V4T=y
CONFIG_ARCH_MULTI_V5=y
# CONFIG_ARCH_MULTI_V7 is not set
@@ -15,19 +13,17 @@
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_INTEGRATOR_IMPD1=y
CONFIG_ARCH_INTEGRATOR_CP=y
-CONFIG_PCI=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
# CONFIG_ATAGS is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPUFREQ_DT=y
-CONFIG_CMA=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PARTITION_ADVANCED=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -37,6 +33,7 @@
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
+CONFIG_PCI=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_AFS_PARTS=y
@@ -52,10 +49,13 @@
CONFIG_NETDEVICES=y
CONFIG_E100=y
CONFIG_SMC91X=y
+CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_DRM=y
-CONFIG_DRM_DUMB_VGA_DAC=y
+CONFIG_DRM_DISPLAY_CONNECTOR=y
+CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_PL111=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_MATROX=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 3d5f5b5..84a3b05 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -11,7 +11,6 @@
CONFIG_CGROUP_SCHED=y
CONFIG_BLK_CGROUP=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_ELF_CORE is not set
# CONFIG_BASE_FULL is not set
@@ -135,6 +134,7 @@
CONFIG_NETDEVICES=y
CONFIG_TI_KEYSTONE_NETCP=y
CONFIG_TI_KEYSTONE_NETCP_ETHSS=y
+CONFIG_TI_CPTS=y
CONFIG_MARVELL_PHY=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
@@ -147,6 +147,7 @@
CONFIG_SPI=y
CONFIG_SPI_DAVINCI=y
CONFIG_SPI_SPIDEV=y
+CONFIG_PTP_1588_CLOCK=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig
index e518168..be882ea 100644
--- a/arch/arm/configs/lpc18xx_defconfig
+++ b/arch/arm/configs/lpc18xx_defconfig
@@ -1,4 +1,3 @@
-CONFIG_CROSS_COMPILE="arm-linux-gnueabihf-"
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_BLK_DEV_INITRD=y
@@ -28,10 +27,7 @@
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y
CONFIG_BINFMT_SHARED_FLAT=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 09deb57..989bcc8 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -9,7 +9,6 @@
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
# CONFIG_ARCH_MULTI_V7 is not set
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index e6486c9..d2e684f 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -9,8 +9,6 @@
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_PXA=y
CONFIG_MACH_H4700=y
CONFIG_MACH_MAGICIAN=y
diff --git a/arch/arm/configs/moxart_defconfig b/arch/arm/configs/moxart_defconfig
index 9b98761..6834e97 100644
--- a/arch/arm/configs/moxart_defconfig
+++ b/arch/arm/configs/moxart_defconfig
@@ -4,7 +4,6 @@
CONFIG_NO_HZ=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
-CONFIG_SYSCTL_SYSCALL=y
# CONFIG_ELF_CORE is not set
# CONFIG_BASE_FULL is not set
# CONFIG_SIGNALFD is not set
@@ -16,7 +15,6 @@
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ARCH_MULTI_V4=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_MOXART=y
diff --git a/arch/arm/configs/multi_v4t_defconfig b/arch/arm/configs/multi_v4t_defconfig
index 0b42bdd..e530107 100644
--- a/arch/arm/configs/multi_v4t_defconfig
+++ b/arch/arm/configs/multi_v4t_defconfig
@@ -4,22 +4,19 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_SLOB=y
-CONFIG_JUMP_LABEL=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MULTI_V4T=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_AT91=y
CONFIG_SOC_AT91RM9200=y
CONFIG_ARCH_CLPS711X=y
+CONFIG_ARCH_MXC=y
+CONFIG_SOC_IMX1=y
CONFIG_ARCH_INTEGRATOR=y
CONFIG_ARCH_INTEGRATOR_AP=y
CONFIG_INTEGRATOR_IMPD1=y
CONFIG_INTEGRATOR_CM720T=y
CONFIG_INTEGRATOR_CM920T=y
CONFIG_INTEGRATOR_CM922T_XA10=y
-CONFIG_ARCH_MXC=y
-CONFIG_SOC_IMX1=y
CONFIG_ARCH_NSPIRE=y
CONFIG_AEABI=y
# CONFIG_ATAGS is not set
@@ -28,6 +25,8 @@
CONFIG_CPU_IDLE=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_CLPS711X_CPUIDLE=y
+CONFIG_JUMP_LABEL=y
+CONFIG_PARTITION_ADVANCED=y
# CONFIG_COREDUMP is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
@@ -81,7 +80,6 @@
CONFIG_FB_CLPS711X=y
CONFIG_FB_IMX=y
CONFIG_LCD_PLATFORM=y
-CONFIG_BACKLIGHT_PWM=y
# CONFIG_USB_SUPPORT is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
@@ -92,12 +90,11 @@
CONFIG_PWM=y
CONFIG_PWM_ATMEL=y
CONFIG_PWM_CLPS711X=y
-CONFIG_PWM_IMX=y
CONFIG_EXT2_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_CRAMFS=y
CONFIG_MINIX_FS=y
+CONFIG_CRC_CCITT=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index bd01887..e00be9f 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -1,14 +1,11 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_ASPEED=y
CONFIG_MACH_ASPEED_G4=y
@@ -32,8 +29,8 @@
CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_IMX27_VISSTRIM_M10=y
CONFIG_MACH_PCA100=y
-CONFIG_MACH_IMX27_DT=y
CONFIG_SOC_IMX25=y
+CONFIG_SOC_IMX27=y
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_KIRKWOOD=y
CONFIG_ARCH_ORION5X=y
@@ -59,8 +56,6 @@
CONFIG_MACH_RD88F5181L_FXO=y
CONFIG_MACH_RD88F6183AP_GE=y
CONFIG_ARCH_U300=y
-CONFIG_PCI_MVEBU=y
-CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -72,6 +67,10 @@
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_IDLE=y
CONFIG_ARM_KIRKWOOD_CPUIDLE=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -84,6 +83,7 @@
CONFIG_NET_PKTGEN=m
CONFIG_CFG80211=y
CONFIG_MAC80211=y
+CONFIG_PCI_MVEBU=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_IMX_WEIM=y
@@ -165,6 +165,8 @@
CONFIG_SPI_IMX=y
CONFIG_SPI_ORION=y
CONFIG_GPIO_ASPEED=m
+CONFIG_GPIO_ASPEED_SGPIO=y
+CONFIG_GPIO_MXC=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_QNAP=y
@@ -186,7 +188,6 @@
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_SOC_CAMERA=y
CONFIG_VIDEO_ASPEED=m
CONFIG_VIDEO_ATMEL_ISI=m
CONFIG_DRM=y
@@ -241,6 +242,9 @@
CONFIG_USB_CONFIGFS=m
CONFIG_MMC=y
CONFIG_SDIO_UART=y
+CONFIG_MMC_SDHCI=m
+CONFIG_MMC_SDHCI_PLTFM=m
+CONFIG_MMC_SDHCI_OF_ASPEED=m
CONFIG_MMC_ATMELMCI=y
CONFIG_MMC_MVSDIO=y
CONFIG_NEW_LEDS=y
@@ -263,7 +267,6 @@
CONFIG_AT_HDMAC=y
CONFIG_MV_XOR=y
CONFIG_STAGING=y
-CONFIG_FB_XGI=y
CONFIG_ASPEED_LPC_CTRL=m
CONFIG_ASPEED_LPC_SNOOP=m
CONFIG_ASPEED_P2A_CTRL=m
@@ -292,6 +295,11 @@
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_UTF8=y
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_DEV_MARVELL_CESA=y
+CONFIG_CRC_CCITT=y
+CONFIG_LIBCRC32C=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
@@ -300,8 +308,3 @@
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
-CONFIG_CRC_CCITT=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e4c8def..a611b0c 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -43,16 +43,21 @@
CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y
+CONFIG_SOC_IMX6SLL=y
CONFIG_SOC_IMX6SX=y
CONFIG_SOC_IMX6UL=y
CONFIG_SOC_LS1021A=y
CONFIG_SOC_IMX7D=y
+CONFIG_SOC_IMX7ULP=y
CONFIG_SOC_VF610=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MESON=y
CONFIG_ARCH_MILBEAUT=y
CONFIG_ARCH_MILBEAUT_M10V=y
+CONFIG_ARCH_MMP=y
+CONFIG_MACH_MMP2_DT=y
+CONFIG_MACH_MMP3_DT=y
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_375=y
@@ -110,6 +115,7 @@
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_ZYNQ_CPUIDLE=y
CONFIG_ARM_EXYNOS_CPUIDLE=y
+CONFIG_ARM_TEGRA_CPUIDLE=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_RASPBERRYPI_FIRMWARE=y
CONFIG_TRUSTED_FOUNDATIONS=y
@@ -128,8 +134,6 @@
CONFIG_CRYPTO_GHASH_ARM_CE=m
CONFIG_CRYPTO_CRC32_ARM_CE=m
CONFIG_CRYPTO_CHACHA20_NEON=m
-CONFIG_GCC_PLUGINS=y
-CONFIG_GCC_PLUGIN_STRUCTLEAK=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
@@ -168,13 +172,20 @@
CONFIG_RFKILL=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=y
+CONFIG_NFC=m
+CONFIG_NFC_DIGITAL=m
+CONFIG_NFC_NCI=m
+CONFIG_NFC_NCI_SPI=m
+CONFIG_NFC_NCI_UART=m
+CONFIG_NFC_HCI=m
+CONFIG_NFC_SHDLC=y
+CONFIG_NFC_S3FWRN5_I2C=m
CONFIG_PCIEPORTBUS=y
CONFIG_PCI_MVEBU=y
CONFIG_PCI_TEGRA=y
CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PCIE_RCAR=y
+CONFIG_PCIE_RCAR_HOST=y
CONFIG_PCI_DRA7XX_EP=y
-CONFIG_PCI_KEYSTONE=y
CONFIG_PCI_ENDPOINT=y
CONFIG_PCI_ENDPOINT_CONFIGFS=y
CONFIG_PCI_EPF_TEST=m
@@ -189,15 +200,14 @@
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_M25P80=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_NAND_MARVELL=y
-CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_VF610_NFC=y
CONFIG_MTD_NAND_DAVINCI=y
CONFIG_MTD_NAND_STM32_FMC2=y
@@ -244,6 +254,7 @@
CONFIG_SYSTEMPORT=m
CONFIG_MACB=y
CONFIG_NET_CALXEDA_XGMAC=y
+CONFIG_FTGMAC100=m
CONFIG_GIANFAR=y
CONFIG_HIX5HD2_GMAC=y
CONFIG_E1000E=y
@@ -260,11 +271,11 @@
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_TI_CPSW=y
CONFIG_XILINX_EMACLITE=y
-CONFIG_AT803X_PHY=y
CONFIG_BROADCOM_PHY=y
CONFIG_ICPLUS_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_MICREL_PHY=y
+CONFIG_AT803X_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_USB_PEGASUS=y
@@ -283,6 +294,7 @@
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_TEGRA=y
+CONFIG_KEYBOARD_PXA27x=m
CONFIG_KEYBOARD_SAMSUNG=m
CONFIG_KEYBOARD_ST_KEYSCAN=y
CONFIG_KEYBOARD_SPEAR=y
@@ -304,6 +316,7 @@
CONFIG_INPUT_MAX8997_HAPTIC=m
CONFIG_INPUT_CPCAP_PWRBUTTON=m
CONFIG_INPUT_AXP20X_PEK=m
+CONFIG_INPUT_DA9063_ONKEY=m
CONFIG_INPUT_ADXL34X=m
CONFIG_INPUT_STPMIC1_ONKEY=y
CONFIG_SERIO_AMBAKMI=y
@@ -377,7 +390,6 @@
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_DIGICOLOR=m
CONFIG_I2C_EMEV2=m
-CONFIG_I2C_GPIO=m
CONFIG_I2C_IMX=y
CONFIG_I2C_MESON=y
CONFIG_I2C_MV64XXX=y
@@ -437,6 +449,7 @@
CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_PINCTRL_QCOM_SSBI_PMIC=y
+CONFIG_GPIO_ASPEED_SGPIO=y
CONFIG_GPIO_DAVINCI=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_EM=y
@@ -452,6 +465,7 @@
CONFIG_GPIO_TPS6586X=y
CONFIG_GPIO_TPS65910=y
CONFIG_GPIO_TWL4030=y
+CONFIG_GPIO_MXC=y
CONFIG_POWER_AVS=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_POWER_RESET_AS3722=y
@@ -467,8 +481,8 @@
CONFIG_AXP20X_POWER=m
CONFIG_BATTERY_MAX17040=m
CONFIG_BATTERY_MAX17042=m
-CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_CPCAP=m
+CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_MAX14577=m
CONFIG_CHARGER_MAX77693=m
CONFIG_CHARGER_MAX8997=m
@@ -483,20 +497,22 @@
CONFIG_SENSORS_RASPBERRYPI_HWMON=m
CONFIG_SENSORS_INA2XX=m
CONFIG_CPU_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_RCAR_THERMAL=y
CONFIG_ARMADA_THERMAL=y
+CONFIG_BCM2711_THERMAL=m
CONFIG_BCM2835_THERMAL=m
CONFIG_BRCMSTB_THERMAL=m
CONFIG_ST_THERMAL_MEMMAP=y
CONFIG_UNIPHIER_THERMAL=y
-CONFIG_WATCHDOG=y
CONFIG_DA9063_WATCHDOG=m
CONFIG_XILINX_WATCHDOG=y
CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_AT91SAM9X_WATCHDOG=y
CONFIG_SAMA5D4_WATCHDOG=y
+CONFIG_S3C2410_WATCHDOG=m
CONFIG_DW_WATCHDOG=y
CONFIG_DAVINCI_WATCHDOG=m
CONFIG_ORION_WATCHDOG=y
@@ -508,6 +524,7 @@
CONFIG_MESON_WATCHDOG=y
CONFIG_DIGICOLOR_WATCHDOG=y
CONFIG_RENESAS_WDT=m
+CONFIG_RENESAS_RZAWDT=m
CONFIG_STPMIC1_WATCHDOG=y
CONFIG_BCM47XX_WDT=y
CONFIG_BCM2835_WDT=y
@@ -525,10 +542,6 @@
CONFIG_MFD_AC100=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
-CONFIG_MFD_CROS_EC=m
-CONFIG_CROS_EC_I2C=m
-CONFIG_CROS_EC_SPI=m
-CONFIG_MFD_CROS_EC_CHARDEV=m
CONFIG_MFD_DA9063=m
CONFIG_MFD_MAX14577=y
CONFIG_MFD_MAX77686=y
@@ -581,10 +594,12 @@
CONFIG_REGULATOR_QCOM_SMD_RPM=m
CONFIG_REGULATOR_RK808=y
CONFIG_REGULATOR_RN5T618=y
+CONFIG_REGULATOR_S2MPA01=m
CONFIG_REGULATOR_S2MPS11=y
CONFIG_REGULATOR_S5M8767=y
CONFIG_REGULATOR_STM32_BOOSTER=m
CONFIG_REGULATOR_STM32_VREFBUF=m
+CONFIG_REGULATOR_STM32_PWR=y
CONFIG_REGULATOR_STPMIC1=y
CONFIG_REGULATOR_TI_ABB=y
CONFIG_REGULATOR_TPS51632=y
@@ -605,8 +620,10 @@
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_MMP_CAMERA=m
CONFIG_VIDEO_ASPEED=m
CONFIG_VIDEO_STM32_DCMI=m
+CONFIG_VIDEO_RENESAS_CEU=m
CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m
CONFIG_VIDEO_S5P_FIMC=m
CONFIG_VIDEO_S5P_MIPI_CSIS=m
@@ -627,10 +644,12 @@
CONFIG_V4L_TEST_DRIVERS=y
CONFIG_VIDEO_VIVID=m
CONFIG_CEC_PLATFORM_DRIVERS=y
-CONFIG_VIDEO_SAMSUNG_S5P_CEC=m
-# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+CONFIG_CEC_SAMSUNG_S5P=m
CONFIG_VIDEO_ADV7180=m
+CONFIG_VIDEO_ADV7604=m
+CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ML86V7667=m
+CONFIG_IMX_IPUV3_CORE=m
CONFIG_DRM=y
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
@@ -646,6 +665,11 @@
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_DRM_IMX=m
+CONFIG_DRM_IMX_PARALLEL_DISPLAY=m
+CONFIG_DRM_IMX_TVE=m
+CONFIG_DRM_IMX_LDB=m
+CONFIG_DRM_IMX_HDMI=m
CONFIG_DRM_ATMEL_HLCDC=m
CONFIG_DRM_RCAR_DU=m
CONFIG_DRM_RCAR_LVDS=y
@@ -661,11 +685,11 @@
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
-CONFIG_DRM_DUMB_VGA_DAC=m
CONFIG_DRM_NXP_PTN3460=m
CONFIG_DRM_PARADE_PS8622=m
CONFIG_DRM_SII902X=m
CONFIG_DRM_SII9234=m
+CONFIG_DRM_SIMPLE_BRIDGE=m
CONFIG_DRM_TOSHIBA_TC358764=m
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_AUDIO=y
@@ -681,7 +705,6 @@
CONFIG_FB_WM8505=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_FB_SIMPLE=y
-CONFIG_LCD_PLATFORM=m
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_AS3711=y
CONFIG_BACKLIGHT_GPIO=y
@@ -702,6 +725,9 @@
CONFIG_SND_ATMEL_SOC_I2S=m
CONFIG_SND_BCM2835_SOC_I2S=m
CONFIG_SND_SOC_FSL_SAI=m
+CONFIG_SND_MMP_SOC=y
+CONFIG_SND_PXA_SOC_SSP=m
+CONFIG_SND_PXA910_SOC=m
CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
@@ -711,9 +737,12 @@
CONFIG_SND_SOC_SMDK_WM8994_PCM=m
CONFIG_SND_SOC_SNOW=m
CONFIG_SND_SOC_ODROID=m
+CONFIG_SND_SOC_ARNDALE=m
CONFIG_SND_SOC_SH4_FSI=m
CONFIG_SND_SOC_RCAR=m
CONFIG_SND_SOC_STI=m
+CONFIG_SND_SOC_STM32_SAI=m
+CONFIG_SND_SOC_STM32_I2S=m
CONFIG_SND_SUN4I_CODEC=m
CONFIG_SND_SOC_TEGRA=m
CONFIG_SND_SOC_TEGRA20_I2S=m
@@ -727,10 +756,12 @@
CONFIG_SND_SOC_TEGRA_MAX98090=m
CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_CPCAP=m
+CONFIG_SND_SOC_CS42L51_I2C=m
CONFIG_SND_SOC_SGTL5000=m
CONFIG_SND_SOC_SPDIF=m
CONFIG_SND_SOC_STI_SAS=m
CONFIG_SND_SOC_WM8978=m
+CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_USB=y
CONFIG_USB_OTG=y
CONFIG_USB_XHCI_HCD=y
@@ -740,6 +771,7 @@
CONFIG_USB_EHCI_HCD_STI=y
CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_EHCI_EXYNOS=y
+CONFIG_USB_EHCI_MV=m
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_STI=y
CONFIG_USB_OHCI_EXYNOS=m
@@ -810,6 +842,7 @@
CONFIG_MMC_SDHCI_TEGRA=y
CONFIG_MMC_SDHCI_S3C=y
CONFIG_MMC_SDHCI_PXAV3=y
+CONFIG_MMC_SDHCI_PXAV2=m
CONFIG_MMC_SDHCI_SPEAR=y
CONFIG_MMC_SDHCI_S3C_DMA=y
CONFIG_MMC_SDHCI_BCM_KONA=y
@@ -875,6 +908,8 @@
CONFIG_RTC_DRV_EFI=m
CONFIG_RTC_DRV_DIGICOLOR=m
CONFIG_RTC_DRV_S3C=m
+CONFIG_RTC_DRV_SA1100=m
+CONFIG_RTC_DRV_SH=m
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_AT91RM9200=m
CONFIG_RTC_DRV_AT91SAM9=m
@@ -919,6 +954,9 @@
CONFIG_NVEC_POWER=y
CONFIG_NVEC_PAZ00=y
CONFIG_STAGING_BOARD=y
+CONFIG_MFD_CROS_EC_DEV=m
+CONFIG_CROS_EC_I2C=m
+CONFIG_CROS_EC_SPI=m
CONFIG_COMMON_CLK_MAX77686=y
CONFIG_COMMON_CLK_RK808=m
CONFIG_COMMON_CLK_S2MPS11=m
@@ -933,6 +971,7 @@
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_TEGRA_IOMMU_GART=y
CONFIG_TEGRA_IOMMU_SMMU=y
+CONFIG_EXYNOS_IOMMU=y
CONFIG_REMOTEPROC=y
CONFIG_ST_REMOTEPROC=m
CONFIG_RPMSG_VIRTIO=m
@@ -949,6 +988,7 @@
CONFIG_ARCH_R7S9210=y
CONFIG_ARCH_R8A73A4=y
CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7742=y
CONFIG_ARCH_R8A7743=y
CONFIG_ARCH_R8A7744=y
CONFIG_ARCH_R8A7745=y
@@ -967,8 +1007,15 @@
CONFIG_ARCH_TEGRA_3x_SOC=y
CONFIG_ARCH_TEGRA_114_SOC=y
CONFIG_ARCH_TEGRA_124_SOC=y
+CONFIG_ARM_EXYNOS_BUS_DEVFREQ=m
CONFIG_ARM_TEGRA_DEVFREQ=m
+CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=m
+CONFIG_EXTCON_MAX14577=m
+CONFIG_EXTCON_MAX77693=m
+CONFIG_EXTCON_MAX8997=m
CONFIG_TI_AEMIF=y
+CONFIG_STM32_FMC2_EBI=y
+CONFIG_EXYNOS5422_DMC=m
CONFIG_IIO=y
CONFIG_IIO_SW_TRIGGER=y
CONFIG_ASPEED_ADC=m
@@ -978,16 +1025,15 @@
CONFIG_CPCAP_ADC=m
CONFIG_EXYNOS_ADC=m
CONFIG_MESON_SARADC=m
+CONFIG_ROCKCHIP_SARADC=m
CONFIG_STM32_ADC_CORE=m
CONFIG_STM32_ADC=m
CONFIG_STM32_DFSDM_ADC=m
CONFIG_VF610_ADC=m
CONFIG_XILINX_XADC=y
-CONFIG_STM32_LPTIMER_CNT=m
-CONFIG_STM32_DAC=m
-CONFIG_ROCKCHIP_SARADC=m
CONFIG_IIO_CROS_EC_SENSORS_CORE=m
CONFIG_IIO_CROS_EC_SENSORS=m
+CONFIG_STM32_DAC=m
CONFIG_MPU3050_I2C=y
CONFIG_CM36651=m
CONFIG_IIO_CROS_EC_LIGHT_PROX=m
@@ -1020,12 +1066,14 @@
CONFIG_PHY_HIX5HD2_SATA=y
CONFIG_PHY_BERLIN_SATA=y
CONFIG_PHY_BERLIN_USB=y
+CONFIG_PHY_MMP3_USB=m
CONFIG_PHY_CPCAP_USB=m
CONFIG_PHY_QCOM_APQ8064_SATA=m
CONFIG_PHY_RCAR_GEN2=m
CONFIG_PHY_ROCKCHIP_DP=m
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PHY_SAMSUNG_USB2=m
+CONFIG_PHY_EXYNOS5250_SATA=m
CONFIG_PHY_UNIPHIER_USB2=y
CONFIG_PHY_UNIPHIER_USB3=y
CONFIG_PHY_MIPHY28LP=y
@@ -1036,11 +1084,18 @@
CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
CONFIG_TWL4030_USB=m
-CONFIG_MESON_MX_EFUSE=m
-CONFIG_ROCKCHIP_EFUSE=m
CONFIG_NVMEM_IMX_OCOTP=y
+CONFIG_ROCKCHIP_EFUSE=m
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_NVMEM_VF610_OCOTP=y
+CONFIG_MESON_MX_EFUSE=m
+CONFIG_FSI=m
+CONFIG_FSI_MASTER_GPIO=m
+CONFIG_FSI_MASTER_HUB=m
+CONFIG_FSI_MASTER_ASPEED=m
+CONFIG_FSI_SCOM=m
+CONFIG_FSI_SBEFIFO=m
+CONFIG_FSI_OCC=m
CONFIG_EXT4_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y
@@ -1058,6 +1113,8 @@
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
@@ -1067,14 +1124,19 @@
CONFIG_CRYPTO_USER_API_SKCIPHER=m
CONFIG_CRYPTO_USER_API_RNG=m
CONFIG_CRYPTO_USER_API_AEAD=m
+CONFIG_CRYPTO_DEV_SUN4I_SS=m
+CONFIG_CRYPTO_DEV_FSL_CAAM=m
CONFIG_CRYPTO_DEV_MARVELL_CESA=m
CONFIG_CRYPTO_DEV_EXYNOS_RNG=m
CONFIG_CRYPTO_DEV_S5P=m
CONFIG_CRYPTO_DEV_ATMEL_AES=m
CONFIG_CRYPTO_DEV_ATMEL_TDES=m
CONFIG_CRYPTO_DEV_ATMEL_SHA=m
-CONFIG_CRYPTO_DEV_SUN4I_SS=m
CONFIG_CRYPTO_DEV_ROCKCHIP=m
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CROS_EC=m
+CONFIG_CROS_EC_CHARDEV=m
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 2773899..a9c6f32 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -25,8 +25,6 @@
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_BLK_DEV_INTEGRITY=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 0c43c58..3b6e745 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -18,8 +18,6 @@
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_OMAP1=y
CONFIG_OMAP_RESET_CLOCKS=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 4ec69fb..58df9fd 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -56,6 +56,8 @@
# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
CONFIG_ARM_TI_CPUFREQ=y
CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_DT_IDLE_STATES=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_PM_DEBUG=y
CONFIG_ARM_CRYPTO=y
@@ -78,6 +80,7 @@
CONFIG_PARTITION_ADVANCED=y
CONFIG_BINFMT_MISC=y
CONFIG_CMA=y
+CONFIG_ZSMALLOC=m
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -91,7 +94,19 @@
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NETFILTER=y
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q=m
CONFIG_PHONET=m
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_CLS_U32=m
+CONFIG_NET_CLS_FLOWER=m
+CONFIG_NET_CLS_MATCHALL=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_NET_SWITCHDEV=y
CONFIG_CAN=m
CONFIG_CAN_C_CAN=m
CONFIG_CAN_C_CAN_PLATFORM=m
@@ -128,8 +143,8 @@
CONFIG_PCI_EPF_TEST=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMA_CMA=y
CONFIG_OMAP_OCP2SCP=y
+CONFIG_SIMPLE_PM_BUS=y
CONFIG_CONNECTOR=m
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
@@ -139,7 +154,6 @@
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_M25P80=m
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_OMAP2=y
@@ -149,6 +163,8 @@
CONFIG_MTD_NAND_OMAP_BCH=y
CONFIG_MTD_SPI_NOR=m
CONFIG_MTD_UBI=y
+CONFIG_ZRAM=m
+CONFIG_ZRAM_WRITEBACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
@@ -182,13 +198,14 @@
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_TI_DAVINCI_EMAC=y
CONFIG_TI_CPSW=y
+CONFIG_TI_CPSW_SWITCHDEV=y
CONFIG_TI_CPTS=y
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_AT803X_PHY=y
CONFIG_DP83848_PHY=y
CONFIG_DP83867_PHY=y
CONFIG_MICREL_PHY=y
+CONFIG_AT803X_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
@@ -267,6 +284,7 @@
CONFIG_HSI=m
CONFIG_OMAP_SSI=m
CONFIG_SSI_PROTOCOL=m
+CONFIG_PTP_1588_CLOCK=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
@@ -277,6 +295,7 @@
CONFIG_GPIO_TWL4030=y
CONFIG_W1=m
CONFIG_HDQ_MASTER_OMAP=m
+CONFIG_W1_SLAVE_DS250X=m
CONFIG_POWER_AVS=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
@@ -343,28 +362,25 @@
CONFIG_CEC_PLATFORM_DRIVERS=y
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_TVP5150=m
+CONFIG_VIDEO_MT9P031=m
CONFIG_DRM=m
CONFIG_DRM_OMAP=m
CONFIG_OMAP5_DSS_HDMI=y
CONFIG_OMAP2_DSS_SDI=y
CONFIG_OMAP2_DSS_DSI=y
-CONFIG_DRM_OMAP_ENCODER_OPA362=m
-CONFIG_DRM_OMAP_ENCODER_TFP410=m
-CONFIG_DRM_OMAP_ENCODER_TPD12S015=m
-CONFIG_DRM_OMAP_CONNECTOR_DVI=m
-CONFIG_DRM_OMAP_CONNECTOR_HDMI=m
-CONFIG_DRM_OMAP_CONNECTOR_ANALOG_TV=m
-CONFIG_DRM_OMAP_PANEL_DPI=m
CONFIG_DRM_OMAP_PANEL_DSI_CM=m
CONFIG_DRM_TILCDC=m
CONFIG_DRM_PANEL_SIMPLE=m
-CONFIG_DRM_TI_TFP410=m
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
+CONFIG_DRM_DISPLAY_CONNECTOR=m
+CONFIG_DRM_SIMPLE_BRIDGE=m
+CONFIG_DRM_TI_TFP410=m
+CONFIG_DRM_TI_TPD12S015=m
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y
@@ -376,6 +392,7 @@
CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_PANDORA=m
CONFIG_BACKLIGHT_GPIO=m
+CONFIG_BACKLIGHT_LED=m
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_LOGO=y
@@ -483,6 +500,8 @@
CONFIG_RTC_DRV_OMAP=m
CONFIG_RTC_DRV_CPCAP=m
CONFIG_DMADEVICES=y
+CONFIG_CLK_TWL6040=m
+CONFIG_COMMON_CLK_PALMAS=m
CONFIG_OMAP_IOMMU=y
CONFIG_REMOTEPROC=y
CONFIG_OMAP_REMOTEPROC=m
@@ -499,7 +518,10 @@
CONFIG_IIO_SW_TRIGGER=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_CPCAP_ADC=m
+CONFIG_INA2XX_ADC=m
CONFIG_TI_AM335X_ADC=m
+CONFIG_TWL4030_MADC=m
+CONFIG_SENSORS_ISL29028=m
CONFIG_BMP280=m
CONFIG_PWM=y
CONFIG_PWM_OMAP_DMTIMER=m
@@ -515,6 +537,7 @@
CONFIG_TWL4030_USB=m
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS_SECURITY=y
CONFIG_FANOTIFY=y
CONFIG_QUOTA=y
CONFIG_QFMT_V2=y
@@ -539,19 +562,24 @@
CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_DEV_OMAP=m
+CONFIG_CRYPTO_DEV_OMAP_SHAM=m
+CONFIG_CRYPTO_DEV_OMAP_AES=m
+CONFIG_CRYPTO_DEV_OMAP_DES=m
CONFIG_CRC_CCITT=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
+CONFIG_DMA_CMA=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_PRINTK_TIME=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_INFO_SPLIT=y
CONFIG_DEBUG_INFO_DWARF4=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_SCHEDSTATS=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig
index 4a3fd82..b47c8ab 100644
--- a/arch/arm/configs/palmz72_defconfig
+++ b/arch/arm/configs/palmz72_defconfig
@@ -7,8 +7,6 @@
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_PXA=y
CONFIG_ARCH_PXA_PALM=y
# CONFIG_MACH_PALMTX is not set
diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig
index a8c5322..e97a158 100644
--- a/arch/arm/configs/pcm027_defconfig
+++ b/arch/arm/configs/pcm027_defconfig
@@ -13,8 +13,6 @@
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_PXA=y
CONFIG_MACH_PCM027=y
CONFIG_MACH_PCM990_BASEBOARD=y
diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig
index f0541b0..2170148 100644
--- a/arch/arm/configs/pleb_defconfig
+++ b/arch/arm/configs/pleb_defconfig
@@ -6,8 +6,6 @@
# CONFIG_HOTPLUG is not set
# CONFIG_SHMEM is not set
CONFIG_MODULES=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SA1100=y
CONFIG_SA1100_PLEB=y
CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig
index b817c57..d7b9eaf 100644
--- a/arch/arm/configs/pxa_defconfig
+++ b/arch/arm/configs/pxa_defconfig
@@ -38,8 +38,6 @@
CONFIG_MACH_BALLOON3=y
CONFIG_MACH_CSB726=y
CONFIG_CSB726_CSB701=y
-CONFIG_MACH_ARMCORE=y
-CONFIG_MACH_EM_X270=y
CONFIG_MACH_EXEDA=y
CONFIG_MACH_CM_X300=y
CONFIG_MACH_CAPC7117=y
@@ -393,7 +391,9 @@
CONFIG_MFD_AS3711=y
CONFIG_MFD_BCM590XX=m
CONFIG_MFD_AXP20X=y
-CONFIG_MFD_CROS_EC=m
+CONFIG_MFD_CROS_EC_DEV=m
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CROS_EC=m
CONFIG_CROS_EC_I2C=m
CONFIG_CROS_EC_SPI=m
CONFIG_MFD_ASIC3=y
@@ -447,11 +447,8 @@
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_SOC_CAMERA=m
-CONFIG_SOC_CAMERA_PLATFORM=m
CONFIG_VIDEO_PXA27x=m
CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_SOC_CAMERA_MT9M111=m
CONFIG_DRM=m
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_TILEBLITTING=y
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 02f1e7b..c882167 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -5,7 +5,6 @@
CONFIG_IKCONFIG_PROC=y
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_SLUB_DEBUG is not set
@@ -51,6 +50,11 @@
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
+CONFIG_QRTR=m
+CONFIG_QRTR_SMD=m
+CONFIG_BT=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_BCM=y
CONFIG_CFG80211=m
CONFIG_MAC80211=m
CONFIG_RFKILL=y
@@ -112,6 +116,7 @@
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@@ -149,6 +154,7 @@
CONFIG_DRM=y
CONFIG_DRM_MSM=m
CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_ANALOGIX_ANX78XX=m
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_LCD_CLASS_DEVICE is not set
@@ -226,6 +232,7 @@
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_QCOM_SMD=y
CONFIG_QCOM_GSBI=y
+CONFIG_QCOM_OCMEM=y
CONFIG_QCOM_PM=y
CONFIG_QCOM_SMEM=y
CONFIG_QCOM_SMD_RPM=y
@@ -251,6 +258,9 @@
CONFIG_PHY_QCOM_USB_HS=y
CONFIG_PHY_QCOM_USB_HSIC=y
CONFIG_QCOM_QFPROM=y
+CONFIG_INTERCONNECT=y
+CONFIG_INTERCONNECT_QCOM=y
+CONFIG_INTERCONNECT_QCOM_MSM8974=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index 8a056cc..483c400 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -5,10 +5,6 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_REALVIEW=y
CONFIG_MACH_REALVIEW_EB=y
@@ -21,11 +17,12 @@
CONFIG_MACH_REALVIEW_PBA8=y
CONFIG_MACH_REALVIEW_PBX=y
CONFIG_SMP=y
-CONFIG_CMA=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=ttyAMA0 mem=128M"
CONFIG_VFP=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -60,8 +57,12 @@
CONFIG_SPI=y
CONFIG_GPIOLIB=y
# CONFIG_HWMON is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_DRM=y
CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_DISPLAY_CONNECTOR=y
+CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_PL111=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
@@ -79,6 +80,7 @@
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
@@ -94,10 +96,9 @@
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index ef78534..037d3a7 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -14,12 +14,11 @@
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_SOC_SAMA5D2=y
CONFIG_SOC_SAMA5D3=y
CONFIG_SOC_SAMA5D4=y
+# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
CONFIG_AEABI=y
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -50,9 +49,14 @@
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
CONFIG_IPV6_SIT_6RD=y
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_NET_DSA=m
+CONFIG_VLAN_8021Q=m
CONFIG_CAN=y
CONFIG_CAN_AT91=y
CONFIG_CAN_M_CAN=y
+CONFIG_CAN_M_CAN_PLATFORM=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_MAC80211_LEDS=y
@@ -81,6 +85,8 @@
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
+CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
+CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
CONFIG_MACB=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
@@ -129,6 +135,7 @@
CONFIG_SPI_ATMEL=y
CONFIG_SPI_GPIO=y
CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_SAMA5D2_PIOBU=m
CONFIG_POWER_SUPPLY=y
CONFIG_BATTERY_ACT8945A=y
CONFIG_POWER_RESET=y
@@ -143,13 +150,12 @@
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_ACT8865=y
CONFIG_REGULATOR_ACT8945A=y
+CONFIG_REGULATOR_MCP16502=m
CONFIG_REGULATOR_PWM=m
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_SOC_CAMERA=y
CONFIG_VIDEO_ATMEL_ISI=y
-CONFIG_SOC_CAMERA_OV2640=m
CONFIG_DRM=y
CONFIG_DRM_ATMEL_HLCDC=y
CONFIG_DRM_PANEL_SIMPLE=y
@@ -164,6 +170,7 @@
CONFIG_SND_ATMEL_SOC=y
CONFIG_SND_ATMEL_SOC_WM8904=y
# CONFIG_HID_GENERIC is not set
+CONFIG_SND_ATMEL_SOC_CLASSD=y
CONFIG_SND_ATMEL_SOC_PDMIC=y
CONFIG_SND_ATMEL_SOC_TSE850_PCM5142=m
CONFIG_SND_ATMEL_SOC_I2S=y
@@ -181,7 +188,6 @@
CONFIG_USB_ATMEL_USBA=y
CONFIG_USB_G_SERIAL=y
CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_AT91=y
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index c6c7035..4a161b3 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -9,13 +9,10 @@
CONFIG_SLAB=y
CONFIG_ARCH_RENESAS=y
CONFIG_PL310_ERRATA_588369=y
-CONFIG_ARM_ERRATA_754322=y
CONFIG_SMP=y
CONFIG_SCHED_MC=y
CONFIG_NR_CPUS=8
CONFIG_HIGHMEM=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_KEXEC=y
CONFIG_CPU_FREQ=y
@@ -40,7 +37,7 @@
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_PCI_RCAR_GEN2=y
-CONFIG_PCIE_RCAR=y
+CONFIG_PCIE_RCAR_HOST=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_SIMPLE_PM_BUS=y
@@ -50,7 +47,6 @@
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_M25P80=y
CONFIG_MTD_SPI_NOR=y
CONFIG_EEPROM_AT24=y
CONFIG_BLK_DEV_SD=y
@@ -66,8 +62,11 @@
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_EDT_FT5X06=y
CONFIG_TOUCHSCREEN_ST1232=y
+CONFIG_TOUCHSCREEN_STMPE=y
CONFIG_INPUT_MISC=y
+CONFIG_INPUT_DA9063_ONKEY=y
CONFIG_INPUT_ADXL34X=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
@@ -91,6 +90,7 @@
CONFIG_PINCTRL_RZA2=y
CONFIG_GPIO_EM=y
CONFIG_GPIO_RCAR=y
+CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCF857X=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_RMOBILE=y
@@ -102,36 +102,40 @@
CONFIG_WATCHDOG=y
CONFIG_DA9063_WATCHDOG=y
CONFIG_RENESAS_WDT=y
+CONFIG_RENESAS_RZAWDT=y
CONFIG_MFD_AS3711=y
CONFIG_MFD_DA9063=y
+CONFIG_MFD_STMPE=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_AS3711=y
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_MAX8973=y
CONFIG_MEDIA_SUPPORT=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_RENESAS_CEU=y
CONFIG_VIDEO_RCAR_VIN=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_RENESAS_FDP1=y
CONFIG_VIDEO_RENESAS_JPU=y
CONFIG_VIDEO_RENESAS_VSP1=y
-# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_ADV7180=y
CONFIG_VIDEO_ADV7604=y
+CONFIG_VIDEO_ADV7604_CEC=y
CONFIG_VIDEO_ML86V7667=y
CONFIG_DRM=y
CONFIG_DRM_RCAR_DU=y
-CONFIG_DRM_DUMB_VGA_DAC=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_DISPLAY_CONNECTOR=y
+CONFIG_DRM_LVDS_CODEC=y
CONFIG_DRM_SII902X=y
+CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_I2C_ADV7511=y
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_FB_SH_MOBILE_LCDC=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_AS3711=y
CONFIG_SOUND=y
@@ -167,6 +171,7 @@
CONFIG_RTC_DRV_S35390A=y
CONFIG_RTC_DRV_RX8581=y
CONFIG_RTC_DRV_DA9063=y
+CONFIG_RTC_DRV_SH=y
CONFIG_DMADEVICES=y
CONFIG_RCAR_DMAC=y
CONFIG_RENESAS_USB_DMAC=y
@@ -178,6 +183,7 @@
CONFIG_ARCH_R7S9210=y
CONFIG_ARCH_R8A73A4=y
CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7742=y
CONFIG_ARCH_R8A7743=y
CONFIG_ARCH_R8A7744=y
CONFIG_ARCH_R8A7745=y
@@ -215,4 +221,5 @@
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_PRINTK_TIME=y
# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index fe2e1e8..e73c97b 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -157,6 +157,7 @@
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_FUNCTION_TRACER=y
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 152321d..551db32 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -14,8 +14,6 @@
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
# CONFIG_MMU is not set
CONFIG_ARCH_STM32=y
CONFIG_CPU_V7M_NUM_IRQ=240
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index df433ab..2441261 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -3,20 +3,19 @@
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_PERF_EVENTS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_SUNXI=y
CONFIG_SMP=y
CONFIG_NR_CPUS=8
-CONFIG_AEABI=y
CONFIG_HIGHMEM=y
-CONFIG_CMA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CPU_FREQ=y
CONFIG_CPUFREQ_DT=y
CONFIG_VFP=y
CONFIG_NEON=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_CMA=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -24,9 +23,6 @@
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_CAN=y
@@ -34,14 +30,12 @@
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMA_CMA=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_AHCI_SUNXI=y
CONFIG_NETDEVICES=y
CONFIG_SUN4I_EMAC=y
# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
@@ -56,6 +50,7 @@
CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MICREL_PHY=y
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_SUN4I_LRADC=y
@@ -64,6 +59,7 @@
CONFIG_TOUCHSCREEN_SUN4I=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AXP20X_PEK=y
+CONFIG_SERIO_SUN4I_PS2=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=8
@@ -84,6 +80,7 @@
CONFIG_AXP20X_POWER=y
CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
+CONFIG_SUN8I_THERMAL=y
CONFIG_WATCHDOG=y
CONFIG_SUNXI_WATCHDOG=y
CONFIG_MFD_AC100=y
@@ -93,18 +90,37 @@
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_GPIO=y
-CONFIG_MEDIA_SUPPORT=y
CONFIG_RC_CORE=y
CONFIG_RC_DEVICES=y
CONFIG_IR_SUNXI=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_SUN4I_CSI=y
+CONFIG_VIDEO_SUN6I_CSI=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_SUN8I_DEINTERLACE=y
+CONFIG_VIDEO_SUN8I_ROTATE=y
CONFIG_DRM=y
CONFIG_DRM_SUN4I=y
-CONFIG_DRM_DUMB_VGA_DAC=y
+CONFIG_DRM_SUN4I_HDMI_CEC=y
+CONFIG_DRM_SUN8I_DW_HDMI=y
+CONFIG_DRM_PANEL_LVDS=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_SIMPLE_BRIDGE=y
+CONFIG_DRM_LIMA=y
CONFIG_FB_SIMPLE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
CONFIG_SND_SUN4I_CODEC=y
+CONFIG_SND_SUN8I_CODEC=y
+CONFIG_SND_SUN8I_CODEC_ANALOG=y
+CONFIG_SND_SUN4I_I2S=y
+CONFIG_SND_SUN4I_SPDIF=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
@@ -129,15 +145,18 @@
CONFIG_RTC_DRV_SUNXI=y
CONFIG_DMADEVICES=y
CONFIG_DMA_SUN6I=y
+CONFIG_STAGING=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_VIDEO_SUNXI=y
+CONFIG_VIDEO_SUNXI_CEDRUS=y
+CONFIG_MAILBOX=y
# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXTCON=y
CONFIG_IIO=y
CONFIG_AXP20X_ADC=y
CONFIG_PWM=y
CONFIG_PWM_SUN4I=y
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN9I_USB=y
-CONFIG_NVMEM=y
CONFIG_NVMEM_SUNXI_SID=y
CONFIG_EXT4_FS=y
CONFIG_VFAT_FS=y
@@ -148,6 +167,10 @@
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
+CONFIG_CRYPTO_DEV_SUN4I_SS=y
+CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
+CONFIG_CRYPTO_DEV_SUN8I_CE=y
+CONFIG_CRYPTO_DEV_SUN8I_SS=y
+CONFIG_DMA_CMA=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_FS=y
-CONFIG_CRYPTO_DEV_SUN4I_SS=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 8f5c6a5..fff5fae 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -10,6 +10,8 @@
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_DEBUG=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_ELF_CORE is not set
CONFIG_EMBEDDED=y
@@ -18,13 +20,16 @@
CONFIG_ARCH_TEGRA=y
CONFIG_SMP=y
CONFIG_HIGHMEM=y
+CONFIG_SECCOMP=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_KEXEC=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPU_IDLE=y
+CONFIG_ARM_TEGRA_CPUIDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_TRUSTED_FOUNDATIONS=y
@@ -62,11 +67,17 @@
CONFIG_BT_BNEP=y
CONFIG_BT_HIDP=y
CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_BCM=y
CONFIG_CFG80211=y
CONFIG_MAC80211=y
CONFIG_RFKILL=y
CONFIG_RFKILL_INPUT=y
CONFIG_RFKILL_GPIO=y
+CONFIG_NFC=y
+CONFIG_NFC_HCI=y
+CONFIG_NFC_SHDLC=y
+CONFIG_NFC_PN544_I2C=y
CONFIG_PCI=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCI_MSI=y
@@ -105,20 +116,24 @@
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_TEGRA=y
+CONFIG_KEYBOARD_CAP11XX=y
CONFIG_KEYBOARD_CROS_EC=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_ELAN=y
CONFIG_TOUCHSCREEN_WM97XX=y
# CONFIG_TOUCHSCREEN_WM9705 is not set
# CONFIG_TOUCHSCREEN_WM9713 is not set
CONFIG_TOUCHSCREEN_STMPE=y
CONFIG_INPUT_MISC=y
+CONFIG_INPUT_GPIO_VIBRA=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_TEGRA=y
+CONFIG_SERIAL_DEV_BUS=y
# CONFIG_HW_RANDOM is not set
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
@@ -130,10 +145,12 @@
CONFIG_SPI_TEGRA20_SFLASH=y
CONFIG_SPI_TEGRA20_SLINK=y
CONFIG_PINCTRL_AS3722=y
+CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_PALMAS=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_MAX77620=y
CONFIG_GPIO_PALMAS=y
CONFIG_GPIO_TPS6586X=y
CONFIG_GPIO_TPS65910=y
@@ -141,13 +158,21 @@
CONFIG_POWER_RESET_AS3722=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_BATTERY_SBS=y
+CONFIG_BATTERY_BQ27XXX=y
+CONFIG_CHARGER_GPIO=y
+CONFIG_CHARGER_SMB347=y
CONFIG_CHARGER_TPS65090=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM95245=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_CPU_THERMAL=y
CONFIG_WATCHDOG=y
+CONFIG_MAX77620_WATCHDOG=y
CONFIG_TEGRA_WATCHDOG=y
CONFIG_MFD_AS3722=y
-CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_DEV=y
+CONFIG_MFD_MAX77620=y
CONFIG_MFD_MAX8907=y
CONFIG_MFD_STMPE=y
CONFIG_MFD_PALMAS=y
@@ -158,6 +183,7 @@
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_AS3722=y
CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX77620=y
CONFIG_REGULATOR_MAX8907=y
CONFIG_REGULATOR_PALMAS=y
CONFIG_REGULATOR_TPS51632=y
@@ -173,7 +199,10 @@
CONFIG_DRM=y
CONFIG_DRM_NOUVEAU=m
CONFIG_DRM_TEGRA=y
+CONFIG_DRM_TEGRA_STAGING=y
+CONFIG_DRM_PANEL_LVDS=y
CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_LVDS_CODEC=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
@@ -237,6 +266,7 @@
CONFIG_RTC_DRV_AS3722=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_MAX8907=y
+CONFIG_RTC_DRV_MAX77686=y
CONFIG_RTC_DRV_PALMAS=y
CONFIG_RTC_DRV_TPS6586X=y
CONFIG_RTC_DRV_TPS65910=y
@@ -250,17 +280,26 @@
CONFIG_SERIO_NVEC_PS2=y
CONFIG_NVEC_POWER=y
CONFIG_NVEC_PAZ00=y
+CONFIG_STAGING_MEDIA=y
+CONFIG_TEGRA_VDE=y
CONFIG_TEGRA_IOMMU_GART=y
CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_ARCH_TEGRA_2x_SOC=y
CONFIG_ARCH_TEGRA_3x_SOC=y
CONFIG_ARCH_TEGRA_114_SOC=y
CONFIG_ARCH_TEGRA_124_SOC=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_ARM_TEGRA_DEVFREQ=y
+CONFIG_ARM_TEGRA20_DEVFREQ=y
CONFIG_MEMORY=y
CONFIG_IIO=y
+CONFIG_KXCJK1013=y
CONFIG_MPU3050_I2C=y
+CONFIG_INV_MPU6050_I2C=y
+CONFIG_AL3010=y
CONFIG_SENSORS_ISL29018=y
CONFIG_SENSORS_ISL29028=y
+CONFIG_AK8974=y
CONFIG_AK8975=y
CONFIG_PWM=y
CONFIG_PWM_TEGRA=y
@@ -279,6 +318,13 @@
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_LZO_COMPRESS=y
+CONFIG_PSTORE_LZ4_COMPRESS=y
+CONFIG_PSTORE_LZ4HC_COMPRESS=y
+CONFIG_PSTORE_842_COMPRESS=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_RAM=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 8223397..543f073 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -11,7 +11,6 @@
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
-# CONFIG_IOSCHED_CFQ is not set
# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_U300=y
CONFIG_MACH_U300_SPIDUMMY=y
@@ -46,7 +45,6 @@
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_ARMMMCI=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 822cddf..28dd7cf 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -12,7 +12,9 @@
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPUFREQ_DT=y
CONFIG_CPU_IDLE=y
CONFIG_ARM_U8500_CPUIDLE=y
CONFIG_VFP=y
@@ -30,6 +32,9 @@
CONFIG_IP_PNP_DHCP=y
CONFIG_NETFILTER=y
CONFIG_PHONET=y
+CONFIG_BT=y
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_BCM=y
CONFIG_CFG80211=y
CONFIG_CFG80211_DEBUGFS=y
CONFIG_MAC80211=y
@@ -42,6 +47,7 @@
CONFIG_NETDEVICES=y
CONFIG_SMSC911X=y
CONFIG_SMSC_PHY=y
+CONFIG_BRCMFMAC=m
CONFIG_CW1200=y
CONFIG_CW1200_WLAN_SDIO=y
CONFIG_INPUT_EVDEV=y
@@ -52,9 +58,11 @@
CONFIG_KEYBOARD_TC3589X=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
CONFIG_TOUCHSCREEN_BU21013=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_AB8500_PONKEY=y
+CONFIG_INPUT_GPIO_VIBRA=y
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=y
CONFIG_RMI4_F11=y
@@ -62,7 +70,9 @@
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
CONFIG_HW_RANDOM=y
+CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_STMPE=y
@@ -76,11 +86,14 @@
CONFIG_REGULATOR_AB8500=y
CONFIG_REGULATOR_GPIO=y
CONFIG_DRM=y
+CONFIG_DRM_PANEL_NOVATEK_NT35510=y
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y
+CONFIG_DRM_PANEL_SONY_ACX424AKP=y
CONFIG_DRM_LIMA=y
CONFIG_DRM_MCDE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=m
+CONFIG_BACKLIGHT_GPIO=y
CONFIG_LOGO=y
CONFIG_SOUND=y
CONFIG_SND=y
@@ -111,9 +124,12 @@
CONFIG_HSEM_U8500=y
CONFIG_IIO=y
CONFIG_IIO_SW_TRIGGER=y
+CONFIG_BMA180=y
CONFIG_IIO_ST_ACCEL_3AXIS=y
CONFIG_IIO_ST_GYRO_3AXIS=y
+CONFIG_INV_MPU6050_I2C=y
CONFIG_BH1780=y
+CONFIG_GP2AP002=y
CONFIG_AK8974=y
CONFIG_IIO_ST_MAGN_3AXIS=y
CONFIG_IIO_HRTIMER_TRIGGER=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index fe4d4b5..e7ecfb3 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -9,8 +9,6 @@
CONFIG_ARCH_VERSATILE=y
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="root=1f03 mem=32M"
CONFIG_FPE_NWFPE=y
CONFIG_VFP=y
@@ -59,7 +57,8 @@
CONFIG_DRM=y
CONFIG_DRM_PANEL_ARM_VERSATILE=y
CONFIG_DRM_PANEL_SIMPLE=y
-CONFIG_DRM_DUMB_VGA_DAC=y
+CONFIG_DRM_DISPLAY_CONNECTOR=y
+CONFIG_DRM_SIMPLE_BRIDGE=y
CONFIG_DRM_PL111=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
@@ -91,8 +90,8 @@
CONFIG_NLS_ISO8859_1=m
CONFIG_FONTS=y
CONFIG_FONT_ACORN_8x8=y
-CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig
index 2575355..c01baf7 100644
--- a/arch/arm/configs/vexpress_defconfig
+++ b/arch/arm/configs/vexpress_defconfig
@@ -15,8 +15,6 @@
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_VEXPRESS_DCSCB=y
CONFIG_ARCH_VEXPRESS_TC2_PM=y
diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
index 2ff1616..989599c 100644
--- a/arch/arm/configs/viper_defconfig
+++ b/arch/arm/configs/viper_defconfig
@@ -9,7 +9,6 @@
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_PXA=y
CONFIG_ARCH_VIPER=y
CONFIG_IWMMXT=y
diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
index aa3023c..d3b98c4 100644
--- a/arch/arm/configs/zeus_defconfig
+++ b/arch/arm/configs/zeus_defconfig
@@ -4,7 +4,6 @@
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_PXA=y
CONFIG_MACH_ARCOM_ZEUS=y
CONFIG_PCCARD=m
@@ -137,7 +136,6 @@
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_PRINTER=m
CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_PXA=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig
index c4070c1..a046a49 100644
--- a/arch/arm/configs/zx_defconfig
+++ b/arch/arm/configs/zx_defconfig
@@ -11,13 +11,11 @@
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_ZX=y
CONFIG_SOC_ZX296702=y
# CONFIG_SWP_EMULATE is not set
diff --git a/arch/arm/crypto/.gitignore b/arch/arm/crypto/.gitignore
index 31e1f53..8d7f4bc 100644
--- a/arch/arm/crypto/.gitignore
+++ b/arch/arm/crypto/.gitignore
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
aesbs-core.S
sha256-core.S
sha512-core.S
+poly1305-core.S
diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig
index 043b0b1..c9bf2df 100644
--- a/arch/arm/crypto/Kconfig
+++ b/arch/arm/crypto/Kconfig
@@ -81,7 +81,7 @@
config CRYPTO_AES_ARM_BS
tristate "Bit sliced AES using NEON instructions"
depends on KERNEL_MODE_NEON
- select CRYPTO_BLKCIPHER
+ select CRYPTO_SKCIPHER
select CRYPTO_LIB_AES
select CRYPTO_SIMD
help
@@ -97,7 +97,7 @@
config CRYPTO_AES_ARM_CE
tristate "Accelerated AES using ARMv8 Crypto Extensions"
depends on KERNEL_MODE_NEON
- select CRYPTO_BLKCIPHER
+ select CRYPTO_SKCIPHER
select CRYPTO_LIB_AES
select CRYPTO_SIMD
help
@@ -118,23 +118,35 @@
config CRYPTO_CRCT10DIF_ARM_CE
tristate "CRCT10DIF digest algorithm using PMULL instructions"
- depends on KERNEL_MODE_NEON && CRC_T10DIF
+ depends on KERNEL_MODE_NEON
+ depends on CRC_T10DIF
select CRYPTO_HASH
config CRYPTO_CRC32_ARM_CE
tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions"
- depends on KERNEL_MODE_NEON && CRC32
+ depends on KERNEL_MODE_NEON
+ depends on CRC32
select CRYPTO_HASH
config CRYPTO_CHACHA20_NEON
- tristate "NEON accelerated ChaCha stream cipher algorithms"
- depends on KERNEL_MODE_NEON
- select CRYPTO_BLKCIPHER
- select CRYPTO_CHACHA20
+ tristate "NEON and scalar accelerated ChaCha stream cipher algorithms"
+ select CRYPTO_SKCIPHER
+ select CRYPTO_ARCH_HAVE_LIB_CHACHA
+
+config CRYPTO_POLY1305_ARM
+ tristate "Accelerated scalar and SIMD Poly1305 hash implementations"
+ select CRYPTO_HASH
+ select CRYPTO_ARCH_HAVE_LIB_POLY1305
config CRYPTO_NHPOLY1305_NEON
tristate "NEON accelerated NHPoly1305 hash function (for Adiantum)"
depends on KERNEL_MODE_NEON
select CRYPTO_NHPOLY1305
+config CRYPTO_CURVE25519_NEON
+ tristate "NEON accelerated Curve25519 scalar multiplication library"
+ depends on KERNEL_MODE_NEON
+ select CRYPTO_LIB_CURVE25519_GENERIC
+ select CRYPTO_ARCH_HAVE_LIB_CURVE25519
+
endif
diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile
index 4180f3a..b745c17 100644
--- a/arch/arm/crypto/Makefile
+++ b/arch/arm/crypto/Makefile
@@ -10,34 +10,16 @@
obj-$(CONFIG_CRYPTO_SHA256_ARM) += sha256-arm.o
obj-$(CONFIG_CRYPTO_SHA512_ARM) += sha512-arm.o
obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha-neon.o
+obj-$(CONFIG_CRYPTO_POLY1305_ARM) += poly1305-arm.o
obj-$(CONFIG_CRYPTO_NHPOLY1305_NEON) += nhpoly1305-neon.o
+obj-$(CONFIG_CRYPTO_CURVE25519_NEON) += curve25519-neon.o
-ce-obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o
-ce-obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o
-crc-obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o
-
-ifneq ($(crc-obj-y)$(crc-obj-m),)
-ifeq ($(call as-instr,.arch armv8-a\n.arch_extension crc,y,n),y)
-ce-obj-y += $(crc-obj-y)
-ce-obj-m += $(crc-obj-m)
-else
-$(warning These CRC Extensions modules need binutils 2.23 or higher)
-$(warning $(crc-obj-y) $(crc-obj-m))
-endif
-endif
-
-ifneq ($(ce-obj-y)$(ce-obj-m),)
-ifeq ($(call as-instr,.fpu crypto-neon-fp-armv8,y,n),y)
-obj-y += $(ce-obj-y)
-obj-m += $(ce-obj-m)
-else
-$(warning These ARMv8 Crypto Extensions modules need binutils 2.23 or higher)
-$(warning $(ce-obj-y) $(ce-obj-m))
-endif
-endif
+obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
+obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
+obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o
+obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o
+obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o
+obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o
aes-arm-y := aes-cipher-core.o aes-cipher-glue.o
aes-arm-bs-y := aes-neonbs-core.o aes-neonbs-glue.o
@@ -53,13 +35,19 @@
ghash-arm-ce-y := ghash-ce-core.o ghash-ce-glue.o
crct10dif-arm-ce-y := crct10dif-ce-core.o crct10dif-ce-glue.o
crc32-arm-ce-y:= crc32-ce-core.o crc32-ce-glue.o
-chacha-neon-y := chacha-neon-core.o chacha-neon-glue.o
+chacha-neon-y := chacha-scalar-core.o chacha-glue.o
+chacha-neon-$(CONFIG_KERNEL_MODE_NEON) += chacha-neon-core.o
+poly1305-arm-y := poly1305-core.o poly1305-glue.o
nhpoly1305-neon-y := nh-neon-core.o nhpoly1305-neon-glue.o
+curve25519-neon-y := curve25519-core.o curve25519-glue.o
ifdef REGENERATE_ARM_CRYPTO
quiet_cmd_perl = PERL $@
cmd_perl = $(PERL) $(<) > $(@)
+$(src)/poly1305-core.S_shipped: $(src)/poly1305-armv4.pl
+ $(call cmd,perl)
+
$(src)/sha256-core.S_shipped: $(src)/sha256-armv4.pl
$(call cmd,perl)
@@ -67,4 +55,9 @@
$(call cmd,perl)
endif
-clean-files += sha256-core.S sha512-core.S
+clean-files += poly1305-core.S sha256-core.S sha512-core.S
+
+# massage the perlasm code a bit so we only get the NEON routine if we need it
+poly1305-aflags-$(CONFIG_CPU_V7) := -U__LINUX_ARM_ARCH__ -D__LINUX_ARM_ARCH__=5
+poly1305-aflags-$(CONFIG_KERNEL_MODE_NEON) := -U__LINUX_ARM_ARCH__ -D__LINUX_ARM_ARCH__=7
+AFLAGS_poly1305-core.o += $(poly1305-aflags-y)
diff --git a/arch/arm/crypto/aes-ce-glue.c b/arch/arm/crypto/aes-ce-glue.c
index cdb1a07..b668c97 100644
--- a/arch/arm/crypto/aes-ce-glue.c
+++ b/arch/arm/crypto/aes-ce-glue.c
@@ -138,14 +138,8 @@
unsigned int key_len)
{
struct crypto_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
- int ret;
- ret = ce_aes_expandkey(ctx, in_key, key_len);
- if (!ret)
- return 0;
-
- crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
- return -EINVAL;
+ return ce_aes_expandkey(ctx, in_key, key_len);
}
struct crypto_aes_xts_ctx {
@@ -167,11 +161,7 @@
if (!ret)
ret = ce_aes_expandkey(&ctx->key2, &in_key[key_len / 2],
key_len / 2);
- if (!ret)
- return 0;
-
- crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
- return -EINVAL;
+ return ret;
}
static int ecb_encrypt(struct skcipher_request *req)
diff --git a/arch/arm/crypto/aes-neonbs-core.S b/arch/arm/crypto/aes-neonbs-core.S
index cfaed4e..7d0cc7f 100644
--- a/arch/arm/crypto/aes-neonbs-core.S
+++ b/arch/arm/crypto/aes-neonbs-core.S
@@ -77,11 +77,6 @@
vldr \out\()h, \sym + 8
.endm
- .macro __adr, reg, lbl
- adr \reg, \lbl
-THUMB( orr \reg, \reg, #1 )
- .endm
-
.macro in_bs_ch, b0, b1, b2, b3, b4, b5, b6, b7
veor \b2, \b2, \b1
veor \b5, \b5, \b6
@@ -629,11 +624,11 @@
push {r4-r6, lr}
ldr r5, [sp, #16] // number of blocks
-99: __adr ip, 0f
+99: adr ip, 0f
and lr, r5, #7
cmp r5, #8
sub ip, ip, lr, lsl #2
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
vld1.8 {q0}, [r1]!
vld1.8 {q1}, [r1]!
@@ -648,11 +643,11 @@
mov rounds, r3
bl \do8
- __adr ip, 1f
+ adr ip, 1f
and lr, r5, #7
cmp r5, #8
sub ip, ip, lr, lsl #2
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
vst1.8 {\o0}, [r0]!
vst1.8 {\o1}, [r0]!
@@ -689,12 +684,12 @@
push {r4-r6, lr}
ldm ip, {r5-r6} // load args 4-5
-99: __adr ip, 0f
+99: adr ip, 0f
and lr, r5, #7
cmp r5, #8
sub ip, ip, lr, lsl #2
mov lr, r1
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
vld1.8 {q0}, [lr]!
vld1.8 {q1}, [lr]!
@@ -718,11 +713,11 @@
vmov q14, q8
vmov q15, q8
- __adr ip, 1f
+ adr ip, 1f
and lr, r5, #7
cmp r5, #8
sub ip, ip, lr, lsl #2
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
vld1.8 {q9}, [r1]!
vld1.8 {q10}, [r1]!
@@ -733,9 +728,9 @@
vld1.8 {q15}, [r1]!
W(nop)
-1: __adr ip, 2f
+1: adr ip, 2f
sub ip, ip, lr, lsl #3
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
veor q0, q0, q8
vst1.8 {q0}, [r0]!
@@ -804,13 +799,13 @@
vmov q6, q0
vmov q7, q0
- __adr ip, 0f
+ adr ip, 0f
sub lr, r5, #1
and lr, lr, #7
cmp r5, #8
sub ip, ip, lr, lsl #5
sub ip, ip, lr, lsl #2
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
next_ctr q1
next_ctr q2
@@ -824,13 +819,13 @@
mov rounds, r3
bl aesbs_encrypt8
- __adr ip, 1f
+ adr ip, 1f
and lr, r5, #7
cmp r5, #8
movgt r4, #0
ldrle r4, [sp, #40] // load final in the last round
sub ip, ip, lr, lsl #2
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
vld1.8 {q8}, [r1]!
vld1.8 {q9}, [r1]!
@@ -843,10 +838,10 @@
1: bne 2f
vld1.8 {q15}, [r1]!
-2: __adr ip, 3f
+2: adr ip, 3f
cmp r5, #8
sub ip, ip, lr, lsl #3
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
veor q0, q0, q8
vst1.8 {q0}, [r0]!
@@ -900,12 +895,12 @@
vshr.u64 d30, d31, #7
vmov q12, q14
- __adr ip, 0f
+ adr ip, 0f
and r4, r6, #7
cmp r6, #8
sub ip, ip, r4, lsl #5
mov r4, sp
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
vld1.8 {q0}, [r1]!
next_tweak q12, q14, q15, q13
@@ -961,8 +956,7 @@
push {r4-r8, lr}
mov r5, sp // preserve sp
ldrd r6, r7, [sp, #24] // get blocks and iv args
- ldr r8, [sp, #32] // reorder final tweak?
- rsb r8, r8, #1
+ rsb r8, ip, #1
sub ip, sp, #128 // make room for 8x tweak
bic ip, ip, #0xf // align sp to 16 bytes
mov sp, ip
@@ -973,12 +967,12 @@
mov rounds, r3
bl \do8
- __adr ip, 0f
+ adr ip, 0f
and lr, r6, #7
cmp r6, #8
sub ip, ip, lr, lsl #2
mov r4, sp
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
vld1.8 {q8}, [r4, :128]!
vld1.8 {q9}, [r4, :128]!
@@ -989,9 +983,9 @@
vld1.8 {q14}, [r4, :128]!
vld1.8 {q15}, [r4, :128]
-0: __adr ip, 1f
+0: adr ip, 1f
sub ip, ip, lr, lsl #3
- bxlt ip // computed goto if blocks < 8
+ movlt pc, ip // computed goto if blocks < 8
veor \o0, \o0, q8
vst1.8 {\o0}, [r0]!
@@ -1018,9 +1012,11 @@
.endm
ENTRY(aesbs_xts_encrypt)
+ mov ip, #0 // never reorder final tweak
__xts_crypt aesbs_encrypt8, q0, q1, q4, q6, q3, q7, q2, q5
ENDPROC(aesbs_xts_encrypt)
ENTRY(aesbs_xts_decrypt)
+ ldr ip, [sp, #8] // reorder final tweak?
__xts_crypt aesbs_decrypt8, q0, q1, q6, q4, q2, q7, q3, q5
ENDPROC(aesbs_xts_decrypt)
diff --git a/arch/arm/crypto/aes-neonbs-glue.c b/arch/arm/crypto/aes-neonbs-glue.c
index e85839a..f70af1d 100644
--- a/arch/arm/crypto/aes-neonbs-glue.c
+++ b/arch/arm/crypto/aes-neonbs-glue.c
@@ -8,7 +8,6 @@
#include <asm/neon.h>
#include <asm/simd.h>
#include <crypto/aes.h>
-#include <crypto/cbc.h>
#include <crypto/ctr.h>
#include <crypto/internal/simd.h>
#include <crypto/internal/skcipher.h>
@@ -20,7 +19,7 @@
MODULE_LICENSE("GPL v2");
MODULE_ALIAS_CRYPTO("ecb(aes)");
-MODULE_ALIAS_CRYPTO("cbc(aes)");
+MODULE_ALIAS_CRYPTO("cbc(aes)-all");
MODULE_ALIAS_CRYPTO("ctr(aes)");
MODULE_ALIAS_CRYPTO("xts(aes)");
@@ -49,7 +48,7 @@
struct aesbs_cbc_ctx {
struct aesbs_ctx key;
- struct crypto_cipher *enc_tfm;
+ struct crypto_skcipher *enc_tfm;
};
struct aesbs_xts_ctx {
@@ -138,20 +137,25 @@
kernel_neon_begin();
aesbs_convert_key(ctx->key.rk, rk.key_enc, ctx->key.rounds);
kernel_neon_end();
+ memzero_explicit(&rk, sizeof(rk));
- return crypto_cipher_setkey(ctx->enc_tfm, in_key, key_len);
-}
-
-static void cbc_encrypt_one(struct crypto_skcipher *tfm, const u8 *src, u8 *dst)
-{
- struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm);
-
- crypto_cipher_encrypt_one(ctx->enc_tfm, dst, src);
+ return crypto_skcipher_setkey(ctx->enc_tfm, in_key, key_len);
}
static int cbc_encrypt(struct skcipher_request *req)
{
- return crypto_cbc_encrypt_walk(req, cbc_encrypt_one);
+ struct skcipher_request *subreq = skcipher_request_ctx(req);
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+ struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm);
+
+ skcipher_request_set_tfm(subreq, ctx->enc_tfm);
+ skcipher_request_set_callback(subreq,
+ skcipher_request_flags(req),
+ NULL, NULL);
+ skcipher_request_set_crypt(subreq, req->src, req->dst,
+ req->cryptlen, req->iv);
+
+ return crypto_skcipher_encrypt(subreq);
}
static int cbc_decrypt(struct skcipher_request *req)
@@ -182,20 +186,28 @@
return err;
}
-static int cbc_init(struct crypto_tfm *tfm)
+static int cbc_init(struct crypto_skcipher *tfm)
{
- struct aesbs_cbc_ctx *ctx = crypto_tfm_ctx(tfm);
+ struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm);
+ unsigned int reqsize;
- ctx->enc_tfm = crypto_alloc_cipher("aes", 0, 0);
+ ctx->enc_tfm = crypto_alloc_skcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC |
+ CRYPTO_ALG_NEED_FALLBACK);
+ if (IS_ERR(ctx->enc_tfm))
+ return PTR_ERR(ctx->enc_tfm);
- return PTR_ERR_OR_ZERO(ctx->enc_tfm);
+ reqsize = sizeof(struct skcipher_request);
+ reqsize += crypto_skcipher_reqsize(ctx->enc_tfm);
+ crypto_skcipher_set_reqsize(tfm, reqsize);
+
+ return 0;
}
-static void cbc_exit(struct crypto_tfm *tfm)
+static void cbc_exit(struct crypto_skcipher *tfm)
{
- struct aesbs_cbc_ctx *ctx = crypto_tfm_ctx(tfm);
+ struct aesbs_cbc_ctx *ctx = crypto_skcipher_ctx(tfm);
- crypto_free_cipher(ctx->enc_tfm);
+ crypto_free_skcipher(ctx->enc_tfm);
}
static int aesbs_ctr_setkey_sync(struct crypto_skcipher *tfm, const u8 *in_key,
@@ -303,9 +315,9 @@
return aesbs_setkey(tfm, in_key, key_len);
}
-static int xts_init(struct crypto_tfm *tfm)
+static int xts_init(struct crypto_skcipher *tfm)
{
- struct aesbs_xts_ctx *ctx = crypto_tfm_ctx(tfm);
+ struct aesbs_xts_ctx *ctx = crypto_skcipher_ctx(tfm);
ctx->cts_tfm = crypto_alloc_cipher("aes", 0, 0);
if (IS_ERR(ctx->cts_tfm))
@@ -318,9 +330,9 @@
return PTR_ERR_OR_ZERO(ctx->tweak_tfm);
}
-static void xts_exit(struct crypto_tfm *tfm)
+static void xts_exit(struct crypto_skcipher *tfm)
{
- struct aesbs_xts_ctx *ctx = crypto_tfm_ctx(tfm);
+ struct aesbs_xts_ctx *ctx = crypto_skcipher_ctx(tfm);
crypto_free_cipher(ctx->tweak_tfm);
crypto_free_cipher(ctx->cts_tfm);
@@ -430,9 +442,8 @@
.base.cra_blocksize = AES_BLOCK_SIZE,
.base.cra_ctxsize = sizeof(struct aesbs_cbc_ctx),
.base.cra_module = THIS_MODULE,
- .base.cra_flags = CRYPTO_ALG_INTERNAL,
- .base.cra_init = cbc_init,
- .base.cra_exit = cbc_exit,
+ .base.cra_flags = CRYPTO_ALG_INTERNAL |
+ CRYPTO_ALG_NEED_FALLBACK,
.min_keysize = AES_MIN_KEY_SIZE,
.max_keysize = AES_MAX_KEY_SIZE,
@@ -441,6 +452,8 @@
.setkey = aesbs_cbc_setkey,
.encrypt = cbc_encrypt,
.decrypt = cbc_decrypt,
+ .init = cbc_init,
+ .exit = cbc_exit,
}, {
.base.cra_name = "__ctr(aes)",
.base.cra_driver_name = "__ctr-aes-neonbs",
@@ -482,8 +495,6 @@
.base.cra_ctxsize = sizeof(struct aesbs_xts_ctx),
.base.cra_module = THIS_MODULE,
.base.cra_flags = CRYPTO_ALG_INTERNAL,
- .base.cra_init = xts_init,
- .base.cra_exit = xts_exit,
.min_keysize = 2 * AES_MIN_KEY_SIZE,
.max_keysize = 2 * AES_MAX_KEY_SIZE,
@@ -492,6 +503,8 @@
.setkey = aesbs_xts_setkey,
.encrypt = xts_encrypt,
.decrypt = xts_decrypt,
+ .init = xts_init,
+ .exit = xts_exit,
} };
static struct simd_skcipher_alg *aes_simd_algs[ARRAY_SIZE(aes_algs)];
diff --git a/arch/arm/crypto/chacha-glue.c b/arch/arm/crypto/chacha-glue.c
new file mode 100644
index 0000000..59da6c0
--- /dev/null
+++ b/arch/arm/crypto/chacha-glue.c
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM NEON accelerated ChaCha and XChaCha stream ciphers,
+ * including ChaCha20 (RFC7539)
+ *
+ * Copyright (C) 2016-2019 Linaro, Ltd. <ard.biesheuvel@linaro.org>
+ * Copyright (C) 2015 Martin Willi
+ */
+
+#include <crypto/algapi.h>
+#include <crypto/internal/chacha.h>
+#include <crypto/internal/simd.h>
+#include <crypto/internal/skcipher.h>
+#include <linux/jump_label.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/cputype.h>
+#include <asm/hwcap.h>
+#include <asm/neon.h>
+#include <asm/simd.h>
+
+asmlinkage void chacha_block_xor_neon(const u32 *state, u8 *dst, const u8 *src,
+ int nrounds);
+asmlinkage void chacha_4block_xor_neon(const u32 *state, u8 *dst, const u8 *src,
+ int nrounds);
+asmlinkage void hchacha_block_arm(const u32 *state, u32 *out, int nrounds);
+asmlinkage void hchacha_block_neon(const u32 *state, u32 *out, int nrounds);
+
+asmlinkage void chacha_doarm(u8 *dst, const u8 *src, unsigned int bytes,
+ const u32 *state, int nrounds);
+
+static __ro_after_init DEFINE_STATIC_KEY_FALSE(use_neon);
+
+static inline bool neon_usable(void)
+{
+ return static_branch_likely(&use_neon) && crypto_simd_usable();
+}
+
+static void chacha_doneon(u32 *state, u8 *dst, const u8 *src,
+ unsigned int bytes, int nrounds)
+{
+ u8 buf[CHACHA_BLOCK_SIZE];
+
+ while (bytes >= CHACHA_BLOCK_SIZE * 4) {
+ chacha_4block_xor_neon(state, dst, src, nrounds);
+ bytes -= CHACHA_BLOCK_SIZE * 4;
+ src += CHACHA_BLOCK_SIZE * 4;
+ dst += CHACHA_BLOCK_SIZE * 4;
+ state[12] += 4;
+ }
+ while (bytes >= CHACHA_BLOCK_SIZE) {
+ chacha_block_xor_neon(state, dst, src, nrounds);
+ bytes -= CHACHA_BLOCK_SIZE;
+ src += CHACHA_BLOCK_SIZE;
+ dst += CHACHA_BLOCK_SIZE;
+ state[12]++;
+ }
+ if (bytes) {
+ memcpy(buf, src, bytes);
+ chacha_block_xor_neon(state, buf, buf, nrounds);
+ memcpy(dst, buf, bytes);
+ }
+}
+
+void hchacha_block_arch(const u32 *state, u32 *stream, int nrounds)
+{
+ if (!IS_ENABLED(CONFIG_KERNEL_MODE_NEON) || !neon_usable()) {
+ hchacha_block_arm(state, stream, nrounds);
+ } else {
+ kernel_neon_begin();
+ hchacha_block_neon(state, stream, nrounds);
+ kernel_neon_end();
+ }
+}
+EXPORT_SYMBOL(hchacha_block_arch);
+
+void chacha_init_arch(u32 *state, const u32 *key, const u8 *iv)
+{
+ chacha_init_generic(state, key, iv);
+}
+EXPORT_SYMBOL(chacha_init_arch);
+
+void chacha_crypt_arch(u32 *state, u8 *dst, const u8 *src, unsigned int bytes,
+ int nrounds)
+{
+ if (!IS_ENABLED(CONFIG_KERNEL_MODE_NEON) || !neon_usable() ||
+ bytes <= CHACHA_BLOCK_SIZE) {
+ chacha_doarm(dst, src, bytes, state, nrounds);
+ state[12] += DIV_ROUND_UP(bytes, CHACHA_BLOCK_SIZE);
+ return;
+ }
+
+ do {
+ unsigned int todo = min_t(unsigned int, bytes, SZ_4K);
+
+ kernel_neon_begin();
+ chacha_doneon(state, dst, src, todo, nrounds);
+ kernel_neon_end();
+
+ bytes -= todo;
+ src += todo;
+ dst += todo;
+ } while (bytes);
+}
+EXPORT_SYMBOL(chacha_crypt_arch);
+
+static int chacha_stream_xor(struct skcipher_request *req,
+ const struct chacha_ctx *ctx, const u8 *iv,
+ bool neon)
+{
+ struct skcipher_walk walk;
+ u32 state[16];
+ int err;
+
+ err = skcipher_walk_virt(&walk, req, false);
+
+ chacha_init_generic(state, ctx->key, iv);
+
+ while (walk.nbytes > 0) {
+ unsigned int nbytes = walk.nbytes;
+
+ if (nbytes < walk.total)
+ nbytes = round_down(nbytes, walk.stride);
+
+ if (!IS_ENABLED(CONFIG_KERNEL_MODE_NEON) || !neon) {
+ chacha_doarm(walk.dst.virt.addr, walk.src.virt.addr,
+ nbytes, state, ctx->nrounds);
+ state[12] += DIV_ROUND_UP(nbytes, CHACHA_BLOCK_SIZE);
+ } else {
+ kernel_neon_begin();
+ chacha_doneon(state, walk.dst.virt.addr,
+ walk.src.virt.addr, nbytes, ctx->nrounds);
+ kernel_neon_end();
+ }
+ err = skcipher_walk_done(&walk, walk.nbytes - nbytes);
+ }
+
+ return err;
+}
+
+static int do_chacha(struct skcipher_request *req, bool neon)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+ struct chacha_ctx *ctx = crypto_skcipher_ctx(tfm);
+
+ return chacha_stream_xor(req, ctx, req->iv, neon);
+}
+
+static int chacha_arm(struct skcipher_request *req)
+{
+ return do_chacha(req, false);
+}
+
+static int chacha_neon(struct skcipher_request *req)
+{
+ return do_chacha(req, neon_usable());
+}
+
+static int do_xchacha(struct skcipher_request *req, bool neon)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
+ struct chacha_ctx *ctx = crypto_skcipher_ctx(tfm);
+ struct chacha_ctx subctx;
+ u32 state[16];
+ u8 real_iv[16];
+
+ chacha_init_generic(state, ctx->key, req->iv);
+
+ if (!IS_ENABLED(CONFIG_KERNEL_MODE_NEON) || !neon) {
+ hchacha_block_arm(state, subctx.key, ctx->nrounds);
+ } else {
+ kernel_neon_begin();
+ hchacha_block_neon(state, subctx.key, ctx->nrounds);
+ kernel_neon_end();
+ }
+ subctx.nrounds = ctx->nrounds;
+
+ memcpy(&real_iv[0], req->iv + 24, 8);
+ memcpy(&real_iv[8], req->iv + 16, 8);
+ return chacha_stream_xor(req, &subctx, real_iv, neon);
+}
+
+static int xchacha_arm(struct skcipher_request *req)
+{
+ return do_xchacha(req, false);
+}
+
+static int xchacha_neon(struct skcipher_request *req)
+{
+ return do_xchacha(req, neon_usable());
+}
+
+static struct skcipher_alg arm_algs[] = {
+ {
+ .base.cra_name = "chacha20",
+ .base.cra_driver_name = "chacha20-arm",
+ .base.cra_priority = 200,
+ .base.cra_blocksize = 1,
+ .base.cra_ctxsize = sizeof(struct chacha_ctx),
+ .base.cra_module = THIS_MODULE,
+
+ .min_keysize = CHACHA_KEY_SIZE,
+ .max_keysize = CHACHA_KEY_SIZE,
+ .ivsize = CHACHA_IV_SIZE,
+ .chunksize = CHACHA_BLOCK_SIZE,
+ .setkey = chacha20_setkey,
+ .encrypt = chacha_arm,
+ .decrypt = chacha_arm,
+ }, {
+ .base.cra_name = "xchacha20",
+ .base.cra_driver_name = "xchacha20-arm",
+ .base.cra_priority = 200,
+ .base.cra_blocksize = 1,
+ .base.cra_ctxsize = sizeof(struct chacha_ctx),
+ .base.cra_module = THIS_MODULE,
+
+ .min_keysize = CHACHA_KEY_SIZE,
+ .max_keysize = CHACHA_KEY_SIZE,
+ .ivsize = XCHACHA_IV_SIZE,
+ .chunksize = CHACHA_BLOCK_SIZE,
+ .setkey = chacha20_setkey,
+ .encrypt = xchacha_arm,
+ .decrypt = xchacha_arm,
+ }, {
+ .base.cra_name = "xchacha12",
+ .base.cra_driver_name = "xchacha12-arm",
+ .base.cra_priority = 200,
+ .base.cra_blocksize = 1,
+ .base.cra_ctxsize = sizeof(struct chacha_ctx),
+ .base.cra_module = THIS_MODULE,
+
+ .min_keysize = CHACHA_KEY_SIZE,
+ .max_keysize = CHACHA_KEY_SIZE,
+ .ivsize = XCHACHA_IV_SIZE,
+ .chunksize = CHACHA_BLOCK_SIZE,
+ .setkey = chacha12_setkey,
+ .encrypt = xchacha_arm,
+ .decrypt = xchacha_arm,
+ },
+};
+
+static struct skcipher_alg neon_algs[] = {
+ {
+ .base.cra_name = "chacha20",
+ .base.cra_driver_name = "chacha20-neon",
+ .base.cra_priority = 300,
+ .base.cra_blocksize = 1,
+ .base.cra_ctxsize = sizeof(struct chacha_ctx),
+ .base.cra_module = THIS_MODULE,
+
+ .min_keysize = CHACHA_KEY_SIZE,
+ .max_keysize = CHACHA_KEY_SIZE,
+ .ivsize = CHACHA_IV_SIZE,
+ .chunksize = CHACHA_BLOCK_SIZE,
+ .walksize = 4 * CHACHA_BLOCK_SIZE,
+ .setkey = chacha20_setkey,
+ .encrypt = chacha_neon,
+ .decrypt = chacha_neon,
+ }, {
+ .base.cra_name = "xchacha20",
+ .base.cra_driver_name = "xchacha20-neon",
+ .base.cra_priority = 300,
+ .base.cra_blocksize = 1,
+ .base.cra_ctxsize = sizeof(struct chacha_ctx),
+ .base.cra_module = THIS_MODULE,
+
+ .min_keysize = CHACHA_KEY_SIZE,
+ .max_keysize = CHACHA_KEY_SIZE,
+ .ivsize = XCHACHA_IV_SIZE,
+ .chunksize = CHACHA_BLOCK_SIZE,
+ .walksize = 4 * CHACHA_BLOCK_SIZE,
+ .setkey = chacha20_setkey,
+ .encrypt = xchacha_neon,
+ .decrypt = xchacha_neon,
+ }, {
+ .base.cra_name = "xchacha12",
+ .base.cra_driver_name = "xchacha12-neon",
+ .base.cra_priority = 300,
+ .base.cra_blocksize = 1,
+ .base.cra_ctxsize = sizeof(struct chacha_ctx),
+ .base.cra_module = THIS_MODULE,
+
+ .min_keysize = CHACHA_KEY_SIZE,
+ .max_keysize = CHACHA_KEY_SIZE,
+ .ivsize = XCHACHA_IV_SIZE,
+ .chunksize = CHACHA_BLOCK_SIZE,
+ .walksize = 4 * CHACHA_BLOCK_SIZE,
+ .setkey = chacha12_setkey,
+ .encrypt = xchacha_neon,
+ .decrypt = xchacha_neon,
+ }
+};
+
+static int __init chacha_simd_mod_init(void)
+{
+ int err = 0;
+
+ if (IS_REACHABLE(CONFIG_CRYPTO_SKCIPHER)) {
+ err = crypto_register_skciphers(arm_algs, ARRAY_SIZE(arm_algs));
+ if (err)
+ return err;
+ }
+
+ if (IS_ENABLED(CONFIG_KERNEL_MODE_NEON) && (elf_hwcap & HWCAP_NEON)) {
+ int i;
+
+ switch (read_cpuid_part()) {
+ case ARM_CPU_PART_CORTEX_A7:
+ case ARM_CPU_PART_CORTEX_A5:
+ /*
+ * The Cortex-A7 and Cortex-A5 do not perform well with
+ * the NEON implementation but do incredibly with the
+ * scalar one and use less power.
+ */
+ for (i = 0; i < ARRAY_SIZE(neon_algs); i++)
+ neon_algs[i].base.cra_priority = 0;
+ break;
+ default:
+ static_branch_enable(&use_neon);
+ }
+
+ if (IS_REACHABLE(CONFIG_CRYPTO_SKCIPHER)) {
+ err = crypto_register_skciphers(neon_algs, ARRAY_SIZE(neon_algs));
+ if (err)
+ crypto_unregister_skciphers(arm_algs, ARRAY_SIZE(arm_algs));
+ }
+ }
+ return err;
+}
+
+static void __exit chacha_simd_mod_fini(void)
+{
+ if (IS_REACHABLE(CONFIG_CRYPTO_SKCIPHER)) {
+ crypto_unregister_skciphers(arm_algs, ARRAY_SIZE(arm_algs));
+ if (IS_ENABLED(CONFIG_KERNEL_MODE_NEON) && (elf_hwcap & HWCAP_NEON))
+ crypto_unregister_skciphers(neon_algs, ARRAY_SIZE(neon_algs));
+ }
+}
+
+module_init(chacha_simd_mod_init);
+module_exit(chacha_simd_mod_fini);
+
+MODULE_DESCRIPTION("ChaCha and XChaCha stream ciphers (scalar and NEON accelerated)");
+MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_CRYPTO("chacha20");
+MODULE_ALIAS_CRYPTO("chacha20-arm");
+MODULE_ALIAS_CRYPTO("xchacha20");
+MODULE_ALIAS_CRYPTO("xchacha20-arm");
+MODULE_ALIAS_CRYPTO("xchacha12");
+MODULE_ALIAS_CRYPTO("xchacha12-arm");
+#ifdef CONFIG_KERNEL_MODE_NEON
+MODULE_ALIAS_CRYPTO("chacha20-neon");
+MODULE_ALIAS_CRYPTO("xchacha20-neon");
+MODULE_ALIAS_CRYPTO("xchacha12-neon");
+#endif
diff --git a/arch/arm/crypto/chacha-neon-glue.c b/arch/arm/crypto/chacha-neon-glue.c
deleted file mode 100644
index a8e9b53..0000000
--- a/arch/arm/crypto/chacha-neon-glue.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * ARM NEON accelerated ChaCha and XChaCha stream ciphers,
- * including ChaCha20 (RFC7539)
- *
- * Copyright (C) 2016 Linaro, Ltd. <ard.biesheuvel@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Based on:
- * ChaCha20 256-bit cipher algorithm, RFC7539, SIMD glue code
- *
- * Copyright (C) 2015 Martin Willi
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <crypto/algapi.h>
-#include <crypto/chacha.h>
-#include <crypto/internal/simd.h>
-#include <crypto/internal/skcipher.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/hwcap.h>
-#include <asm/neon.h>
-#include <asm/simd.h>
-
-asmlinkage void chacha_block_xor_neon(const u32 *state, u8 *dst, const u8 *src,
- int nrounds);
-asmlinkage void chacha_4block_xor_neon(const u32 *state, u8 *dst, const u8 *src,
- int nrounds);
-asmlinkage void hchacha_block_neon(const u32 *state, u32 *out, int nrounds);
-
-static void chacha_doneon(u32 *state, u8 *dst, const u8 *src,
- unsigned int bytes, int nrounds)
-{
- u8 buf[CHACHA_BLOCK_SIZE];
-
- while (bytes >= CHACHA_BLOCK_SIZE * 4) {
- chacha_4block_xor_neon(state, dst, src, nrounds);
- bytes -= CHACHA_BLOCK_SIZE * 4;
- src += CHACHA_BLOCK_SIZE * 4;
- dst += CHACHA_BLOCK_SIZE * 4;
- state[12] += 4;
- }
- while (bytes >= CHACHA_BLOCK_SIZE) {
- chacha_block_xor_neon(state, dst, src, nrounds);
- bytes -= CHACHA_BLOCK_SIZE;
- src += CHACHA_BLOCK_SIZE;
- dst += CHACHA_BLOCK_SIZE;
- state[12]++;
- }
- if (bytes) {
- memcpy(buf, src, bytes);
- chacha_block_xor_neon(state, buf, buf, nrounds);
- memcpy(dst, buf, bytes);
- }
-}
-
-static int chacha_neon_stream_xor(struct skcipher_request *req,
- const struct chacha_ctx *ctx, const u8 *iv)
-{
- struct skcipher_walk walk;
- u32 state[16];
- int err;
-
- err = skcipher_walk_virt(&walk, req, false);
-
- crypto_chacha_init(state, ctx, iv);
-
- while (walk.nbytes > 0) {
- unsigned int nbytes = walk.nbytes;
-
- if (nbytes < walk.total)
- nbytes = round_down(nbytes, walk.stride);
-
- kernel_neon_begin();
- chacha_doneon(state, walk.dst.virt.addr, walk.src.virt.addr,
- nbytes, ctx->nrounds);
- kernel_neon_end();
- err = skcipher_walk_done(&walk, walk.nbytes - nbytes);
- }
-
- return err;
-}
-
-static int chacha_neon(struct skcipher_request *req)
-{
- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
- struct chacha_ctx *ctx = crypto_skcipher_ctx(tfm);
-
- if (req->cryptlen <= CHACHA_BLOCK_SIZE || !crypto_simd_usable())
- return crypto_chacha_crypt(req);
-
- return chacha_neon_stream_xor(req, ctx, req->iv);
-}
-
-static int xchacha_neon(struct skcipher_request *req)
-{
- struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
- struct chacha_ctx *ctx = crypto_skcipher_ctx(tfm);
- struct chacha_ctx subctx;
- u32 state[16];
- u8 real_iv[16];
-
- if (req->cryptlen <= CHACHA_BLOCK_SIZE || !crypto_simd_usable())
- return crypto_xchacha_crypt(req);
-
- crypto_chacha_init(state, ctx, req->iv);
-
- kernel_neon_begin();
- hchacha_block_neon(state, subctx.key, ctx->nrounds);
- kernel_neon_end();
- subctx.nrounds = ctx->nrounds;
-
- memcpy(&real_iv[0], req->iv + 24, 8);
- memcpy(&real_iv[8], req->iv + 16, 8);
- return chacha_neon_stream_xor(req, &subctx, real_iv);
-}
-
-static struct skcipher_alg algs[] = {
- {
- .base.cra_name = "chacha20",
- .base.cra_driver_name = "chacha20-neon",
- .base.cra_priority = 300,
- .base.cra_blocksize = 1,
- .base.cra_ctxsize = sizeof(struct chacha_ctx),
- .base.cra_module = THIS_MODULE,
-
- .min_keysize = CHACHA_KEY_SIZE,
- .max_keysize = CHACHA_KEY_SIZE,
- .ivsize = CHACHA_IV_SIZE,
- .chunksize = CHACHA_BLOCK_SIZE,
- .walksize = 4 * CHACHA_BLOCK_SIZE,
- .setkey = crypto_chacha20_setkey,
- .encrypt = chacha_neon,
- .decrypt = chacha_neon,
- }, {
- .base.cra_name = "xchacha20",
- .base.cra_driver_name = "xchacha20-neon",
- .base.cra_priority = 300,
- .base.cra_blocksize = 1,
- .base.cra_ctxsize = sizeof(struct chacha_ctx),
- .base.cra_module = THIS_MODULE,
-
- .min_keysize = CHACHA_KEY_SIZE,
- .max_keysize = CHACHA_KEY_SIZE,
- .ivsize = XCHACHA_IV_SIZE,
- .chunksize = CHACHA_BLOCK_SIZE,
- .walksize = 4 * CHACHA_BLOCK_SIZE,
- .setkey = crypto_chacha20_setkey,
- .encrypt = xchacha_neon,
- .decrypt = xchacha_neon,
- }, {
- .base.cra_name = "xchacha12",
- .base.cra_driver_name = "xchacha12-neon",
- .base.cra_priority = 300,
- .base.cra_blocksize = 1,
- .base.cra_ctxsize = sizeof(struct chacha_ctx),
- .base.cra_module = THIS_MODULE,
-
- .min_keysize = CHACHA_KEY_SIZE,
- .max_keysize = CHACHA_KEY_SIZE,
- .ivsize = XCHACHA_IV_SIZE,
- .chunksize = CHACHA_BLOCK_SIZE,
- .walksize = 4 * CHACHA_BLOCK_SIZE,
- .setkey = crypto_chacha12_setkey,
- .encrypt = xchacha_neon,
- .decrypt = xchacha_neon,
- }
-};
-
-static int __init chacha_simd_mod_init(void)
-{
- if (!(elf_hwcap & HWCAP_NEON))
- return -ENODEV;
-
- return crypto_register_skciphers(algs, ARRAY_SIZE(algs));
-}
-
-static void __exit chacha_simd_mod_fini(void)
-{
- crypto_unregister_skciphers(algs, ARRAY_SIZE(algs));
-}
-
-module_init(chacha_simd_mod_init);
-module_exit(chacha_simd_mod_fini);
-
-MODULE_DESCRIPTION("ChaCha and XChaCha stream ciphers (NEON accelerated)");
-MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS_CRYPTO("chacha20");
-MODULE_ALIAS_CRYPTO("chacha20-neon");
-MODULE_ALIAS_CRYPTO("xchacha20");
-MODULE_ALIAS_CRYPTO("xchacha20-neon");
-MODULE_ALIAS_CRYPTO("xchacha12");
-MODULE_ALIAS_CRYPTO("xchacha12-neon");
diff --git a/arch/arm/crypto/chacha-scalar-core.S b/arch/arm/crypto/chacha-scalar-core.S
new file mode 100644
index 0000000..2985b80
--- /dev/null
+++ b/arch/arm/crypto/chacha-scalar-core.S
@@ -0,0 +1,460 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Google, Inc.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Design notes:
+ *
+ * 16 registers would be needed to hold the state matrix, but only 14 are
+ * available because 'sp' and 'pc' cannot be used. So we spill the elements
+ * (x8, x9) to the stack and swap them out with (x10, x11). This adds one
+ * 'ldrd' and one 'strd' instruction per round.
+ *
+ * All rotates are performed using the implicit rotate operand accepted by the
+ * 'add' and 'eor' instructions. This is faster than using explicit rotate
+ * instructions. To make this work, we allow the values in the second and last
+ * rows of the ChaCha state matrix (rows 'b' and 'd') to temporarily have the
+ * wrong rotation amount. The rotation amount is then fixed up just in time
+ * when the values are used. 'brot' is the number of bits the values in row 'b'
+ * need to be rotated right to arrive at the correct values, and 'drot'
+ * similarly for row 'd'. (brot, drot) start out as (0, 0) but we make it such
+ * that they end up as (25, 24) after every round.
+ */
+
+ // ChaCha state registers
+ X0 .req r0
+ X1 .req r1
+ X2 .req r2
+ X3 .req r3
+ X4 .req r4
+ X5 .req r5
+ X6 .req r6
+ X7 .req r7
+ X8_X10 .req r8 // shared by x8 and x10
+ X9_X11 .req r9 // shared by x9 and x11
+ X12 .req r10
+ X13 .req r11
+ X14 .req r12
+ X15 .req r14
+
+.macro __rev out, in, t0, t1, t2
+.if __LINUX_ARM_ARCH__ >= 6
+ rev \out, \in
+.else
+ lsl \t0, \in, #24
+ and \t1, \in, #0xff00
+ and \t2, \in, #0xff0000
+ orr \out, \t0, \in, lsr #24
+ orr \out, \out, \t1, lsl #8
+ orr \out, \out, \t2, lsr #8
+.endif
+.endm
+
+.macro _le32_bswap x, t0, t1, t2
+#ifdef __ARMEB__
+ __rev \x, \x, \t0, \t1, \t2
+#endif
+.endm
+
+.macro _le32_bswap_4x a, b, c, d, t0, t1, t2
+ _le32_bswap \a, \t0, \t1, \t2
+ _le32_bswap \b, \t0, \t1, \t2
+ _le32_bswap \c, \t0, \t1, \t2
+ _le32_bswap \d, \t0, \t1, \t2
+.endm
+
+.macro __ldrd a, b, src, offset
+#if __LINUX_ARM_ARCH__ >= 6
+ ldrd \a, \b, [\src, #\offset]
+#else
+ ldr \a, [\src, #\offset]
+ ldr \b, [\src, #\offset + 4]
+#endif
+.endm
+
+.macro __strd a, b, dst, offset
+#if __LINUX_ARM_ARCH__ >= 6
+ strd \a, \b, [\dst, #\offset]
+#else
+ str \a, [\dst, #\offset]
+ str \b, [\dst, #\offset + 4]
+#endif
+.endm
+
+.macro _halfround a1, b1, c1, d1, a2, b2, c2, d2
+
+ // a += b; d ^= a; d = rol(d, 16);
+ add \a1, \a1, \b1, ror #brot
+ add \a2, \a2, \b2, ror #brot
+ eor \d1, \a1, \d1, ror #drot
+ eor \d2, \a2, \d2, ror #drot
+ // drot == 32 - 16 == 16
+
+ // c += d; b ^= c; b = rol(b, 12);
+ add \c1, \c1, \d1, ror #16
+ add \c2, \c2, \d2, ror #16
+ eor \b1, \c1, \b1, ror #brot
+ eor \b2, \c2, \b2, ror #brot
+ // brot == 32 - 12 == 20
+
+ // a += b; d ^= a; d = rol(d, 8);
+ add \a1, \a1, \b1, ror #20
+ add \a2, \a2, \b2, ror #20
+ eor \d1, \a1, \d1, ror #16
+ eor \d2, \a2, \d2, ror #16
+ // drot == 32 - 8 == 24
+
+ // c += d; b ^= c; b = rol(b, 7);
+ add \c1, \c1, \d1, ror #24
+ add \c2, \c2, \d2, ror #24
+ eor \b1, \c1, \b1, ror #20
+ eor \b2, \c2, \b2, ror #20
+ // brot == 32 - 7 == 25
+.endm
+
+.macro _doubleround
+
+ // column round
+
+ // quarterrounds: (x0, x4, x8, x12) and (x1, x5, x9, x13)
+ _halfround X0, X4, X8_X10, X12, X1, X5, X9_X11, X13
+
+ // save (x8, x9); restore (x10, x11)
+ __strd X8_X10, X9_X11, sp, 0
+ __ldrd X8_X10, X9_X11, sp, 8
+
+ // quarterrounds: (x2, x6, x10, x14) and (x3, x7, x11, x15)
+ _halfround X2, X6, X8_X10, X14, X3, X7, X9_X11, X15
+
+ .set brot, 25
+ .set drot, 24
+
+ // diagonal round
+
+ // quarterrounds: (x0, x5, x10, x15) and (x1, x6, x11, x12)
+ _halfround X0, X5, X8_X10, X15, X1, X6, X9_X11, X12
+
+ // save (x10, x11); restore (x8, x9)
+ __strd X8_X10, X9_X11, sp, 8
+ __ldrd X8_X10, X9_X11, sp, 0
+
+ // quarterrounds: (x2, x7, x8, x13) and (x3, x4, x9, x14)
+ _halfround X2, X7, X8_X10, X13, X3, X4, X9_X11, X14
+.endm
+
+.macro _chacha_permute nrounds
+ .set brot, 0
+ .set drot, 0
+ .rept \nrounds / 2
+ _doubleround
+ .endr
+.endm
+
+.macro _chacha nrounds
+
+.Lnext_block\@:
+ // Stack: unused0-unused1 x10-x11 x0-x15 OUT IN LEN
+ // Registers contain x0-x9,x12-x15.
+
+ // Do the core ChaCha permutation to update x0-x15.
+ _chacha_permute \nrounds
+
+ add sp, #8
+ // Stack: x10-x11 orig_x0-orig_x15 OUT IN LEN
+ // Registers contain x0-x9,x12-x15.
+ // x4-x7 are rotated by 'brot'; x12-x15 are rotated by 'drot'.
+
+ // Free up some registers (r8-r12,r14) by pushing (x8-x9,x12-x15).
+ push {X8_X10, X9_X11, X12, X13, X14, X15}
+
+ // Load (OUT, IN, LEN).
+ ldr r14, [sp, #96]
+ ldr r12, [sp, #100]
+ ldr r11, [sp, #104]
+
+ orr r10, r14, r12
+
+ // Use slow path if fewer than 64 bytes remain.
+ cmp r11, #64
+ blt .Lxor_slowpath\@
+
+ // Use slow path if IN and/or OUT isn't 4-byte aligned. Needed even on
+ // ARMv6+, since ldmia and stmia (used below) still require alignment.
+ tst r10, #3
+ bne .Lxor_slowpath\@
+
+ // Fast path: XOR 64 bytes of aligned data.
+
+ // Stack: x8-x9 x12-x15 x10-x11 orig_x0-orig_x15 OUT IN LEN
+ // Registers: r0-r7 are x0-x7; r8-r11 are free; r12 is IN; r14 is OUT.
+ // x4-x7 are rotated by 'brot'; x12-x15 are rotated by 'drot'.
+
+ // x0-x3
+ __ldrd r8, r9, sp, 32
+ __ldrd r10, r11, sp, 40
+ add X0, X0, r8
+ add X1, X1, r9
+ add X2, X2, r10
+ add X3, X3, r11
+ _le32_bswap_4x X0, X1, X2, X3, r8, r9, r10
+ ldmia r12!, {r8-r11}
+ eor X0, X0, r8
+ eor X1, X1, r9
+ eor X2, X2, r10
+ eor X3, X3, r11
+ stmia r14!, {X0-X3}
+
+ // x4-x7
+ __ldrd r8, r9, sp, 48
+ __ldrd r10, r11, sp, 56
+ add X4, r8, X4, ror #brot
+ add X5, r9, X5, ror #brot
+ ldmia r12!, {X0-X3}
+ add X6, r10, X6, ror #brot
+ add X7, r11, X7, ror #brot
+ _le32_bswap_4x X4, X5, X6, X7, r8, r9, r10
+ eor X4, X4, X0
+ eor X5, X5, X1
+ eor X6, X6, X2
+ eor X7, X7, X3
+ stmia r14!, {X4-X7}
+
+ // x8-x15
+ pop {r0-r7} // (x8-x9,x12-x15,x10-x11)
+ __ldrd r8, r9, sp, 32
+ __ldrd r10, r11, sp, 40
+ add r0, r0, r8 // x8
+ add r1, r1, r9 // x9
+ add r6, r6, r10 // x10
+ add r7, r7, r11 // x11
+ _le32_bswap_4x r0, r1, r6, r7, r8, r9, r10
+ ldmia r12!, {r8-r11}
+ eor r0, r0, r8 // x8
+ eor r1, r1, r9 // x9
+ eor r6, r6, r10 // x10
+ eor r7, r7, r11 // x11
+ stmia r14!, {r0,r1,r6,r7}
+ ldmia r12!, {r0,r1,r6,r7}
+ __ldrd r8, r9, sp, 48
+ __ldrd r10, r11, sp, 56
+ add r2, r8, r2, ror #drot // x12
+ add r3, r9, r3, ror #drot // x13
+ add r4, r10, r4, ror #drot // x14
+ add r5, r11, r5, ror #drot // x15
+ _le32_bswap_4x r2, r3, r4, r5, r9, r10, r11
+ ldr r9, [sp, #72] // load LEN
+ eor r2, r2, r0 // x12
+ eor r3, r3, r1 // x13
+ eor r4, r4, r6 // x14
+ eor r5, r5, r7 // x15
+ subs r9, #64 // decrement and check LEN
+ stmia r14!, {r2-r5}
+
+ beq .Ldone\@
+
+.Lprepare_for_next_block\@:
+
+ // Stack: x0-x15 OUT IN LEN
+
+ // Increment block counter (x12)
+ add r8, #1
+
+ // Store updated (OUT, IN, LEN)
+ str r14, [sp, #64]
+ str r12, [sp, #68]
+ str r9, [sp, #72]
+
+ mov r14, sp
+
+ // Store updated block counter (x12)
+ str r8, [sp, #48]
+
+ sub sp, #16
+
+ // Reload state and do next block
+ ldmia r14!, {r0-r11} // load x0-x11
+ __strd r10, r11, sp, 8 // store x10-x11 before state
+ ldmia r14, {r10-r12,r14} // load x12-x15
+ b .Lnext_block\@
+
+.Lxor_slowpath\@:
+ // Slow path: < 64 bytes remaining, or unaligned input or output buffer.
+ // We handle it by storing the 64 bytes of keystream to the stack, then
+ // XOR-ing the needed portion with the data.
+
+ // Allocate keystream buffer
+ sub sp, #64
+ mov r14, sp
+
+ // Stack: ks0-ks15 x8-x9 x12-x15 x10-x11 orig_x0-orig_x15 OUT IN LEN
+ // Registers: r0-r7 are x0-x7; r8-r11 are free; r12 is IN; r14 is &ks0.
+ // x4-x7 are rotated by 'brot'; x12-x15 are rotated by 'drot'.
+
+ // Save keystream for x0-x3
+ __ldrd r8, r9, sp, 96
+ __ldrd r10, r11, sp, 104
+ add X0, X0, r8
+ add X1, X1, r9
+ add X2, X2, r10
+ add X3, X3, r11
+ _le32_bswap_4x X0, X1, X2, X3, r8, r9, r10
+ stmia r14!, {X0-X3}
+
+ // Save keystream for x4-x7
+ __ldrd r8, r9, sp, 112
+ __ldrd r10, r11, sp, 120
+ add X4, r8, X4, ror #brot
+ add X5, r9, X5, ror #brot
+ add X6, r10, X6, ror #brot
+ add X7, r11, X7, ror #brot
+ _le32_bswap_4x X4, X5, X6, X7, r8, r9, r10
+ add r8, sp, #64
+ stmia r14!, {X4-X7}
+
+ // Save keystream for x8-x15
+ ldm r8, {r0-r7} // (x8-x9,x12-x15,x10-x11)
+ __ldrd r8, r9, sp, 128
+ __ldrd r10, r11, sp, 136
+ add r0, r0, r8 // x8
+ add r1, r1, r9 // x9
+ add r6, r6, r10 // x10
+ add r7, r7, r11 // x11
+ _le32_bswap_4x r0, r1, r6, r7, r8, r9, r10
+ stmia r14!, {r0,r1,r6,r7}
+ __ldrd r8, r9, sp, 144
+ __ldrd r10, r11, sp, 152
+ add r2, r8, r2, ror #drot // x12
+ add r3, r9, r3, ror #drot // x13
+ add r4, r10, r4, ror #drot // x14
+ add r5, r11, r5, ror #drot // x15
+ _le32_bswap_4x r2, r3, r4, r5, r9, r10, r11
+ stmia r14, {r2-r5}
+
+ // Stack: ks0-ks15 unused0-unused7 x0-x15 OUT IN LEN
+ // Registers: r8 is block counter, r12 is IN.
+
+ ldr r9, [sp, #168] // LEN
+ ldr r14, [sp, #160] // OUT
+ cmp r9, #64
+ mov r0, sp
+ movle r1, r9
+ movgt r1, #64
+ // r1 is number of bytes to XOR, in range [1, 64]
+
+.if __LINUX_ARM_ARCH__ < 6
+ orr r2, r12, r14
+ tst r2, #3 // IN or OUT misaligned?
+ bne .Lxor_next_byte\@
+.endif
+
+ // XOR a word at a time
+.rept 16
+ subs r1, #4
+ blt .Lxor_words_done\@
+ ldr r2, [r12], #4
+ ldr r3, [r0], #4
+ eor r2, r2, r3
+ str r2, [r14], #4
+.endr
+ b .Lxor_slowpath_done\@
+.Lxor_words_done\@:
+ ands r1, r1, #3
+ beq .Lxor_slowpath_done\@
+
+ // XOR a byte at a time
+.Lxor_next_byte\@:
+ ldrb r2, [r12], #1
+ ldrb r3, [r0], #1
+ eor r2, r2, r3
+ strb r2, [r14], #1
+ subs r1, #1
+ bne .Lxor_next_byte\@
+
+.Lxor_slowpath_done\@:
+ subs r9, #64
+ add sp, #96
+ bgt .Lprepare_for_next_block\@
+
+.Ldone\@:
+.endm // _chacha
+
+/*
+ * void chacha_doarm(u8 *dst, const u8 *src, unsigned int bytes,
+ * const u32 *state, int nrounds);
+ */
+ENTRY(chacha_doarm)
+ cmp r2, #0 // len == 0?
+ reteq lr
+
+ ldr ip, [sp]
+ cmp ip, #12
+
+ push {r0-r2,r4-r11,lr}
+
+ // Push state x0-x15 onto stack.
+ // Also store an extra copy of x10-x11 just before the state.
+
+ add X12, r3, #48
+ ldm X12, {X12,X13,X14,X15}
+ push {X12,X13,X14,X15}
+ sub sp, sp, #64
+
+ __ldrd X8_X10, X9_X11, r3, 40
+ __strd X8_X10, X9_X11, sp, 8
+ __strd X8_X10, X9_X11, sp, 56
+ ldm r3, {X0-X9_X11}
+ __strd X0, X1, sp, 16
+ __strd X2, X3, sp, 24
+ __strd X4, X5, sp, 32
+ __strd X6, X7, sp, 40
+ __strd X8_X10, X9_X11, sp, 48
+
+ beq 1f
+ _chacha 20
+
+0: add sp, #76
+ pop {r4-r11, pc}
+
+1: _chacha 12
+ b 0b
+ENDPROC(chacha_doarm)
+
+/*
+ * void hchacha_block_arm(const u32 state[16], u32 out[8], int nrounds);
+ */
+ENTRY(hchacha_block_arm)
+ push {r1,r4-r11,lr}
+
+ cmp r2, #12 // ChaCha12 ?
+
+ mov r14, r0
+ ldmia r14!, {r0-r11} // load x0-x11
+ push {r10-r11} // store x10-x11 to stack
+ ldm r14, {r10-r12,r14} // load x12-x15
+ sub sp, #8
+
+ beq 1f
+ _chacha_permute 20
+
+ // Skip over (unused0-unused1, x10-x11)
+0: add sp, #16
+
+ // Fix up rotations of x12-x15
+ ror X12, X12, #drot
+ ror X13, X13, #drot
+ pop {r4} // load 'out'
+ ror X14, X14, #drot
+ ror X15, X15, #drot
+
+ // Store (x0-x3,x12-x15) to 'out'
+ stm r4, {X0,X1,X2,X3,X12,X13,X14,X15}
+
+ pop {r4-r11,pc}
+
+1: _chacha_permute 12
+ b 0b
+ENDPROC(hchacha_block_arm)
diff --git a/arch/arm/crypto/crc32-ce-core.S b/arch/arm/crypto/crc32-ce-core.S
index 5cbd4a6..3f13a76 100644
--- a/arch/arm/crypto/crc32-ce-core.S
+++ b/arch/arm/crypto/crc32-ce-core.S
@@ -39,7 +39,7 @@
* CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE)
* PCLMULQDQ is a new instruction in Intel SSE4.2, the reference can be found
* at:
- * http://www.intel.com/products/processor/manuals/
+ * https://www.intel.com/products/processor/manuals/
* Intel(R) 64 and IA-32 Architectures Software Developer's Manual
* Volume 2B: Instruction Set Reference, N-Z
*
diff --git a/arch/arm/crypto/crc32-ce-glue.c b/arch/arm/crypto/crc32-ce-glue.c
index 9559249..2208445 100644
--- a/arch/arm/crypto/crc32-ce-glue.c
+++ b/arch/arm/crypto/crc32-ce-glue.c
@@ -54,10 +54,8 @@
{
u32 *mctx = crypto_shash_ctx(hash);
- if (keylen != sizeof(u32)) {
- crypto_shash_set_flags(hash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ if (keylen != sizeof(u32))
return -EINVAL;
- }
*mctx = le32_to_cpup((__le32 *)key);
return 0;
}
diff --git a/arch/arm/crypto/crct10dif-ce-core.S b/arch/arm/crypto/crct10dif-ce-core.S
index 86be258..46c02c5 100644
--- a/arch/arm/crypto/crct10dif-ce-core.S
+++ b/arch/arm/crypto/crct10dif-ce-core.S
@@ -72,7 +72,7 @@
#endif
.text
- .arch armv7-a
+ .arch armv8-a
.fpu crypto-neon-fp-armv8
init_crc .req r0
diff --git a/arch/arm/crypto/curve25519-core.S b/arch/arm/crypto/curve25519-core.S
new file mode 100644
index 0000000..b697fa5
--- /dev/null
+++ b/arch/arm/crypto/curve25519-core.S
@@ -0,0 +1,2062 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
+ *
+ * Based on public domain code from Daniel J. Bernstein and Peter Schwabe. This
+ * began from SUPERCOP's curve25519/neon2/scalarmult.s, but has subsequently been
+ * manually reworked for use in kernel space.
+ */
+
+#include <linux/linkage.h>
+
+.text
+.arch armv7-a
+.fpu neon
+.align 4
+
+ENTRY(curve25519_neon)
+ push {r4-r11, lr}
+ mov ip, sp
+ sub r3, sp, #704
+ and r3, r3, #0xfffffff0
+ mov sp, r3
+ movw r4, #0
+ movw r5, #254
+ vmov.i32 q0, #1
+ vshr.u64 q1, q0, #7
+ vshr.u64 q0, q0, #8
+ vmov.i32 d4, #19
+ vmov.i32 d5, #38
+ add r6, sp, #480
+ vst1.8 {d2-d3}, [r6, : 128]!
+ vst1.8 {d0-d1}, [r6, : 128]!
+ vst1.8 {d4-d5}, [r6, : 128]
+ add r6, r3, #0
+ vmov.i32 q2, #0
+ vst1.8 {d4-d5}, [r6, : 128]!
+ vst1.8 {d4-d5}, [r6, : 128]!
+ vst1.8 d4, [r6, : 64]
+ add r6, r3, #0
+ movw r7, #960
+ sub r7, r7, #2
+ neg r7, r7
+ sub r7, r7, r7, LSL #7
+ str r7, [r6]
+ add r6, sp, #672
+ vld1.8 {d4-d5}, [r1]!
+ vld1.8 {d6-d7}, [r1]
+ vst1.8 {d4-d5}, [r6, : 128]!
+ vst1.8 {d6-d7}, [r6, : 128]
+ sub r1, r6, #16
+ ldrb r6, [r1]
+ and r6, r6, #248
+ strb r6, [r1]
+ ldrb r6, [r1, #31]
+ and r6, r6, #127
+ orr r6, r6, #64
+ strb r6, [r1, #31]
+ vmov.i64 q2, #0xffffffff
+ vshr.u64 q3, q2, #7
+ vshr.u64 q2, q2, #6
+ vld1.8 {d8}, [r2]
+ vld1.8 {d10}, [r2]
+ add r2, r2, #6
+ vld1.8 {d12}, [r2]
+ vld1.8 {d14}, [r2]
+ add r2, r2, #6
+ vld1.8 {d16}, [r2]
+ add r2, r2, #4
+ vld1.8 {d18}, [r2]
+ vld1.8 {d20}, [r2]
+ add r2, r2, #6
+ vld1.8 {d22}, [r2]
+ add r2, r2, #2
+ vld1.8 {d24}, [r2]
+ vld1.8 {d26}, [r2]
+ vshr.u64 q5, q5, #26
+ vshr.u64 q6, q6, #3
+ vshr.u64 q7, q7, #29
+ vshr.u64 q8, q8, #6
+ vshr.u64 q10, q10, #25
+ vshr.u64 q11, q11, #3
+ vshr.u64 q12, q12, #12
+ vshr.u64 q13, q13, #38
+ vand q4, q4, q2
+ vand q6, q6, q2
+ vand q8, q8, q2
+ vand q10, q10, q2
+ vand q2, q12, q2
+ vand q5, q5, q3
+ vand q7, q7, q3
+ vand q9, q9, q3
+ vand q11, q11, q3
+ vand q3, q13, q3
+ add r2, r3, #48
+ vadd.i64 q12, q4, q1
+ vadd.i64 q13, q10, q1
+ vshr.s64 q12, q12, #26
+ vshr.s64 q13, q13, #26
+ vadd.i64 q5, q5, q12
+ vshl.i64 q12, q12, #26
+ vadd.i64 q14, q5, q0
+ vadd.i64 q11, q11, q13
+ vshl.i64 q13, q13, #26
+ vadd.i64 q15, q11, q0
+ vsub.i64 q4, q4, q12
+ vshr.s64 q12, q14, #25
+ vsub.i64 q10, q10, q13
+ vshr.s64 q13, q15, #25
+ vadd.i64 q6, q6, q12
+ vshl.i64 q12, q12, #25
+ vadd.i64 q14, q6, q1
+ vadd.i64 q2, q2, q13
+ vsub.i64 q5, q5, q12
+ vshr.s64 q12, q14, #26
+ vshl.i64 q13, q13, #25
+ vadd.i64 q14, q2, q1
+ vadd.i64 q7, q7, q12
+ vshl.i64 q12, q12, #26
+ vadd.i64 q15, q7, q0
+ vsub.i64 q11, q11, q13
+ vshr.s64 q13, q14, #26
+ vsub.i64 q6, q6, q12
+ vshr.s64 q12, q15, #25
+ vadd.i64 q3, q3, q13
+ vshl.i64 q13, q13, #26
+ vadd.i64 q14, q3, q0
+ vadd.i64 q8, q8, q12
+ vshl.i64 q12, q12, #25
+ vadd.i64 q15, q8, q1
+ add r2, r2, #8
+ vsub.i64 q2, q2, q13
+ vshr.s64 q13, q14, #25
+ vsub.i64 q7, q7, q12
+ vshr.s64 q12, q15, #26
+ vadd.i64 q14, q13, q13
+ vadd.i64 q9, q9, q12
+ vtrn.32 d12, d14
+ vshl.i64 q12, q12, #26
+ vtrn.32 d13, d15
+ vadd.i64 q0, q9, q0
+ vadd.i64 q4, q4, q14
+ vst1.8 d12, [r2, : 64]!
+ vshl.i64 q6, q13, #4
+ vsub.i64 q7, q8, q12
+ vshr.s64 q0, q0, #25
+ vadd.i64 q4, q4, q6
+ vadd.i64 q6, q10, q0
+ vshl.i64 q0, q0, #25
+ vadd.i64 q8, q6, q1
+ vadd.i64 q4, q4, q13
+ vshl.i64 q10, q13, #25
+ vadd.i64 q1, q4, q1
+ vsub.i64 q0, q9, q0
+ vshr.s64 q8, q8, #26
+ vsub.i64 q3, q3, q10
+ vtrn.32 d14, d0
+ vshr.s64 q1, q1, #26
+ vtrn.32 d15, d1
+ vadd.i64 q0, q11, q8
+ vst1.8 d14, [r2, : 64]
+ vshl.i64 q7, q8, #26
+ vadd.i64 q5, q5, q1
+ vtrn.32 d4, d6
+ vshl.i64 q1, q1, #26
+ vtrn.32 d5, d7
+ vsub.i64 q3, q6, q7
+ add r2, r2, #16
+ vsub.i64 q1, q4, q1
+ vst1.8 d4, [r2, : 64]
+ vtrn.32 d6, d0
+ vtrn.32 d7, d1
+ sub r2, r2, #8
+ vtrn.32 d2, d10
+ vtrn.32 d3, d11
+ vst1.8 d6, [r2, : 64]
+ sub r2, r2, #24
+ vst1.8 d2, [r2, : 64]
+ add r2, r3, #96
+ vmov.i32 q0, #0
+ vmov.i64 d2, #0xff
+ vmov.i64 d3, #0
+ vshr.u32 q1, q1, #7
+ vst1.8 {d2-d3}, [r2, : 128]!
+ vst1.8 {d0-d1}, [r2, : 128]!
+ vst1.8 d0, [r2, : 64]
+ add r2, r3, #144
+ vmov.i32 q0, #0
+ vst1.8 {d0-d1}, [r2, : 128]!
+ vst1.8 {d0-d1}, [r2, : 128]!
+ vst1.8 d0, [r2, : 64]
+ add r2, r3, #240
+ vmov.i32 q0, #0
+ vmov.i64 d2, #0xff
+ vmov.i64 d3, #0
+ vshr.u32 q1, q1, #7
+ vst1.8 {d2-d3}, [r2, : 128]!
+ vst1.8 {d0-d1}, [r2, : 128]!
+ vst1.8 d0, [r2, : 64]
+ add r2, r3, #48
+ add r6, r3, #192
+ vld1.8 {d0-d1}, [r2, : 128]!
+ vld1.8 {d2-d3}, [r2, : 128]!
+ vld1.8 {d4}, [r2, : 64]
+ vst1.8 {d0-d1}, [r6, : 128]!
+ vst1.8 {d2-d3}, [r6, : 128]!
+ vst1.8 d4, [r6, : 64]
+.Lmainloop:
+ mov r2, r5, LSR #3
+ and r6, r5, #7
+ ldrb r2, [r1, r2]
+ mov r2, r2, LSR r6
+ and r2, r2, #1
+ str r5, [sp, #456]
+ eor r4, r4, r2
+ str r2, [sp, #460]
+ neg r2, r4
+ add r4, r3, #96
+ add r5, r3, #192
+ add r6, r3, #144
+ vld1.8 {d8-d9}, [r4, : 128]!
+ add r7, r3, #240
+ vld1.8 {d10-d11}, [r5, : 128]!
+ veor q6, q4, q5
+ vld1.8 {d14-d15}, [r6, : 128]!
+ vdup.i32 q8, r2
+ vld1.8 {d18-d19}, [r7, : 128]!
+ veor q10, q7, q9
+ vld1.8 {d22-d23}, [r4, : 128]!
+ vand q6, q6, q8
+ vld1.8 {d24-d25}, [r5, : 128]!
+ vand q10, q10, q8
+ vld1.8 {d26-d27}, [r6, : 128]!
+ veor q4, q4, q6
+ vld1.8 {d28-d29}, [r7, : 128]!
+ veor q5, q5, q6
+ vld1.8 {d0}, [r4, : 64]
+ veor q6, q7, q10
+ vld1.8 {d2}, [r5, : 64]
+ veor q7, q9, q10
+ vld1.8 {d4}, [r6, : 64]
+ veor q9, q11, q12
+ vld1.8 {d6}, [r7, : 64]
+ veor q10, q0, q1
+ sub r2, r4, #32
+ vand q9, q9, q8
+ sub r4, r5, #32
+ vand q10, q10, q8
+ sub r5, r6, #32
+ veor q11, q11, q9
+ sub r6, r7, #32
+ veor q0, q0, q10
+ veor q9, q12, q9
+ veor q1, q1, q10
+ veor q10, q13, q14
+ veor q12, q2, q3
+ vand q10, q10, q8
+ vand q8, q12, q8
+ veor q12, q13, q10
+ veor q2, q2, q8
+ veor q10, q14, q10
+ veor q3, q3, q8
+ vadd.i32 q8, q4, q6
+ vsub.i32 q4, q4, q6
+ vst1.8 {d16-d17}, [r2, : 128]!
+ vadd.i32 q6, q11, q12
+ vst1.8 {d8-d9}, [r5, : 128]!
+ vsub.i32 q4, q11, q12
+ vst1.8 {d12-d13}, [r2, : 128]!
+ vadd.i32 q6, q0, q2
+ vst1.8 {d8-d9}, [r5, : 128]!
+ vsub.i32 q0, q0, q2
+ vst1.8 d12, [r2, : 64]
+ vadd.i32 q2, q5, q7
+ vst1.8 d0, [r5, : 64]
+ vsub.i32 q0, q5, q7
+ vst1.8 {d4-d5}, [r4, : 128]!
+ vadd.i32 q2, q9, q10
+ vst1.8 {d0-d1}, [r6, : 128]!
+ vsub.i32 q0, q9, q10
+ vst1.8 {d4-d5}, [r4, : 128]!
+ vadd.i32 q2, q1, q3
+ vst1.8 {d0-d1}, [r6, : 128]!
+ vsub.i32 q0, q1, q3
+ vst1.8 d4, [r4, : 64]
+ vst1.8 d0, [r6, : 64]
+ add r2, sp, #512
+ add r4, r3, #96
+ add r5, r3, #144
+ vld1.8 {d0-d1}, [r2, : 128]
+ vld1.8 {d2-d3}, [r4, : 128]!
+ vld1.8 {d4-d5}, [r5, : 128]!
+ vzip.i32 q1, q2
+ vld1.8 {d6-d7}, [r4, : 128]!
+ vld1.8 {d8-d9}, [r5, : 128]!
+ vshl.i32 q5, q1, #1
+ vzip.i32 q3, q4
+ vshl.i32 q6, q2, #1
+ vld1.8 {d14}, [r4, : 64]
+ vshl.i32 q8, q3, #1
+ vld1.8 {d15}, [r5, : 64]
+ vshl.i32 q9, q4, #1
+ vmul.i32 d21, d7, d1
+ vtrn.32 d14, d15
+ vmul.i32 q11, q4, q0
+ vmul.i32 q0, q7, q0
+ vmull.s32 q12, d2, d2
+ vmlal.s32 q12, d11, d1
+ vmlal.s32 q12, d12, d0
+ vmlal.s32 q12, d13, d23
+ vmlal.s32 q12, d16, d22
+ vmlal.s32 q12, d7, d21
+ vmull.s32 q10, d2, d11
+ vmlal.s32 q10, d4, d1
+ vmlal.s32 q10, d13, d0
+ vmlal.s32 q10, d6, d23
+ vmlal.s32 q10, d17, d22
+ vmull.s32 q13, d10, d4
+ vmlal.s32 q13, d11, d3
+ vmlal.s32 q13, d13, d1
+ vmlal.s32 q13, d16, d0
+ vmlal.s32 q13, d17, d23
+ vmlal.s32 q13, d8, d22
+ vmull.s32 q1, d10, d5
+ vmlal.s32 q1, d11, d4
+ vmlal.s32 q1, d6, d1
+ vmlal.s32 q1, d17, d0
+ vmlal.s32 q1, d8, d23
+ vmull.s32 q14, d10, d6
+ vmlal.s32 q14, d11, d13
+ vmlal.s32 q14, d4, d4
+ vmlal.s32 q14, d17, d1
+ vmlal.s32 q14, d18, d0
+ vmlal.s32 q14, d9, d23
+ vmull.s32 q11, d10, d7
+ vmlal.s32 q11, d11, d6
+ vmlal.s32 q11, d12, d5
+ vmlal.s32 q11, d8, d1
+ vmlal.s32 q11, d19, d0
+ vmull.s32 q15, d10, d8
+ vmlal.s32 q15, d11, d17
+ vmlal.s32 q15, d12, d6
+ vmlal.s32 q15, d13, d5
+ vmlal.s32 q15, d19, d1
+ vmlal.s32 q15, d14, d0
+ vmull.s32 q2, d10, d9
+ vmlal.s32 q2, d11, d8
+ vmlal.s32 q2, d12, d7
+ vmlal.s32 q2, d13, d6
+ vmlal.s32 q2, d14, d1
+ vmull.s32 q0, d15, d1
+ vmlal.s32 q0, d10, d14
+ vmlal.s32 q0, d11, d19
+ vmlal.s32 q0, d12, d8
+ vmlal.s32 q0, d13, d17
+ vmlal.s32 q0, d6, d6
+ add r2, sp, #480
+ vld1.8 {d18-d19}, [r2, : 128]!
+ vmull.s32 q3, d16, d7
+ vmlal.s32 q3, d10, d15
+ vmlal.s32 q3, d11, d14
+ vmlal.s32 q3, d12, d9
+ vmlal.s32 q3, d13, d8
+ vld1.8 {d8-d9}, [r2, : 128]
+ vadd.i64 q5, q12, q9
+ vadd.i64 q6, q15, q9
+ vshr.s64 q5, q5, #26
+ vshr.s64 q6, q6, #26
+ vadd.i64 q7, q10, q5
+ vshl.i64 q5, q5, #26
+ vadd.i64 q8, q7, q4
+ vadd.i64 q2, q2, q6
+ vshl.i64 q6, q6, #26
+ vadd.i64 q10, q2, q4
+ vsub.i64 q5, q12, q5
+ vshr.s64 q8, q8, #25
+ vsub.i64 q6, q15, q6
+ vshr.s64 q10, q10, #25
+ vadd.i64 q12, q13, q8
+ vshl.i64 q8, q8, #25
+ vadd.i64 q13, q12, q9
+ vadd.i64 q0, q0, q10
+ vsub.i64 q7, q7, q8
+ vshr.s64 q8, q13, #26
+ vshl.i64 q10, q10, #25
+ vadd.i64 q13, q0, q9
+ vadd.i64 q1, q1, q8
+ vshl.i64 q8, q8, #26
+ vadd.i64 q15, q1, q4
+ vsub.i64 q2, q2, q10
+ vshr.s64 q10, q13, #26
+ vsub.i64 q8, q12, q8
+ vshr.s64 q12, q15, #25
+ vadd.i64 q3, q3, q10
+ vshl.i64 q10, q10, #26
+ vadd.i64 q13, q3, q4
+ vadd.i64 q14, q14, q12
+ add r2, r3, #288
+ vshl.i64 q12, q12, #25
+ add r4, r3, #336
+ vadd.i64 q15, q14, q9
+ add r2, r2, #8
+ vsub.i64 q0, q0, q10
+ add r4, r4, #8
+ vshr.s64 q10, q13, #25
+ vsub.i64 q1, q1, q12
+ vshr.s64 q12, q15, #26
+ vadd.i64 q13, q10, q10
+ vadd.i64 q11, q11, q12
+ vtrn.32 d16, d2
+ vshl.i64 q12, q12, #26
+ vtrn.32 d17, d3
+ vadd.i64 q1, q11, q4
+ vadd.i64 q4, q5, q13
+ vst1.8 d16, [r2, : 64]!
+ vshl.i64 q5, q10, #4
+ vst1.8 d17, [r4, : 64]!
+ vsub.i64 q8, q14, q12
+ vshr.s64 q1, q1, #25
+ vadd.i64 q4, q4, q5
+ vadd.i64 q5, q6, q1
+ vshl.i64 q1, q1, #25
+ vadd.i64 q6, q5, q9
+ vadd.i64 q4, q4, q10
+ vshl.i64 q10, q10, #25
+ vadd.i64 q9, q4, q9
+ vsub.i64 q1, q11, q1
+ vshr.s64 q6, q6, #26
+ vsub.i64 q3, q3, q10
+ vtrn.32 d16, d2
+ vshr.s64 q9, q9, #26
+ vtrn.32 d17, d3
+ vadd.i64 q1, q2, q6
+ vst1.8 d16, [r2, : 64]
+ vshl.i64 q2, q6, #26
+ vst1.8 d17, [r4, : 64]
+ vadd.i64 q6, q7, q9
+ vtrn.32 d0, d6
+ vshl.i64 q7, q9, #26
+ vtrn.32 d1, d7
+ vsub.i64 q2, q5, q2
+ add r2, r2, #16
+ vsub.i64 q3, q4, q7
+ vst1.8 d0, [r2, : 64]
+ add r4, r4, #16
+ vst1.8 d1, [r4, : 64]
+ vtrn.32 d4, d2
+ vtrn.32 d5, d3
+ sub r2, r2, #8
+ sub r4, r4, #8
+ vtrn.32 d6, d12
+ vtrn.32 d7, d13
+ vst1.8 d4, [r2, : 64]
+ vst1.8 d5, [r4, : 64]
+ sub r2, r2, #24
+ sub r4, r4, #24
+ vst1.8 d6, [r2, : 64]
+ vst1.8 d7, [r4, : 64]
+ add r2, r3, #240
+ add r4, r3, #96
+ vld1.8 {d0-d1}, [r4, : 128]!
+ vld1.8 {d2-d3}, [r4, : 128]!
+ vld1.8 {d4}, [r4, : 64]
+ add r4, r3, #144
+ vld1.8 {d6-d7}, [r4, : 128]!
+ vtrn.32 q0, q3
+ vld1.8 {d8-d9}, [r4, : 128]!
+ vshl.i32 q5, q0, #4
+ vtrn.32 q1, q4
+ vshl.i32 q6, q3, #4
+ vadd.i32 q5, q5, q0
+ vadd.i32 q6, q6, q3
+ vshl.i32 q7, q1, #4
+ vld1.8 {d5}, [r4, : 64]
+ vshl.i32 q8, q4, #4
+ vtrn.32 d4, d5
+ vadd.i32 q7, q7, q1
+ vadd.i32 q8, q8, q4
+ vld1.8 {d18-d19}, [r2, : 128]!
+ vshl.i32 q10, q2, #4
+ vld1.8 {d22-d23}, [r2, : 128]!
+ vadd.i32 q10, q10, q2
+ vld1.8 {d24}, [r2, : 64]
+ vadd.i32 q5, q5, q0
+ add r2, r3, #192
+ vld1.8 {d26-d27}, [r2, : 128]!
+ vadd.i32 q6, q6, q3
+ vld1.8 {d28-d29}, [r2, : 128]!
+ vadd.i32 q8, q8, q4
+ vld1.8 {d25}, [r2, : 64]
+ vadd.i32 q10, q10, q2
+ vtrn.32 q9, q13
+ vadd.i32 q7, q7, q1
+ vadd.i32 q5, q5, q0
+ vtrn.32 q11, q14
+ vadd.i32 q6, q6, q3
+ add r2, sp, #528
+ vadd.i32 q10, q10, q2
+ vtrn.32 d24, d25
+ vst1.8 {d12-d13}, [r2, : 128]!
+ vshl.i32 q6, q13, #1
+ vst1.8 {d20-d21}, [r2, : 128]!
+ vshl.i32 q10, q14, #1
+ vst1.8 {d12-d13}, [r2, : 128]!
+ vshl.i32 q15, q12, #1
+ vadd.i32 q8, q8, q4
+ vext.32 d10, d31, d30, #0
+ vadd.i32 q7, q7, q1
+ vst1.8 {d16-d17}, [r2, : 128]!
+ vmull.s32 q8, d18, d5
+ vmlal.s32 q8, d26, d4
+ vmlal.s32 q8, d19, d9
+ vmlal.s32 q8, d27, d3
+ vmlal.s32 q8, d22, d8
+ vmlal.s32 q8, d28, d2
+ vmlal.s32 q8, d23, d7
+ vmlal.s32 q8, d29, d1
+ vmlal.s32 q8, d24, d6
+ vmlal.s32 q8, d25, d0
+ vst1.8 {d14-d15}, [r2, : 128]!
+ vmull.s32 q2, d18, d4
+ vmlal.s32 q2, d12, d9
+ vmlal.s32 q2, d13, d8
+ vmlal.s32 q2, d19, d3
+ vmlal.s32 q2, d22, d2
+ vmlal.s32 q2, d23, d1
+ vmlal.s32 q2, d24, d0
+ vst1.8 {d20-d21}, [r2, : 128]!
+ vmull.s32 q7, d18, d9
+ vmlal.s32 q7, d26, d3
+ vmlal.s32 q7, d19, d8
+ vmlal.s32 q7, d27, d2
+ vmlal.s32 q7, d22, d7
+ vmlal.s32 q7, d28, d1
+ vmlal.s32 q7, d23, d6
+ vmlal.s32 q7, d29, d0
+ vst1.8 {d10-d11}, [r2, : 128]!
+ vmull.s32 q5, d18, d3
+ vmlal.s32 q5, d19, d2
+ vmlal.s32 q5, d22, d1
+ vmlal.s32 q5, d23, d0
+ vmlal.s32 q5, d12, d8
+ vst1.8 {d16-d17}, [r2, : 128]
+ vmull.s32 q4, d18, d8
+ vmlal.s32 q4, d26, d2
+ vmlal.s32 q4, d19, d7
+ vmlal.s32 q4, d27, d1
+ vmlal.s32 q4, d22, d6
+ vmlal.s32 q4, d28, d0
+ vmull.s32 q8, d18, d7
+ vmlal.s32 q8, d26, d1
+ vmlal.s32 q8, d19, d6
+ vmlal.s32 q8, d27, d0
+ add r2, sp, #544
+ vld1.8 {d20-d21}, [r2, : 128]
+ vmlal.s32 q7, d24, d21
+ vmlal.s32 q7, d25, d20
+ vmlal.s32 q4, d23, d21
+ vmlal.s32 q4, d29, d20
+ vmlal.s32 q8, d22, d21
+ vmlal.s32 q8, d28, d20
+ vmlal.s32 q5, d24, d20
+ vst1.8 {d14-d15}, [r2, : 128]
+ vmull.s32 q7, d18, d6
+ vmlal.s32 q7, d26, d0
+ add r2, sp, #624
+ vld1.8 {d30-d31}, [r2, : 128]
+ vmlal.s32 q2, d30, d21
+ vmlal.s32 q7, d19, d21
+ vmlal.s32 q7, d27, d20
+ add r2, sp, #592
+ vld1.8 {d26-d27}, [r2, : 128]
+ vmlal.s32 q4, d25, d27
+ vmlal.s32 q8, d29, d27
+ vmlal.s32 q8, d25, d26
+ vmlal.s32 q7, d28, d27
+ vmlal.s32 q7, d29, d26
+ add r2, sp, #576
+ vld1.8 {d28-d29}, [r2, : 128]
+ vmlal.s32 q4, d24, d29
+ vmlal.s32 q8, d23, d29
+ vmlal.s32 q8, d24, d28
+ vmlal.s32 q7, d22, d29
+ vmlal.s32 q7, d23, d28
+ vst1.8 {d8-d9}, [r2, : 128]
+ add r2, sp, #528
+ vld1.8 {d8-d9}, [r2, : 128]
+ vmlal.s32 q7, d24, d9
+ vmlal.s32 q7, d25, d31
+ vmull.s32 q1, d18, d2
+ vmlal.s32 q1, d19, d1
+ vmlal.s32 q1, d22, d0
+ vmlal.s32 q1, d24, d27
+ vmlal.s32 q1, d23, d20
+ vmlal.s32 q1, d12, d7
+ vmlal.s32 q1, d13, d6
+ vmull.s32 q6, d18, d1
+ vmlal.s32 q6, d19, d0
+ vmlal.s32 q6, d23, d27
+ vmlal.s32 q6, d22, d20
+ vmlal.s32 q6, d24, d26
+ vmull.s32 q0, d18, d0
+ vmlal.s32 q0, d22, d27
+ vmlal.s32 q0, d23, d26
+ vmlal.s32 q0, d24, d31
+ vmlal.s32 q0, d19, d20
+ add r2, sp, #608
+ vld1.8 {d18-d19}, [r2, : 128]
+ vmlal.s32 q2, d18, d7
+ vmlal.s32 q5, d18, d6
+ vmlal.s32 q1, d18, d21
+ vmlal.s32 q0, d18, d28
+ vmlal.s32 q6, d18, d29
+ vmlal.s32 q2, d19, d6
+ vmlal.s32 q5, d19, d21
+ vmlal.s32 q1, d19, d29
+ vmlal.s32 q0, d19, d9
+ vmlal.s32 q6, d19, d28
+ add r2, sp, #560
+ vld1.8 {d18-d19}, [r2, : 128]
+ add r2, sp, #480
+ vld1.8 {d22-d23}, [r2, : 128]
+ vmlal.s32 q5, d19, d7
+ vmlal.s32 q0, d18, d21
+ vmlal.s32 q0, d19, d29
+ vmlal.s32 q6, d18, d6
+ add r2, sp, #496
+ vld1.8 {d6-d7}, [r2, : 128]
+ vmlal.s32 q6, d19, d21
+ add r2, sp, #544
+ vld1.8 {d18-d19}, [r2, : 128]
+ vmlal.s32 q0, d30, d8
+ add r2, sp, #640
+ vld1.8 {d20-d21}, [r2, : 128]
+ vmlal.s32 q5, d30, d29
+ add r2, sp, #576
+ vld1.8 {d24-d25}, [r2, : 128]
+ vmlal.s32 q1, d30, d28
+ vadd.i64 q13, q0, q11
+ vadd.i64 q14, q5, q11
+ vmlal.s32 q6, d30, d9
+ vshr.s64 q4, q13, #26
+ vshr.s64 q13, q14, #26
+ vadd.i64 q7, q7, q4
+ vshl.i64 q4, q4, #26
+ vadd.i64 q14, q7, q3
+ vadd.i64 q9, q9, q13
+ vshl.i64 q13, q13, #26
+ vadd.i64 q15, q9, q3
+ vsub.i64 q0, q0, q4
+ vshr.s64 q4, q14, #25
+ vsub.i64 q5, q5, q13
+ vshr.s64 q13, q15, #25
+ vadd.i64 q6, q6, q4
+ vshl.i64 q4, q4, #25
+ vadd.i64 q14, q6, q11
+ vadd.i64 q2, q2, q13
+ vsub.i64 q4, q7, q4
+ vshr.s64 q7, q14, #26
+ vshl.i64 q13, q13, #25
+ vadd.i64 q14, q2, q11
+ vadd.i64 q8, q8, q7
+ vshl.i64 q7, q7, #26
+ vadd.i64 q15, q8, q3
+ vsub.i64 q9, q9, q13
+ vshr.s64 q13, q14, #26
+ vsub.i64 q6, q6, q7
+ vshr.s64 q7, q15, #25
+ vadd.i64 q10, q10, q13
+ vshl.i64 q13, q13, #26
+ vadd.i64 q14, q10, q3
+ vadd.i64 q1, q1, q7
+ add r2, r3, #144
+ vshl.i64 q7, q7, #25
+ add r4, r3, #96
+ vadd.i64 q15, q1, q11
+ add r2, r2, #8
+ vsub.i64 q2, q2, q13
+ add r4, r4, #8
+ vshr.s64 q13, q14, #25
+ vsub.i64 q7, q8, q7
+ vshr.s64 q8, q15, #26
+ vadd.i64 q14, q13, q13
+ vadd.i64 q12, q12, q8
+ vtrn.32 d12, d14
+ vshl.i64 q8, q8, #26
+ vtrn.32 d13, d15
+ vadd.i64 q3, q12, q3
+ vadd.i64 q0, q0, q14
+ vst1.8 d12, [r2, : 64]!
+ vshl.i64 q7, q13, #4
+ vst1.8 d13, [r4, : 64]!
+ vsub.i64 q1, q1, q8
+ vshr.s64 q3, q3, #25
+ vadd.i64 q0, q0, q7
+ vadd.i64 q5, q5, q3
+ vshl.i64 q3, q3, #25
+ vadd.i64 q6, q5, q11
+ vadd.i64 q0, q0, q13
+ vshl.i64 q7, q13, #25
+ vadd.i64 q8, q0, q11
+ vsub.i64 q3, q12, q3
+ vshr.s64 q6, q6, #26
+ vsub.i64 q7, q10, q7
+ vtrn.32 d2, d6
+ vshr.s64 q8, q8, #26
+ vtrn.32 d3, d7
+ vadd.i64 q3, q9, q6
+ vst1.8 d2, [r2, : 64]
+ vshl.i64 q6, q6, #26
+ vst1.8 d3, [r4, : 64]
+ vadd.i64 q1, q4, q8
+ vtrn.32 d4, d14
+ vshl.i64 q4, q8, #26
+ vtrn.32 d5, d15
+ vsub.i64 q5, q5, q6
+ add r2, r2, #16
+ vsub.i64 q0, q0, q4
+ vst1.8 d4, [r2, : 64]
+ add r4, r4, #16
+ vst1.8 d5, [r4, : 64]
+ vtrn.32 d10, d6
+ vtrn.32 d11, d7
+ sub r2, r2, #8
+ sub r4, r4, #8
+ vtrn.32 d0, d2
+ vtrn.32 d1, d3
+ vst1.8 d10, [r2, : 64]
+ vst1.8 d11, [r4, : 64]
+ sub r2, r2, #24
+ sub r4, r4, #24
+ vst1.8 d0, [r2, : 64]
+ vst1.8 d1, [r4, : 64]
+ add r2, r3, #288
+ add r4, r3, #336
+ vld1.8 {d0-d1}, [r2, : 128]!
+ vld1.8 {d2-d3}, [r4, : 128]!
+ vsub.i32 q0, q0, q1
+ vld1.8 {d2-d3}, [r2, : 128]!
+ vld1.8 {d4-d5}, [r4, : 128]!
+ vsub.i32 q1, q1, q2
+ add r5, r3, #240
+ vld1.8 {d4}, [r2, : 64]
+ vld1.8 {d6}, [r4, : 64]
+ vsub.i32 q2, q2, q3
+ vst1.8 {d0-d1}, [r5, : 128]!
+ vst1.8 {d2-d3}, [r5, : 128]!
+ vst1.8 d4, [r5, : 64]
+ add r2, r3, #144
+ add r4, r3, #96
+ add r5, r3, #144
+ add r6, r3, #192
+ vld1.8 {d0-d1}, [r2, : 128]!
+ vld1.8 {d2-d3}, [r4, : 128]!
+ vsub.i32 q2, q0, q1
+ vadd.i32 q0, q0, q1
+ vld1.8 {d2-d3}, [r2, : 128]!
+ vld1.8 {d6-d7}, [r4, : 128]!
+ vsub.i32 q4, q1, q3
+ vadd.i32 q1, q1, q3
+ vld1.8 {d6}, [r2, : 64]
+ vld1.8 {d10}, [r4, : 64]
+ vsub.i32 q6, q3, q5
+ vadd.i32 q3, q3, q5
+ vst1.8 {d4-d5}, [r5, : 128]!
+ vst1.8 {d0-d1}, [r6, : 128]!
+ vst1.8 {d8-d9}, [r5, : 128]!
+ vst1.8 {d2-d3}, [r6, : 128]!
+ vst1.8 d12, [r5, : 64]
+ vst1.8 d6, [r6, : 64]
+ add r2, r3, #0
+ add r4, r3, #240
+ vld1.8 {d0-d1}, [r4, : 128]!
+ vld1.8 {d2-d3}, [r4, : 128]!
+ vld1.8 {d4}, [r4, : 64]
+ add r4, r3, #336
+ vld1.8 {d6-d7}, [r4, : 128]!
+ vtrn.32 q0, q3
+ vld1.8 {d8-d9}, [r4, : 128]!
+ vshl.i32 q5, q0, #4
+ vtrn.32 q1, q4
+ vshl.i32 q6, q3, #4
+ vadd.i32 q5, q5, q0
+ vadd.i32 q6, q6, q3
+ vshl.i32 q7, q1, #4
+ vld1.8 {d5}, [r4, : 64]
+ vshl.i32 q8, q4, #4
+ vtrn.32 d4, d5
+ vadd.i32 q7, q7, q1
+ vadd.i32 q8, q8, q4
+ vld1.8 {d18-d19}, [r2, : 128]!
+ vshl.i32 q10, q2, #4
+ vld1.8 {d22-d23}, [r2, : 128]!
+ vadd.i32 q10, q10, q2
+ vld1.8 {d24}, [r2, : 64]
+ vadd.i32 q5, q5, q0
+ add r2, r3, #288
+ vld1.8 {d26-d27}, [r2, : 128]!
+ vadd.i32 q6, q6, q3
+ vld1.8 {d28-d29}, [r2, : 128]!
+ vadd.i32 q8, q8, q4
+ vld1.8 {d25}, [r2, : 64]
+ vadd.i32 q10, q10, q2
+ vtrn.32 q9, q13
+ vadd.i32 q7, q7, q1
+ vadd.i32 q5, q5, q0
+ vtrn.32 q11, q14
+ vadd.i32 q6, q6, q3
+ add r2, sp, #528
+ vadd.i32 q10, q10, q2
+ vtrn.32 d24, d25
+ vst1.8 {d12-d13}, [r2, : 128]!
+ vshl.i32 q6, q13, #1
+ vst1.8 {d20-d21}, [r2, : 128]!
+ vshl.i32 q10, q14, #1
+ vst1.8 {d12-d13}, [r2, : 128]!
+ vshl.i32 q15, q12, #1
+ vadd.i32 q8, q8, q4
+ vext.32 d10, d31, d30, #0
+ vadd.i32 q7, q7, q1
+ vst1.8 {d16-d17}, [r2, : 128]!
+ vmull.s32 q8, d18, d5
+ vmlal.s32 q8, d26, d4
+ vmlal.s32 q8, d19, d9
+ vmlal.s32 q8, d27, d3
+ vmlal.s32 q8, d22, d8
+ vmlal.s32 q8, d28, d2
+ vmlal.s32 q8, d23, d7
+ vmlal.s32 q8, d29, d1
+ vmlal.s32 q8, d24, d6
+ vmlal.s32 q8, d25, d0
+ vst1.8 {d14-d15}, [r2, : 128]!
+ vmull.s32 q2, d18, d4
+ vmlal.s32 q2, d12, d9
+ vmlal.s32 q2, d13, d8
+ vmlal.s32 q2, d19, d3
+ vmlal.s32 q2, d22, d2
+ vmlal.s32 q2, d23, d1
+ vmlal.s32 q2, d24, d0
+ vst1.8 {d20-d21}, [r2, : 128]!
+ vmull.s32 q7, d18, d9
+ vmlal.s32 q7, d26, d3
+ vmlal.s32 q7, d19, d8
+ vmlal.s32 q7, d27, d2
+ vmlal.s32 q7, d22, d7
+ vmlal.s32 q7, d28, d1
+ vmlal.s32 q7, d23, d6
+ vmlal.s32 q7, d29, d0
+ vst1.8 {d10-d11}, [r2, : 128]!
+ vmull.s32 q5, d18, d3
+ vmlal.s32 q5, d19, d2
+ vmlal.s32 q5, d22, d1
+ vmlal.s32 q5, d23, d0
+ vmlal.s32 q5, d12, d8
+ vst1.8 {d16-d17}, [r2, : 128]!
+ vmull.s32 q4, d18, d8
+ vmlal.s32 q4, d26, d2
+ vmlal.s32 q4, d19, d7
+ vmlal.s32 q4, d27, d1
+ vmlal.s32 q4, d22, d6
+ vmlal.s32 q4, d28, d0
+ vmull.s32 q8, d18, d7
+ vmlal.s32 q8, d26, d1
+ vmlal.s32 q8, d19, d6
+ vmlal.s32 q8, d27, d0
+ add r2, sp, #544
+ vld1.8 {d20-d21}, [r2, : 128]
+ vmlal.s32 q7, d24, d21
+ vmlal.s32 q7, d25, d20
+ vmlal.s32 q4, d23, d21
+ vmlal.s32 q4, d29, d20
+ vmlal.s32 q8, d22, d21
+ vmlal.s32 q8, d28, d20
+ vmlal.s32 q5, d24, d20
+ vst1.8 {d14-d15}, [r2, : 128]
+ vmull.s32 q7, d18, d6
+ vmlal.s32 q7, d26, d0
+ add r2, sp, #624
+ vld1.8 {d30-d31}, [r2, : 128]
+ vmlal.s32 q2, d30, d21
+ vmlal.s32 q7, d19, d21
+ vmlal.s32 q7, d27, d20
+ add r2, sp, #592
+ vld1.8 {d26-d27}, [r2, : 128]
+ vmlal.s32 q4, d25, d27
+ vmlal.s32 q8, d29, d27
+ vmlal.s32 q8, d25, d26
+ vmlal.s32 q7, d28, d27
+ vmlal.s32 q7, d29, d26
+ add r2, sp, #576
+ vld1.8 {d28-d29}, [r2, : 128]
+ vmlal.s32 q4, d24, d29
+ vmlal.s32 q8, d23, d29
+ vmlal.s32 q8, d24, d28
+ vmlal.s32 q7, d22, d29
+ vmlal.s32 q7, d23, d28
+ vst1.8 {d8-d9}, [r2, : 128]
+ add r2, sp, #528
+ vld1.8 {d8-d9}, [r2, : 128]
+ vmlal.s32 q7, d24, d9
+ vmlal.s32 q7, d25, d31
+ vmull.s32 q1, d18, d2
+ vmlal.s32 q1, d19, d1
+ vmlal.s32 q1, d22, d0
+ vmlal.s32 q1, d24, d27
+ vmlal.s32 q1, d23, d20
+ vmlal.s32 q1, d12, d7
+ vmlal.s32 q1, d13, d6
+ vmull.s32 q6, d18, d1
+ vmlal.s32 q6, d19, d0
+ vmlal.s32 q6, d23, d27
+ vmlal.s32 q6, d22, d20
+ vmlal.s32 q6, d24, d26
+ vmull.s32 q0, d18, d0
+ vmlal.s32 q0, d22, d27
+ vmlal.s32 q0, d23, d26
+ vmlal.s32 q0, d24, d31
+ vmlal.s32 q0, d19, d20
+ add r2, sp, #608
+ vld1.8 {d18-d19}, [r2, : 128]
+ vmlal.s32 q2, d18, d7
+ vmlal.s32 q5, d18, d6
+ vmlal.s32 q1, d18, d21
+ vmlal.s32 q0, d18, d28
+ vmlal.s32 q6, d18, d29
+ vmlal.s32 q2, d19, d6
+ vmlal.s32 q5, d19, d21
+ vmlal.s32 q1, d19, d29
+ vmlal.s32 q0, d19, d9
+ vmlal.s32 q6, d19, d28
+ add r2, sp, #560
+ vld1.8 {d18-d19}, [r2, : 128]
+ add r2, sp, #480
+ vld1.8 {d22-d23}, [r2, : 128]
+ vmlal.s32 q5, d19, d7
+ vmlal.s32 q0, d18, d21
+ vmlal.s32 q0, d19, d29
+ vmlal.s32 q6, d18, d6
+ add r2, sp, #496
+ vld1.8 {d6-d7}, [r2, : 128]
+ vmlal.s32 q6, d19, d21
+ add r2, sp, #544
+ vld1.8 {d18-d19}, [r2, : 128]
+ vmlal.s32 q0, d30, d8
+ add r2, sp, #640
+ vld1.8 {d20-d21}, [r2, : 128]
+ vmlal.s32 q5, d30, d29
+ add r2, sp, #576
+ vld1.8 {d24-d25}, [r2, : 128]
+ vmlal.s32 q1, d30, d28
+ vadd.i64 q13, q0, q11
+ vadd.i64 q14, q5, q11
+ vmlal.s32 q6, d30, d9
+ vshr.s64 q4, q13, #26
+ vshr.s64 q13, q14, #26
+ vadd.i64 q7, q7, q4
+ vshl.i64 q4, q4, #26
+ vadd.i64 q14, q7, q3
+ vadd.i64 q9, q9, q13
+ vshl.i64 q13, q13, #26
+ vadd.i64 q15, q9, q3
+ vsub.i64 q0, q0, q4
+ vshr.s64 q4, q14, #25
+ vsub.i64 q5, q5, q13
+ vshr.s64 q13, q15, #25
+ vadd.i64 q6, q6, q4
+ vshl.i64 q4, q4, #25
+ vadd.i64 q14, q6, q11
+ vadd.i64 q2, q2, q13
+ vsub.i64 q4, q7, q4
+ vshr.s64 q7, q14, #26
+ vshl.i64 q13, q13, #25
+ vadd.i64 q14, q2, q11
+ vadd.i64 q8, q8, q7
+ vshl.i64 q7, q7, #26
+ vadd.i64 q15, q8, q3
+ vsub.i64 q9, q9, q13
+ vshr.s64 q13, q14, #26
+ vsub.i64 q6, q6, q7
+ vshr.s64 q7, q15, #25
+ vadd.i64 q10, q10, q13
+ vshl.i64 q13, q13, #26
+ vadd.i64 q14, q10, q3
+ vadd.i64 q1, q1, q7
+ add r2, r3, #288
+ vshl.i64 q7, q7, #25
+ add r4, r3, #96
+ vadd.i64 q15, q1, q11
+ add r2, r2, #8
+ vsub.i64 q2, q2, q13
+ add r4, r4, #8
+ vshr.s64 q13, q14, #25
+ vsub.i64 q7, q8, q7
+ vshr.s64 q8, q15, #26
+ vadd.i64 q14, q13, q13
+ vadd.i64 q12, q12, q8
+ vtrn.32 d12, d14
+ vshl.i64 q8, q8, #26
+ vtrn.32 d13, d15
+ vadd.i64 q3, q12, q3
+ vadd.i64 q0, q0, q14
+ vst1.8 d12, [r2, : 64]!
+ vshl.i64 q7, q13, #4
+ vst1.8 d13, [r4, : 64]!
+ vsub.i64 q1, q1, q8
+ vshr.s64 q3, q3, #25
+ vadd.i64 q0, q0, q7
+ vadd.i64 q5, q5, q3
+ vshl.i64 q3, q3, #25
+ vadd.i64 q6, q5, q11
+ vadd.i64 q0, q0, q13
+ vshl.i64 q7, q13, #25
+ vadd.i64 q8, q0, q11
+ vsub.i64 q3, q12, q3
+ vshr.s64 q6, q6, #26
+ vsub.i64 q7, q10, q7
+ vtrn.32 d2, d6
+ vshr.s64 q8, q8, #26
+ vtrn.32 d3, d7
+ vadd.i64 q3, q9, q6
+ vst1.8 d2, [r2, : 64]
+ vshl.i64 q6, q6, #26
+ vst1.8 d3, [r4, : 64]
+ vadd.i64 q1, q4, q8
+ vtrn.32 d4, d14
+ vshl.i64 q4, q8, #26
+ vtrn.32 d5, d15
+ vsub.i64 q5, q5, q6
+ add r2, r2, #16
+ vsub.i64 q0, q0, q4
+ vst1.8 d4, [r2, : 64]
+ add r4, r4, #16
+ vst1.8 d5, [r4, : 64]
+ vtrn.32 d10, d6
+ vtrn.32 d11, d7
+ sub r2, r2, #8
+ sub r4, r4, #8
+ vtrn.32 d0, d2
+ vtrn.32 d1, d3
+ vst1.8 d10, [r2, : 64]
+ vst1.8 d11, [r4, : 64]
+ sub r2, r2, #24
+ sub r4, r4, #24
+ vst1.8 d0, [r2, : 64]
+ vst1.8 d1, [r4, : 64]
+ add r2, sp, #512
+ add r4, r3, #144
+ add r5, r3, #192
+ vld1.8 {d0-d1}, [r2, : 128]
+ vld1.8 {d2-d3}, [r4, : 128]!
+ vld1.8 {d4-d5}, [r5, : 128]!
+ vzip.i32 q1, q2
+ vld1.8 {d6-d7}, [r4, : 128]!
+ vld1.8 {d8-d9}, [r5, : 128]!
+ vshl.i32 q5, q1, #1
+ vzip.i32 q3, q4
+ vshl.i32 q6, q2, #1
+ vld1.8 {d14}, [r4, : 64]
+ vshl.i32 q8, q3, #1
+ vld1.8 {d15}, [r5, : 64]
+ vshl.i32 q9, q4, #1
+ vmul.i32 d21, d7, d1
+ vtrn.32 d14, d15
+ vmul.i32 q11, q4, q0
+ vmul.i32 q0, q7, q0
+ vmull.s32 q12, d2, d2
+ vmlal.s32 q12, d11, d1
+ vmlal.s32 q12, d12, d0
+ vmlal.s32 q12, d13, d23
+ vmlal.s32 q12, d16, d22
+ vmlal.s32 q12, d7, d21
+ vmull.s32 q10, d2, d11
+ vmlal.s32 q10, d4, d1
+ vmlal.s32 q10, d13, d0
+ vmlal.s32 q10, d6, d23
+ vmlal.s32 q10, d17, d22
+ vmull.s32 q13, d10, d4
+ vmlal.s32 q13, d11, d3
+ vmlal.s32 q13, d13, d1
+ vmlal.s32 q13, d16, d0
+ vmlal.s32 q13, d17, d23
+ vmlal.s32 q13, d8, d22
+ vmull.s32 q1, d10, d5
+ vmlal.s32 q1, d11, d4
+ vmlal.s32 q1, d6, d1
+ vmlal.s32 q1, d17, d0
+ vmlal.s32 q1, d8, d23
+ vmull.s32 q14, d10, d6
+ vmlal.s32 q14, d11, d13
+ vmlal.s32 q14, d4, d4
+ vmlal.s32 q14, d17, d1
+ vmlal.s32 q14, d18, d0
+ vmlal.s32 q14, d9, d23
+ vmull.s32 q11, d10, d7
+ vmlal.s32 q11, d11, d6
+ vmlal.s32 q11, d12, d5
+ vmlal.s32 q11, d8, d1
+ vmlal.s32 q11, d19, d0
+ vmull.s32 q15, d10, d8
+ vmlal.s32 q15, d11, d17
+ vmlal.s32 q15, d12, d6
+ vmlal.s32 q15, d13, d5
+ vmlal.s32 q15, d19, d1
+ vmlal.s32 q15, d14, d0
+ vmull.s32 q2, d10, d9
+ vmlal.s32 q2, d11, d8
+ vmlal.s32 q2, d12, d7
+ vmlal.s32 q2, d13, d6
+ vmlal.s32 q2, d14, d1
+ vmull.s32 q0, d15, d1
+ vmlal.s32 q0, d10, d14
+ vmlal.s32 q0, d11, d19
+ vmlal.s32 q0, d12, d8
+ vmlal.s32 q0, d13, d17
+ vmlal.s32 q0, d6, d6
+ add r2, sp, #480
+ vld1.8 {d18-d19}, [r2, : 128]!
+ vmull.s32 q3, d16, d7
+ vmlal.s32 q3, d10, d15
+ vmlal.s32 q3, d11, d14
+ vmlal.s32 q3, d12, d9
+ vmlal.s32 q3, d13, d8
+ vld1.8 {d8-d9}, [r2, : 128]
+ vadd.i64 q5, q12, q9
+ vadd.i64 q6, q15, q9
+ vshr.s64 q5, q5, #26
+ vshr.s64 q6, q6, #26
+ vadd.i64 q7, q10, q5
+ vshl.i64 q5, q5, #26
+ vadd.i64 q8, q7, q4
+ vadd.i64 q2, q2, q6
+ vshl.i64 q6, q6, #26
+ vadd.i64 q10, q2, q4
+ vsub.i64 q5, q12, q5
+ vshr.s64 q8, q8, #25
+ vsub.i64 q6, q15, q6
+ vshr.s64 q10, q10, #25
+ vadd.i64 q12, q13, q8
+ vshl.i64 q8, q8, #25
+ vadd.i64 q13, q12, q9
+ vadd.i64 q0, q0, q10
+ vsub.i64 q7, q7, q8
+ vshr.s64 q8, q13, #26
+ vshl.i64 q10, q10, #25
+ vadd.i64 q13, q0, q9
+ vadd.i64 q1, q1, q8
+ vshl.i64 q8, q8, #26
+ vadd.i64 q15, q1, q4
+ vsub.i64 q2, q2, q10
+ vshr.s64 q10, q13, #26
+ vsub.i64 q8, q12, q8
+ vshr.s64 q12, q15, #25
+ vadd.i64 q3, q3, q10
+ vshl.i64 q10, q10, #26
+ vadd.i64 q13, q3, q4
+ vadd.i64 q14, q14, q12
+ add r2, r3, #144
+ vshl.i64 q12, q12, #25
+ add r4, r3, #192
+ vadd.i64 q15, q14, q9
+ add r2, r2, #8
+ vsub.i64 q0, q0, q10
+ add r4, r4, #8
+ vshr.s64 q10, q13, #25
+ vsub.i64 q1, q1, q12
+ vshr.s64 q12, q15, #26
+ vadd.i64 q13, q10, q10
+ vadd.i64 q11, q11, q12
+ vtrn.32 d16, d2
+ vshl.i64 q12, q12, #26
+ vtrn.32 d17, d3
+ vadd.i64 q1, q11, q4
+ vadd.i64 q4, q5, q13
+ vst1.8 d16, [r2, : 64]!
+ vshl.i64 q5, q10, #4
+ vst1.8 d17, [r4, : 64]!
+ vsub.i64 q8, q14, q12
+ vshr.s64 q1, q1, #25
+ vadd.i64 q4, q4, q5
+ vadd.i64 q5, q6, q1
+ vshl.i64 q1, q1, #25
+ vadd.i64 q6, q5, q9
+ vadd.i64 q4, q4, q10
+ vshl.i64 q10, q10, #25
+ vadd.i64 q9, q4, q9
+ vsub.i64 q1, q11, q1
+ vshr.s64 q6, q6, #26
+ vsub.i64 q3, q3, q10
+ vtrn.32 d16, d2
+ vshr.s64 q9, q9, #26
+ vtrn.32 d17, d3
+ vadd.i64 q1, q2, q6
+ vst1.8 d16, [r2, : 64]
+ vshl.i64 q2, q6, #26
+ vst1.8 d17, [r4, : 64]
+ vadd.i64 q6, q7, q9
+ vtrn.32 d0, d6
+ vshl.i64 q7, q9, #26
+ vtrn.32 d1, d7
+ vsub.i64 q2, q5, q2
+ add r2, r2, #16
+ vsub.i64 q3, q4, q7
+ vst1.8 d0, [r2, : 64]
+ add r4, r4, #16
+ vst1.8 d1, [r4, : 64]
+ vtrn.32 d4, d2
+ vtrn.32 d5, d3
+ sub r2, r2, #8
+ sub r4, r4, #8
+ vtrn.32 d6, d12
+ vtrn.32 d7, d13
+ vst1.8 d4, [r2, : 64]
+ vst1.8 d5, [r4, : 64]
+ sub r2, r2, #24
+ sub r4, r4, #24
+ vst1.8 d6, [r2, : 64]
+ vst1.8 d7, [r4, : 64]
+ add r2, r3, #336
+ add r4, r3, #288
+ vld1.8 {d0-d1}, [r2, : 128]!
+ vld1.8 {d2-d3}, [r4, : 128]!
+ vadd.i32 q0, q0, q1
+ vld1.8 {d2-d3}, [r2, : 128]!
+ vld1.8 {d4-d5}, [r4, : 128]!
+ vadd.i32 q1, q1, q2
+ add r5, r3, #288
+ vld1.8 {d4}, [r2, : 64]
+ vld1.8 {d6}, [r4, : 64]
+ vadd.i32 q2, q2, q3
+ vst1.8 {d0-d1}, [r5, : 128]!
+ vst1.8 {d2-d3}, [r5, : 128]!
+ vst1.8 d4, [r5, : 64]
+ add r2, r3, #48
+ add r4, r3, #144
+ vld1.8 {d0-d1}, [r4, : 128]!
+ vld1.8 {d2-d3}, [r4, : 128]!
+ vld1.8 {d4}, [r4, : 64]
+ add r4, r3, #288
+ vld1.8 {d6-d7}, [r4, : 128]!
+ vtrn.32 q0, q3
+ vld1.8 {d8-d9}, [r4, : 128]!
+ vshl.i32 q5, q0, #4
+ vtrn.32 q1, q4
+ vshl.i32 q6, q3, #4
+ vadd.i32 q5, q5, q0
+ vadd.i32 q6, q6, q3
+ vshl.i32 q7, q1, #4
+ vld1.8 {d5}, [r4, : 64]
+ vshl.i32 q8, q4, #4
+ vtrn.32 d4, d5
+ vadd.i32 q7, q7, q1
+ vadd.i32 q8, q8, q4
+ vld1.8 {d18-d19}, [r2, : 128]!
+ vshl.i32 q10, q2, #4
+ vld1.8 {d22-d23}, [r2, : 128]!
+ vadd.i32 q10, q10, q2
+ vld1.8 {d24}, [r2, : 64]
+ vadd.i32 q5, q5, q0
+ add r2, r3, #240
+ vld1.8 {d26-d27}, [r2, : 128]!
+ vadd.i32 q6, q6, q3
+ vld1.8 {d28-d29}, [r2, : 128]!
+ vadd.i32 q8, q8, q4
+ vld1.8 {d25}, [r2, : 64]
+ vadd.i32 q10, q10, q2
+ vtrn.32 q9, q13
+ vadd.i32 q7, q7, q1
+ vadd.i32 q5, q5, q0
+ vtrn.32 q11, q14
+ vadd.i32 q6, q6, q3
+ add r2, sp, #528
+ vadd.i32 q10, q10, q2
+ vtrn.32 d24, d25
+ vst1.8 {d12-d13}, [r2, : 128]!
+ vshl.i32 q6, q13, #1
+ vst1.8 {d20-d21}, [r2, : 128]!
+ vshl.i32 q10, q14, #1
+ vst1.8 {d12-d13}, [r2, : 128]!
+ vshl.i32 q15, q12, #1
+ vadd.i32 q8, q8, q4
+ vext.32 d10, d31, d30, #0
+ vadd.i32 q7, q7, q1
+ vst1.8 {d16-d17}, [r2, : 128]!
+ vmull.s32 q8, d18, d5
+ vmlal.s32 q8, d26, d4
+ vmlal.s32 q8, d19, d9
+ vmlal.s32 q8, d27, d3
+ vmlal.s32 q8, d22, d8
+ vmlal.s32 q8, d28, d2
+ vmlal.s32 q8, d23, d7
+ vmlal.s32 q8, d29, d1
+ vmlal.s32 q8, d24, d6
+ vmlal.s32 q8, d25, d0
+ vst1.8 {d14-d15}, [r2, : 128]!
+ vmull.s32 q2, d18, d4
+ vmlal.s32 q2, d12, d9
+ vmlal.s32 q2, d13, d8
+ vmlal.s32 q2, d19, d3
+ vmlal.s32 q2, d22, d2
+ vmlal.s32 q2, d23, d1
+ vmlal.s32 q2, d24, d0
+ vst1.8 {d20-d21}, [r2, : 128]!
+ vmull.s32 q7, d18, d9
+ vmlal.s32 q7, d26, d3
+ vmlal.s32 q7, d19, d8
+ vmlal.s32 q7, d27, d2
+ vmlal.s32 q7, d22, d7
+ vmlal.s32 q7, d28, d1
+ vmlal.s32 q7, d23, d6
+ vmlal.s32 q7, d29, d0
+ vst1.8 {d10-d11}, [r2, : 128]!
+ vmull.s32 q5, d18, d3
+ vmlal.s32 q5, d19, d2
+ vmlal.s32 q5, d22, d1
+ vmlal.s32 q5, d23, d0
+ vmlal.s32 q5, d12, d8
+ vst1.8 {d16-d17}, [r2, : 128]!
+ vmull.s32 q4, d18, d8
+ vmlal.s32 q4, d26, d2
+ vmlal.s32 q4, d19, d7
+ vmlal.s32 q4, d27, d1
+ vmlal.s32 q4, d22, d6
+ vmlal.s32 q4, d28, d0
+ vmull.s32 q8, d18, d7
+ vmlal.s32 q8, d26, d1
+ vmlal.s32 q8, d19, d6
+ vmlal.s32 q8, d27, d0
+ add r2, sp, #544
+ vld1.8 {d20-d21}, [r2, : 128]
+ vmlal.s32 q7, d24, d21
+ vmlal.s32 q7, d25, d20
+ vmlal.s32 q4, d23, d21
+ vmlal.s32 q4, d29, d20
+ vmlal.s32 q8, d22, d21
+ vmlal.s32 q8, d28, d20
+ vmlal.s32 q5, d24, d20
+ vst1.8 {d14-d15}, [r2, : 128]
+ vmull.s32 q7, d18, d6
+ vmlal.s32 q7, d26, d0
+ add r2, sp, #624
+ vld1.8 {d30-d31}, [r2, : 128]
+ vmlal.s32 q2, d30, d21
+ vmlal.s32 q7, d19, d21
+ vmlal.s32 q7, d27, d20
+ add r2, sp, #592
+ vld1.8 {d26-d27}, [r2, : 128]
+ vmlal.s32 q4, d25, d27
+ vmlal.s32 q8, d29, d27
+ vmlal.s32 q8, d25, d26
+ vmlal.s32 q7, d28, d27
+ vmlal.s32 q7, d29, d26
+ add r2, sp, #576
+ vld1.8 {d28-d29}, [r2, : 128]
+ vmlal.s32 q4, d24, d29
+ vmlal.s32 q8, d23, d29
+ vmlal.s32 q8, d24, d28
+ vmlal.s32 q7, d22, d29
+ vmlal.s32 q7, d23, d28
+ vst1.8 {d8-d9}, [r2, : 128]
+ add r2, sp, #528
+ vld1.8 {d8-d9}, [r2, : 128]
+ vmlal.s32 q7, d24, d9
+ vmlal.s32 q7, d25, d31
+ vmull.s32 q1, d18, d2
+ vmlal.s32 q1, d19, d1
+ vmlal.s32 q1, d22, d0
+ vmlal.s32 q1, d24, d27
+ vmlal.s32 q1, d23, d20
+ vmlal.s32 q1, d12, d7
+ vmlal.s32 q1, d13, d6
+ vmull.s32 q6, d18, d1
+ vmlal.s32 q6, d19, d0
+ vmlal.s32 q6, d23, d27
+ vmlal.s32 q6, d22, d20
+ vmlal.s32 q6, d24, d26
+ vmull.s32 q0, d18, d0
+ vmlal.s32 q0, d22, d27
+ vmlal.s32 q0, d23, d26
+ vmlal.s32 q0, d24, d31
+ vmlal.s32 q0, d19, d20
+ add r2, sp, #608
+ vld1.8 {d18-d19}, [r2, : 128]
+ vmlal.s32 q2, d18, d7
+ vmlal.s32 q5, d18, d6
+ vmlal.s32 q1, d18, d21
+ vmlal.s32 q0, d18, d28
+ vmlal.s32 q6, d18, d29
+ vmlal.s32 q2, d19, d6
+ vmlal.s32 q5, d19, d21
+ vmlal.s32 q1, d19, d29
+ vmlal.s32 q0, d19, d9
+ vmlal.s32 q6, d19, d28
+ add r2, sp, #560
+ vld1.8 {d18-d19}, [r2, : 128]
+ add r2, sp, #480
+ vld1.8 {d22-d23}, [r2, : 128]
+ vmlal.s32 q5, d19, d7
+ vmlal.s32 q0, d18, d21
+ vmlal.s32 q0, d19, d29
+ vmlal.s32 q6, d18, d6
+ add r2, sp, #496
+ vld1.8 {d6-d7}, [r2, : 128]
+ vmlal.s32 q6, d19, d21
+ add r2, sp, #544
+ vld1.8 {d18-d19}, [r2, : 128]
+ vmlal.s32 q0, d30, d8
+ add r2, sp, #640
+ vld1.8 {d20-d21}, [r2, : 128]
+ vmlal.s32 q5, d30, d29
+ add r2, sp, #576
+ vld1.8 {d24-d25}, [r2, : 128]
+ vmlal.s32 q1, d30, d28
+ vadd.i64 q13, q0, q11
+ vadd.i64 q14, q5, q11
+ vmlal.s32 q6, d30, d9
+ vshr.s64 q4, q13, #26
+ vshr.s64 q13, q14, #26
+ vadd.i64 q7, q7, q4
+ vshl.i64 q4, q4, #26
+ vadd.i64 q14, q7, q3
+ vadd.i64 q9, q9, q13
+ vshl.i64 q13, q13, #26
+ vadd.i64 q15, q9, q3
+ vsub.i64 q0, q0, q4
+ vshr.s64 q4, q14, #25
+ vsub.i64 q5, q5, q13
+ vshr.s64 q13, q15, #25
+ vadd.i64 q6, q6, q4
+ vshl.i64 q4, q4, #25
+ vadd.i64 q14, q6, q11
+ vadd.i64 q2, q2, q13
+ vsub.i64 q4, q7, q4
+ vshr.s64 q7, q14, #26
+ vshl.i64 q13, q13, #25
+ vadd.i64 q14, q2, q11
+ vadd.i64 q8, q8, q7
+ vshl.i64 q7, q7, #26
+ vadd.i64 q15, q8, q3
+ vsub.i64 q9, q9, q13
+ vshr.s64 q13, q14, #26
+ vsub.i64 q6, q6, q7
+ vshr.s64 q7, q15, #25
+ vadd.i64 q10, q10, q13
+ vshl.i64 q13, q13, #26
+ vadd.i64 q14, q10, q3
+ vadd.i64 q1, q1, q7
+ add r2, r3, #240
+ vshl.i64 q7, q7, #25
+ add r4, r3, #144
+ vadd.i64 q15, q1, q11
+ add r2, r2, #8
+ vsub.i64 q2, q2, q13
+ add r4, r4, #8
+ vshr.s64 q13, q14, #25
+ vsub.i64 q7, q8, q7
+ vshr.s64 q8, q15, #26
+ vadd.i64 q14, q13, q13
+ vadd.i64 q12, q12, q8
+ vtrn.32 d12, d14
+ vshl.i64 q8, q8, #26
+ vtrn.32 d13, d15
+ vadd.i64 q3, q12, q3
+ vadd.i64 q0, q0, q14
+ vst1.8 d12, [r2, : 64]!
+ vshl.i64 q7, q13, #4
+ vst1.8 d13, [r4, : 64]!
+ vsub.i64 q1, q1, q8
+ vshr.s64 q3, q3, #25
+ vadd.i64 q0, q0, q7
+ vadd.i64 q5, q5, q3
+ vshl.i64 q3, q3, #25
+ vadd.i64 q6, q5, q11
+ vadd.i64 q0, q0, q13
+ vshl.i64 q7, q13, #25
+ vadd.i64 q8, q0, q11
+ vsub.i64 q3, q12, q3
+ vshr.s64 q6, q6, #26
+ vsub.i64 q7, q10, q7
+ vtrn.32 d2, d6
+ vshr.s64 q8, q8, #26
+ vtrn.32 d3, d7
+ vadd.i64 q3, q9, q6
+ vst1.8 d2, [r2, : 64]
+ vshl.i64 q6, q6, #26
+ vst1.8 d3, [r4, : 64]
+ vadd.i64 q1, q4, q8
+ vtrn.32 d4, d14
+ vshl.i64 q4, q8, #26
+ vtrn.32 d5, d15
+ vsub.i64 q5, q5, q6
+ add r2, r2, #16
+ vsub.i64 q0, q0, q4
+ vst1.8 d4, [r2, : 64]
+ add r4, r4, #16
+ vst1.8 d5, [r4, : 64]
+ vtrn.32 d10, d6
+ vtrn.32 d11, d7
+ sub r2, r2, #8
+ sub r4, r4, #8
+ vtrn.32 d0, d2
+ vtrn.32 d1, d3
+ vst1.8 d10, [r2, : 64]
+ vst1.8 d11, [r4, : 64]
+ sub r2, r2, #24
+ sub r4, r4, #24
+ vst1.8 d0, [r2, : 64]
+ vst1.8 d1, [r4, : 64]
+ ldr r2, [sp, #456]
+ ldr r4, [sp, #460]
+ subs r5, r2, #1
+ bge .Lmainloop
+ add r1, r3, #144
+ add r2, r3, #336
+ vld1.8 {d0-d1}, [r1, : 128]!
+ vld1.8 {d2-d3}, [r1, : 128]!
+ vld1.8 {d4}, [r1, : 64]
+ vst1.8 {d0-d1}, [r2, : 128]!
+ vst1.8 {d2-d3}, [r2, : 128]!
+ vst1.8 d4, [r2, : 64]
+ movw r1, #0
+.Linvertloop:
+ add r2, r3, #144
+ movw r4, #0
+ movw r5, #2
+ cmp r1, #1
+ moveq r5, #1
+ addeq r2, r3, #336
+ addeq r4, r3, #48
+ cmp r1, #2
+ moveq r5, #1
+ addeq r2, r3, #48
+ cmp r1, #3
+ moveq r5, #5
+ addeq r4, r3, #336
+ cmp r1, #4
+ moveq r5, #10
+ cmp r1, #5
+ moveq r5, #20
+ cmp r1, #6
+ moveq r5, #10
+ addeq r2, r3, #336
+ addeq r4, r3, #336
+ cmp r1, #7
+ moveq r5, #50
+ cmp r1, #8
+ moveq r5, #100
+ cmp r1, #9
+ moveq r5, #50
+ addeq r2, r3, #336
+ cmp r1, #10
+ moveq r5, #5
+ addeq r2, r3, #48
+ cmp r1, #11
+ moveq r5, #0
+ addeq r2, r3, #96
+ add r6, r3, #144
+ add r7, r3, #288
+ vld1.8 {d0-d1}, [r6, : 128]!
+ vld1.8 {d2-d3}, [r6, : 128]!
+ vld1.8 {d4}, [r6, : 64]
+ vst1.8 {d0-d1}, [r7, : 128]!
+ vst1.8 {d2-d3}, [r7, : 128]!
+ vst1.8 d4, [r7, : 64]
+ cmp r5, #0
+ beq .Lskipsquaringloop
+.Lsquaringloop:
+ add r6, r3, #288
+ add r7, r3, #288
+ add r8, r3, #288
+ vmov.i32 q0, #19
+ vmov.i32 q1, #0
+ vmov.i32 q2, #1
+ vzip.i32 q1, q2
+ vld1.8 {d4-d5}, [r7, : 128]!
+ vld1.8 {d6-d7}, [r7, : 128]!
+ vld1.8 {d9}, [r7, : 64]
+ vld1.8 {d10-d11}, [r6, : 128]!
+ add r7, sp, #384
+ vld1.8 {d12-d13}, [r6, : 128]!
+ vmul.i32 q7, q2, q0
+ vld1.8 {d8}, [r6, : 64]
+ vext.32 d17, d11, d10, #1
+ vmul.i32 q9, q3, q0
+ vext.32 d16, d10, d8, #1
+ vshl.u32 q10, q5, q1
+ vext.32 d22, d14, d4, #1
+ vext.32 d24, d18, d6, #1
+ vshl.u32 q13, q6, q1
+ vshl.u32 d28, d8, d2
+ vrev64.i32 d22, d22
+ vmul.i32 d1, d9, d1
+ vrev64.i32 d24, d24
+ vext.32 d29, d8, d13, #1
+ vext.32 d0, d1, d9, #1
+ vrev64.i32 d0, d0
+ vext.32 d2, d9, d1, #1
+ vext.32 d23, d15, d5, #1
+ vmull.s32 q4, d20, d4
+ vrev64.i32 d23, d23
+ vmlal.s32 q4, d21, d1
+ vrev64.i32 d2, d2
+ vmlal.s32 q4, d26, d19
+ vext.32 d3, d5, d15, #1
+ vmlal.s32 q4, d27, d18
+ vrev64.i32 d3, d3
+ vmlal.s32 q4, d28, d15
+ vext.32 d14, d12, d11, #1
+ vmull.s32 q5, d16, d23
+ vext.32 d15, d13, d12, #1
+ vmlal.s32 q5, d17, d4
+ vst1.8 d8, [r7, : 64]!
+ vmlal.s32 q5, d14, d1
+ vext.32 d12, d9, d8, #0
+ vmlal.s32 q5, d15, d19
+ vmov.i64 d13, #0
+ vmlal.s32 q5, d29, d18
+ vext.32 d25, d19, d7, #1
+ vmlal.s32 q6, d20, d5
+ vrev64.i32 d25, d25
+ vmlal.s32 q6, d21, d4
+ vst1.8 d11, [r7, : 64]!
+ vmlal.s32 q6, d26, d1
+ vext.32 d9, d10, d10, #0
+ vmlal.s32 q6, d27, d19
+ vmov.i64 d8, #0
+ vmlal.s32 q6, d28, d18
+ vmlal.s32 q4, d16, d24
+ vmlal.s32 q4, d17, d5
+ vmlal.s32 q4, d14, d4
+ vst1.8 d12, [r7, : 64]!
+ vmlal.s32 q4, d15, d1
+ vext.32 d10, d13, d12, #0
+ vmlal.s32 q4, d29, d19
+ vmov.i64 d11, #0
+ vmlal.s32 q5, d20, d6
+ vmlal.s32 q5, d21, d5
+ vmlal.s32 q5, d26, d4
+ vext.32 d13, d8, d8, #0
+ vmlal.s32 q5, d27, d1
+ vmov.i64 d12, #0
+ vmlal.s32 q5, d28, d19
+ vst1.8 d9, [r7, : 64]!
+ vmlal.s32 q6, d16, d25
+ vmlal.s32 q6, d17, d6
+ vst1.8 d10, [r7, : 64]
+ vmlal.s32 q6, d14, d5
+ vext.32 d8, d11, d10, #0
+ vmlal.s32 q6, d15, d4
+ vmov.i64 d9, #0
+ vmlal.s32 q6, d29, d1
+ vmlal.s32 q4, d20, d7
+ vmlal.s32 q4, d21, d6
+ vmlal.s32 q4, d26, d5
+ vext.32 d11, d12, d12, #0
+ vmlal.s32 q4, d27, d4
+ vmov.i64 d10, #0
+ vmlal.s32 q4, d28, d1
+ vmlal.s32 q5, d16, d0
+ sub r6, r7, #32
+ vmlal.s32 q5, d17, d7
+ vmlal.s32 q5, d14, d6
+ vext.32 d30, d9, d8, #0
+ vmlal.s32 q5, d15, d5
+ vld1.8 {d31}, [r6, : 64]!
+ vmlal.s32 q5, d29, d4
+ vmlal.s32 q15, d20, d0
+ vext.32 d0, d6, d18, #1
+ vmlal.s32 q15, d21, d25
+ vrev64.i32 d0, d0
+ vmlal.s32 q15, d26, d24
+ vext.32 d1, d7, d19, #1
+ vext.32 d7, d10, d10, #0
+ vmlal.s32 q15, d27, d23
+ vrev64.i32 d1, d1
+ vld1.8 {d6}, [r6, : 64]
+ vmlal.s32 q15, d28, d22
+ vmlal.s32 q3, d16, d4
+ add r6, r6, #24
+ vmlal.s32 q3, d17, d2
+ vext.32 d4, d31, d30, #0
+ vmov d17, d11
+ vmlal.s32 q3, d14, d1
+ vext.32 d11, d13, d13, #0
+ vext.32 d13, d30, d30, #0
+ vmlal.s32 q3, d15, d0
+ vext.32 d1, d8, d8, #0
+ vmlal.s32 q3, d29, d3
+ vld1.8 {d5}, [r6, : 64]
+ sub r6, r6, #16
+ vext.32 d10, d6, d6, #0
+ vmov.i32 q1, #0xffffffff
+ vshl.i64 q4, q1, #25
+ add r7, sp, #480
+ vld1.8 {d14-d15}, [r7, : 128]
+ vadd.i64 q9, q2, q7
+ vshl.i64 q1, q1, #26
+ vshr.s64 q10, q9, #26
+ vld1.8 {d0}, [r6, : 64]!
+ vadd.i64 q5, q5, q10
+ vand q9, q9, q1
+ vld1.8 {d16}, [r6, : 64]!
+ add r6, sp, #496
+ vld1.8 {d20-d21}, [r6, : 128]
+ vadd.i64 q11, q5, q10
+ vsub.i64 q2, q2, q9
+ vshr.s64 q9, q11, #25
+ vext.32 d12, d5, d4, #0
+ vand q11, q11, q4
+ vadd.i64 q0, q0, q9
+ vmov d19, d7
+ vadd.i64 q3, q0, q7
+ vsub.i64 q5, q5, q11
+ vshr.s64 q11, q3, #26
+ vext.32 d18, d11, d10, #0
+ vand q3, q3, q1
+ vadd.i64 q8, q8, q11
+ vadd.i64 q11, q8, q10
+ vsub.i64 q0, q0, q3
+ vshr.s64 q3, q11, #25
+ vand q11, q11, q4
+ vadd.i64 q3, q6, q3
+ vadd.i64 q6, q3, q7
+ vsub.i64 q8, q8, q11
+ vshr.s64 q11, q6, #26
+ vand q6, q6, q1
+ vadd.i64 q9, q9, q11
+ vadd.i64 d25, d19, d21
+ vsub.i64 q3, q3, q6
+ vshr.s64 d23, d25, #25
+ vand q4, q12, q4
+ vadd.i64 d21, d23, d23
+ vshl.i64 d25, d23, #4
+ vadd.i64 d21, d21, d23
+ vadd.i64 d25, d25, d21
+ vadd.i64 d4, d4, d25
+ vzip.i32 q0, q8
+ vadd.i64 d12, d4, d14
+ add r6, r8, #8
+ vst1.8 d0, [r6, : 64]
+ vsub.i64 d19, d19, d9
+ add r6, r6, #16
+ vst1.8 d16, [r6, : 64]
+ vshr.s64 d22, d12, #26
+ vand q0, q6, q1
+ vadd.i64 d10, d10, d22
+ vzip.i32 q3, q9
+ vsub.i64 d4, d4, d0
+ sub r6, r6, #8
+ vst1.8 d6, [r6, : 64]
+ add r6, r6, #16
+ vst1.8 d18, [r6, : 64]
+ vzip.i32 q2, q5
+ sub r6, r6, #32
+ vst1.8 d4, [r6, : 64]
+ subs r5, r5, #1
+ bhi .Lsquaringloop
+.Lskipsquaringloop:
+ mov r2, r2
+ add r5, r3, #288
+ add r6, r3, #144
+ vmov.i32 q0, #19
+ vmov.i32 q1, #0
+ vmov.i32 q2, #1
+ vzip.i32 q1, q2
+ vld1.8 {d4-d5}, [r5, : 128]!
+ vld1.8 {d6-d7}, [r5, : 128]!
+ vld1.8 {d9}, [r5, : 64]
+ vld1.8 {d10-d11}, [r2, : 128]!
+ add r5, sp, #384
+ vld1.8 {d12-d13}, [r2, : 128]!
+ vmul.i32 q7, q2, q0
+ vld1.8 {d8}, [r2, : 64]
+ vext.32 d17, d11, d10, #1
+ vmul.i32 q9, q3, q0
+ vext.32 d16, d10, d8, #1
+ vshl.u32 q10, q5, q1
+ vext.32 d22, d14, d4, #1
+ vext.32 d24, d18, d6, #1
+ vshl.u32 q13, q6, q1
+ vshl.u32 d28, d8, d2
+ vrev64.i32 d22, d22
+ vmul.i32 d1, d9, d1
+ vrev64.i32 d24, d24
+ vext.32 d29, d8, d13, #1
+ vext.32 d0, d1, d9, #1
+ vrev64.i32 d0, d0
+ vext.32 d2, d9, d1, #1
+ vext.32 d23, d15, d5, #1
+ vmull.s32 q4, d20, d4
+ vrev64.i32 d23, d23
+ vmlal.s32 q4, d21, d1
+ vrev64.i32 d2, d2
+ vmlal.s32 q4, d26, d19
+ vext.32 d3, d5, d15, #1
+ vmlal.s32 q4, d27, d18
+ vrev64.i32 d3, d3
+ vmlal.s32 q4, d28, d15
+ vext.32 d14, d12, d11, #1
+ vmull.s32 q5, d16, d23
+ vext.32 d15, d13, d12, #1
+ vmlal.s32 q5, d17, d4
+ vst1.8 d8, [r5, : 64]!
+ vmlal.s32 q5, d14, d1
+ vext.32 d12, d9, d8, #0
+ vmlal.s32 q5, d15, d19
+ vmov.i64 d13, #0
+ vmlal.s32 q5, d29, d18
+ vext.32 d25, d19, d7, #1
+ vmlal.s32 q6, d20, d5
+ vrev64.i32 d25, d25
+ vmlal.s32 q6, d21, d4
+ vst1.8 d11, [r5, : 64]!
+ vmlal.s32 q6, d26, d1
+ vext.32 d9, d10, d10, #0
+ vmlal.s32 q6, d27, d19
+ vmov.i64 d8, #0
+ vmlal.s32 q6, d28, d18
+ vmlal.s32 q4, d16, d24
+ vmlal.s32 q4, d17, d5
+ vmlal.s32 q4, d14, d4
+ vst1.8 d12, [r5, : 64]!
+ vmlal.s32 q4, d15, d1
+ vext.32 d10, d13, d12, #0
+ vmlal.s32 q4, d29, d19
+ vmov.i64 d11, #0
+ vmlal.s32 q5, d20, d6
+ vmlal.s32 q5, d21, d5
+ vmlal.s32 q5, d26, d4
+ vext.32 d13, d8, d8, #0
+ vmlal.s32 q5, d27, d1
+ vmov.i64 d12, #0
+ vmlal.s32 q5, d28, d19
+ vst1.8 d9, [r5, : 64]!
+ vmlal.s32 q6, d16, d25
+ vmlal.s32 q6, d17, d6
+ vst1.8 d10, [r5, : 64]
+ vmlal.s32 q6, d14, d5
+ vext.32 d8, d11, d10, #0
+ vmlal.s32 q6, d15, d4
+ vmov.i64 d9, #0
+ vmlal.s32 q6, d29, d1
+ vmlal.s32 q4, d20, d7
+ vmlal.s32 q4, d21, d6
+ vmlal.s32 q4, d26, d5
+ vext.32 d11, d12, d12, #0
+ vmlal.s32 q4, d27, d4
+ vmov.i64 d10, #0
+ vmlal.s32 q4, d28, d1
+ vmlal.s32 q5, d16, d0
+ sub r2, r5, #32
+ vmlal.s32 q5, d17, d7
+ vmlal.s32 q5, d14, d6
+ vext.32 d30, d9, d8, #0
+ vmlal.s32 q5, d15, d5
+ vld1.8 {d31}, [r2, : 64]!
+ vmlal.s32 q5, d29, d4
+ vmlal.s32 q15, d20, d0
+ vext.32 d0, d6, d18, #1
+ vmlal.s32 q15, d21, d25
+ vrev64.i32 d0, d0
+ vmlal.s32 q15, d26, d24
+ vext.32 d1, d7, d19, #1
+ vext.32 d7, d10, d10, #0
+ vmlal.s32 q15, d27, d23
+ vrev64.i32 d1, d1
+ vld1.8 {d6}, [r2, : 64]
+ vmlal.s32 q15, d28, d22
+ vmlal.s32 q3, d16, d4
+ add r2, r2, #24
+ vmlal.s32 q3, d17, d2
+ vext.32 d4, d31, d30, #0
+ vmov d17, d11
+ vmlal.s32 q3, d14, d1
+ vext.32 d11, d13, d13, #0
+ vext.32 d13, d30, d30, #0
+ vmlal.s32 q3, d15, d0
+ vext.32 d1, d8, d8, #0
+ vmlal.s32 q3, d29, d3
+ vld1.8 {d5}, [r2, : 64]
+ sub r2, r2, #16
+ vext.32 d10, d6, d6, #0
+ vmov.i32 q1, #0xffffffff
+ vshl.i64 q4, q1, #25
+ add r5, sp, #480
+ vld1.8 {d14-d15}, [r5, : 128]
+ vadd.i64 q9, q2, q7
+ vshl.i64 q1, q1, #26
+ vshr.s64 q10, q9, #26
+ vld1.8 {d0}, [r2, : 64]!
+ vadd.i64 q5, q5, q10
+ vand q9, q9, q1
+ vld1.8 {d16}, [r2, : 64]!
+ add r2, sp, #496
+ vld1.8 {d20-d21}, [r2, : 128]
+ vadd.i64 q11, q5, q10
+ vsub.i64 q2, q2, q9
+ vshr.s64 q9, q11, #25
+ vext.32 d12, d5, d4, #0
+ vand q11, q11, q4
+ vadd.i64 q0, q0, q9
+ vmov d19, d7
+ vadd.i64 q3, q0, q7
+ vsub.i64 q5, q5, q11
+ vshr.s64 q11, q3, #26
+ vext.32 d18, d11, d10, #0
+ vand q3, q3, q1
+ vadd.i64 q8, q8, q11
+ vadd.i64 q11, q8, q10
+ vsub.i64 q0, q0, q3
+ vshr.s64 q3, q11, #25
+ vand q11, q11, q4
+ vadd.i64 q3, q6, q3
+ vadd.i64 q6, q3, q7
+ vsub.i64 q8, q8, q11
+ vshr.s64 q11, q6, #26
+ vand q6, q6, q1
+ vadd.i64 q9, q9, q11
+ vadd.i64 d25, d19, d21
+ vsub.i64 q3, q3, q6
+ vshr.s64 d23, d25, #25
+ vand q4, q12, q4
+ vadd.i64 d21, d23, d23
+ vshl.i64 d25, d23, #4
+ vadd.i64 d21, d21, d23
+ vadd.i64 d25, d25, d21
+ vadd.i64 d4, d4, d25
+ vzip.i32 q0, q8
+ vadd.i64 d12, d4, d14
+ add r2, r6, #8
+ vst1.8 d0, [r2, : 64]
+ vsub.i64 d19, d19, d9
+ add r2, r2, #16
+ vst1.8 d16, [r2, : 64]
+ vshr.s64 d22, d12, #26
+ vand q0, q6, q1
+ vadd.i64 d10, d10, d22
+ vzip.i32 q3, q9
+ vsub.i64 d4, d4, d0
+ sub r2, r2, #8
+ vst1.8 d6, [r2, : 64]
+ add r2, r2, #16
+ vst1.8 d18, [r2, : 64]
+ vzip.i32 q2, q5
+ sub r2, r2, #32
+ vst1.8 d4, [r2, : 64]
+ cmp r4, #0
+ beq .Lskippostcopy
+ add r2, r3, #144
+ mov r4, r4
+ vld1.8 {d0-d1}, [r2, : 128]!
+ vld1.8 {d2-d3}, [r2, : 128]!
+ vld1.8 {d4}, [r2, : 64]
+ vst1.8 {d0-d1}, [r4, : 128]!
+ vst1.8 {d2-d3}, [r4, : 128]!
+ vst1.8 d4, [r4, : 64]
+.Lskippostcopy:
+ cmp r1, #1
+ bne .Lskipfinalcopy
+ add r2, r3, #288
+ add r4, r3, #144
+ vld1.8 {d0-d1}, [r2, : 128]!
+ vld1.8 {d2-d3}, [r2, : 128]!
+ vld1.8 {d4}, [r2, : 64]
+ vst1.8 {d0-d1}, [r4, : 128]!
+ vst1.8 {d2-d3}, [r4, : 128]!
+ vst1.8 d4, [r4, : 64]
+.Lskipfinalcopy:
+ add r1, r1, #1
+ cmp r1, #12
+ blo .Linvertloop
+ add r1, r3, #144
+ ldr r2, [r1], #4
+ ldr r3, [r1], #4
+ ldr r4, [r1], #4
+ ldr r5, [r1], #4
+ ldr r6, [r1], #4
+ ldr r7, [r1], #4
+ ldr r8, [r1], #4
+ ldr r9, [r1], #4
+ ldr r10, [r1], #4
+ ldr r1, [r1]
+ add r11, r1, r1, LSL #4
+ add r11, r11, r1, LSL #1
+ add r11, r11, #16777216
+ mov r11, r11, ASR #25
+ add r11, r11, r2
+ mov r11, r11, ASR #26
+ add r11, r11, r3
+ mov r11, r11, ASR #25
+ add r11, r11, r4
+ mov r11, r11, ASR #26
+ add r11, r11, r5
+ mov r11, r11, ASR #25
+ add r11, r11, r6
+ mov r11, r11, ASR #26
+ add r11, r11, r7
+ mov r11, r11, ASR #25
+ add r11, r11, r8
+ mov r11, r11, ASR #26
+ add r11, r11, r9
+ mov r11, r11, ASR #25
+ add r11, r11, r10
+ mov r11, r11, ASR #26
+ add r11, r11, r1
+ mov r11, r11, ASR #25
+ add r2, r2, r11
+ add r2, r2, r11, LSL #1
+ add r2, r2, r11, LSL #4
+ mov r11, r2, ASR #26
+ add r3, r3, r11
+ sub r2, r2, r11, LSL #26
+ mov r11, r3, ASR #25
+ add r4, r4, r11
+ sub r3, r3, r11, LSL #25
+ mov r11, r4, ASR #26
+ add r5, r5, r11
+ sub r4, r4, r11, LSL #26
+ mov r11, r5, ASR #25
+ add r6, r6, r11
+ sub r5, r5, r11, LSL #25
+ mov r11, r6, ASR #26
+ add r7, r7, r11
+ sub r6, r6, r11, LSL #26
+ mov r11, r7, ASR #25
+ add r8, r8, r11
+ sub r7, r7, r11, LSL #25
+ mov r11, r8, ASR #26
+ add r9, r9, r11
+ sub r8, r8, r11, LSL #26
+ mov r11, r9, ASR #25
+ add r10, r10, r11
+ sub r9, r9, r11, LSL #25
+ mov r11, r10, ASR #26
+ add r1, r1, r11
+ sub r10, r10, r11, LSL #26
+ mov r11, r1, ASR #25
+ sub r1, r1, r11, LSL #25
+ add r2, r2, r3, LSL #26
+ mov r3, r3, LSR #6
+ add r3, r3, r4, LSL #19
+ mov r4, r4, LSR #13
+ add r4, r4, r5, LSL #13
+ mov r5, r5, LSR #19
+ add r5, r5, r6, LSL #6
+ add r6, r7, r8, LSL #25
+ mov r7, r8, LSR #7
+ add r7, r7, r9, LSL #19
+ mov r8, r9, LSR #13
+ add r8, r8, r10, LSL #12
+ mov r9, r10, LSR #20
+ add r1, r9, r1, LSL #6
+ str r2, [r0]
+ str r3, [r0, #4]
+ str r4, [r0, #8]
+ str r5, [r0, #12]
+ str r6, [r0, #16]
+ str r7, [r0, #20]
+ str r8, [r0, #24]
+ str r1, [r0, #28]
+ movw r0, #0
+ mov sp, ip
+ pop {r4-r11, pc}
+ENDPROC(curve25519_neon)
diff --git a/arch/arm/crypto/curve25519-glue.c b/arch/arm/crypto/curve25519-glue.c
new file mode 100644
index 0000000..31eb75b
--- /dev/null
+++ b/arch/arm/crypto/curve25519-glue.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
+ *
+ * Based on public domain code from Daniel J. Bernstein and Peter Schwabe. This
+ * began from SUPERCOP's curve25519/neon2/scalarmult.s, but has subsequently been
+ * manually reworked for use in kernel space.
+ */
+
+#include <asm/hwcap.h>
+#include <asm/neon.h>
+#include <asm/simd.h>
+#include <crypto/internal/kpp.h>
+#include <crypto/internal/simd.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/jump_label.h>
+#include <linux/scatterlist.h>
+#include <crypto/curve25519.h>
+
+asmlinkage void curve25519_neon(u8 mypublic[CURVE25519_KEY_SIZE],
+ const u8 secret[CURVE25519_KEY_SIZE],
+ const u8 basepoint[CURVE25519_KEY_SIZE]);
+
+static __ro_after_init DEFINE_STATIC_KEY_FALSE(have_neon);
+
+void curve25519_arch(u8 out[CURVE25519_KEY_SIZE],
+ const u8 scalar[CURVE25519_KEY_SIZE],
+ const u8 point[CURVE25519_KEY_SIZE])
+{
+ if (static_branch_likely(&have_neon) && crypto_simd_usable()) {
+ kernel_neon_begin();
+ curve25519_neon(out, scalar, point);
+ kernel_neon_end();
+ } else {
+ curve25519_generic(out, scalar, point);
+ }
+}
+EXPORT_SYMBOL(curve25519_arch);
+
+void curve25519_base_arch(u8 pub[CURVE25519_KEY_SIZE],
+ const u8 secret[CURVE25519_KEY_SIZE])
+{
+ return curve25519_arch(pub, secret, curve25519_base_point);
+}
+EXPORT_SYMBOL(curve25519_base_arch);
+
+static int curve25519_set_secret(struct crypto_kpp *tfm, const void *buf,
+ unsigned int len)
+{
+ u8 *secret = kpp_tfm_ctx(tfm);
+
+ if (!len)
+ curve25519_generate_secret(secret);
+ else if (len == CURVE25519_KEY_SIZE &&
+ crypto_memneq(buf, curve25519_null_point, CURVE25519_KEY_SIZE))
+ memcpy(secret, buf, CURVE25519_KEY_SIZE);
+ else
+ return -EINVAL;
+ return 0;
+}
+
+static int curve25519_compute_value(struct kpp_request *req)
+{
+ struct crypto_kpp *tfm = crypto_kpp_reqtfm(req);
+ const u8 *secret = kpp_tfm_ctx(tfm);
+ u8 public_key[CURVE25519_KEY_SIZE];
+ u8 buf[CURVE25519_KEY_SIZE];
+ int copied, nbytes;
+ u8 const *bp;
+
+ if (req->src) {
+ copied = sg_copy_to_buffer(req->src,
+ sg_nents_for_len(req->src,
+ CURVE25519_KEY_SIZE),
+ public_key, CURVE25519_KEY_SIZE);
+ if (copied != CURVE25519_KEY_SIZE)
+ return -EINVAL;
+ bp = public_key;
+ } else {
+ bp = curve25519_base_point;
+ }
+
+ curve25519_arch(buf, secret, bp);
+
+ /* might want less than we've got */
+ nbytes = min_t(size_t, CURVE25519_KEY_SIZE, req->dst_len);
+ copied = sg_copy_from_buffer(req->dst, sg_nents_for_len(req->dst,
+ nbytes),
+ buf, nbytes);
+ if (copied != nbytes)
+ return -EINVAL;
+ return 0;
+}
+
+static unsigned int curve25519_max_size(struct crypto_kpp *tfm)
+{
+ return CURVE25519_KEY_SIZE;
+}
+
+static struct kpp_alg curve25519_alg = {
+ .base.cra_name = "curve25519",
+ .base.cra_driver_name = "curve25519-neon",
+ .base.cra_priority = 200,
+ .base.cra_module = THIS_MODULE,
+ .base.cra_ctxsize = CURVE25519_KEY_SIZE,
+
+ .set_secret = curve25519_set_secret,
+ .generate_public_key = curve25519_compute_value,
+ .compute_shared_secret = curve25519_compute_value,
+ .max_size = curve25519_max_size,
+};
+
+static int __init mod_init(void)
+{
+ if (elf_hwcap & HWCAP_NEON) {
+ static_branch_enable(&have_neon);
+ return IS_REACHABLE(CONFIG_CRYPTO_KPP) ?
+ crypto_register_kpp(&curve25519_alg) : 0;
+ }
+ return 0;
+}
+
+static void __exit mod_exit(void)
+{
+ if (IS_REACHABLE(CONFIG_CRYPTO_KPP) && elf_hwcap & HWCAP_NEON)
+ crypto_unregister_kpp(&curve25519_alg);
+}
+
+module_init(mod_init);
+module_exit(mod_exit);
+
+MODULE_ALIAS_CRYPTO("curve25519");
+MODULE_ALIAS_CRYPTO("curve25519-neon");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/crypto/ghash-ce-core.S b/arch/arm/crypto/ghash-ce-core.S
index c47fe81..9f51e3f 100644
--- a/arch/arm/crypto/ghash-ce-core.S
+++ b/arch/arm/crypto/ghash-ce-core.S
@@ -8,6 +8,9 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
+ .arch armv8-a
+ .fpu crypto-neon-fp-armv8
+
SHASH .req q0
T1 .req q1
XL .req q2
@@ -88,7 +91,6 @@
T3_H .req d17
.text
- .fpu crypto-neon-fp-armv8
.macro __pmull_p64, rd, rn, rm, b1, b2, b3, b4
vmull.p64 \rd, \rn, \rm
diff --git a/arch/arm/crypto/ghash-ce-glue.c b/arch/arm/crypto/ghash-ce-glue.c
index c691077..f13401f 100644
--- a/arch/arm/crypto/ghash-ce-glue.c
+++ b/arch/arm/crypto/ghash-ce-glue.c
@@ -16,6 +16,7 @@
#include <crypto/gf128mul.h>
#include <linux/cpufeature.h>
#include <linux/crypto.h>
+#include <linux/jump_label.h>
#include <linux/module.h>
MODULE_DESCRIPTION("GHASH hash function using ARMv8 Crypto Extensions");
@@ -27,12 +28,8 @@
#define GHASH_DIGEST_SIZE 16
struct ghash_key {
- u64 h[2];
- u64 h2[2];
- u64 h3[2];
- u64 h4[2];
-
be128 k;
+ u64 h[][2];
};
struct ghash_desc_ctx {
@@ -46,16 +43,12 @@
};
asmlinkage void pmull_ghash_update_p64(int blocks, u64 dg[], const char *src,
- struct ghash_key const *k,
- const char *head);
+ u64 const h[][2], const char *head);
asmlinkage void pmull_ghash_update_p8(int blocks, u64 dg[], const char *src,
- struct ghash_key const *k,
- const char *head);
+ u64 const h[][2], const char *head);
-static void (*pmull_ghash_update)(int blocks, u64 dg[], const char *src,
- struct ghash_key const *k,
- const char *head);
+static __ro_after_init DEFINE_STATIC_KEY_FALSE(use_p64);
static int ghash_init(struct shash_desc *desc)
{
@@ -70,7 +63,10 @@
{
if (likely(crypto_simd_usable())) {
kernel_neon_begin();
- pmull_ghash_update(blocks, dg, src, key, head);
+ if (static_branch_likely(&use_p64))
+ pmull_ghash_update_p64(blocks, dg, src, key->h, head);
+ else
+ pmull_ghash_update_p8(blocks, dg, src, key->h, head);
kernel_neon_end();
} else {
be128 dst = { cpu_to_be64(dg[1]), cpu_to_be64(dg[0]) };
@@ -161,27 +157,26 @@
const u8 *inkey, unsigned int keylen)
{
struct ghash_key *key = crypto_shash_ctx(tfm);
- be128 h;
- if (keylen != GHASH_BLOCK_SIZE) {
- crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ if (keylen != GHASH_BLOCK_SIZE)
return -EINVAL;
- }
/* needed for the fallback */
memcpy(&key->k, inkey, GHASH_BLOCK_SIZE);
- ghash_reflect(key->h, &key->k);
+ ghash_reflect(key->h[0], &key->k);
- h = key->k;
- gf128mul_lle(&h, &key->k);
- ghash_reflect(key->h2, &h);
+ if (static_branch_likely(&use_p64)) {
+ be128 h = key->k;
- gf128mul_lle(&h, &key->k);
- ghash_reflect(key->h3, &h);
+ gf128mul_lle(&h, &key->k);
+ ghash_reflect(key->h[1], &h);
- gf128mul_lle(&h, &key->k);
- ghash_reflect(key->h4, &h);
+ gf128mul_lle(&h, &key->k);
+ ghash_reflect(key->h[2], &h);
+ gf128mul_lle(&h, &key->k);
+ ghash_reflect(key->h[3], &h);
+ }
return 0;
}
@@ -197,7 +192,7 @@
.base.cra_driver_name = "ghash-ce-sync",
.base.cra_priority = 300 - 1,
.base.cra_blocksize = GHASH_BLOCK_SIZE,
- .base.cra_ctxsize = sizeof(struct ghash_key),
+ .base.cra_ctxsize = sizeof(struct ghash_key) + sizeof(u64[2]),
.base.cra_module = THIS_MODULE,
};
@@ -296,16 +291,11 @@
{
struct ghash_async_ctx *ctx = crypto_ahash_ctx(tfm);
struct crypto_ahash *child = &ctx->cryptd_tfm->base;
- int err;
crypto_ahash_clear_flags(child, CRYPTO_TFM_REQ_MASK);
crypto_ahash_set_flags(child, crypto_ahash_get_flags(tfm)
& CRYPTO_TFM_REQ_MASK);
- err = crypto_ahash_setkey(child, key, keylen);
- crypto_ahash_set_flags(tfm, crypto_ahash_get_flags(child)
- & CRYPTO_TFM_RES_MASK);
-
- return err;
+ return crypto_ahash_setkey(child, key, keylen);
}
static int ghash_async_init_tfm(struct crypto_tfm *tfm)
@@ -361,10 +351,10 @@
if (!(elf_hwcap & HWCAP_NEON))
return -ENODEV;
- if (elf_hwcap2 & HWCAP2_PMULL)
- pmull_ghash_update = pmull_ghash_update_p64;
- else
- pmull_ghash_update = pmull_ghash_update_p8;
+ if (elf_hwcap2 & HWCAP2_PMULL) {
+ ghash_alg.base.cra_ctxsize += 3 * sizeof(u64[2]);
+ static_branch_enable(&use_p64);
+ }
err = crypto_register_shash(&ghash_alg);
if (err)
diff --git a/arch/arm/crypto/poly1305-armv4.pl b/arch/arm/crypto/poly1305-armv4.pl
new file mode 100644
index 0000000..6d79498
--- /dev/null
+++ b/arch/arm/crypto/poly1305-armv4.pl
@@ -0,0 +1,1236 @@
+#!/usr/bin/env perl
+# SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
+#
+# ====================================================================
+# Written by Andy Polyakov, @dot-asm, initially for the OpenSSL
+# project.
+# ====================================================================
+#
+# IALU(*)/gcc-4.4 NEON
+#
+# ARM11xx(ARMv6) 7.78/+100% -
+# Cortex-A5 6.35/+130% 3.00
+# Cortex-A8 6.25/+115% 2.36
+# Cortex-A9 5.10/+95% 2.55
+# Cortex-A15 3.85/+85% 1.25(**)
+# Snapdragon S4 5.70/+100% 1.48(**)
+#
+# (*) this is for -march=armv6, i.e. with bunch of ldrb loading data;
+# (**) these are trade-off results, they can be improved by ~8% but at
+# the cost of 15/12% regression on Cortex-A5/A7, it's even possible
+# to improve Cortex-A9 result, but then A5/A7 loose more than 20%;
+
+$flavour = shift;
+if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; }
+else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} }
+
+if ($flavour && $flavour ne "void") {
+ $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
+ ( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or
+ ( $xlate="${dir}../../perlasm/arm-xlate.pl" and -f $xlate) or
+ die "can't locate arm-xlate.pl";
+
+ open STDOUT,"| \"$^X\" $xlate $flavour $output";
+} else {
+ open STDOUT,">$output";
+}
+
+($ctx,$inp,$len,$padbit)=map("r$_",(0..3));
+
+$code.=<<___;
+#ifndef __KERNEL__
+# include "arm_arch.h"
+#else
+# define __ARM_ARCH__ __LINUX_ARM_ARCH__
+# define __ARM_MAX_ARCH__ __LINUX_ARM_ARCH__
+# define poly1305_init poly1305_init_arm
+# define poly1305_blocks poly1305_blocks_arm
+# define poly1305_emit poly1305_emit_arm
+.globl poly1305_blocks_neon
+#endif
+
+#if defined(__thumb2__)
+.syntax unified
+.thumb
+#else
+.code 32
+#endif
+
+.text
+
+.globl poly1305_emit
+.globl poly1305_blocks
+.globl poly1305_init
+.type poly1305_init,%function
+.align 5
+poly1305_init:
+.Lpoly1305_init:
+ stmdb sp!,{r4-r11}
+
+ eor r3,r3,r3
+ cmp $inp,#0
+ str r3,[$ctx,#0] @ zero hash value
+ str r3,[$ctx,#4]
+ str r3,[$ctx,#8]
+ str r3,[$ctx,#12]
+ str r3,[$ctx,#16]
+ str r3,[$ctx,#36] @ clear is_base2_26
+ add $ctx,$ctx,#20
+
+#ifdef __thumb2__
+ it eq
+#endif
+ moveq r0,#0
+ beq .Lno_key
+
+#if __ARM_MAX_ARCH__>=7
+ mov r3,#-1
+ str r3,[$ctx,#28] @ impossible key power value
+# ifndef __KERNEL__
+ adr r11,.Lpoly1305_init
+ ldr r12,.LOPENSSL_armcap
+# endif
+#endif
+ ldrb r4,[$inp,#0]
+ mov r10,#0x0fffffff
+ ldrb r5,[$inp,#1]
+ and r3,r10,#-4 @ 0x0ffffffc
+ ldrb r6,[$inp,#2]
+ ldrb r7,[$inp,#3]
+ orr r4,r4,r5,lsl#8
+ ldrb r5,[$inp,#4]
+ orr r4,r4,r6,lsl#16
+ ldrb r6,[$inp,#5]
+ orr r4,r4,r7,lsl#24
+ ldrb r7,[$inp,#6]
+ and r4,r4,r10
+
+#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
+# if !defined(_WIN32)
+ ldr r12,[r11,r12] @ OPENSSL_armcap_P
+# endif
+# if defined(__APPLE__) || defined(_WIN32)
+ ldr r12,[r12]
+# endif
+#endif
+ ldrb r8,[$inp,#7]
+ orr r5,r5,r6,lsl#8
+ ldrb r6,[$inp,#8]
+ orr r5,r5,r7,lsl#16
+ ldrb r7,[$inp,#9]
+ orr r5,r5,r8,lsl#24
+ ldrb r8,[$inp,#10]
+ and r5,r5,r3
+
+#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
+ tst r12,#ARMV7_NEON @ check for NEON
+# ifdef __thumb2__
+ adr r9,.Lpoly1305_blocks_neon
+ adr r11,.Lpoly1305_blocks
+ it ne
+ movne r11,r9
+ adr r12,.Lpoly1305_emit
+ orr r11,r11,#1 @ thumb-ify addresses
+ orr r12,r12,#1
+# else
+ add r12,r11,#(.Lpoly1305_emit-.Lpoly1305_init)
+ ite eq
+ addeq r11,r11,#(.Lpoly1305_blocks-.Lpoly1305_init)
+ addne r11,r11,#(.Lpoly1305_blocks_neon-.Lpoly1305_init)
+# endif
+#endif
+ ldrb r9,[$inp,#11]
+ orr r6,r6,r7,lsl#8
+ ldrb r7,[$inp,#12]
+ orr r6,r6,r8,lsl#16
+ ldrb r8,[$inp,#13]
+ orr r6,r6,r9,lsl#24
+ ldrb r9,[$inp,#14]
+ and r6,r6,r3
+
+ ldrb r10,[$inp,#15]
+ orr r7,r7,r8,lsl#8
+ str r4,[$ctx,#0]
+ orr r7,r7,r9,lsl#16
+ str r5,[$ctx,#4]
+ orr r7,r7,r10,lsl#24
+ str r6,[$ctx,#8]
+ and r7,r7,r3
+ str r7,[$ctx,#12]
+#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
+ stmia r2,{r11,r12} @ fill functions table
+ mov r0,#1
+#else
+ mov r0,#0
+#endif
+.Lno_key:
+ ldmia sp!,{r4-r11}
+#if __ARM_ARCH__>=5
+ ret @ bx lr
+#else
+ tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ bx lr @ interoperable with Thumb ISA:-)
+#endif
+.size poly1305_init,.-poly1305_init
+___
+{
+my ($h0,$h1,$h2,$h3,$h4,$r0,$r1,$r2,$r3)=map("r$_",(4..12));
+my ($s1,$s2,$s3)=($r1,$r2,$r3);
+
+$code.=<<___;
+.type poly1305_blocks,%function
+.align 5
+poly1305_blocks:
+.Lpoly1305_blocks:
+ stmdb sp!,{r3-r11,lr}
+
+ ands $len,$len,#-16
+ beq .Lno_data
+
+ add $len,$len,$inp @ end pointer
+ sub sp,sp,#32
+
+#if __ARM_ARCH__<7
+ ldmia $ctx,{$h0-$r3} @ load context
+ add $ctx,$ctx,#20
+ str $len,[sp,#16] @ offload stuff
+ str $ctx,[sp,#12]
+#else
+ ldr lr,[$ctx,#36] @ is_base2_26
+ ldmia $ctx!,{$h0-$h4} @ load hash value
+ str $len,[sp,#16] @ offload stuff
+ str $ctx,[sp,#12]
+
+ adds $r0,$h0,$h1,lsl#26 @ base 2^26 -> base 2^32
+ mov $r1,$h1,lsr#6
+ adcs $r1,$r1,$h2,lsl#20
+ mov $r2,$h2,lsr#12
+ adcs $r2,$r2,$h3,lsl#14
+ mov $r3,$h3,lsr#18
+ adcs $r3,$r3,$h4,lsl#8
+ mov $len,#0
+ teq lr,#0
+ str $len,[$ctx,#16] @ clear is_base2_26
+ adc $len,$len,$h4,lsr#24
+
+ itttt ne
+ movne $h0,$r0 @ choose between radixes
+ movne $h1,$r1
+ movne $h2,$r2
+ movne $h3,$r3
+ ldmia $ctx,{$r0-$r3} @ load key
+ it ne
+ movne $h4,$len
+#endif
+
+ mov lr,$inp
+ cmp $padbit,#0
+ str $r1,[sp,#20]
+ str $r2,[sp,#24]
+ str $r3,[sp,#28]
+ b .Loop
+
+.align 4
+.Loop:
+#if __ARM_ARCH__<7
+ ldrb r0,[lr],#16 @ load input
+# ifdef __thumb2__
+ it hi
+# endif
+ addhi $h4,$h4,#1 @ 1<<128
+ ldrb r1,[lr,#-15]
+ ldrb r2,[lr,#-14]
+ ldrb r3,[lr,#-13]
+ orr r1,r0,r1,lsl#8
+ ldrb r0,[lr,#-12]
+ orr r2,r1,r2,lsl#16
+ ldrb r1,[lr,#-11]
+ orr r3,r2,r3,lsl#24
+ ldrb r2,[lr,#-10]
+ adds $h0,$h0,r3 @ accumulate input
+
+ ldrb r3,[lr,#-9]
+ orr r1,r0,r1,lsl#8
+ ldrb r0,[lr,#-8]
+ orr r2,r1,r2,lsl#16
+ ldrb r1,[lr,#-7]
+ orr r3,r2,r3,lsl#24
+ ldrb r2,[lr,#-6]
+ adcs $h1,$h1,r3
+
+ ldrb r3,[lr,#-5]
+ orr r1,r0,r1,lsl#8
+ ldrb r0,[lr,#-4]
+ orr r2,r1,r2,lsl#16
+ ldrb r1,[lr,#-3]
+ orr r3,r2,r3,lsl#24
+ ldrb r2,[lr,#-2]
+ adcs $h2,$h2,r3
+
+ ldrb r3,[lr,#-1]
+ orr r1,r0,r1,lsl#8
+ str lr,[sp,#8] @ offload input pointer
+ orr r2,r1,r2,lsl#16
+ add $s1,$r1,$r1,lsr#2
+ orr r3,r2,r3,lsl#24
+#else
+ ldr r0,[lr],#16 @ load input
+ it hi
+ addhi $h4,$h4,#1 @ padbit
+ ldr r1,[lr,#-12]
+ ldr r2,[lr,#-8]
+ ldr r3,[lr,#-4]
+# ifdef __ARMEB__
+ rev r0,r0
+ rev r1,r1
+ rev r2,r2
+ rev r3,r3
+# endif
+ adds $h0,$h0,r0 @ accumulate input
+ str lr,[sp,#8] @ offload input pointer
+ adcs $h1,$h1,r1
+ add $s1,$r1,$r1,lsr#2
+ adcs $h2,$h2,r2
+#endif
+ add $s2,$r2,$r2,lsr#2
+ adcs $h3,$h3,r3
+ add $s3,$r3,$r3,lsr#2
+
+ umull r2,r3,$h1,$r0
+ adc $h4,$h4,#0
+ umull r0,r1,$h0,$r0
+ umlal r2,r3,$h4,$s1
+ umlal r0,r1,$h3,$s1
+ ldr $r1,[sp,#20] @ reload $r1
+ umlal r2,r3,$h2,$s3
+ umlal r0,r1,$h1,$s3
+ umlal r2,r3,$h3,$s2
+ umlal r0,r1,$h2,$s2
+ umlal r2,r3,$h0,$r1
+ str r0,[sp,#0] @ future $h0
+ mul r0,$s2,$h4
+ ldr $r2,[sp,#24] @ reload $r2
+ adds r2,r2,r1 @ d1+=d0>>32
+ eor r1,r1,r1
+ adc lr,r3,#0 @ future $h2
+ str r2,[sp,#4] @ future $h1
+
+ mul r2,$s3,$h4
+ eor r3,r3,r3
+ umlal r0,r1,$h3,$s3
+ ldr $r3,[sp,#28] @ reload $r3
+ umlal r2,r3,$h3,$r0
+ umlal r0,r1,$h2,$r0
+ umlal r2,r3,$h2,$r1
+ umlal r0,r1,$h1,$r1
+ umlal r2,r3,$h1,$r2
+ umlal r0,r1,$h0,$r2
+ umlal r2,r3,$h0,$r3
+ ldr $h0,[sp,#0]
+ mul $h4,$r0,$h4
+ ldr $h1,[sp,#4]
+
+ adds $h2,lr,r0 @ d2+=d1>>32
+ ldr lr,[sp,#8] @ reload input pointer
+ adc r1,r1,#0
+ adds $h3,r2,r1 @ d3+=d2>>32
+ ldr r0,[sp,#16] @ reload end pointer
+ adc r3,r3,#0
+ add $h4,$h4,r3 @ h4+=d3>>32
+
+ and r1,$h4,#-4
+ and $h4,$h4,#3
+ add r1,r1,r1,lsr#2 @ *=5
+ adds $h0,$h0,r1
+ adcs $h1,$h1,#0
+ adcs $h2,$h2,#0
+ adcs $h3,$h3,#0
+ adc $h4,$h4,#0
+
+ cmp r0,lr @ done yet?
+ bhi .Loop
+
+ ldr $ctx,[sp,#12]
+ add sp,sp,#32
+ stmdb $ctx,{$h0-$h4} @ store the result
+
+.Lno_data:
+#if __ARM_ARCH__>=5
+ ldmia sp!,{r3-r11,pc}
+#else
+ ldmia sp!,{r3-r11,lr}
+ tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ bx lr @ interoperable with Thumb ISA:-)
+#endif
+.size poly1305_blocks,.-poly1305_blocks
+___
+}
+{
+my ($ctx,$mac,$nonce)=map("r$_",(0..2));
+my ($h0,$h1,$h2,$h3,$h4,$g0,$g1,$g2,$g3)=map("r$_",(3..11));
+my $g4=$ctx;
+
+$code.=<<___;
+.type poly1305_emit,%function
+.align 5
+poly1305_emit:
+.Lpoly1305_emit:
+ stmdb sp!,{r4-r11}
+
+ ldmia $ctx,{$h0-$h4}
+
+#if __ARM_ARCH__>=7
+ ldr ip,[$ctx,#36] @ is_base2_26
+
+ adds $g0,$h0,$h1,lsl#26 @ base 2^26 -> base 2^32
+ mov $g1,$h1,lsr#6
+ adcs $g1,$g1,$h2,lsl#20
+ mov $g2,$h2,lsr#12
+ adcs $g2,$g2,$h3,lsl#14
+ mov $g3,$h3,lsr#18
+ adcs $g3,$g3,$h4,lsl#8
+ mov $g4,#0
+ adc $g4,$g4,$h4,lsr#24
+
+ tst ip,ip
+ itttt ne
+ movne $h0,$g0
+ movne $h1,$g1
+ movne $h2,$g2
+ movne $h3,$g3
+ it ne
+ movne $h4,$g4
+#endif
+
+ adds $g0,$h0,#5 @ compare to modulus
+ adcs $g1,$h1,#0
+ adcs $g2,$h2,#0
+ adcs $g3,$h3,#0
+ adc $g4,$h4,#0
+ tst $g4,#4 @ did it carry/borrow?
+
+#ifdef __thumb2__
+ it ne
+#endif
+ movne $h0,$g0
+ ldr $g0,[$nonce,#0]
+#ifdef __thumb2__
+ it ne
+#endif
+ movne $h1,$g1
+ ldr $g1,[$nonce,#4]
+#ifdef __thumb2__
+ it ne
+#endif
+ movne $h2,$g2
+ ldr $g2,[$nonce,#8]
+#ifdef __thumb2__
+ it ne
+#endif
+ movne $h3,$g3
+ ldr $g3,[$nonce,#12]
+
+ adds $h0,$h0,$g0
+ adcs $h1,$h1,$g1
+ adcs $h2,$h2,$g2
+ adc $h3,$h3,$g3
+
+#if __ARM_ARCH__>=7
+# ifdef __ARMEB__
+ rev $h0,$h0
+ rev $h1,$h1
+ rev $h2,$h2
+ rev $h3,$h3
+# endif
+ str $h0,[$mac,#0]
+ str $h1,[$mac,#4]
+ str $h2,[$mac,#8]
+ str $h3,[$mac,#12]
+#else
+ strb $h0,[$mac,#0]
+ mov $h0,$h0,lsr#8
+ strb $h1,[$mac,#4]
+ mov $h1,$h1,lsr#8
+ strb $h2,[$mac,#8]
+ mov $h2,$h2,lsr#8
+ strb $h3,[$mac,#12]
+ mov $h3,$h3,lsr#8
+
+ strb $h0,[$mac,#1]
+ mov $h0,$h0,lsr#8
+ strb $h1,[$mac,#5]
+ mov $h1,$h1,lsr#8
+ strb $h2,[$mac,#9]
+ mov $h2,$h2,lsr#8
+ strb $h3,[$mac,#13]
+ mov $h3,$h3,lsr#8
+
+ strb $h0,[$mac,#2]
+ mov $h0,$h0,lsr#8
+ strb $h1,[$mac,#6]
+ mov $h1,$h1,lsr#8
+ strb $h2,[$mac,#10]
+ mov $h2,$h2,lsr#8
+ strb $h3,[$mac,#14]
+ mov $h3,$h3,lsr#8
+
+ strb $h0,[$mac,#3]
+ strb $h1,[$mac,#7]
+ strb $h2,[$mac,#11]
+ strb $h3,[$mac,#15]
+#endif
+ ldmia sp!,{r4-r11}
+#if __ARM_ARCH__>=5
+ ret @ bx lr
+#else
+ tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ bx lr @ interoperable with Thumb ISA:-)
+#endif
+.size poly1305_emit,.-poly1305_emit
+___
+{
+my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("d$_",(0..9));
+my ($D0,$D1,$D2,$D3,$D4, $H0,$H1,$H2,$H3,$H4) = map("q$_",(5..14));
+my ($T0,$T1,$MASK) = map("q$_",(15,4,0));
+
+my ($in2,$zeros,$tbl0,$tbl1) = map("r$_",(4..7));
+
+$code.=<<___;
+#if __ARM_MAX_ARCH__>=7
+.fpu neon
+
+.type poly1305_init_neon,%function
+.align 5
+poly1305_init_neon:
+.Lpoly1305_init_neon:
+ ldr r3,[$ctx,#48] @ first table element
+ cmp r3,#-1 @ is value impossible?
+ bne .Lno_init_neon
+
+ ldr r4,[$ctx,#20] @ load key base 2^32
+ ldr r5,[$ctx,#24]
+ ldr r6,[$ctx,#28]
+ ldr r7,[$ctx,#32]
+
+ and r2,r4,#0x03ffffff @ base 2^32 -> base 2^26
+ mov r3,r4,lsr#26
+ mov r4,r5,lsr#20
+ orr r3,r3,r5,lsl#6
+ mov r5,r6,lsr#14
+ orr r4,r4,r6,lsl#12
+ mov r6,r7,lsr#8
+ orr r5,r5,r7,lsl#18
+ and r3,r3,#0x03ffffff
+ and r4,r4,#0x03ffffff
+ and r5,r5,#0x03ffffff
+
+ vdup.32 $R0,r2 @ r^1 in both lanes
+ add r2,r3,r3,lsl#2 @ *5
+ vdup.32 $R1,r3
+ add r3,r4,r4,lsl#2
+ vdup.32 $S1,r2
+ vdup.32 $R2,r4
+ add r4,r5,r5,lsl#2
+ vdup.32 $S2,r3
+ vdup.32 $R3,r5
+ add r5,r6,r6,lsl#2
+ vdup.32 $S3,r4
+ vdup.32 $R4,r6
+ vdup.32 $S4,r5
+
+ mov $zeros,#2 @ counter
+
+.Lsquare_neon:
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
+ @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
+ @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
+ @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
+ @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
+
+ vmull.u32 $D0,$R0,${R0}[1]
+ vmull.u32 $D1,$R1,${R0}[1]
+ vmull.u32 $D2,$R2,${R0}[1]
+ vmull.u32 $D3,$R3,${R0}[1]
+ vmull.u32 $D4,$R4,${R0}[1]
+
+ vmlal.u32 $D0,$R4,${S1}[1]
+ vmlal.u32 $D1,$R0,${R1}[1]
+ vmlal.u32 $D2,$R1,${R1}[1]
+ vmlal.u32 $D3,$R2,${R1}[1]
+ vmlal.u32 $D4,$R3,${R1}[1]
+
+ vmlal.u32 $D0,$R3,${S2}[1]
+ vmlal.u32 $D1,$R4,${S2}[1]
+ vmlal.u32 $D3,$R1,${R2}[1]
+ vmlal.u32 $D2,$R0,${R2}[1]
+ vmlal.u32 $D4,$R2,${R2}[1]
+
+ vmlal.u32 $D0,$R2,${S3}[1]
+ vmlal.u32 $D3,$R0,${R3}[1]
+ vmlal.u32 $D1,$R3,${S3}[1]
+ vmlal.u32 $D2,$R4,${S3}[1]
+ vmlal.u32 $D4,$R1,${R3}[1]
+
+ vmlal.u32 $D3,$R4,${S4}[1]
+ vmlal.u32 $D0,$R1,${S4}[1]
+ vmlal.u32 $D1,$R2,${S4}[1]
+ vmlal.u32 $D2,$R3,${S4}[1]
+ vmlal.u32 $D4,$R0,${R4}[1]
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ lazy reduction as discussed in "NEON crypto" by D.J. Bernstein
+ @ and P. Schwabe
+ @
+ @ H0>>+H1>>+H2>>+H3>>+H4
+ @ H3>>+H4>>*5+H0>>+H1
+ @
+ @ Trivia.
+ @
+ @ Result of multiplication of n-bit number by m-bit number is
+ @ n+m bits wide. However! Even though 2^n is a n+1-bit number,
+ @ m-bit number multiplied by 2^n is still n+m bits wide.
+ @
+ @ Sum of two n-bit numbers is n+1 bits wide, sum of three - n+2,
+ @ and so is sum of four. Sum of 2^m n-m-bit numbers and n-bit
+ @ one is n+1 bits wide.
+ @
+ @ >>+ denotes Hnext += Hn>>26, Hn &= 0x3ffffff. This means that
+ @ H0, H2, H3 are guaranteed to be 26 bits wide, while H1 and H4
+ @ can be 27. However! In cases when their width exceeds 26 bits
+ @ they are limited by 2^26+2^6. This in turn means that *sum*
+ @ of the products with these values can still be viewed as sum
+ @ of 52-bit numbers as long as the amount of addends is not a
+ @ power of 2. For example,
+ @
+ @ H4 = H4*R0 + H3*R1 + H2*R2 + H1*R3 + H0 * R4,
+ @
+ @ which can't be larger than 5 * (2^26 + 2^6) * (2^26 + 2^6), or
+ @ 5 * (2^52 + 2*2^32 + 2^12), which in turn is smaller than
+ @ 8 * (2^52) or 2^55. However, the value is then multiplied by
+ @ by 5, so we should be looking at 5 * 5 * (2^52 + 2^33 + 2^12),
+ @ which is less than 32 * (2^52) or 2^57. And when processing
+ @ data we are looking at triple as many addends...
+ @
+ @ In key setup procedure pre-reduced H0 is limited by 5*4+1 and
+ @ 5*H4 - by 5*5 52-bit addends, or 57 bits. But when hashing the
+ @ input H0 is limited by (5*4+1)*3 addends, or 58 bits, while
+ @ 5*H4 by 5*5*3, or 59[!] bits. How is this relevant? vmlal.u32
+ @ instruction accepts 2x32-bit input and writes 2x64-bit result.
+ @ This means that result of reduction have to be compressed upon
+ @ loop wrap-around. This can be done in the process of reduction
+ @ to minimize amount of instructions [as well as amount of
+ @ 128-bit instructions, which benefits low-end processors], but
+ @ one has to watch for H2 (which is narrower than H0) and 5*H4
+ @ not being wider than 58 bits, so that result of right shift
+ @ by 26 bits fits in 32 bits. This is also useful on x86,
+ @ because it allows to use paddd in place for paddq, which
+ @ benefits Atom, where paddq is ridiculously slow.
+
+ vshr.u64 $T0,$D3,#26
+ vmovn.i64 $D3#lo,$D3
+ vshr.u64 $T1,$D0,#26
+ vmovn.i64 $D0#lo,$D0
+ vadd.i64 $D4,$D4,$T0 @ h3 -> h4
+ vbic.i32 $D3#lo,#0xfc000000 @ &=0x03ffffff
+ vadd.i64 $D1,$D1,$T1 @ h0 -> h1
+ vbic.i32 $D0#lo,#0xfc000000
+
+ vshrn.u64 $T0#lo,$D4,#26
+ vmovn.i64 $D4#lo,$D4
+ vshr.u64 $T1,$D1,#26
+ vmovn.i64 $D1#lo,$D1
+ vadd.i64 $D2,$D2,$T1 @ h1 -> h2
+ vbic.i32 $D4#lo,#0xfc000000
+ vbic.i32 $D1#lo,#0xfc000000
+
+ vadd.i32 $D0#lo,$D0#lo,$T0#lo
+ vshl.u32 $T0#lo,$T0#lo,#2
+ vshrn.u64 $T1#lo,$D2,#26
+ vmovn.i64 $D2#lo,$D2
+ vadd.i32 $D0#lo,$D0#lo,$T0#lo @ h4 -> h0
+ vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
+ vbic.i32 $D2#lo,#0xfc000000
+
+ vshr.u32 $T0#lo,$D0#lo,#26
+ vbic.i32 $D0#lo,#0xfc000000
+ vshr.u32 $T1#lo,$D3#lo,#26
+ vbic.i32 $D3#lo,#0xfc000000
+ vadd.i32 $D1#lo,$D1#lo,$T0#lo @ h0 -> h1
+ vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
+
+ subs $zeros,$zeros,#1
+ beq .Lsquare_break_neon
+
+ add $tbl0,$ctx,#(48+0*9*4)
+ add $tbl1,$ctx,#(48+1*9*4)
+
+ vtrn.32 $R0,$D0#lo @ r^2:r^1
+ vtrn.32 $R2,$D2#lo
+ vtrn.32 $R3,$D3#lo
+ vtrn.32 $R1,$D1#lo
+ vtrn.32 $R4,$D4#lo
+
+ vshl.u32 $S2,$R2,#2 @ *5
+ vshl.u32 $S3,$R3,#2
+ vshl.u32 $S1,$R1,#2
+ vshl.u32 $S4,$R4,#2
+ vadd.i32 $S2,$S2,$R2
+ vadd.i32 $S1,$S1,$R1
+ vadd.i32 $S3,$S3,$R3
+ vadd.i32 $S4,$S4,$R4
+
+ vst4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]!
+ vst4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]!
+ vst4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
+ vst4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
+ vst1.32 {${S4}[0]},[$tbl0,:32]
+ vst1.32 {${S4}[1]},[$tbl1,:32]
+
+ b .Lsquare_neon
+
+.align 4
+.Lsquare_break_neon:
+ add $tbl0,$ctx,#(48+2*4*9)
+ add $tbl1,$ctx,#(48+3*4*9)
+
+ vmov $R0,$D0#lo @ r^4:r^3
+ vshl.u32 $S1,$D1#lo,#2 @ *5
+ vmov $R1,$D1#lo
+ vshl.u32 $S2,$D2#lo,#2
+ vmov $R2,$D2#lo
+ vshl.u32 $S3,$D3#lo,#2
+ vmov $R3,$D3#lo
+ vshl.u32 $S4,$D4#lo,#2
+ vmov $R4,$D4#lo
+ vadd.i32 $S1,$S1,$D1#lo
+ vadd.i32 $S2,$S2,$D2#lo
+ vadd.i32 $S3,$S3,$D3#lo
+ vadd.i32 $S4,$S4,$D4#lo
+
+ vst4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]!
+ vst4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]!
+ vst4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
+ vst4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
+ vst1.32 {${S4}[0]},[$tbl0]
+ vst1.32 {${S4}[1]},[$tbl1]
+
+.Lno_init_neon:
+ ret @ bx lr
+.size poly1305_init_neon,.-poly1305_init_neon
+
+.type poly1305_blocks_neon,%function
+.align 5
+poly1305_blocks_neon:
+.Lpoly1305_blocks_neon:
+ ldr ip,[$ctx,#36] @ is_base2_26
+
+ cmp $len,#64
+ blo .Lpoly1305_blocks
+
+ stmdb sp!,{r4-r7}
+ vstmdb sp!,{d8-d15} @ ABI specification says so
+
+ tst ip,ip @ is_base2_26?
+ bne .Lbase2_26_neon
+
+ stmdb sp!,{r1-r3,lr}
+ bl .Lpoly1305_init_neon
+
+ ldr r4,[$ctx,#0] @ load hash value base 2^32
+ ldr r5,[$ctx,#4]
+ ldr r6,[$ctx,#8]
+ ldr r7,[$ctx,#12]
+ ldr ip,[$ctx,#16]
+
+ and r2,r4,#0x03ffffff @ base 2^32 -> base 2^26
+ mov r3,r4,lsr#26
+ veor $D0#lo,$D0#lo,$D0#lo
+ mov r4,r5,lsr#20
+ orr r3,r3,r5,lsl#6
+ veor $D1#lo,$D1#lo,$D1#lo
+ mov r5,r6,lsr#14
+ orr r4,r4,r6,lsl#12
+ veor $D2#lo,$D2#lo,$D2#lo
+ mov r6,r7,lsr#8
+ orr r5,r5,r7,lsl#18
+ veor $D3#lo,$D3#lo,$D3#lo
+ and r3,r3,#0x03ffffff
+ orr r6,r6,ip,lsl#24
+ veor $D4#lo,$D4#lo,$D4#lo
+ and r4,r4,#0x03ffffff
+ mov r1,#1
+ and r5,r5,#0x03ffffff
+ str r1,[$ctx,#36] @ set is_base2_26
+
+ vmov.32 $D0#lo[0],r2
+ vmov.32 $D1#lo[0],r3
+ vmov.32 $D2#lo[0],r4
+ vmov.32 $D3#lo[0],r5
+ vmov.32 $D4#lo[0],r6
+ adr $zeros,.Lzeros
+
+ ldmia sp!,{r1-r3,lr}
+ b .Lhash_loaded
+
+.align 4
+.Lbase2_26_neon:
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ load hash value
+
+ veor $D0#lo,$D0#lo,$D0#lo
+ veor $D1#lo,$D1#lo,$D1#lo
+ veor $D2#lo,$D2#lo,$D2#lo
+ veor $D3#lo,$D3#lo,$D3#lo
+ veor $D4#lo,$D4#lo,$D4#lo
+ vld4.32 {$D0#lo[0],$D1#lo[0],$D2#lo[0],$D3#lo[0]},[$ctx]!
+ adr $zeros,.Lzeros
+ vld1.32 {$D4#lo[0]},[$ctx]
+ sub $ctx,$ctx,#16 @ rewind
+
+.Lhash_loaded:
+ add $in2,$inp,#32
+ mov $padbit,$padbit,lsl#24
+ tst $len,#31
+ beq .Leven
+
+ vld4.32 {$H0#lo[0],$H1#lo[0],$H2#lo[0],$H3#lo[0]},[$inp]!
+ vmov.32 $H4#lo[0],$padbit
+ sub $len,$len,#16
+ add $in2,$inp,#32
+
+# ifdef __ARMEB__
+ vrev32.8 $H0,$H0
+ vrev32.8 $H3,$H3
+ vrev32.8 $H1,$H1
+ vrev32.8 $H2,$H2
+# endif
+ vsri.u32 $H4#lo,$H3#lo,#8 @ base 2^32 -> base 2^26
+ vshl.u32 $H3#lo,$H3#lo,#18
+
+ vsri.u32 $H3#lo,$H2#lo,#14
+ vshl.u32 $H2#lo,$H2#lo,#12
+ vadd.i32 $H4#hi,$H4#lo,$D4#lo @ add hash value and move to #hi
+
+ vbic.i32 $H3#lo,#0xfc000000
+ vsri.u32 $H2#lo,$H1#lo,#20
+ vshl.u32 $H1#lo,$H1#lo,#6
+
+ vbic.i32 $H2#lo,#0xfc000000
+ vsri.u32 $H1#lo,$H0#lo,#26
+ vadd.i32 $H3#hi,$H3#lo,$D3#lo
+
+ vbic.i32 $H0#lo,#0xfc000000
+ vbic.i32 $H1#lo,#0xfc000000
+ vadd.i32 $H2#hi,$H2#lo,$D2#lo
+
+ vadd.i32 $H0#hi,$H0#lo,$D0#lo
+ vadd.i32 $H1#hi,$H1#lo,$D1#lo
+
+ mov $tbl1,$zeros
+ add $tbl0,$ctx,#48
+
+ cmp $len,$len
+ b .Long_tail
+
+.align 4
+.Leven:
+ subs $len,$len,#64
+ it lo
+ movlo $in2,$zeros
+
+ vmov.i32 $H4,#1<<24 @ padbit, yes, always
+ vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
+ add $inp,$inp,#64
+ vld4.32 {$H0#hi,$H1#hi,$H2#hi,$H3#hi},[$in2] @ inp[2:3] (or 0)
+ add $in2,$in2,#64
+ itt hi
+ addhi $tbl1,$ctx,#(48+1*9*4)
+ addhi $tbl0,$ctx,#(48+3*9*4)
+
+# ifdef __ARMEB__
+ vrev32.8 $H0,$H0
+ vrev32.8 $H3,$H3
+ vrev32.8 $H1,$H1
+ vrev32.8 $H2,$H2
+# endif
+ vsri.u32 $H4,$H3,#8 @ base 2^32 -> base 2^26
+ vshl.u32 $H3,$H3,#18
+
+ vsri.u32 $H3,$H2,#14
+ vshl.u32 $H2,$H2,#12
+
+ vbic.i32 $H3,#0xfc000000
+ vsri.u32 $H2,$H1,#20
+ vshl.u32 $H1,$H1,#6
+
+ vbic.i32 $H2,#0xfc000000
+ vsri.u32 $H1,$H0,#26
+
+ vbic.i32 $H0,#0xfc000000
+ vbic.i32 $H1,#0xfc000000
+
+ bls .Lskip_loop
+
+ vld4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]! @ load r^2
+ vld4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]! @ load r^4
+ vld4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
+ vld4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
+ b .Loop_neon
+
+.align 5
+.Loop_neon:
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2
+ @ ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^3+inp[7]*r
+ @ \___________________/
+ @ ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2+inp[8])*r^2
+ @ ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^4+inp[7]*r^2+inp[9])*r
+ @ \___________________/ \____________________/
+ @
+ @ Note that we start with inp[2:3]*r^2. This is because it
+ @ doesn't depend on reduction in previous iteration.
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
+ @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
+ @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
+ @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
+ @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ inp[2:3]*r^2
+
+ vadd.i32 $H2#lo,$H2#lo,$D2#lo @ accumulate inp[0:1]
+ vmull.u32 $D2,$H2#hi,${R0}[1]
+ vadd.i32 $H0#lo,$H0#lo,$D0#lo
+ vmull.u32 $D0,$H0#hi,${R0}[1]
+ vadd.i32 $H3#lo,$H3#lo,$D3#lo
+ vmull.u32 $D3,$H3#hi,${R0}[1]
+ vmlal.u32 $D2,$H1#hi,${R1}[1]
+ vadd.i32 $H1#lo,$H1#lo,$D1#lo
+ vmull.u32 $D1,$H1#hi,${R0}[1]
+
+ vadd.i32 $H4#lo,$H4#lo,$D4#lo
+ vmull.u32 $D4,$H4#hi,${R0}[1]
+ subs $len,$len,#64
+ vmlal.u32 $D0,$H4#hi,${S1}[1]
+ it lo
+ movlo $in2,$zeros
+ vmlal.u32 $D3,$H2#hi,${R1}[1]
+ vld1.32 ${S4}[1],[$tbl1,:32]
+ vmlal.u32 $D1,$H0#hi,${R1}[1]
+ vmlal.u32 $D4,$H3#hi,${R1}[1]
+
+ vmlal.u32 $D0,$H3#hi,${S2}[1]
+ vmlal.u32 $D3,$H1#hi,${R2}[1]
+ vmlal.u32 $D4,$H2#hi,${R2}[1]
+ vmlal.u32 $D1,$H4#hi,${S2}[1]
+ vmlal.u32 $D2,$H0#hi,${R2}[1]
+
+ vmlal.u32 $D3,$H0#hi,${R3}[1]
+ vmlal.u32 $D0,$H2#hi,${S3}[1]
+ vmlal.u32 $D4,$H1#hi,${R3}[1]
+ vmlal.u32 $D1,$H3#hi,${S3}[1]
+ vmlal.u32 $D2,$H4#hi,${S3}[1]
+
+ vmlal.u32 $D3,$H4#hi,${S4}[1]
+ vmlal.u32 $D0,$H1#hi,${S4}[1]
+ vmlal.u32 $D4,$H0#hi,${R4}[1]
+ vmlal.u32 $D1,$H2#hi,${S4}[1]
+ vmlal.u32 $D2,$H3#hi,${S4}[1]
+
+ vld4.32 {$H0#hi,$H1#hi,$H2#hi,$H3#hi},[$in2] @ inp[2:3] (or 0)
+ add $in2,$in2,#64
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ (hash+inp[0:1])*r^4 and accumulate
+
+ vmlal.u32 $D3,$H3#lo,${R0}[0]
+ vmlal.u32 $D0,$H0#lo,${R0}[0]
+ vmlal.u32 $D4,$H4#lo,${R0}[0]
+ vmlal.u32 $D1,$H1#lo,${R0}[0]
+ vmlal.u32 $D2,$H2#lo,${R0}[0]
+ vld1.32 ${S4}[0],[$tbl0,:32]
+
+ vmlal.u32 $D3,$H2#lo,${R1}[0]
+ vmlal.u32 $D0,$H4#lo,${S1}[0]
+ vmlal.u32 $D4,$H3#lo,${R1}[0]
+ vmlal.u32 $D1,$H0#lo,${R1}[0]
+ vmlal.u32 $D2,$H1#lo,${R1}[0]
+
+ vmlal.u32 $D3,$H1#lo,${R2}[0]
+ vmlal.u32 $D0,$H3#lo,${S2}[0]
+ vmlal.u32 $D4,$H2#lo,${R2}[0]
+ vmlal.u32 $D1,$H4#lo,${S2}[0]
+ vmlal.u32 $D2,$H0#lo,${R2}[0]
+
+ vmlal.u32 $D3,$H0#lo,${R3}[0]
+ vmlal.u32 $D0,$H2#lo,${S3}[0]
+ vmlal.u32 $D4,$H1#lo,${R3}[0]
+ vmlal.u32 $D1,$H3#lo,${S3}[0]
+ vmlal.u32 $D3,$H4#lo,${S4}[0]
+
+ vmlal.u32 $D2,$H4#lo,${S3}[0]
+ vmlal.u32 $D0,$H1#lo,${S4}[0]
+ vmlal.u32 $D4,$H0#lo,${R4}[0]
+ vmov.i32 $H4,#1<<24 @ padbit, yes, always
+ vmlal.u32 $D1,$H2#lo,${S4}[0]
+ vmlal.u32 $D2,$H3#lo,${S4}[0]
+
+ vld4.32 {$H0#lo,$H1#lo,$H2#lo,$H3#lo},[$inp] @ inp[0:1]
+ add $inp,$inp,#64
+# ifdef __ARMEB__
+ vrev32.8 $H0,$H0
+ vrev32.8 $H1,$H1
+ vrev32.8 $H2,$H2
+ vrev32.8 $H3,$H3
+# endif
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ lazy reduction interleaved with base 2^32 -> base 2^26 of
+ @ inp[0:3] previously loaded to $H0-$H3 and smashed to $H0-$H4.
+
+ vshr.u64 $T0,$D3,#26
+ vmovn.i64 $D3#lo,$D3
+ vshr.u64 $T1,$D0,#26
+ vmovn.i64 $D0#lo,$D0
+ vadd.i64 $D4,$D4,$T0 @ h3 -> h4
+ vbic.i32 $D3#lo,#0xfc000000
+ vsri.u32 $H4,$H3,#8 @ base 2^32 -> base 2^26
+ vadd.i64 $D1,$D1,$T1 @ h0 -> h1
+ vshl.u32 $H3,$H3,#18
+ vbic.i32 $D0#lo,#0xfc000000
+
+ vshrn.u64 $T0#lo,$D4,#26
+ vmovn.i64 $D4#lo,$D4
+ vshr.u64 $T1,$D1,#26
+ vmovn.i64 $D1#lo,$D1
+ vadd.i64 $D2,$D2,$T1 @ h1 -> h2
+ vsri.u32 $H3,$H2,#14
+ vbic.i32 $D4#lo,#0xfc000000
+ vshl.u32 $H2,$H2,#12
+ vbic.i32 $D1#lo,#0xfc000000
+
+ vadd.i32 $D0#lo,$D0#lo,$T0#lo
+ vshl.u32 $T0#lo,$T0#lo,#2
+ vbic.i32 $H3,#0xfc000000
+ vshrn.u64 $T1#lo,$D2,#26
+ vmovn.i64 $D2#lo,$D2
+ vaddl.u32 $D0,$D0#lo,$T0#lo @ h4 -> h0 [widen for a sec]
+ vsri.u32 $H2,$H1,#20
+ vadd.i32 $D3#lo,$D3#lo,$T1#lo @ h2 -> h3
+ vshl.u32 $H1,$H1,#6
+ vbic.i32 $D2#lo,#0xfc000000
+ vbic.i32 $H2,#0xfc000000
+
+ vshrn.u64 $T0#lo,$D0,#26 @ re-narrow
+ vmovn.i64 $D0#lo,$D0
+ vsri.u32 $H1,$H0,#26
+ vbic.i32 $H0,#0xfc000000
+ vshr.u32 $T1#lo,$D3#lo,#26
+ vbic.i32 $D3#lo,#0xfc000000
+ vbic.i32 $D0#lo,#0xfc000000
+ vadd.i32 $D1#lo,$D1#lo,$T0#lo @ h0 -> h1
+ vadd.i32 $D4#lo,$D4#lo,$T1#lo @ h3 -> h4
+ vbic.i32 $H1,#0xfc000000
+
+ bhi .Loop_neon
+
+.Lskip_loop:
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ multiply (inp[0:1]+hash) or inp[2:3] by r^2:r^1
+
+ add $tbl1,$ctx,#(48+0*9*4)
+ add $tbl0,$ctx,#(48+1*9*4)
+ adds $len,$len,#32
+ it ne
+ movne $len,#0
+ bne .Long_tail
+
+ vadd.i32 $H2#hi,$H2#lo,$D2#lo @ add hash value and move to #hi
+ vadd.i32 $H0#hi,$H0#lo,$D0#lo
+ vadd.i32 $H3#hi,$H3#lo,$D3#lo
+ vadd.i32 $H1#hi,$H1#lo,$D1#lo
+ vadd.i32 $H4#hi,$H4#lo,$D4#lo
+
+.Long_tail:
+ vld4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]! @ load r^1
+ vld4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]! @ load r^2
+
+ vadd.i32 $H2#lo,$H2#lo,$D2#lo @ can be redundant
+ vmull.u32 $D2,$H2#hi,$R0
+ vadd.i32 $H0#lo,$H0#lo,$D0#lo
+ vmull.u32 $D0,$H0#hi,$R0
+ vadd.i32 $H3#lo,$H3#lo,$D3#lo
+ vmull.u32 $D3,$H3#hi,$R0
+ vadd.i32 $H1#lo,$H1#lo,$D1#lo
+ vmull.u32 $D1,$H1#hi,$R0
+ vadd.i32 $H4#lo,$H4#lo,$D4#lo
+ vmull.u32 $D4,$H4#hi,$R0
+
+ vmlal.u32 $D0,$H4#hi,$S1
+ vld4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
+ vmlal.u32 $D3,$H2#hi,$R1
+ vld4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
+ vmlal.u32 $D1,$H0#hi,$R1
+ vmlal.u32 $D4,$H3#hi,$R1
+ vmlal.u32 $D2,$H1#hi,$R1
+
+ vmlal.u32 $D3,$H1#hi,$R2
+ vld1.32 ${S4}[1],[$tbl1,:32]
+ vmlal.u32 $D0,$H3#hi,$S2
+ vld1.32 ${S4}[0],[$tbl0,:32]
+ vmlal.u32 $D4,$H2#hi,$R2
+ vmlal.u32 $D1,$H4#hi,$S2
+ vmlal.u32 $D2,$H0#hi,$R2
+
+ vmlal.u32 $D3,$H0#hi,$R3
+ it ne
+ addne $tbl1,$ctx,#(48+2*9*4)
+ vmlal.u32 $D0,$H2#hi,$S3
+ it ne
+ addne $tbl0,$ctx,#(48+3*9*4)
+ vmlal.u32 $D4,$H1#hi,$R3
+ vmlal.u32 $D1,$H3#hi,$S3
+ vmlal.u32 $D2,$H4#hi,$S3
+
+ vmlal.u32 $D3,$H4#hi,$S4
+ vorn $MASK,$MASK,$MASK @ all-ones, can be redundant
+ vmlal.u32 $D0,$H1#hi,$S4
+ vshr.u64 $MASK,$MASK,#38
+ vmlal.u32 $D4,$H0#hi,$R4
+ vmlal.u32 $D1,$H2#hi,$S4
+ vmlal.u32 $D2,$H3#hi,$S4
+
+ beq .Lshort_tail
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ (hash+inp[0:1])*r^4:r^3 and accumulate
+
+ vld4.32 {${R0}[1],${R1}[1],${S1}[1],${R2}[1]},[$tbl1]! @ load r^3
+ vld4.32 {${R0}[0],${R1}[0],${S1}[0],${R2}[0]},[$tbl0]! @ load r^4
+
+ vmlal.u32 $D2,$H2#lo,$R0
+ vmlal.u32 $D0,$H0#lo,$R0
+ vmlal.u32 $D3,$H3#lo,$R0
+ vmlal.u32 $D1,$H1#lo,$R0
+ vmlal.u32 $D4,$H4#lo,$R0
+
+ vmlal.u32 $D0,$H4#lo,$S1
+ vld4.32 {${S2}[1],${R3}[1],${S3}[1],${R4}[1]},[$tbl1]!
+ vmlal.u32 $D3,$H2#lo,$R1
+ vld4.32 {${S2}[0],${R3}[0],${S3}[0],${R4}[0]},[$tbl0]!
+ vmlal.u32 $D1,$H0#lo,$R1
+ vmlal.u32 $D4,$H3#lo,$R1
+ vmlal.u32 $D2,$H1#lo,$R1
+
+ vmlal.u32 $D3,$H1#lo,$R2
+ vld1.32 ${S4}[1],[$tbl1,:32]
+ vmlal.u32 $D0,$H3#lo,$S2
+ vld1.32 ${S4}[0],[$tbl0,:32]
+ vmlal.u32 $D4,$H2#lo,$R2
+ vmlal.u32 $D1,$H4#lo,$S2
+ vmlal.u32 $D2,$H0#lo,$R2
+
+ vmlal.u32 $D3,$H0#lo,$R3
+ vmlal.u32 $D0,$H2#lo,$S3
+ vmlal.u32 $D4,$H1#lo,$R3
+ vmlal.u32 $D1,$H3#lo,$S3
+ vmlal.u32 $D2,$H4#lo,$S3
+
+ vmlal.u32 $D3,$H4#lo,$S4
+ vorn $MASK,$MASK,$MASK @ all-ones
+ vmlal.u32 $D0,$H1#lo,$S4
+ vshr.u64 $MASK,$MASK,#38
+ vmlal.u32 $D4,$H0#lo,$R4
+ vmlal.u32 $D1,$H2#lo,$S4
+ vmlal.u32 $D2,$H3#lo,$S4
+
+.Lshort_tail:
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ horizontal addition
+
+ vadd.i64 $D3#lo,$D3#lo,$D3#hi
+ vadd.i64 $D0#lo,$D0#lo,$D0#hi
+ vadd.i64 $D4#lo,$D4#lo,$D4#hi
+ vadd.i64 $D1#lo,$D1#lo,$D1#hi
+ vadd.i64 $D2#lo,$D2#lo,$D2#hi
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ lazy reduction, but without narrowing
+
+ vshr.u64 $T0,$D3,#26
+ vand.i64 $D3,$D3,$MASK
+ vshr.u64 $T1,$D0,#26
+ vand.i64 $D0,$D0,$MASK
+ vadd.i64 $D4,$D4,$T0 @ h3 -> h4
+ vadd.i64 $D1,$D1,$T1 @ h0 -> h1
+
+ vshr.u64 $T0,$D4,#26
+ vand.i64 $D4,$D4,$MASK
+ vshr.u64 $T1,$D1,#26
+ vand.i64 $D1,$D1,$MASK
+ vadd.i64 $D2,$D2,$T1 @ h1 -> h2
+
+ vadd.i64 $D0,$D0,$T0
+ vshl.u64 $T0,$T0,#2
+ vshr.u64 $T1,$D2,#26
+ vand.i64 $D2,$D2,$MASK
+ vadd.i64 $D0,$D0,$T0 @ h4 -> h0
+ vadd.i64 $D3,$D3,$T1 @ h2 -> h3
+
+ vshr.u64 $T0,$D0,#26
+ vand.i64 $D0,$D0,$MASK
+ vshr.u64 $T1,$D3,#26
+ vand.i64 $D3,$D3,$MASK
+ vadd.i64 $D1,$D1,$T0 @ h0 -> h1
+ vadd.i64 $D4,$D4,$T1 @ h3 -> h4
+
+ cmp $len,#0
+ bne .Leven
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ store hash value
+
+ vst4.32 {$D0#lo[0],$D1#lo[0],$D2#lo[0],$D3#lo[0]},[$ctx]!
+ vst1.32 {$D4#lo[0]},[$ctx]
+
+ vldmia sp!,{d8-d15} @ epilogue
+ ldmia sp!,{r4-r7}
+ ret @ bx lr
+.size poly1305_blocks_neon,.-poly1305_blocks_neon
+
+.align 5
+.Lzeros:
+.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+#ifndef __KERNEL__
+.LOPENSSL_armcap:
+# ifdef _WIN32
+.word OPENSSL_armcap_P
+# else
+.word OPENSSL_armcap_P-.Lpoly1305_init
+# endif
+.comm OPENSSL_armcap_P,4,4
+.hidden OPENSSL_armcap_P
+#endif
+#endif
+___
+} }
+$code.=<<___;
+.asciz "Poly1305 for ARMv4/NEON, CRYPTOGAMS by \@dot-asm"
+.align 2
+___
+
+foreach (split("\n",$code)) {
+ s/\`([^\`]*)\`/eval $1/geo;
+
+ s/\bq([0-9]+)#(lo|hi)/sprintf "d%d",2*$1+($2 eq "hi")/geo or
+ s/\bret\b/bx lr/go or
+ s/\bbx\s+lr\b/.word\t0xe12fff1e/go; # make it possible to compile with -march=armv4
+
+ print $_,"\n";
+}
+close STDOUT; # enforce flush
diff --git a/arch/arm/crypto/poly1305-core.S_shipped b/arch/arm/crypto/poly1305-core.S_shipped
new file mode 100644
index 0000000..37b71d9
--- /dev/null
+++ b/arch/arm/crypto/poly1305-core.S_shipped
@@ -0,0 +1,1158 @@
+#ifndef __KERNEL__
+# include "arm_arch.h"
+#else
+# define __ARM_ARCH__ __LINUX_ARM_ARCH__
+# define __ARM_MAX_ARCH__ __LINUX_ARM_ARCH__
+# define poly1305_init poly1305_init_arm
+# define poly1305_blocks poly1305_blocks_arm
+# define poly1305_emit poly1305_emit_arm
+.globl poly1305_blocks_neon
+#endif
+
+#if defined(__thumb2__)
+.syntax unified
+.thumb
+#else
+.code 32
+#endif
+
+.text
+
+.globl poly1305_emit
+.globl poly1305_blocks
+.globl poly1305_init
+.type poly1305_init,%function
+.align 5
+poly1305_init:
+.Lpoly1305_init:
+ stmdb sp!,{r4-r11}
+
+ eor r3,r3,r3
+ cmp r1,#0
+ str r3,[r0,#0] @ zero hash value
+ str r3,[r0,#4]
+ str r3,[r0,#8]
+ str r3,[r0,#12]
+ str r3,[r0,#16]
+ str r3,[r0,#36] @ clear is_base2_26
+ add r0,r0,#20
+
+#ifdef __thumb2__
+ it eq
+#endif
+ moveq r0,#0
+ beq .Lno_key
+
+#if __ARM_MAX_ARCH__>=7
+ mov r3,#-1
+ str r3,[r0,#28] @ impossible key power value
+# ifndef __KERNEL__
+ adr r11,.Lpoly1305_init
+ ldr r12,.LOPENSSL_armcap
+# endif
+#endif
+ ldrb r4,[r1,#0]
+ mov r10,#0x0fffffff
+ ldrb r5,[r1,#1]
+ and r3,r10,#-4 @ 0x0ffffffc
+ ldrb r6,[r1,#2]
+ ldrb r7,[r1,#3]
+ orr r4,r4,r5,lsl#8
+ ldrb r5,[r1,#4]
+ orr r4,r4,r6,lsl#16
+ ldrb r6,[r1,#5]
+ orr r4,r4,r7,lsl#24
+ ldrb r7,[r1,#6]
+ and r4,r4,r10
+
+#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
+# if !defined(_WIN32)
+ ldr r12,[r11,r12] @ OPENSSL_armcap_P
+# endif
+# if defined(__APPLE__) || defined(_WIN32)
+ ldr r12,[r12]
+# endif
+#endif
+ ldrb r8,[r1,#7]
+ orr r5,r5,r6,lsl#8
+ ldrb r6,[r1,#8]
+ orr r5,r5,r7,lsl#16
+ ldrb r7,[r1,#9]
+ orr r5,r5,r8,lsl#24
+ ldrb r8,[r1,#10]
+ and r5,r5,r3
+
+#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
+ tst r12,#ARMV7_NEON @ check for NEON
+# ifdef __thumb2__
+ adr r9,.Lpoly1305_blocks_neon
+ adr r11,.Lpoly1305_blocks
+ it ne
+ movne r11,r9
+ adr r12,.Lpoly1305_emit
+ orr r11,r11,#1 @ thumb-ify addresses
+ orr r12,r12,#1
+# else
+ add r12,r11,#(.Lpoly1305_emit-.Lpoly1305_init)
+ ite eq
+ addeq r11,r11,#(.Lpoly1305_blocks-.Lpoly1305_init)
+ addne r11,r11,#(.Lpoly1305_blocks_neon-.Lpoly1305_init)
+# endif
+#endif
+ ldrb r9,[r1,#11]
+ orr r6,r6,r7,lsl#8
+ ldrb r7,[r1,#12]
+ orr r6,r6,r8,lsl#16
+ ldrb r8,[r1,#13]
+ orr r6,r6,r9,lsl#24
+ ldrb r9,[r1,#14]
+ and r6,r6,r3
+
+ ldrb r10,[r1,#15]
+ orr r7,r7,r8,lsl#8
+ str r4,[r0,#0]
+ orr r7,r7,r9,lsl#16
+ str r5,[r0,#4]
+ orr r7,r7,r10,lsl#24
+ str r6,[r0,#8]
+ and r7,r7,r3
+ str r7,[r0,#12]
+#if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
+ stmia r2,{r11,r12} @ fill functions table
+ mov r0,#1
+#else
+ mov r0,#0
+#endif
+.Lno_key:
+ ldmia sp!,{r4-r11}
+#if __ARM_ARCH__>=5
+ bx lr @ bx lr
+#else
+ tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ .word 0xe12fff1e @ interoperable with Thumb ISA:-)
+#endif
+.size poly1305_init,.-poly1305_init
+.type poly1305_blocks,%function
+.align 5
+poly1305_blocks:
+.Lpoly1305_blocks:
+ stmdb sp!,{r3-r11,lr}
+
+ ands r2,r2,#-16
+ beq .Lno_data
+
+ add r2,r2,r1 @ end pointer
+ sub sp,sp,#32
+
+#if __ARM_ARCH__<7
+ ldmia r0,{r4-r12} @ load context
+ add r0,r0,#20
+ str r2,[sp,#16] @ offload stuff
+ str r0,[sp,#12]
+#else
+ ldr lr,[r0,#36] @ is_base2_26
+ ldmia r0!,{r4-r8} @ load hash value
+ str r2,[sp,#16] @ offload stuff
+ str r0,[sp,#12]
+
+ adds r9,r4,r5,lsl#26 @ base 2^26 -> base 2^32
+ mov r10,r5,lsr#6
+ adcs r10,r10,r6,lsl#20
+ mov r11,r6,lsr#12
+ adcs r11,r11,r7,lsl#14
+ mov r12,r7,lsr#18
+ adcs r12,r12,r8,lsl#8
+ mov r2,#0
+ teq lr,#0
+ str r2,[r0,#16] @ clear is_base2_26
+ adc r2,r2,r8,lsr#24
+
+ itttt ne
+ movne r4,r9 @ choose between radixes
+ movne r5,r10
+ movne r6,r11
+ movne r7,r12
+ ldmia r0,{r9-r12} @ load key
+ it ne
+ movne r8,r2
+#endif
+
+ mov lr,r1
+ cmp r3,#0
+ str r10,[sp,#20]
+ str r11,[sp,#24]
+ str r12,[sp,#28]
+ b .Loop
+
+.align 4
+.Loop:
+#if __ARM_ARCH__<7
+ ldrb r0,[lr],#16 @ load input
+# ifdef __thumb2__
+ it hi
+# endif
+ addhi r8,r8,#1 @ 1<<128
+ ldrb r1,[lr,#-15]
+ ldrb r2,[lr,#-14]
+ ldrb r3,[lr,#-13]
+ orr r1,r0,r1,lsl#8
+ ldrb r0,[lr,#-12]
+ orr r2,r1,r2,lsl#16
+ ldrb r1,[lr,#-11]
+ orr r3,r2,r3,lsl#24
+ ldrb r2,[lr,#-10]
+ adds r4,r4,r3 @ accumulate input
+
+ ldrb r3,[lr,#-9]
+ orr r1,r0,r1,lsl#8
+ ldrb r0,[lr,#-8]
+ orr r2,r1,r2,lsl#16
+ ldrb r1,[lr,#-7]
+ orr r3,r2,r3,lsl#24
+ ldrb r2,[lr,#-6]
+ adcs r5,r5,r3
+
+ ldrb r3,[lr,#-5]
+ orr r1,r0,r1,lsl#8
+ ldrb r0,[lr,#-4]
+ orr r2,r1,r2,lsl#16
+ ldrb r1,[lr,#-3]
+ orr r3,r2,r3,lsl#24
+ ldrb r2,[lr,#-2]
+ adcs r6,r6,r3
+
+ ldrb r3,[lr,#-1]
+ orr r1,r0,r1,lsl#8
+ str lr,[sp,#8] @ offload input pointer
+ orr r2,r1,r2,lsl#16
+ add r10,r10,r10,lsr#2
+ orr r3,r2,r3,lsl#24
+#else
+ ldr r0,[lr],#16 @ load input
+ it hi
+ addhi r8,r8,#1 @ padbit
+ ldr r1,[lr,#-12]
+ ldr r2,[lr,#-8]
+ ldr r3,[lr,#-4]
+# ifdef __ARMEB__
+ rev r0,r0
+ rev r1,r1
+ rev r2,r2
+ rev r3,r3
+# endif
+ adds r4,r4,r0 @ accumulate input
+ str lr,[sp,#8] @ offload input pointer
+ adcs r5,r5,r1
+ add r10,r10,r10,lsr#2
+ adcs r6,r6,r2
+#endif
+ add r11,r11,r11,lsr#2
+ adcs r7,r7,r3
+ add r12,r12,r12,lsr#2
+
+ umull r2,r3,r5,r9
+ adc r8,r8,#0
+ umull r0,r1,r4,r9
+ umlal r2,r3,r8,r10
+ umlal r0,r1,r7,r10
+ ldr r10,[sp,#20] @ reload r10
+ umlal r2,r3,r6,r12
+ umlal r0,r1,r5,r12
+ umlal r2,r3,r7,r11
+ umlal r0,r1,r6,r11
+ umlal r2,r3,r4,r10
+ str r0,[sp,#0] @ future r4
+ mul r0,r11,r8
+ ldr r11,[sp,#24] @ reload r11
+ adds r2,r2,r1 @ d1+=d0>>32
+ eor r1,r1,r1
+ adc lr,r3,#0 @ future r6
+ str r2,[sp,#4] @ future r5
+
+ mul r2,r12,r8
+ eor r3,r3,r3
+ umlal r0,r1,r7,r12
+ ldr r12,[sp,#28] @ reload r12
+ umlal r2,r3,r7,r9
+ umlal r0,r1,r6,r9
+ umlal r2,r3,r6,r10
+ umlal r0,r1,r5,r10
+ umlal r2,r3,r5,r11
+ umlal r0,r1,r4,r11
+ umlal r2,r3,r4,r12
+ ldr r4,[sp,#0]
+ mul r8,r9,r8
+ ldr r5,[sp,#4]
+
+ adds r6,lr,r0 @ d2+=d1>>32
+ ldr lr,[sp,#8] @ reload input pointer
+ adc r1,r1,#0
+ adds r7,r2,r1 @ d3+=d2>>32
+ ldr r0,[sp,#16] @ reload end pointer
+ adc r3,r3,#0
+ add r8,r8,r3 @ h4+=d3>>32
+
+ and r1,r8,#-4
+ and r8,r8,#3
+ add r1,r1,r1,lsr#2 @ *=5
+ adds r4,r4,r1
+ adcs r5,r5,#0
+ adcs r6,r6,#0
+ adcs r7,r7,#0
+ adc r8,r8,#0
+
+ cmp r0,lr @ done yet?
+ bhi .Loop
+
+ ldr r0,[sp,#12]
+ add sp,sp,#32
+ stmdb r0,{r4-r8} @ store the result
+
+.Lno_data:
+#if __ARM_ARCH__>=5
+ ldmia sp!,{r3-r11,pc}
+#else
+ ldmia sp!,{r3-r11,lr}
+ tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ .word 0xe12fff1e @ interoperable with Thumb ISA:-)
+#endif
+.size poly1305_blocks,.-poly1305_blocks
+.type poly1305_emit,%function
+.align 5
+poly1305_emit:
+.Lpoly1305_emit:
+ stmdb sp!,{r4-r11}
+
+ ldmia r0,{r3-r7}
+
+#if __ARM_ARCH__>=7
+ ldr ip,[r0,#36] @ is_base2_26
+
+ adds r8,r3,r4,lsl#26 @ base 2^26 -> base 2^32
+ mov r9,r4,lsr#6
+ adcs r9,r9,r5,lsl#20
+ mov r10,r5,lsr#12
+ adcs r10,r10,r6,lsl#14
+ mov r11,r6,lsr#18
+ adcs r11,r11,r7,lsl#8
+ mov r0,#0
+ adc r0,r0,r7,lsr#24
+
+ tst ip,ip
+ itttt ne
+ movne r3,r8
+ movne r4,r9
+ movne r5,r10
+ movne r6,r11
+ it ne
+ movne r7,r0
+#endif
+
+ adds r8,r3,#5 @ compare to modulus
+ adcs r9,r4,#0
+ adcs r10,r5,#0
+ adcs r11,r6,#0
+ adc r0,r7,#0
+ tst r0,#4 @ did it carry/borrow?
+
+#ifdef __thumb2__
+ it ne
+#endif
+ movne r3,r8
+ ldr r8,[r2,#0]
+#ifdef __thumb2__
+ it ne
+#endif
+ movne r4,r9
+ ldr r9,[r2,#4]
+#ifdef __thumb2__
+ it ne
+#endif
+ movne r5,r10
+ ldr r10,[r2,#8]
+#ifdef __thumb2__
+ it ne
+#endif
+ movne r6,r11
+ ldr r11,[r2,#12]
+
+ adds r3,r3,r8
+ adcs r4,r4,r9
+ adcs r5,r5,r10
+ adc r6,r6,r11
+
+#if __ARM_ARCH__>=7
+# ifdef __ARMEB__
+ rev r3,r3
+ rev r4,r4
+ rev r5,r5
+ rev r6,r6
+# endif
+ str r3,[r1,#0]
+ str r4,[r1,#4]
+ str r5,[r1,#8]
+ str r6,[r1,#12]
+#else
+ strb r3,[r1,#0]
+ mov r3,r3,lsr#8
+ strb r4,[r1,#4]
+ mov r4,r4,lsr#8
+ strb r5,[r1,#8]
+ mov r5,r5,lsr#8
+ strb r6,[r1,#12]
+ mov r6,r6,lsr#8
+
+ strb r3,[r1,#1]
+ mov r3,r3,lsr#8
+ strb r4,[r1,#5]
+ mov r4,r4,lsr#8
+ strb r5,[r1,#9]
+ mov r5,r5,lsr#8
+ strb r6,[r1,#13]
+ mov r6,r6,lsr#8
+
+ strb r3,[r1,#2]
+ mov r3,r3,lsr#8
+ strb r4,[r1,#6]
+ mov r4,r4,lsr#8
+ strb r5,[r1,#10]
+ mov r5,r5,lsr#8
+ strb r6,[r1,#14]
+ mov r6,r6,lsr#8
+
+ strb r3,[r1,#3]
+ strb r4,[r1,#7]
+ strb r5,[r1,#11]
+ strb r6,[r1,#15]
+#endif
+ ldmia sp!,{r4-r11}
+#if __ARM_ARCH__>=5
+ bx lr @ bx lr
+#else
+ tst lr,#1
+ moveq pc,lr @ be binary compatible with V4, yet
+ .word 0xe12fff1e @ interoperable with Thumb ISA:-)
+#endif
+.size poly1305_emit,.-poly1305_emit
+#if __ARM_MAX_ARCH__>=7
+.fpu neon
+
+.type poly1305_init_neon,%function
+.align 5
+poly1305_init_neon:
+.Lpoly1305_init_neon:
+ ldr r3,[r0,#48] @ first table element
+ cmp r3,#-1 @ is value impossible?
+ bne .Lno_init_neon
+
+ ldr r4,[r0,#20] @ load key base 2^32
+ ldr r5,[r0,#24]
+ ldr r6,[r0,#28]
+ ldr r7,[r0,#32]
+
+ and r2,r4,#0x03ffffff @ base 2^32 -> base 2^26
+ mov r3,r4,lsr#26
+ mov r4,r5,lsr#20
+ orr r3,r3,r5,lsl#6
+ mov r5,r6,lsr#14
+ orr r4,r4,r6,lsl#12
+ mov r6,r7,lsr#8
+ orr r5,r5,r7,lsl#18
+ and r3,r3,#0x03ffffff
+ and r4,r4,#0x03ffffff
+ and r5,r5,#0x03ffffff
+
+ vdup.32 d0,r2 @ r^1 in both lanes
+ add r2,r3,r3,lsl#2 @ *5
+ vdup.32 d1,r3
+ add r3,r4,r4,lsl#2
+ vdup.32 d2,r2
+ vdup.32 d3,r4
+ add r4,r5,r5,lsl#2
+ vdup.32 d4,r3
+ vdup.32 d5,r5
+ add r5,r6,r6,lsl#2
+ vdup.32 d6,r4
+ vdup.32 d7,r6
+ vdup.32 d8,r5
+
+ mov r5,#2 @ counter
+
+.Lsquare_neon:
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
+ @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
+ @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
+ @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
+ @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
+
+ vmull.u32 q5,d0,d0[1]
+ vmull.u32 q6,d1,d0[1]
+ vmull.u32 q7,d3,d0[1]
+ vmull.u32 q8,d5,d0[1]
+ vmull.u32 q9,d7,d0[1]
+
+ vmlal.u32 q5,d7,d2[1]
+ vmlal.u32 q6,d0,d1[1]
+ vmlal.u32 q7,d1,d1[1]
+ vmlal.u32 q8,d3,d1[1]
+ vmlal.u32 q9,d5,d1[1]
+
+ vmlal.u32 q5,d5,d4[1]
+ vmlal.u32 q6,d7,d4[1]
+ vmlal.u32 q8,d1,d3[1]
+ vmlal.u32 q7,d0,d3[1]
+ vmlal.u32 q9,d3,d3[1]
+
+ vmlal.u32 q5,d3,d6[1]
+ vmlal.u32 q8,d0,d5[1]
+ vmlal.u32 q6,d5,d6[1]
+ vmlal.u32 q7,d7,d6[1]
+ vmlal.u32 q9,d1,d5[1]
+
+ vmlal.u32 q8,d7,d8[1]
+ vmlal.u32 q5,d1,d8[1]
+ vmlal.u32 q6,d3,d8[1]
+ vmlal.u32 q7,d5,d8[1]
+ vmlal.u32 q9,d0,d7[1]
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ lazy reduction as discussed in "NEON crypto" by D.J. Bernstein
+ @ and P. Schwabe
+ @
+ @ H0>>+H1>>+H2>>+H3>>+H4
+ @ H3>>+H4>>*5+H0>>+H1
+ @
+ @ Trivia.
+ @
+ @ Result of multiplication of n-bit number by m-bit number is
+ @ n+m bits wide. However! Even though 2^n is a n+1-bit number,
+ @ m-bit number multiplied by 2^n is still n+m bits wide.
+ @
+ @ Sum of two n-bit numbers is n+1 bits wide, sum of three - n+2,
+ @ and so is sum of four. Sum of 2^m n-m-bit numbers and n-bit
+ @ one is n+1 bits wide.
+ @
+ @ >>+ denotes Hnext += Hn>>26, Hn &= 0x3ffffff. This means that
+ @ H0, H2, H3 are guaranteed to be 26 bits wide, while H1 and H4
+ @ can be 27. However! In cases when their width exceeds 26 bits
+ @ they are limited by 2^26+2^6. This in turn means that *sum*
+ @ of the products with these values can still be viewed as sum
+ @ of 52-bit numbers as long as the amount of addends is not a
+ @ power of 2. For example,
+ @
+ @ H4 = H4*R0 + H3*R1 + H2*R2 + H1*R3 + H0 * R4,
+ @
+ @ which can't be larger than 5 * (2^26 + 2^6) * (2^26 + 2^6), or
+ @ 5 * (2^52 + 2*2^32 + 2^12), which in turn is smaller than
+ @ 8 * (2^52) or 2^55. However, the value is then multiplied by
+ @ by 5, so we should be looking at 5 * 5 * (2^52 + 2^33 + 2^12),
+ @ which is less than 32 * (2^52) or 2^57. And when processing
+ @ data we are looking at triple as many addends...
+ @
+ @ In key setup procedure pre-reduced H0 is limited by 5*4+1 and
+ @ 5*H4 - by 5*5 52-bit addends, or 57 bits. But when hashing the
+ @ input H0 is limited by (5*4+1)*3 addends, or 58 bits, while
+ @ 5*H4 by 5*5*3, or 59[!] bits. How is this relevant? vmlal.u32
+ @ instruction accepts 2x32-bit input and writes 2x64-bit result.
+ @ This means that result of reduction have to be compressed upon
+ @ loop wrap-around. This can be done in the process of reduction
+ @ to minimize amount of instructions [as well as amount of
+ @ 128-bit instructions, which benefits low-end processors], but
+ @ one has to watch for H2 (which is narrower than H0) and 5*H4
+ @ not being wider than 58 bits, so that result of right shift
+ @ by 26 bits fits in 32 bits. This is also useful on x86,
+ @ because it allows to use paddd in place for paddq, which
+ @ benefits Atom, where paddq is ridiculously slow.
+
+ vshr.u64 q15,q8,#26
+ vmovn.i64 d16,q8
+ vshr.u64 q4,q5,#26
+ vmovn.i64 d10,q5
+ vadd.i64 q9,q9,q15 @ h3 -> h4
+ vbic.i32 d16,#0xfc000000 @ &=0x03ffffff
+ vadd.i64 q6,q6,q4 @ h0 -> h1
+ vbic.i32 d10,#0xfc000000
+
+ vshrn.u64 d30,q9,#26
+ vmovn.i64 d18,q9
+ vshr.u64 q4,q6,#26
+ vmovn.i64 d12,q6
+ vadd.i64 q7,q7,q4 @ h1 -> h2
+ vbic.i32 d18,#0xfc000000
+ vbic.i32 d12,#0xfc000000
+
+ vadd.i32 d10,d10,d30
+ vshl.u32 d30,d30,#2
+ vshrn.u64 d8,q7,#26
+ vmovn.i64 d14,q7
+ vadd.i32 d10,d10,d30 @ h4 -> h0
+ vadd.i32 d16,d16,d8 @ h2 -> h3
+ vbic.i32 d14,#0xfc000000
+
+ vshr.u32 d30,d10,#26
+ vbic.i32 d10,#0xfc000000
+ vshr.u32 d8,d16,#26
+ vbic.i32 d16,#0xfc000000
+ vadd.i32 d12,d12,d30 @ h0 -> h1
+ vadd.i32 d18,d18,d8 @ h3 -> h4
+
+ subs r5,r5,#1
+ beq .Lsquare_break_neon
+
+ add r6,r0,#(48+0*9*4)
+ add r7,r0,#(48+1*9*4)
+
+ vtrn.32 d0,d10 @ r^2:r^1
+ vtrn.32 d3,d14
+ vtrn.32 d5,d16
+ vtrn.32 d1,d12
+ vtrn.32 d7,d18
+
+ vshl.u32 d4,d3,#2 @ *5
+ vshl.u32 d6,d5,#2
+ vshl.u32 d2,d1,#2
+ vshl.u32 d8,d7,#2
+ vadd.i32 d4,d4,d3
+ vadd.i32 d2,d2,d1
+ vadd.i32 d6,d6,d5
+ vadd.i32 d8,d8,d7
+
+ vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r6]!
+ vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r7]!
+ vst4.32 {d4[0],d5[0],d6[0],d7[0]},[r6]!
+ vst4.32 {d4[1],d5[1],d6[1],d7[1]},[r7]!
+ vst1.32 {d8[0]},[r6,:32]
+ vst1.32 {d8[1]},[r7,:32]
+
+ b .Lsquare_neon
+
+.align 4
+.Lsquare_break_neon:
+ add r6,r0,#(48+2*4*9)
+ add r7,r0,#(48+3*4*9)
+
+ vmov d0,d10 @ r^4:r^3
+ vshl.u32 d2,d12,#2 @ *5
+ vmov d1,d12
+ vshl.u32 d4,d14,#2
+ vmov d3,d14
+ vshl.u32 d6,d16,#2
+ vmov d5,d16
+ vshl.u32 d8,d18,#2
+ vmov d7,d18
+ vadd.i32 d2,d2,d12
+ vadd.i32 d4,d4,d14
+ vadd.i32 d6,d6,d16
+ vadd.i32 d8,d8,d18
+
+ vst4.32 {d0[0],d1[0],d2[0],d3[0]},[r6]!
+ vst4.32 {d0[1],d1[1],d2[1],d3[1]},[r7]!
+ vst4.32 {d4[0],d5[0],d6[0],d7[0]},[r6]!
+ vst4.32 {d4[1],d5[1],d6[1],d7[1]},[r7]!
+ vst1.32 {d8[0]},[r6]
+ vst1.32 {d8[1]},[r7]
+
+.Lno_init_neon:
+ bx lr @ bx lr
+.size poly1305_init_neon,.-poly1305_init_neon
+
+.type poly1305_blocks_neon,%function
+.align 5
+poly1305_blocks_neon:
+.Lpoly1305_blocks_neon:
+ ldr ip,[r0,#36] @ is_base2_26
+
+ cmp r2,#64
+ blo .Lpoly1305_blocks
+
+ stmdb sp!,{r4-r7}
+ vstmdb sp!,{d8-d15} @ ABI specification says so
+
+ tst ip,ip @ is_base2_26?
+ bne .Lbase2_26_neon
+
+ stmdb sp!,{r1-r3,lr}
+ bl .Lpoly1305_init_neon
+
+ ldr r4,[r0,#0] @ load hash value base 2^32
+ ldr r5,[r0,#4]
+ ldr r6,[r0,#8]
+ ldr r7,[r0,#12]
+ ldr ip,[r0,#16]
+
+ and r2,r4,#0x03ffffff @ base 2^32 -> base 2^26
+ mov r3,r4,lsr#26
+ veor d10,d10,d10
+ mov r4,r5,lsr#20
+ orr r3,r3,r5,lsl#6
+ veor d12,d12,d12
+ mov r5,r6,lsr#14
+ orr r4,r4,r6,lsl#12
+ veor d14,d14,d14
+ mov r6,r7,lsr#8
+ orr r5,r5,r7,lsl#18
+ veor d16,d16,d16
+ and r3,r3,#0x03ffffff
+ orr r6,r6,ip,lsl#24
+ veor d18,d18,d18
+ and r4,r4,#0x03ffffff
+ mov r1,#1
+ and r5,r5,#0x03ffffff
+ str r1,[r0,#36] @ set is_base2_26
+
+ vmov.32 d10[0],r2
+ vmov.32 d12[0],r3
+ vmov.32 d14[0],r4
+ vmov.32 d16[0],r5
+ vmov.32 d18[0],r6
+ adr r5,.Lzeros
+
+ ldmia sp!,{r1-r3,lr}
+ b .Lhash_loaded
+
+.align 4
+.Lbase2_26_neon:
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ load hash value
+
+ veor d10,d10,d10
+ veor d12,d12,d12
+ veor d14,d14,d14
+ veor d16,d16,d16
+ veor d18,d18,d18
+ vld4.32 {d10[0],d12[0],d14[0],d16[0]},[r0]!
+ adr r5,.Lzeros
+ vld1.32 {d18[0]},[r0]
+ sub r0,r0,#16 @ rewind
+
+.Lhash_loaded:
+ add r4,r1,#32
+ mov r3,r3,lsl#24
+ tst r2,#31
+ beq .Leven
+
+ vld4.32 {d20[0],d22[0],d24[0],d26[0]},[r1]!
+ vmov.32 d28[0],r3
+ sub r2,r2,#16
+ add r4,r1,#32
+
+# ifdef __ARMEB__
+ vrev32.8 q10,q10
+ vrev32.8 q13,q13
+ vrev32.8 q11,q11
+ vrev32.8 q12,q12
+# endif
+ vsri.u32 d28,d26,#8 @ base 2^32 -> base 2^26
+ vshl.u32 d26,d26,#18
+
+ vsri.u32 d26,d24,#14
+ vshl.u32 d24,d24,#12
+ vadd.i32 d29,d28,d18 @ add hash value and move to #hi
+
+ vbic.i32 d26,#0xfc000000
+ vsri.u32 d24,d22,#20
+ vshl.u32 d22,d22,#6
+
+ vbic.i32 d24,#0xfc000000
+ vsri.u32 d22,d20,#26
+ vadd.i32 d27,d26,d16
+
+ vbic.i32 d20,#0xfc000000
+ vbic.i32 d22,#0xfc000000
+ vadd.i32 d25,d24,d14
+
+ vadd.i32 d21,d20,d10
+ vadd.i32 d23,d22,d12
+
+ mov r7,r5
+ add r6,r0,#48
+
+ cmp r2,r2
+ b .Long_tail
+
+.align 4
+.Leven:
+ subs r2,r2,#64
+ it lo
+ movlo r4,r5
+
+ vmov.i32 q14,#1<<24 @ padbit, yes, always
+ vld4.32 {d20,d22,d24,d26},[r1] @ inp[0:1]
+ add r1,r1,#64
+ vld4.32 {d21,d23,d25,d27},[r4] @ inp[2:3] (or 0)
+ add r4,r4,#64
+ itt hi
+ addhi r7,r0,#(48+1*9*4)
+ addhi r6,r0,#(48+3*9*4)
+
+# ifdef __ARMEB__
+ vrev32.8 q10,q10
+ vrev32.8 q13,q13
+ vrev32.8 q11,q11
+ vrev32.8 q12,q12
+# endif
+ vsri.u32 q14,q13,#8 @ base 2^32 -> base 2^26
+ vshl.u32 q13,q13,#18
+
+ vsri.u32 q13,q12,#14
+ vshl.u32 q12,q12,#12
+
+ vbic.i32 q13,#0xfc000000
+ vsri.u32 q12,q11,#20
+ vshl.u32 q11,q11,#6
+
+ vbic.i32 q12,#0xfc000000
+ vsri.u32 q11,q10,#26
+
+ vbic.i32 q10,#0xfc000000
+ vbic.i32 q11,#0xfc000000
+
+ bls .Lskip_loop
+
+ vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r7]! @ load r^2
+ vld4.32 {d0[0],d1[0],d2[0],d3[0]},[r6]! @ load r^4
+ vld4.32 {d4[1],d5[1],d6[1],d7[1]},[r7]!
+ vld4.32 {d4[0],d5[0],d6[0],d7[0]},[r6]!
+ b .Loop_neon
+
+.align 5
+.Loop_neon:
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2
+ @ ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^3+inp[7]*r
+ @ ___________________/
+ @ ((inp[0]*r^4+inp[2]*r^2+inp[4])*r^4+inp[6]*r^2+inp[8])*r^2
+ @ ((inp[1]*r^4+inp[3]*r^2+inp[5])*r^4+inp[7]*r^2+inp[9])*r
+ @ ___________________/ ____________________/
+ @
+ @ Note that we start with inp[2:3]*r^2. This is because it
+ @ doesn't depend on reduction in previous iteration.
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ d4 = h4*r0 + h3*r1 + h2*r2 + h1*r3 + h0*r4
+ @ d3 = h3*r0 + h2*r1 + h1*r2 + h0*r3 + h4*5*r4
+ @ d2 = h2*r0 + h1*r1 + h0*r2 + h4*5*r3 + h3*5*r4
+ @ d1 = h1*r0 + h0*r1 + h4*5*r2 + h3*5*r3 + h2*5*r4
+ @ d0 = h0*r0 + h4*5*r1 + h3*5*r2 + h2*5*r3 + h1*5*r4
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ inp[2:3]*r^2
+
+ vadd.i32 d24,d24,d14 @ accumulate inp[0:1]
+ vmull.u32 q7,d25,d0[1]
+ vadd.i32 d20,d20,d10
+ vmull.u32 q5,d21,d0[1]
+ vadd.i32 d26,d26,d16
+ vmull.u32 q8,d27,d0[1]
+ vmlal.u32 q7,d23,d1[1]
+ vadd.i32 d22,d22,d12
+ vmull.u32 q6,d23,d0[1]
+
+ vadd.i32 d28,d28,d18
+ vmull.u32 q9,d29,d0[1]
+ subs r2,r2,#64
+ vmlal.u32 q5,d29,d2[1]
+ it lo
+ movlo r4,r5
+ vmlal.u32 q8,d25,d1[1]
+ vld1.32 d8[1],[r7,:32]
+ vmlal.u32 q6,d21,d1[1]
+ vmlal.u32 q9,d27,d1[1]
+
+ vmlal.u32 q5,d27,d4[1]
+ vmlal.u32 q8,d23,d3[1]
+ vmlal.u32 q9,d25,d3[1]
+ vmlal.u32 q6,d29,d4[1]
+ vmlal.u32 q7,d21,d3[1]
+
+ vmlal.u32 q8,d21,d5[1]
+ vmlal.u32 q5,d25,d6[1]
+ vmlal.u32 q9,d23,d5[1]
+ vmlal.u32 q6,d27,d6[1]
+ vmlal.u32 q7,d29,d6[1]
+
+ vmlal.u32 q8,d29,d8[1]
+ vmlal.u32 q5,d23,d8[1]
+ vmlal.u32 q9,d21,d7[1]
+ vmlal.u32 q6,d25,d8[1]
+ vmlal.u32 q7,d27,d8[1]
+
+ vld4.32 {d21,d23,d25,d27},[r4] @ inp[2:3] (or 0)
+ add r4,r4,#64
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ (hash+inp[0:1])*r^4 and accumulate
+
+ vmlal.u32 q8,d26,d0[0]
+ vmlal.u32 q5,d20,d0[0]
+ vmlal.u32 q9,d28,d0[0]
+ vmlal.u32 q6,d22,d0[0]
+ vmlal.u32 q7,d24,d0[0]
+ vld1.32 d8[0],[r6,:32]
+
+ vmlal.u32 q8,d24,d1[0]
+ vmlal.u32 q5,d28,d2[0]
+ vmlal.u32 q9,d26,d1[0]
+ vmlal.u32 q6,d20,d1[0]
+ vmlal.u32 q7,d22,d1[0]
+
+ vmlal.u32 q8,d22,d3[0]
+ vmlal.u32 q5,d26,d4[0]
+ vmlal.u32 q9,d24,d3[0]
+ vmlal.u32 q6,d28,d4[0]
+ vmlal.u32 q7,d20,d3[0]
+
+ vmlal.u32 q8,d20,d5[0]
+ vmlal.u32 q5,d24,d6[0]
+ vmlal.u32 q9,d22,d5[0]
+ vmlal.u32 q6,d26,d6[0]
+ vmlal.u32 q8,d28,d8[0]
+
+ vmlal.u32 q7,d28,d6[0]
+ vmlal.u32 q5,d22,d8[0]
+ vmlal.u32 q9,d20,d7[0]
+ vmov.i32 q14,#1<<24 @ padbit, yes, always
+ vmlal.u32 q6,d24,d8[0]
+ vmlal.u32 q7,d26,d8[0]
+
+ vld4.32 {d20,d22,d24,d26},[r1] @ inp[0:1]
+ add r1,r1,#64
+# ifdef __ARMEB__
+ vrev32.8 q10,q10
+ vrev32.8 q11,q11
+ vrev32.8 q12,q12
+ vrev32.8 q13,q13
+# endif
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ lazy reduction interleaved with base 2^32 -> base 2^26 of
+ @ inp[0:3] previously loaded to q10-q13 and smashed to q10-q14.
+
+ vshr.u64 q15,q8,#26
+ vmovn.i64 d16,q8
+ vshr.u64 q4,q5,#26
+ vmovn.i64 d10,q5
+ vadd.i64 q9,q9,q15 @ h3 -> h4
+ vbic.i32 d16,#0xfc000000
+ vsri.u32 q14,q13,#8 @ base 2^32 -> base 2^26
+ vadd.i64 q6,q6,q4 @ h0 -> h1
+ vshl.u32 q13,q13,#18
+ vbic.i32 d10,#0xfc000000
+
+ vshrn.u64 d30,q9,#26
+ vmovn.i64 d18,q9
+ vshr.u64 q4,q6,#26
+ vmovn.i64 d12,q6
+ vadd.i64 q7,q7,q4 @ h1 -> h2
+ vsri.u32 q13,q12,#14
+ vbic.i32 d18,#0xfc000000
+ vshl.u32 q12,q12,#12
+ vbic.i32 d12,#0xfc000000
+
+ vadd.i32 d10,d10,d30
+ vshl.u32 d30,d30,#2
+ vbic.i32 q13,#0xfc000000
+ vshrn.u64 d8,q7,#26
+ vmovn.i64 d14,q7
+ vaddl.u32 q5,d10,d30 @ h4 -> h0 [widen for a sec]
+ vsri.u32 q12,q11,#20
+ vadd.i32 d16,d16,d8 @ h2 -> h3
+ vshl.u32 q11,q11,#6
+ vbic.i32 d14,#0xfc000000
+ vbic.i32 q12,#0xfc000000
+
+ vshrn.u64 d30,q5,#26 @ re-narrow
+ vmovn.i64 d10,q5
+ vsri.u32 q11,q10,#26
+ vbic.i32 q10,#0xfc000000
+ vshr.u32 d8,d16,#26
+ vbic.i32 d16,#0xfc000000
+ vbic.i32 d10,#0xfc000000
+ vadd.i32 d12,d12,d30 @ h0 -> h1
+ vadd.i32 d18,d18,d8 @ h3 -> h4
+ vbic.i32 q11,#0xfc000000
+
+ bhi .Loop_neon
+
+.Lskip_loop:
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ multiply (inp[0:1]+hash) or inp[2:3] by r^2:r^1
+
+ add r7,r0,#(48+0*9*4)
+ add r6,r0,#(48+1*9*4)
+ adds r2,r2,#32
+ it ne
+ movne r2,#0
+ bne .Long_tail
+
+ vadd.i32 d25,d24,d14 @ add hash value and move to #hi
+ vadd.i32 d21,d20,d10
+ vadd.i32 d27,d26,d16
+ vadd.i32 d23,d22,d12
+ vadd.i32 d29,d28,d18
+
+.Long_tail:
+ vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r7]! @ load r^1
+ vld4.32 {d0[0],d1[0],d2[0],d3[0]},[r6]! @ load r^2
+
+ vadd.i32 d24,d24,d14 @ can be redundant
+ vmull.u32 q7,d25,d0
+ vadd.i32 d20,d20,d10
+ vmull.u32 q5,d21,d0
+ vadd.i32 d26,d26,d16
+ vmull.u32 q8,d27,d0
+ vadd.i32 d22,d22,d12
+ vmull.u32 q6,d23,d0
+ vadd.i32 d28,d28,d18
+ vmull.u32 q9,d29,d0
+
+ vmlal.u32 q5,d29,d2
+ vld4.32 {d4[1],d5[1],d6[1],d7[1]},[r7]!
+ vmlal.u32 q8,d25,d1
+ vld4.32 {d4[0],d5[0],d6[0],d7[0]},[r6]!
+ vmlal.u32 q6,d21,d1
+ vmlal.u32 q9,d27,d1
+ vmlal.u32 q7,d23,d1
+
+ vmlal.u32 q8,d23,d3
+ vld1.32 d8[1],[r7,:32]
+ vmlal.u32 q5,d27,d4
+ vld1.32 d8[0],[r6,:32]
+ vmlal.u32 q9,d25,d3
+ vmlal.u32 q6,d29,d4
+ vmlal.u32 q7,d21,d3
+
+ vmlal.u32 q8,d21,d5
+ it ne
+ addne r7,r0,#(48+2*9*4)
+ vmlal.u32 q5,d25,d6
+ it ne
+ addne r6,r0,#(48+3*9*4)
+ vmlal.u32 q9,d23,d5
+ vmlal.u32 q6,d27,d6
+ vmlal.u32 q7,d29,d6
+
+ vmlal.u32 q8,d29,d8
+ vorn q0,q0,q0 @ all-ones, can be redundant
+ vmlal.u32 q5,d23,d8
+ vshr.u64 q0,q0,#38
+ vmlal.u32 q9,d21,d7
+ vmlal.u32 q6,d25,d8
+ vmlal.u32 q7,d27,d8
+
+ beq .Lshort_tail
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ (hash+inp[0:1])*r^4:r^3 and accumulate
+
+ vld4.32 {d0[1],d1[1],d2[1],d3[1]},[r7]! @ load r^3
+ vld4.32 {d0[0],d1[0],d2[0],d3[0]},[r6]! @ load r^4
+
+ vmlal.u32 q7,d24,d0
+ vmlal.u32 q5,d20,d0
+ vmlal.u32 q8,d26,d0
+ vmlal.u32 q6,d22,d0
+ vmlal.u32 q9,d28,d0
+
+ vmlal.u32 q5,d28,d2
+ vld4.32 {d4[1],d5[1],d6[1],d7[1]},[r7]!
+ vmlal.u32 q8,d24,d1
+ vld4.32 {d4[0],d5[0],d6[0],d7[0]},[r6]!
+ vmlal.u32 q6,d20,d1
+ vmlal.u32 q9,d26,d1
+ vmlal.u32 q7,d22,d1
+
+ vmlal.u32 q8,d22,d3
+ vld1.32 d8[1],[r7,:32]
+ vmlal.u32 q5,d26,d4
+ vld1.32 d8[0],[r6,:32]
+ vmlal.u32 q9,d24,d3
+ vmlal.u32 q6,d28,d4
+ vmlal.u32 q7,d20,d3
+
+ vmlal.u32 q8,d20,d5
+ vmlal.u32 q5,d24,d6
+ vmlal.u32 q9,d22,d5
+ vmlal.u32 q6,d26,d6
+ vmlal.u32 q7,d28,d6
+
+ vmlal.u32 q8,d28,d8
+ vorn q0,q0,q0 @ all-ones
+ vmlal.u32 q5,d22,d8
+ vshr.u64 q0,q0,#38
+ vmlal.u32 q9,d20,d7
+ vmlal.u32 q6,d24,d8
+ vmlal.u32 q7,d26,d8
+
+.Lshort_tail:
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ horizontal addition
+
+ vadd.i64 d16,d16,d17
+ vadd.i64 d10,d10,d11
+ vadd.i64 d18,d18,d19
+ vadd.i64 d12,d12,d13
+ vadd.i64 d14,d14,d15
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ lazy reduction, but without narrowing
+
+ vshr.u64 q15,q8,#26
+ vand.i64 q8,q8,q0
+ vshr.u64 q4,q5,#26
+ vand.i64 q5,q5,q0
+ vadd.i64 q9,q9,q15 @ h3 -> h4
+ vadd.i64 q6,q6,q4 @ h0 -> h1
+
+ vshr.u64 q15,q9,#26
+ vand.i64 q9,q9,q0
+ vshr.u64 q4,q6,#26
+ vand.i64 q6,q6,q0
+ vadd.i64 q7,q7,q4 @ h1 -> h2
+
+ vadd.i64 q5,q5,q15
+ vshl.u64 q15,q15,#2
+ vshr.u64 q4,q7,#26
+ vand.i64 q7,q7,q0
+ vadd.i64 q5,q5,q15 @ h4 -> h0
+ vadd.i64 q8,q8,q4 @ h2 -> h3
+
+ vshr.u64 q15,q5,#26
+ vand.i64 q5,q5,q0
+ vshr.u64 q4,q8,#26
+ vand.i64 q8,q8,q0
+ vadd.i64 q6,q6,q15 @ h0 -> h1
+ vadd.i64 q9,q9,q4 @ h3 -> h4
+
+ cmp r2,#0
+ bne .Leven
+
+ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+ @ store hash value
+
+ vst4.32 {d10[0],d12[0],d14[0],d16[0]},[r0]!
+ vst1.32 {d18[0]},[r0]
+
+ vldmia sp!,{d8-d15} @ epilogue
+ ldmia sp!,{r4-r7}
+ bx lr @ bx lr
+.size poly1305_blocks_neon,.-poly1305_blocks_neon
+
+.align 5
+.Lzeros:
+.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+#ifndef __KERNEL__
+.LOPENSSL_armcap:
+# ifdef _WIN32
+.word OPENSSL_armcap_P
+# else
+.word OPENSSL_armcap_P-.Lpoly1305_init
+# endif
+.comm OPENSSL_armcap_P,4,4
+.hidden OPENSSL_armcap_P
+#endif
+#endif
+.asciz "Poly1305 for ARMv4/NEON, CRYPTOGAMS by @dot-asm"
+.align 2
diff --git a/arch/arm/crypto/poly1305-glue.c b/arch/arm/crypto/poly1305-glue.c
new file mode 100644
index 0000000..c31bd8f
--- /dev/null
+++ b/arch/arm/crypto/poly1305-glue.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * OpenSSL/Cryptogams accelerated Poly1305 transform for ARM
+ *
+ * Copyright (C) 2019 Linaro Ltd. <ard.biesheuvel@linaro.org>
+ */
+
+#include <asm/hwcap.h>
+#include <asm/neon.h>
+#include <asm/simd.h>
+#include <asm/unaligned.h>
+#include <crypto/algapi.h>
+#include <crypto/internal/hash.h>
+#include <crypto/internal/poly1305.h>
+#include <crypto/internal/simd.h>
+#include <linux/cpufeature.h>
+#include <linux/crypto.h>
+#include <linux/jump_label.h>
+#include <linux/module.h>
+
+void poly1305_init_arm(void *state, const u8 *key);
+void poly1305_blocks_arm(void *state, const u8 *src, u32 len, u32 hibit);
+void poly1305_blocks_neon(void *state, const u8 *src, u32 len, u32 hibit);
+void poly1305_emit_arm(void *state, u8 *digest, const u32 *nonce);
+
+void __weak poly1305_blocks_neon(void *state, const u8 *src, u32 len, u32 hibit)
+{
+}
+
+static __ro_after_init DEFINE_STATIC_KEY_FALSE(have_neon);
+
+void poly1305_init_arch(struct poly1305_desc_ctx *dctx, const u8 key[POLY1305_KEY_SIZE])
+{
+ poly1305_init_arm(&dctx->h, key);
+ dctx->s[0] = get_unaligned_le32(key + 16);
+ dctx->s[1] = get_unaligned_le32(key + 20);
+ dctx->s[2] = get_unaligned_le32(key + 24);
+ dctx->s[3] = get_unaligned_le32(key + 28);
+ dctx->buflen = 0;
+}
+EXPORT_SYMBOL(poly1305_init_arch);
+
+static int arm_poly1305_init(struct shash_desc *desc)
+{
+ struct poly1305_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ dctx->buflen = 0;
+ dctx->rset = 0;
+ dctx->sset = false;
+
+ return 0;
+}
+
+static void arm_poly1305_blocks(struct poly1305_desc_ctx *dctx, const u8 *src,
+ u32 len, u32 hibit, bool do_neon)
+{
+ if (unlikely(!dctx->sset)) {
+ if (!dctx->rset) {
+ poly1305_init_arm(&dctx->h, src);
+ src += POLY1305_BLOCK_SIZE;
+ len -= POLY1305_BLOCK_SIZE;
+ dctx->rset = 1;
+ }
+ if (len >= POLY1305_BLOCK_SIZE) {
+ dctx->s[0] = get_unaligned_le32(src + 0);
+ dctx->s[1] = get_unaligned_le32(src + 4);
+ dctx->s[2] = get_unaligned_le32(src + 8);
+ dctx->s[3] = get_unaligned_le32(src + 12);
+ src += POLY1305_BLOCK_SIZE;
+ len -= POLY1305_BLOCK_SIZE;
+ dctx->sset = true;
+ }
+ if (len < POLY1305_BLOCK_SIZE)
+ return;
+ }
+
+ len &= ~(POLY1305_BLOCK_SIZE - 1);
+
+ if (static_branch_likely(&have_neon) && likely(do_neon))
+ poly1305_blocks_neon(&dctx->h, src, len, hibit);
+ else
+ poly1305_blocks_arm(&dctx->h, src, len, hibit);
+}
+
+static void arm_poly1305_do_update(struct poly1305_desc_ctx *dctx,
+ const u8 *src, u32 len, bool do_neon)
+{
+ if (unlikely(dctx->buflen)) {
+ u32 bytes = min(len, POLY1305_BLOCK_SIZE - dctx->buflen);
+
+ memcpy(dctx->buf + dctx->buflen, src, bytes);
+ src += bytes;
+ len -= bytes;
+ dctx->buflen += bytes;
+
+ if (dctx->buflen == POLY1305_BLOCK_SIZE) {
+ arm_poly1305_blocks(dctx, dctx->buf,
+ POLY1305_BLOCK_SIZE, 1, false);
+ dctx->buflen = 0;
+ }
+ }
+
+ if (likely(len >= POLY1305_BLOCK_SIZE)) {
+ arm_poly1305_blocks(dctx, src, len, 1, do_neon);
+ src += round_down(len, POLY1305_BLOCK_SIZE);
+ len %= POLY1305_BLOCK_SIZE;
+ }
+
+ if (unlikely(len)) {
+ dctx->buflen = len;
+ memcpy(dctx->buf, src, len);
+ }
+}
+
+static int arm_poly1305_update(struct shash_desc *desc,
+ const u8 *src, unsigned int srclen)
+{
+ struct poly1305_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ arm_poly1305_do_update(dctx, src, srclen, false);
+ return 0;
+}
+
+static int __maybe_unused arm_poly1305_update_neon(struct shash_desc *desc,
+ const u8 *src,
+ unsigned int srclen)
+{
+ struct poly1305_desc_ctx *dctx = shash_desc_ctx(desc);
+ bool do_neon = crypto_simd_usable() && srclen > 128;
+
+ if (static_branch_likely(&have_neon) && do_neon)
+ kernel_neon_begin();
+ arm_poly1305_do_update(dctx, src, srclen, do_neon);
+ if (static_branch_likely(&have_neon) && do_neon)
+ kernel_neon_end();
+ return 0;
+}
+
+void poly1305_update_arch(struct poly1305_desc_ctx *dctx, const u8 *src,
+ unsigned int nbytes)
+{
+ bool do_neon = IS_ENABLED(CONFIG_KERNEL_MODE_NEON) &&
+ crypto_simd_usable();
+
+ if (unlikely(dctx->buflen)) {
+ u32 bytes = min(nbytes, POLY1305_BLOCK_SIZE - dctx->buflen);
+
+ memcpy(dctx->buf + dctx->buflen, src, bytes);
+ src += bytes;
+ nbytes -= bytes;
+ dctx->buflen += bytes;
+
+ if (dctx->buflen == POLY1305_BLOCK_SIZE) {
+ poly1305_blocks_arm(&dctx->h, dctx->buf,
+ POLY1305_BLOCK_SIZE, 1);
+ dctx->buflen = 0;
+ }
+ }
+
+ if (likely(nbytes >= POLY1305_BLOCK_SIZE)) {
+ unsigned int len = round_down(nbytes, POLY1305_BLOCK_SIZE);
+
+ if (static_branch_likely(&have_neon) && do_neon) {
+ do {
+ unsigned int todo = min_t(unsigned int, len, SZ_4K);
+
+ kernel_neon_begin();
+ poly1305_blocks_neon(&dctx->h, src, todo, 1);
+ kernel_neon_end();
+
+ len -= todo;
+ src += todo;
+ } while (len);
+ } else {
+ poly1305_blocks_arm(&dctx->h, src, len, 1);
+ src += len;
+ }
+ nbytes %= POLY1305_BLOCK_SIZE;
+ }
+
+ if (unlikely(nbytes)) {
+ dctx->buflen = nbytes;
+ memcpy(dctx->buf, src, nbytes);
+ }
+}
+EXPORT_SYMBOL(poly1305_update_arch);
+
+void poly1305_final_arch(struct poly1305_desc_ctx *dctx, u8 *dst)
+{
+ if (unlikely(dctx->buflen)) {
+ dctx->buf[dctx->buflen++] = 1;
+ memset(dctx->buf + dctx->buflen, 0,
+ POLY1305_BLOCK_SIZE - dctx->buflen);
+ poly1305_blocks_arm(&dctx->h, dctx->buf, POLY1305_BLOCK_SIZE, 0);
+ }
+
+ poly1305_emit_arm(&dctx->h, dst, dctx->s);
+ *dctx = (struct poly1305_desc_ctx){};
+}
+EXPORT_SYMBOL(poly1305_final_arch);
+
+static int arm_poly1305_final(struct shash_desc *desc, u8 *dst)
+{
+ struct poly1305_desc_ctx *dctx = shash_desc_ctx(desc);
+
+ if (unlikely(!dctx->sset))
+ return -ENOKEY;
+
+ poly1305_final_arch(dctx, dst);
+ return 0;
+}
+
+static struct shash_alg arm_poly1305_algs[] = {{
+ .init = arm_poly1305_init,
+ .update = arm_poly1305_update,
+ .final = arm_poly1305_final,
+ .digestsize = POLY1305_DIGEST_SIZE,
+ .descsize = sizeof(struct poly1305_desc_ctx),
+
+ .base.cra_name = "poly1305",
+ .base.cra_driver_name = "poly1305-arm",
+ .base.cra_priority = 150,
+ .base.cra_blocksize = POLY1305_BLOCK_SIZE,
+ .base.cra_module = THIS_MODULE,
+#ifdef CONFIG_KERNEL_MODE_NEON
+}, {
+ .init = arm_poly1305_init,
+ .update = arm_poly1305_update_neon,
+ .final = arm_poly1305_final,
+ .digestsize = POLY1305_DIGEST_SIZE,
+ .descsize = sizeof(struct poly1305_desc_ctx),
+
+ .base.cra_name = "poly1305",
+ .base.cra_driver_name = "poly1305-neon",
+ .base.cra_priority = 200,
+ .base.cra_blocksize = POLY1305_BLOCK_SIZE,
+ .base.cra_module = THIS_MODULE,
+#endif
+}};
+
+static int __init arm_poly1305_mod_init(void)
+{
+ if (IS_ENABLED(CONFIG_KERNEL_MODE_NEON) &&
+ (elf_hwcap & HWCAP_NEON))
+ static_branch_enable(&have_neon);
+ else if (IS_REACHABLE(CONFIG_CRYPTO_HASH))
+ /* register only the first entry */
+ return crypto_register_shash(&arm_poly1305_algs[0]);
+
+ return IS_REACHABLE(CONFIG_CRYPTO_HASH) ?
+ crypto_register_shashes(arm_poly1305_algs,
+ ARRAY_SIZE(arm_poly1305_algs)) : 0;
+}
+
+static void __exit arm_poly1305_mod_exit(void)
+{
+ if (!IS_REACHABLE(CONFIG_CRYPTO_HASH))
+ return;
+ if (!static_branch_likely(&have_neon)) {
+ crypto_unregister_shash(&arm_poly1305_algs[0]);
+ return;
+ }
+ crypto_unregister_shashes(arm_poly1305_algs,
+ ARRAY_SIZE(arm_poly1305_algs));
+}
+
+module_init(arm_poly1305_mod_init);
+module_exit(arm_poly1305_mod_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS_CRYPTO("poly1305");
+MODULE_ALIAS_CRYPTO("poly1305-arm");
+MODULE_ALIAS_CRYPTO("poly1305-neon");
diff --git a/arch/arm/crypto/sha1-armv4-large.S b/arch/arm/crypto/sha1-armv4-large.S
index f82cd8c..1c8b685 100644
--- a/arch/arm/crypto/sha1-armv4-large.S
+++ b/arch/arm/crypto/sha1-armv4-large.S
@@ -13,7 +13,7 @@
@ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
@ project. The module is, however, dual licensed under OpenSSL and
@ CRYPTOGAMS licenses depending on where you obtain it. For further
-@ details see http://www.openssl.org/~appro/cryptogams/.
+@ details see https://www.openssl.org/~appro/cryptogams/.
@ ====================================================================
@ sha1_block procedure for ARMv4.
diff --git a/arch/arm/crypto/sha1-ce-core.S b/arch/arm/crypto/sha1-ce-core.S
index 49a74a4..8a702e0 100644
--- a/arch/arm/crypto/sha1-ce-core.S
+++ b/arch/arm/crypto/sha1-ce-core.S
@@ -10,6 +10,7 @@
#include <asm/assembler.h>
.text
+ .arch armv8-a
.fpu crypto-neon-fp-armv8
k0 .req q0
diff --git a/arch/arm/crypto/sha1_glue.c b/arch/arm/crypto/sha1_glue.c
index c80b0eb..4e954b3 100644
--- a/arch/arm/crypto/sha1_glue.c
+++ b/arch/arm/crypto/sha1_glue.c
@@ -14,7 +14,6 @@
#include <crypto/internal/hash.h>
#include <linux/init.h>
#include <linux/module.h>
-#include <linux/cryptohash.h>
#include <linux/types.h>
#include <crypto/sha.h>
#include <crypto/sha1_base.h>
diff --git a/arch/arm/crypto/sha1_neon_glue.c b/arch/arm/crypto/sha1_neon_glue.c
index 2c36273..0071e5e 100644
--- a/arch/arm/crypto/sha1_neon_glue.c
+++ b/arch/arm/crypto/sha1_neon_glue.c
@@ -18,7 +18,6 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mm.h>
-#include <linux/cryptohash.h>
#include <linux/types.h>
#include <crypto/sha.h>
#include <crypto/sha1_base.h>
diff --git a/arch/arm/crypto/sha2-ce-core.S b/arch/arm/crypto/sha2-ce-core.S
index 4ad5175..b6369d2 100644
--- a/arch/arm/crypto/sha2-ce-core.S
+++ b/arch/arm/crypto/sha2-ce-core.S
@@ -10,6 +10,7 @@
#include <asm/assembler.h>
.text
+ .arch armv8-a
.fpu crypto-neon-fp-armv8
k0 .req q7
diff --git a/arch/arm/crypto/sha256-armv4.pl b/arch/arm/crypto/sha256-armv4.pl
index a03cf4d..f3a2b54 100644
--- a/arch/arm/crypto/sha256-armv4.pl
+++ b/arch/arm/crypto/sha256-armv4.pl
@@ -13,7 +13,7 @@
# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
# project. The module is, however, dual licensed under OpenSSL and
# CRYPTOGAMS licenses depending on where you obtain it. For further
-# details see http://www.openssl.org/~appro/cryptogams/.
+# details see https://www.openssl.org/~appro/cryptogams/.
# ====================================================================
# SHA256 block procedure for ARMv4. May 2007.
@@ -175,7 +175,6 @@
#else
.syntax unified
# ifdef __thumb2__
-# define adrl adr
.thumb
# else
.code 32
@@ -471,7 +470,8 @@
stmdb sp!,{r4-r12,lr}
sub $H,sp,#16*4+16
- adrl $Ktbl,K256
+ adr $Ktbl,.Lsha256_block_data_order
+ sub $Ktbl,$Ktbl,#.Lsha256_block_data_order-K256
bic $H,$H,#15 @ align for 128-bit stores
mov $t2,sp
mov sp,$H @ alloca
diff --git a/arch/arm/crypto/sha256-core.S_shipped b/arch/arm/crypto/sha256-core.S_shipped
index 054aae0..6363014 100644
--- a/arch/arm/crypto/sha256-core.S_shipped
+++ b/arch/arm/crypto/sha256-core.S_shipped
@@ -12,7 +12,7 @@
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
@ project. The module is, however, dual licensed under OpenSSL and
@ CRYPTOGAMS licenses depending on where you obtain it. For further
-@ details see http://www.openssl.org/~appro/cryptogams/.
+@ details see https://www.openssl.org/~appro/cryptogams/.
@ ====================================================================
@ SHA256 block procedure for ARMv4. May 2007.
@@ -56,7 +56,6 @@
#else
.syntax unified
# ifdef __thumb2__
-# define adrl adr
.thumb
# else
.code 32
@@ -1885,7 +1884,8 @@
stmdb sp!,{r4-r12,lr}
sub r11,sp,#16*4+16
- adrl r14,K256
+ adr r14,.Lsha256_block_data_order
+ sub r14,r14,#.Lsha256_block_data_order-K256
bic r11,r11,#15 @ align for 128-bit stores
mov r12,sp
mov sp,r11 @ alloca
diff --git a/arch/arm/crypto/sha256_glue.c b/arch/arm/crypto/sha256_glue.c
index 215497f..b8a4f79 100644
--- a/arch/arm/crypto/sha256_glue.c
+++ b/arch/arm/crypto/sha256_glue.c
@@ -15,7 +15,6 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mm.h>
-#include <linux/cryptohash.h>
#include <linux/types.h>
#include <linux/string.h>
#include <crypto/sha.h>
diff --git a/arch/arm/crypto/sha256_neon_glue.c b/arch/arm/crypto/sha256_neon_glue.c
index 38645e4..79820b9 100644
--- a/arch/arm/crypto/sha256_neon_glue.c
+++ b/arch/arm/crypto/sha256_neon_glue.c
@@ -11,7 +11,6 @@
#include <crypto/internal/hash.h>
#include <crypto/internal/simd.h>
-#include <linux/cryptohash.h>
#include <linux/types.h>
#include <linux/string.h>
#include <crypto/sha.h>
diff --git a/arch/arm/crypto/sha512-armv4.pl b/arch/arm/crypto/sha512-armv4.pl
index 788c17b..2fc3516 100644
--- a/arch/arm/crypto/sha512-armv4.pl
+++ b/arch/arm/crypto/sha512-armv4.pl
@@ -13,7 +13,7 @@
# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
# project. The module is, however, dual licensed under OpenSSL and
# CRYPTOGAMS licenses depending on where you obtain it. For further
-# details see http://www.openssl.org/~appro/cryptogams/.
+# details see https://www.openssl.org/~appro/cryptogams/.
# ====================================================================
# SHA512 block procedure for ARMv4. September 2007.
@@ -43,7 +43,7 @@
# terms it's 22.6 cycles per byte, which is disappointing result.
# Technical writers asserted that 3-way S4 pipeline can sustain
# multiple NEON instructions per cycle, but dual NEON issue could
-# not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
+# not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html
# for further details. On side note Cortex-A15 processes one byte in
# 16 cycles.
@@ -212,7 +212,6 @@
#else
.syntax unified
# ifdef __thumb2__
-# define adrl adr
.thumb
# else
.code 32
@@ -602,7 +601,8 @@
dmb @ errata #451034 on early Cortex A8
add $len,$inp,$len,lsl#7 @ len to point at the end of inp
VFP_ABI_PUSH
- adrl $Ktbl,K512
+ adr $Ktbl,.Lsha512_block_data_order
+ sub $Ktbl,$Ktbl,.Lsha512_block_data_order-K512
vldmia $ctx,{$A-$H} @ load context
.Loop_neon:
___
diff --git a/arch/arm/crypto/sha512-core.S_shipped b/arch/arm/crypto/sha512-core.S_shipped
index 710ea30..0301462 100644
--- a/arch/arm/crypto/sha512-core.S_shipped
+++ b/arch/arm/crypto/sha512-core.S_shipped
@@ -12,7 +12,7 @@
@ Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
@ project. The module is, however, dual licensed under OpenSSL and
@ CRYPTOGAMS licenses depending on where you obtain it. For further
-@ details see http://www.openssl.org/~appro/cryptogams/.
+@ details see https://www.openssl.org/~appro/cryptogams/.
@ ====================================================================
@ SHA512 block procedure for ARMv4. September 2007.
@@ -42,7 +42,7 @@
@ terms it's 22.6 cycles per byte, which is disappointing result.
@ Technical writers asserted that 3-way S4 pipeline can sustain
@ multiple NEON instructions per cycle, but dual NEON issue could
-@ not be observed, see http://www.openssl.org/~appro/Snapdragon-S4.html
+@ not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html
@ for further details. On side note Cortex-A15 processes one byte in
@ 16 cycles.
@@ -79,7 +79,6 @@
#else
.syntax unified
# ifdef __thumb2__
-# define adrl adr
.thumb
# else
.code 32
@@ -543,7 +542,8 @@
dmb @ errata #451034 on early Cortex A8
add r2,r1,r2,lsl#7 @ len to point at the end of inp
VFP_ABI_PUSH
- adrl r3,K512
+ adr r3,.Lsha512_block_data_order
+ sub r3,r3,.Lsha512_block_data_order-K512
vldmia r0,{d16-d23} @ load context
.Loop_neon:
vshr.u64 d24,d20,#14 @ 0
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 68ca86f..f1398b9 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -1,23 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
-generic-y += compat.h
-generic-y += current.h
generic-y += early_ioremap.h
-generic-y += emergency-restart.h
-generic-y += exec.h
generic-y += extable.h
generic-y += flat.h
-generic-y += irq_regs.h
-generic-y += kdebug.h
-generic-y += local.h
-generic-y += local64.h
-generic-y += mm-arch-hooks.h
-generic-y += mmiowb.h
-generic-y += msi.h
generic-y += parport.h
-generic-y += preempt.h
generic-y += seccomp.h
-generic-y += serial.h
-generic-y += trace_clock.h
generated-y += mach-types.h
generated-y += unistd-nr.h
diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index 0555f14..413abfb 100644
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -10,6 +10,7 @@
#ifndef __ASSEMBLY__
#include <linux/io.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
#include <asm/barrier.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
@@ -37,71 +38,6 @@
#define ICC_AP1R2 __ICC_AP1Rx(2)
#define ICC_AP1R3 __ICC_AP1Rx(3)
-#define ICC_HSRE __ACCESS_CP15(c12, 4, c9, 5)
-
-#define ICH_VSEIR __ACCESS_CP15(c12, 4, c9, 4)
-#define ICH_HCR __ACCESS_CP15(c12, 4, c11, 0)
-#define ICH_VTR __ACCESS_CP15(c12, 4, c11, 1)
-#define ICH_MISR __ACCESS_CP15(c12, 4, c11, 2)
-#define ICH_EISR __ACCESS_CP15(c12, 4, c11, 3)
-#define ICH_ELRSR __ACCESS_CP15(c12, 4, c11, 5)
-#define ICH_VMCR __ACCESS_CP15(c12, 4, c11, 7)
-
-#define __LR0(x) __ACCESS_CP15(c12, 4, c12, x)
-#define __LR8(x) __ACCESS_CP15(c12, 4, c13, x)
-
-#define ICH_LR0 __LR0(0)
-#define ICH_LR1 __LR0(1)
-#define ICH_LR2 __LR0(2)
-#define ICH_LR3 __LR0(3)
-#define ICH_LR4 __LR0(4)
-#define ICH_LR5 __LR0(5)
-#define ICH_LR6 __LR0(6)
-#define ICH_LR7 __LR0(7)
-#define ICH_LR8 __LR8(0)
-#define ICH_LR9 __LR8(1)
-#define ICH_LR10 __LR8(2)
-#define ICH_LR11 __LR8(3)
-#define ICH_LR12 __LR8(4)
-#define ICH_LR13 __LR8(5)
-#define ICH_LR14 __LR8(6)
-#define ICH_LR15 __LR8(7)
-
-/* LR top half */
-#define __LRC0(x) __ACCESS_CP15(c12, 4, c14, x)
-#define __LRC8(x) __ACCESS_CP15(c12, 4, c15, x)
-
-#define ICH_LRC0 __LRC0(0)
-#define ICH_LRC1 __LRC0(1)
-#define ICH_LRC2 __LRC0(2)
-#define ICH_LRC3 __LRC0(3)
-#define ICH_LRC4 __LRC0(4)
-#define ICH_LRC5 __LRC0(5)
-#define ICH_LRC6 __LRC0(6)
-#define ICH_LRC7 __LRC0(7)
-#define ICH_LRC8 __LRC8(0)
-#define ICH_LRC9 __LRC8(1)
-#define ICH_LRC10 __LRC8(2)
-#define ICH_LRC11 __LRC8(3)
-#define ICH_LRC12 __LRC8(4)
-#define ICH_LRC13 __LRC8(5)
-#define ICH_LRC14 __LRC8(6)
-#define ICH_LRC15 __LRC8(7)
-
-#define __ICH_AP0Rx(x) __ACCESS_CP15(c12, 4, c8, x)
-#define ICH_AP0R0 __ICH_AP0Rx(0)
-#define ICH_AP0R1 __ICH_AP0Rx(1)
-#define ICH_AP0R2 __ICH_AP0Rx(2)
-#define ICH_AP0R3 __ICH_AP0Rx(3)
-
-#define __ICH_AP1Rx(x) __ACCESS_CP15(c12, 4, c9, x)
-#define ICH_AP1R0 __ICH_AP1Rx(0)
-#define ICH_AP1R1 __ICH_AP1Rx(1)
-#define ICH_AP1R2 __ICH_AP1Rx(2)
-#define ICH_AP1R3 __ICH_AP1Rx(3)
-
-/* A32-to-A64 mappings used by VGIC save/restore */
-
#define CPUIF_MAP(a32, a64) \
static inline void write_ ## a64(u32 val) \
{ \
@@ -112,21 +48,6 @@
return read_sysreg(a32); \
} \
-#define CPUIF_MAP_LO_HI(a32lo, a32hi, a64) \
-static inline void write_ ## a64(u64 val) \
-{ \
- write_sysreg(lower_32_bits(val), a32lo);\
- write_sysreg(upper_32_bits(val), a32hi);\
-} \
-static inline u64 read_ ## a64(void) \
-{ \
- u64 val = read_sysreg(a32lo); \
- \
- val |= (u64)read_sysreg(a32hi) << 32; \
- \
- return val; \
-}
-
CPUIF_MAP(ICC_PMR, ICC_PMR_EL1)
CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1)
CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1)
@@ -137,40 +58,6 @@
CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1)
CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1)
-CPUIF_MAP(ICH_HCR, ICH_HCR_EL2)
-CPUIF_MAP(ICH_VTR, ICH_VTR_EL2)
-CPUIF_MAP(ICH_MISR, ICH_MISR_EL2)
-CPUIF_MAP(ICH_EISR, ICH_EISR_EL2)
-CPUIF_MAP(ICH_ELRSR, ICH_ELRSR_EL2)
-CPUIF_MAP(ICH_VMCR, ICH_VMCR_EL2)
-CPUIF_MAP(ICH_AP0R3, ICH_AP0R3_EL2)
-CPUIF_MAP(ICH_AP0R2, ICH_AP0R2_EL2)
-CPUIF_MAP(ICH_AP0R1, ICH_AP0R1_EL2)
-CPUIF_MAP(ICH_AP0R0, ICH_AP0R0_EL2)
-CPUIF_MAP(ICH_AP1R3, ICH_AP1R3_EL2)
-CPUIF_MAP(ICH_AP1R2, ICH_AP1R2_EL2)
-CPUIF_MAP(ICH_AP1R1, ICH_AP1R1_EL2)
-CPUIF_MAP(ICH_AP1R0, ICH_AP1R0_EL2)
-CPUIF_MAP(ICC_HSRE, ICC_SRE_EL2)
-CPUIF_MAP(ICC_SRE, ICC_SRE_EL1)
-
-CPUIF_MAP_LO_HI(ICH_LR15, ICH_LRC15, ICH_LR15_EL2)
-CPUIF_MAP_LO_HI(ICH_LR14, ICH_LRC14, ICH_LR14_EL2)
-CPUIF_MAP_LO_HI(ICH_LR13, ICH_LRC13, ICH_LR13_EL2)
-CPUIF_MAP_LO_HI(ICH_LR12, ICH_LRC12, ICH_LR12_EL2)
-CPUIF_MAP_LO_HI(ICH_LR11, ICH_LRC11, ICH_LR11_EL2)
-CPUIF_MAP_LO_HI(ICH_LR10, ICH_LRC10, ICH_LR10_EL2)
-CPUIF_MAP_LO_HI(ICH_LR9, ICH_LRC9, ICH_LR9_EL2)
-CPUIF_MAP_LO_HI(ICH_LR8, ICH_LRC8, ICH_LR8_EL2)
-CPUIF_MAP_LO_HI(ICH_LR7, ICH_LRC7, ICH_LR7_EL2)
-CPUIF_MAP_LO_HI(ICH_LR6, ICH_LRC6, ICH_LR6_EL2)
-CPUIF_MAP_LO_HI(ICH_LR5, ICH_LRC5, ICH_LR5_EL2)
-CPUIF_MAP_LO_HI(ICH_LR4, ICH_LRC4, ICH_LR4_EL2)
-CPUIF_MAP_LO_HI(ICH_LR3, ICH_LRC3, ICH_LR3_EL2)
-CPUIF_MAP_LO_HI(ICH_LR2, ICH_LRC2, ICH_LR2_EL2)
-CPUIF_MAP_LO_HI(ICH_LR1, ICH_LRC1, ICH_LR1_EL2)
-CPUIF_MAP_LO_HI(ICH_LR0, ICH_LRC0, ICH_LR0_EL2)
-
#define read_gicreg(r) read_##r()
#define write_gicreg(v, r) write_##r(v)
@@ -325,15 +212,16 @@
#define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c)
/*
- * GITS_VPROPBASER - hi and lo bits may be accessed independently.
+ * GICR_VPROPBASER - hi and lo bits may be accessed independently.
*/
-#define gits_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c)
+#define gicr_read_vpropbaser(c) __gic_readq_nonatomic(c)
+#define gicr_write_vpropbaser(v, c) __gic_writeq_nonatomic(v, c)
/*
- * GITS_VPENDBASER - the Valid bit must be cleared before changing
+ * GICR_VPENDBASER - the Valid bit must be cleared before changing
* anything else.
*/
-static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)
+static inline void gicr_write_vpendbaser(u64 val, void __iomem *addr)
{
u32 tmp;
@@ -350,7 +238,7 @@
__gic_writeq_nonatomic(val, addr);
}
-#define gits_read_vpendbaser(c) __gic_readq_nonatomic(c)
+#define gicr_read_vpendbaser(c) __gic_readq_nonatomic(c)
static inline bool gic_prio_masking_enabled(void)
{
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 3546d29..24a1f49 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -107,6 +107,16 @@
.endm
#endif
+#if __LINUX_ARM_ARCH__ < 7
+ .macro dsb, args
+ mcr p15, 0, r0, c7, c10, 4
+ .endm
+
+ .macro isb, args
+ mcr p15, 0, r0, c7, c5, 4
+ .endm
+#endif
+
.macro asm_trace_hardirqs_off, save=1
#if defined(CONFIG_TRACE_IRQFLAGS)
.if \save
@@ -269,10 +279,9 @@
.endif ;\
.popsection
#define ALT_UP_B(label) \
- .equ up_b_offset, label - 9998b ;\
.pushsection ".alt.smp.init", "a" ;\
.long 9998b ;\
- W(b) . + up_b_offset ;\
+ W(b) . + (label - 9998b) ;\
.popsection
#else
#define ALT_SMP(instr...)
@@ -495,4 +504,88 @@
#define _ASM_NOKPROBE(entry)
#endif
+ .macro __adldst_l, op, reg, sym, tmp, c
+ .if __LINUX_ARM_ARCH__ < 7
+ ldr\c \tmp, .La\@
+ .subsection 1
+ .align 2
+.La\@: .long \sym - .Lpc\@
+ .previous
+ .else
+ .ifnb \c
+ THUMB( ittt \c )
+ .endif
+ movw\c \tmp, #:lower16:\sym - .Lpc\@
+ movt\c \tmp, #:upper16:\sym - .Lpc\@
+ .endif
+
+#ifndef CONFIG_THUMB2_KERNEL
+ .set .Lpc\@, . + 8 // PC bias
+ .ifc \op, add
+ add\c \reg, \tmp, pc
+ .else
+ \op\c \reg, [pc, \tmp]
+ .endif
+#else
+.Lb\@: add\c \tmp, \tmp, pc
+ /*
+ * In Thumb-2 builds, the PC bias depends on whether we are currently
+ * emitting into a .arm or a .thumb section. The size of the add opcode
+ * above will be 2 bytes when emitting in Thumb mode and 4 bytes when
+ * emitting in ARM mode, so let's use this to account for the bias.
+ */
+ .set .Lpc\@, . + (. - .Lb\@)
+
+ .ifnc \op, add
+ \op\c \reg, [\tmp]
+ .endif
+#endif
+ .endm
+
+ /*
+ * mov_l - move a constant value or [relocated] address into a register
+ */
+ .macro mov_l, dst:req, imm:req
+ .if __LINUX_ARM_ARCH__ < 7
+ ldr \dst, =\imm
+ .else
+ movw \dst, #:lower16:\imm
+ movt \dst, #:upper16:\imm
+ .endif
+ .endm
+
+ /*
+ * adr_l - adr pseudo-op with unlimited range
+ *
+ * @dst: destination register
+ * @sym: name of the symbol
+ * @cond: conditional opcode suffix
+ */
+ .macro adr_l, dst:req, sym:req, cond
+ __adldst_l add, \dst, \sym, \dst, \cond
+ .endm
+
+ /*
+ * ldr_l - ldr <literal> pseudo-op with unlimited range
+ *
+ * @dst: destination register
+ * @sym: name of the symbol
+ * @cond: conditional opcode suffix
+ */
+ .macro ldr_l, dst:req, sym:req, cond
+ __adldst_l ldr, \dst, \sym, \dst, \cond
+ .endm
+
+ /*
+ * str_l - str <literal> pseudo-op with unlimited range
+ *
+ * @src: source register
+ * @sym: name of the symbol
+ * @tmp: mandatory scratch register
+ * @cond: conditional opcode suffix
+ */
+ .macro str_l, src:req, sym:req, tmp:req, cond
+ __adldst_l str, \src, \sym, \tmp, \cond
+ .endm
+
#endif /* __ASM_ASSEMBLER_H__ */
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 75bb2c5..455eb19 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -15,8 +15,6 @@
#include <asm/barrier.h>
#include <asm/cmpxchg.h>
-#define ATOMIC_INIT(i) { (i) }
-
#ifdef __KERNEL__
/*
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index deef4d0..673c7dd 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -82,7 +82,8 @@
struct pt_regs *),
int sig, int code, const char *name);
-extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
+extern asmlinkage void c_backtrace(unsigned long fp, int pmode,
+ const char *loglvl);
struct mm_struct;
void show_pte(const char *lvl, struct mm_struct *mm, unsigned long addr);
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 1d65ed3..e3ea345 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -24,6 +24,6 @@
#define ARCH_SLAB_MINALIGN 8
#endif
-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
+#define __read_mostly __section(".data..read_mostly")
#endif
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 7114b9a..2e24e76 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -258,11 +258,11 @@
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
/*
- * flush_cache_user_range is used when we want to ensure that the
+ * flush_icache_user_range is used when we want to ensure that the
* Harvard caches are synchronised for the user space address range.
* This is used for the ARM private sys_cacheflush system call.
*/
-#define flush_cache_user_range(s,e) __cpuc_coherent_user_range(s,e)
+#define flush_icache_user_range(s,e) __cpuc_coherent_user_range(s,e)
/*
* Perform necessary cache operations to ensure that data previously
@@ -318,9 +318,6 @@
#define flush_dcache_mmap_lock(mapping) xa_lock_irq(&mapping->i_pages)
#define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&mapping->i_pages)
-#define flush_icache_user_range(vma,page,addr,len) \
- flush_dcache_page(page)
-
/*
* We don't appear to need to do anything here. In fact, if we did, we'd
* duplicate cache flushing elsewhere performed by flush_dcache_page().
diff --git a/arch/arm/include/asm/checksum.h b/arch/arm/include/asm/checksum.h
index 20043e0..f0f54ae 100644
--- a/arch/arm/include/asm/checksum.h
+++ b/arch/arm/include/asm/checksum.h
@@ -35,10 +35,21 @@
*/
__wsum
-csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum);
+csum_partial_copy_nocheck(const void *src, void *dst, int len);
__wsum
-csum_partial_copy_from_user(const void __user *src, void *dst, int len, __wsum sum, int *err_ptr);
+csum_partial_copy_from_user(const void __user *src, void *dst, int len);
+
+#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
+#define _HAVE_ARCH_CSUM_AND_COPY
+static inline
+__wsum csum_and_copy_from_user(const void __user *src, void *dst, int len)
+{
+ if (!access_ok(src, len))
+ return 0;
+
+ return csum_partial_copy_from_user(src, dst, len);
+}
/*
* Fold a partial checksum without adding pseudo headers
diff --git a/arch/arm/include/asm/clocksource.h b/arch/arm/include/asm/clocksource.h
index afb7a59..13651c7 100644
--- a/arch/arm/include/asm/clocksource.h
+++ b/arch/arm/include/asm/clocksource.h
@@ -1,17 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_CLOCKSOURCE_H
#define _ASM_CLOCKSOURCE_H
-enum vdso_arch_clockmode {
- /* vdso clocksource not usable */
- VDSO_CLOCKMODE_NONE,
- /* vdso clocksource usable */
- VDSO_CLOCKMODE_ARCHTIMER,
- VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT = VDSO_CLOCKMODE_ARCHTIMER,
-};
+#include <asm/vdso/clocksource.h>
-struct arch_clocksource_data {
- /* Usable for direct VDSO access? */
- enum vdso_arch_clockmode clock_mode;
-};
-
-#endif
+#endif /* _ASM_CLOCKSOURCE_H */
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index d2453e2..a54230e 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -50,25 +50,7 @@
#ifdef CONFIG_CPU_CP15
-#define __ACCESS_CP15(CRn, Op1, CRm, Op2) \
- "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
-#define __ACCESS_CP15_64(Op1, CRm) \
- "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
-
-#define __read_sysreg(r, w, c, t) ({ \
- t __val; \
- asm volatile(r " " c : "=r" (__val)); \
- __val; \
-})
-#define read_sysreg(...) __read_sysreg(__VA_ARGS__)
-
-#define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v)))
-#define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__)
-
-#define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
-#define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
-
-#define CNTVCT __ACCESS_CP15_64(1, c14)
+#include <asm/vdso/cp15.h>
extern unsigned long cr_alignment; /* defined in entry-armv.S */
diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h
index 6b2ff72..bc4ffa7 100644
--- a/arch/arm/include/asm/cpuidle.h
+++ b/arch/arm/include/asm/cpuidle.h
@@ -7,9 +7,11 @@
#ifdef CONFIG_CPU_IDLE
extern int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
+#define __cpuidle_method_section __used __section("__cpuidle_method_of_table")
#else
static inline int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index) { return -ENODEV; }
+#define __cpuidle_method_section __maybe_unused /* drop silently */
#endif
/* Common ARM WFI state */
@@ -42,8 +44,7 @@
#define CPUIDLE_METHOD_OF_DECLARE(name, _method, _ops) \
static const struct of_cpuidle_method __cpuidle_method_of_table_##name \
- __used __section(__cpuidle_method_of_table) \
- = { .method = _method, .ops = _ops }
+ __cpuidle_method_section = { .method = _method, .ops = _ops }
extern int arm_cpuidle_suspend(int index);
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index c675bc0..be666f5 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -9,9 +9,6 @@
#ifdef CONFIG_DMABOUNCE
struct dmabounce_device_info *dmabounce;
#endif
-#ifdef CONFIG_IOMMU_API
- void *iommu; /* private IOMMU data */
-#endif
#ifdef CONFIG_ARM_DMA_USE_IOMMU
struct dma_iommu_mapping *mapping;
#endif
diff --git a/arch/arm/include/asm/dma-contiguous.h b/arch/arm/include/asm/dma-contiguous.h
deleted file mode 100644
index d785187..0000000
--- a/arch/arm/include/asm/dma-contiguous.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef ASMARM_DMA_CONTIGUOUS_H
-#define ASMARM_DMA_CONTIGUOUS_H
-
-#ifdef __KERNEL__
-#ifdef CONFIG_DMA_CMA
-
-#include <linux/types.h>
-
-void dma_contiguous_early_fixup(phys_addr_t base, unsigned long size);
-
-#endif
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/dma-direct.h b/arch/arm/include/asm/dma-direct.h
index b67e5fc..77fcb7e 100644
--- a/arch/arm/include/asm/dma-direct.h
+++ b/arch/arm/include/asm/dma-direct.h
@@ -2,35 +2,47 @@
#ifndef ASM_ARM_DMA_DIRECT_H
#define ASM_ARM_DMA_DIRECT_H 1
-static inline dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
+#include <asm/memory.h>
+
+/*
+ * dma_to_pfn/pfn_to_dma/virt_to_dma are architecture private
+ * functions used internally by the DMA-mapping API to provide DMA
+ * addresses. They must not be used by drivers.
+ */
+static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
+{
+ if (dev && dev->dma_range_map)
+ pfn = PFN_DOWN(translate_phys_to_dma(dev, PFN_PHYS(pfn)));
+ return (dma_addr_t)__pfn_to_bus(pfn);
+}
+
+static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
+{
+ unsigned long pfn = __bus_to_pfn(addr);
+
+ if (dev && dev->dma_range_map)
+ pfn = PFN_DOWN(translate_dma_to_phys(dev, PFN_PHYS(pfn)));
+ return pfn;
+}
+
+static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
+{
+ if (dev)
+ return pfn_to_dma(dev, virt_to_pfn(addr));
+
+ return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
+}
+
+static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
{
unsigned int offset = paddr & ~PAGE_MASK;
return pfn_to_dma(dev, __phys_to_pfn(paddr)) + offset;
}
-static inline phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dev_addr)
+static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr)
{
unsigned int offset = dev_addr & ~PAGE_MASK;
return __pfn_to_phys(dma_to_pfn(dev, dev_addr)) + offset;
}
-static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
-{
- u64 limit, mask;
-
- if (!dev->dma_mask)
- return 0;
-
- mask = *dev->dma_mask;
-
- limit = (mask + 1) & ~mask;
- if (limit && size > limit)
- return 0;
-
- if ((addr | (addr + size - 1)) & ~mask)
- return 0;
-
- return 1;
-}
-
#endif /* ASM_ARM_DMA_DIRECT_H */
diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h
index 772f48e..fe9ef6f 100644
--- a/arch/arm/include/asm/dma-iommu.h
+++ b/arch/arm/include/asm/dma-iommu.h
@@ -6,7 +6,6 @@
#include <linux/mm_types.h>
#include <linux/scatterlist.h>
-#include <linux/dma-debug.h>
#include <linux/kref.h>
struct dma_iommu_mapping {
@@ -33,7 +32,5 @@
struct dma_iommu_mapping *mapping);
void arm_iommu_detach_device(struct device *dev);
-int arm_dma_supported(struct device *dev, u64 mask);
-
#endif /* __KERNEL__ */
#endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index bdd80dd..7708224 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -6,9 +6,6 @@
#include <linux/mm_types.h>
#include <linux/scatterlist.h>
-#include <linux/dma-debug.h>
-
-#include <asm/memory.h>
#include <xen/xen.h>
#include <asm/xen/hypervisor.h>
@@ -23,74 +20,6 @@
return NULL;
}
-#ifdef __arch_page_to_dma
-#error Please update to __arch_pfn_to_dma
-#endif
-
-/*
- * dma_to_pfn/pfn_to_dma/dma_to_virt/virt_to_dma are architecture private
- * functions used internally by the DMA-mapping API to provide DMA
- * addresses. They must not be used by drivers.
- */
-#ifndef __arch_pfn_to_dma
-static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
-{
- if (dev)
- pfn -= dev->dma_pfn_offset;
- return (dma_addr_t)__pfn_to_bus(pfn);
-}
-
-static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
-{
- unsigned long pfn = __bus_to_pfn(addr);
-
- if (dev)
- pfn += dev->dma_pfn_offset;
-
- return pfn;
-}
-
-static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
-{
- if (dev) {
- unsigned long pfn = dma_to_pfn(dev, addr);
-
- return phys_to_virt(__pfn_to_phys(pfn));
- }
-
- return (void *)__bus_to_virt((unsigned long)addr);
-}
-
-static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
-{
- if (dev)
- return pfn_to_dma(dev, virt_to_pfn(addr));
-
- return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
-}
-
-#else
-static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
-{
- return __arch_pfn_to_dma(dev, pfn);
-}
-
-static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
-{
- return __arch_dma_to_pfn(dev, addr);
-}
-
-static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
-{
- return __arch_dma_to_virt(dev, addr);
-}
-
-static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
-{
- return __arch_virt_to_dma(dev, addr);
-}
-#endif
-
/**
* arm_dma_alloc - allocate consistent memory for DMA
* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
diff --git a/arch/arm/include/asm/efi.h b/arch/arm/include/asm/efi.h
index 7667826..3ee4f43 100644
--- a/arch/arm/include/asm/efi.h
+++ b/arch/arm/include/asm/efi.h
@@ -13,7 +13,6 @@
#include <asm/highmem.h>
#include <asm/mach/map.h>
#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#ifdef CONFIG_EFI
@@ -50,19 +49,8 @@
/* arch specific definitions used by the stub code */
-#define efi_call_early(f, ...) sys_table_arg->boottime->f(__VA_ARGS__)
-#define __efi_call_early(f, ...) f(__VA_ARGS__)
-#define efi_call_runtime(f, ...) sys_table_arg->runtime->f(__VA_ARGS__)
-#define efi_is_64bit() (false)
-
-#define efi_table_attr(table, attr, instance) \
- ((table##_t *)instance)->attr
-
-#define efi_call_proto(protocol, f, instance, ...) \
- ((protocol##_t *)instance)->f(instance, ##__VA_ARGS__)
-
-struct screen_info *alloc_screen_info(efi_system_table_t *sys_table_arg);
-void free_screen_info(efi_system_table_t *sys_table, struct screen_info *si);
+struct screen_info *alloc_screen_info(void);
+void free_screen_info(struct screen_info *si);
static inline void efifb_setup_from_dmi(struct screen_info *si, const char *opt)
{
@@ -78,25 +66,31 @@
#define MAX_UNCOMP_KERNEL_SIZE SZ_32M
/*
- * The kernel zImage should preferably be located between 32 MB and 128 MB
- * from the base of DRAM. The min address leaves space for a maximal size
- * uncompressed image, and the max address is due to how the zImage decompressor
- * picks a destination address.
+ * phys-to-virt patching requires that the physical to virtual offset fits
+ * into the immediate field of an add/sub instruction, which comes down to the
+ * 24 least significant bits being zero, and so the offset should be a multiple
+ * of 16 MB. Since PAGE_OFFSET itself is a multiple of 16 MB, the physical
+ * base should be aligned to 16 MB as well.
*/
-#define ZIMAGE_OFFSET_LIMIT SZ_128M
-#define MIN_ZIMAGE_OFFSET MAX_UNCOMP_KERNEL_SIZE
+#define EFI_PHYS_ALIGN SZ_16M
-/* on ARM, the FDT should be located in the first 128 MB of RAM */
-static inline unsigned long efi_get_max_fdt_addr(unsigned long dram_base)
+/* on ARM, the FDT should be located in a lowmem region */
+static inline unsigned long efi_get_max_fdt_addr(unsigned long image_addr)
{
- return dram_base + ZIMAGE_OFFSET_LIMIT;
+ return round_down(image_addr, EFI_PHYS_ALIGN) + SZ_512M;
}
/* on ARM, the initrd should be loaded in a lowmem region */
-static inline unsigned long efi_get_max_initrd_addr(unsigned long dram_base,
- unsigned long image_addr)
+static inline unsigned long efi_get_max_initrd_addr(unsigned long image_addr)
{
- return dram_base + SZ_512M;
+ return round_down(image_addr, EFI_PHYS_ALIGN) + SZ_512M;
}
+struct efi_arm_entry_state {
+ u32 cpsr_before_ebs;
+ u32 sctlr_before_ebs;
+ u32 cpsr_after_ebs;
+ u32 sctlr_after_ebs;
+};
+
#endif /* _ASM_ARM_EFI_H */
diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h
index 763c3f6..9575b40 100644
--- a/arch/arm/include/asm/fixmap.h
+++ b/arch/arm/include/asm/fixmap.h
@@ -6,8 +6,8 @@
#define FIXADDR_END 0xfff00000UL
#define FIXADDR_TOP (FIXADDR_END - PAGE_SIZE)
+#include <linux/pgtable.h>
#include <asm/kmap_types.h>
-#include <asm/pgtable.h>
enum fixed_addresses {
FIX_EARLYCON_MEM_BASE,
diff --git a/arch/arm/include/asm/floppy.h b/arch/arm/include/asm/floppy.h
index f4fe4d0..e1cb04e 100644
--- a/arch/arm/include/asm/floppy.h
+++ b/arch/arm/include/asm/floppy.h
@@ -8,19 +8,21 @@
*/
#ifndef __ASM_ARM_FLOPPY_H
#define __ASM_ARM_FLOPPY_H
-#if 0
-#include <mach/floppy.h>
-#endif
-#define fd_outb(val,port) \
- do { \
- if ((port) == (u32)FD_DOR) \
- fd_setdor((val)); \
- else \
- outb((val),(port)); \
+#define fd_outb(val, base, reg) \
+ do { \
+ int new_val = (val); \
+ if ((reg) == FD_DOR) { \
+ if (new_val & 0xf0) \
+ new_val = (new_val & 0x0c) | \
+ floppy_selects[new_val & 3]; \
+ else \
+ new_val &= 0x0c; \
+ } \
+ outb(new_val, (base) + (reg)); \
} while(0)
-#define fd_inb(port) inb((port))
+#define fd_inb(base, reg) inb((base) + (reg))
#define fd_request_irq() request_irq(IRQ_FLOPPYDISK,floppy_interrupt,\
0,"floppy",NULL)
#define fd_free_irq() free_irq(IRQ_FLOPPYDISK,NULL)
@@ -53,69 +55,7 @@
* to a non-zero track, and then restoring it to track 0. If an error occurs,
* then there is no floppy drive present. [to be put back in again]
*/
-static unsigned char floppy_selects[2][4] =
-{
- { 0x10, 0x21, 0x23, 0x33 },
- { 0x10, 0x21, 0x23, 0x33 }
-};
-
-#define fd_setdor(dor) \
-do { \
- int new_dor = (dor); \
- if (new_dor & 0xf0) \
- new_dor = (new_dor & 0x0c) | floppy_selects[fdc][new_dor & 3]; \
- else \
- new_dor &= 0x0c; \
- outb(new_dor, FD_DOR); \
-} while (0)
-
-/*
- * Someday, we'll automatically detect which drives are present...
- */
-static inline void fd_scandrives (void)
-{
-#if 0
- int floppy, drive_count;
-
- fd_disable_irq();
- raw_cmd = &default_raw_cmd;
- raw_cmd->flags = FD_RAW_SPIN | FD_RAW_NEED_SEEK;
- raw_cmd->track = 0;
- raw_cmd->rate = ?;
- drive_count = 0;
- for (floppy = 0; floppy < 4; floppy ++) {
- current_drive = drive_count;
- /*
- * Turn on floppy motor
- */
- if (start_motor(redo_fd_request))
- continue;
- /*
- * Set up FDC
- */
- fdc_specify();
- /*
- * Tell FDC to recalibrate
- */
- output_byte(FD_RECALIBRATE);
- LAST_OUT(UNIT(floppy));
- /* wait for command to complete */
- if (!successful) {
- int i;
- for (i = drive_count; i < 3; i--)
- floppy_selects[fdc][i] = floppy_selects[fdc][i + 1];
- floppy_selects[fdc][3] = 0;
- floppy -= 1;
- } else
- drive_count++;
- }
-#else
- floppy_selects[0][0] = 0x10;
- floppy_selects[0][1] = 0x21;
- floppy_selects[0][2] = 0x23;
- floppy_selects[0][3] = 0x33;
-#endif
-}
+static unsigned char floppy_selects[4] = { 0x10, 0x21, 0x23, 0x33 };
#define FDC1 (0x3f0)
@@ -135,9 +75,7 @@
*/
static void driveswap(int *ints, int dummy, int dummy2)
{
- floppy_selects[0][0] ^= floppy_selects[0][1];
- floppy_selects[0][1] ^= floppy_selects[0][0];
- floppy_selects[0][0] ^= floppy_selects[0][1];
+ swap(floppy_selects[0], floppy_selects[1]);
}
#define EXTRA_FLOPPY_PARAMS ,{ "driveswap", &driveswap, NULL, 0, 0 }
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index 18b0197..a4dbac0 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -11,11 +11,13 @@
#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
#ifndef __ASSEMBLY__
-extern void mcount(void);
extern void __gnu_mcount_nc(void);
#ifdef CONFIG_DYNAMIC_FTRACE
struct dyn_arch_ftrace {
+#ifdef CONFIG_ARM_MODULE_PLTS
+ struct module *mod;
+#endif
};
static inline unsigned long ftrace_call_adjust(unsigned long addr)
@@ -23,9 +25,6 @@
/* With Thumb-2, the recorded addresses have the lsb set */
return addr & ~1;
}
-
-extern void ftrace_caller_old(void);
-extern void ftrace_call_old(void);
#endif
#endif
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index fdc4ae3..a915188 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -134,10 +134,12 @@
{
int oldval = 0, ret, tmp;
+ if (!access_ok(uaddr, sizeof(u32)))
+ return -EFAULT;
+
#ifndef CONFIG_SMP
preempt_disable();
#endif
- pagefault_disable();
switch (op) {
case FUTEX_OP_SET:
@@ -159,7 +161,6 @@
ret = -ENOSYS;
}
- pagefault_enable();
#ifndef CONFIG_SMP
preempt_enable();
#endif
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 7a88f16..b95848e 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -6,29 +6,12 @@
#include <linux/threads.h>
#include <asm/irq.h>
-/* number of IPIS _not_ including IPI_CPU_BACKTRACE */
-#define NR_IPI 7
-
typedef struct {
unsigned int __softirq_pending;
-#ifdef CONFIG_SMP
- unsigned int ipi_irqs[NR_IPI];
-#endif
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
-#define __inc_irq_stat(cpu, member) __IRQ_STAT(cpu, member)++
-#define __get_irq_stat(cpu, member) __IRQ_STAT(cpu, member)
-
-#ifdef CONFIG_SMP
-u64 smp_irq_stat_cpu(unsigned int cpu);
-#else
-#define smp_irq_stat_cpu(cpu) 0
-#endif
-
-#define arch_irq_stat_cpu smp_irq_stat_cpu
-
#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
#endif /* __ASM_HARDIRQ_H */
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 32edfad..a6d4ee8 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -118,6 +118,8 @@
#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
+#define L310_AUX_CTRL_FWA_SHIFT 23
+#define L310_AUX_CTRL_FWA_MASK (3 << 23)
#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
deleted file mode 100644
index e175c23..0000000
--- a/arch/arm/include/asm/hardware/it8152.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/include/arm/hardware/it8152.h
- *
- * Copyright Compulab Ltd., 2006,2007
- * Mike Rapoport <mike@compulab.co.il>
- *
- * ITE 8152 companion chip register definitions
- */
-
-#ifndef __ASM_HARDWARE_IT8152_H
-#define __ASM_HARDWARE_IT8152_H
-
-#include <mach/irqs.h>
-
-extern void __iomem *it8152_base_address;
-
-#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
-#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)
-
-#define __REG_IT8152(x) (it8152_base_address + (x))
-
-#define IT8152_PCI_CFG_ADDR __REG_IT8152(0x3f00800)
-#define IT8152_PCI_CFG_DATA __REG_IT8152(0x3f00804)
-
-#define IT8152_INTC_LDCNIRR __REG_IT8152(0x3f00300)
-#define IT8152_INTC_LDPNIRR __REG_IT8152(0x3f00304)
-#define IT8152_INTC_LDCNIMR __REG_IT8152(0x3f00308)
-#define IT8152_INTC_LDPNIMR __REG_IT8152(0x3f0030C)
-#define IT8152_INTC_LDNITR __REG_IT8152(0x3f00310)
-#define IT8152_INTC_LDNIAR __REG_IT8152(0x3f00314)
-#define IT8152_INTC_LPCNIRR __REG_IT8152(0x3f00320)
-#define IT8152_INTC_LPPNIRR __REG_IT8152(0x3f00324)
-#define IT8152_INTC_LPCNIMR __REG_IT8152(0x3f00328)
-#define IT8152_INTC_LPPNIMR __REG_IT8152(0x3f0032C)
-#define IT8152_INTC_LPNITR __REG_IT8152(0x3f00330)
-#define IT8152_INTC_LPNIAR __REG_IT8152(0x3f00334)
-#define IT8152_INTC_PDCNIRR __REG_IT8152(0x3f00340)
-#define IT8152_INTC_PDPNIRR __REG_IT8152(0x3f00344)
-#define IT8152_INTC_PDCNIMR __REG_IT8152(0x3f00348)
-#define IT8152_INTC_PDPNIMR __REG_IT8152(0x3f0034C)
-#define IT8152_INTC_PDNITR __REG_IT8152(0x3f00350)
-#define IT8152_INTC_PDNIAR __REG_IT8152(0x3f00354)
-#define IT8152_INTC_INTC_TYPER __REG_IT8152(0x3f003FC)
-
-#define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500)
-
-/*
- Interrupt controller per register summary:
- ---------------------------------------
- LCDNIRR:
- IT8152_LD_IRQ(8) PCICLK stop
- IT8152_LD_IRQ(7) MCLK ready
- IT8152_LD_IRQ(6) s/w
- IT8152_LD_IRQ(5) UART
- IT8152_LD_IRQ(4) GPIO
- IT8152_LD_IRQ(3) TIMER 4
- IT8152_LD_IRQ(2) TIMER 3
- IT8152_LD_IRQ(1) TIMER 2
- IT8152_LD_IRQ(0) TIMER 1
-
- LPCNIRR:
- IT8152_LP_IRQ(x) serial IRQ x
-
- PCIDNIRR:
- IT8152_PD_IRQ(14) PCISERR
- IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR)
- IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR)
- IT8152_PD_IRQ(11) PCI INTD
- IT8152_PD_IRQ(10) PCI INTC
- IT8152_PD_IRQ(9) PCI INTB
- IT8152_PD_IRQ(8) PCI INTA
- IT8152_PD_IRQ(7) serial INTD
- IT8152_PD_IRQ(6) serial INTC
- IT8152_PD_IRQ(5) serial INTB
- IT8152_PD_IRQ(4) serial INTA
- IT8152_PD_IRQ(3) serial IRQ IOCHK (IOCHKR)
- IT8152_PD_IRQ(2) chaining DMA (CDMAR)
- IT8152_PD_IRQ(1) USB (USBR)
- IT8152_PD_IRQ(0) Audio controller (ACR)
- */
-#define IT8152_IRQ(x) (IRQ_BOARD_START + (x))
-#define IT8152_LAST_IRQ (IRQ_BOARD_START + 40)
-
-/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
-#define IT8152_LD_IRQ_COUNT 9
-#define IT8152_LP_IRQ_COUNT 16
-#define IT8152_PD_IRQ_COUNT 15
-
-/* Priorities: */
-#define IT8152_PD_IRQ(i) IT8152_IRQ(i)
-#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT)
-#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT)
-
-/* frequently used interrupts */
-#define IT8152_PCISERR IT8152_PD_IRQ(14)
-#define IT8152_H2PTADR IT8152_PD_IRQ(13)
-#define IT8152_H2PMAR IT8152_PD_IRQ(12)
-#define IT8152_PCI_INTD IT8152_PD_IRQ(11)
-#define IT8152_PCI_INTC IT8152_PD_IRQ(10)
-#define IT8152_PCI_INTB IT8152_PD_IRQ(9)
-#define IT8152_PCI_INTA IT8152_PD_IRQ(8)
-#define IT8152_CDMA_INT IT8152_PD_IRQ(2)
-#define IT8152_USB_INT IT8152_PD_IRQ(1)
-#define IT8152_AUDIO_INT IT8152_PD_IRQ(0)
-
-struct pci_dev;
-struct pci_sys_data;
-
-extern void it8152_irq_demux(struct irq_desc *desc);
-extern void it8152_init_irq(void);
-extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
-extern struct pci_ops it8152_ops;
-
-#endif /* __ASM_HARDWARE_IT8152_H */
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index eb4e420..31811be 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -10,8 +10,6 @@
#define PKMAP_NR(virt) (((virt) - PKMAP_BASE) >> PAGE_SHIFT)
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-#define kmap_prot PAGE_KERNEL
-
#define flush_cache_kmaps() \
do { \
if (cache_is_vivt()) \
@@ -20,9 +18,6 @@
extern pte_t *pkmap_page_table;
-extern void *kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-
/*
* The reason for kmap_high_get() is to ensure that the currently kmap'd
* page usage count does not decrease to zero while we're using its
@@ -63,10 +58,6 @@
* when CONFIG_HIGHMEM is not set.
*/
#ifdef CONFIG_HIGHMEM
-extern void *kmap(struct page *page);
-extern void kunmap(struct page *page);
-extern void *kmap_atomic(struct page *page);
-extern void __kunmap_atomic(void *kvaddr);
extern void *kmap_atomic_pfn(unsigned long pfn);
#endif
diff --git a/arch/arm/include/asm/hugetlb.h b/arch/arm/include/asm/hugetlb.h
index 318dcf5..d02d6ca 100644
--- a/arch/arm/include/asm/hugetlb.h
+++ b/arch/arm/include/asm/hugetlb.h
@@ -14,15 +14,10 @@
#include <asm/hugetlb-3level.h>
#include <asm-generic/hugetlb.h>
-static inline int is_hugepage_only_range(struct mm_struct *mm,
- unsigned long addr, unsigned long len)
-{
- return 0;
-}
-
static inline void arch_clear_hugepage_flags(struct page *page)
{
clear_bit(PG_dcache_clean, &page->flags);
}
+#define arch_clear_hugepage_flags arch_clear_hugepage_flags
#endif /* _ASM_ARM_HUGETLB_H */
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index ac54c06..62358d3 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -53,6 +53,9 @@
#define ARM_DEBUG_ARCH_V7_MM 4
#define ARM_DEBUG_ARCH_V7_1 5
#define ARM_DEBUG_ARCH_V8 6
+#define ARM_DEBUG_ARCH_V8_1 7
+#define ARM_DEBUG_ARCH_V8_2 8
+#define ARM_DEBUG_ARCH_V8_4 9
/* Breakpoint */
#define ARM_BREAKPOINT_EXECUTE 0
diff --git a/arch/arm/include/asm/idmap.h b/arch/arm/include/asm/idmap.h
index 73ba956..baebb67 100644
--- a/arch/arm/include/asm/idmap.h
+++ b/arch/arm/include/asm/idmap.h
@@ -3,10 +3,10 @@
#define __ASM_IDMAP_H
#include <linux/compiler.h>
-#include <asm/pgtable.h>
+#include <linux/pgtable.h>
/* Tag a function as requiring to be executed via an identity mapping. */
-#define __idmap __section(.idmap.text) noinline notrace
+#define __idmap __section(".idmap.text") noinline notrace
extern pgd_t *idmap_pgd;
diff --git a/arch/arm/include/asm/insn.h b/arch/arm/include/asm/insn.h
index f20e08a..5475cbf 100644
--- a/arch/arm/include/asm/insn.h
+++ b/arch/arm/include/asm/insn.h
@@ -13,18 +13,18 @@
}
unsigned long
-__arm_gen_branch(unsigned long pc, unsigned long addr, bool link);
+__arm_gen_branch(unsigned long pc, unsigned long addr, bool link, bool warn);
static inline unsigned long
arm_gen_branch(unsigned long pc, unsigned long addr)
{
- return __arm_gen_branch(pc, addr, false);
+ return __arm_gen_branch(pc, addr, false, true);
}
static inline unsigned long
-arm_gen_branch_link(unsigned long pc, unsigned long addr)
+arm_gen_branch_link(unsigned long pc, unsigned long addr, bool warn)
{
- return __arm_gen_branch(pc, addr, true);
+ return __arm_gen_branch(pc, addr, true, warn);
}
#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 7a0596f..ab2b654 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -356,7 +356,6 @@
*
* Function Memory type Cacheability Cache hint
* ioremap() Device n/a n/a
- * ioremap_nocache() Device n/a n/a
* ioremap_cache() Normal Writeback Read allocate
* ioremap_wc() Normal Non-cacheable n/a
* ioremap_wt() Normal Non-cacheable n/a
@@ -368,13 +367,6 @@
* - unaligned accesses are "unpredictable"
* - writes may be delayed before they hit the endpoint device
*
- * ioremap_nocache() is the same as ioremap() as there are too many device
- * drivers using this for device registers, and documentation which tells
- * people to use it for such for this to be any different. This is not a
- * safe fallback for memory-like mappings, or memory regions where the
- * compiler may generate unaligned accesses - eg, via inlining its own
- * memcpy.
- *
* All normal memory mappings have the following properties:
* - reads can be repeated with no side effects
* - repeated reads return the last value written
@@ -392,7 +384,6 @@
*/
void __iomem *ioremap(resource_size_t res_cookie, size_t size);
#define ioremap ioremap
-#define ioremap_nocache ioremap
/*
* Do not use ioremap_cache for mapping memory. Use memremap instead.
@@ -400,12 +391,6 @@
void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
#define ioremap_cache ioremap_cache
-/*
- * Do not use ioremap_cached in new code. Provided for the benefit of
- * the pxa2xx-flash MTD driver only.
- */
-void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size);
-
void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
#define ioremap_wc ioremap_wc
#define ioremap_wt ioremap_wc
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
deleted file mode 100644
index 0125aa0..0000000
--- a/arch/arm/include/asm/kvm_arm.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#ifndef __ARM_KVM_ARM_H__
-#define __ARM_KVM_ARM_H__
-
-#include <linux/const.h>
-#include <linux/types.h>
-
-/* Hyp Configuration Register (HCR) bits */
-#define HCR_TGE (1 << 27)
-#define HCR_TVM (1 << 26)
-#define HCR_TTLB (1 << 25)
-#define HCR_TPU (1 << 24)
-#define HCR_TPC (1 << 23)
-#define HCR_TSW (1 << 22)
-#define HCR_TAC (1 << 21)
-#define HCR_TIDCP (1 << 20)
-#define HCR_TSC (1 << 19)
-#define HCR_TID3 (1 << 18)
-#define HCR_TID2 (1 << 17)
-#define HCR_TID1 (1 << 16)
-#define HCR_TID0 (1 << 15)
-#define HCR_TWE (1 << 14)
-#define HCR_TWI (1 << 13)
-#define HCR_DC (1 << 12)
-#define HCR_BSU (3 << 10)
-#define HCR_BSU_IS (1 << 10)
-#define HCR_FB (1 << 9)
-#define HCR_VA (1 << 8)
-#define HCR_VI (1 << 7)
-#define HCR_VF (1 << 6)
-#define HCR_AMO (1 << 5)
-#define HCR_IMO (1 << 4)
-#define HCR_FMO (1 << 3)
-#define HCR_PTW (1 << 2)
-#define HCR_SWIO (1 << 1)
-#define HCR_VM 1
-
-/*
- * The bits we set in HCR:
- * TAC: Trap ACTLR
- * TSC: Trap SMC
- * TVM: Trap VM ops (until MMU and caches are on)
- * TSW: Trap cache operations by set/way
- * TWI: Trap WFI
- * TWE: Trap WFE
- * TIDCP: Trap L2CTLR/L2ECTLR
- * BSU_IS: Upgrade barriers to the inner shareable domain
- * FB: Force broadcast of all maintainance operations
- * AMO: Override CPSR.A and enable signaling with VA
- * IMO: Override CPSR.I and enable signaling with VI
- * FMO: Override CPSR.F and enable signaling with VF
- * SWIO: Turn set/way invalidates into set/way clean+invalidate
- */
-#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
- HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
- HCR_TVM | HCR_TWE | HCR_SWIO | HCR_TIDCP)
-
-/* System Control Register (SCTLR) bits */
-#define SCTLR_TE (1 << 30)
-#define SCTLR_EE (1 << 25)
-#define SCTLR_V (1 << 13)
-
-/* Hyp System Control Register (HSCTLR) bits */
-#define HSCTLR_TE (1 << 30)
-#define HSCTLR_EE (1 << 25)
-#define HSCTLR_FI (1 << 21)
-#define HSCTLR_WXN (1 << 19)
-#define HSCTLR_I (1 << 12)
-#define HSCTLR_C (1 << 2)
-#define HSCTLR_A (1 << 1)
-#define HSCTLR_M 1
-#define HSCTLR_MASK (HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \
- HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE)
-
-/* TTBCR and HTCR Registers bits */
-#define TTBCR_EAE (1 << 31)
-#define TTBCR_IMP (1 << 30)
-#define TTBCR_SH1 (3 << 28)
-#define TTBCR_ORGN1 (3 << 26)
-#define TTBCR_IRGN1 (3 << 24)
-#define TTBCR_EPD1 (1 << 23)
-#define TTBCR_A1 (1 << 22)
-#define TTBCR_T1SZ (7 << 16)
-#define TTBCR_SH0 (3 << 12)
-#define TTBCR_ORGN0 (3 << 10)
-#define TTBCR_IRGN0 (3 << 8)
-#define TTBCR_EPD0 (1 << 7)
-#define TTBCR_T0SZ (7 << 0)
-#define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0)
-
-/* Hyp System Trap Register */
-#define HSTR_T(x) (1 << x)
-#define HSTR_TTEE (1 << 16)
-#define HSTR_TJDBX (1 << 17)
-
-/* Hyp Coprocessor Trap Register */
-#define HCPTR_TCP(x) (1 << x)
-#define HCPTR_TCP_MASK (0x3fff)
-#define HCPTR_TASE (1 << 15)
-#define HCPTR_TTA (1 << 20)
-#define HCPTR_TCPAC (1 << 31)
-
-/* Hyp Debug Configuration Register bits */
-#define HDCR_TDRA (1 << 11)
-#define HDCR_TDOSA (1 << 10)
-#define HDCR_TDA (1 << 9)
-#define HDCR_TDE (1 << 8)
-#define HDCR_HPME (1 << 7)
-#define HDCR_TPM (1 << 6)
-#define HDCR_TPMCR (1 << 5)
-#define HDCR_HPMN_MASK (0x1F)
-
-/*
- * The architecture supports 40-bit IPA as input to the 2nd stage translations
- * and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address
- * space.
- */
-#define KVM_PHYS_SHIFT (40)
-
-#define PTRS_PER_S2_PGD (_AC(1, ULL) << (KVM_PHYS_SHIFT - 30))
-
-/* Virtualization Translation Control Register (VTCR) bits */
-#define VTCR_SH0 (3 << 12)
-#define VTCR_ORGN0 (3 << 10)
-#define VTCR_IRGN0 (3 << 8)
-#define VTCR_SL0 (3 << 6)
-#define VTCR_S (1 << 4)
-#define VTCR_T0SZ (0xf)
-#define VTCR_MASK (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \
- VTCR_S | VTCR_T0SZ)
-#define VTCR_HTCR_SH (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0)
-#define VTCR_SL_L2 (0 << 6) /* Starting-level: 2 */
-#define VTCR_SL_L1 (1 << 6) /* Starting-level: 1 */
-#define KVM_VTCR_SL0 VTCR_SL_L1
-/* stage-2 input address range defined as 2^(32-T0SZ) */
-#define KVM_T0SZ (32 - KVM_PHYS_SHIFT)
-#define KVM_VTCR_T0SZ (KVM_T0SZ & VTCR_T0SZ)
-#define KVM_VTCR_S ((KVM_VTCR_T0SZ << 1) & VTCR_S)
-
-/* Virtualization Translation Table Base Register (VTTBR) bits */
-#if KVM_VTCR_SL0 == VTCR_SL_L2 /* see ARM DDI 0406C: B4-1720 */
-#define VTTBR_X (14 - KVM_T0SZ)
-#else
-#define VTTBR_X (5 - KVM_T0SZ)
-#endif
-#define VTTBR_CNP_BIT _AC(1, UL)
-#define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_X)
-#define VTTBR_VMID_SHIFT _AC(48, ULL)
-#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
-
-/* Hyp Syndrome Register (HSR) bits */
-#define HSR_EC_SHIFT (26)
-#define HSR_EC (_AC(0x3f, UL) << HSR_EC_SHIFT)
-#define HSR_IL (_AC(1, UL) << 25)
-#define HSR_ISS (HSR_IL - 1)
-#define HSR_ISV_SHIFT (24)
-#define HSR_ISV (_AC(1, UL) << HSR_ISV_SHIFT)
-#define HSR_SRT_SHIFT (16)
-#define HSR_SRT_MASK (0xf << HSR_SRT_SHIFT)
-#define HSR_FSC (0x3f)
-#define HSR_FSC_TYPE (0x3c)
-#define HSR_SSE (1 << 21)
-#define HSR_WNR (1 << 6)
-#define HSR_CV_SHIFT (24)
-#define HSR_CV (_AC(1, UL) << HSR_CV_SHIFT)
-#define HSR_COND_SHIFT (20)
-#define HSR_COND (_AC(0xf, UL) << HSR_COND_SHIFT)
-
-#define FSC_FAULT (0x04)
-#define FSC_ACCESS (0x08)
-#define FSC_PERM (0x0c)
-#define FSC_SEA (0x10)
-#define FSC_SEA_TTW0 (0x14)
-#define FSC_SEA_TTW1 (0x15)
-#define FSC_SEA_TTW2 (0x16)
-#define FSC_SEA_TTW3 (0x17)
-#define FSC_SECC (0x18)
-#define FSC_SECC_TTW0 (0x1c)
-#define FSC_SECC_TTW1 (0x1d)
-#define FSC_SECC_TTW2 (0x1e)
-#define FSC_SECC_TTW3 (0x1f)
-
-/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
-#define HPFAR_MASK (~0xf)
-
-#define HSR_EC_UNKNOWN (0x00)
-#define HSR_EC_WFI (0x01)
-#define HSR_EC_CP15_32 (0x03)
-#define HSR_EC_CP15_64 (0x04)
-#define HSR_EC_CP14_MR (0x05)
-#define HSR_EC_CP14_LS (0x06)
-#define HSR_EC_CP_0_13 (0x07)
-#define HSR_EC_CP10_ID (0x08)
-#define HSR_EC_JAZELLE (0x09)
-#define HSR_EC_BXJ (0x0A)
-#define HSR_EC_CP14_64 (0x0C)
-#define HSR_EC_SVC_HYP (0x11)
-#define HSR_EC_HVC (0x12)
-#define HSR_EC_SMC (0x13)
-#define HSR_EC_IABT (0x20)
-#define HSR_EC_IABT_HYP (0x21)
-#define HSR_EC_DABT (0x24)
-#define HSR_EC_DABT_HYP (0x25)
-#define HSR_EC_MAX (0x3f)
-
-#define HSR_WFI_IS_WFE (_AC(1, UL) << 0)
-
-#define HSR_HVC_IMM_MASK ((_AC(1, UL) << 16) - 1)
-
-#define HSR_DABT_S1PTW (_AC(1, UL) << 7)
-#define HSR_DABT_CM (_AC(1, UL) << 8)
-
-#define kvm_arm_exception_type \
- {0, "RESET" }, \
- {1, "UNDEFINED" }, \
- {2, "SOFTWARE" }, \
- {3, "PREF_ABORT" }, \
- {4, "DATA_ABORT" }, \
- {5, "IRQ" }, \
- {6, "FIQ" }, \
- {7, "HVC" }
-
-#define HSRECN(x) { HSR_EC_##x, #x }
-
-#define kvm_arm_exception_class \
- HSRECN(UNKNOWN), HSRECN(WFI), HSRECN(CP15_32), HSRECN(CP15_64), \
- HSRECN(CP14_MR), HSRECN(CP14_LS), HSRECN(CP_0_13), HSRECN(CP10_ID), \
- HSRECN(JAZELLE), HSRECN(BXJ), HSRECN(CP14_64), HSRECN(SVC_HYP), \
- HSRECN(HVC), HSRECN(SMC), HSRECN(IABT), HSRECN(IABT_HYP), \
- HSRECN(DABT), HSRECN(DABT_HYP)
-
-
-#endif /* __ARM_KVM_ARM_H__ */
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
deleted file mode 100644
index 9d0b7e6..0000000
--- a/arch/arm/include/asm/kvm_asm.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#ifndef __ARM_KVM_ASM_H__
-#define __ARM_KVM_ASM_H__
-
-#include <asm/virt.h>
-
-#define ARM_EXIT_WITH_ABORT_BIT 31
-#define ARM_EXCEPTION_CODE(x) ((x) & ~(1U << ARM_EXIT_WITH_ABORT_BIT))
-#define ARM_EXCEPTION_IS_TRAP(x) \
- (ARM_EXCEPTION_CODE((x)) == ARM_EXCEPTION_PREF_ABORT || \
- ARM_EXCEPTION_CODE((x)) == ARM_EXCEPTION_DATA_ABORT || \
- ARM_EXCEPTION_CODE((x)) == ARM_EXCEPTION_HVC)
-#define ARM_ABORT_PENDING(x) !!((x) & (1U << ARM_EXIT_WITH_ABORT_BIT))
-
-#define ARM_EXCEPTION_RESET 0
-#define ARM_EXCEPTION_UNDEFINED 1
-#define ARM_EXCEPTION_SOFTWARE 2
-#define ARM_EXCEPTION_PREF_ABORT 3
-#define ARM_EXCEPTION_DATA_ABORT 4
-#define ARM_EXCEPTION_IRQ 5
-#define ARM_EXCEPTION_FIQ 6
-#define ARM_EXCEPTION_HVC 7
-#define ARM_EXCEPTION_HYP_GONE HVC_STUB_ERR
-/*
- * The rr_lo_hi macro swaps a pair of registers depending on
- * current endianness. It is used in conjunction with ldrd and strd
- * instructions that load/store a 64-bit value from/to memory to/from
- * a pair of registers which are used with the mrrc and mcrr instructions.
- * If used with the ldrd/strd instructions, the a1 parameter is the first
- * source/destination register and the a2 parameter is the second
- * source/destination register. Note that the ldrd/strd instructions
- * already swap the bytes within the words correctly according to the
- * endianness setting, but the order of the registers need to be effectively
- * swapped when used with the mrrc/mcrr instructions.
- */
-#ifdef CONFIG_CPU_ENDIAN_BE8
-#define rr_lo_hi(a1, a2) a2, a1
-#else
-#define rr_lo_hi(a1, a2) a1, a2
-#endif
-
-#define kvm_ksym_ref(kva) (kva)
-
-#ifndef __ASSEMBLY__
-struct kvm;
-struct kvm_vcpu;
-
-extern char __kvm_hyp_init[];
-extern char __kvm_hyp_init_end[];
-
-extern void __kvm_flush_vm_context(void);
-extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
-extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
-extern void __kvm_flush_cpu_context(struct kvm_vcpu *vcpu);
-
-extern void __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high);
-
-/* no VHE on 32-bit :( */
-static inline int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) { BUG(); return 0; }
-
-extern int __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu);
-
-extern void __init_stage2_translation(void);
-
-extern u64 __vgic_v3_get_ich_vtr_el2(void);
-extern u64 __vgic_v3_read_vmcr(void);
-extern void __vgic_v3_write_vmcr(u32 vmcr);
-extern void __vgic_v3_init_lrs(void);
-
-#endif
-
-#endif /* __ARM_KVM_ASM_H__ */
diff --git a/arch/arm/include/asm/kvm_coproc.h b/arch/arm/include/asm/kvm_coproc.h
deleted file mode 100644
index a238261..0000000
--- a/arch/arm/include/asm/kvm_coproc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 Rusty Russell IBM Corporation
- */
-
-#ifndef __ARM_KVM_COPROC_H__
-#define __ARM_KVM_COPROC_H__
-#include <linux/kvm_host.h>
-
-void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
-
-struct kvm_coproc_target_table {
- unsigned target;
- const struct coproc_reg *table;
- size_t num;
-};
-void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table);
-
-int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
-
-unsigned long kvm_arm_num_guest_msrs(struct kvm_vcpu *vcpu);
-int kvm_arm_copy_msrindices(struct kvm_vcpu *vcpu, u64 __user *uindices);
-void kvm_coproc_table_init(void);
-
-struct kvm_one_reg;
-int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
-int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
-int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
-unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
-#endif /* __ARM_KVM_COPROC_H__ */
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
deleted file mode 100644
index c1747fc..0000000
--- a/arch/arm/include/asm/kvm_emulate.h
+++ /dev/null
@@ -1,374 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#ifndef __ARM_KVM_EMULATE_H__
-#define __ARM_KVM_EMULATE_H__
-
-#include <linux/kvm_host.h>
-#include <asm/kvm_asm.h>
-#include <asm/kvm_mmio.h>
-#include <asm/kvm_arm.h>
-#include <asm/cputype.h>
-
-/* arm64 compatibility macros */
-#define PSR_AA32_MODE_FIQ FIQ_MODE
-#define PSR_AA32_MODE_SVC SVC_MODE
-#define PSR_AA32_MODE_ABT ABT_MODE
-#define PSR_AA32_MODE_UND UND_MODE
-#define PSR_AA32_T_BIT PSR_T_BIT
-#define PSR_AA32_F_BIT PSR_F_BIT
-#define PSR_AA32_I_BIT PSR_I_BIT
-#define PSR_AA32_A_BIT PSR_A_BIT
-#define PSR_AA32_E_BIT PSR_E_BIT
-#define PSR_AA32_IT_MASK PSR_IT_MASK
-#define PSR_AA32_GE_MASK 0x000f0000
-#define PSR_AA32_DIT_BIT 0x00200000
-#define PSR_AA32_PAN_BIT 0x00400000
-#define PSR_AA32_SSBS_BIT 0x00800000
-#define PSR_AA32_Q_BIT PSR_Q_BIT
-#define PSR_AA32_V_BIT PSR_V_BIT
-#define PSR_AA32_C_BIT PSR_C_BIT
-#define PSR_AA32_Z_BIT PSR_Z_BIT
-#define PSR_AA32_N_BIT PSR_N_BIT
-
-unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
-
-static inline unsigned long *vcpu_reg32(struct kvm_vcpu *vcpu, u8 reg_num)
-{
- return vcpu_reg(vcpu, reg_num);
-}
-
-unsigned long *__vcpu_spsr(struct kvm_vcpu *vcpu);
-
-static inline unsigned long vpcu_read_spsr(struct kvm_vcpu *vcpu)
-{
- return *__vcpu_spsr(vcpu);
-}
-
-static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
-{
- *__vcpu_spsr(vcpu) = v;
-}
-
-static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
-{
- return spsr;
-}
-
-static inline unsigned long vcpu_get_reg(struct kvm_vcpu *vcpu,
- u8 reg_num)
-{
- return *vcpu_reg(vcpu, reg_num);
-}
-
-static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
- unsigned long val)
-{
- *vcpu_reg(vcpu, reg_num) = val;
-}
-
-bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
-void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
-void kvm_inject_undef32(struct kvm_vcpu *vcpu);
-void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
-void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
-void kvm_inject_vabt(struct kvm_vcpu *vcpu);
-
-static inline void kvm_inject_undefined(struct kvm_vcpu *vcpu)
-{
- kvm_inject_undef32(vcpu);
-}
-
-static inline void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
-{
- kvm_inject_dabt32(vcpu, addr);
-}
-
-static inline void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
-{
- kvm_inject_pabt32(vcpu, addr);
-}
-
-static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
-{
- return kvm_condition_valid32(vcpu);
-}
-
-static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
-{
- kvm_skip_instr32(vcpu, is_wide_instr);
-}
-
-static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
-{
- vcpu->arch.hcr = HCR_GUEST_MASK;
-}
-
-static inline unsigned long *vcpu_hcr(const struct kvm_vcpu *vcpu)
-{
- return (unsigned long *)&vcpu->arch.hcr;
-}
-
-static inline void vcpu_clear_wfe_traps(struct kvm_vcpu *vcpu)
-{
- vcpu->arch.hcr &= ~HCR_TWE;
-}
-
-static inline void vcpu_set_wfe_traps(struct kvm_vcpu *vcpu)
-{
- vcpu->arch.hcr |= HCR_TWE;
-}
-
-static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
-{
- return true;
-}
-
-static inline unsigned long *vcpu_pc(struct kvm_vcpu *vcpu)
-{
- return &vcpu->arch.ctxt.gp_regs.usr_regs.ARM_pc;
-}
-
-static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
-{
- return (unsigned long *)&vcpu->arch.ctxt.gp_regs.usr_regs.ARM_cpsr;
-}
-
-static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
-{
- *vcpu_cpsr(vcpu) |= PSR_T_BIT;
-}
-
-static inline bool mode_has_spsr(struct kvm_vcpu *vcpu)
-{
- unsigned long cpsr_mode = vcpu->arch.ctxt.gp_regs.usr_regs.ARM_cpsr & MODE_MASK;
- return (cpsr_mode > USR_MODE && cpsr_mode < SYSTEM_MODE);
-}
-
-static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
-{
- unsigned long cpsr_mode = vcpu->arch.ctxt.gp_regs.usr_regs.ARM_cpsr & MODE_MASK;
- return cpsr_mode > USR_MODE;
-}
-
-static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
-{
- return vcpu->arch.fault.hsr;
-}
-
-static inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
-{
- u32 hsr = kvm_vcpu_get_hsr(vcpu);
-
- if (hsr & HSR_CV)
- return (hsr & HSR_COND) >> HSR_COND_SHIFT;
-
- return -1;
-}
-
-static inline unsigned long kvm_vcpu_get_hfar(struct kvm_vcpu *vcpu)
-{
- return vcpu->arch.fault.hxfar;
-}
-
-static inline phys_addr_t kvm_vcpu_get_fault_ipa(struct kvm_vcpu *vcpu)
-{
- return ((phys_addr_t)vcpu->arch.fault.hpfar & HPFAR_MASK) << 8;
-}
-
-static inline bool kvm_vcpu_dabt_isvalid(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_ISV;
-}
-
-static inline bool kvm_vcpu_dabt_iswrite(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_WNR;
-}
-
-static inline bool kvm_vcpu_dabt_issext(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_SSE;
-}
-
-static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
-{
- return false;
-}
-
-static inline int kvm_vcpu_dabt_get_rd(struct kvm_vcpu *vcpu)
-{
- return (kvm_vcpu_get_hsr(vcpu) & HSR_SRT_MASK) >> HSR_SRT_SHIFT;
-}
-
-static inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_DABT_S1PTW;
-}
-
-static inline bool kvm_vcpu_dabt_is_cm(struct kvm_vcpu *vcpu)
-{
- return !!(kvm_vcpu_get_hsr(vcpu) & HSR_DABT_CM);
-}
-
-/* Get Access Size from a data abort */
-static inline int kvm_vcpu_dabt_get_as(struct kvm_vcpu *vcpu)
-{
- switch ((kvm_vcpu_get_hsr(vcpu) >> 22) & 0x3) {
- case 0:
- return 1;
- case 1:
- return 2;
- case 2:
- return 4;
- default:
- kvm_err("Hardware is weird: SAS 0b11 is reserved\n");
- return -EFAULT;
- }
-}
-
-/* This one is not specific to Data Abort */
-static inline bool kvm_vcpu_trap_il_is32bit(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_IL;
-}
-
-static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) >> HSR_EC_SHIFT;
-}
-
-static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_trap_get_class(vcpu) == HSR_EC_IABT;
-}
-
-static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu);
-}
-
-static inline u8 kvm_vcpu_trap_get_fault(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_FSC;
-}
-
-static inline u8 kvm_vcpu_trap_get_fault_type(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_FSC_TYPE;
-}
-
-static inline bool kvm_vcpu_dabt_isextabt(struct kvm_vcpu *vcpu)
-{
- switch (kvm_vcpu_trap_get_fault(vcpu)) {
- case FSC_SEA:
- case FSC_SEA_TTW0:
- case FSC_SEA_TTW1:
- case FSC_SEA_TTW2:
- case FSC_SEA_TTW3:
- case FSC_SECC:
- case FSC_SECC_TTW0:
- case FSC_SECC_TTW1:
- case FSC_SECC_TTW2:
- case FSC_SECC_TTW3:
- return true;
- default:
- return false;
- }
-}
-
-static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
-{
- if (kvm_vcpu_trap_is_iabt(vcpu))
- return false;
-
- return kvm_vcpu_dabt_iswrite(vcpu);
-}
-
-static inline u32 kvm_vcpu_hvc_get_imm(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_HVC_IMM_MASK;
-}
-
-static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
-{
- return vcpu_cp15(vcpu, c0_MPIDR) & MPIDR_HWID_BITMASK;
-}
-
-static inline bool kvm_arm_get_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu)
-{
- return false;
-}
-
-static inline void kvm_arm_set_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu,
- bool flag)
-{
-}
-
-static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
-{
- *vcpu_cpsr(vcpu) |= PSR_E_BIT;
-}
-
-static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
-{
- return !!(*vcpu_cpsr(vcpu) & PSR_E_BIT);
-}
-
-static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
- unsigned long data,
- unsigned int len)
-{
- if (kvm_vcpu_is_be(vcpu)) {
- switch (len) {
- case 1:
- return data & 0xff;
- case 2:
- return be16_to_cpu(data & 0xffff);
- default:
- return be32_to_cpu(data);
- }
- } else {
- switch (len) {
- case 1:
- return data & 0xff;
- case 2:
- return le16_to_cpu(data & 0xffff);
- default:
- return le32_to_cpu(data);
- }
- }
-}
-
-static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
- unsigned long data,
- unsigned int len)
-{
- if (kvm_vcpu_is_be(vcpu)) {
- switch (len) {
- case 1:
- return data & 0xff;
- case 2:
- return cpu_to_be16(data & 0xffff);
- default:
- return cpu_to_be32(data);
- }
- } else {
- switch (len) {
- case 1:
- return data & 0xff;
- case 2:
- return cpu_to_le16(data & 0xffff);
- default:
- return cpu_to_le32(data);
- }
- }
-}
-
-static inline bool vcpu_has_ptrauth(struct kvm_vcpu *vcpu) { return false; }
-static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu) { }
-
-#endif /* __ARM_KVM_EMULATE_H__ */
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
deleted file mode 100644
index 32564b0..0000000
--- a/arch/arm/include/asm/kvm_host.h
+++ /dev/null
@@ -1,427 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#ifndef __ARM_KVM_HOST_H__
-#define __ARM_KVM_HOST_H__
-
-#include <linux/errno.h>
-#include <linux/types.h>
-#include <linux/kvm_types.h>
-#include <asm/cputype.h>
-#include <asm/kvm.h>
-#include <asm/kvm_asm.h>
-#include <asm/kvm_mmio.h>
-#include <asm/fpstate.h>
-#include <kvm/arm_arch_timer.h>
-
-#define __KVM_HAVE_ARCH_INTC_INITIALIZED
-
-#define KVM_USER_MEM_SLOTS 32
-#define KVM_HAVE_ONE_REG
-#define KVM_HALT_POLL_NS_DEFAULT 500000
-
-#define KVM_VCPU_MAX_FEATURES 2
-
-#include <kvm/arm_vgic.h>
-
-
-#ifdef CONFIG_ARM_GIC_V3
-#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
-#else
-#define KVM_MAX_VCPUS VGIC_V2_MAX_CPUS
-#endif
-
-#define KVM_REQ_SLEEP \
- KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
-#define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
-#define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
-
-DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
-
-static inline int kvm_arm_init_sve(void) { return 0; }
-
-u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
-int __attribute_const__ kvm_target_cpu(void);
-int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
-void kvm_reset_coprocs(struct kvm_vcpu *vcpu);
-
-struct kvm_vmid {
- /* The VMID generation used for the virt. memory system */
- u64 vmid_gen;
- u32 vmid;
-};
-
-struct kvm_arch {
- /* The last vcpu id that ran on each physical CPU */
- int __percpu *last_vcpu_ran;
-
- /*
- * Anything that is not used directly from assembly code goes
- * here.
- */
-
- /* The VMID generation used for the virt. memory system */
- struct kvm_vmid vmid;
-
- /* Stage-2 page table */
- pgd_t *pgd;
- phys_addr_t pgd_phys;
-
- /* Interrupt controller */
- struct vgic_dist vgic;
- int max_vcpus;
-
- /* Mandated version of PSCI */
- u32 psci_version;
-};
-
-#define KVM_NR_MEM_OBJS 40
-
-/*
- * We don't want allocation failures within the mmu code, so we preallocate
- * enough memory for a single page fault in a cache.
- */
-struct kvm_mmu_memory_cache {
- int nobjs;
- void *objects[KVM_NR_MEM_OBJS];
-};
-
-struct kvm_vcpu_fault_info {
- u32 hsr; /* Hyp Syndrome Register */
- u32 hxfar; /* Hyp Data/Inst. Fault Address Register */
- u32 hpfar; /* Hyp IPA Fault Address Register */
-};
-
-/*
- * 0 is reserved as an invalid value.
- * Order should be kept in sync with the save/restore code.
- */
-enum vcpu_sysreg {
- __INVALID_SYSREG__,
- c0_MPIDR, /* MultiProcessor ID Register */
- c0_CSSELR, /* Cache Size Selection Register */
- c1_SCTLR, /* System Control Register */
- c1_ACTLR, /* Auxiliary Control Register */
- c1_CPACR, /* Coprocessor Access Control */
- c2_TTBR0, /* Translation Table Base Register 0 */
- c2_TTBR0_high, /* TTBR0 top 32 bits */
- c2_TTBR1, /* Translation Table Base Register 1 */
- c2_TTBR1_high, /* TTBR1 top 32 bits */
- c2_TTBCR, /* Translation Table Base Control R. */
- c3_DACR, /* Domain Access Control Register */
- c5_DFSR, /* Data Fault Status Register */
- c5_IFSR, /* Instruction Fault Status Register */
- c5_ADFSR, /* Auxilary Data Fault Status R */
- c5_AIFSR, /* Auxilary Instrunction Fault Status R */
- c6_DFAR, /* Data Fault Address Register */
- c6_IFAR, /* Instruction Fault Address Register */
- c7_PAR, /* Physical Address Register */
- c7_PAR_high, /* PAR top 32 bits */
- c9_L2CTLR, /* Cortex A15/A7 L2 Control Register */
- c10_PRRR, /* Primary Region Remap Register */
- c10_NMRR, /* Normal Memory Remap Register */
- c12_VBAR, /* Vector Base Address Register */
- c13_CID, /* Context ID Register */
- c13_TID_URW, /* Thread ID, User R/W */
- c13_TID_URO, /* Thread ID, User R/O */
- c13_TID_PRIV, /* Thread ID, Privileged */
- c14_CNTKCTL, /* Timer Control Register (PL1) */
- c10_AMAIR0, /* Auxilary Memory Attribute Indirection Reg0 */
- c10_AMAIR1, /* Auxilary Memory Attribute Indirection Reg1 */
- NR_CP15_REGS /* Number of regs (incl. invalid) */
-};
-
-struct kvm_cpu_context {
- struct kvm_regs gp_regs;
- struct vfp_hard_struct vfp;
- u32 cp15[NR_CP15_REGS];
-};
-
-struct kvm_host_data {
- struct kvm_cpu_context host_ctxt;
-};
-
-typedef struct kvm_host_data kvm_host_data_t;
-
-static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
-{
- /* The host's MPIDR is immutable, so let's set it up at boot time */
- cpu_ctxt->cp15[c0_MPIDR] = read_cpuid_mpidr();
-}
-
-struct vcpu_reset_state {
- unsigned long pc;
- unsigned long r0;
- bool be;
- bool reset;
-};
-
-struct kvm_vcpu_arch {
- struct kvm_cpu_context ctxt;
-
- int target; /* Processor target */
- DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
-
- /* The CPU type we expose to the VM */
- u32 midr;
-
- /* HYP trapping configuration */
- u32 hcr;
-
- /* Exception Information */
- struct kvm_vcpu_fault_info fault;
-
- /* Host FP context */
- struct kvm_cpu_context *host_cpu_context;
-
- /* VGIC state */
- struct vgic_cpu vgic_cpu;
- struct arch_timer_cpu timer_cpu;
-
- /*
- * Anything that is not used directly from assembly code goes
- * here.
- */
-
- /* vcpu power-off state */
- bool power_off;
-
- /* Don't run the guest (internal implementation need) */
- bool pause;
-
- /* IO related fields */
- struct kvm_decode mmio_decode;
-
- /* Cache some mmu pages needed inside spinlock regions */
- struct kvm_mmu_memory_cache mmu_page_cache;
-
- struct vcpu_reset_state reset_state;
-
- /* Detect first run of a vcpu */
- bool has_run_once;
-};
-
-struct kvm_vm_stat {
- ulong remote_tlb_flush;
-};
-
-struct kvm_vcpu_stat {
- u64 halt_successful_poll;
- u64 halt_attempted_poll;
- u64 halt_poll_invalid;
- u64 halt_wakeup;
- u64 hvc_exit_stat;
- u64 wfe_exit_stat;
- u64 wfi_exit_stat;
- u64 mmio_exit_user;
- u64 mmio_exit_kernel;
- u64 exits;
-};
-
-#define vcpu_cp15(v,r) (v)->arch.ctxt.cp15[r]
-
-int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
-unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
-int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
-int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
-int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
-
-unsigned long __kvm_call_hyp(void *hypfn, ...);
-
-/*
- * The has_vhe() part doesn't get emitted, but is used for type-checking.
- */
-#define kvm_call_hyp(f, ...) \
- do { \
- if (has_vhe()) { \
- f(__VA_ARGS__); \
- } else { \
- __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__); \
- } \
- } while(0)
-
-#define kvm_call_hyp_ret(f, ...) \
- ({ \
- typeof(f(__VA_ARGS__)) ret; \
- \
- if (has_vhe()) { \
- ret = f(__VA_ARGS__); \
- } else { \
- ret = __kvm_call_hyp(kvm_ksym_ref(f), \
- ##__VA_ARGS__); \
- } \
- \
- ret; \
- })
-
-void force_vm_exit(const cpumask_t *mask);
-int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
- struct kvm_vcpu_events *events);
-
-int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
- struct kvm_vcpu_events *events);
-
-#define KVM_ARCH_WANT_MMU_NOTIFIER
-int kvm_unmap_hva_range(struct kvm *kvm,
- unsigned long start, unsigned long end, unsigned flags);
-int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
-
-unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
-int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
-int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
-int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
-
-struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
-struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
-void kvm_arm_halt_guest(struct kvm *kvm);
-void kvm_arm_resume_guest(struct kvm *kvm);
-
-int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
-unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu);
-int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
-int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
-
-int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
- int exception_index);
-
-static inline void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
- int exception_index) {}
-
-static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
- unsigned long hyp_stack_ptr,
- unsigned long vector_ptr)
-{
- /*
- * Call initialization code, and switch to the full blown HYP
- * code. The init code doesn't need to preserve these
- * registers as r0-r3 are already callee saved according to
- * the AAPCS.
- * Note that we slightly misuse the prototype by casting the
- * stack pointer to a void *.
-
- * The PGDs are always passed as the third argument, in order
- * to be passed into r2-r3 to the init code (yes, this is
- * compliant with the PCS!).
- */
-
- __kvm_call_hyp((void*)hyp_stack_ptr, vector_ptr, pgd_ptr);
-}
-
-static inline void __cpu_init_stage2(void)
-{
- kvm_call_hyp(__init_stage2_translation);
-}
-
-static inline int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext)
-{
- return 0;
-}
-
-int kvm_perf_init(void);
-int kvm_perf_teardown(void);
-
-void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
-
-struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
-
-static inline bool kvm_arch_requires_vhe(void) { return false; }
-static inline void kvm_arch_hardware_unsetup(void) {}
-static inline void kvm_arch_sync_events(struct kvm *kvm) {}
-static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
-static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
-static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
-
-static inline void kvm_arm_init_debug(void) {}
-static inline void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu) {}
-static inline void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) {}
-static inline void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) {}
-static inline void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) {}
-
-int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
- struct kvm_device_attr *attr);
-int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
- struct kvm_device_attr *attr);
-int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
- struct kvm_device_attr *attr);
-
-/*
- * VFP/NEON switching is all done by the hyp switch code, so no need to
- * coordinate with host context handling for this state:
- */
-static inline void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu) {}
-static inline void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) {}
-static inline void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) {}
-
-static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
-static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
-
-static inline void kvm_arm_vhe_guest_enter(void) {}
-static inline void kvm_arm_vhe_guest_exit(void) {}
-
-#define KVM_BP_HARDEN_UNKNOWN -1
-#define KVM_BP_HARDEN_WA_NEEDED 0
-#define KVM_BP_HARDEN_NOT_REQUIRED 1
-
-static inline int kvm_arm_harden_branch_predictor(void)
-{
- switch(read_cpuid_part()) {
-#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
- case ARM_CPU_PART_BRAHMA_B15:
- case ARM_CPU_PART_CORTEX_A12:
- case ARM_CPU_PART_CORTEX_A15:
- case ARM_CPU_PART_CORTEX_A17:
- return KVM_BP_HARDEN_WA_NEEDED;
-#endif
- case ARM_CPU_PART_CORTEX_A7:
- return KVM_BP_HARDEN_NOT_REQUIRED;
- default:
- return KVM_BP_HARDEN_UNKNOWN;
- }
-}
-
-#define KVM_SSBD_UNKNOWN -1
-#define KVM_SSBD_FORCE_DISABLE 0
-#define KVM_SSBD_KERNEL 1
-#define KVM_SSBD_FORCE_ENABLE 2
-#define KVM_SSBD_MITIGATED 3
-
-static inline int kvm_arm_have_ssbd(void)
-{
- /* No way to detect it yet, pretend it is not there. */
- return KVM_SSBD_UNKNOWN;
-}
-
-static inline void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu) {}
-static inline void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu) {}
-
-#define __KVM_HAVE_ARCH_VM_ALLOC
-struct kvm *kvm_arch_alloc_vm(void);
-void kvm_arch_free_vm(struct kvm *kvm);
-
-static inline int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type)
-{
- /*
- * On 32bit ARM, VMs get a static 40bit IPA stage2 setup,
- * so any non-zero value used as type is illegal.
- */
- if (type)
- return -EINVAL;
- return 0;
-}
-
-static inline int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature)
-{
- return -EINVAL;
-}
-
-static inline bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu)
-{
- return true;
-}
-
-#define kvm_arm_vcpu_loaded(vcpu) (false)
-
-#endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/asm/kvm_hyp.h b/arch/arm/include/asm/kvm_hyp.h
deleted file mode 100644
index 40e9034..0000000
--- a/arch/arm/include/asm/kvm_hyp.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2015 - ARM Ltd
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- */
-
-#ifndef __ARM_KVM_HYP_H__
-#define __ARM_KVM_HYP_H__
-
-#include <linux/compiler.h>
-#include <linux/kvm_host.h>
-#include <asm/cp15.h>
-#include <asm/vfp.h>
-
-#define __hyp_text __section(.hyp.text) notrace
-
-#define __ACCESS_VFP(CRn) \
- "mrc", "mcr", __stringify(p10, 7, %0, CRn, cr0, 0), u32
-
-#define write_special(v, r) \
- asm volatile("msr " __stringify(r) ", %0" : : "r" (v))
-#define read_special(r) ({ \
- u32 __val; \
- asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
- __val; \
-})
-
-#define TTBR0 __ACCESS_CP15_64(0, c2)
-#define TTBR1 __ACCESS_CP15_64(1, c2)
-#define VTTBR __ACCESS_CP15_64(6, c2)
-#define PAR __ACCESS_CP15_64(0, c7)
-#define CNTP_CVAL __ACCESS_CP15_64(2, c14)
-#define CNTV_CVAL __ACCESS_CP15_64(3, c14)
-#define CNTVOFF __ACCESS_CP15_64(4, c14)
-
-#define MIDR __ACCESS_CP15(c0, 0, c0, 0)
-#define CSSELR __ACCESS_CP15(c0, 2, c0, 0)
-#define VPIDR __ACCESS_CP15(c0, 4, c0, 0)
-#define VMPIDR __ACCESS_CP15(c0, 4, c0, 5)
-#define SCTLR __ACCESS_CP15(c1, 0, c0, 0)
-#define CPACR __ACCESS_CP15(c1, 0, c0, 2)
-#define HCR __ACCESS_CP15(c1, 4, c1, 0)
-#define HDCR __ACCESS_CP15(c1, 4, c1, 1)
-#define HCPTR __ACCESS_CP15(c1, 4, c1, 2)
-#define HSTR __ACCESS_CP15(c1, 4, c1, 3)
-#define TTBCR __ACCESS_CP15(c2, 0, c0, 2)
-#define HTCR __ACCESS_CP15(c2, 4, c0, 2)
-#define VTCR __ACCESS_CP15(c2, 4, c1, 2)
-#define DACR __ACCESS_CP15(c3, 0, c0, 0)
-#define DFSR __ACCESS_CP15(c5, 0, c0, 0)
-#define IFSR __ACCESS_CP15(c5, 0, c0, 1)
-#define ADFSR __ACCESS_CP15(c5, 0, c1, 0)
-#define AIFSR __ACCESS_CP15(c5, 0, c1, 1)
-#define HSR __ACCESS_CP15(c5, 4, c2, 0)
-#define DFAR __ACCESS_CP15(c6, 0, c0, 0)
-#define IFAR __ACCESS_CP15(c6, 0, c0, 2)
-#define HDFAR __ACCESS_CP15(c6, 4, c0, 0)
-#define HIFAR __ACCESS_CP15(c6, 4, c0, 2)
-#define HPFAR __ACCESS_CP15(c6, 4, c0, 4)
-#define ICIALLUIS __ACCESS_CP15(c7, 0, c1, 0)
-#define BPIALLIS __ACCESS_CP15(c7, 0, c1, 6)
-#define ICIMVAU __ACCESS_CP15(c7, 0, c5, 1)
-#define ATS1CPR __ACCESS_CP15(c7, 0, c8, 0)
-#define TLBIALLIS __ACCESS_CP15(c8, 0, c3, 0)
-#define TLBIALL __ACCESS_CP15(c8, 0, c7, 0)
-#define TLBIALLNSNHIS __ACCESS_CP15(c8, 4, c3, 4)
-#define PRRR __ACCESS_CP15(c10, 0, c2, 0)
-#define NMRR __ACCESS_CP15(c10, 0, c2, 1)
-#define AMAIR0 __ACCESS_CP15(c10, 0, c3, 0)
-#define AMAIR1 __ACCESS_CP15(c10, 0, c3, 1)
-#define VBAR __ACCESS_CP15(c12, 0, c0, 0)
-#define CID __ACCESS_CP15(c13, 0, c0, 1)
-#define TID_URW __ACCESS_CP15(c13, 0, c0, 2)
-#define TID_URO __ACCESS_CP15(c13, 0, c0, 3)
-#define TID_PRIV __ACCESS_CP15(c13, 0, c0, 4)
-#define HTPIDR __ACCESS_CP15(c13, 4, c0, 2)
-#define CNTKCTL __ACCESS_CP15(c14, 0, c1, 0)
-#define CNTP_CTL __ACCESS_CP15(c14, 0, c2, 1)
-#define CNTV_CTL __ACCESS_CP15(c14, 0, c3, 1)
-#define CNTHCTL __ACCESS_CP15(c14, 4, c1, 0)
-
-#define VFP_FPEXC __ACCESS_VFP(FPEXC)
-
-/* AArch64 compatibility macros, only for the timer so far */
-#define read_sysreg_el0(r) read_sysreg(r##_EL0)
-#define write_sysreg_el0(v, r) write_sysreg(v, r##_EL0)
-
-#define SYS_CNTP_CTL_EL0 CNTP_CTL
-#define SYS_CNTP_CVAL_EL0 CNTP_CVAL
-#define SYS_CNTV_CTL_EL0 CNTV_CTL
-#define SYS_CNTV_CVAL_EL0 CNTV_CVAL
-
-#define cntvoff_el2 CNTVOFF
-#define cnthctl_el2 CNTHCTL
-
-void __timer_enable_traps(struct kvm_vcpu *vcpu);
-void __timer_disable_traps(struct kvm_vcpu *vcpu);
-
-void __vgic_v2_save_state(struct kvm_vcpu *vcpu);
-void __vgic_v2_restore_state(struct kvm_vcpu *vcpu);
-
-void __sysreg_save_state(struct kvm_cpu_context *ctxt);
-void __sysreg_restore_state(struct kvm_cpu_context *ctxt);
-
-void __vgic_v3_save_state(struct kvm_vcpu *vcpu);
-void __vgic_v3_restore_state(struct kvm_vcpu *vcpu);
-void __vgic_v3_activate_traps(struct kvm_vcpu *vcpu);
-void __vgic_v3_deactivate_traps(struct kvm_vcpu *vcpu);
-void __vgic_v3_save_aprs(struct kvm_vcpu *vcpu);
-void __vgic_v3_restore_aprs(struct kvm_vcpu *vcpu);
-
-asmlinkage void __vfp_save_state(struct vfp_hard_struct *vfp);
-asmlinkage void __vfp_restore_state(struct vfp_hard_struct *vfp);
-static inline bool __vfp_enabled(void)
-{
- return !(read_sysreg(HCPTR) & (HCPTR_TCP(11) | HCPTR_TCP(10)));
-}
-
-void __hyp_text __banked_save_state(struct kvm_cpu_context *ctxt);
-void __hyp_text __banked_restore_state(struct kvm_cpu_context *ctxt);
-
-asmlinkage int __guest_enter(struct kvm_vcpu *vcpu,
- struct kvm_cpu_context *host);
-asmlinkage int __hyp_do_panic(const char *, int, u32);
-
-#endif /* __ARM_KVM_HYP_H__ */
diff --git a/arch/arm/include/asm/kvm_mmio.h b/arch/arm/include/asm/kvm_mmio.h
deleted file mode 100644
index 32fbf82..0000000
--- a/arch/arm/include/asm/kvm_mmio.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#ifndef __ARM_KVM_MMIO_H__
-#define __ARM_KVM_MMIO_H__
-
-#include <linux/kvm_host.h>
-#include <asm/kvm_asm.h>
-#include <asm/kvm_arm.h>
-
-struct kvm_decode {
- unsigned long rt;
- bool sign_extend;
- /* Not used on 32-bit arm */
- bool sixty_four;
-};
-
-void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
-unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
-
-int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
- phys_addr_t fault_ipa);
-
-#endif /* __ARM_KVM_MMIO_H__ */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
deleted file mode 100644
index 0d84d50..0000000
--- a/arch/arm/include/asm/kvm_mmu.h
+++ /dev/null
@@ -1,435 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#ifndef __ARM_KVM_MMU_H__
-#define __ARM_KVM_MMU_H__
-
-#include <asm/memory.h>
-#include <asm/page.h>
-
-/*
- * We directly use the kernel VA for the HYP, as we can directly share
- * the mapping (HTTBR "covers" TTBR1).
- */
-#define kern_hyp_va(kva) (kva)
-
-/* Contrary to arm64, there is no need to generate a PC-relative address */
-#define hyp_symbol_addr(s) \
- ({ \
- typeof(s) *addr = &(s); \
- addr; \
- })
-
-#ifndef __ASSEMBLY__
-
-#include <linux/highmem.h>
-#include <asm/cacheflush.h>
-#include <asm/cputype.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_hyp.h>
-#include <asm/pgalloc.h>
-#include <asm/stage2_pgtable.h>
-
-/* Ensure compatibility with arm64 */
-#define VA_BITS 32
-
-#define kvm_phys_shift(kvm) KVM_PHYS_SHIFT
-#define kvm_phys_size(kvm) (1ULL << kvm_phys_shift(kvm))
-#define kvm_phys_mask(kvm) (kvm_phys_size(kvm) - 1ULL)
-#define kvm_vttbr_baddr_mask(kvm) VTTBR_BADDR_MASK
-
-#define stage2_pgd_size(kvm) (PTRS_PER_S2_PGD * sizeof(pgd_t))
-
-int create_hyp_mappings(void *from, void *to, pgprot_t prot);
-int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
- void __iomem **kaddr,
- void __iomem **haddr);
-int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
- void **haddr);
-void free_hyp_pgds(void);
-
-void stage2_unmap_vm(struct kvm *kvm);
-int kvm_alloc_stage2_pgd(struct kvm *kvm);
-void kvm_free_stage2_pgd(struct kvm *kvm);
-int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
- phys_addr_t pa, unsigned long size, bool writable);
-
-int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
-
-void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
-
-phys_addr_t kvm_mmu_get_httbr(void);
-phys_addr_t kvm_get_idmap_vector(void);
-int kvm_mmu_init(void);
-void kvm_clear_hyp_idmap(void);
-
-#define kvm_mk_pmd(ptep) __pmd(__pa(ptep) | PMD_TYPE_TABLE)
-#define kvm_mk_pud(pmdp) __pud(__pa(pmdp) | PMD_TYPE_TABLE)
-#define kvm_mk_pgd(pudp) ({ BUILD_BUG(); 0; })
-
-#define kvm_pfn_pte(pfn, prot) pfn_pte(pfn, prot)
-#define kvm_pfn_pmd(pfn, prot) pfn_pmd(pfn, prot)
-#define kvm_pfn_pud(pfn, prot) (__pud(0))
-
-#define kvm_pud_pfn(pud) ({ WARN_ON(1); 0; })
-
-
-#define kvm_pmd_mkhuge(pmd) pmd_mkhuge(pmd)
-/* No support for pud hugepages */
-#define kvm_pud_mkhuge(pud) ( {WARN_ON(1); pud; })
-
-/*
- * The following kvm_*pud*() functions are provided strictly to allow
- * sharing code with arm64. They should never be called in practice.
- */
-static inline void kvm_set_s2pud_readonly(pud_t *pud)
-{
- WARN_ON(1);
-}
-
-static inline bool kvm_s2pud_readonly(pud_t *pud)
-{
- WARN_ON(1);
- return false;
-}
-
-static inline void kvm_set_pud(pud_t *pud, pud_t new_pud)
-{
- WARN_ON(1);
-}
-
-static inline pud_t kvm_s2pud_mkwrite(pud_t pud)
-{
- WARN_ON(1);
- return pud;
-}
-
-static inline pud_t kvm_s2pud_mkexec(pud_t pud)
-{
- WARN_ON(1);
- return pud;
-}
-
-static inline bool kvm_s2pud_exec(pud_t *pud)
-{
- WARN_ON(1);
- return false;
-}
-
-static inline pud_t kvm_s2pud_mkyoung(pud_t pud)
-{
- BUG();
- return pud;
-}
-
-static inline bool kvm_s2pud_young(pud_t pud)
-{
- WARN_ON(1);
- return false;
-}
-
-static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
-{
- pte_val(pte) |= L_PTE_S2_RDWR;
- return pte;
-}
-
-static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd)
-{
- pmd_val(pmd) |= L_PMD_S2_RDWR;
- return pmd;
-}
-
-static inline pte_t kvm_s2pte_mkexec(pte_t pte)
-{
- pte_val(pte) &= ~L_PTE_XN;
- return pte;
-}
-
-static inline pmd_t kvm_s2pmd_mkexec(pmd_t pmd)
-{
- pmd_val(pmd) &= ~PMD_SECT_XN;
- return pmd;
-}
-
-static inline void kvm_set_s2pte_readonly(pte_t *pte)
-{
- pte_val(*pte) = (pte_val(*pte) & ~L_PTE_S2_RDWR) | L_PTE_S2_RDONLY;
-}
-
-static inline bool kvm_s2pte_readonly(pte_t *pte)
-{
- return (pte_val(*pte) & L_PTE_S2_RDWR) == L_PTE_S2_RDONLY;
-}
-
-static inline bool kvm_s2pte_exec(pte_t *pte)
-{
- return !(pte_val(*pte) & L_PTE_XN);
-}
-
-static inline void kvm_set_s2pmd_readonly(pmd_t *pmd)
-{
- pmd_val(*pmd) = (pmd_val(*pmd) & ~L_PMD_S2_RDWR) | L_PMD_S2_RDONLY;
-}
-
-static inline bool kvm_s2pmd_readonly(pmd_t *pmd)
-{
- return (pmd_val(*pmd) & L_PMD_S2_RDWR) == L_PMD_S2_RDONLY;
-}
-
-static inline bool kvm_s2pmd_exec(pmd_t *pmd)
-{
- return !(pmd_val(*pmd) & PMD_SECT_XN);
-}
-
-static inline bool kvm_page_empty(void *ptr)
-{
- struct page *ptr_page = virt_to_page(ptr);
- return page_count(ptr_page) == 1;
-}
-
-#define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep)
-#define kvm_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp)
-#define kvm_pud_table_empty(kvm, pudp) false
-
-#define hyp_pte_table_empty(ptep) kvm_page_empty(ptep)
-#define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp)
-#define hyp_pud_table_empty(pudp) false
-
-struct kvm;
-
-#define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
-
-static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
-{
- return (vcpu_cp15(vcpu, c1_SCTLR) & 0b101) == 0b101;
-}
-
-static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size)
-{
- /*
- * Clean the dcache to the Point of Coherency.
- *
- * We need to do this through a kernel mapping (using the
- * user-space mapping has proved to be the wrong
- * solution). For that, we need to kmap one page at a time,
- * and iterate over the range.
- */
-
- VM_BUG_ON(size & ~PAGE_MASK);
-
- while (size) {
- void *va = kmap_atomic_pfn(pfn);
-
- kvm_flush_dcache_to_poc(va, PAGE_SIZE);
-
- size -= PAGE_SIZE;
- pfn++;
-
- kunmap_atomic(va);
- }
-}
-
-static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn,
- unsigned long size)
-{
- u32 iclsz;
-
- /*
- * If we are going to insert an instruction page and the icache is
- * either VIPT or PIPT, there is a potential problem where the host
- * (or another VM) may have used the same page as this guest, and we
- * read incorrect data from the icache. If we're using a PIPT cache,
- * we can invalidate just that page, but if we are using a VIPT cache
- * we need to invalidate the entire icache - damn shame - as written
- * in the ARM ARM (DDI 0406C.b - Page B3-1393).
- *
- * VIVT caches are tagged using both the ASID and the VMID and doesn't
- * need any kind of flushing (DDI 0406C.b - Page B3-1392).
- */
-
- VM_BUG_ON(size & ~PAGE_MASK);
-
- if (icache_is_vivt_asid_tagged())
- return;
-
- if (!icache_is_pipt()) {
- /* any kind of VIPT cache */
- __flush_icache_all();
- return;
- }
-
- /*
- * CTR IminLine contains Log2 of the number of words in the
- * cache line, so we can get the number of words as
- * 2 << (IminLine - 1). To get the number of bytes, we
- * multiply by 4 (the number of bytes in a 32-bit word), and
- * get 4 << (IminLine).
- */
- iclsz = 4 << (read_cpuid(CPUID_CACHETYPE) & 0xf);
-
- while (size) {
- void *va = kmap_atomic_pfn(pfn);
- void *end = va + PAGE_SIZE;
- void *addr = va;
-
- do {
- write_sysreg(addr, ICIMVAU);
- addr += iclsz;
- } while (addr < end);
-
- dsb(ishst);
- isb();
-
- size -= PAGE_SIZE;
- pfn++;
-
- kunmap_atomic(va);
- }
-
- /* Check if we need to invalidate the BTB */
- if ((read_cpuid_ext(CPUID_EXT_MMFR1) >> 28) != 4) {
- write_sysreg(0, BPIALLIS);
- dsb(ishst);
- isb();
- }
-}
-
-static inline void __kvm_flush_dcache_pte(pte_t pte)
-{
- void *va = kmap_atomic(pte_page(pte));
-
- kvm_flush_dcache_to_poc(va, PAGE_SIZE);
-
- kunmap_atomic(va);
-}
-
-static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
-{
- unsigned long size = PMD_SIZE;
- kvm_pfn_t pfn = pmd_pfn(pmd);
-
- while (size) {
- void *va = kmap_atomic_pfn(pfn);
-
- kvm_flush_dcache_to_poc(va, PAGE_SIZE);
-
- pfn++;
- size -= PAGE_SIZE;
-
- kunmap_atomic(va);
- }
-}
-
-static inline void __kvm_flush_dcache_pud(pud_t pud)
-{
-}
-
-#define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x))
-
-void kvm_set_way_flush(struct kvm_vcpu *vcpu);
-void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
-
-static inline bool __kvm_cpu_uses_extended_idmap(void)
-{
- return false;
-}
-
-static inline unsigned long __kvm_idmap_ptrs_per_pgd(void)
-{
- return PTRS_PER_PGD;
-}
-
-static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd,
- pgd_t *hyp_pgd,
- pgd_t *merged_hyp_pgd,
- unsigned long hyp_idmap_start) { }
-
-static inline unsigned int kvm_get_vmid_bits(void)
-{
- return 8;
-}
-
-/*
- * We are not in the kvm->srcu critical section most of the time, so we take
- * the SRCU read lock here. Since we copy the data from the user page, we
- * can immediately drop the lock again.
- */
-static inline int kvm_read_guest_lock(struct kvm *kvm,
- gpa_t gpa, void *data, unsigned long len)
-{
- int srcu_idx = srcu_read_lock(&kvm->srcu);
- int ret = kvm_read_guest(kvm, gpa, data, len);
-
- srcu_read_unlock(&kvm->srcu, srcu_idx);
-
- return ret;
-}
-
-static inline int kvm_write_guest_lock(struct kvm *kvm, gpa_t gpa,
- const void *data, unsigned long len)
-{
- int srcu_idx = srcu_read_lock(&kvm->srcu);
- int ret = kvm_write_guest(kvm, gpa, data, len);
-
- srcu_read_unlock(&kvm->srcu, srcu_idx);
-
- return ret;
-}
-
-static inline void *kvm_get_hyp_vector(void)
-{
- switch(read_cpuid_part()) {
-#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
- case ARM_CPU_PART_CORTEX_A12:
- case ARM_CPU_PART_CORTEX_A17:
- {
- extern char __kvm_hyp_vector_bp_inv[];
- return kvm_ksym_ref(__kvm_hyp_vector_bp_inv);
- }
-
- case ARM_CPU_PART_BRAHMA_B15:
- case ARM_CPU_PART_CORTEX_A15:
- {
- extern char __kvm_hyp_vector_ic_inv[];
- return kvm_ksym_ref(__kvm_hyp_vector_ic_inv);
- }
-#endif
- default:
- {
- extern char __kvm_hyp_vector[];
- return kvm_ksym_ref(__kvm_hyp_vector);
- }
- }
-}
-
-static inline int kvm_map_vectors(void)
-{
- return 0;
-}
-
-static inline int hyp_map_aux_data(void)
-{
- return 0;
-}
-
-#define kvm_phys_to_vttbr(addr) (addr)
-
-static inline void kvm_set_ipa_limit(void) {}
-
-static __always_inline u64 kvm_get_vttbr(struct kvm *kvm)
-{
- struct kvm_vmid *vmid = &kvm->arch.vmid;
- u64 vmid_field, baddr;
-
- baddr = kvm->arch.pgd_phys;
- vmid_field = (u64)vmid->vmid << VTTBR_VMID_SHIFT;
- return kvm_phys_to_vttbr(baddr) | vmid_field;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __ARM_KVM_MMU_H__ */
diff --git a/arch/arm/include/asm/kvm_ras.h b/arch/arm/include/asm/kvm_ras.h
deleted file mode 100644
index e957729..0000000
--- a/arch/arm/include/asm/kvm_ras.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (C) 2018 - Arm Ltd */
-
-#ifndef __ARM_KVM_RAS_H__
-#define __ARM_KVM_RAS_H__
-
-#include <linux/types.h>
-
-static inline int kvm_handle_guest_sea(phys_addr_t addr, unsigned int esr)
-{
- return -1;
-}
-
-#endif /* __ARM_KVM_RAS_H__ */
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index e7df5a8..eec0c0b 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -81,7 +81,7 @@
#define MACHINE_START(_type,_name) \
static const struct machine_desc __mach_desc_##_type \
__used \
- __attribute__((__section__(".arch.info.init"))) = { \
+ __section(".arch.info.init") = { \
.nr = MACH_TYPE_##_type, \
.name = _name,
@@ -91,7 +91,7 @@
#define DT_MACHINE_START(_name, _namestr) \
static const struct machine_desc __mach_desc_##_name \
__used \
- __attribute__((__section__(".arch.info.init"))) = { \
+ __section(".arch.info.init") = { \
.nr = ~0, \
.name = _namestr,
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 83d3407..ea9bd08 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -17,10 +17,8 @@
struct device;
struct hw_pci {
- struct msi_controller *msi_ctrl;
struct pci_ops *ops;
int nr_controllers;
- unsigned int io_optional:1;
void **private_data;
int (*setup)(int nr, struct pci_sys_data *);
int (*scan)(int nr, struct pci_host_bridge *);
@@ -28,11 +26,6 @@
void (*postinit)(void);
u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
- resource_size_t (*align_resource)(struct pci_dev *dev,
- const struct resource *res,
- resource_size_t start,
- resource_size_t size,
- resource_size_t align);
};
/*
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index 182163b..cfffae6 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -19,8 +19,18 @@
};
#endif
+#define PLT_ENT_STRIDE L1_CACHE_BYTES
+#define PLT_ENT_COUNT (PLT_ENT_STRIDE / sizeof(u32))
+#define PLT_ENT_SIZE (sizeof(struct plt_entries) / PLT_ENT_COUNT)
+
+struct plt_entries {
+ u32 ldr[PLT_ENT_COUNT];
+ u32 lit[PLT_ENT_COUNT];
+};
+
struct mod_plt_sec {
struct elf32_shdr *plt;
+ struct plt_entries *plt_ent;
int plt_count;
};
@@ -37,30 +47,6 @@
struct module;
u32 get_module_plt(struct module *mod, unsigned long loc, Elf32_Addr val);
-/*
- * Add the ARM architecture version to the version magic string
- */
-#define MODULE_ARCH_VERMAGIC_ARMVSN "ARMv" __stringify(__LINUX_ARM_ARCH__) " "
-
-/* Add __virt_to_phys patching state as well */
-#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
-#define MODULE_ARCH_VERMAGIC_P2V "p2v8 "
-#else
-#define MODULE_ARCH_VERMAGIC_P2V ""
-#endif
-
-/* Add instruction set architecture tag to distinguish ARM/Thumb kernels */
-#ifdef CONFIG_THUMB2_KERNEL
-#define MODULE_ARCH_VERMAGIC_ARMTHUMB "thumb2 "
-#else
-#define MODULE_ARCH_VERMAGIC_ARMTHUMB ""
-#endif
-
-#define MODULE_ARCH_VERMAGIC \
- MODULE_ARCH_VERMAGIC_ARMVSN \
- MODULE_ARCH_VERMAGIC_ARMTHUMB \
- MODULE_ARCH_VERMAGIC_P2V
-
#ifdef CONFIG_THUMB2_KERNEL
#define HAVE_ARCH_KALLSYMS_SYMBOL_VALUE
static inline unsigned long kallsyms_symbol_value(const Elf_Sym *sym)
diff --git a/arch/arm/kernel/module.lds b/arch/arm/include/asm/module.lds.h
similarity index 71%
rename from arch/arm/kernel/module.lds
rename to arch/arm/include/asm/module.lds.h
index 79cb6af..0e7cb4e 100644
--- a/arch/arm/kernel/module.lds
+++ b/arch/arm/include/asm/module.lds.h
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
+#ifdef CONFIG_ARM_MODULE_PLTS
SECTIONS {
.plt : { BYTE(0) }
.init.plt : { BYTE(0) }
}
+#endif
diff --git a/arch/arm/include/asm/nwflash.h b/arch/arm/include/asm/nwflash.h
index 0ec6f07..66b7e68 100644
--- a/arch/arm/include/asm/nwflash.h
+++ b/arch/arm/include/asm/nwflash.h
@@ -2,7 +2,6 @@
#ifndef _FLASH_H
#define _FLASH_H
-#define FLASH_MINOR 160 /* MAJOR is 10 - miscdevice */
#define CMD_WRITE_DISABLE 0
#define CMD_WRITE_ENABLE 0x28
#define CMD_WRITE_BASE64K_ENABLE 0x47
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index c2b75cb..11b058a 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -161,9 +161,7 @@
#endif /* !__ASSEMBLY__ */
-#define VM_DATA_DEFAULT_FLAGS \
- (((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
- VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+#define VM_DATA_DEFAULT_FLAGS VM_DATA_FLAGS_TSK_EXEC
#include <asm-generic/getorder.h>
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 0abd389..68e6f25 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -27,5 +27,7 @@
return channel ? 15 : 14;
}
+extern void pcibios_report_status(unsigned int status_mask, int warn);
+
#endif /* __KERNEL__ */
#endif
diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h
index 1a3eedb..e2fcb3c 100644
--- a/arch/arm/include/asm/percpu.h
+++ b/arch/arm/include/asm/percpu.h
@@ -5,7 +5,7 @@
#ifndef _ASM_ARM_PERCPU_H_
#define _ASM_ARM_PERCPU_H_
-#include <asm/thread_info.h>
+register unsigned long current_stack_pointer asm ("sp");
/*
* Same as asm-generic/percpu.h, except that we store the per cpu offset
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h
index 069da39..15f4674 100644
--- a/arch/arm/include/asm/pgalloc.h
+++ b/arch/arm/include/asm/pgalloc.h
@@ -22,17 +22,6 @@
#ifdef CONFIG_ARM_LPAE
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
-{
- return (pmd_t *)get_zeroed_page(GFP_KERNEL);
-}
-
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
-{
- BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
- free_page((unsigned long)pmd);
-}
-
static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
{
set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE));
@@ -76,6 +65,7 @@
#define __HAVE_ARCH_PTE_ALLOC_ONE_KERNEL
#define __HAVE_ARCH_PTE_ALLOC_ONE
+#define __HAVE_ARCH_PGD_FREE
#include <asm-generic/pgalloc.h>
static inline pte_t *
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 50b51ac..baf7d02 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -189,8 +189,10 @@
{
return (pmd_t *)pud;
}
+#define pmd_offset pmd_offset
#define pmd_large(pmd) (pmd_val(pmd) & 2)
+#define pmd_leaf(pmd) (pmd_val(pmd) & 2)
#define pmd_bad(pmd) (pmd_val(pmd) & 2)
#define pmd_present(pmd) (pmd_val(pmd))
@@ -212,8 +214,6 @@
#define pmd_addr_end(addr,end) (end)
#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
-#define pte_special(pte) (0)
-static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
/*
* We don't have huge page support for short descriptors, for the moment
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 8006a56..2b85d17 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -106,26 +106,6 @@
*/
#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
-/*
- * 2nd stage PTE definitions for LPAE.
- */
-#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
-#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
-#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
-#define L_PTE_S2_MT_DEV_SHARED (_AT(pteval_t, 0x1) << 2) /* device */
-#define L_PTE_S2_MT_MASK (_AT(pteval_t, 0xf) << 2)
-
-#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
-#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
-
-#define L_PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[1] */
-#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
-
-/*
- * Hyp-mode PL2 PTE definitions for LPAE.
- */
-#define L_PTE_HYP L_PTE_USER
-
#ifndef __ASSEMBLY__
#define pud_none(pud) (!pud_val(pud))
@@ -136,6 +116,7 @@
#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
PMD_TYPE_SECT)
#define pmd_large(pmd) pmd_sect(pmd)
+#define pmd_leaf(pmd) pmd_sect(pmd)
#define pud_clear(pudp) \
do { \
@@ -154,13 +135,6 @@
return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
}
-/* Find an entry in the second-level page table.. */
-#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
-static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
-{
- return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
-}
-
#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
#define copy_pmd(pmdpd,pmdps) \
@@ -242,7 +216,7 @@
#define pmdp_establish generic_pmdp_establish
/* represent a notpresent pmd by faulting entry, this is used by pmdp_invalidate */
-static inline pmd_t pmd_mknotpresent(pmd_t pmd)
+static inline pmd_t pmd_mkinvalid(pmd_t pmd)
{
return __pmd(pmd_val(pmd) & ~L_PMD_SECT_VALID);
}
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index 010fa1a..d16aba4 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -22,7 +22,6 @@
#define pgd_bad(pgd) (0)
#define pgd_clear(pgdp)
#define kern_addr_valid(addr) (1)
-#define pmd_offset(a, b) ((void *)0)
/* FIXME */
/*
* PMD_SHIFT determines the size of the area a second-level page table can map
@@ -42,12 +41,6 @@
#define swapper_pg_dir ((pgd_t *) 0)
-#define __swp_type(x) (0)
-#define __swp_offset(x) (0)
-#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
typedef pte_t *pte_addr_t;
@@ -79,8 +72,6 @@
#define FIRST_USER_ADDRESS 0UL
-#include <asm-generic/pgtable.h>
-
#else
/*
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 3ae120c..c02f244 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -12,12 +12,11 @@
#ifndef CONFIG_MMU
-#include <asm-generic/4level-fixup.h>
+#include <asm-generic/pgtable-nopud.h>
#include <asm/pgtable-nommu.h>
#else
-#define __ARCH_USE_5LEVEL_HACK
#include <asm-generic/pgtable-nopud.h>
#include <asm/memory.h>
#include <asm/pgtable-hwdef.h>
@@ -80,9 +79,6 @@
extern pgprot_t pgprot_user;
extern pgprot_t pgprot_kernel;
-extern pgprot_t pgprot_hyp_device;
-extern pgprot_t pgprot_s2;
-extern pgprot_t pgprot_s2_device;
#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
@@ -95,12 +91,6 @@
#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
#define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN)
#define PAGE_KERNEL_EXEC pgprot_kernel
-#define PAGE_HYP _MOD_PROT(pgprot_kernel, L_PTE_HYP | L_PTE_XN)
-#define PAGE_HYP_EXEC _MOD_PROT(pgprot_kernel, L_PTE_HYP | L_PTE_RDONLY)
-#define PAGE_HYP_RO _MOD_PROT(pgprot_kernel, L_PTE_HYP | L_PTE_RDONLY | L_PTE_XN)
-#define PAGE_HYP_DEVICE _MOD_PROT(pgprot_hyp_device, L_PTE_HYP)
-#define PAGE_S2 _MOD_PROT(pgprot_s2, L_PTE_S2_RDONLY | L_PTE_XN)
-#define PAGE_S2_DEVICE _MOD_PROT(pgprot_s2_device, L_PTE_S2_RDONLY | L_PTE_XN)
#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN | L_PTE_NONE)
#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
@@ -176,14 +166,6 @@
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-/* to find an entry in a page-table-directory */
-#define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
-
-#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
-
#define pmd_none(pmd) (!pmd_val(pmd))
static inline pte_t *pmd_page_vaddr(pmd_t pmd)
@@ -193,21 +175,6 @@
#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
-#ifndef CONFIG_HIGHPTE
-#define __pte_map(pmd) pmd_page_vaddr(*(pmd))
-#define __pte_unmap(pte) do { } while (0)
-#else
-#define __pte_map(pmd) (pte_t *)kmap_atomic(pmd_page(*(pmd)))
-#define __pte_unmap(pte) kunmap_atomic(pte)
-#endif
-
-#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-
-#define pte_offset_kernel(pmd,addr) (pmd_page_vaddr(*(pmd)) + pte_index(addr))
-
-#define pte_offset_map(pmd,addr) (__pte_map(pmd) + pte_index(addr))
-#define pte_unmap(pte) __pte_unmap(pte)
-
#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
#define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
@@ -252,19 +219,8 @@
extern void __sync_icache_dcache(pte_t pteval);
#endif
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
- pte_t *ptep, pte_t pteval)
-{
- unsigned long ext = 0;
-
- if (addr < TASK_SIZE && pte_valid_user(pteval)) {
- if (!pte_special(pteval))
- __sync_icache_dcache(pteval);
- ext |= PTE_EXT_NG;
- }
-
- set_pte_ext(ptep, pteval, ext);
-}
+void set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pteval);
static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
{
@@ -360,8 +316,6 @@
/* FIXME: this is not correct */
#define kern_addr_valid(addr) (1)
-#include <asm-generic/pgtable.h>
-
/*
* We provide our own arch_get_unmapped_area to cope with VIPT caches.
*/
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 614bf82..b924105 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -14,6 +14,7 @@
#include <asm/ptrace.h>
#include <asm/types.h>
#include <asm/unified.h>
+#include <asm/vdso/processor.h>
#ifdef __KERNEL__
#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \
@@ -85,16 +86,6 @@
unsigned long get_wchan(struct task_struct *p);
-#if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
-#define cpu_relax() \
- do { \
- smp_mb(); \
- __asm__ __volatile__("nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;"); \
- } while (0)
-#else
-#define cpu_relax() barrier()
-#endif
-
#define task_pt_regs(p) \
((struct pt_regs *)(THREAD_START_SP + task_stack_page(p)) - 1)
diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h
index 4ceb4f7..700b8bc 100644
--- a/arch/arm/include/asm/sections.h
+++ b/arch/arm/include/asm/sections.h
@@ -10,8 +10,6 @@
extern char __idmap_text_end[];
extern char __entry_text_start[];
extern char __entry_text_end[];
-extern char __hyp_idmap_text_start[];
-extern char __hyp_idmap_text_end[];
static inline bool in_entry_text(unsigned long addr)
{
@@ -22,9 +20,7 @@
static inline bool in_idmap_text(unsigned long addr)
{
void *a = (void *)addr;
- return memory_contains(__idmap_text_start, __idmap_text_end, a, 1) ||
- memory_contains(__hyp_idmap_text_start, __hyp_idmap_text_end,
- a, 1);
+ return memory_contains(__idmap_text_start, __idmap_text_end, a, 1);
}
#endif /* _ASM_ARM_SECTIONS_H */
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 67d2071..3ae68a1 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -14,7 +14,7 @@
#include <uapi/asm/setup.h>
-#define __tag __used __attribute__((__section__(".taglist.init")))
+#define __tag __used __section(".taglist.init")
#define __tagtable(tag, fn) \
static const struct tagtable __tagtable_##fn __tag = { tag, fn }
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index a91f21e..5d508f5 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -39,11 +39,10 @@
*/
extern void smp_init_cpus(void);
-
/*
- * Provide a function to raise an IPI cross call on CPUs in callmap.
+ * Register IPI interrupts with the arch SMP code
*/
-extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
+extern void set_smp_ipi_range(int ipi_base, int nr_ipi);
/*
* Called from platform specific assembly code, this is the
@@ -113,7 +112,7 @@
#define CPU_METHOD_OF_DECLARE(name, _method, _ops) \
static const struct of_cpu_method __cpu_method_of_table_##name \
- __used __section(__cpu_method_of_table) \
+ __used __section("__cpu_method_of_table") \
= { .method = _method, .ops = _ops }
/*
* set platform specific SMP operations
diff --git a/arch/arm/include/asm/spectre.h b/arch/arm/include/asm/spectre.h
new file mode 100644
index 0000000..85f9e53
--- /dev/null
+++ b/arch/arm/include/asm/spectre.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ASM_SPECTRE_H
+#define __ASM_SPECTRE_H
+
+enum {
+ SPECTRE_UNAFFECTED,
+ SPECTRE_MITIGATED,
+ SPECTRE_VULNERABLE,
+};
+
+enum {
+ __SPECTRE_V2_METHOD_BPIALL,
+ __SPECTRE_V2_METHOD_ICIALLU,
+ __SPECTRE_V2_METHOD_SMC,
+ __SPECTRE_V2_METHOD_HVC,
+ __SPECTRE_V2_METHOD_LOOP8,
+};
+
+enum {
+ SPECTRE_V2_METHOD_BPIALL = BIT(__SPECTRE_V2_METHOD_BPIALL),
+ SPECTRE_V2_METHOD_ICIALLU = BIT(__SPECTRE_V2_METHOD_ICIALLU),
+ SPECTRE_V2_METHOD_SMC = BIT(__SPECTRE_V2_METHOD_SMC),
+ SPECTRE_V2_METHOD_HVC = BIT(__SPECTRE_V2_METHOD_HVC),
+ SPECTRE_V2_METHOD_LOOP8 = BIT(__SPECTRE_V2_METHOD_LOOP8),
+};
+
+#ifdef CONFIG_GENERIC_CPU_VULNERABILITIES
+void spectre_v2_update_state(unsigned int state, unsigned int methods);
+#else
+static inline void spectre_v2_update_state(unsigned int state,
+ unsigned int methods)
+{}
+#endif
+
+int spectre_bhb_update_vectors(unsigned int method);
+
+#endif
diff --git a/arch/arm/include/asm/stage2_pgtable.h b/arch/arm/include/asm/stage2_pgtable.h
deleted file mode 100644
index aaceec7..0000000
--- a/arch/arm/include/asm/stage2_pgtable.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 - ARM Ltd
- *
- * stage2 page table helpers
- */
-
-#ifndef __ARM_S2_PGTABLE_H_
-#define __ARM_S2_PGTABLE_H_
-
-/*
- * kvm_mmu_cache_min_pages() is the number of pages required
- * to install a stage-2 translation. We pre-allocate the entry
- * level table at VM creation. Since we have a 3 level page-table,
- * we need only two pages to add a new mapping.
- */
-#define kvm_mmu_cache_min_pages(kvm) 2
-
-#define stage2_pgd_none(kvm, pgd) pgd_none(pgd)
-#define stage2_pgd_clear(kvm, pgd) pgd_clear(pgd)
-#define stage2_pgd_present(kvm, pgd) pgd_present(pgd)
-#define stage2_pgd_populate(kvm, pgd, pud) pgd_populate(NULL, pgd, pud)
-#define stage2_pud_offset(kvm, pgd, address) pud_offset(pgd, address)
-#define stage2_pud_free(kvm, pud) do { } while (0)
-
-#define stage2_pud_none(kvm, pud) pud_none(pud)
-#define stage2_pud_clear(kvm, pud) pud_clear(pud)
-#define stage2_pud_present(kvm, pud) pud_present(pud)
-#define stage2_pud_populate(kvm, pud, pmd) pud_populate(NULL, pud, pmd)
-#define stage2_pmd_offset(kvm, pud, address) pmd_offset(pud, address)
-#define stage2_pmd_free(kvm, pmd) free_page((unsigned long)pmd)
-
-#define stage2_pud_huge(kvm, pud) pud_huge(pud)
-
-/* Open coded p*d_addr_end that can deal with 64bit addresses */
-static inline phys_addr_t
-stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)
-{
- phys_addr_t boundary = (addr + PGDIR_SIZE) & PGDIR_MASK;
-
- return (boundary - 1 < end - 1) ? boundary : end;
-}
-
-#define stage2_pud_addr_end(kvm, addr, end) (end)
-
-static inline phys_addr_t
-stage2_pmd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)
-{
- phys_addr_t boundary = (addr + PMD_SIZE) & PMD_MASK;
-
- return (boundary - 1 < end - 1) ? boundary : end;
-}
-
-#define stage2_pgd_index(kvm, addr) pgd_index(addr)
-
-#define stage2_pte_table_empty(kvm, ptep) kvm_page_empty(ptep)
-#define stage2_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp)
-#define stage2_pud_table_empty(kvm, pudp) false
-
-static inline bool kvm_stage2_has_pud(struct kvm *kvm)
-{
- return false;
-}
-
-#define S2_PMD_MASK PMD_MASK
-#define S2_PMD_SIZE PMD_SIZE
-#define S2_PUD_MASK PUD_MASK
-#define S2_PUD_SIZE PUD_SIZE
-
-static inline bool kvm_stage2_has_pmd(struct kvm *kvm)
-{
- return true;
-}
-
-#endif /* __ARM_S2_PGTABLE_H_ */
diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h
index d3e937d..007d8fe 100644
--- a/arch/arm/include/asm/switch_to.h
+++ b/arch/arm/include/asm/switch_to.h
@@ -10,7 +10,7 @@
* to ensure that the maintenance completes in case we migrate to another
* CPU.
*/
-#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
+#if defined(CONFIG_PREEMPTION) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
#define __complete_pending_tlbi() dsb(ish)
#else
#define __complete_pending_tlbi()
diff --git a/arch/arm/include/asm/tcm.h b/arch/arm/include/asm/tcm.h
index b845b10..d8bd8a4 100644
--- a/arch/arm/include/asm/tcm.h
+++ b/arch/arm/include/asm/tcm.h
@@ -16,13 +16,13 @@
#include <linux/compiler.h>
/* Tag variables with this */
-#define __tcmdata __section(.tcm.data)
+#define __tcmdata __section(".tcm.data")
/* Tag constants with this */
-#define __tcmconst __section(.tcm.rodata)
+#define __tcmconst __section(".tcm.rodata")
/* Tag functions inside TCM called from outside TCM with this */
-#define __tcmfunc __attribute__((long_call)) __section(.tcm.text) noinline
+#define __tcmfunc __attribute__((long_call)) __section(".tcm.text") noinline
/* Tag function inside TCM called from inside TCM with this */
-#define __tcmlocalfunc __section(.tcm.text)
+#define __tcmlocalfunc __section(".tcm.text")
void *tcm_alloc(size_t len);
void tcm_free(void *addr, size_t len);
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 0d0d517..536b6b9 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -76,11 +76,6 @@
}
/*
- * how to get the current stack pointer in C
- */
-register unsigned long current_stack_pointer asm ("sp");
-
-/*
* how to get the thread information struct from C
*/
static inline struct thread_info *current_thread_info(void) __attribute_const__;
@@ -141,7 +136,6 @@
#define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentation */
#define TIF_SECCOMP 7 /* seccomp syscall filtering active */
-#define TIF_NOHZ 12 /* in adaptive nohz mode */
#define TIF_USING_IWMMXT 17
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
#define TIF_RESTORE_SIGMASK 20
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 669474a..b8cbe03 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -27,7 +27,6 @@
#else /* !CONFIG_MMU */
#include <linux/swap.h>
-#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
static inline void __tlb_remove_table(void *_table)
@@ -37,10 +36,6 @@
#include <asm-generic/tlb.h>
-#ifndef CONFIG_HAVE_RCU_TABLE_FREE
-#define tlb_remove_table(tlb, entry) tlb_remove_page(tlb, entry)
-#endif
-
static inline void
__pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, unsigned long addr)
{
@@ -64,6 +59,7 @@
#ifdef CONFIG_ARM_LPAE
struct page *page = virt_to_page(pmdp);
+ pgtable_pmd_page_dtor(page);
tlb_remove_table(tlb, page);
#endif
}
diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h
index 8a0fae9..470299e 100644
--- a/arch/arm/include/asm/topology.h
+++ b/arch/arm/include/asm/topology.h
@@ -7,8 +7,13 @@
#include <linux/cpumask.h>
#include <linux/arch_topology.h>
+/* big.LITTLE switcher is incompatible with frequency invariance */
+#ifndef CONFIG_BL_SWITCHER
/* Replace task scheduler's default frequency-invariant accounting */
+#define arch_set_freq_scale topology_set_freq_scale
#define arch_scale_freq_capacity topology_get_freq_scale
+#define arch_scale_freq_invariant topology_scale_freq_invariant
+#endif
/* Replace task scheduler's default cpu-invariant accounting */
#define arch_scale_cpu_capacity topology_get_cpu_scale
@@ -16,6 +21,10 @@
/* Enable topology flag updates */
#define arch_update_cpu_topology topology_update_cpu_topology
+/* Replace task scheduler's default thermal pressure API */
+#define arch_scale_thermal_pressure topology_get_thermal_pressure
+#define arch_set_thermal_pressure topology_set_thermal_pressure
+
#else
static inline void init_cpu_topology(void) { }
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h
index 172b08f..987fefb 100644
--- a/arch/arm/include/asm/traps.h
+++ b/arch/arm/include/asm/traps.h
@@ -29,7 +29,8 @@
}
extern void __init early_trap_init(void *);
-extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame);
+extern void dump_backtrace_entry(unsigned long where, unsigned long from,
+ unsigned long frame, const char *loglvl);
extern void ptrace_break(struct pt_regs *regs);
extern void *vectors_page;
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 98c6b91..d9db752 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -76,9 +76,13 @@
modify_domain(DOMAIN_KERNEL, fs ? DOMAIN_CLIENT : DOMAIN_MANAGER);
}
-#define segment_eq(a, b) ((a) == (b))
+#define uaccess_kernel() (get_fs() == KERNEL_DS)
-/* We use 33-bit arithmetic here... */
+/*
+ * We use 33-bit arithmetic here. Success returns zero, failure returns
+ * addr_limit. We take advantage that addr_limit will be zero for KERNEL_DS,
+ * so this will always return success in that case.
+ */
#define __range_ok(addr, size) ({ \
unsigned long flag, roksum; \
__chk_user_ptr(addr); \
@@ -196,6 +200,7 @@
register unsigned long __l asm("r1") = __limit; \
register int __e asm("r0"); \
unsigned int __ua_flags = uaccess_save_and_enable(); \
+ int __tmp_e; \
switch (sizeof(*(__p))) { \
case 1: \
if (sizeof((x)) >= 8) \
@@ -223,9 +228,10 @@
break; \
default: __e = __get_user_bad(); break; \
} \
+ __tmp_e = __e; \
uaccess_restore(__ua_flags); \
x = (typeof(*(p))) __r2; \
- __e; \
+ __tmp_e; \
})
#define get_user(x, p) \
@@ -263,7 +269,7 @@
*/
#define USER_DS KERNEL_DS
-#define segment_eq(a, b) (1)
+#define uaccess_kernel() (true)
#define __addr_ok(addr) ((void)(addr), 1)
#define __range_ok(addr, size) ((void)(addr), 0)
#define get_fs() (KERNEL_DS)
diff --git a/arch/arm/include/asm/unwind.h b/arch/arm/include/asm/unwind.h
index 6e282c3..0f8a343 100644
--- a/arch/arm/include/asm/unwind.h
+++ b/arch/arm/include/asm/unwind.h
@@ -36,7 +36,8 @@
unsigned long text_addr,
unsigned long text_size);
extern void unwind_table_del(struct unwind_table *tab);
-extern void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk);
+extern void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk,
+ const char *loglvl);
#endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/include/asm/vdso/clocksource.h b/arch/arm/include/asm/vdso/clocksource.h
new file mode 100644
index 0000000..50c0b19
--- /dev/null
+++ b/arch/arm/include/asm/vdso/clocksource.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_VDSOCLOCKSOURCE_H
+#define __ASM_VDSOCLOCKSOURCE_H
+
+#define VDSO_ARCH_CLOCKMODES \
+ VDSO_CLOCKMODE_ARCHTIMER
+
+#endif /* __ASM_VDSOCLOCKSOURCE_H */
diff --git a/arch/arm/include/asm/vdso/cp15.h b/arch/arm/include/asm/vdso/cp15.h
new file mode 100644
index 0000000..bed16fa
--- /dev/null
+++ b/arch/arm/include/asm/vdso/cp15.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 ARM Ltd.
+ */
+#ifndef __ASM_VDSO_CP15_H
+#define __ASM_VDSO_CP15_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_CPU_CP15
+
+#include <linux/stringify.h>
+
+#define __ACCESS_CP15(CRn, Op1, CRm, Op2) \
+ "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
+#define __ACCESS_CP15_64(Op1, CRm) \
+ "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
+
+#define __read_sysreg(r, w, c, t) ({ \
+ t __val; \
+ asm volatile(r " " c : "=r" (__val)); \
+ __val; \
+})
+#define read_sysreg(...) __read_sysreg(__VA_ARGS__)
+
+#define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v)))
+#define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__)
+
+#define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
+#define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
+
+#define CNTVCT __ACCESS_CP15_64(1, c14)
+
+#endif /* CONFIG_CPU_CP15 */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_VDSO_CP15_H */
diff --git a/arch/arm/include/asm/vdso/gettimeofday.h b/arch/arm/include/asm/vdso/gettimeofday.h
new file mode 100644
index 0000000..2134cbd
--- /dev/null
+++ b/arch/arm/include/asm/vdso/gettimeofday.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 ARM Limited
+ */
+#ifndef __ASM_VDSO_GETTIMEOFDAY_H
+#define __ASM_VDSO_GETTIMEOFDAY_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/barrier.h>
+#include <asm/errno.h>
+#include <asm/unistd.h>
+#include <asm/vdso/cp15.h>
+#include <uapi/linux/time.h>
+
+#define VDSO_HAS_CLOCK_GETRES 1
+
+extern struct vdso_data *__get_datapage(void);
+
+static __always_inline int gettimeofday_fallback(
+ struct __kernel_old_timeval *_tv,
+ struct timezone *_tz)
+{
+ register struct timezone *tz asm("r1") = _tz;
+ register struct __kernel_old_timeval *tv asm("r0") = _tv;
+ register long ret asm ("r0");
+ register long nr asm("r7") = __NR_gettimeofday;
+
+ asm volatile(
+ " swi #0\n"
+ : "=r" (ret)
+ : "r" (tv), "r" (tz), "r" (nr)
+ : "memory");
+
+ return ret;
+}
+
+static __always_inline long clock_gettime_fallback(
+ clockid_t _clkid,
+ struct __kernel_timespec *_ts)
+{
+ register struct __kernel_timespec *ts asm("r1") = _ts;
+ register clockid_t clkid asm("r0") = _clkid;
+ register long ret asm ("r0");
+ register long nr asm("r7") = __NR_clock_gettime64;
+
+ asm volatile(
+ " swi #0\n"
+ : "=r" (ret)
+ : "r" (clkid), "r" (ts), "r" (nr)
+ : "memory");
+
+ return ret;
+}
+
+static __always_inline long clock_gettime32_fallback(
+ clockid_t _clkid,
+ struct old_timespec32 *_ts)
+{
+ register struct old_timespec32 *ts asm("r1") = _ts;
+ register clockid_t clkid asm("r0") = _clkid;
+ register long ret asm ("r0");
+ register long nr asm("r7") = __NR_clock_gettime;
+
+ asm volatile(
+ " swi #0\n"
+ : "=r" (ret)
+ : "r" (clkid), "r" (ts), "r" (nr)
+ : "memory");
+
+ return ret;
+}
+
+static __always_inline int clock_getres_fallback(
+ clockid_t _clkid,
+ struct __kernel_timespec *_ts)
+{
+ register struct __kernel_timespec *ts asm("r1") = _ts;
+ register clockid_t clkid asm("r0") = _clkid;
+ register long ret asm ("r0");
+ register long nr asm("r7") = __NR_clock_getres_time64;
+
+ asm volatile(
+ " swi #0\n"
+ : "=r" (ret)
+ : "r" (clkid), "r" (ts), "r" (nr)
+ : "memory");
+
+ return ret;
+}
+
+static __always_inline int clock_getres32_fallback(
+ clockid_t _clkid,
+ struct old_timespec32 *_ts)
+{
+ register struct old_timespec32 *ts asm("r1") = _ts;
+ register clockid_t clkid asm("r0") = _clkid;
+ register long ret asm ("r0");
+ register long nr asm("r7") = __NR_clock_getres;
+
+ asm volatile(
+ " swi #0\n"
+ : "=r" (ret)
+ : "r" (clkid), "r" (ts), "r" (nr)
+ : "memory");
+
+ return ret;
+}
+
+static inline bool arm_vdso_hres_capable(void)
+{
+ return IS_ENABLED(CONFIG_ARM_ARCH_TIMER);
+}
+#define __arch_vdso_hres_capable arm_vdso_hres_capable
+
+static __always_inline u64 __arch_get_hw_counter(int clock_mode,
+ const struct vdso_data *vd)
+{
+#ifdef CONFIG_ARM_ARCH_TIMER
+ u64 cycle_now;
+
+ /*
+ * Core checks for mode already, so this raced against a concurrent
+ * update. Return something. Core will do another round and then
+ * see the mode change and fallback to the syscall.
+ */
+ if (clock_mode == VDSO_CLOCKMODE_NONE)
+ return 0;
+
+ isb();
+ cycle_now = read_sysreg(CNTVCT);
+
+ return cycle_now;
+#else
+ /* Make GCC happy. This is compiled out anyway */
+ return 0;
+#endif
+}
+
+static __always_inline const struct vdso_data *__arch_get_vdso_data(void)
+{
+ return __get_datapage();
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_VDSO_GETTIMEOFDAY_H */
diff --git a/arch/arm/include/asm/vdso/processor.h b/arch/arm/include/asm/vdso/processor.h
new file mode 100644
index 0000000..45efb3f
--- /dev/null
+++ b/arch/arm/include/asm/vdso/processor.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 ARM Ltd.
+ */
+#ifndef __ASM_VDSO_PROCESSOR_H
+#define __ASM_VDSO_PROCESSOR_H
+
+#ifndef __ASSEMBLY__
+
+#if __LINUX_ARM_ARCH__ == 6 || defined(CONFIG_ARM_ERRATA_754327)
+#define cpu_relax() \
+ do { \
+ smp_mb(); \
+ __asm__ __volatile__("nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;"); \
+ } while (0)
+#else
+#define cpu_relax() barrier()
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_VDSO_PROCESSOR_H */
diff --git a/arch/arm/include/asm/vdso/vsyscall.h b/arch/arm/include/asm/vdso/vsyscall.h
new file mode 100644
index 0000000..47e41ae
--- /dev/null
+++ b/arch/arm/include/asm/vdso/vsyscall.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_VDSO_VSYSCALL_H
+#define __ASM_VDSO_VSYSCALL_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/timekeeper_internal.h>
+#include <vdso/datapage.h>
+#include <asm/cacheflush.h>
+
+extern struct vdso_data *vdso_data;
+extern bool cntvct_ok;
+
+/*
+ * Update the vDSO data page to keep in sync with kernel timekeeping.
+ */
+static __always_inline
+struct vdso_data *__arm_get_k_vdso_data(void)
+{
+ return vdso_data;
+}
+#define __arch_get_k_vdso_data __arm_get_k_vdso_data
+
+static __always_inline
+void __arm_sync_vdso_data(struct vdso_data *vdata)
+{
+ flush_dcache_page(virt_to_page(vdata));
+}
+#define __arch_sync_vdso_data __arm_sync_vdso_data
+
+/* The asm-generic header needs to be included after the definitions above */
+#include <asm-generic/vdso/vsyscall.h>
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_VDSO_VSYSCALL_H */
diff --git a/arch/arm/include/asm/vdso_datapage.h b/arch/arm/include/asm/vdso_datapage.h
index 7910abf..bef68f5 100644
--- a/arch/arm/include/asm/vdso_datapage.h
+++ b/arch/arm/include/asm/vdso_datapage.h
@@ -11,35 +11,12 @@
#ifndef __ASSEMBLY__
+#include <vdso/datapage.h>
#include <asm/page.h>
-/* Try to be cache-friendly on systems that don't implement the
- * generic timer: fit the unconditionally updated fields in the first
- * 32 bytes.
- */
-struct vdso_data {
- u32 seq_count; /* sequence count - odd during updates */
- u16 tk_is_cntvct; /* fall back to syscall if false */
- u16 cs_shift; /* clocksource shift */
- u32 xtime_coarse_sec; /* coarse time */
- u32 xtime_coarse_nsec;
-
- u32 wtm_clock_sec; /* wall to monotonic offset */
- u32 wtm_clock_nsec;
- u32 xtime_clock_sec; /* CLOCK_REALTIME - seconds */
- u32 cs_mult; /* clocksource multiplier */
-
- u64 cs_cycle_last; /* last cycle value */
- u64 cs_mask; /* clocksource mask */
-
- u64 xtime_clock_snsec; /* CLOCK_REALTIME sub-ns base */
- u32 tz_minuteswest; /* timezone info for gettimeofday(2) */
- u32 tz_dsttime;
-};
-
union vdso_data_store {
- struct vdso_data data;
- u8 page[PAGE_SIZE];
+ struct vdso_data data[CS_BASES];
+ u8 page[PAGE_SIZE];
};
#endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/include/asm/vermagic.h b/arch/arm/include/asm/vermagic.h
new file mode 100644
index 0000000..62ce94e
--- /dev/null
+++ b/arch/arm/include/asm/vermagic.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_VERMAGIC_H
+#define _ASM_VERMAGIC_H
+
+#include <linux/stringify.h>
+
+/*
+ * Add the ARM architecture version to the version magic string
+ */
+#define MODULE_ARCH_VERMAGIC_ARMVSN "ARMv" __stringify(__LINUX_ARM_ARCH__) " "
+
+/* Add __virt_to_phys patching state as well */
+#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
+#define MODULE_ARCH_VERMAGIC_P2V "p2v8 "
+#else
+#define MODULE_ARCH_VERMAGIC_P2V ""
+#endif
+
+/* Add instruction set architecture tag to distinguish ARM/Thumb kernels */
+#ifdef CONFIG_THUMB2_KERNEL
+#define MODULE_ARCH_VERMAGIC_ARMTHUMB "thumb2 "
+#else
+#define MODULE_ARCH_VERMAGIC_ARMTHUMB ""
+#endif
+
+#define MODULE_ARCH_VERMAGIC \
+ MODULE_ARCH_VERMAGIC_ARMVSN \
+ MODULE_ARCH_VERMAGIC_ARMTHUMB \
+ MODULE_ARCH_VERMAGIC_P2V
+
+#endif /* _ASM_VERMAGIC_H */
diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h
index 7157d2a..19928bf 100644
--- a/arch/arm/include/asm/vfp.h
+++ b/arch/arm/include/asm/vfp.h
@@ -9,6 +9,7 @@
#ifndef __ASM_VFP_H
#define __ASM_VFP_H
+#ifndef CONFIG_AS_VFP_VMRS_FPINST
#define FPSID cr0
#define FPSCR cr1
#define MVFR1 cr6
@@ -16,6 +17,7 @@
#define FPEXC cr8
#define FPINST cr9
#define FPINST2 cr10
+#endif
/* FPSID bits */
#define FPSID_IMPLEMENTER_BIT (24)
diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index 628c336..ba0d4cb 100644
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -8,7 +8,16 @@
#include <asm/vfp.h>
-@ Macros to allow building with old toolkits (with no VFP support)
+#ifdef CONFIG_AS_VFP_VMRS_FPINST
+ .macro VFPFMRX, rd, sysreg, cond
+ vmrs\cond \rd, \sysreg
+ .endm
+
+ .macro VFPFMXR, sysreg, rd, cond
+ vmsr\cond \sysreg, \rd
+ .endm
+#else
+ @ Macros to allow building with old toolkits (with no VFP support)
.macro VFPFMRX, rd, sysreg, cond
MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg
.endm
@@ -16,26 +25,29 @@
.macro VFPFMXR, sysreg, rd, cond
MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd
.endm
+#endif
@ read all the working registers back into the VFP
.macro VFPFLDMIA, base, tmp
+ .fpu vfpv2
#if __LINUX_ARM_ARCH__ < 6
- LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15}
+ fldmiax \base!, {d0-d15}
#else
- LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
+ vldmia \base!, {d0-d15}
#endif
#ifdef CONFIG_VFPv3
+ .fpu vfpv3
#if __LINUX_ARM_ARCH__ <= 6
ldr \tmp, =elf_hwcap @ may not have MVFR regs
ldr \tmp, [\tmp, #0]
tst \tmp, #HWCAP_VFPD32
- ldclne p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
+ vldmiane \base!, {d16-d31}
addeq \base, \base, #32*4 @ step over unused register space
#else
VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
cmp \tmp, #2 @ 32 x 64bit registers?
- ldcleq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
+ vldmiaeq \base!, {d16-d31}
addne \base, \base, #32*4 @ step over unused register space
#endif
#endif
@@ -44,22 +56,23 @@
@ write all the working registers out of the VFP
.macro VFPFSTMIA, base, tmp
#if __LINUX_ARM_ARCH__ < 6
- STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
+ fstmiax \base!, {d0-d15}
#else
- STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
+ vstmia \base!, {d0-d15}
#endif
#ifdef CONFIG_VFPv3
+ .fpu vfpv3
#if __LINUX_ARM_ARCH__ <= 6
ldr \tmp, =elf_hwcap @ may not have MVFR regs
ldr \tmp, [\tmp, #0]
tst \tmp, #HWCAP_VFPD32
- stclne p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
+ vstmiane \base!, {d16-d31}
addeq \base, \base, #32*4 @ step over unused register space
#else
VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
cmp \tmp, #2 @ 32 x 64bit registers?
- stcleq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
+ vstmiaeq \base!, {d16-d31}
addne \base, \base, #32*4 @ step over unused register space
#endif
#endif
diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h
index 17c26cc..dd9697b 100644
--- a/arch/arm/include/asm/virt.h
+++ b/arch/arm/include/asm/virt.h
@@ -39,8 +39,6 @@
sync_cache_r(&__boot_cpu_mode);
}
-void __hyp_set_vectors(unsigned long phys_vector_base);
-void __hyp_reset_vectors(void);
#else
#define __boot_cpu_mode (SVC_MODE)
#define sync_boot_mode()
@@ -67,18 +65,6 @@
return false;
}
-static inline bool has_vhe(void)
-{
- return false;
-}
-
-/* The section containing the hypervisor idmap text */
-extern char __hyp_idmap_text_start[];
-extern char __hyp_idmap_text_end[];
-
-/* The section containing the hypervisor text */
-extern char __hyp_text_start[];
-extern char __hyp_text_end[];
#endif
#else
@@ -87,9 +73,6 @@
#define HVC_SET_VECTORS 0
#define HVC_SOFT_RESTART 1
-#define HVC_RESET_VECTORS 2
-
-#define HVC_STUB_HCALL_NR 3
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/vmalloc.h b/arch/arm/include/asm/vmalloc.h
new file mode 100644
index 0000000..a9b3718
--- /dev/null
+++ b/arch/arm/include/asm/vmalloc.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_ARM_VMALLOC_H
+#define _ASM_ARM_VMALLOC_H
+
+#endif /* _ASM_ARM_VMALLOC_H */
diff --git a/arch/arm/kernel/vmlinux.lds.h b/arch/arm/include/asm/vmlinux.lds.h
similarity index 63%
rename from arch/arm/kernel/vmlinux.lds.h
rename to arch/arm/include/asm/vmlinux.lds.h
index 8247bc1..fad45c8 100644
--- a/arch/arm/kernel/vmlinux.lds.h
+++ b/arch/arm/include/asm/vmlinux.lds.h
@@ -1,4 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm-generic/vmlinux.lds.h>
#ifdef CONFIG_HOTPLUG_CPU
#define ARM_CPU_DISCARD(x)
@@ -25,26 +26,30 @@
#define ARM_MMU_DISCARD(x) x
#endif
+/*
+ * ld.lld does not support NOCROSSREFS:
+ * https://github.com/ClangBuiltLinux/linux/issues/1609
+ */
+#ifdef CONFIG_LD_IS_LLD
+#define NOCROSSREFS
+#endif
+
+/* Set start/end symbol names to the LMA for the section */
+#define ARM_LMA(sym, section) \
+ sym##_start = LOADADDR(section); \
+ sym##_end = LOADADDR(section) + SIZEOF(section)
+
#define PROC_INFO \
. = ALIGN(4); \
__proc_info_begin = .; \
*(.proc.info.init) \
__proc_info_end = .;
-#define HYPERVISOR_TEXT \
- __hyp_text_start = .; \
- *(.hyp.text) \
- __hyp_text_end = .;
-
#define IDMAP_TEXT \
ALIGN_FUNCTION(); \
__idmap_text_start = .; \
*(.idmap.text) \
__idmap_text_end = .; \
- . = ALIGN(PAGE_SIZE); \
- __hyp_idmap_text_start = .; \
- *(.hyp.idmap.text) \
- __hyp_idmap_text_end = .;
#define ARM_DISCARD \
*(.ARM.exidx.exit.text) \
@@ -58,8 +63,29 @@
EXIT_CALL \
ARM_MMU_DISCARD(*(.text.fixup)) \
ARM_MMU_DISCARD(*(__ex_table)) \
- *(.discard) \
- *(.discard.*)
+ COMMON_DISCARDS
+
+/*
+ * Sections that should stay zero sized, which is safer to explicitly
+ * check instead of blindly discarding.
+ */
+#define ARM_ASSERTS \
+ .plt : { \
+ *(.iplt) *(.rel.iplt) *(.iplt) *(.igot.plt) \
+ } \
+ ASSERT(SIZEOF(.plt) == 0, \
+ "Unexpected run-time procedure linkages detected!")
+
+#define ARM_DETAILS \
+ ELF_DETAILS \
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+#define ARM_STUBS_TEXT \
+ *(.gnu.warning) \
+ *(.glue_7) \
+ *(.glue_7t) \
+ *(.vfp11_veneer) \
+ *(.v4_bx)
#define ARM_TEXT \
IDMAP_TEXT \
@@ -72,11 +98,8 @@
SCHED_TEXT \
CPUIDLE_TEXT \
LOCK_TEXT \
- HYPERVISOR_TEXT \
KPROBES_TEXT \
- *(.gnu.warning) \
- *(.glue_7) \
- *(.glue_7t) \
+ ARM_STUBS_TEXT \
. = ALIGN(4); \
*(.got) /* Global offset table */ \
ARM_CPU_KEEP(PROC_INFO)
@@ -100,19 +123,31 @@
* only thing that matters is their relative offsets
*/
#define ARM_VECTORS \
- __vectors_start = .; \
- .vectors 0xffff0000 : AT(__vectors_start) { \
- *(.vectors) \
+ __vectors_lma = .; \
+ OVERLAY 0xffff0000 : NOCROSSREFS AT(__vectors_lma) { \
+ .vectors { \
+ *(.vectors) \
+ } \
+ .vectors.bhb.loop8 { \
+ *(.vectors.bhb.loop8) \
+ } \
+ .vectors.bhb.bpiall { \
+ *(.vectors.bhb.bpiall) \
+ } \
} \
- . = __vectors_start + SIZEOF(.vectors); \
- __vectors_end = .; \
+ ARM_LMA(__vectors, .vectors); \
+ ARM_LMA(__vectors_bhb_loop8, .vectors.bhb.loop8); \
+ ARM_LMA(__vectors_bhb_bpiall, .vectors.bhb.bpiall); \
+ . = __vectors_lma + SIZEOF(.vectors) + \
+ SIZEOF(.vectors.bhb.loop8) + \
+ SIZEOF(.vectors.bhb.bpiall); \
\
- __stubs_start = .; \
- .stubs ADDR(.vectors) + 0x1000 : AT(__stubs_start) { \
+ __stubs_lma = .; \
+ .stubs ADDR(.vectors) + 0x1000 : AT(__stubs_lma) { \
*(.stubs) \
} \
- . = __stubs_start + SIZEOF(.stubs); \
- __stubs_end = .; \
+ ARM_LMA(__stubs, .stubs); \
+ . = __stubs_lma + SIZEOF(.stubs); \
\
PROVIDE(vector_fiq_offset = vector_fiq - ADDR(.vectors));
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index 31bbc80..dc7f6e9 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -1 +1,6 @@
#include <xen/arm/page.h>
+
+static inline bool xen_kernel_unmapped_at_usr(void)
+{
+ return false;
+}
diff --git a/arch/arm/include/debug/8250.S b/arch/arm/include/debug/8250.S
index e4a036f..e3692a3 100644
--- a/arch/arm/include/debug/8250.S
+++ b/arch/arm/include/debug/8250.S
@@ -45,10 +45,11 @@
bne 1002b
.endm
- .macro waituart,rd,rx
-#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL
+ .macro waituarttxrdy,rd,rx
+ .endm
+
+ .macro waituartcts,rd,rx
1001: load \rd, [\rx, #UART_MSR << UART_SHIFT]
tst \rd, #UART_MSR_CTS
beq 1001b
-#endif
.endm
diff --git a/arch/arm/include/debug/asm9260.S b/arch/arm/include/debug/asm9260.S
index 0da1eb6..5a0ce14 100644
--- a/arch/arm/include/debug/asm9260.S
+++ b/arch/arm/include/debug/asm9260.S
@@ -11,7 +11,10 @@
ldr \rv, = CONFIG_DEBUG_UART_VIRT
.endm
- .macro waituart,rd,rx
+ .macro waituarttxrdy,rd,rx
+ .endm
+
+ .macro waituartcts,rd,rx
.endm
.macro senduart,rd,rx
diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S
index 6c91cba..1772282 100644
--- a/arch/arm/include/debug/at91.S
+++ b/arch/arm/include/debug/at91.S
@@ -19,12 +19,15 @@
strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
.endm
- .macro waituart,rd,rx
+ .macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
beq 1001b
.endm
+ .macro waituartcts,rd,rx
+ .endm
+
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
diff --git a/arch/arm/include/debug/bcm63xx.S b/arch/arm/include/debug/bcm63xx.S
index 06a8962..da65abb 100644
--- a/arch/arm/include/debug/bcm63xx.S
+++ b/arch/arm/include/debug/bcm63xx.S
@@ -17,12 +17,15 @@
strb \rd, [\rx, #UART_FIFO_REG]
.endm
- .macro waituart, rd, rx
+ .macro waituarttxrdy, rd, rx
1001: ldr \rd, [\rx, #UART_IR_REG]
tst \rd, #(1 << UART_IR_TXEMPTY)
beq 1001b
.endm
+ .macro waituartcts, rd, rx
+ .endm
+
.macro busyuart, rd, rx
1002: ldr \rd, [\rx, #UART_IR_REG]
tst \rd, #(1 << UART_IR_TXTRESH)
diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S
index bf8702e..0ff32ff 100644
--- a/arch/arm/include/debug/brcmstb.S
+++ b/arch/arm/include/debug/brcmstb.S
@@ -31,6 +31,9 @@
#define UARTA_7268 UARTA_7255
#define UARTA_7271 UARTA_7268
#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
+#define UARTA_7216 UARTA_7278
+#define UARTA_72164 UARTA_7278
+#define UARTA_72165 UARTA_7278
#define UARTA_7364 REG_PHYS_ADDR(0x40b000)
#define UARTA_7366 UARTA_7364
#define UARTA_74371 REG_PHYS_ADDR(0x406b00)
@@ -82,17 +85,20 @@
/* Chip specific detection starts here */
20: checkuart(\rp, \rv, 0x33900000, 3390)
-21: checkuart(\rp, \rv, 0x72500000, 7250)
-22: checkuart(\rp, \rv, 0x72550000, 7255)
-23: checkuart(\rp, \rv, 0x72600000, 7260)
-24: checkuart(\rp, \rv, 0x72680000, 7268)
-25: checkuart(\rp, \rv, 0x72710000, 7271)
-26: checkuart(\rp, \rv, 0x72780000, 7278)
-27: checkuart(\rp, \rv, 0x73640000, 7364)
-28: checkuart(\rp, \rv, 0x73660000, 7366)
-29: checkuart(\rp, \rv, 0x07437100, 74371)
-30: checkuart(\rp, \rv, 0x74390000, 7439)
-31: checkuart(\rp, \rv, 0x74450000, 7445)
+21: checkuart(\rp, \rv, 0x72160000, 7216)
+22: checkuart(\rp, \rv, 0x07216400, 72164)
+23: checkuart(\rp, \rv, 0x07216500, 72165)
+24: checkuart(\rp, \rv, 0x72500000, 7250)
+25: checkuart(\rp, \rv, 0x72550000, 7255)
+26: checkuart(\rp, \rv, 0x72600000, 7260)
+27: checkuart(\rp, \rv, 0x72680000, 7268)
+28: checkuart(\rp, \rv, 0x72710000, 7271)
+29: checkuart(\rp, \rv, 0x72780000, 7278)
+30: checkuart(\rp, \rv, 0x73640000, 7364)
+31: checkuart(\rp, \rv, 0x73660000, 7366)
+32: checkuart(\rp, \rv, 0x07437100, 74371)
+33: checkuart(\rp, \rv, 0x74390000, 7439)
+34: checkuart(\rp, \rv, 0x74450000, 7445)
/* No valid UART found */
90: mov \rp, #0
@@ -140,7 +146,10 @@
bne 1002b
.endm
- .macro waituart,rd,rx
+ .macro waituarttxrdy,rd,rx
+ .endm
+
+ .macro waituartcts,rd,rx
.endm
/*
diff --git a/arch/arm/include/debug/clps711x.S b/arch/arm/include/debug/clps711x.S
index 774a67a..a983d12 100644
--- a/arch/arm/include/debug/clps711x.S
+++ b/arch/arm/include/debug/clps711x.S
@@ -20,7 +20,10 @@
ldr \rp, =CLPS711X_UART_PADDR
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
.endm
.macro senduart,rd,rx
diff --git a/arch/arm/include/debug/dc21285.S b/arch/arm/include/debug/dc21285.S
index d7e8c71..4ec0e5e 100644
--- a/arch/arm/include/debug/dc21285.S
+++ b/arch/arm/include/debug/dc21285.S
@@ -34,5 +34,8 @@
bne 1001b
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
.endm
diff --git a/arch/arm/include/debug/digicolor.S b/arch/arm/include/debug/digicolor.S
index 256f5f4..443674c 100644
--- a/arch/arm/include/debug/digicolor.S
+++ b/arch/arm/include/debug/digicolor.S
@@ -21,7 +21,10 @@
strb \rd, [\rx, #UA0_EMI_REC]
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
.endm
.macro busyuart,rd,rx
diff --git a/arch/arm/include/debug/efm32.S b/arch/arm/include/debug/efm32.S
index 5ed5028..b0083d6 100644
--- a/arch/arm/include/debug/efm32.S
+++ b/arch/arm/include/debug/efm32.S
@@ -29,7 +29,10 @@
strb \rd, [\rx, #UARTn_TXDATA]
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #UARTn_STATUS]
tst \rd, #UARTn_STATUS_TXBL
beq 1001b
diff --git a/arch/arm/include/debug/icedcc.S b/arch/arm/include/debug/icedcc.S
index 74a0dd0..d5e65da 100644
--- a/arch/arm/include/debug/icedcc.S
+++ b/arch/arm/include/debug/icedcc.S
@@ -23,7 +23,10 @@
beq 1001b
.endm
- .macro waituart, rd, rx
+ .macro waituartcts, rd, rx
+ .endm
+
+ .macro waituarttxrdy, rd, rx
mov \rd, #0x2000000
1001:
subs \rd, \rd, #1
@@ -47,7 +50,10 @@
beq 1001b
.endm
- .macro waituart, rd, rx
+ .macro waituartcts, rd, rx
+ .endm
+
+ .macro waituarttxrdy, rd, rx
mov \rd, #0x10000000
1001:
subs \rd, \rd, #1
@@ -72,7 +78,10 @@
.endm
- .macro waituart, rd, rx
+ .macro waituartcts, rd, rx
+ .endm
+
+ .macro waituarttxrdy, rd, rx
mov \rd, #0x2000000
1001:
subs \rd, \rd, #1
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index c8eb83d..3edbb3c 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -11,13 +11,6 @@
#define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR
#define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n)
-#define IMX21_UART1_BASE_ADDR 0x1000a000
-#define IMX21_UART2_BASE_ADDR 0x1000b000
-#define IMX21_UART3_BASE_ADDR 0x1000c000
-#define IMX21_UART4_BASE_ADDR 0x1000d000
-#define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR
-#define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n)
-
#define IMX25_UART1_BASE_ADDR 0x43f90000
#define IMX25_UART2_BASE_ADDR 0x43f94000
#define IMX25_UART3_BASE_ADDR 0x5000c000
@@ -26,6 +19,13 @@
#define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR
#define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n)
+#define IMX27_UART1_BASE_ADDR 0x1000a000
+#define IMX27_UART2_BASE_ADDR 0x1000b000
+#define IMX27_UART3_BASE_ADDR 0x1000c000
+#define IMX27_UART4_BASE_ADDR 0x1000d000
+#define IMX27_UART_BASE_ADDR(n) IMX27_UART##n##_BASE_ADDR
+#define IMX27_UART_BASE(n) IMX27_UART_BASE_ADDR(n)
+
#define IMX31_UART1_BASE_ADDR 0x43f90000
#define IMX31_UART2_BASE_ADDR 0x43f94000
#define IMX31_UART3_BASE_ADDR 0x5000c000
@@ -112,10 +112,10 @@
#ifdef CONFIG_DEBUG_IMX1_UART
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX1)
-#elif defined(CONFIG_DEBUG_IMX21_IMX27_UART)
-#define UART_PADDR IMX_DEBUG_UART_BASE(IMX21)
#elif defined(CONFIG_DEBUG_IMX25_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX25)
+#elif defined(CONFIG_DEBUG_IMX27_UART)
+#define UART_PADDR IMX_DEBUG_UART_BASE(IMX27)
#elif defined(CONFIG_DEBUG_IMX31_UART)
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
#elif defined(CONFIG_DEBUG_IMX35_UART)
diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S
index 1c1b9d1..bb7b955 100644
--- a/arch/arm/include/debug/imx.S
+++ b/arch/arm/include/debug/imx.S
@@ -35,7 +35,10 @@
str \rd, [\rx, #0x40] @ TXDATA
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
.endm
.macro busyuart,rd,rx
diff --git a/arch/arm/include/debug/meson.S b/arch/arm/include/debug/meson.S
index 1e501a0..7b60e44 100644
--- a/arch/arm/include/debug/meson.S
+++ b/arch/arm/include/debug/meson.S
@@ -25,7 +25,10 @@
beq 1002b
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
tst \rd, #MESON_AO_UART_TX_FIFO_FULL
bne 1001b
diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S
index 9405b71..530edc7 100644
--- a/arch/arm/include/debug/msm.S
+++ b/arch/arm/include/debug/msm.S
@@ -17,7 +17,10 @@
str \rd, [\rx, #0x70]
.endm
- .macro waituart, rd, rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy, rd, rx
@ check for TX_EMT in UARTDM_SR
ldr \rd, [\rx, #0x08]
ARM_BE8(rev \rd, \rd )
diff --git a/arch/arm/include/debug/omap2plus.S b/arch/arm/include/debug/omap2plus.S
index b5696a3..0680be6 100644
--- a/arch/arm/include/debug/omap2plus.S
+++ b/arch/arm/include/debug/omap2plus.S
@@ -75,5 +75,8 @@
bne 1001b
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
.endm
diff --git a/arch/arm/include/debug/pl01x.S b/arch/arm/include/debug/pl01x.S
index a2a553a..0c7bfa4 100644
--- a/arch/arm/include/debug/pl01x.S
+++ b/arch/arm/include/debug/pl01x.S
@@ -26,7 +26,10 @@
strb \rd, [\rx, #UART01x_DR]
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #UART01x_FR]
ARM_BE8( rev \rd, \rd )
tst \rd, #UART01x_FR_TXFF
diff --git a/arch/arm/include/debug/renesas-scif.S b/arch/arm/include/debug/renesas-scif.S
index 25f0666..8e433e9 100644
--- a/arch/arm/include/debug/renesas-scif.S
+++ b/arch/arm/include/debug/renesas-scif.S
@@ -33,7 +33,10 @@
ldr \rv, =SCIF_VIRT
.endm
- .macro waituart, rd, rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy, rd, rx
1001: ldrh \rd, [\rx, #FSR]
tst \rd, #TDFE
beq 1001b
diff --git a/arch/arm/include/debug/sa1100.S b/arch/arm/include/debug/sa1100.S
index 6109e60..7968ea5 100644
--- a/arch/arm/include/debug/sa1100.S
+++ b/arch/arm/include/debug/sa1100.S
@@ -51,7 +51,10 @@
str \rd, [\rx, #UTDR]
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #UTSR1]
tst \rd, #UTSR1_TNF
beq 1001b
diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S
index 69201d7..ab474d5 100644
--- a/arch/arm/include/debug/samsung.S
+++ b/arch/arm/include/debug/samsung.S
@@ -69,7 +69,10 @@
1002: @ exit busyuart
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
ldr \rd, [\rx, # S3C2410_UFCON]
ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
diff --git a/arch/arm/include/debug/sirf.S b/arch/arm/include/debug/sirf.S
index e73e4de..3612c7b 100644
--- a/arch/arm/include/debug/sirf.S
+++ b/arch/arm/include/debug/sirf.S
@@ -29,7 +29,10 @@
.macro busyuart,rd,rx
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS]
tst \rd, #SIRF_LLUART_TXFIFO_EMPTY
beq 1001b
diff --git a/arch/arm/include/debug/sti.S b/arch/arm/include/debug/sti.S
index 6b42c91..72d0525 100644
--- a/arch/arm/include/debug/sti.S
+++ b/arch/arm/include/debug/sti.S
@@ -45,7 +45,10 @@
strb \rd, [\rx, #ASC_TX_BUF_OFF]
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #ASC_STA_OFF]
tst \rd, #ASC_STA_TX_FULL
bne 1001b
diff --git a/arch/arm/include/debug/stm32.S b/arch/arm/include/debug/stm32.S
index 1abb32f..b6d9df3 100644
--- a/arch/arm/include/debug/stm32.S
+++ b/arch/arm/include/debug/stm32.S
@@ -4,14 +4,13 @@
* Author: Gerald Baeza <gerald.baeza@st.com> for STMicroelectronics.
*/
-#define STM32_UART_BASE 0x40011000 /* USART1 */
-
#ifdef CONFIG_STM32F4_DEBUG_UART
#define STM32_USART_SR_OFF 0x00
#define STM32_USART_TDR_OFF 0x04
#endif
-#ifdef CONFIG_STM32F7_DEBUG_UART
+#if defined(CONFIG_STM32F7_DEBUG_UART) || defined(CONFIG_STM32H7_DEBUG_UART) || \
+ defined(CONFIG_STM32MP1_DEBUG_UART)
#define STM32_USART_SR_OFF 0x1C
#define STM32_USART_TDR_OFF 0x28
#endif
@@ -20,15 +19,18 @@
#define STM32_USART_TXE (1 << 7) /* Tx data reg empty */
.macro addruart, rp, rv, tmp
- ldr \rp, =STM32_UART_BASE @ physical base
- ldr \rv, =STM32_UART_BASE @ virt base /* NoMMU */
+ ldr \rp, =CONFIG_DEBUG_UART_PHYS @ physical base
+ ldr \rv, =CONFIG_DEBUG_UART_VIRT @ virt base
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #STM32_USART_TDR_OFF]
.endm
-.macro waituart,rd,rx
+.macro waituartcts,rd,rx
+.endm
+
+.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty
beq 1001b
diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
index 2148d0f..7454480 100644
--- a/arch/arm/include/debug/tegra.S
+++ b/arch/arm/include/debug/tegra.S
@@ -149,7 +149,34 @@
.align
99: .word .
+#if defined(ZIMAGE)
+ .word . + 4
+/*
+ * Storage for the state maintained by the macro.
+ *
+ * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
+ * That's because this header is included from multiple files, and we only
+ * want a single copy of the data. In particular, the UART probing code above
+ * assumes it's running using physical addresses. This is true when this file
+ * is included from head.o, but not when included from debug.o. So we need
+ * to share the probe results between the two copies, rather than having
+ * to re-run the probing again later.
+ *
+ * In the decompressor, we put the storage right here, since common.c
+ * isn't included in the decompressor build. This storage data gets put in
+ * .text even though it's really data, since .data is discarded from the
+ * decompressor. Luckily, .text is writeable in the decompressor, unless
+ * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
+ */
+ /* Debug UART initialization required */
+ .word 1
+ /* Debug UART physical address */
+ .word 0
+ /* Debug UART virtual address */
+ .word 0
+#else
.word tegra_uart_config
+#endif
.ltorg
/* Load previously selected UART address */
@@ -178,40 +205,14 @@
1002:
.endm
- .macro waituart, rd, rx
-#ifdef FLOW_CONTROL
+ .macro waituartcts, rd, rx
cmp \rx, #0
beq 1002f
1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
tst \rd, #UART_MSR_CTS
beq 1001b
1002:
-#endif
.endm
-/*
- * Storage for the state maintained by the macros above.
- *
- * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
- * That's because this header is included from multiple files, and we only
- * want a single copy of the data. In particular, the UART probing code above
- * assumes it's running using physical addresses. This is true when this file
- * is included from head.o, but not when included from debug.o. So we need
- * to share the probe results between the two copies, rather than having
- * to re-run the probing again later.
- *
- * In the decompressor, we put the symbol/storage right here, since common.c
- * isn't included in the decompressor build. This symbol gets put in .text
- * even though it's really data, since .data is discarded from the
- * decompressor. Luckily, .text is writeable in the decompressor, unless
- * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
- */
-#if defined(ZIMAGE)
-tegra_uart_config:
- /* Debug UART initialization required */
- .word 1
- /* Debug UART physical address */
- .word 0
- /* Debug UART virtual address */
- .word 0
-#endif
+ .macro waituarttxrdy,rd,rx
+ .endm
diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S
index 854d9bd..035bcbf 100644
--- a/arch/arm/include/debug/vf.S
+++ b/arch/arm/include/debug/vf.S
@@ -29,5 +29,8 @@
beq 1001b @ wait until transmit done
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
.endm
diff --git a/arch/arm/include/debug/vt8500.S b/arch/arm/include/debug/vt8500.S
index 8dc1df2..d01094f 100644
--- a/arch/arm/include/debug/vt8500.S
+++ b/arch/arm/include/debug/vt8500.S
@@ -28,7 +28,10 @@
bne 1001b
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
.endm
#endif
diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S
index 58d77c9..5d42cc3 100644
--- a/arch/arm/include/debug/zynq.S
+++ b/arch/arm/include/debug/zynq.S
@@ -33,7 +33,10 @@
strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
.endm
- .macro waituart,rd,rx
+ .macro waituartcts,rd,rx
+ .endm
+
+ .macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #UART_SR_OFFSET]
ARM_BE8( rev \rd, \rd )
tst \rd, #UART_SR_TXEMPTY
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
deleted file mode 100644
index 2769360..0000000
--- a/arch/arm/include/uapi/asm/kvm.h
+++ /dev/null
@@ -1,313 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#ifndef __ARM_KVM_H__
-#define __ARM_KVM_H__
-
-#include <linux/types.h>
-#include <linux/psci.h>
-#include <asm/ptrace.h>
-
-#define __KVM_HAVE_GUEST_DEBUG
-#define __KVM_HAVE_IRQ_LINE
-#define __KVM_HAVE_READONLY_MEM
-#define __KVM_HAVE_VCPU_EVENTS
-
-#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
-
-#define KVM_REG_SIZE(id) \
- (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
-
-/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
-#define KVM_ARM_SVC_sp svc_regs[0]
-#define KVM_ARM_SVC_lr svc_regs[1]
-#define KVM_ARM_SVC_spsr svc_regs[2]
-#define KVM_ARM_ABT_sp abt_regs[0]
-#define KVM_ARM_ABT_lr abt_regs[1]
-#define KVM_ARM_ABT_spsr abt_regs[2]
-#define KVM_ARM_UND_sp und_regs[0]
-#define KVM_ARM_UND_lr und_regs[1]
-#define KVM_ARM_UND_spsr und_regs[2]
-#define KVM_ARM_IRQ_sp irq_regs[0]
-#define KVM_ARM_IRQ_lr irq_regs[1]
-#define KVM_ARM_IRQ_spsr irq_regs[2]
-
-/* Valid only for fiq_regs in struct kvm_regs */
-#define KVM_ARM_FIQ_r8 fiq_regs[0]
-#define KVM_ARM_FIQ_r9 fiq_regs[1]
-#define KVM_ARM_FIQ_r10 fiq_regs[2]
-#define KVM_ARM_FIQ_fp fiq_regs[3]
-#define KVM_ARM_FIQ_ip fiq_regs[4]
-#define KVM_ARM_FIQ_sp fiq_regs[5]
-#define KVM_ARM_FIQ_lr fiq_regs[6]
-#define KVM_ARM_FIQ_spsr fiq_regs[7]
-
-struct kvm_regs {
- struct pt_regs usr_regs; /* R0_usr - R14_usr, PC, CPSR */
- unsigned long svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
- unsigned long abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
- unsigned long und_regs[3]; /* SP_und, LR_und, SPSR_und */
- unsigned long irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
- unsigned long fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
-};
-
-/* Supported Processor Types */
-#define KVM_ARM_TARGET_CORTEX_A15 0
-#define KVM_ARM_TARGET_CORTEX_A7 1
-#define KVM_ARM_NUM_TARGETS 2
-
-/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
-#define KVM_ARM_DEVICE_TYPE_SHIFT 0
-#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
-#define KVM_ARM_DEVICE_ID_SHIFT 16
-#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
-
-/* Supported device IDs */
-#define KVM_ARM_DEVICE_VGIC_V2 0
-
-/* Supported VGIC address types */
-#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
-#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
-
-#define KVM_VGIC_V2_DIST_SIZE 0x1000
-#define KVM_VGIC_V2_CPU_SIZE 0x2000
-
-/* Supported VGICv3 address types */
-#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
-#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
-#define KVM_VGIC_ITS_ADDR_TYPE 4
-#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
-
-#define KVM_VGIC_V3_DIST_SIZE SZ_64K
-#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
-#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
-
-#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
-#define KVM_ARM_VCPU_PSCI_0_2 1 /* CPU uses PSCI v0.2 */
-
-struct kvm_vcpu_init {
- __u32 target;
- __u32 features[7];
-};
-
-struct kvm_sregs {
-};
-
-struct kvm_fpu {
-};
-
-struct kvm_guest_debug_arch {
-};
-
-struct kvm_debug_exit_arch {
-};
-
-struct kvm_sync_regs {
- /* Used with KVM_CAP_ARM_USER_IRQ */
- __u64 device_irq_level;
-};
-
-struct kvm_arch_memory_slot {
-};
-
-/* for KVM_GET/SET_VCPU_EVENTS */
-struct kvm_vcpu_events {
- struct {
- __u8 serror_pending;
- __u8 serror_has_esr;
- /* Align it to 8 bytes */
- __u8 pad[6];
- __u64 serror_esr;
- } exception;
- __u32 reserved[12];
-};
-
-/* If you need to interpret the index values, here is the key: */
-#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
-#define KVM_REG_ARM_COPROC_SHIFT 16
-#define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007
-#define KVM_REG_ARM_32_OPC2_SHIFT 0
-#define KVM_REG_ARM_OPC1_MASK 0x0000000000000078
-#define KVM_REG_ARM_OPC1_SHIFT 3
-#define KVM_REG_ARM_CRM_MASK 0x0000000000000780
-#define KVM_REG_ARM_CRM_SHIFT 7
-#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
-#define KVM_REG_ARM_32_CRN_SHIFT 11
-/*
- * For KVM currently all guest registers are nonsecure, but we reserve a bit
- * in the encoding to distinguish secure from nonsecure for AArch32 system
- * registers that are banked by security. This is 1 for the secure banked
- * register, and 0 for the nonsecure banked register or if the register is
- * not banked by security.
- */
-#define KVM_REG_ARM_SECURE_MASK 0x0000000010000000
-#define KVM_REG_ARM_SECURE_SHIFT 28
-
-#define ARM_CP15_REG_SHIFT_MASK(x,n) \
- (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
-
-#define __ARM_CP15_REG(op1,crn,crm,op2) \
- (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
- ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
- ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
- ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
- ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
-
-#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
-
-#define __ARM_CP15_REG64(op1,crm) \
- (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
-#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
-
-/* PL1 Physical Timer Registers */
-#define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1)
-#define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14)
-#define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14)
-
-/* Virtual Timer Registers */
-#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
-#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
-#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
-
-/* Normal registers are mapped as coprocessor 16. */
-#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
-#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
-
-/* Some registers need more space to represent values. */
-#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
-#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
-#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
-#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
-#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
-#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
-
-/* VFP registers: we could overload CP10 like ARM does, but that's ugly. */
-#define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
-#define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF
-#define KVM_REG_ARM_VFP_BASE_REG 0x0
-#define KVM_REG_ARM_VFP_FPSID 0x1000
-#define KVM_REG_ARM_VFP_FPSCR 0x1001
-#define KVM_REG_ARM_VFP_MVFR1 0x1006
-#define KVM_REG_ARM_VFP_MVFR0 0x1007
-#define KVM_REG_ARM_VFP_FPEXC 0x1008
-#define KVM_REG_ARM_VFP_FPINST 0x1009
-#define KVM_REG_ARM_VFP_FPINST2 0x100A
-
-/* KVM-as-firmware specific pseudo-registers */
-#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
-#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \
- KVM_REG_ARM_FW | ((r) & 0xffff))
-#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
-#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1)
- /* Higher values mean better protection. */
-#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0
-#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1
-#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2
-#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2)
- /* Higher values mean better protection. */
-#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0
-#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1
-#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2
-#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3
-#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4)
-
-/* Device Control API: ARM VGIC */
-#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
-#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
-#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
-#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
-#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
-#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
-#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
- (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
-#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
-#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
-#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
-#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
-#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
-#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
-#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
-#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
-#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
-#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
-#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
- (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
-#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
-#define VGIC_LEVEL_INFO_LINE_LEVEL 0
-
-/* Device Control API on vcpu fd */
-#define KVM_ARM_VCPU_PMU_V3_CTRL 0
-#define KVM_ARM_VCPU_PMU_V3_IRQ 0
-#define KVM_ARM_VCPU_PMU_V3_INIT 1
-#define KVM_ARM_VCPU_TIMER_CTRL 1
-#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
-#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
-
-#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
-#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
-#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
-#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
-#define KVM_DEV_ARM_ITS_CTRL_RESET 4
-
-/* KVM_IRQ_LINE irq field index values */
-#define KVM_ARM_IRQ_VCPU2_SHIFT 28
-#define KVM_ARM_IRQ_VCPU2_MASK 0xf
-#define KVM_ARM_IRQ_TYPE_SHIFT 24
-#define KVM_ARM_IRQ_TYPE_MASK 0xf
-#define KVM_ARM_IRQ_VCPU_SHIFT 16
-#define KVM_ARM_IRQ_VCPU_MASK 0xff
-#define KVM_ARM_IRQ_NUM_SHIFT 0
-#define KVM_ARM_IRQ_NUM_MASK 0xffff
-
-/* irq_type field */
-#define KVM_ARM_IRQ_TYPE_CPU 0
-#define KVM_ARM_IRQ_TYPE_SPI 1
-#define KVM_ARM_IRQ_TYPE_PPI 2
-
-/* out-of-kernel GIC cpu interrupt injection irq_number field */
-#define KVM_ARM_IRQ_CPU_IRQ 0
-#define KVM_ARM_IRQ_CPU_FIQ 1
-
-/*
- * This used to hold the highest supported SPI, but it is now obsolete
- * and only here to provide source code level compatibility with older
- * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
- */
-#ifndef __KERNEL__
-#define KVM_ARM_IRQ_GIC_MAX 127
-#endif
-
-/* One single KVM irqchip, ie. the VGIC */
-#define KVM_NR_IRQCHIPS 1
-
-/* PSCI interface */
-#define KVM_PSCI_FN_BASE 0x95c1ba5e
-#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
-
-#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
-#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
-#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
-#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
-
-#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
-#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
-#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
-#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
-
-#endif /* __ARM_KVM_H__ */
diff --git a/arch/arm/kernel/.gitignore b/arch/arm/kernel/.gitignore
index c5f676c..bbb90f9 100644
--- a/arch/arm/kernel/.gitignore
+++ b/arch/arm/kernel/.gitignore
@@ -1 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
vmlinux.lds
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 8b679e2..79588b5 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -53,8 +53,8 @@
obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arch_timer.o
obj-$(CONFIG_FUNCTION_TRACER) += entry-ftrace.o
-obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o insn.o
-obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o insn.o
+obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o insn.o patch.o
+obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o insn.o patch.o
obj-$(CONFIG_JUMP_LABEL) += jump_label.o insn.o patch.o
obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
# Main staffs in KPROBES are in arch/arm/probes/ .
@@ -106,4 +106,6 @@
obj-$(CONFIG_HAVE_ARM_SMCCC) += smccc-call.o
+obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) += spectre.o
+
extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index c125582..b5e2179 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -10,6 +10,7 @@
#include <linux/errno.h>
#include <asm/delay.h>
+#include <asm/arch_timer.h>
#include <clocksource/arm_arch_timer.h>
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 98bdea5..82e96ac 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -7,7 +7,6 @@
#include <linux/export.h>
#include <linux/sched.h>
#include <linux/string.h>
-#include <linux/cryptohash.h>
#include <linux/delay.h>
#include <linux/in6.h>
#include <linux/syscalls.h>
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 4ce2e29..70993af 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -11,9 +11,6 @@
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
-#ifdef CONFIG_KVM_ARM_HOST
-#include <linux/kvm_host.h>
-#endif
#include <asm/cacheflush.h>
#include <asm/kexec-internal.h>
#include <asm/glue-df.h>
@@ -36,15 +33,6 @@
#if defined(__APCS_26__)
#error Sorry, your compiler targets APCS-26 but this kernel requires APCS-32
#endif
-/*
- * GCC 4.8.0-4.8.2: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854
- * miscompiles find_get_entry(), and can result in EXT3 and EXT4
- * filesystem corruption (possibly other FS too).
- */
-#if defined(GCC_VERSION) && GCC_VERSION >= 40800 && GCC_VERSION < 40803
-#error Your compiler is too buggy; it is known to miscompile kernels
-#error and result in filesystem corruption and oopses.
-#endif
int main(void)
{
@@ -171,14 +159,6 @@
DEFINE(CACHE_WRITEBACK_ORDER, __CACHE_WRITEBACK_ORDER);
DEFINE(CACHE_WRITEBACK_GRANULE, __CACHE_WRITEBACK_GRANULE);
BLANK();
-#ifdef CONFIG_KVM_ARM_HOST
- DEFINE(VCPU_GUEST_CTXT, offsetof(struct kvm_vcpu, arch.ctxt));
- DEFINE(VCPU_HOST_CTXT, offsetof(struct kvm_vcpu, arch.host_cpu_context));
- DEFINE(CPU_CTXT_VFP, offsetof(struct kvm_cpu_context, vfp));
- DEFINE(CPU_CTXT_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs));
- DEFINE(GP_REGS_USR, offsetof(struct kvm_regs, usr_regs));
-#endif
- BLANK();
#ifdef CONFIG_VDSO
DEFINE(VDSO_DATA_SIZE, sizeof(union vdso_data_store));
#endif
diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c
index 8288151..373b61f 100644
--- a/arch/arm/kernel/atags_parse.c
+++ b/arch/arm/kernel/atags_parse.c
@@ -91,8 +91,6 @@
static int __init parse_tag_ramdisk(const struct tag *tag)
{
rd_image_start = tag->u.ramdisk.start;
- rd_doload = (tag->u.ramdisk.flags & 1) == 0;
- rd_prompt = (tag->u.ramdisk.flags & 2) == 0;
if (tag->u.ramdisk.size)
rd_size = tag->u.ramdisk.size;
diff --git a/arch/arm/kernel/atags_proc.c b/arch/arm/kernel/atags_proc.c
index 312cb89..3c2faf2 100644
--- a/arch/arm/kernel/atags_proc.c
+++ b/arch/arm/kernel/atags_proc.c
@@ -17,9 +17,9 @@
return simple_read_from_buffer(buf, count, ppos, b->data, b->size);
}
-static const struct file_operations atags_fops = {
- .read = atags_read,
- .llseek = default_llseek,
+static const struct proc_ops atags_proc_ops = {
+ .proc_read = atags_read,
+ .proc_lseek = default_llseek,
};
#define BOOT_PARAMS_SIZE 1536
@@ -42,7 +42,7 @@
size_t size;
if (tag->hdr.tag != ATAG_CORE) {
- pr_info("No ATAGs?");
+ pr_info("No ATAGs?\n");
return -EINVAL;
}
@@ -61,7 +61,7 @@
b->size = size;
memcpy(b->data, atags_copy, size);
- tags_entry = proc_create_data("atags", 0400, NULL, &atags_fops, b);
+ tags_entry = proc_create_data("atags", 0400, NULL, &atags_proc_ops, b);
if (!tags_entry)
goto nomem;
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index ed46ca6..e7ef2b5 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -252,23 +252,6 @@
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
-static void pci_fixup_it8152(struct pci_dev *dev)
-{
- int i;
- /* fixup for ITE 8152 devices */
- /* FIXME: add defines for class 0x68000 and 0x80103 */
- if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
- dev->class == 0x68000 ||
- dev->class == 0x80103) {
- for (i = 0; i < PCI_NUM_RESOURCES; i++) {
- dev->resource[i].start = 0;
- dev->resource[i].end = 0;
- dev->resource[i].flags = 0;
- }
- }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
-
/*
* If the bus contains any of these devices, then we must not turn on
* parity checking of any kind. Currently this is CyberPro 20x0 only.
@@ -411,8 +394,7 @@
return irq;
}
-static int pcibios_init_resource(int busnr, struct pci_sys_data *sys,
- int io_optional)
+static int pcibios_init_resource(int busnr, struct pci_sys_data *sys)
{
int ret;
struct resource_entry *window;
@@ -422,14 +404,6 @@
&iomem_resource, sys->mem_offset);
}
- /*
- * If a platform says I/O port support is optional, we don't add
- * the default I/O space. The platform is responsible for adding
- * any I/O space it needs.
- */
- if (io_optional)
- return 0;
-
resource_list_for_each_entry(window, &sys->resources)
if (resource_type(window->res) == IORESOURCE_IO)
return 0;
@@ -479,7 +453,7 @@
if (ret > 0) {
- ret = pcibios_init_resource(nr, sys, hw->io_optional);
+ ret = pcibios_init_resource(nr, sys);
if (ret) {
pci_free_host_bridge(bridge);
break;
@@ -497,9 +471,6 @@
bridge->sysdata = sys;
bridge->busnr = sys->busnr;
bridge->ops = hw->ops;
- bridge->msi = hw->msi_ctrl;
- bridge->align_resource =
- hw->align_resource;
ret = pci_scan_root_bus_bridge(bridge);
}
diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c
index 093368e..e168462 100644
--- a/arch/arm/kernel/cpuidle.c
+++ b/arch/arm/kernel/cpuidle.c
@@ -11,7 +11,7 @@
extern struct of_cpuidle_method __cpuidle_method_of_table[];
static const struct of_cpuidle_method __cpuidle_method_of_table_sentinel
- __used __section(__cpuidle_method_of_table_end);
+ __used __section("__cpuidle_method_of_table_end");
static struct cpuidle_ops cpuidle_ops[NR_CPUS] __ro_after_init;
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index e112072..d92f44b 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -89,11 +89,18 @@
2: teq r1, #'\n'
bne 3f
mov r1, #'\r'
- waituart r2, r3
+#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL
+ waituartcts r2, r3
+#endif
+ waituarttxrdy r2, r3
senduart r1, r3
busyuart r2, r3
mov r1, #'\n'
-3: waituart r2, r3
+3:
+#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL
+ waituartcts r2, r3
+#endif
+ waituarttxrdy r2, r3
senduart r1, r3
busyuart r2, r3
b 1b
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 4e09883..28311dd 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -29,7 +29,7 @@
extern struct of_cpu_method __cpu_method_of_table[];
static const struct of_cpu_method __cpu_method_of_table_sentinel
- __used __section(__cpu_method_of_table_end);
+ __used __section("__cpu_method_of_table_end");
static int __init set_smp_ops_by_method(struct device_node *node)
diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c
index 1824229..254ab71 100644
--- a/arch/arm/kernel/elf.c
+++ b/arch/arm/kernel/elf.c
@@ -78,13 +78,32 @@
EXPORT_SYMBOL(elf_set_personality);
/*
- * Set READ_IMPLIES_EXEC if:
- * - the binary requires an executable stack
- * - we're running on a CPU which doesn't support NX.
+ * An executable for which elf_read_implies_exec() returns TRUE will
+ * have the READ_IMPLIES_EXEC personality flag set automatically.
+ *
+ * The decision process for determining the results are:
+ *
+ * CPU: | lacks NX* | has NX |
+ * ELF: | | |
+ * ---------------------|------------|------------|
+ * missing PT_GNU_STACK | exec-all | exec-all |
+ * PT_GNU_STACK == RWX | exec-all | exec-stack |
+ * PT_GNU_STACK == RW | exec-all | exec-none |
+ *
+ * exec-all : all PROT_READ user mappings are executable, except when
+ * backed by files on a noexec-filesystem.
+ * exec-none : only PROT_EXEC user mappings are executable.
+ * exec-stack: only the stack and PROT_EXEC user mappings are executable.
+ *
+ * *this column has no architectural effect: NX markings are ignored by
+ * hardware, but may have behavioral effects when "wants X" collides with
+ * "cannot be X" constraints in memory permission flags, as in
+ * https://lkml.kernel.org/r/20190418055759.GA3155@mellanox.com
+ *
*/
int arm_elf_read_implies_exec(int executable_stack)
{
- if (executable_stack != EXSTACK_DISABLE_X)
+ if (executable_stack == EXSTACK_DEFAULT)
return 1;
if (cpu_architecture() < CPU_ARCH_ARMv6)
return 1;
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index b62d74a..c3ebe35 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -204,7 +204,7 @@
svc_entry
irq_handler
-#ifdef CONFIG_PREEMPT
+#ifdef CONFIG_PREEMPTION
ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
ldr r0, [tsk, #TI_FLAGS] @ get flags
teq r8, #0 @ if preempt count != 0
@@ -219,7 +219,7 @@
.ltorg
-#ifdef CONFIG_PREEMPT
+#ifdef CONFIG_PREEMPTION
svc_preempt:
mov r8, lr
1: bl preempt_schedule_irq @ irq en/disable is done inside
@@ -596,11 +596,9 @@
tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
reteq lr
and r8, r0, #0x00000f00 @ mask out CP number
- THUMB( lsr r8, r8, #8 )
mov r7, #1
- add r6, r10, #TI_USED_CP
- ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
- THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
+ add r6, r10, r8, lsr #8 @ add used_cp[] array offset first
+ strb r7, [r6, #TI_USED_CP] @ set appropriate used_cp[]
#ifdef CONFIG_IWMMXT
@ Test if we need to give access to iWMMXt coprocessors
ldr r5, [r10, #TI_FLAGS]
@@ -609,7 +607,7 @@
bcs iwmmxt_task_enable
#endif
ARM( add pc, pc, r8, lsr #6 )
- THUMB( lsl r8, r8, #2 )
+ THUMB( lsr r8, r8, #6 )
THUMB( add pc, r8 )
nop
@@ -1007,12 +1005,11 @@
sub lr, lr, #\correction
.endif
- @
- @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
- @ (parent CPSR)
- @
+ @ Save r0, lr_<exception> (parent PC)
stmia sp, {r0, lr} @ save r0, lr
- mrs lr, spsr
+
+ @ Save spsr_<exception> (parent CPSR)
+2: mrs lr, spsr
str lr, [sp, #8] @ save spsr
@
@@ -1033,6 +1030,44 @@
movs pc, lr @ branch to handler in SVC mode
ENDPROC(vector_\name)
+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
+ .subsection 1
+ .align 5
+vector_bhb_loop8_\name:
+ .if \correction
+ sub lr, lr, #\correction
+ .endif
+
+ @ Save r0, lr_<exception> (parent PC)
+ stmia sp, {r0, lr}
+
+ @ bhb workaround
+ mov r0, #8
+3: b . + 4
+ subs r0, r0, #1
+ bne 3b
+ dsb
+ isb
+ b 2b
+ENDPROC(vector_bhb_loop8_\name)
+
+vector_bhb_bpiall_\name:
+ .if \correction
+ sub lr, lr, #\correction
+ .endif
+
+ @ Save r0, lr_<exception> (parent PC)
+ stmia sp, {r0, lr}
+
+ @ bhb workaround
+ mcr p15, 0, r0, c7, c5, 6 @ BPIALL
+ @ isb not needed due to "movs pc, lr" in the vector stub
+ @ which gives a "context synchronisation".
+ b 2b
+ENDPROC(vector_bhb_bpiall_\name)
+ .previous
+#endif
+
.align 2
@ handler addresses follow this label
1:
@@ -1041,6 +1076,10 @@
.section .stubs, "ax", %progbits
@ This must be the first word
.word vector_swi
+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
+ .word vector_bhb_loop8_swi
+ .word vector_bhb_bpiall_swi
+#endif
vector_rst:
ARM( swi SYS_ERROR0 )
@@ -1155,8 +1194,10 @@
* FIQ "NMI" handler
*-----------------------------------------------------------------------------
* Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
- * systems.
+ * systems. This must be the last vector stub, so lets place it in its own
+ * subsection.
*/
+ .subsection 2
vector_stub fiq, FIQ_MODE, 4
.long __fiq_usr @ 0 (USR_26 / USR_32)
@@ -1189,6 +1230,30 @@
W(b) vector_irq
W(b) vector_fiq
+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
+ .section .vectors.bhb.loop8, "ax", %progbits
+.L__vectors_bhb_loop8_start:
+ W(b) vector_rst
+ W(b) vector_bhb_loop8_und
+ W(ldr) pc, .L__vectors_bhb_loop8_start + 0x1004
+ W(b) vector_bhb_loop8_pabt
+ W(b) vector_bhb_loop8_dabt
+ W(b) vector_addrexcptn
+ W(b) vector_bhb_loop8_irq
+ W(b) vector_bhb_loop8_fiq
+
+ .section .vectors.bhb.bpiall, "ax", %progbits
+.L__vectors_bhb_bpiall_start:
+ W(b) vector_rst
+ W(b) vector_bhb_bpiall_und
+ W(ldr) pc, .L__vectors_bhb_bpiall_start + 0x1008
+ W(b) vector_bhb_bpiall_pabt
+ W(b) vector_bhb_bpiall_dabt
+ W(b) vector_addrexcptn
+ W(b) vector_bhb_bpiall_irq
+ W(b) vector_bhb_bpiall_fiq
+#endif
+
.data
.align 2
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 271cb8a..bd619da 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -163,12 +163,36 @@
*/
.align 5
+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
+ENTRY(vector_bhb_loop8_swi)
+ sub sp, sp, #PT_REGS_SIZE
+ stmia sp, {r0 - r12}
+ mov r8, #8
+1: b 2f
+2: subs r8, r8, #1
+ bne 1b
+ dsb
+ isb
+ b 3f
+ENDPROC(vector_bhb_loop8_swi)
+
+ .align 5
+ENTRY(vector_bhb_bpiall_swi)
+ sub sp, sp, #PT_REGS_SIZE
+ stmia sp, {r0 - r12}
+ mcr p15, 0, r8, c7, c5, 6 @ BPIALL
+ isb
+ b 3f
+ENDPROC(vector_bhb_bpiall_swi)
+#endif
+ .align 5
ENTRY(vector_swi)
#ifdef CONFIG_CPU_V7M
v7m_exception_entry
#else
sub sp, sp, #PT_REGS_SIZE
stmia sp, {r0 - r12} @ Calling r0 - r12
+3:
ARM( add r8, sp, #S_PC )
ARM( stmdb r8, {sp, lr}^ ) @ Calling sp, lr
THUMB( mov r8, sp )
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index cd1234c..98ca3e3 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -98,8 +98,8 @@
memcpy(base + offset, start, length);
if (!cache_is_vipt_nonaliasing())
- flush_icache_range((unsigned long)base + offset, offset +
- length);
+ flush_icache_range((unsigned long)base + offset,
+ (unsigned long)base + offset + length);
flush_icache_range(0xffff0000 + offset, 0xffff0000 + offset + length);
}
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
index bda949f..3c83b5d 100644
--- a/arch/arm/kernel/ftrace.c
+++ b/arch/arm/kernel/ftrace.c
@@ -22,6 +22,7 @@
#include <asm/ftrace.h>
#include <asm/insn.h>
#include <asm/set_memory.h>
+#include <asm/patch.h>
#ifdef CONFIG_THUMB2_KERNEL
#define NOP 0xf85deb04 /* pop.w {lr} */
@@ -35,9 +36,7 @@
{
int *command = data;
- set_kernel_text_rw();
ftrace_modify_all_code(*command);
- set_kernel_text_ro();
return 0;
}
@@ -59,21 +58,20 @@
int ftrace_arch_code_modify_prepare(void)
{
- set_all_modules_text_rw();
return 0;
}
int ftrace_arch_code_modify_post_process(void)
{
- set_all_modules_text_ro();
/* Make sure any TLB misses during machine stop are cleared. */
flush_tlb_all();
return 0;
}
-static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
+static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr,
+ bool warn)
{
- return arm_gen_branch_link(pc, addr);
+ return arm_gen_branch_link(pc, addr, warn);
}
static int ftrace_modify_code(unsigned long pc, unsigned long old,
@@ -81,26 +79,21 @@
{
unsigned long replaced;
- if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {
+ if (IS_ENABLED(CONFIG_THUMB2_KERNEL))
old = __opcode_to_mem_thumb32(old);
- new = __opcode_to_mem_thumb32(new);
- } else {
+ else
old = __opcode_to_mem_arm(old);
- new = __opcode_to_mem_arm(new);
- }
if (validate) {
- if (probe_kernel_read(&replaced, (void *)pc, MCOUNT_INSN_SIZE))
+ if (copy_from_kernel_nofault(&replaced, (void *)pc,
+ MCOUNT_INSN_SIZE))
return -EFAULT;
if (replaced != old)
return -EINVAL;
}
- if (probe_kernel_write((void *)pc, &new, MCOUNT_INSN_SIZE))
- return -EPERM;
-
- flush_icache_range(pc, pc + MCOUNT_INSN_SIZE);
+ __patch_text((void *)pc, new);
return 0;
}
@@ -112,14 +105,14 @@
int ret;
pc = (unsigned long)&ftrace_call;
- new = ftrace_call_replace(pc, (unsigned long)func);
+ new = ftrace_call_replace(pc, (unsigned long)func, true);
ret = ftrace_modify_code(pc, 0, new, false);
#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS
if (!ret) {
pc = (unsigned long)&ftrace_regs_call;
- new = ftrace_call_replace(pc, (unsigned long)func);
+ new = ftrace_call_replace(pc, (unsigned long)func, true);
ret = ftrace_modify_code(pc, 0, new, false);
}
@@ -132,10 +125,22 @@
{
unsigned long new, old;
unsigned long ip = rec->ip;
+ unsigned long aaddr = adjust_address(rec, addr);
+ struct module *mod = NULL;
+
+#ifdef CONFIG_ARM_MODULE_PLTS
+ mod = rec->arch.mod;
+#endif
old = ftrace_nop_replace(rec);
- new = ftrace_call_replace(ip, adjust_address(rec, addr));
+ new = ftrace_call_replace(ip, aaddr, !mod);
+#ifdef CONFIG_ARM_MODULE_PLTS
+ if (!new && mod) {
+ aaddr = get_module_plt(mod, ip, aaddr);
+ new = ftrace_call_replace(ip, aaddr, true);
+ }
+#endif
return ftrace_modify_code(rec->ip, old, new, true);
}
@@ -148,9 +153,9 @@
unsigned long new, old;
unsigned long ip = rec->ip;
- old = ftrace_call_replace(ip, adjust_address(rec, old_addr));
+ old = ftrace_call_replace(ip, adjust_address(rec, old_addr), true);
- new = ftrace_call_replace(ip, adjust_address(rec, addr));
+ new = ftrace_call_replace(ip, adjust_address(rec, addr), true);
return ftrace_modify_code(rec->ip, old, new, true);
}
@@ -160,12 +165,29 @@
int ftrace_make_nop(struct module *mod,
struct dyn_ftrace *rec, unsigned long addr)
{
+ unsigned long aaddr = adjust_address(rec, addr);
unsigned long ip = rec->ip;
unsigned long old;
unsigned long new;
int ret;
- old = ftrace_call_replace(ip, adjust_address(rec, addr));
+#ifdef CONFIG_ARM_MODULE_PLTS
+ /* mod is only supplied during module loading */
+ if (!mod)
+ mod = rec->arch.mod;
+ else
+ rec->arch.mod = mod;
+#endif
+
+ old = ftrace_call_replace(ip, aaddr,
+ !IS_ENABLED(CONFIG_ARM_MODULE_PLTS) || !mod);
+#ifdef CONFIG_ARM_MODULE_PLTS
+ if (!old && mod) {
+ aaddr = get_module_plt(mod, ip, aaddr);
+ old = ftrace_call_replace(ip, aaddr, true);
+ }
+#endif
+
new = ftrace_nop_replace(rec);
ret = ftrace_modify_code(ip, old, new, true);
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 5ceed4d..4af5c76 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -10,6 +10,7 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/cp15.h>
@@ -18,7 +19,6 @@
#include <asm/asm-offsets.h>
#include <asm/memory.h>
#include <asm/thread_info.h>
-#include <asm/pgtable.h>
#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
#include CONFIG_DEBUG_LL_INCLUDE
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index b06d9ea..b1423fb 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -246,6 +246,9 @@
case ARM_DEBUG_ARCH_V7_ECP14:
case ARM_DEBUG_ARCH_V7_1:
case ARM_DEBUG_ARCH_V8:
+ case ARM_DEBUG_ARCH_V8_1:
+ case ARM_DEBUG_ARCH_V8_2:
+ case ARM_DEBUG_ARCH_V8_4:
ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
isb();
break;
@@ -544,7 +547,7 @@
if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE)
&& max_watchpoint_len >= 8)
break;
- /* Else, fall through */
+ fallthrough;
default:
return -EINVAL;
}
@@ -609,12 +612,12 @@
/* Allow halfword watchpoints and breakpoints. */
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
break;
- /* Else, fall through */
+ fallthrough;
case 3:
/* Allow single byte watchpoint. */
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
break;
- /* Else, fall through */
+ fallthrough;
default:
ret = -EINVAL;
goto out;
@@ -925,7 +928,7 @@
break;
case ARM_ENTRY_ASYNC_WATCHPOINT:
WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
- /* Fall through */
+ fallthrough;
case ARM_ENTRY_SYNC_WATCHPOINT:
watchpoint_handler(addr, fsr, regs);
break;
@@ -974,7 +977,7 @@
ARM_DBG_READ(c1, c1, 4, oslsr);
if (oslsr & ARM_OSLSR_OSLM0)
return true;
- /* Else, fall through */
+ fallthrough;
default:
return false;
}
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 6607fa8..26d8e03 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -189,19 +189,19 @@
ENDPROC(__hyp_stub_install_secondary)
__hyp_stub_do_trap:
+#ifdef ZIMAGE
teq r0, #HVC_SET_VECTORS
bne 1f
+ /* Only the ZIMAGE stubs can change the HYP vectors */
mcr p15, 4, r1, c12, c0, 0 @ set HVBAR
b __hyp_stub_exit
+#endif
1: teq r0, #HVC_SOFT_RESTART
- bne 1f
+ bne 2f
bx r1
-1: teq r0, #HVC_RESET_VECTORS
- beq __hyp_stub_exit
-
- ldr r0, =HVC_STUB_ERR
+2: ldr r0, =HVC_STUB_ERR
__ERET
__hyp_stub_exit:
@@ -210,26 +210,9 @@
ENDPROC(__hyp_stub_do_trap)
/*
- * __hyp_set_vectors: Call this after boot to set the initial hypervisor
- * vectors as part of hypervisor installation. On an SMP system, this should
- * be called on each CPU.
- *
- * r0 must be the physical address of the new vector table (which must lie in
- * the bottom 4GB of physical address space.
- *
- * r0 must be 32-byte aligned.
- *
- * Before calling this, you must check that the stub hypervisor is installed
- * everywhere, by waiting for any secondary CPUs to be brought up and then
- * checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true.
- *
- * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
- * something else went wrong... in such cases, trying to install a new
- * hypervisor is unlikely to work as desired.
- *
- * When you call into your shiny new hypervisor, sp_hyp will contain junk,
- * so you will need to set that to something sensible at the new hypervisor's
- * initialisation entry point.
+ * __hyp_set_vectors is only used when ZIMAGE must bounce between HYP
+ * and SVC. For the kernel itself, the vectors are set once and for
+ * all by the stubs.
*/
ENTRY(__hyp_set_vectors)
mov r1, r0
@@ -245,12 +228,6 @@
ret lr
ENDPROC(__hyp_soft_restart)
-ENTRY(__hyp_reset_vectors)
- mov r0, #HVC_RESET_VECTORS
- __HVC(0)
- ret lr
-ENDPROC(__hyp_reset_vectors)
-
#ifndef ZIMAGE
.align 2
.L__boot_cpu_mode_offset:
diff --git a/arch/arm/kernel/insn.c b/arch/arm/kernel/insn.c
index 2e844b7..db0acbb 100644
--- a/arch/arm/kernel/insn.c
+++ b/arch/arm/kernel/insn.c
@@ -3,8 +3,9 @@
#include <linux/kernel.h>
#include <asm/opcodes.h>
-static unsigned long
-__arm_gen_branch_thumb2(unsigned long pc, unsigned long addr, bool link)
+static unsigned long __arm_gen_branch_thumb2(unsigned long pc,
+ unsigned long addr, bool link,
+ bool warn)
{
unsigned long s, j1, j2, i1, i2, imm10, imm11;
unsigned long first, second;
@@ -12,7 +13,7 @@
offset = (long)addr - (long)(pc + 4);
if (offset < -16777216 || offset > 16777214) {
- WARN_ON_ONCE(1);
+ WARN_ON_ONCE(warn);
return 0;
}
@@ -33,8 +34,8 @@
return __opcode_thumb32_compose(first, second);
}
-static unsigned long
-__arm_gen_branch_arm(unsigned long pc, unsigned long addr, bool link)
+static unsigned long __arm_gen_branch_arm(unsigned long pc, unsigned long addr,
+ bool link, bool warn)
{
unsigned long opcode = 0xea000000;
long offset;
@@ -44,7 +45,7 @@
offset = (long)addr - (long)(pc + 8);
if (unlikely(offset < -33554432 || offset > 33554428)) {
- WARN_ON_ONCE(1);
+ WARN_ON_ONCE(warn);
return 0;
}
@@ -54,10 +55,10 @@
}
unsigned long
-__arm_gen_branch(unsigned long pc, unsigned long addr, bool link)
+__arm_gen_branch(unsigned long pc, unsigned long addr, bool link, bool warn)
{
if (IS_ENABLED(CONFIG_THUMB2_KERNEL))
- return __arm_gen_branch_thumb2(pc, addr, link);
+ return __arm_gen_branch_thumb2(pc, addr, link, warn);
else
- return __arm_gen_branch_arm(pc, addr, link);
+ return __arm_gen_branch_arm(pc, addr, link, warn);
}
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index ee51403..698b6f6 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -18,7 +18,6 @@
* IRQ's are in fact implemented a bit like signal handlers for the kernel.
* Naturally it's not a 1:1 relation, but there are similarities.
*/
-#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index 0dcae78..d2b4ac0 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -16,6 +16,7 @@
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#include <asm/assembler.h>
+#include "iwmmxt.h"
#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
#define PJ4(code...) code
@@ -113,33 +114,33 @@
concan_dump:
- wstrw wCSSF, [r1, #MMX_WCSSF]
- wstrw wCASF, [r1, #MMX_WCASF]
- wstrw wCGR0, [r1, #MMX_WCGR0]
- wstrw wCGR1, [r1, #MMX_WCGR1]
- wstrw wCGR2, [r1, #MMX_WCGR2]
- wstrw wCGR3, [r1, #MMX_WCGR3]
+ wstrw wCSSF, r1, MMX_WCSSF
+ wstrw wCASF, r1, MMX_WCASF
+ wstrw wCGR0, r1, MMX_WCGR0
+ wstrw wCGR1, r1, MMX_WCGR1
+ wstrw wCGR2, r1, MMX_WCGR2
+ wstrw wCGR3, r1, MMX_WCGR3
1: @ MUP? wRn
tst r2, #0x2
beq 2f
- wstrd wR0, [r1, #MMX_WR0]
- wstrd wR1, [r1, #MMX_WR1]
- wstrd wR2, [r1, #MMX_WR2]
- wstrd wR3, [r1, #MMX_WR3]
- wstrd wR4, [r1, #MMX_WR4]
- wstrd wR5, [r1, #MMX_WR5]
- wstrd wR6, [r1, #MMX_WR6]
- wstrd wR7, [r1, #MMX_WR7]
- wstrd wR8, [r1, #MMX_WR8]
- wstrd wR9, [r1, #MMX_WR9]
- wstrd wR10, [r1, #MMX_WR10]
- wstrd wR11, [r1, #MMX_WR11]
- wstrd wR12, [r1, #MMX_WR12]
- wstrd wR13, [r1, #MMX_WR13]
- wstrd wR14, [r1, #MMX_WR14]
- wstrd wR15, [r1, #MMX_WR15]
+ wstrd wR0, r1, MMX_WR0
+ wstrd wR1, r1, MMX_WR1
+ wstrd wR2, r1, MMX_WR2
+ wstrd wR3, r1, MMX_WR3
+ wstrd wR4, r1, MMX_WR4
+ wstrd wR5, r1, MMX_WR5
+ wstrd wR6, r1, MMX_WR6
+ wstrd wR7, r1, MMX_WR7
+ wstrd wR8, r1, MMX_WR8
+ wstrd wR9, r1, MMX_WR9
+ wstrd wR10, r1, MMX_WR10
+ wstrd wR11, r1, MMX_WR11
+ wstrd wR12, r1, MMX_WR12
+ wstrd wR13, r1, MMX_WR13
+ wstrd wR14, r1, MMX_WR14
+ wstrd wR15, r1, MMX_WR15
2: teq r0, #0 @ anything to load?
reteq lr @ if not, return
@@ -147,30 +148,30 @@
concan_load:
@ Load wRn
- wldrd wR0, [r0, #MMX_WR0]
- wldrd wR1, [r0, #MMX_WR1]
- wldrd wR2, [r0, #MMX_WR2]
- wldrd wR3, [r0, #MMX_WR3]
- wldrd wR4, [r0, #MMX_WR4]
- wldrd wR5, [r0, #MMX_WR5]
- wldrd wR6, [r0, #MMX_WR6]
- wldrd wR7, [r0, #MMX_WR7]
- wldrd wR8, [r0, #MMX_WR8]
- wldrd wR9, [r0, #MMX_WR9]
- wldrd wR10, [r0, #MMX_WR10]
- wldrd wR11, [r0, #MMX_WR11]
- wldrd wR12, [r0, #MMX_WR12]
- wldrd wR13, [r0, #MMX_WR13]
- wldrd wR14, [r0, #MMX_WR14]
- wldrd wR15, [r0, #MMX_WR15]
+ wldrd wR0, r0, MMX_WR0
+ wldrd wR1, r0, MMX_WR1
+ wldrd wR2, r0, MMX_WR2
+ wldrd wR3, r0, MMX_WR3
+ wldrd wR4, r0, MMX_WR4
+ wldrd wR5, r0, MMX_WR5
+ wldrd wR6, r0, MMX_WR6
+ wldrd wR7, r0, MMX_WR7
+ wldrd wR8, r0, MMX_WR8
+ wldrd wR9, r0, MMX_WR9
+ wldrd wR10, r0, MMX_WR10
+ wldrd wR11, r0, MMX_WR11
+ wldrd wR12, r0, MMX_WR12
+ wldrd wR13, r0, MMX_WR13
+ wldrd wR14, r0, MMX_WR14
+ wldrd wR15, r0, MMX_WR15
@ Load wCx
- wldrw wCSSF, [r0, #MMX_WCSSF]
- wldrw wCASF, [r0, #MMX_WCASF]
- wldrw wCGR0, [r0, #MMX_WCGR0]
- wldrw wCGR1, [r0, #MMX_WCGR1]
- wldrw wCGR2, [r0, #MMX_WCGR2]
- wldrw wCGR3, [r0, #MMX_WCGR3]
+ wldrw wCSSF, r0, MMX_WCSSF
+ wldrw wCASF, r0, MMX_WCASF
+ wldrw wCGR0, r0, MMX_WCGR0
+ wldrw wCGR1, r0, MMX_WCGR1
+ wldrw wCGR2, r0, MMX_WCGR2
+ wldrw wCGR3, r0, MMX_WCGR3
@ clear CUP/MUP (only if r1 != 0)
teq r1, #0
diff --git a/arch/arm/kernel/iwmmxt.h b/arch/arm/kernel/iwmmxt.h
new file mode 100644
index 0000000..fb62728
--- /dev/null
+++ b/arch/arm/kernel/iwmmxt.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __IWMMXT_H__
+#define __IWMMXT_H__
+
+.irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+.set .LwR\b, \b
+.set .Lr\b, \b
+.endr
+
+.set .LwCSSF, 0x2
+.set .LwCASF, 0x3
+.set .LwCGR0, 0x8
+.set .LwCGR1, 0x9
+.set .LwCGR2, 0xa
+.set .LwCGR3, 0xb
+
+.macro wldrd, reg:req, base:req, offset:req
+.inst 0xedd00100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
+.endm
+
+.macro wldrw, reg:req, base:req, offset:req
+.inst 0xfd900100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
+.endm
+
+.macro wstrd, reg:req, base:req, offset:req
+.inst 0xedc00100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
+.endm
+
+.macro wstrw, reg:req, base:req, offset:req
+.inst 0xfd800100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
+.endm
+
+#ifdef __clang__
+
+#define wCon c1
+
+.macro tmrc, dest:req, control:req
+mrc p1, 0, \dest, \control, c0, 0
+.endm
+
+.macro tmcr, control:req, src:req
+mcr p1, 0, \src, \control, c0, 0
+.endm
+#endif
+
+#endif
diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c
index 6a95b92..22f937e 100644
--- a/arch/arm/kernel/kgdb.c
+++ b/arch/arm/kernel/kgdb.c
@@ -154,22 +154,38 @@
return 0;
}
-static struct undef_hook kgdb_brkpt_hook = {
+static struct undef_hook kgdb_brkpt_arm_hook = {
.instr_mask = 0xffffffff,
.instr_val = KGDB_BREAKINST,
- .cpsr_mask = MODE_MASK,
+ .cpsr_mask = PSR_T_BIT | MODE_MASK,
.cpsr_val = SVC_MODE,
.fn = kgdb_brk_fn
};
-static struct undef_hook kgdb_compiled_brkpt_hook = {
+static struct undef_hook kgdb_brkpt_thumb_hook = {
+ .instr_mask = 0xffff,
+ .instr_val = KGDB_BREAKINST & 0xffff,
+ .cpsr_mask = PSR_T_BIT | MODE_MASK,
+ .cpsr_val = PSR_T_BIT | SVC_MODE,
+ .fn = kgdb_brk_fn
+};
+
+static struct undef_hook kgdb_compiled_brkpt_arm_hook = {
.instr_mask = 0xffffffff,
.instr_val = KGDB_COMPILED_BREAK,
- .cpsr_mask = MODE_MASK,
+ .cpsr_mask = PSR_T_BIT | MODE_MASK,
.cpsr_val = SVC_MODE,
.fn = kgdb_compiled_brk_fn
};
+static struct undef_hook kgdb_compiled_brkpt_thumb_hook = {
+ .instr_mask = 0xffff,
+ .instr_val = KGDB_COMPILED_BREAK & 0xffff,
+ .cpsr_mask = PSR_T_BIT | MODE_MASK,
+ .cpsr_val = PSR_T_BIT | SVC_MODE,
+ .fn = kgdb_compiled_brk_fn
+};
+
static int __kgdb_notify(struct die_args *args, unsigned long cmd)
{
struct pt_regs *regs = args->regs;
@@ -210,8 +226,10 @@
if (ret != 0)
return ret;
- register_undef_hook(&kgdb_brkpt_hook);
- register_undef_hook(&kgdb_compiled_brkpt_hook);
+ register_undef_hook(&kgdb_brkpt_arm_hook);
+ register_undef_hook(&kgdb_brkpt_thumb_hook);
+ register_undef_hook(&kgdb_compiled_brkpt_arm_hook);
+ register_undef_hook(&kgdb_compiled_brkpt_thumb_hook);
return 0;
}
@@ -224,8 +242,10 @@
*/
void kgdb_arch_exit(void)
{
- unregister_undef_hook(&kgdb_brkpt_hook);
- unregister_undef_hook(&kgdb_compiled_brkpt_hook);
+ unregister_undef_hook(&kgdb_brkpt_arm_hook);
+ unregister_undef_hook(&kgdb_brkpt_thumb_hook);
+ unregister_undef_hook(&kgdb_compiled_brkpt_arm_hook);
+ unregister_undef_hook(&kgdb_compiled_brkpt_thumb_hook);
unregister_die_notifier(&kgdb_notifier);
}
@@ -236,7 +256,7 @@
/* patch_text() only supports int-sized breakpoints */
BUILD_BUG_ON(sizeof(int) != BREAK_INSTR_SIZE);
- err = probe_kernel_read(bpt->saved_instr, (char *)bpt->bpt_addr,
+ err = copy_from_kernel_nofault(bpt->saved_instr, (char *)bpt->bpt_addr,
BREAK_INSTR_SIZE);
if (err)
return err;
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 734adeb..2b09dad 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -10,9 +10,7 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/memblock.h>
-#include <asm/pgtable.h>
#include <linux/of_fdt.h>
-#include <asm/pgalloc.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
#include <asm/kexec-internal.h>
diff --git a/arch/arm/kernel/module-plts.c b/arch/arm/kernel/module-plts.c
index b647741..1fc309b 100644
--- a/arch/arm/kernel/module-plts.c
+++ b/arch/arm/kernel/module-plts.c
@@ -4,17 +4,15 @@
*/
#include <linux/elf.h>
+#include <linux/ftrace.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sort.h>
+#include <linux/moduleloader.h>
#include <asm/cache.h>
#include <asm/opcodes.h>
-#define PLT_ENT_STRIDE L1_CACHE_BYTES
-#define PLT_ENT_COUNT (PLT_ENT_STRIDE / sizeof(u32))
-#define PLT_ENT_SIZE (sizeof(struct plt_entries) / PLT_ENT_COUNT)
-
#ifdef CONFIG_THUMB2_KERNEL
#define PLT_ENT_LDR __opcode_to_mem_thumb32(0xf8dff000 | \
(PLT_ENT_STRIDE - 4))
@@ -23,9 +21,11 @@
(PLT_ENT_STRIDE - 8))
#endif
-struct plt_entries {
- u32 ldr[PLT_ENT_COUNT];
- u32 lit[PLT_ENT_COUNT];
+static const u32 fixed_plts[] = {
+#ifdef CONFIG_DYNAMIC_FTRACE
+ FTRACE_ADDR,
+ MCOUNT_ADDR,
+#endif
};
static bool in_init(const struct module *mod, unsigned long loc)
@@ -33,14 +33,40 @@
return loc - (u32)mod->init_layout.base < mod->init_layout.size;
}
+static void prealloc_fixed(struct mod_plt_sec *pltsec, struct plt_entries *plt)
+{
+ int i;
+
+ if (!ARRAY_SIZE(fixed_plts) || pltsec->plt_count)
+ return;
+ pltsec->plt_count = ARRAY_SIZE(fixed_plts);
+
+ for (i = 0; i < ARRAY_SIZE(plt->ldr); ++i)
+ plt->ldr[i] = PLT_ENT_LDR;
+
+ BUILD_BUG_ON(sizeof(fixed_plts) > sizeof(plt->lit));
+ memcpy(plt->lit, fixed_plts, sizeof(fixed_plts));
+}
+
u32 get_module_plt(struct module *mod, unsigned long loc, Elf32_Addr val)
{
struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core :
&mod->arch.init;
+ struct plt_entries *plt;
+ int idx;
- struct plt_entries *plt = (struct plt_entries *)pltsec->plt->sh_addr;
- int idx = 0;
+ /* cache the address, ELF header is available only during module load */
+ if (!pltsec->plt_ent)
+ pltsec->plt_ent = (struct plt_entries *)pltsec->plt->sh_addr;
+ plt = pltsec->plt_ent;
+ prealloc_fixed(pltsec, plt);
+
+ for (idx = 0; idx < ARRAY_SIZE(fixed_plts); ++idx)
+ if (plt->lit[idx] == val)
+ return (u32)&plt->ldr[idx];
+
+ idx = 0;
/*
* Look for an existing entry pointing to 'val'. Given that the
* relocations are sorted, this will be the last entry we allocated.
@@ -188,8 +214,8 @@
int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
char *secstrings, struct module *mod)
{
- unsigned long core_plts = 0;
- unsigned long init_plts = 0;
+ unsigned long core_plts = ARRAY_SIZE(fixed_plts);
+ unsigned long init_plts = ARRAY_SIZE(fixed_plts);
Elf32_Shdr *s, *sechdrs_end = sechdrs + ehdr->e_shnum;
Elf32_Sym *syms = NULL;
@@ -244,6 +270,7 @@
mod->arch.core.plt->sh_size = round_up(core_plts * PLT_ENT_SIZE,
sizeof(struct plt_entries));
mod->arch.core.plt_count = 0;
+ mod->arch.core.plt_ent = NULL;
mod->arch.init.plt->sh_type = SHT_NOBITS;
mod->arch.init.plt->sh_flags = SHF_EXECINSTR | SHF_ALLOC;
@@ -251,6 +278,7 @@
mod->arch.init.plt->sh_size = round_up(init_plts * PLT_ENT_SIZE,
sizeof(struct plt_entries));
mod->arch.init.plt_count = 0;
+ mod->arch.init.plt_ent = NULL;
pr_debug("%s: plt=%x, init.plt=%x\n", __func__,
mod->arch.core.plt->sh_size, mod->arch.init.plt->sh_size);
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index deef17f..e15444b 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -17,7 +17,6 @@
#include <linux/string.h>
#include <linux/gfp.h>
-#include <asm/pgtable.h>
#include <asm/sections.h>
#include <asm/smp_plat.h>
#include <asm/unwind.h>
@@ -55,6 +54,13 @@
}
#endif
+bool module_init_section(const char *name)
+{
+ return strstarts(name, ".init") ||
+ strstarts(name, ".ARM.extab.init") ||
+ strstarts(name, ".ARM.exidx.init");
+}
+
bool module_exit_section(const char *name)
{
return strstarts(name, ".exit") ||
@@ -409,8 +415,17 @@
#ifdef CONFIG_ARM_UNWIND
int i;
- for (i = 0; i < ARM_SEC_MAX; i++)
- if (mod->arch.unwind[i])
- unwind_table_del(mod->arch.unwind[i]);
+ for (i = 0; i < ARM_SEC_MAX; i++) {
+ unwind_table_del(mod->arch.unwind[i]);
+ mod->arch.unwind[i] = NULL;
+ }
+#endif
+}
+
+void __weak module_arch_freeing_init(struct module *mod)
+{
+#ifdef CONFIG_ARM_UNWIND
+ unwind_table_del(mod->arch.unwind[ARM_SEC_INIT]);
+ mod->arch.unwind[ARM_SEC_INIT] = NULL;
#endif
}
diff --git a/arch/arm/kernel/patch.c b/arch/arm/kernel/patch.c
index d0a05a3..e9e828b 100644
--- a/arch/arm/kernel/patch.c
+++ b/arch/arm/kernel/patch.c
@@ -16,10 +16,10 @@
unsigned int insn;
};
+#ifdef CONFIG_MMU
static DEFINE_RAW_SPINLOCK(patch_lock);
static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags)
- __acquires(&patch_lock)
{
unsigned int uintaddr = (uintptr_t) addr;
bool module = !core_kernel_text(uintaddr);
@@ -34,8 +34,6 @@
if (flags)
raw_spin_lock_irqsave(&patch_lock, *flags);
- else
- __acquire(&patch_lock);
set_fixmap(fixmap, page_to_phys(page));
@@ -43,15 +41,19 @@
}
static void __kprobes patch_unmap(int fixmap, unsigned long *flags)
- __releases(&patch_lock)
{
clear_fixmap(fixmap);
if (flags)
raw_spin_unlock_irqrestore(&patch_lock, *flags);
- else
- __release(&patch_lock);
}
+#else
+static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags)
+{
+ return addr;
+}
+static void __kprobes patch_unmap(int fixmap, unsigned long *flags) { }
+#endif
void __kprobes __patch_text_real(void *addr, unsigned int insn, bool remap)
{
@@ -64,8 +66,6 @@
if (remap)
waddr = patch_map(addr, FIX_TEXT_POKE0, &flags);
- else
- __acquire(&patch_lock);
if (thumb2 && __opcode_is_thumb16(insn)) {
*(u16 *)waddr = __opcode_to_mem_thumb16(insn);
@@ -102,8 +102,7 @@
if (waddr != addr) {
flush_kernel_vmap_range(waddr, twopage ? size / 2 : size);
patch_unmap(FIX_TEXT_POKE0, &flags);
- } else
- __release(&patch_lock);
+ }
flush_icache_range((uintptr_t)(addr),
(uintptr_t)(addr) + size);
diff --git a/arch/arm/kernel/perf_callchain.c b/arch/arm/kernel/perf_callchain.c
index 3b69a76..1626dfc 100644
--- a/arch/arm/kernel/perf_callchain.c
+++ b/arch/arm/kernel/perf_callchain.c
@@ -62,9 +62,10 @@
void
perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
{
+ struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
struct frame_tail __user *tail;
- if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+ if (guest_cbs && guest_cbs->is_in_guest()) {
/* We don't support guest os callchain now */
return;
}
@@ -98,9 +99,10 @@
void
perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
{
+ struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
struct stackframe fr;
- if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+ if (guest_cbs && guest_cbs->is_in_guest()) {
/* We don't support guest os callchain now */
return;
}
@@ -111,18 +113,21 @@
unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
- if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
- return perf_guest_cbs->get_guest_ip();
+ struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
+
+ if (guest_cbs && guest_cbs->is_in_guest())
+ return guest_cbs->get_guest_ip();
return instruction_pointer(regs);
}
unsigned long perf_misc_flags(struct pt_regs *regs)
{
+ struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs();
int misc = 0;
- if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
- if (perf_guest_cbs->is_user_mode())
+ if (guest_cbs && guest_cbs->is_in_guest()) {
+ if (guest_cbs->is_user_mode())
misc |= PERF_RECORD_MISC_GUEST_USER;
else
misc |= PERF_RECORD_MISC_GUEST_KERNEL;
diff --git a/arch/arm/kernel/perf_regs.c b/arch/arm/kernel/perf_regs.c
index 05fe92a..0529f90 100644
--- a/arch/arm/kernel/perf_regs.c
+++ b/arch/arm/kernel/perf_regs.c
@@ -32,8 +32,7 @@
}
void perf_get_regs_user(struct perf_regs *regs_user,
- struct pt_regs *regs,
- struct pt_regs *regs_user_copy)
+ struct pt_regs *regs)
{
regs_user->regs = task_pt_regs(current);
regs_user->abi = perf_reg_abi(current);
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index e7fac12..9f199b1 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -36,6 +36,8 @@
#include <asm/tls.h>
#include <asm/vdso.h>
+#include "signal.h"
+
#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK)
#include <linux/stackprotector.h>
unsigned long __stack_chk_guard __read_mostly;
@@ -69,7 +71,7 @@
arm_pm_idle();
else
cpu_do_idle();
- local_irq_enable();
+ raw_local_irq_enable();
}
void arch_cpu_idle_prepare(void)
@@ -223,9 +225,8 @@
asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
-int
-copy_thread_tls(unsigned long clone_flags, unsigned long stack_start,
- unsigned long stk_sz, struct task_struct *p, unsigned long tls)
+int copy_thread(unsigned long clone_flags, unsigned long stack_start,
+ unsigned long stk_sz, struct task_struct *p, unsigned long tls)
{
struct thread_info *thread = task_thread_info(p);
struct pt_regs *childregs = task_pt_regs(p);
@@ -280,21 +281,6 @@
return 1;
}
-/*
- * fill in the fpe structure for a core dump...
- */
-int dump_fpu (struct pt_regs *regs, struct user_fp *fp)
-{
- struct thread_info *thread = current_thread_info();
- int used_math = thread->used_cp[1] | thread->used_cp[2];
-
- if (used_math)
- memcpy(fp, &thread->fpstate.soft, sizeof (*fp));
-
- return used_math != 0;
-}
-EXPORT_SYMBOL(dump_fpu);
-
unsigned long get_wchan(struct task_struct *p)
{
struct stackframe frame;
@@ -429,7 +415,7 @@
npages = 1; /* for sigpage */
npages += vdso_total_pages;
- if (down_write_killable(&mm->mmap_sem))
+ if (mmap_write_lock_killable(mm))
return -EINTR;
hint = sigpage_addr(mm, npages);
addr = get_unmapped_area(NULL, hint, npages << PAGE_SHIFT, 0, 0);
@@ -456,7 +442,7 @@
arm_install_vdso(mm, addr + PAGE_SIZE);
up_fail:
- up_write(&mm->mmap_sem);
+ mmap_write_unlock(mm);
return ret;
}
#endif
diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c
index aba6b2a..d4392e1 100644
--- a/arch/arm/kernel/psci_smp.c
+++ b/arch/arm/kernel/psci_smp.c
@@ -51,7 +51,7 @@
}
#ifdef CONFIG_HOTPLUG_CPU
-int psci_cpu_disable(unsigned int cpu)
+static int psci_cpu_disable(unsigned int cpu)
{
/* Fail early if we don't have CPU_OFF support */
if (!psci_ops.cpu_off)
@@ -64,7 +64,7 @@
return 0;
}
-void psci_cpu_die(unsigned int cpu)
+static void psci_cpu_die(unsigned int cpu)
{
u32 state = PSCI_POWER_STATE_TYPE_POWER_DOWN <<
PSCI_0_2_POWER_STATE_TYPE_SHIFT;
@@ -76,7 +76,7 @@
panic("psci: cpu %d failed to shutdown\n", cpu);
}
-int psci_cpu_kill(unsigned int cpu)
+static int psci_cpu_kill(unsigned int cpu)
{
int err, i;
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index db94015..2771e68 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -25,7 +25,6 @@
#include <linux/tracehook.h>
#include <linux/unistd.h>
-#include <asm/pgtable.h>
#include <asm/traps.h>
#define CREATE_TRACE_POINTS
@@ -570,14 +569,9 @@
static int gpr_get(struct task_struct *target,
const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
+ struct membuf to)
{
- struct pt_regs *regs = task_pt_regs(target);
-
- return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- regs,
- 0, sizeof(*regs));
+ return membuf_write(&to, task_pt_regs(target), sizeof(struct pt_regs));
}
static int gpr_set(struct task_struct *target,
@@ -603,12 +597,10 @@
static int fpa_get(struct task_struct *target,
const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
+ struct membuf to)
{
- return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &task_thread_info(target)->fpstate,
- 0, sizeof(struct user_fp));
+ return membuf_write(&to, &task_thread_info(target)->fpstate,
+ sizeof(struct user_fp));
}
static int fpa_set(struct task_struct *target,
@@ -643,41 +635,20 @@
* vfp_set() ignores this chunk
*
* 1 word for the FPSCR
- *
- * The bounds-checking logic built into user_regset_copyout and friends
- * means that we can make a simple sequence of calls to map the relevant data
- * to/from the specified slice of the user regset structure.
*/
static int vfp_get(struct task_struct *target,
const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
+ struct membuf to)
{
- int ret;
struct thread_info *thread = task_thread_info(target);
struct vfp_hard_struct const *vfp = &thread->vfpstate.hard;
- const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs);
const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr);
vfp_sync_hwstate(thread);
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &vfp->fpregs,
- user_fpregs_offset,
- user_fpregs_offset + sizeof(vfp->fpregs));
- if (ret)
- return ret;
-
- ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- user_fpregs_offset + sizeof(vfp->fpregs),
- user_fpscr_offset);
- if (ret)
- return ret;
-
- return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &vfp->fpscr,
- user_fpscr_offset,
- user_fpscr_offset + sizeof(vfp->fpscr));
+ membuf_write(&to, vfp->fpregs, sizeof(vfp->fpregs));
+ membuf_zero(&to, user_fpscr_offset - sizeof(vfp->fpregs));
+ return membuf_store(&to, vfp->fpscr);
}
/*
@@ -740,7 +711,7 @@
.n = ELF_NGREG,
.size = sizeof(u32),
.align = sizeof(u32),
- .get = gpr_get,
+ .regset_get = gpr_get,
.set = gpr_set
},
[REGSET_FPR] = {
@@ -752,7 +723,7 @@
.n = sizeof(struct user_fp) / sizeof(u32),
.size = sizeof(u32),
.align = sizeof(u32),
- .get = fpa_get,
+ .regset_get = fpa_get,
.set = fpa_set
},
#ifdef CONFIG_VFP
@@ -765,7 +736,7 @@
.n = ARM_VFPREGS_SIZE / sizeof(u32),
.size = sizeof(u32),
.align = sizeof(u32),
- .get = vfp_get,
+ .regset_get = vfp_get,
.set = vfp_set
},
#endif /* CONFIG_VFP */
@@ -923,7 +894,7 @@
/* Do seccomp after ptrace; syscall may have changed. */
#ifdef CONFIG_HAVE_ARCH_SECCOMP_FILTER
- if (secure_computing(NULL) == -1)
+ if (secure_computing() == -1)
return -1;
#else
/* XXX: remove this once OABI gets fixed */
diff --git a/arch/arm/kernel/reboot.c b/arch/arm/kernel/reboot.c
index bb18ed0..0ce388f 100644
--- a/arch/arm/kernel/reboot.c
+++ b/arch/arm/kernel/reboot.c
@@ -88,11 +88,11 @@
* to execute e.g. a RAM-based pin loop is not sufficient. This allows the
* kexec'd kernel to use any and all RAM as it sees fit, without having to
* avoid any code or data used by any SW CPU pin loop. The CPU hotplug
- * functionality embodied in disable_nonboot_cpus() to achieve this.
+ * functionality embodied in smp_shutdown_nonboot_cpus() to achieve this.
*/
void machine_shutdown(void)
{
- disable_nonboot_cpus();
+ smp_shutdown_nonboot_cpus(reboot_cpu);
}
/*
diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index 5e15b59..218d524 100644
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -27,26 +27,26 @@
ldr r3, [r0],#4
/* Is it a destination page. Put destination address to r4 */
- tst r3,#1,0
+ tst r3,#1
beq 1f
bic r4,r3,#1
b 0b
1:
/* Is it an indirection page */
- tst r3,#2,0
+ tst r3,#2
beq 1f
bic r0,r3,#2
b 0b
1:
/* are we done ? */
- tst r3,#4,0
+ tst r3,#4
beq 1f
b 2f
1:
/* is it source ? */
- tst r3,#8,0
+ tst r3,#8
beq 0b
bic r3,r3,#8
mov r6,#1024
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 43d6a60..b06602c 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -846,20 +846,26 @@
static void __init request_standard_resources(const struct machine_desc *mdesc)
{
- struct memblock_region *region;
+ phys_addr_t start, end, res_end;
struct resource *res;
+ u64 i;
kernel_code.start = virt_to_phys(_text);
kernel_code.end = virt_to_phys(__init_begin - 1);
kernel_data.start = virt_to_phys(_sdata);
kernel_data.end = virt_to_phys(_end - 1);
- for_each_memblock(memory, region) {
- phys_addr_t start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
- phys_addr_t end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
+ for_each_mem_range(i, &start, &end) {
unsigned long boot_alias_start;
/*
+ * In memblock, end points to the first byte after the
+ * range while in resourses, end points to the last byte in
+ * the range.
+ */
+ res_end = end - 1;
+
+ /*
* Some systems have a special memory alias which is only
* used for booting. We need to advertise this region to
* kexec-tools so they know where bootable RAM is located.
@@ -872,7 +878,7 @@
__func__, sizeof(*res));
res->name = "System RAM (boot alias)";
res->start = boot_alias_start;
- res->end = phys_to_idmap(end);
+ res->end = phys_to_idmap(res_end);
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
request_resource(&iomem_resource, res);
}
@@ -883,7 +889,7 @@
sizeof(*res));
res->name = "System RAM";
res->start = start;
- res->end = end;
+ res->end = res_end;
res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
request_resource(&iomem_resource, res);
@@ -1175,8 +1181,6 @@
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
-#elif defined(CONFIG_DUMMY_CONSOLE)
- conswitchp = &dummy_con;
#endif
#endif
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index c01f76c..2f81d3a 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -596,7 +596,7 @@
switch (retval) {
case -ERESTART_RESTARTBLOCK:
restart -= 2;
- /* Fall through */
+ fallthrough;
case -ERESTARTNOHAND:
case -ERESTARTSYS:
case -ERESTARTNOINTR:
@@ -669,7 +669,6 @@
} else if (thread_flags & _TIF_UPROBE) {
uprobe_notify_resume(regs);
} else {
- clear_thread_flag(TIF_NOTIFY_RESUME);
tracehook_notify_resume(regs);
rseq_handle_notify_resume(NULL, regs);
}
@@ -715,7 +714,9 @@
/* Defer to generic check */
asmlinkage void addr_limit_check_failed(void)
{
+#ifdef CONFIG_MMU
addr_limit_user_check();
+#endif
}
#ifdef CONFIG_DEBUG_RSEQ
diff --git a/arch/arm/kernel/signal.h b/arch/arm/kernel/signal.h
index b7b838b..cb076d3 100644
--- a/arch/arm/kernel/signal.h
+++ b/arch/arm/kernel/signal.h
@@ -9,3 +9,5 @@
struct siginfo info;
struct sigframe sig;
};
+
+extern struct page *get_signal_page(void);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 46e1be9..8aa7fa9 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -26,6 +26,7 @@
#include <linux/completion.h>
#include <linux/cpufreq.h>
#include <linux/irq_work.h>
+#include <linux/kernel_stat.h>
#include <linux/atomic.h>
#include <asm/bugs.h>
@@ -37,8 +38,6 @@
#include <asm/idmap.h>
#include <asm/topology.h>
#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
#include <asm/procinfo.h>
#include <asm/processor.h>
#include <asm/sections.h>
@@ -67,18 +66,26 @@
IPI_CPU_STOP,
IPI_IRQ_WORK,
IPI_COMPLETION,
+ NR_IPI,
/*
* CPU_BACKTRACE is special and not included in NR_IPI
* or tracable with trace_ipi_*
*/
- IPI_CPU_BACKTRACE,
+ IPI_CPU_BACKTRACE = NR_IPI,
/*
* SGI8-15 can be reserved by secure firmware, and thus may
* not be usable by the kernel. Please keep the above limited
* to at most 8 entries.
*/
+ MAX_IPI
};
+static int ipi_irq_base __read_mostly;
+static int nr_ipi __read_mostly = NR_IPI;
+static struct irq_desc *ipi_desc[MAX_IPI] __read_mostly;
+
+static void ipi_setup(int cpu);
+
static DECLARE_COMPLETION(cpu_running);
static struct smp_operations smp_ops __ro_after_init;
@@ -228,6 +235,17 @@
return cpu != 0;
}
+static void ipi_teardown(int cpu)
+{
+ int i;
+
+ if (WARN_ON_ONCE(!ipi_irq_base))
+ return;
+
+ for (i = 0; i < nr_ipi; i++)
+ disable_percpu_irq(ipi_irq_base + i);
+}
+
/*
* __cpu_disable runs on the processor to be shutdown.
*/
@@ -249,6 +267,7 @@
* and we must not schedule until we're ready to give up the cpu.
*/
set_cpu_online(cpu, false);
+ ipi_teardown(cpu);
/*
* OK - migrate IRQs away from this CPU
@@ -413,7 +432,6 @@
#endif
pr_debug("CPU%u: Booted secondary processor\n", cpu);
- preempt_disable();
trace_hardirqs_off();
/*
@@ -424,6 +442,8 @@
notify_cpu_starting(cpu);
+ ipi_setup(cpu);
+
calibrate_delay();
smp_store_cpu_info(cpu);
@@ -502,14 +522,6 @@
}
}
-static void (*__smp_cross_call)(const struct cpumask *, unsigned int);
-
-void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
-{
- if (!__smp_cross_call)
- __smp_cross_call = fn;
-}
-
static const char *ipi_types[NR_IPI] __tracepoint_string = {
#define S(x,s) [x] = s
S(IPI_WAKEUP, "CPU wakeup interrupts"),
@@ -521,38 +533,28 @@
S(IPI_COMPLETION, "completion interrupts"),
};
-static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
-{
- trace_ipi_raise_rcuidle(target, ipi_types[ipinr]);
- __smp_cross_call(target, ipinr);
-}
+static void smp_cross_call(const struct cpumask *target, unsigned int ipinr);
void show_ipi_list(struct seq_file *p, int prec)
{
unsigned int cpu, i;
for (i = 0; i < NR_IPI; i++) {
+ unsigned int irq;
+
+ if (!ipi_desc[i])
+ continue;
+
+ irq = irq_desc_get_irq(ipi_desc[i]);
seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
for_each_online_cpu(cpu)
- seq_printf(p, "%10u ",
- __get_irq_stat(cpu, ipi_irqs[i]));
+ seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
seq_printf(p, " %s\n", ipi_types[i]);
}
}
-u64 smp_irq_stat_cpu(unsigned int cpu)
-{
- u64 sum = 0;
- int i;
-
- for (i = 0; i < NR_IPI; i++)
- sum += __get_irq_stat(cpu, ipi_irqs[i]);
-
- return sum;
-}
-
void arch_send_call_function_ipi_mask(const struct cpumask *mask)
{
smp_cross_call(mask, IPI_CALL_FUNC);
@@ -629,15 +631,12 @@
handle_IPI(ipinr, regs);
}
-void handle_IPI(int ipinr, struct pt_regs *regs)
+static void do_handle_IPI(int ipinr)
{
unsigned int cpu = smp_processor_id();
- struct pt_regs *old_regs = set_irq_regs(regs);
- if ((unsigned)ipinr < NR_IPI) {
+ if ((unsigned)ipinr < NR_IPI)
trace_ipi_entry_rcuidle(ipi_types[ipinr]);
- __inc_irq_stat(cpu, ipi_irqs[ipinr]);
- }
switch (ipinr) {
case IPI_WAKEUP:
@@ -645,9 +644,7 @@
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
case IPI_TIMER:
- irq_enter();
tick_receive_broadcast();
- irq_exit();
break;
#endif
@@ -656,36 +653,26 @@
break;
case IPI_CALL_FUNC:
- irq_enter();
generic_smp_call_function_interrupt();
- irq_exit();
break;
case IPI_CPU_STOP:
- irq_enter();
ipi_cpu_stop(cpu);
- irq_exit();
break;
#ifdef CONFIG_IRQ_WORK
case IPI_IRQ_WORK:
- irq_enter();
irq_work_run();
- irq_exit();
break;
#endif
case IPI_COMPLETION:
- irq_enter();
ipi_complete(cpu);
- irq_exit();
break;
case IPI_CPU_BACKTRACE:
printk_nmi_enter();
- irq_enter();
- nmi_cpu_backtrace(regs);
- irq_exit();
+ nmi_cpu_backtrace(get_irq_regs());
printk_nmi_exit();
break;
@@ -697,9 +684,67 @@
if ((unsigned)ipinr < NR_IPI)
trace_ipi_exit_rcuidle(ipi_types[ipinr]);
+}
+
+/* Legacy version, should go away once all irqchips have been converted */
+void handle_IPI(int ipinr, struct pt_regs *regs)
+{
+ struct pt_regs *old_regs = set_irq_regs(regs);
+
+ irq_enter();
+ do_handle_IPI(ipinr);
+ irq_exit();
+
set_irq_regs(old_regs);
}
+static irqreturn_t ipi_handler(int irq, void *data)
+{
+ do_handle_IPI(irq - ipi_irq_base);
+ return IRQ_HANDLED;
+}
+
+static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
+{
+ trace_ipi_raise_rcuidle(target, ipi_types[ipinr]);
+ __ipi_send_mask(ipi_desc[ipinr], target);
+}
+
+static void ipi_setup(int cpu)
+{
+ int i;
+
+ if (WARN_ON_ONCE(!ipi_irq_base))
+ return;
+
+ for (i = 0; i < nr_ipi; i++)
+ enable_percpu_irq(ipi_irq_base + i, 0);
+}
+
+void __init set_smp_ipi_range(int ipi_base, int n)
+{
+ int i;
+
+ WARN_ON(n < MAX_IPI);
+ nr_ipi = min(n, MAX_IPI);
+
+ for (i = 0; i < nr_ipi; i++) {
+ int err;
+
+ err = request_percpu_irq(ipi_base + i, ipi_handler,
+ "IPI", &irq_stat);
+ WARN_ON(err);
+
+ ipi_desc[i] = irq_to_desc(ipi_base + i);
+ irq_set_status_flags(ipi_base + i, IRQ_HIDDEN);
+ }
+
+ ipi_irq_base = ipi_base;
+
+ /* Setup the boot CPU immediately */
+ ipi_setup(smp_processor_id());
+}
+
void smp_send_reschedule(int cpu)
{
smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
@@ -807,7 +852,7 @@
static void raise_nmi(cpumask_t *mask)
{
- __smp_cross_call(mask, IPI_CPU_BACKTRACE);
+ __ipi_send_mask(ipi_desc[IPI_CPU_BACKTRACE], mask);
}
void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
diff --git a/arch/arm/kernel/spectre.c b/arch/arm/kernel/spectre.c
new file mode 100644
index 0000000..0dcefc3
--- /dev/null
+++ b/arch/arm/kernel/spectre.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/bpf.h>
+#include <linux/cpu.h>
+#include <linux/device.h>
+
+#include <asm/spectre.h>
+
+static bool _unprivileged_ebpf_enabled(void)
+{
+#ifdef CONFIG_BPF_SYSCALL
+ return !sysctl_unprivileged_bpf_disabled;
+#else
+ return false;
+#endif
+}
+
+ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "Mitigation: __user pointer sanitization\n");
+}
+
+static unsigned int spectre_v2_state;
+static unsigned int spectre_v2_methods;
+
+void spectre_v2_update_state(unsigned int state, unsigned int method)
+{
+ if (state > spectre_v2_state)
+ spectre_v2_state = state;
+ spectre_v2_methods |= method;
+}
+
+ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ const char *method;
+
+ if (spectre_v2_state == SPECTRE_UNAFFECTED)
+ return sprintf(buf, "%s\n", "Not affected");
+
+ if (spectre_v2_state != SPECTRE_MITIGATED)
+ return sprintf(buf, "%s\n", "Vulnerable");
+
+ if (_unprivileged_ebpf_enabled())
+ return sprintf(buf, "Vulnerable: Unprivileged eBPF enabled\n");
+
+ switch (spectre_v2_methods) {
+ case SPECTRE_V2_METHOD_BPIALL:
+ method = "Branch predictor hardening";
+ break;
+
+ case SPECTRE_V2_METHOD_ICIALLU:
+ method = "I-cache invalidation";
+ break;
+
+ case SPECTRE_V2_METHOD_SMC:
+ case SPECTRE_V2_METHOD_HVC:
+ method = "Firmware call";
+ break;
+
+ case SPECTRE_V2_METHOD_LOOP8:
+ method = "History overwrite";
+ break;
+
+ default:
+ method = "Multiple mitigations";
+ break;
+ }
+
+ return sprintf(buf, "Mitigation: %s\n", method);
+}
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index 76ea417..db798ea 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -54,8 +54,7 @@
frame->sp = frame->fp;
frame->fp = *(unsigned long *)(fp);
- frame->pc = frame->lr;
- frame->lr = *(unsigned long *)(fp + 4);
+ frame->pc = *(unsigned long *)(fp + 4);
#else
/* check current frame pointer is within bounds */
if (fp < low + 12 || fp > high - 4)
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
index e126386..43f0a3e 100644
--- a/arch/arm/kernel/suspend.c
+++ b/arch/arm/kernel/suspend.c
@@ -3,12 +3,11 @@
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/mm_types.h>
+#include <linux/pgtable.h>
#include <asm/bugs.h>
#include <asm/cacheflush.h>
#include <asm/idmap.h>
-#include <asm/pgalloc.h>
-#include <asm/pgtable.h>
#include <asm/memory.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c
index e640871..6166ba3 100644
--- a/arch/arm/kernel/swp_emulate.c
+++ b/arch/arm/kernel/swp_emulate.c
@@ -97,12 +97,12 @@
{
int si_code;
- down_read(¤t->mm->mmap_sem);
+ mmap_read_lock(current->mm);
if (find_vma(current->mm, addr) == NULL)
si_code = SEGV_MAPERR;
else
si_code = SEGV_ACCERR;
- up_read(¤t->mm->mmap_sem);
+ mmap_read_unlock(current->mm);
pr_debug("SWP{B} emulation: access caused memory abort!\n");
arm_notify_die("Illegal memory access", regs,
diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c
index 17bd32b..075a2e0 100644
--- a/arch/arm/kernel/sys_oabi-compat.c
+++ b/arch/arm/kernel/sys_oabi-compat.c
@@ -248,25 +248,21 @@
__u64 data;
} __attribute__ ((packed,aligned(4)));
+#ifdef CONFIG_EPOLL
asmlinkage long sys_oabi_epoll_ctl(int epfd, int op, int fd,
struct oabi_epoll_event __user *event)
{
struct oabi_epoll_event user;
struct epoll_event kernel;
- mm_segment_t fs;
- long ret;
- if (op == EPOLL_CTL_DEL)
- return sys_epoll_ctl(epfd, op, fd, NULL);
- if (copy_from_user(&user, event, sizeof(user)))
+ if (ep_op_has_event(op) &&
+ copy_from_user(&user, event, sizeof(user)))
return -EFAULT;
+
kernel.events = user.events;
kernel.data = user.data;
- fs = get_fs();
- set_fs(KERNEL_DS);
- ret = sys_epoll_ctl(epfd, op, fd, &kernel);
- set_fs(fs);
- return ret;
+
+ return do_epoll_ctl(epfd, op, fd, &kernel, false);
}
asmlinkage long sys_oabi_epoll_wait(int epfd,
@@ -303,6 +299,20 @@
kfree(kbuf);
return err ? -EFAULT : ret;
}
+#else
+asmlinkage long sys_oabi_epoll_ctl(int epfd, int op, int fd,
+ struct oabi_epoll_event __user *event)
+{
+ return -EINVAL;
+}
+
+asmlinkage long sys_oabi_epoll_wait(int epfd,
+ struct oabi_epoll_event __user *events,
+ int maxevents, int timeout)
+{
+ return -EINVAL;
+}
+#endif
struct oabi_sembuf {
unsigned short sem_num;
diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
index 9d9b1db..d3a85f0 100644
--- a/arch/arm/kernel/tcm.c
+++ b/arch/arm/kernel/tcm.c
@@ -18,6 +18,7 @@
#include <asm/memory.h>
#include <asm/system_info.h>
#include <asm/traps.h>
+#include <asm/tcm.h>
#define TCMTR_FORMAT_MASK 0xe0000000U
@@ -30,8 +31,8 @@
extern char __dtcm_start, __sdtcm_data, __edtcm_data;
/* These will be increased as we run */
-u32 dtcm_end = DTCM_OFFSET;
-u32 itcm_end = ITCM_OFFSET;
+static u32 dtcm_end = DTCM_OFFSET;
+static u32 itcm_end = ITCM_OFFSET;
/*
* TCM memory resources
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index b996b2c..09b149b 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -8,7 +8,7 @@
* This file contains the ARM-specific time handling details:
* reading the RTC at bootup, etc...
*/
-#include <linux/clk-provider.h>
+#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/errno.h>
#include <linux/export.h>
@@ -16,6 +16,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
+#include <linux/of_clk.h>
#include <linux/profile.h>
#include <linux/sched.h>
#include <linux/sched_clock.h>
@@ -107,5 +108,6 @@
of_clk_init(NULL);
#endif
timer_probe();
+ tick_setup_hrtimer_broadcast();
}
}
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 8d2e61d..ef0058d 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -95,7 +95,7 @@
GFP_NOWAIT);
for_each_possible_cpu(cpu) {
- const u32 *rate;
+ const __be32 *rate;
int len;
/* too early to use cpu->of_node */
@@ -178,15 +178,6 @@
#endif
/*
- * The current assumption is that we can power gate each core independently.
- * This will be superseded by DT binding once available.
- */
-const struct cpumask *cpu_corepower_mask(int cpu)
-{
- return &cpu_topology[cpu].thread_sibling;
-}
-
-/*
* store_cpu_topology is called at boot when only one cpu is running
* and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
* which prevents simultaneous write access to cpu_topology array
@@ -241,20 +232,6 @@
update_siblings_masks(cpuid);
}
-static inline int cpu_corepower_flags(void)
-{
- return SD_SHARE_PKG_RESOURCES | SD_SHARE_POWERDOMAIN;
-}
-
-static struct sched_domain_topology_level arm_topology[] = {
-#ifdef CONFIG_SCHED_MC
- { cpu_corepower_mask, cpu_corepower_flags, SD_INIT_NAME(GMC) },
- { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
-#endif
- { cpu_cpu_mask, SD_INIT_NAME(DIE) },
- { NULL, },
-};
-
/*
* init_cpu_topology is called at boot when only one cpu is running
* which prevent simultaneous write access to cpu_topology array
@@ -265,7 +242,4 @@
smp_wmb();
parse_dt_topology();
-
- /* Set scheduler topology descriptor */
- set_sched_topology(arm_topology);
}
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 97a5125..2d9e72a 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -30,6 +30,7 @@
#include <linux/atomic.h>
#include <asm/cacheflush.h>
#include <asm/exception.h>
+#include <asm/spectre.h>
#include <asm/unistd.h>
#include <asm/traps.h>
#include <asm/ptrace.h>
@@ -62,21 +63,24 @@
static void dump_mem(const char *, const char *, unsigned long, unsigned long);
-void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame)
+void dump_backtrace_entry(unsigned long where, unsigned long from,
+ unsigned long frame, const char *loglvl)
{
unsigned long end = frame + 4 + sizeof(struct pt_regs);
#ifdef CONFIG_KALLSYMS
- printk("[<%08lx>] (%ps) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
+ printk("%s[<%08lx>] (%ps) from [<%08lx>] (%pS)\n",
+ loglvl, where, (void *)where, from, (void *)from);
#else
- printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
+ printk("%sFunction entered at [<%08lx>] from [<%08lx>]\n",
+ loglvl, where, from);
#endif
if (in_entry_text(from) && end <= ALIGN(frame, THREAD_SIZE))
- dump_mem("", "Exception stack", frame + 4, end);
+ dump_mem(loglvl, "Exception stack", frame + 4, end);
}
-void dump_backtrace_stm(u32 *stack, u32 instruction)
+void dump_backtrace_stm(u32 *stack, u32 instruction, const char *loglvl)
{
char str[80], *p;
unsigned int x;
@@ -88,12 +92,12 @@
if (++x == 6) {
x = 0;
p = str;
- printk("%s\n", str);
+ printk("%s%s\n", loglvl, str);
}
}
}
if (p != str)
- printk("%s\n", str);
+ printk("%s%s\n", loglvl, str);
}
#ifndef CONFIG_ARM_UNWIND
@@ -201,17 +205,19 @@
}
#ifdef CONFIG_ARM_UNWIND
-static inline void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
+static inline void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk,
+ const char *loglvl)
{
- unwind_backtrace(regs, tsk);
+ unwind_backtrace(regs, tsk, loglvl);
}
#else
-static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
+static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk,
+ const char *loglvl)
{
unsigned int fp, mode;
int ok = 1;
- printk("Backtrace: ");
+ printk("%sBacktrace: ", loglvl);
if (!tsk)
tsk = current;
@@ -238,18 +244,20 @@
pr_cont("\n");
if (ok)
- c_backtrace(fp, mode);
+ c_backtrace(fp, mode, loglvl);
}
#endif
-void show_stack(struct task_struct *tsk, unsigned long *sp)
+void show_stack(struct task_struct *tsk, unsigned long *sp, const char *loglvl)
{
- dump_backtrace(NULL, tsk);
+ dump_backtrace(NULL, tsk, loglvl);
barrier();
}
#ifdef CONFIG_PREEMPT
#define S_PREEMPT " PREEMPT"
+#elif defined(CONFIG_PREEMPT_RT)
+#define S_PREEMPT " PREEMPT_RT"
#else
#define S_PREEMPT ""
#endif
@@ -286,7 +294,7 @@
if (!user_mode(regs) || in_interrupt()) {
dump_mem(KERN_EMERG, "Stack: ", regs->ARM_sp,
THREAD_SIZE + (unsigned long)task_stack_page(tsk));
- dump_backtrace(regs, tsk);
+ dump_backtrace(regs, tsk, KERN_EMERG);
dump_instr(KERN_EMERG, regs);
}
@@ -389,7 +397,7 @@
u32 insn = __opcode_to_mem_arm(BUG_INSTR_VALUE);
#endif
- if (probe_kernel_address((unsigned *)pc, bkpt))
+ if (get_kernel_nofault(bkpt, (void *)pc))
return 0;
return bkpt == insn;
@@ -564,7 +572,7 @@
if (fatal_signal_pending(current))
return 0;
- ret = flush_cache_user_range(start, start + chunk);
+ ret = flush_icache_user_range(start, start + chunk);
if (ret)
return ret;
@@ -661,10 +669,10 @@
if (user_debug & UDBG_SYSCALL) {
pr_err("[%d] %s: arm syscall %d\n",
task_pid_nr(current), current->comm, no);
- dump_instr("", regs);
+ dump_instr(KERN_ERR, regs);
if (user_mode(regs)) {
__show_regs(regs);
- c_backtrace(frame_pointer(regs), processor_mode(regs));
+ c_backtrace(frame_pointer(regs), processor_mode(regs), KERN_ERR);
}
}
#endif
@@ -799,10 +807,59 @@
}
#endif
+#ifndef CONFIG_CPU_V7M
+static void copy_from_lma(void *vma, void *lma_start, void *lma_end)
+{
+ memcpy(vma, lma_start, lma_end - lma_start);
+}
+
+static void flush_vectors(void *vma, size_t offset, size_t size)
+{
+ unsigned long start = (unsigned long)vma + offset;
+ unsigned long end = start + size;
+
+ flush_icache_range(start, end);
+}
+
+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
+int spectre_bhb_update_vectors(unsigned int method)
+{
+ extern char __vectors_bhb_bpiall_start[], __vectors_bhb_bpiall_end[];
+ extern char __vectors_bhb_loop8_start[], __vectors_bhb_loop8_end[];
+ void *vec_start, *vec_end;
+
+ if (system_state > SYSTEM_SCHEDULING) {
+ pr_err("CPU%u: Spectre BHB workaround too late - system vulnerable\n",
+ smp_processor_id());
+ return SPECTRE_VULNERABLE;
+ }
+
+ switch (method) {
+ case SPECTRE_V2_METHOD_LOOP8:
+ vec_start = __vectors_bhb_loop8_start;
+ vec_end = __vectors_bhb_loop8_end;
+ break;
+
+ case SPECTRE_V2_METHOD_BPIALL:
+ vec_start = __vectors_bhb_bpiall_start;
+ vec_end = __vectors_bhb_bpiall_end;
+ break;
+
+ default:
+ pr_err("CPU%u: unknown Spectre BHB state %d\n",
+ smp_processor_id(), method);
+ return SPECTRE_VULNERABLE;
+ }
+
+ copy_from_lma(vectors_page, vec_start, vec_end);
+ flush_vectors(vectors_page, 0, vec_end - vec_start);
+
+ return SPECTRE_MITIGATED;
+}
+#endif
+
void __init early_trap_init(void *vectors_base)
{
-#ifndef CONFIG_CPU_V7M
- unsigned long vectors = (unsigned long)vectors_base;
extern char __stubs_start[], __stubs_end[];
extern char __vectors_start[], __vectors_end[];
unsigned i;
@@ -823,17 +880,20 @@
* into the vector page, mapped at 0xffff0000, and ensure these
* are visible to the instruction stream.
*/
- memcpy((void *)vectors, __vectors_start, __vectors_end - __vectors_start);
- memcpy((void *)vectors + 0x1000, __stubs_start, __stubs_end - __stubs_start);
+ copy_from_lma(vectors_base, __vectors_start, __vectors_end);
+ copy_from_lma(vectors_base + 0x1000, __stubs_start, __stubs_end);
kuser_init(vectors_base);
- flush_icache_range(vectors, vectors + PAGE_SIZE * 2);
+ flush_vectors(vectors_base, 0, PAGE_SIZE * 2);
+}
#else /* ifndef CONFIG_CPU_V7M */
+void __init early_trap_init(void *vectors_base)
+{
/*
* on V7-M there is no need to copy the vector table to a dedicated
* memory area. The address is configurable and so a table in the kernel
* image can be used.
*/
-#endif
}
+#endif
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index 4574e6a..d2bd0df 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -444,7 +444,7 @@
ctrl.vrs[PC] = ctrl.vrs[LR];
/* check for infinite loop */
- if (frame->pc == ctrl.vrs[PC])
+ if (frame->pc == ctrl.vrs[PC] && frame->sp == ctrl.vrs[SP])
return -URC_FAILURE;
frame->fp = ctrl.vrs[FP];
@@ -455,7 +455,8 @@
return URC_OK;
}
-void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk)
+void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk,
+ const char *loglvl)
{
struct stackframe frame;
@@ -493,7 +494,7 @@
urc = unwind_frame(&frame);
if (urc < 0)
break;
- dump_backtrace_entry(where, frame.pc, frame.sp - 4);
+ dump_backtrace_entry(where, frame.pc, frame.sp - 4, loglvl);
}
}
diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c
index 6c69a55..fddd08a 100644
--- a/arch/arm/kernel/vdso.c
+++ b/arch/arm/kernel/vdso.c
@@ -23,6 +23,8 @@
#include <asm/vdso.h>
#include <asm/vdso_datapage.h>
#include <clocksource/arm_arch_timer.h>
+#include <vdso/helpers.h>
+#include <vdso/vsyscall.h>
#define MAX_SYMNAME 64
@@ -37,7 +39,7 @@
* The VDSO data page.
*/
static union vdso_data_store vdso_data_store __page_aligned_data;
-static struct vdso_data *vdso_data = &vdso_data_store.data;
+struct vdso_data *vdso_data = vdso_data_store.data;
static struct page *vdso_data_page __ro_after_init;
static const struct vm_special_mapping vdso_data_mapping = {
@@ -77,7 +79,7 @@
/* Cached result of boot-time check for whether the arch timer exists,
* and if so, whether the virtual counter is useable.
*/
-static bool cntvct_ok __ro_after_init;
+bool cntvct_ok __ro_after_init;
static bool __init cntvct_functional(void)
{
@@ -182,6 +184,7 @@
if (!cntvct_ok) {
vdso_nullpatch_one(&einfo, "__vdso_gettimeofday");
vdso_nullpatch_one(&einfo, "__vdso_clock_gettime");
+ vdso_nullpatch_one(&einfo, "__vdso_clock_gettime64");
}
}
@@ -238,7 +241,7 @@
return PTR_ERR_OR_ZERO(vma);
}
-/* assumes mmap_sem is write-locked */
+/* assumes mmap_lock is write-locked */
void arm_install_vdso(struct mm_struct *mm, unsigned long addr)
{
struct vm_area_struct *vma;
@@ -264,84 +267,3 @@
mm->context.vdso = addr;
}
-static void vdso_write_begin(struct vdso_data *vdata)
-{
- ++vdso_data->seq_count;
- smp_wmb(); /* Pairs with smp_rmb in vdso_read_retry */
-}
-
-static void vdso_write_end(struct vdso_data *vdata)
-{
- smp_wmb(); /* Pairs with smp_rmb in vdso_read_begin */
- ++vdso_data->seq_count;
-}
-
-static bool tk_is_cntvct(const struct timekeeper *tk)
-{
- if (!IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
- return false;
-
- if (tk->tkr_mono.clock->archdata.clock_mode != VDSO_CLOCKMODE_ARCHTIMER)
- return false;
-
- return true;
-}
-
-/**
- * update_vsyscall - update the vdso data page
- *
- * Increment the sequence counter, making it odd, indicating to
- * userspace that an update is in progress. Update the fields used
- * for coarse clocks and, if the architected system timer is in use,
- * the fields used for high precision clocks. Increment the sequence
- * counter again, making it even, indicating to userspace that the
- * update is finished.
- *
- * Userspace is expected to sample seq_count before reading any other
- * fields from the data page. If seq_count is odd, userspace is
- * expected to wait until it becomes even. After copying data from
- * the page, userspace must sample seq_count again; if it has changed
- * from its previous value, userspace must retry the whole sequence.
- *
- * Calls to update_vsyscall are serialized by the timekeeping core.
- */
-void update_vsyscall(struct timekeeper *tk)
-{
- struct timespec64 *wtm = &tk->wall_to_monotonic;
-
- if (!cntvct_ok) {
- /* The entry points have been zeroed, so there is no
- * point in updating the data page.
- */
- return;
- }
-
- vdso_write_begin(vdso_data);
-
- vdso_data->tk_is_cntvct = tk_is_cntvct(tk);
- vdso_data->xtime_coarse_sec = tk->xtime_sec;
- vdso_data->xtime_coarse_nsec = (u32)(tk->tkr_mono.xtime_nsec >>
- tk->tkr_mono.shift);
- vdso_data->wtm_clock_sec = wtm->tv_sec;
- vdso_data->wtm_clock_nsec = wtm->tv_nsec;
-
- if (vdso_data->tk_is_cntvct) {
- vdso_data->cs_cycle_last = tk->tkr_mono.cycle_last;
- vdso_data->xtime_clock_sec = tk->xtime_sec;
- vdso_data->xtime_clock_snsec = tk->tkr_mono.xtime_nsec;
- vdso_data->cs_mult = tk->tkr_mono.mult;
- vdso_data->cs_shift = tk->tkr_mono.shift;
- vdso_data->cs_mask = tk->tkr_mono.mask;
- }
-
- vdso_write_end(vdso_data);
-
- flush_dcache_page(virt_to_page(vdso_data));
-}
-
-void update_vsyscall_tz(void)
-{
- vdso_data->tz_minuteswest = sys_tz.tz_minuteswest;
- vdso_data->tz_dsttime = sys_tz.tz_dsttime;
- flush_dcache_page(virt_to_page(vdso_data));
-}
diff --git a/arch/arm/kernel/vmlinux-xip.lds.S b/arch/arm/kernel/vmlinux-xip.lds.S
index 8c74037..f14c236 100644
--- a/arch/arm/kernel/vmlinux-xip.lds.S
+++ b/arch/arm/kernel/vmlinux-xip.lds.S
@@ -9,15 +9,13 @@
#include <linux/sizes.h>
-#include <asm-generic/vmlinux.lds.h>
+#include <asm/vmlinux.lds.h>
#include <asm/cache.h>
#include <asm/thread_info.h>
#include <asm/memory.h>
#include <asm/mpu.h>
#include <asm/page.h>
-#include "vmlinux.lds.h"
-
OUTPUT_ARCH(arm)
ENTRY(stext)
@@ -42,6 +40,10 @@
ARM_DISCARD
*(.alt.smp.init)
*(.pv_table)
+#ifndef CONFIG_ARM_UNWIND
+ *(.ARM.exidx) *(.ARM.exidx.*)
+ *(.ARM.extab) *(.ARM.extab.*)
+#endif
}
. = XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR);
@@ -70,8 +72,6 @@
ARM_UNWIND_SECTIONS
#endif
- NOTES
-
_etext = .; /* End of text and rodata section */
ARM_VECTORS
@@ -114,7 +114,7 @@
. = ALIGN(THREAD_SIZE);
_sdata = .;
- RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
+ RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
.data.ro_after_init : AT(ADDR(.data.ro_after_init) - LOAD_OFFSET) {
*(.data..ro_after_init)
}
@@ -154,6 +154,10 @@
_end = .;
STABS_DEBUG
+ DWARF_DEBUG
+ ARM_DETAILS
+
+ ARM_ASSERTS
}
/*
@@ -164,14 +168,6 @@
ASSERT((__proc_info_end - __proc_info_begin), "missing CPU support")
ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined")
-/*
- * The HYP init code can't be more than a page long,
- * and should not cross a page boundary.
- * The above comment applies as well.
- */
-ASSERT(__hyp_idmap_text_end - (__hyp_idmap_text_start & PAGE_MASK) <= PAGE_SIZE,
- "HYP init code too big or misaligned")
-
#ifdef CONFIG_XIP_DEFLATED_DATA
/*
* The .bss is used as a stack area for __inflate_kernel_data() whose stack
@@ -180,7 +176,7 @@
ASSERT((_end - __bss_start) >= 12288, ".bss too small for CONFIG_XIP_DEFLATED_DATA")
#endif
-#ifdef CONFIG_ARM_MPU
+#if defined(CONFIG_ARM_MPU) && !defined(CONFIG_COMPILE_TEST)
/*
* Due to PMSAv7 restriction on base address and size we have to
* enforce minimal alignment restrictions. It was seen that weaker
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 23150c0..f7f4620 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -8,15 +8,13 @@
#include "vmlinux-xip.lds.S"
#else
-#include <asm-generic/vmlinux.lds.h>
+#include <linux/pgtable.h>
+#include <asm/vmlinux.lds.h>
#include <asm/cache.h>
#include <asm/thread_info.h>
#include <asm/memory.h>
#include <asm/mpu.h>
#include <asm/page.h>
-#include <asm/pgtable.h>
-
-#include "vmlinux.lds.h"
OUTPUT_ARCH(arm)
ENTRY(stext)
@@ -43,6 +41,10 @@
#ifndef CONFIG_SMP_ON_UP
*(.alt.smp.init)
#endif
+#ifndef CONFIG_ARM_UNWIND
+ *(.ARM.exidx) *(.ARM.exidx.*)
+ *(.ARM.extab) *(.ARM.extab.*)
+#endif
}
. = PAGE_OFFSET + TEXT_OFFSET;
@@ -81,8 +83,6 @@
ARM_UNWIND_SECTIONS
#endif
- NOTES
-
#ifdef CONFIG_STRICT_KERNEL_RWX
. = ALIGN(1<<SECTION_SHIFT);
#else
@@ -143,7 +143,7 @@
__init_end = .;
_sdata = .;
- RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
+ RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
_edata = .;
BSS_SECTION(0, 0, 0)
@@ -153,6 +153,10 @@
_end = .;
STABS_DEBUG
+ DWARF_DEBUG
+ ARM_DETAILS
+
+ ARM_ASSERTS
}
#ifdef CONFIG_STRICT_KERNEL_RWX
@@ -172,12 +176,4 @@
ASSERT((__proc_info_end - __proc_info_begin), "missing CPU support")
ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined")
-/*
- * The HYP init code can't be more than a page long,
- * and should not cross a page boundary.
- * The above comment applies as well.
- */
-ASSERT(__hyp_idmap_text_end - (__hyp_idmap_text_start & PAGE_MASK) <= PAGE_SIZE,
- "HYP init code too big or misaligned")
-
#endif /* CONFIG_XIP_KERNEL */
diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig
deleted file mode 100644
index f591026..0000000
--- a/arch/arm/kvm/Kconfig
+++ /dev/null
@@ -1,59 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# KVM configuration
-#
-
-source "virt/kvm/Kconfig"
-source "virt/lib/Kconfig"
-
-menuconfig VIRTUALIZATION
- bool "Virtualization"
- ---help---
- Say Y here to get to see options for using your Linux host to run
- other operating systems inside virtual machines (guests).
- This option alone does not add any kernel code.
-
- If you say N, all options in this submenu will be skipped and
- disabled.
-
-if VIRTUALIZATION
-
-config KVM
- bool "Kernel-based Virtual Machine (KVM) support"
- depends on MMU && OF
- select PREEMPT_NOTIFIERS
- select ARM_GIC
- select ARM_GIC_V3
- select ARM_GIC_V3_ITS
- select HAVE_KVM_CPU_RELAX_INTERCEPT
- select HAVE_KVM_ARCH_TLB_FLUSH_ALL
- select KVM_MMIO
- select KVM_ARM_HOST
- select KVM_GENERIC_DIRTYLOG_READ_PROTECT
- select SRCU
- select MMU_NOTIFIER
- select KVM_VFIO
- select HAVE_KVM_EVENTFD
- select HAVE_KVM_IRQFD
- select HAVE_KVM_IRQCHIP
- select HAVE_KVM_IRQ_ROUTING
- select HAVE_KVM_MSI
- select IRQ_BYPASS_MANAGER
- select HAVE_KVM_IRQ_BYPASS
- depends on ARM_VIRT_EXT && ARM_LPAE && ARM_ARCH_TIMER
- ---help---
- Support hosting virtualized guest machines.
-
- This module provides access to the hardware capabilities through
- a character device node named /dev/kvm.
-
- If unsure, say N.
-
-config KVM_ARM_HOST
- bool
- ---help---
- Provides host support for ARM processors.
-
-source "drivers/vhost/Kconfig"
-
-endif # VIRTUALIZATION
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
deleted file mode 100644
index b76b75b..0000000
--- a/arch/arm/kvm/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for Kernel-based Virtual Machine module
-#
-
-plus_virt := $(call as-instr,.arch_extension virt,+virt)
-ifeq ($(plus_virt),+virt)
- plus_virt_def := -DREQUIRES_VIRT=1
-endif
-
-KVM := ../../../virt/kvm
-
-ccflags-y += -I $(srctree)/$(src) -I $(srctree)/virt/kvm/arm/vgic
-CFLAGS_$(KVM)/arm/arm.o := $(plus_virt_def)
-
-AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
-AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
-
-kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o $(KVM)/vfio.o
-
-obj-$(CONFIG_KVM_ARM_HOST) += hyp/
-
-obj-y += kvm-arm.o init.o interrupts.o
-obj-y += handle_exit.o guest.o emulate.o reset.o
-obj-y += coproc.o coproc_a15.o coproc_a7.o vgic-v3-coproc.o
-obj-y += $(KVM)/arm/arm.o $(KVM)/arm/mmu.o $(KVM)/arm/mmio.o
-obj-y += $(KVM)/arm/psci.o $(KVM)/arm/perf.o
-obj-y += $(KVM)/arm/aarch32.o
-
-obj-y += $(KVM)/arm/vgic/vgic.o
-obj-y += $(KVM)/arm/vgic/vgic-init.o
-obj-y += $(KVM)/arm/vgic/vgic-irqfd.o
-obj-y += $(KVM)/arm/vgic/vgic-v2.o
-obj-y += $(KVM)/arm/vgic/vgic-v3.o
-obj-y += $(KVM)/arm/vgic/vgic-v4.o
-obj-y += $(KVM)/arm/vgic/vgic-mmio.o
-obj-y += $(KVM)/arm/vgic/vgic-mmio-v2.o
-obj-y += $(KVM)/arm/vgic/vgic-mmio-v3.o
-obj-y += $(KVM)/arm/vgic/vgic-kvm-device.o
-obj-y += $(KVM)/arm/vgic/vgic-its.o
-obj-y += $(KVM)/arm/vgic/vgic-debug.o
-obj-y += $(KVM)/irqchip.o
-obj-y += $(KVM)/arm/arch_timer.o
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
deleted file mode 100644
index 07745ee..0000000
--- a/arch/arm/kvm/coproc.c
+++ /dev/null
@@ -1,1455 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Authors: Rusty Russell <rusty@rustcorp.com.au>
- * Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#include <linux/bsearch.h>
-#include <linux/mm.h>
-#include <linux/kvm_host.h>
-#include <linux/uaccess.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_host.h>
-#include <asm/kvm_emulate.h>
-#include <asm/kvm_coproc.h>
-#include <asm/kvm_mmu.h>
-#include <asm/cacheflush.h>
-#include <asm/cputype.h>
-#include <trace/events/kvm.h>
-#include <asm/vfp.h>
-#include "../vfp/vfpinstr.h"
-
-#define CREATE_TRACE_POINTS
-#include "trace.h"
-#include "coproc.h"
-
-
-/******************************************************************************
- * Co-processor emulation
- *****************************************************************************/
-
-static bool write_to_read_only(struct kvm_vcpu *vcpu,
- const struct coproc_params *params)
-{
- WARN_ONCE(1, "CP15 write to read-only register\n");
- print_cp_instr(params);
- kvm_inject_undefined(vcpu);
- return false;
-}
-
-static bool read_from_write_only(struct kvm_vcpu *vcpu,
- const struct coproc_params *params)
-{
- WARN_ONCE(1, "CP15 read to write-only register\n");
- print_cp_instr(params);
- kvm_inject_undefined(vcpu);
- return false;
-}
-
-/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
-static u32 cache_levels;
-
-/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
-#define CSSELR_MAX 12
-
-/*
- * kvm_vcpu_arch.cp15 holds cp15 registers as an array of u32, but some
- * of cp15 registers can be viewed either as couple of two u32 registers
- * or one u64 register. Current u64 register encoding is that least
- * significant u32 word is followed by most significant u32 word.
- */
-static inline void vcpu_cp15_reg64_set(struct kvm_vcpu *vcpu,
- const struct coproc_reg *r,
- u64 val)
-{
- vcpu_cp15(vcpu, r->reg) = val & 0xffffffff;
- vcpu_cp15(vcpu, r->reg + 1) = val >> 32;
-}
-
-static inline u64 vcpu_cp15_reg64_get(struct kvm_vcpu *vcpu,
- const struct coproc_reg *r)
-{
- u64 val;
-
- val = vcpu_cp15(vcpu, r->reg + 1);
- val = val << 32;
- val = val | vcpu_cp15(vcpu, r->reg);
- return val;
-}
-
-int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- kvm_inject_undefined(vcpu);
- return 1;
-}
-
-int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- /*
- * We can get here, if the host has been built without VFPv3 support,
- * but the guest attempted a floating point operation.
- */
- kvm_inject_undefined(vcpu);
- return 1;
-}
-
-int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- kvm_inject_undefined(vcpu);
- return 1;
-}
-
-static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
-{
- /*
- * Compute guest MPIDR. We build a virtual cluster out of the
- * vcpu_id, but we read the 'U' bit from the underlying
- * hardware directly.
- */
- vcpu_cp15(vcpu, c0_MPIDR) = ((read_cpuid_mpidr() & MPIDR_SMP_BITMASK) |
- ((vcpu->vcpu_id >> 2) << MPIDR_LEVEL_BITS) |
- (vcpu->vcpu_id & 3));
-}
-
-/* TRM entries A7:4.3.31 A15:4.3.28 - RO WI */
-static bool access_actlr(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- if (p->is_write)
- return ignore_write(vcpu, p);
-
- *vcpu_reg(vcpu, p->Rt1) = vcpu_cp15(vcpu, c1_ACTLR);
- return true;
-}
-
-/* TRM entries A7:4.3.56, A15:4.3.60 - R/O. */
-static bool access_cbar(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- if (p->is_write)
- return write_to_read_only(vcpu, p);
- return read_zero(vcpu, p);
-}
-
-/* TRM entries A7:4.3.49, A15:4.3.48 - R/O WI */
-static bool access_l2ctlr(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- if (p->is_write)
- return ignore_write(vcpu, p);
-
- *vcpu_reg(vcpu, p->Rt1) = vcpu_cp15(vcpu, c9_L2CTLR);
- return true;
-}
-
-static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
-{
- u32 l2ctlr, ncores;
-
- asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
- l2ctlr &= ~(3 << 24);
- ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
- /* How many cores in the current cluster and the next ones */
- ncores -= (vcpu->vcpu_id & ~3);
- /* Cap it to the maximum number of cores in a single cluster */
- ncores = min(ncores, 3U);
- l2ctlr |= (ncores & 3) << 24;
-
- vcpu_cp15(vcpu, c9_L2CTLR) = l2ctlr;
-}
-
-static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
-{
- u32 actlr;
-
- /* ACTLR contains SMP bit: make sure you create all cpus first! */
- asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
- /* Make the SMP bit consistent with the guest configuration */
- if (atomic_read(&vcpu->kvm->online_vcpus) > 1)
- actlr |= 1U << 6;
- else
- actlr &= ~(1U << 6);
-
- vcpu_cp15(vcpu, c1_ACTLR) = actlr;
-}
-
-/*
- * TRM entries: A7:4.3.50, A15:4.3.49
- * R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored).
- */
-static bool access_l2ectlr(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- if (p->is_write)
- return ignore_write(vcpu, p);
-
- *vcpu_reg(vcpu, p->Rt1) = 0;
- return true;
-}
-
-/*
- * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
- */
-static bool access_dcsw(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- if (!p->is_write)
- return read_from_write_only(vcpu, p);
-
- kvm_set_way_flush(vcpu);
- return true;
-}
-
-/*
- * Generic accessor for VM registers. Only called as long as HCR_TVM
- * is set. If the guest enables the MMU, we stop trapping the VM
- * sys_regs and leave it in complete control of the caches.
- *
- * Used by the cpu-specific code.
- */
-bool access_vm_reg(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- bool was_enabled = vcpu_has_cache_enabled(vcpu);
-
- BUG_ON(!p->is_write);
-
- vcpu_cp15(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt1);
- if (p->is_64bit)
- vcpu_cp15(vcpu, r->reg + 1) = *vcpu_reg(vcpu, p->Rt2);
-
- kvm_toggle_cache(vcpu, was_enabled);
- return true;
-}
-
-static bool access_gic_sgi(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- u64 reg;
- bool g1;
-
- if (!p->is_write)
- return read_from_write_only(vcpu, p);
-
- reg = (u64)*vcpu_reg(vcpu, p->Rt2) << 32;
- reg |= *vcpu_reg(vcpu, p->Rt1) ;
-
- /*
- * In a system where GICD_CTLR.DS=1, a ICC_SGI0R access generates
- * Group0 SGIs only, while ICC_SGI1R can generate either group,
- * depending on the SGI configuration. ICC_ASGI1R is effectively
- * equivalent to ICC_SGI0R, as there is no "alternative" secure
- * group.
- */
- switch (p->Op1) {
- default: /* Keep GCC quiet */
- case 0: /* ICC_SGI1R */
- g1 = true;
- break;
- case 1: /* ICC_ASGI1R */
- case 2: /* ICC_SGI0R */
- g1 = false;
- break;
- }
-
- vgic_v3_dispatch_sgi(vcpu, reg, g1);
-
- return true;
-}
-
-static bool access_gic_sre(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- if (p->is_write)
- return ignore_write(vcpu, p);
-
- *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
-
- return true;
-}
-
-static bool access_cntp_tval(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- u32 val;
-
- if (p->is_write) {
- val = *vcpu_reg(vcpu, p->Rt1);
- kvm_arm_timer_write_sysreg(vcpu,
- TIMER_PTIMER, TIMER_REG_TVAL, val);
- } else {
- val = kvm_arm_timer_read_sysreg(vcpu,
- TIMER_PTIMER, TIMER_REG_TVAL);
- *vcpu_reg(vcpu, p->Rt1) = val;
- }
-
- return true;
-}
-
-static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- u32 val;
-
- if (p->is_write) {
- val = *vcpu_reg(vcpu, p->Rt1);
- kvm_arm_timer_write_sysreg(vcpu,
- TIMER_PTIMER, TIMER_REG_CTL, val);
- } else {
- val = kvm_arm_timer_read_sysreg(vcpu,
- TIMER_PTIMER, TIMER_REG_CTL);
- *vcpu_reg(vcpu, p->Rt1) = val;
- }
-
- return true;
-}
-
-static bool access_cntp_cval(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- u64 val;
-
- if (p->is_write) {
- val = (u64)*vcpu_reg(vcpu, p->Rt2) << 32;
- val |= *vcpu_reg(vcpu, p->Rt1);
- kvm_arm_timer_write_sysreg(vcpu,
- TIMER_PTIMER, TIMER_REG_CVAL, val);
- } else {
- val = kvm_arm_timer_read_sysreg(vcpu,
- TIMER_PTIMER, TIMER_REG_CVAL);
- *vcpu_reg(vcpu, p->Rt1) = val;
- *vcpu_reg(vcpu, p->Rt2) = val >> 32;
- }
-
- return true;
-}
-
-/*
- * We could trap ID_DFR0 and tell the guest we don't support performance
- * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
- * NAKed, so it will read the PMCR anyway.
- *
- * Therefore we tell the guest we have 0 counters. Unfortunately, we
- * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
- * all PM registers, which doesn't crash the guest kernel at least.
- */
-static bool trap_raz_wi(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r)
-{
- if (p->is_write)
- return ignore_write(vcpu, p);
- else
- return read_zero(vcpu, p);
-}
-
-#define access_pmcr trap_raz_wi
-#define access_pmcntenset trap_raz_wi
-#define access_pmcntenclr trap_raz_wi
-#define access_pmovsr trap_raz_wi
-#define access_pmselr trap_raz_wi
-#define access_pmceid0 trap_raz_wi
-#define access_pmceid1 trap_raz_wi
-#define access_pmccntr trap_raz_wi
-#define access_pmxevtyper trap_raz_wi
-#define access_pmxevcntr trap_raz_wi
-#define access_pmuserenr trap_raz_wi
-#define access_pmintenset trap_raz_wi
-#define access_pmintenclr trap_raz_wi
-
-/* Architected CP15 registers.
- * CRn denotes the primary register number, but is copied to the CRm in the
- * user space API for 64-bit register access in line with the terminology used
- * in the ARM ARM.
- * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
- * registers preceding 32-bit ones.
- */
-static const struct coproc_reg cp15_regs[] = {
- /* MPIDR: we use VMPIDR for guest access. */
- { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
- NULL, reset_mpidr, c0_MPIDR },
-
- /* CSSELR: swapped by interrupt.S. */
- { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
- NULL, reset_unknown, c0_CSSELR },
-
- /* ACTLR: trapped by HCR.TAC bit. */
- { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
- access_actlr, reset_actlr, c1_ACTLR },
-
- /* CPACR: swapped by interrupt.S. */
- { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
- NULL, reset_val, c1_CPACR, 0x00000000 },
-
- /* TTBR0/TTBR1/TTBCR: swapped by interrupt.S. */
- { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 },
- { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
- access_vm_reg, reset_unknown, c2_TTBR0 },
- { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
- access_vm_reg, reset_unknown, c2_TTBR1 },
- { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
- access_vm_reg, reset_val, c2_TTBCR, 0x00000000 },
- { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 },
-
-
- /* DACR: swapped by interrupt.S. */
- { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
- access_vm_reg, reset_unknown, c3_DACR },
-
- /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
- { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
- access_vm_reg, reset_unknown, c5_DFSR },
- { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
- access_vm_reg, reset_unknown, c5_IFSR },
- { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
- access_vm_reg, reset_unknown, c5_ADFSR },
- { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
- access_vm_reg, reset_unknown, c5_AIFSR },
-
- /* DFAR/IFAR: swapped by interrupt.S. */
- { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
- access_vm_reg, reset_unknown, c6_DFAR },
- { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
- access_vm_reg, reset_unknown, c6_IFAR },
-
- /* PAR swapped by interrupt.S */
- { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
-
- /*
- * DC{C,I,CI}SW operations:
- */
- { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
- { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
- { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
- /*
- * L2CTLR access (guest wants to know #CPUs).
- */
- { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32,
- access_l2ctlr, reset_l2ctlr, c9_L2CTLR },
- { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr},
-
- /*
- * Dummy performance monitor implementation.
- */
- { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
- { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
- { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
- { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
- { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
- { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
- { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
- { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
- { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
- { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
- { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
- { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
- { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
-
- /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
- { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
- access_vm_reg, reset_unknown, c10_PRRR},
- { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
- access_vm_reg, reset_unknown, c10_NMRR},
-
- /* AMAIR0/AMAIR1: swapped by interrupt.S. */
- { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32,
- access_vm_reg, reset_unknown, c10_AMAIR0},
- { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32,
- access_vm_reg, reset_unknown, c10_AMAIR1},
-
- /* ICC_SGI1R */
- { CRm64(12), Op1( 0), is64, access_gic_sgi},
-
- /* VBAR: swapped by interrupt.S. */
- { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
- NULL, reset_val, c12_VBAR, 0x00000000 },
-
- /* ICC_ASGI1R */
- { CRm64(12), Op1( 1), is64, access_gic_sgi},
- /* ICC_SGI0R */
- { CRm64(12), Op1( 2), is64, access_gic_sgi},
- /* ICC_SRE */
- { CRn(12), CRm(12), Op1( 0), Op2(5), is32, access_gic_sre },
-
- /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
- { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
- access_vm_reg, reset_val, c13_CID, 0x00000000 },
- { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
- NULL, reset_unknown, c13_TID_URW },
- { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
- NULL, reset_unknown, c13_TID_URO },
- { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
- NULL, reset_unknown, c13_TID_PRIV },
-
- /* CNTP */
- { CRm64(14), Op1( 2), is64, access_cntp_cval},
-
- /* CNTKCTL: swapped by interrupt.S. */
- { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
- NULL, reset_val, c14_CNTKCTL, 0x00000000 },
-
- /* CNTP */
- { CRn(14), CRm( 2), Op1( 0), Op2( 0), is32, access_cntp_tval },
- { CRn(14), CRm( 2), Op1( 0), Op2( 1), is32, access_cntp_ctl },
-
- /* The Configuration Base Address Register. */
- { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
-};
-
-static int check_reg_table(const struct coproc_reg *table, unsigned int n)
-{
- unsigned int i;
-
- for (i = 1; i < n; i++) {
- if (cmp_reg(&table[i-1], &table[i]) >= 0) {
- kvm_err("reg table %p out of order (%d)\n", table, i - 1);
- return 1;
- }
- }
-
- return 0;
-}
-
-/* Target specific emulation tables */
-static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
-
-void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
-{
- BUG_ON(check_reg_table(table->table, table->num));
- target_tables[table->target] = table;
-}
-
-/* Get specific register table for this target. */
-static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
-{
- struct kvm_coproc_target_table *table;
-
- table = target_tables[target];
- *num = table->num;
- return table->table;
-}
-
-#define reg_to_match_value(x) \
- ({ \
- unsigned long val; \
- val = (x)->CRn << 11; \
- val |= (x)->CRm << 7; \
- val |= (x)->Op1 << 4; \
- val |= (x)->Op2 << 1; \
- val |= !(x)->is_64bit; \
- val; \
- })
-
-static int match_reg(const void *key, const void *elt)
-{
- const unsigned long pval = (unsigned long)key;
- const struct coproc_reg *r = elt;
-
- return pval - reg_to_match_value(r);
-}
-
-static const struct coproc_reg *find_reg(const struct coproc_params *params,
- const struct coproc_reg table[],
- unsigned int num)
-{
- unsigned long pval = reg_to_match_value(params);
-
- return bsearch((void *)pval, table, num, sizeof(table[0]), match_reg);
-}
-
-static int emulate_cp15(struct kvm_vcpu *vcpu,
- const struct coproc_params *params)
-{
- size_t num;
- const struct coproc_reg *table, *r;
-
- trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
- params->CRm, params->Op2, params->is_write);
-
- table = get_target_table(vcpu->arch.target, &num);
-
- /* Search target-specific then generic table. */
- r = find_reg(params, table, num);
- if (!r)
- r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
-
- if (likely(r)) {
- /* If we don't have an accessor, we should never get here! */
- BUG_ON(!r->access);
-
- if (likely(r->access(vcpu, params, r))) {
- /* Skip instruction, since it was emulated */
- kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
- }
- } else {
- /* If access function fails, it should complain. */
- kvm_err("Unsupported guest CP15 access at: %08lx [%08lx]\n",
- *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
- print_cp_instr(params);
- kvm_inject_undefined(vcpu);
- }
-
- return 1;
-}
-
-static struct coproc_params decode_64bit_hsr(struct kvm_vcpu *vcpu)
-{
- struct coproc_params params;
-
- params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
- params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
- params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
- params.is_64bit = true;
-
- params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
- params.Op2 = 0;
- params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
- params.CRm = 0;
-
- return params;
-}
-
-/**
- * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
- * @vcpu: The VCPU pointer
- * @run: The kvm_run struct
- */
-int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- struct coproc_params params = decode_64bit_hsr(vcpu);
-
- return emulate_cp15(vcpu, ¶ms);
-}
-
-/**
- * kvm_handle_cp14_64 -- handles a mrrc/mcrr trap on a guest CP14 access
- * @vcpu: The VCPU pointer
- * @run: The kvm_run struct
- */
-int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- struct coproc_params params = decode_64bit_hsr(vcpu);
-
- /* raz_wi cp14 */
- trap_raz_wi(vcpu, ¶ms, NULL);
-
- /* handled */
- kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
- return 1;
-}
-
-static void reset_coproc_regs(struct kvm_vcpu *vcpu,
- const struct coproc_reg *table, size_t num,
- unsigned long *bmap)
-{
- unsigned long i;
-
- for (i = 0; i < num; i++)
- if (table[i].reset) {
- int reg = table[i].reg;
-
- table[i].reset(vcpu, &table[i]);
- if (reg > 0 && reg < NR_CP15_REGS) {
- set_bit(reg, bmap);
- if (table[i].is_64bit)
- set_bit(reg + 1, bmap);
- }
- }
-}
-
-static struct coproc_params decode_32bit_hsr(struct kvm_vcpu *vcpu)
-{
- struct coproc_params params;
-
- params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
- params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
- params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
- params.is_64bit = false;
-
- params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
- params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
- params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
- params.Rt2 = 0;
-
- return params;
-}
-
-/**
- * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
- * @vcpu: The VCPU pointer
- * @run: The kvm_run struct
- */
-int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- struct coproc_params params = decode_32bit_hsr(vcpu);
- return emulate_cp15(vcpu, ¶ms);
-}
-
-/**
- * kvm_handle_cp14_32 -- handles a mrc/mcr trap on a guest CP14 access
- * @vcpu: The VCPU pointer
- * @run: The kvm_run struct
- */
-int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- struct coproc_params params = decode_32bit_hsr(vcpu);
-
- /* raz_wi cp14 */
- trap_raz_wi(vcpu, ¶ms, NULL);
-
- /* handled */
- kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
- return 1;
-}
-
-/******************************************************************************
- * Userspace API
- *****************************************************************************/
-
-static bool index_to_params(u64 id, struct coproc_params *params)
-{
- switch (id & KVM_REG_SIZE_MASK) {
- case KVM_REG_SIZE_U32:
- /* Any unused index bits means it's not valid. */
- if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
- | KVM_REG_ARM_COPROC_MASK
- | KVM_REG_ARM_32_CRN_MASK
- | KVM_REG_ARM_CRM_MASK
- | KVM_REG_ARM_OPC1_MASK
- | KVM_REG_ARM_32_OPC2_MASK))
- return false;
-
- params->is_64bit = false;
- params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
- >> KVM_REG_ARM_32_CRN_SHIFT);
- params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
- >> KVM_REG_ARM_CRM_SHIFT);
- params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
- >> KVM_REG_ARM_OPC1_SHIFT);
- params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
- >> KVM_REG_ARM_32_OPC2_SHIFT);
- return true;
- case KVM_REG_SIZE_U64:
- /* Any unused index bits means it's not valid. */
- if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
- | KVM_REG_ARM_COPROC_MASK
- | KVM_REG_ARM_CRM_MASK
- | KVM_REG_ARM_OPC1_MASK))
- return false;
- params->is_64bit = true;
- /* CRm to CRn: see cp15_to_index for details */
- params->CRn = ((id & KVM_REG_ARM_CRM_MASK)
- >> KVM_REG_ARM_CRM_SHIFT);
- params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
- >> KVM_REG_ARM_OPC1_SHIFT);
- params->Op2 = 0;
- params->CRm = 0;
- return true;
- default:
- return false;
- }
-}
-
-/* Decode an index value, and find the cp15 coproc_reg entry. */
-static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
- u64 id)
-{
- size_t num;
- const struct coproc_reg *table, *r;
- struct coproc_params params;
-
- /* We only do cp15 for now. */
- if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
- return NULL;
-
- if (!index_to_params(id, ¶ms))
- return NULL;
-
- table = get_target_table(vcpu->arch.target, &num);
- r = find_reg(¶ms, table, num);
- if (!r)
- r = find_reg(¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
-
- /* Not saved in the cp15 array? */
- if (r && !r->reg)
- r = NULL;
-
- return r;
-}
-
-/*
- * These are the invariant cp15 registers: we let the guest see the host
- * versions of these, so they're part of the guest state.
- *
- * A future CPU may provide a mechanism to present different values to
- * the guest, or a future kvm may trap them.
- */
-/* Unfortunately, there's no register-argument for mrc, so generate. */
-#define FUNCTION_FOR32(crn, crm, op1, op2, name) \
- static void get_##name(struct kvm_vcpu *v, \
- const struct coproc_reg *r) \
- { \
- u32 val; \
- \
- asm volatile("mrc p15, " __stringify(op1) \
- ", %0, c" __stringify(crn) \
- ", c" __stringify(crm) \
- ", " __stringify(op2) "\n" : "=r" (val)); \
- ((struct coproc_reg *)r)->val = val; \
- }
-
-FUNCTION_FOR32(0, 0, 0, 0, MIDR)
-FUNCTION_FOR32(0, 0, 0, 1, CTR)
-FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
-FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
-FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
-FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
-FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
-FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
-FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
-FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
-FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
-FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
-FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
-FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
-FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
-FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
-FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
-FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
-FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
-FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
-FUNCTION_FOR32(0, 0, 1, 7, AIDR)
-
-/* ->val is filled in by kvm_invariant_coproc_table_init() */
-static struct coproc_reg invariant_cp15[] = {
- { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
- { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
- { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
- { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
- { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
-
- { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
- { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
-
- { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
- { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
- { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
- { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
- { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
- { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
- { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
- { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
-
- { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
- { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
- { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
- { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
- { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
- { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
-};
-
-/*
- * Reads a register value from a userspace address to a kernel
- * variable. Make sure that register size matches sizeof(*__val).
- */
-static int reg_from_user(void *val, const void __user *uaddr, u64 id)
-{
- if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
- return -EFAULT;
- return 0;
-}
-
-/*
- * Writes a register value to a userspace address from a kernel variable.
- * Make sure that register size matches sizeof(*__val).
- */
-static int reg_to_user(void __user *uaddr, const void *val, u64 id)
-{
- if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
- return -EFAULT;
- return 0;
-}
-
-static int get_invariant_cp15(u64 id, void __user *uaddr)
-{
- struct coproc_params params;
- const struct coproc_reg *r;
- int ret;
-
- if (!index_to_params(id, ¶ms))
- return -ENOENT;
-
- r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15));
- if (!r)
- return -ENOENT;
-
- ret = -ENOENT;
- if (KVM_REG_SIZE(id) == 4) {
- u32 val = r->val;
-
- ret = reg_to_user(uaddr, &val, id);
- } else if (KVM_REG_SIZE(id) == 8) {
- ret = reg_to_user(uaddr, &r->val, id);
- }
- return ret;
-}
-
-static int set_invariant_cp15(u64 id, void __user *uaddr)
-{
- struct coproc_params params;
- const struct coproc_reg *r;
- int err;
- u64 val;
-
- if (!index_to_params(id, ¶ms))
- return -ENOENT;
- r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15));
- if (!r)
- return -ENOENT;
-
- err = -ENOENT;
- if (KVM_REG_SIZE(id) == 4) {
- u32 val32;
-
- err = reg_from_user(&val32, uaddr, id);
- if (!err)
- val = val32;
- } else if (KVM_REG_SIZE(id) == 8) {
- err = reg_from_user(&val, uaddr, id);
- }
- if (err)
- return err;
-
- /* This is what we mean by invariant: you can't change it. */
- if (r->val != val)
- return -EINVAL;
-
- return 0;
-}
-
-static bool is_valid_cache(u32 val)
-{
- u32 level, ctype;
-
- if (val >= CSSELR_MAX)
- return false;
-
- /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
- level = (val >> 1);
- ctype = (cache_levels >> (level * 3)) & 7;
-
- switch (ctype) {
- case 0: /* No cache */
- return false;
- case 1: /* Instruction cache only */
- return (val & 1);
- case 2: /* Data cache only */
- case 4: /* Unified cache */
- return !(val & 1);
- case 3: /* Separate instruction and data caches */
- return true;
- default: /* Reserved: we can't know instruction or data. */
- return false;
- }
-}
-
-/* Which cache CCSIDR represents depends on CSSELR value. */
-static u32 get_ccsidr(u32 csselr)
-{
- u32 ccsidr;
-
- /* Make sure noone else changes CSSELR during this! */
- local_irq_disable();
- /* Put value into CSSELR */
- asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
- isb();
- /* Read result out of CCSIDR */
- asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
- local_irq_enable();
-
- return ccsidr;
-}
-
-static int demux_c15_get(u64 id, void __user *uaddr)
-{
- u32 val;
- u32 __user *uval = uaddr;
-
- /* Fail if we have unknown bits set. */
- if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
- | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
- return -ENOENT;
-
- switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
- case KVM_REG_ARM_DEMUX_ID_CCSIDR:
- if (KVM_REG_SIZE(id) != 4)
- return -ENOENT;
- val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
- >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
- if (!is_valid_cache(val))
- return -ENOENT;
-
- return put_user(get_ccsidr(val), uval);
- default:
- return -ENOENT;
- }
-}
-
-static int demux_c15_set(u64 id, void __user *uaddr)
-{
- u32 val, newval;
- u32 __user *uval = uaddr;
-
- /* Fail if we have unknown bits set. */
- if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
- | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
- return -ENOENT;
-
- switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
- case KVM_REG_ARM_DEMUX_ID_CCSIDR:
- if (KVM_REG_SIZE(id) != 4)
- return -ENOENT;
- val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
- >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
- if (!is_valid_cache(val))
- return -ENOENT;
-
- if (get_user(newval, uval))
- return -EFAULT;
-
- /* This is also invariant: you can't change it. */
- if (newval != get_ccsidr(val))
- return -EINVAL;
- return 0;
- default:
- return -ENOENT;
- }
-}
-
-#ifdef CONFIG_VFPv3
-static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
- KVM_REG_ARM_VFP_FPSCR,
- KVM_REG_ARM_VFP_FPINST,
- KVM_REG_ARM_VFP_FPINST2,
- KVM_REG_ARM_VFP_MVFR0,
- KVM_REG_ARM_VFP_MVFR1,
- KVM_REG_ARM_VFP_FPSID };
-
-static unsigned int num_fp_regs(void)
-{
- if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
- return 32;
- else
- return 16;
-}
-
-static unsigned int num_vfp_regs(void)
-{
- /* Normal FP regs + control regs. */
- return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
-}
-
-static int copy_vfp_regids(u64 __user *uindices)
-{
- unsigned int i;
- const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
- const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
-
- for (i = 0; i < num_fp_regs(); i++) {
- if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
- uindices))
- return -EFAULT;
- uindices++;
- }
-
- for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
- if (put_user(u32reg | vfp_sysregs[i], uindices))
- return -EFAULT;
- uindices++;
- }
-
- return num_vfp_regs();
-}
-
-static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
-{
- u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
- u32 val;
-
- /* Fail if we have unknown bits set. */
- if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
- | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
- return -ENOENT;
-
- if (vfpid < num_fp_regs()) {
- if (KVM_REG_SIZE(id) != 8)
- return -ENOENT;
- return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpregs[vfpid],
- id);
- }
-
- /* FP control registers are all 32 bit. */
- if (KVM_REG_SIZE(id) != 4)
- return -ENOENT;
-
- switch (vfpid) {
- case KVM_REG_ARM_VFP_FPEXC:
- return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpexc, id);
- case KVM_REG_ARM_VFP_FPSCR:
- return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpscr, id);
- case KVM_REG_ARM_VFP_FPINST:
- return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpinst, id);
- case KVM_REG_ARM_VFP_FPINST2:
- return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpinst2, id);
- case KVM_REG_ARM_VFP_MVFR0:
- val = fmrx(MVFR0);
- return reg_to_user(uaddr, &val, id);
- case KVM_REG_ARM_VFP_MVFR1:
- val = fmrx(MVFR1);
- return reg_to_user(uaddr, &val, id);
- case KVM_REG_ARM_VFP_FPSID:
- val = fmrx(FPSID);
- return reg_to_user(uaddr, &val, id);
- default:
- return -ENOENT;
- }
-}
-
-static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
-{
- u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
- u32 val;
-
- /* Fail if we have unknown bits set. */
- if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
- | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
- return -ENOENT;
-
- if (vfpid < num_fp_regs()) {
- if (KVM_REG_SIZE(id) != 8)
- return -ENOENT;
- return reg_from_user(&vcpu->arch.ctxt.vfp.fpregs[vfpid],
- uaddr, id);
- }
-
- /* FP control registers are all 32 bit. */
- if (KVM_REG_SIZE(id) != 4)
- return -ENOENT;
-
- switch (vfpid) {
- case KVM_REG_ARM_VFP_FPEXC:
- return reg_from_user(&vcpu->arch.ctxt.vfp.fpexc, uaddr, id);
- case KVM_REG_ARM_VFP_FPSCR:
- return reg_from_user(&vcpu->arch.ctxt.vfp.fpscr, uaddr, id);
- case KVM_REG_ARM_VFP_FPINST:
- return reg_from_user(&vcpu->arch.ctxt.vfp.fpinst, uaddr, id);
- case KVM_REG_ARM_VFP_FPINST2:
- return reg_from_user(&vcpu->arch.ctxt.vfp.fpinst2, uaddr, id);
- /* These are invariant. */
- case KVM_REG_ARM_VFP_MVFR0:
- if (reg_from_user(&val, uaddr, id))
- return -EFAULT;
- if (val != fmrx(MVFR0))
- return -EINVAL;
- return 0;
- case KVM_REG_ARM_VFP_MVFR1:
- if (reg_from_user(&val, uaddr, id))
- return -EFAULT;
- if (val != fmrx(MVFR1))
- return -EINVAL;
- return 0;
- case KVM_REG_ARM_VFP_FPSID:
- if (reg_from_user(&val, uaddr, id))
- return -EFAULT;
- if (val != fmrx(FPSID))
- return -EINVAL;
- return 0;
- default:
- return -ENOENT;
- }
-}
-#else /* !CONFIG_VFPv3 */
-static unsigned int num_vfp_regs(void)
-{
- return 0;
-}
-
-static int copy_vfp_regids(u64 __user *uindices)
-{
- return 0;
-}
-
-static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
-{
- return -ENOENT;
-}
-
-static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
-{
- return -ENOENT;
-}
-#endif /* !CONFIG_VFPv3 */
-
-int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
-{
- const struct coproc_reg *r;
- void __user *uaddr = (void __user *)(long)reg->addr;
- int ret;
-
- if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
- return demux_c15_get(reg->id, uaddr);
-
- if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
- return vfp_get_reg(vcpu, reg->id, uaddr);
-
- r = index_to_coproc_reg(vcpu, reg->id);
- if (!r)
- return get_invariant_cp15(reg->id, uaddr);
-
- ret = -ENOENT;
- if (KVM_REG_SIZE(reg->id) == 8) {
- u64 val;
-
- val = vcpu_cp15_reg64_get(vcpu, r);
- ret = reg_to_user(uaddr, &val, reg->id);
- } else if (KVM_REG_SIZE(reg->id) == 4) {
- ret = reg_to_user(uaddr, &vcpu_cp15(vcpu, r->reg), reg->id);
- }
-
- return ret;
-}
-
-int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
-{
- const struct coproc_reg *r;
- void __user *uaddr = (void __user *)(long)reg->addr;
- int ret;
-
- if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
- return demux_c15_set(reg->id, uaddr);
-
- if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
- return vfp_set_reg(vcpu, reg->id, uaddr);
-
- r = index_to_coproc_reg(vcpu, reg->id);
- if (!r)
- return set_invariant_cp15(reg->id, uaddr);
-
- ret = -ENOENT;
- if (KVM_REG_SIZE(reg->id) == 8) {
- u64 val;
-
- ret = reg_from_user(&val, uaddr, reg->id);
- if (!ret)
- vcpu_cp15_reg64_set(vcpu, r, val);
- } else if (KVM_REG_SIZE(reg->id) == 4) {
- ret = reg_from_user(&vcpu_cp15(vcpu, r->reg), uaddr, reg->id);
- }
-
- return ret;
-}
-
-static unsigned int num_demux_regs(void)
-{
- unsigned int i, count = 0;
-
- for (i = 0; i < CSSELR_MAX; i++)
- if (is_valid_cache(i))
- count++;
-
- return count;
-}
-
-static int write_demux_regids(u64 __user *uindices)
-{
- u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
- unsigned int i;
-
- val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
- for (i = 0; i < CSSELR_MAX; i++) {
- if (!is_valid_cache(i))
- continue;
- if (put_user(val | i, uindices))
- return -EFAULT;
- uindices++;
- }
- return 0;
-}
-
-static u64 cp15_to_index(const struct coproc_reg *reg)
-{
- u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
- if (reg->is_64bit) {
- val |= KVM_REG_SIZE_U64;
- val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
- /*
- * CRn always denotes the primary coproc. reg. nr. for the
- * in-kernel representation, but the user space API uses the
- * CRm for the encoding, because it is modelled after the
- * MRRC/MCRR instructions: see the ARM ARM rev. c page
- * B3-1445
- */
- val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT);
- } else {
- val |= KVM_REG_SIZE_U32;
- val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
- val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
- val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
- val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
- }
- return val;
-}
-
-static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
-{
- if (!*uind)
- return true;
-
- if (put_user(cp15_to_index(reg), *uind))
- return false;
-
- (*uind)++;
- return true;
-}
-
-/* Assumed ordered tables, see kvm_coproc_table_init. */
-static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
-{
- const struct coproc_reg *i1, *i2, *end1, *end2;
- unsigned int total = 0;
- size_t num;
-
- /* We check for duplicates here, to allow arch-specific overrides. */
- i1 = get_target_table(vcpu->arch.target, &num);
- end1 = i1 + num;
- i2 = cp15_regs;
- end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
-
- BUG_ON(i1 == end1 || i2 == end2);
-
- /* Walk carefully, as both tables may refer to the same register. */
- while (i1 || i2) {
- int cmp = cmp_reg(i1, i2);
- /* target-specific overrides generic entry. */
- if (cmp <= 0) {
- /* Ignore registers we trap but don't save. */
- if (i1->reg) {
- if (!copy_reg_to_user(i1, &uind))
- return -EFAULT;
- total++;
- }
- } else {
- /* Ignore registers we trap but don't save. */
- if (i2->reg) {
- if (!copy_reg_to_user(i2, &uind))
- return -EFAULT;
- total++;
- }
- }
-
- if (cmp <= 0 && ++i1 == end1)
- i1 = NULL;
- if (cmp >= 0 && ++i2 == end2)
- i2 = NULL;
- }
- return total;
-}
-
-unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
-{
- return ARRAY_SIZE(invariant_cp15)
- + num_demux_regs()
- + num_vfp_regs()
- + walk_cp15(vcpu, (u64 __user *)NULL);
-}
-
-int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
-{
- unsigned int i;
- int err;
-
- /* Then give them all the invariant registers' indices. */
- for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
- if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
- return -EFAULT;
- uindices++;
- }
-
- err = walk_cp15(vcpu, uindices);
- if (err < 0)
- return err;
- uindices += err;
-
- err = copy_vfp_regids(uindices);
- if (err < 0)
- return err;
- uindices += err;
-
- return write_demux_regids(uindices);
-}
-
-void kvm_coproc_table_init(void)
-{
- unsigned int i;
-
- /* Make sure tables are unique and in order. */
- BUG_ON(check_reg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
- BUG_ON(check_reg_table(invariant_cp15, ARRAY_SIZE(invariant_cp15)));
-
- /* We abuse the reset function to overwrite the table itself. */
- for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
- invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
-
- /*
- * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
- *
- * If software reads the Cache Type fields from Ctype1
- * upwards, once it has seen a value of 0b000, no caches
- * exist at further-out levels of the hierarchy. So, for
- * example, if Ctype3 is the first Cache Type field with a
- * value of 0b000, the values of Ctype4 to Ctype7 must be
- * ignored.
- */
- asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
- for (i = 0; i < 7; i++)
- if (((cache_levels >> (i*3)) & 7) == 0)
- break;
- /* Clear all higher bits. */
- cache_levels &= (1 << (i*3))-1;
-}
-
-/**
- * kvm_reset_coprocs - sets cp15 registers to reset value
- * @vcpu: The VCPU pointer
- *
- * This function finds the right table above and sets the registers on the
- * virtual CPU struct to their architecturally defined reset values.
- */
-void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
-{
- size_t num;
- const struct coproc_reg *table;
- DECLARE_BITMAP(bmap, NR_CP15_REGS) = { 0, };
-
- /* Generic chip reset first (so target could override). */
- reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs), bmap);
-
- table = get_target_table(vcpu->arch.target, &num);
- reset_coproc_regs(vcpu, table, num, bmap);
-
- for (num = 1; num < NR_CP15_REGS; num++)
- WARN(!test_bit(num, bmap),
- "Didn't reset vcpu_cp15(vcpu, %zi)", num);
-}
diff --git a/arch/arm/kvm/coproc.h b/arch/arm/kvm/coproc.h
deleted file mode 100644
index 637065b..0000000
--- a/arch/arm/kvm/coproc.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Authors: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#ifndef __ARM_KVM_COPROC_LOCAL_H__
-#define __ARM_KVM_COPROC_LOCAL_H__
-
-struct coproc_params {
- unsigned long CRn;
- unsigned long CRm;
- unsigned long Op1;
- unsigned long Op2;
- unsigned long Rt1;
- unsigned long Rt2;
- bool is_64bit;
- bool is_write;
-};
-
-struct coproc_reg {
- /* MRC/MCR/MRRC/MCRR instruction which accesses it. */
- unsigned long CRn;
- unsigned long CRm;
- unsigned long Op1;
- unsigned long Op2;
-
- bool is_64bit;
-
- /* Trapped access from guest, if non-NULL. */
- bool (*access)(struct kvm_vcpu *,
- const struct coproc_params *,
- const struct coproc_reg *);
-
- /* Initialization for vcpu. */
- void (*reset)(struct kvm_vcpu *, const struct coproc_reg *);
-
- /* Index into vcpu_cp15(vcpu, ...), or 0 if we don't need to save it. */
- unsigned long reg;
-
- /* Value (usually reset value) */
- u64 val;
-};
-
-static inline void print_cp_instr(const struct coproc_params *p)
-{
- /* Look, we even formatted it for you to paste into the table! */
- if (p->is_64bit) {
- kvm_pr_unimpl(" { CRm64(%2lu), Op1(%2lu), is64, func_%s },\n",
- p->CRn, p->Op1, p->is_write ? "write" : "read");
- } else {
- kvm_pr_unimpl(" { CRn(%2lu), CRm(%2lu), Op1(%2lu), Op2(%2lu), is32,"
- " func_%s },\n",
- p->CRn, p->CRm, p->Op1, p->Op2,
- p->is_write ? "write" : "read");
- }
-}
-
-static inline bool ignore_write(struct kvm_vcpu *vcpu,
- const struct coproc_params *p)
-{
- return true;
-}
-
-static inline bool read_zero(struct kvm_vcpu *vcpu,
- const struct coproc_params *p)
-{
- *vcpu_reg(vcpu, p->Rt1) = 0;
- return true;
-}
-
-/* Reset functions */
-static inline void reset_unknown(struct kvm_vcpu *vcpu,
- const struct coproc_reg *r)
-{
- BUG_ON(!r->reg);
- BUG_ON(r->reg >= ARRAY_SIZE(vcpu->arch.ctxt.cp15));
- vcpu_cp15(vcpu, r->reg) = 0xdecafbad;
-}
-
-static inline void reset_val(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
-{
- BUG_ON(!r->reg);
- BUG_ON(r->reg >= ARRAY_SIZE(vcpu->arch.ctxt.cp15));
- vcpu_cp15(vcpu, r->reg) = r->val;
-}
-
-static inline void reset_unknown64(struct kvm_vcpu *vcpu,
- const struct coproc_reg *r)
-{
- BUG_ON(!r->reg);
- BUG_ON(r->reg + 1 >= ARRAY_SIZE(vcpu->arch.ctxt.cp15));
-
- vcpu_cp15(vcpu, r->reg) = 0xdecafbad;
- vcpu_cp15(vcpu, r->reg+1) = 0xd0c0ffee;
-}
-
-static inline int cmp_reg(const struct coproc_reg *i1,
- const struct coproc_reg *i2)
-{
- BUG_ON(i1 == i2);
- if (!i1)
- return 1;
- else if (!i2)
- return -1;
- if (i1->CRn != i2->CRn)
- return i1->CRn - i2->CRn;
- if (i1->CRm != i2->CRm)
- return i1->CRm - i2->CRm;
- if (i1->Op1 != i2->Op1)
- return i1->Op1 - i2->Op1;
- if (i1->Op2 != i2->Op2)
- return i1->Op2 - i2->Op2;
- return i2->is_64bit - i1->is_64bit;
-}
-
-
-#define CRn(_x) .CRn = _x
-#define CRm(_x) .CRm = _x
-#define CRm64(_x) .CRn = _x, .CRm = 0
-#define Op1(_x) .Op1 = _x
-#define Op2(_x) .Op2 = _x
-#define is64 .is_64bit = true
-#define is32 .is_64bit = false
-
-bool access_vm_reg(struct kvm_vcpu *vcpu,
- const struct coproc_params *p,
- const struct coproc_reg *r);
-
-#endif /* __ARM_KVM_COPROC_LOCAL_H__ */
diff --git a/arch/arm/kvm/coproc_a15.c b/arch/arm/kvm/coproc_a15.c
deleted file mode 100644
index 36bf154..0000000
--- a/arch/arm/kvm/coproc_a15.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Authors: Rusty Russell <rusty@rustcorp.au>
- * Christoffer Dall <c.dall@virtualopensystems.com>
- */
-#include <linux/kvm_host.h>
-#include <asm/kvm_coproc.h>
-#include <asm/kvm_emulate.h>
-#include <linux/init.h>
-
-#include "coproc.h"
-
-/*
- * A15-specific CP15 registers.
- * CRn denotes the primary register number, but is copied to the CRm in the
- * user space API for 64-bit register access in line with the terminology used
- * in the ARM ARM.
- * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
- * registers preceding 32-bit ones.
- */
-static const struct coproc_reg a15_regs[] = {
- /* SCTLR: swapped by interrupt.S. */
- { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
- access_vm_reg, reset_val, c1_SCTLR, 0x00C50078 },
-};
-
-static struct kvm_coproc_target_table a15_target_table = {
- .target = KVM_ARM_TARGET_CORTEX_A15,
- .table = a15_regs,
- .num = ARRAY_SIZE(a15_regs),
-};
-
-static int __init coproc_a15_init(void)
-{
- kvm_register_target_coproc_table(&a15_target_table);
- return 0;
-}
-late_initcall(coproc_a15_init);
diff --git a/arch/arm/kvm/coproc_a7.c b/arch/arm/kvm/coproc_a7.c
deleted file mode 100644
index 40f643e..0000000
--- a/arch/arm/kvm/coproc_a7.c
+++ /dev/null
@@ -1,42 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Copyright (C) 2013 - ARM Ltd
- *
- * Authors: Rusty Russell <rusty@rustcorp.au>
- * Christoffer Dall <c.dall@virtualopensystems.com>
- * Jonathan Austin <jonathan.austin@arm.com>
- */
-#include <linux/kvm_host.h>
-#include <asm/kvm_coproc.h>
-#include <asm/kvm_emulate.h>
-#include <linux/init.h>
-
-#include "coproc.h"
-
-/*
- * Cortex-A7 specific CP15 registers.
- * CRn denotes the primary register number, but is copied to the CRm in the
- * user space API for 64-bit register access in line with the terminology used
- * in the ARM ARM.
- * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
- * registers preceding 32-bit ones.
- */
-static const struct coproc_reg a7_regs[] = {
- /* SCTLR: swapped by interrupt.S. */
- { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
- access_vm_reg, reset_val, c1_SCTLR, 0x00C50878 },
-};
-
-static struct kvm_coproc_target_table a7_target_table = {
- .target = KVM_ARM_TARGET_CORTEX_A7,
- .table = a7_regs,
- .num = ARRAY_SIZE(a7_regs),
-};
-
-static int __init coproc_a7_init(void)
-{
- kvm_register_target_coproc_table(&a7_target_table);
- return 0;
-}
-late_initcall(coproc_a7_init);
diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
deleted file mode 100644
index 29bb852..0000000
--- a/arch/arm/kvm/emulate.c
+++ /dev/null
@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#include <linux/mm.h>
-#include <linux/kvm_host.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_emulate.h>
-#include <asm/opcodes.h>
-#include <trace/events/kvm.h>
-
-#include "trace.h"
-
-#define VCPU_NR_MODES 6
-#define VCPU_REG_OFFSET_USR 0
-#define VCPU_REG_OFFSET_FIQ 1
-#define VCPU_REG_OFFSET_IRQ 2
-#define VCPU_REG_OFFSET_SVC 3
-#define VCPU_REG_OFFSET_ABT 4
-#define VCPU_REG_OFFSET_UND 5
-#define REG_OFFSET(_reg) \
- (offsetof(struct kvm_regs, _reg) / sizeof(u32))
-
-#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
-
-static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
- /* USR/SYS Registers */
- [VCPU_REG_OFFSET_USR] = {
- USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
- USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
- USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
- USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
- USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
- },
-
- /* FIQ Registers */
- [VCPU_REG_OFFSET_FIQ] = {
- USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
- USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
- USR_REG_OFFSET(6), USR_REG_OFFSET(7),
- REG_OFFSET(fiq_regs[0]), /* r8 */
- REG_OFFSET(fiq_regs[1]), /* r9 */
- REG_OFFSET(fiq_regs[2]), /* r10 */
- REG_OFFSET(fiq_regs[3]), /* r11 */
- REG_OFFSET(fiq_regs[4]), /* r12 */
- REG_OFFSET(fiq_regs[5]), /* r13 */
- REG_OFFSET(fiq_regs[6]), /* r14 */
- },
-
- /* IRQ Registers */
- [VCPU_REG_OFFSET_IRQ] = {
- USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
- USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
- USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
- USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
- USR_REG_OFFSET(12),
- REG_OFFSET(irq_regs[0]), /* r13 */
- REG_OFFSET(irq_regs[1]), /* r14 */
- },
-
- /* SVC Registers */
- [VCPU_REG_OFFSET_SVC] = {
- USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
- USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
- USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
- USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
- USR_REG_OFFSET(12),
- REG_OFFSET(svc_regs[0]), /* r13 */
- REG_OFFSET(svc_regs[1]), /* r14 */
- },
-
- /* ABT Registers */
- [VCPU_REG_OFFSET_ABT] = {
- USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
- USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
- USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
- USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
- USR_REG_OFFSET(12),
- REG_OFFSET(abt_regs[0]), /* r13 */
- REG_OFFSET(abt_regs[1]), /* r14 */
- },
-
- /* UND Registers */
- [VCPU_REG_OFFSET_UND] = {
- USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
- USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
- USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
- USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
- USR_REG_OFFSET(12),
- REG_OFFSET(und_regs[0]), /* r13 */
- REG_OFFSET(und_regs[1]), /* r14 */
- },
-};
-
-/*
- * Return a pointer to the register number valid in the current mode of
- * the virtual CPU.
- */
-unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
-{
- unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.gp_regs;
- unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
-
- switch (mode) {
- case USR_MODE...SVC_MODE:
- mode &= ~MODE32_BIT; /* 0 ... 3 */
- break;
-
- case ABT_MODE:
- mode = VCPU_REG_OFFSET_ABT;
- break;
-
- case UND_MODE:
- mode = VCPU_REG_OFFSET_UND;
- break;
-
- case SYSTEM_MODE:
- mode = VCPU_REG_OFFSET_USR;
- break;
-
- default:
- BUG();
- }
-
- return reg_array + vcpu_reg_offsets[mode][reg_num];
-}
-
-/*
- * Return the SPSR for the current mode of the virtual CPU.
- */
-unsigned long *__vcpu_spsr(struct kvm_vcpu *vcpu)
-{
- unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
- switch (mode) {
- case SVC_MODE:
- return &vcpu->arch.ctxt.gp_regs.KVM_ARM_SVC_spsr;
- case ABT_MODE:
- return &vcpu->arch.ctxt.gp_regs.KVM_ARM_ABT_spsr;
- case UND_MODE:
- return &vcpu->arch.ctxt.gp_regs.KVM_ARM_UND_spsr;
- case IRQ_MODE:
- return &vcpu->arch.ctxt.gp_regs.KVM_ARM_IRQ_spsr;
- case FIQ_MODE:
- return &vcpu->arch.ctxt.gp_regs.KVM_ARM_FIQ_spsr;
- default:
- BUG();
- }
-}
-
-/******************************************************************************
- * Inject exceptions into the guest
- */
-
-/**
- * kvm_inject_vabt - inject an async abort / SError into the guest
- * @vcpu: The VCPU to receive the exception
- *
- * It is assumed that this code is called from the VCPU thread and that the
- * VCPU therefore is not currently executing guest code.
- */
-void kvm_inject_vabt(struct kvm_vcpu *vcpu)
-{
- *vcpu_hcr(vcpu) |= HCR_VA;
-}
diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c
deleted file mode 100644
index 684cf64..0000000
--- a/arch/arm/kvm/guest.c
+++ /dev/null
@@ -1,378 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/kvm_host.h>
-#include <linux/module.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <kvm/arm_psci.h>
-#include <asm/cputype.h>
-#include <linux/uaccess.h>
-#include <asm/kvm.h>
-#include <asm/kvm_emulate.h>
-#include <asm/kvm_coproc.h>
-
-#define VM_STAT(x) { #x, offsetof(struct kvm, stat.x), KVM_STAT_VM }
-#define VCPU_STAT(x) { #x, offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU }
-
-struct kvm_stats_debugfs_item debugfs_entries[] = {
- VCPU_STAT(hvc_exit_stat),
- VCPU_STAT(wfe_exit_stat),
- VCPU_STAT(wfi_exit_stat),
- VCPU_STAT(mmio_exit_user),
- VCPU_STAT(mmio_exit_kernel),
- VCPU_STAT(exits),
- { NULL }
-};
-
-int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
-{
- return 0;
-}
-
-static u64 core_reg_offset_from_id(u64 id)
-{
- return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
-}
-
-static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
-{
- u32 __user *uaddr = (u32 __user *)(long)reg->addr;
- struct kvm_regs *regs = &vcpu->arch.ctxt.gp_regs;
- u64 off;
-
- if (KVM_REG_SIZE(reg->id) != 4)
- return -ENOENT;
-
- /* Our ID is an index into the kvm_regs struct. */
- off = core_reg_offset_from_id(reg->id);
- if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id))
- return -ENOENT;
-
- return put_user(((u32 *)regs)[off], uaddr);
-}
-
-static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
-{
- u32 __user *uaddr = (u32 __user *)(long)reg->addr;
- struct kvm_regs *regs = &vcpu->arch.ctxt.gp_regs;
- u64 off, val;
-
- if (KVM_REG_SIZE(reg->id) != 4)
- return -ENOENT;
-
- /* Our ID is an index into the kvm_regs struct. */
- off = core_reg_offset_from_id(reg->id);
- if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id))
- return -ENOENT;
-
- if (get_user(val, uaddr) != 0)
- return -EFAULT;
-
- if (off == KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr)) {
- unsigned long mode = val & MODE_MASK;
- switch (mode) {
- case USR_MODE:
- case FIQ_MODE:
- case IRQ_MODE:
- case SVC_MODE:
- case ABT_MODE:
- case UND_MODE:
- break;
- default:
- return -EINVAL;
- }
- }
-
- ((u32 *)regs)[off] = val;
- return 0;
-}
-
-int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
-{
- return -EINVAL;
-}
-
-int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
-{
- return -EINVAL;
-}
-
-#define NUM_TIMER_REGS 3
-
-static bool is_timer_reg(u64 index)
-{
- switch (index) {
- case KVM_REG_ARM_TIMER_CTL:
- case KVM_REG_ARM_TIMER_CNT:
- case KVM_REG_ARM_TIMER_CVAL:
- return true;
- }
- return false;
-}
-
-static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
-{
- if (put_user(KVM_REG_ARM_TIMER_CTL, uindices))
- return -EFAULT;
- uindices++;
- if (put_user(KVM_REG_ARM_TIMER_CNT, uindices))
- return -EFAULT;
- uindices++;
- if (put_user(KVM_REG_ARM_TIMER_CVAL, uindices))
- return -EFAULT;
-
- return 0;
-}
-
-static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
-{
- void __user *uaddr = (void __user *)(long)reg->addr;
- u64 val;
- int ret;
-
- ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id));
- if (ret != 0)
- return -EFAULT;
-
- return kvm_arm_timer_set_reg(vcpu, reg->id, val);
-}
-
-static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
-{
- void __user *uaddr = (void __user *)(long)reg->addr;
- u64 val;
-
- val = kvm_arm_timer_get_reg(vcpu, reg->id);
- return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0;
-}
-
-static unsigned long num_core_regs(void)
-{
- return sizeof(struct kvm_regs) / sizeof(u32);
-}
-
-/**
- * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG
- *
- * This is for all registers.
- */
-unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
-{
- return num_core_regs() + kvm_arm_num_coproc_regs(vcpu)
- + kvm_arm_get_fw_num_regs(vcpu)
- + NUM_TIMER_REGS;
-}
-
-/**
- * kvm_arm_copy_reg_indices - get indices of all registers.
- *
- * We do core registers right here, then we append coproc regs.
- */
-int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
-{
- unsigned int i;
- const u64 core_reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_CORE;
- int ret;
-
- for (i = 0; i < sizeof(struct kvm_regs)/sizeof(u32); i++) {
- if (put_user(core_reg | i, uindices))
- return -EFAULT;
- uindices++;
- }
-
- ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices);
- if (ret)
- return ret;
- uindices += kvm_arm_get_fw_num_regs(vcpu);
-
- ret = copy_timer_indices(vcpu, uindices);
- if (ret)
- return ret;
- uindices += NUM_TIMER_REGS;
-
- return kvm_arm_copy_coproc_indices(vcpu, uindices);
-}
-
-int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
-{
- /* We currently use nothing arch-specific in upper 32 bits */
- if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM >> 32)
- return -EINVAL;
-
- /* Register group 16 means we want a core register. */
- if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
- return get_core_reg(vcpu, reg);
-
- if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW)
- return kvm_arm_get_fw_reg(vcpu, reg);
-
- if (is_timer_reg(reg->id))
- return get_timer_reg(vcpu, reg);
-
- return kvm_arm_coproc_get_reg(vcpu, reg);
-}
-
-int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
-{
- /* We currently use nothing arch-specific in upper 32 bits */
- if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM >> 32)
- return -EINVAL;
-
- /* Register group 16 means we set a core register. */
- if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
- return set_core_reg(vcpu, reg);
-
- if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW)
- return kvm_arm_set_fw_reg(vcpu, reg);
-
- if (is_timer_reg(reg->id))
- return set_timer_reg(vcpu, reg);
-
- return kvm_arm_coproc_set_reg(vcpu, reg);
-}
-
-int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
- struct kvm_sregs *sregs)
-{
- return -EINVAL;
-}
-
-int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
- struct kvm_sregs *sregs)
-{
- return -EINVAL;
-}
-
-
-int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
- struct kvm_vcpu_events *events)
-{
- events->exception.serror_pending = !!(*vcpu_hcr(vcpu) & HCR_VA);
-
- return 0;
-}
-
-int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
- struct kvm_vcpu_events *events)
-{
- bool serror_pending = events->exception.serror_pending;
- bool has_esr = events->exception.serror_has_esr;
-
- if (serror_pending && has_esr)
- return -EINVAL;
- else if (serror_pending)
- kvm_inject_vabt(vcpu);
-
- return 0;
-}
-
-int __attribute_const__ kvm_target_cpu(void)
-{
- switch (read_cpuid_part()) {
- case ARM_CPU_PART_CORTEX_A7:
- return KVM_ARM_TARGET_CORTEX_A7;
- case ARM_CPU_PART_CORTEX_A15:
- return KVM_ARM_TARGET_CORTEX_A15;
- default:
- return -EINVAL;
- }
-}
-
-int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init)
-{
- int target = kvm_target_cpu();
-
- if (target < 0)
- return -ENODEV;
-
- memset(init, 0, sizeof(*init));
-
- /*
- * For now, we don't return any features.
- * In future, we might use features to return target
- * specific features available for the preferred
- * target type.
- */
- init->target = (__u32)target;
-
- return 0;
-}
-
-int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
-{
- return -EINVAL;
-}
-
-int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
-{
- return -EINVAL;
-}
-
-int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
- struct kvm_translation *tr)
-{
- return -EINVAL;
-}
-
-int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
- struct kvm_guest_debug *dbg)
-{
- return -EINVAL;
-}
-
-int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
- struct kvm_device_attr *attr)
-{
- int ret;
-
- switch (attr->group) {
- case KVM_ARM_VCPU_TIMER_CTRL:
- ret = kvm_arm_timer_set_attr(vcpu, attr);
- break;
- default:
- ret = -ENXIO;
- break;
- }
-
- return ret;
-}
-
-int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
- struct kvm_device_attr *attr)
-{
- int ret;
-
- switch (attr->group) {
- case KVM_ARM_VCPU_TIMER_CTRL:
- ret = kvm_arm_timer_get_attr(vcpu, attr);
- break;
- default:
- ret = -ENXIO;
- break;
- }
-
- return ret;
-}
-
-int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
- struct kvm_device_attr *attr)
-{
- int ret;
-
- switch (attr->group) {
- case KVM_ARM_VCPU_TIMER_CTRL:
- ret = kvm_arm_timer_has_attr(vcpu, attr);
- break;
- default:
- ret = -ENXIO;
- break;
- }
-
- return ret;
-}
diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c
deleted file mode 100644
index 2a6a139..0000000
--- a/arch/arm/kvm/handle_exit.c
+++ /dev/null
@@ -1,175 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#include <linux/kvm.h>
-#include <linux/kvm_host.h>
-#include <asm/kvm_emulate.h>
-#include <asm/kvm_coproc.h>
-#include <asm/kvm_mmu.h>
-#include <kvm/arm_psci.h>
-#include <trace/events/kvm.h>
-
-#include "trace.h"
-
-typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
-
-static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- int ret;
-
- trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0),
- kvm_vcpu_hvc_get_imm(vcpu));
- vcpu->stat.hvc_exit_stat++;
-
- ret = kvm_hvc_call_handler(vcpu);
- if (ret < 0) {
- vcpu_set_reg(vcpu, 0, ~0UL);
- return 1;
- }
-
- return ret;
-}
-
-static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- /*
- * "If an SMC instruction executed at Non-secure EL1 is
- * trapped to EL2 because HCR_EL2.TSC is 1, the exception is a
- * Trap exception, not a Secure Monitor Call exception [...]"
- *
- * We need to advance the PC after the trap, as it would
- * otherwise return to the same address...
- */
- vcpu_set_reg(vcpu, 0, ~0UL);
- kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
- return 1;
-}
-
-/**
- * kvm_handle_wfx - handle a WFI or WFE instructions trapped in guests
- * @vcpu: the vcpu pointer
- * @run: the kvm_run structure pointer
- *
- * WFE: Yield the CPU and come back to this vcpu when the scheduler
- * decides to.
- * WFI: Simply call kvm_vcpu_block(), which will halt execution of
- * world-switches and schedule other host processes until there is an
- * incoming IRQ or FIQ to the VM.
- */
-static int kvm_handle_wfx(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- if (kvm_vcpu_get_hsr(vcpu) & HSR_WFI_IS_WFE) {
- trace_kvm_wfx(*vcpu_pc(vcpu), true);
- vcpu->stat.wfe_exit_stat++;
- kvm_vcpu_on_spin(vcpu, vcpu_mode_priv(vcpu));
- } else {
- trace_kvm_wfx(*vcpu_pc(vcpu), false);
- vcpu->stat.wfi_exit_stat++;
- kvm_vcpu_block(vcpu);
- kvm_clear_request(KVM_REQ_UNHALT, vcpu);
- }
-
- kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
-
- return 1;
-}
-
-static int kvm_handle_unknown_ec(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- u32 hsr = kvm_vcpu_get_hsr(vcpu);
-
- kvm_pr_unimpl("Unknown exception class: hsr: %#08x\n",
- hsr);
-
- kvm_inject_undefined(vcpu);
- return 1;
-}
-
-static exit_handle_fn arm_exit_handlers[] = {
- [0 ... HSR_EC_MAX] = kvm_handle_unknown_ec,
- [HSR_EC_WFI] = kvm_handle_wfx,
- [HSR_EC_CP15_32] = kvm_handle_cp15_32,
- [HSR_EC_CP15_64] = kvm_handle_cp15_64,
- [HSR_EC_CP14_MR] = kvm_handle_cp14_32,
- [HSR_EC_CP14_LS] = kvm_handle_cp14_load_store,
- [HSR_EC_CP14_64] = kvm_handle_cp14_64,
- [HSR_EC_CP_0_13] = kvm_handle_cp_0_13_access,
- [HSR_EC_CP10_ID] = kvm_handle_cp10_id,
- [HSR_EC_HVC] = handle_hvc,
- [HSR_EC_SMC] = handle_smc,
- [HSR_EC_IABT] = kvm_handle_guest_abort,
- [HSR_EC_DABT] = kvm_handle_guest_abort,
-};
-
-static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
-{
- u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
-
- return arm_exit_handlers[hsr_ec];
-}
-
-/*
- * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
- * proper exit to userspace.
- */
-int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
- int exception_index)
-{
- exit_handle_fn exit_handler;
-
- if (ARM_ABORT_PENDING(exception_index)) {
- u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
-
- /*
- * HVC/SMC already have an adjusted PC, which we need
- * to correct in order to return to after having
- * injected the abort.
- */
- if (hsr_ec == HSR_EC_HVC || hsr_ec == HSR_EC_SMC) {
- u32 adj = kvm_vcpu_trap_il_is32bit(vcpu) ? 4 : 2;
- *vcpu_pc(vcpu) -= adj;
- }
-
- kvm_inject_vabt(vcpu);
- return 1;
- }
-
- exception_index = ARM_EXCEPTION_CODE(exception_index);
-
- switch (exception_index) {
- case ARM_EXCEPTION_IRQ:
- return 1;
- case ARM_EXCEPTION_HVC:
- /*
- * See ARM ARM B1.14.1: "Hyp traps on instructions
- * that fail their condition code check"
- */
- if (!kvm_condition_valid(vcpu)) {
- kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
- return 1;
- }
-
- exit_handler = kvm_get_exit_handler(vcpu);
-
- return exit_handler(vcpu, run);
- case ARM_EXCEPTION_DATA_ABORT:
- kvm_inject_vabt(vcpu);
- return 1;
- case ARM_EXCEPTION_HYP_GONE:
- /*
- * HYP has been reset to the hyp-stub. This happens
- * when a guest is pre-empted by kvm_reboot()'s
- * shutdown call.
- */
- run->exit_reason = KVM_EXIT_FAIL_ENTRY;
- return 0;
- default:
- kvm_pr_unimpl("Unsupported exception type: %d",
- exception_index);
- run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
- return 0;
- }
-}
diff --git a/arch/arm/kvm/hyp/Makefile b/arch/arm/kvm/hyp/Makefile
deleted file mode 100644
index ba88b1e..0000000
--- a/arch/arm/kvm/hyp/Makefile
+++ /dev/null
@@ -1,34 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for Kernel-based Virtual Machine module, HYP part
-#
-
-ccflags-y += -fno-stack-protector -DDISABLE_BRANCH_PROFILING
-
-KVM=../../../../virt/kvm
-
-CFLAGS_ARMV7VE :=$(call cc-option, -march=armv7ve)
-
-obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
-obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
-obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/aarch32.o
-
-obj-$(CONFIG_KVM_ARM_HOST) += tlb.o
-obj-$(CONFIG_KVM_ARM_HOST) += cp15-sr.o
-obj-$(CONFIG_KVM_ARM_HOST) += vfp.o
-obj-$(CONFIG_KVM_ARM_HOST) += banked-sr.o
-CFLAGS_banked-sr.o += $(CFLAGS_ARMV7VE)
-
-obj-$(CONFIG_KVM_ARM_HOST) += entry.o
-obj-$(CONFIG_KVM_ARM_HOST) += hyp-entry.o
-obj-$(CONFIG_KVM_ARM_HOST) += switch.o
-CFLAGS_switch.o += $(CFLAGS_ARMV7VE)
-obj-$(CONFIG_KVM_ARM_HOST) += s2-setup.o
-
-# KVM code is run at a different exception code with a different map, so
-# compiler instrumentation that inserts callbacks or checks into the code may
-# cause crashes. Just disable it.
-GCOV_PROFILE := n
-KASAN_SANITIZE := n
-UBSAN_SANITIZE := n
-KCOV_INSTRUMENT := n
diff --git a/arch/arm/kvm/hyp/banked-sr.c b/arch/arm/kvm/hyp/banked-sr.c
deleted file mode 100644
index c4632ed..0000000
--- a/arch/arm/kvm/hyp/banked-sr.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Original code:
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- *
- * Mostly rewritten in C by Marc Zyngier <marc.zyngier@arm.com>
- */
-
-#include <asm/kvm_hyp.h>
-
-/*
- * gcc before 4.9 doesn't understand -march=armv7ve, so we have to
- * trick the assembler.
- */
-__asm__(".arch_extension virt");
-
-void __hyp_text __banked_save_state(struct kvm_cpu_context *ctxt)
-{
- ctxt->gp_regs.usr_regs.ARM_sp = read_special(SP_usr);
- ctxt->gp_regs.usr_regs.ARM_pc = read_special(ELR_hyp);
- ctxt->gp_regs.usr_regs.ARM_cpsr = read_special(SPSR);
- ctxt->gp_regs.KVM_ARM_SVC_sp = read_special(SP_svc);
- ctxt->gp_regs.KVM_ARM_SVC_lr = read_special(LR_svc);
- ctxt->gp_regs.KVM_ARM_SVC_spsr = read_special(SPSR_svc);
- ctxt->gp_regs.KVM_ARM_ABT_sp = read_special(SP_abt);
- ctxt->gp_regs.KVM_ARM_ABT_lr = read_special(LR_abt);
- ctxt->gp_regs.KVM_ARM_ABT_spsr = read_special(SPSR_abt);
- ctxt->gp_regs.KVM_ARM_UND_sp = read_special(SP_und);
- ctxt->gp_regs.KVM_ARM_UND_lr = read_special(LR_und);
- ctxt->gp_regs.KVM_ARM_UND_spsr = read_special(SPSR_und);
- ctxt->gp_regs.KVM_ARM_IRQ_sp = read_special(SP_irq);
- ctxt->gp_regs.KVM_ARM_IRQ_lr = read_special(LR_irq);
- ctxt->gp_regs.KVM_ARM_IRQ_spsr = read_special(SPSR_irq);
- ctxt->gp_regs.KVM_ARM_FIQ_r8 = read_special(R8_fiq);
- ctxt->gp_regs.KVM_ARM_FIQ_r9 = read_special(R9_fiq);
- ctxt->gp_regs.KVM_ARM_FIQ_r10 = read_special(R10_fiq);
- ctxt->gp_regs.KVM_ARM_FIQ_fp = read_special(R11_fiq);
- ctxt->gp_regs.KVM_ARM_FIQ_ip = read_special(R12_fiq);
- ctxt->gp_regs.KVM_ARM_FIQ_sp = read_special(SP_fiq);
- ctxt->gp_regs.KVM_ARM_FIQ_lr = read_special(LR_fiq);
- ctxt->gp_regs.KVM_ARM_FIQ_spsr = read_special(SPSR_fiq);
-}
-
-void __hyp_text __banked_restore_state(struct kvm_cpu_context *ctxt)
-{
- write_special(ctxt->gp_regs.usr_regs.ARM_sp, SP_usr);
- write_special(ctxt->gp_regs.usr_regs.ARM_pc, ELR_hyp);
- write_special(ctxt->gp_regs.usr_regs.ARM_cpsr, SPSR_cxsf);
- write_special(ctxt->gp_regs.KVM_ARM_SVC_sp, SP_svc);
- write_special(ctxt->gp_regs.KVM_ARM_SVC_lr, LR_svc);
- write_special(ctxt->gp_regs.KVM_ARM_SVC_spsr, SPSR_svc);
- write_special(ctxt->gp_regs.KVM_ARM_ABT_sp, SP_abt);
- write_special(ctxt->gp_regs.KVM_ARM_ABT_lr, LR_abt);
- write_special(ctxt->gp_regs.KVM_ARM_ABT_spsr, SPSR_abt);
- write_special(ctxt->gp_regs.KVM_ARM_UND_sp, SP_und);
- write_special(ctxt->gp_regs.KVM_ARM_UND_lr, LR_und);
- write_special(ctxt->gp_regs.KVM_ARM_UND_spsr, SPSR_und);
- write_special(ctxt->gp_regs.KVM_ARM_IRQ_sp, SP_irq);
- write_special(ctxt->gp_regs.KVM_ARM_IRQ_lr, LR_irq);
- write_special(ctxt->gp_regs.KVM_ARM_IRQ_spsr, SPSR_irq);
- write_special(ctxt->gp_regs.KVM_ARM_FIQ_r8, R8_fiq);
- write_special(ctxt->gp_regs.KVM_ARM_FIQ_r9, R9_fiq);
- write_special(ctxt->gp_regs.KVM_ARM_FIQ_r10, R10_fiq);
- write_special(ctxt->gp_regs.KVM_ARM_FIQ_fp, R11_fiq);
- write_special(ctxt->gp_regs.KVM_ARM_FIQ_ip, R12_fiq);
- write_special(ctxt->gp_regs.KVM_ARM_FIQ_sp, SP_fiq);
- write_special(ctxt->gp_regs.KVM_ARM_FIQ_lr, LR_fiq);
- write_special(ctxt->gp_regs.KVM_ARM_FIQ_spsr, SPSR_fiq);
-}
diff --git a/arch/arm/kvm/hyp/cp15-sr.c b/arch/arm/kvm/hyp/cp15-sr.c
deleted file mode 100644
index e692330..0000000
--- a/arch/arm/kvm/hyp/cp15-sr.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Original code:
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- *
- * Mostly rewritten in C by Marc Zyngier <marc.zyngier@arm.com>
- */
-
-#include <asm/kvm_hyp.h>
-
-static u64 *cp15_64(struct kvm_cpu_context *ctxt, int idx)
-{
- return (u64 *)(ctxt->cp15 + idx);
-}
-
-void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt)
-{
- ctxt->cp15[c0_CSSELR] = read_sysreg(CSSELR);
- ctxt->cp15[c1_SCTLR] = read_sysreg(SCTLR);
- ctxt->cp15[c1_CPACR] = read_sysreg(CPACR);
- *cp15_64(ctxt, c2_TTBR0) = read_sysreg(TTBR0);
- *cp15_64(ctxt, c2_TTBR1) = read_sysreg(TTBR1);
- ctxt->cp15[c2_TTBCR] = read_sysreg(TTBCR);
- ctxt->cp15[c3_DACR] = read_sysreg(DACR);
- ctxt->cp15[c5_DFSR] = read_sysreg(DFSR);
- ctxt->cp15[c5_IFSR] = read_sysreg(IFSR);
- ctxt->cp15[c5_ADFSR] = read_sysreg(ADFSR);
- ctxt->cp15[c5_AIFSR] = read_sysreg(AIFSR);
- ctxt->cp15[c6_DFAR] = read_sysreg(DFAR);
- ctxt->cp15[c6_IFAR] = read_sysreg(IFAR);
- *cp15_64(ctxt, c7_PAR) = read_sysreg(PAR);
- ctxt->cp15[c10_PRRR] = read_sysreg(PRRR);
- ctxt->cp15[c10_NMRR] = read_sysreg(NMRR);
- ctxt->cp15[c10_AMAIR0] = read_sysreg(AMAIR0);
- ctxt->cp15[c10_AMAIR1] = read_sysreg(AMAIR1);
- ctxt->cp15[c12_VBAR] = read_sysreg(VBAR);
- ctxt->cp15[c13_CID] = read_sysreg(CID);
- ctxt->cp15[c13_TID_URW] = read_sysreg(TID_URW);
- ctxt->cp15[c13_TID_URO] = read_sysreg(TID_URO);
- ctxt->cp15[c13_TID_PRIV] = read_sysreg(TID_PRIV);
- ctxt->cp15[c14_CNTKCTL] = read_sysreg(CNTKCTL);
-}
-
-void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt)
-{
- write_sysreg(ctxt->cp15[c0_MPIDR], VMPIDR);
- write_sysreg(ctxt->cp15[c0_CSSELR], CSSELR);
- write_sysreg(ctxt->cp15[c1_SCTLR], SCTLR);
- write_sysreg(ctxt->cp15[c1_CPACR], CPACR);
- write_sysreg(*cp15_64(ctxt, c2_TTBR0), TTBR0);
- write_sysreg(*cp15_64(ctxt, c2_TTBR1), TTBR1);
- write_sysreg(ctxt->cp15[c2_TTBCR], TTBCR);
- write_sysreg(ctxt->cp15[c3_DACR], DACR);
- write_sysreg(ctxt->cp15[c5_DFSR], DFSR);
- write_sysreg(ctxt->cp15[c5_IFSR], IFSR);
- write_sysreg(ctxt->cp15[c5_ADFSR], ADFSR);
- write_sysreg(ctxt->cp15[c5_AIFSR], AIFSR);
- write_sysreg(ctxt->cp15[c6_DFAR], DFAR);
- write_sysreg(ctxt->cp15[c6_IFAR], IFAR);
- write_sysreg(*cp15_64(ctxt, c7_PAR), PAR);
- write_sysreg(ctxt->cp15[c10_PRRR], PRRR);
- write_sysreg(ctxt->cp15[c10_NMRR], NMRR);
- write_sysreg(ctxt->cp15[c10_AMAIR0], AMAIR0);
- write_sysreg(ctxt->cp15[c10_AMAIR1], AMAIR1);
- write_sysreg(ctxt->cp15[c12_VBAR], VBAR);
- write_sysreg(ctxt->cp15[c13_CID], CID);
- write_sysreg(ctxt->cp15[c13_TID_URW], TID_URW);
- write_sysreg(ctxt->cp15[c13_TID_URO], TID_URO);
- write_sysreg(ctxt->cp15[c13_TID_PRIV], TID_PRIV);
- write_sysreg(ctxt->cp15[c14_CNTKCTL], CNTKCTL);
-}
diff --git a/arch/arm/kvm/hyp/entry.S b/arch/arm/kvm/hyp/entry.S
deleted file mode 100644
index 4bd1f6a..0000000
--- a/arch/arm/kvm/hyp/entry.S
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 - ARM Ltd
- * Author: Marc Zyngier <marc.zyngier@arm.com>
-*/
-
-#include <linux/linkage.h>
-#include <asm/asm-offsets.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_asm.h>
-
- .arch_extension virt
-
- .text
- .pushsection .hyp.text, "ax"
-
-#define USR_REGS_OFFSET (CPU_CTXT_GP_REGS + GP_REGS_USR)
-
-/* int __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host) */
-ENTRY(__guest_enter)
- @ Save host registers
- add r1, r1, #(USR_REGS_OFFSET + S_R4)
- stm r1!, {r4-r12}
- str lr, [r1, #4] @ Skip SP_usr (already saved)
-
- @ Restore guest registers
- add r0, r0, #(VCPU_GUEST_CTXT + USR_REGS_OFFSET + S_R0)
- ldr lr, [r0, #S_LR]
- ldm r0, {r0-r12}
-
- clrex
- eret
-ENDPROC(__guest_enter)
-
-ENTRY(__guest_exit)
- /*
- * return convention:
- * guest r0, r1, r2 saved on the stack
- * r0: vcpu pointer
- * r1: exception code
- */
-
- add r2, r0, #(VCPU_GUEST_CTXT + USR_REGS_OFFSET + S_R3)
- stm r2!, {r3-r12}
- str lr, [r2, #4]
- add r2, r0, #(VCPU_GUEST_CTXT + USR_REGS_OFFSET + S_R0)
- pop {r3, r4, r5} @ r0, r1, r2
- stm r2, {r3-r5}
-
- ldr r0, [r0, #VCPU_HOST_CTXT]
- add r0, r0, #(USR_REGS_OFFSET + S_R4)
- ldm r0!, {r4-r12}
- ldr lr, [r0, #4]
-
- mov r0, r1
- mrs r1, SPSR
- mrs r2, ELR_hyp
- mrc p15, 4, r3, c5, c2, 0 @ HSR
-
- /*
- * Force loads and stores to complete before unmasking aborts
- * and forcing the delivery of the exception. This gives us a
- * single instruction window, which the handler will try to
- * match.
- */
- dsb sy
- cpsie a
-
- .global abort_guest_exit_start
-abort_guest_exit_start:
-
- isb
-
- .global abort_guest_exit_end
-abort_guest_exit_end:
-
- /*
- * If we took an abort, r0[31] will be set, and cmp will set
- * the N bit in PSTATE.
- */
- cmp r0, #0
- msrmi SPSR_cxsf, r1
- msrmi ELR_hyp, r2
- mcrmi p15, 4, r3, c5, c2, 0 @ HSR
-
- bx lr
-ENDPROC(__guest_exit)
-
-/*
- * If VFPv3 support is not available, then we will not switch the VFP
- * registers; however cp10 and cp11 accesses will still trap and fallback
- * to the regular coprocessor emulation code, which currently will
- * inject an undefined exception to the guest.
- */
-#ifdef CONFIG_VFPv3
-ENTRY(__vfp_guest_restore)
- push {r3, r4, lr}
-
- @ NEON/VFP used. Turn on VFP access.
- mrc p15, 4, r1, c1, c1, 2 @ HCPTR
- bic r1, r1, #(HCPTR_TCP(10) | HCPTR_TCP(11))
- mcr p15, 4, r1, c1, c1, 2 @ HCPTR
- isb
-
- @ Switch VFP/NEON hardware state to the guest's
- mov r4, r0
- ldr r0, [r0, #VCPU_HOST_CTXT]
- add r0, r0, #CPU_CTXT_VFP
- bl __vfp_save_state
- add r0, r4, #(VCPU_GUEST_CTXT + CPU_CTXT_VFP)
- bl __vfp_restore_state
-
- pop {r3, r4, lr}
- pop {r0, r1, r2}
- clrex
- eret
-ENDPROC(__vfp_guest_restore)
-#endif
-
- .popsection
-
diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S
deleted file mode 100644
index fe3d781..0000000
--- a/arch/arm/kvm/hyp/hyp-entry.S
+++ /dev/null
@@ -1,295 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#include <linux/arm-smccc.h>
-#include <linux/linkage.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_asm.h>
-
- .arch_extension virt
-
- .text
- .pushsection .hyp.text, "ax"
-
-.macro load_vcpu reg
- mrc p15, 4, \reg, c13, c0, 2 @ HTPIDR
-.endm
-
-/********************************************************************
- * Hypervisor exception vector and handlers
- *
- *
- * The KVM/ARM Hypervisor ABI is defined as follows:
- *
- * Entry to Hyp mode from the host kernel will happen _only_ when an HVC
- * instruction is issued since all traps are disabled when running the host
- * kernel as per the Hyp-mode initialization at boot time.
- *
- * HVC instructions cause a trap to the vector page + offset 0x14 (see hyp_hvc
- * below) when the HVC instruction is called from SVC mode (i.e. a guest or the
- * host kernel) and they cause a trap to the vector page + offset 0x8 when HVC
- * instructions are called from within Hyp-mode.
- *
- * Hyp-ABI: Calling HYP-mode functions from host (in SVC mode):
- * Switching to Hyp mode is done through a simple HVC #0 instruction. The
- * exception vector code will check that the HVC comes from VMID==0.
- * - r0 contains a pointer to a HYP function
- * - r1, r2, and r3 contain arguments to the above function.
- * - The HYP function will be called with its arguments in r0, r1 and r2.
- * On HYP function return, we return directly to SVC.
- *
- * Note that the above is used to execute code in Hyp-mode from a host-kernel
- * point of view, and is a different concept from performing a world-switch and
- * executing guest code SVC mode (with a VMID != 0).
- */
-
- .align 5
-__kvm_hyp_vector:
- .global __kvm_hyp_vector
-
- @ Hyp-mode exception vector
- W(b) hyp_reset
- W(b) hyp_undef
- W(b) hyp_svc
- W(b) hyp_pabt
- W(b) hyp_dabt
- W(b) hyp_hvc
- W(b) hyp_irq
- W(b) hyp_fiq
-
-#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
- .align 5
-__kvm_hyp_vector_ic_inv:
- .global __kvm_hyp_vector_ic_inv
-
- /*
- * We encode the exception entry in the bottom 3 bits of
- * SP, and we have to guarantee to be 8 bytes aligned.
- */
- W(add) sp, sp, #1 /* Reset 7 */
- W(add) sp, sp, #1 /* Undef 6 */
- W(add) sp, sp, #1 /* Syscall 5 */
- W(add) sp, sp, #1 /* Prefetch abort 4 */
- W(add) sp, sp, #1 /* Data abort 3 */
- W(add) sp, sp, #1 /* HVC 2 */
- W(add) sp, sp, #1 /* IRQ 1 */
- W(nop) /* FIQ 0 */
-
- mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */
- isb
-
- b decode_vectors
-
- .align 5
-__kvm_hyp_vector_bp_inv:
- .global __kvm_hyp_vector_bp_inv
-
- /*
- * We encode the exception entry in the bottom 3 bits of
- * SP, and we have to guarantee to be 8 bytes aligned.
- */
- W(add) sp, sp, #1 /* Reset 7 */
- W(add) sp, sp, #1 /* Undef 6 */
- W(add) sp, sp, #1 /* Syscall 5 */
- W(add) sp, sp, #1 /* Prefetch abort 4 */
- W(add) sp, sp, #1 /* Data abort 3 */
- W(add) sp, sp, #1 /* HVC 2 */
- W(add) sp, sp, #1 /* IRQ 1 */
- W(nop) /* FIQ 0 */
-
- mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
- isb
-
-decode_vectors:
-
-#ifdef CONFIG_THUMB2_KERNEL
- /*
- * Yet another silly hack: Use VPIDR as a temp register.
- * Thumb2 is really a pain, as SP cannot be used with most
- * of the bitwise instructions. The vect_br macro ensures
- * things gets cleaned-up.
- */
- mcr p15, 4, r0, c0, c0, 0 /* VPIDR */
- mov r0, sp
- and r0, r0, #7
- sub sp, sp, r0
- push {r1, r2}
- mov r1, r0
- mrc p15, 4, r0, c0, c0, 0 /* VPIDR */
- mrc p15, 0, r2, c0, c0, 0 /* MIDR */
- mcr p15, 4, r2, c0, c0, 0 /* VPIDR */
-#endif
-
-.macro vect_br val, targ
-ARM( eor sp, sp, #\val )
-ARM( tst sp, #7 )
-ARM( eorne sp, sp, #\val )
-
-THUMB( cmp r1, #\val )
-THUMB( popeq {r1, r2} )
-
- beq \targ
-.endm
-
- vect_br 0, hyp_fiq
- vect_br 1, hyp_irq
- vect_br 2, hyp_hvc
- vect_br 3, hyp_dabt
- vect_br 4, hyp_pabt
- vect_br 5, hyp_svc
- vect_br 6, hyp_undef
- vect_br 7, hyp_reset
-#endif
-
-.macro invalid_vector label, cause
- .align
-\label: mov r0, #\cause
- b __hyp_panic
-.endm
-
- invalid_vector hyp_reset ARM_EXCEPTION_RESET
- invalid_vector hyp_undef ARM_EXCEPTION_UNDEFINED
- invalid_vector hyp_svc ARM_EXCEPTION_SOFTWARE
- invalid_vector hyp_pabt ARM_EXCEPTION_PREF_ABORT
- invalid_vector hyp_fiq ARM_EXCEPTION_FIQ
-
-ENTRY(__hyp_do_panic)
- mrs lr, cpsr
- bic lr, lr, #MODE_MASK
- orr lr, lr, #SVC_MODE
-THUMB( orr lr, lr, #PSR_T_BIT )
- msr spsr_cxsf, lr
- ldr lr, =panic
- msr ELR_hyp, lr
- ldr lr, =__kvm_call_hyp
- clrex
- eret
-ENDPROC(__hyp_do_panic)
-
-hyp_hvc:
- /*
- * Getting here is either because of a trap from a guest,
- * or from executing HVC from the host kernel, which means
- * "do something in Hyp mode".
- */
- push {r0, r1, r2}
-
- @ Check syndrome register
- mrc p15, 4, r1, c5, c2, 0 @ HSR
- lsr r0, r1, #HSR_EC_SHIFT
- cmp r0, #HSR_EC_HVC
- bne guest_trap @ Not HVC instr.
-
- /*
- * Let's check if the HVC came from VMID 0 and allow simple
- * switch to Hyp mode
- */
- mrrc p15, 6, r0, r2, c2
- lsr r2, r2, #16
- and r2, r2, #0xff
- cmp r2, #0
- bne guest_hvc_trap @ Guest called HVC
-
- /*
- * Getting here means host called HVC, we shift parameters and branch
- * to Hyp function.
- */
- pop {r0, r1, r2}
-
- /*
- * Check if we have a kernel function, which is guaranteed to be
- * bigger than the maximum hyp stub hypercall
- */
- cmp r0, #HVC_STUB_HCALL_NR
- bhs 1f
-
- /*
- * Not a kernel function, treat it as a stub hypercall.
- * Compute the physical address for __kvm_handle_stub_hvc
- * (as the code lives in the idmaped page) and branch there.
- * We hijack ip (r12) as a tmp register.
- */
- push {r1}
- ldr r1, =kimage_voffset
- ldr r1, [r1]
- ldr ip, =__kvm_handle_stub_hvc
- sub ip, ip, r1
- pop {r1}
-
- bx ip
-
-1:
- /*
- * Pushing r2 here is just a way of keeping the stack aligned to
- * 8 bytes on any path that can trigger a HYP exception. Here,
- * we may well be about to jump into the guest, and the guest
- * exit would otherwise be badly decoded by our fancy
- * "decode-exception-without-a-branch" code...
- */
- push {r2, lr}
-
- mov lr, r0
- mov r0, r1
- mov r1, r2
- mov r2, r3
-
-THUMB( orr lr, #1)
- blx lr @ Call the HYP function
-
- pop {r2, lr}
- eret
-
-guest_hvc_trap:
- movw r2, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
- movt r2, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
- ldr r0, [sp] @ Guest's r0
- teq r0, r2
- bne guest_trap
- add sp, sp, #12
- @ Returns:
- @ r0 = 0
- @ r1 = HSR value (perfectly predictable)
- @ r2 = ARM_SMCCC_ARCH_WORKAROUND_1
- mov r0, #0
- eret
-
-guest_trap:
- load_vcpu r0 @ Load VCPU pointer to r0
-
-#ifdef CONFIG_VFPv3
- @ Check for a VFP access
- lsr r1, r1, #HSR_EC_SHIFT
- cmp r1, #HSR_EC_CP_0_13
- beq __vfp_guest_restore
-#endif
-
- mov r1, #ARM_EXCEPTION_HVC
- b __guest_exit
-
-hyp_irq:
- push {r0, r1, r2}
- mov r1, #ARM_EXCEPTION_IRQ
- load_vcpu r0 @ Load VCPU pointer to r0
- b __guest_exit
-
-hyp_dabt:
- push {r0, r1}
- mrs r0, ELR_hyp
- ldr r1, =abort_guest_exit_start
-THUMB( add r1, r1, #1)
- cmp r0, r1
- ldrne r1, =abort_guest_exit_end
-THUMB( addne r1, r1, #1)
- cmpne r0, r1
- pop {r0, r1}
- bne __hyp_panic
-
- orr r0, r0, #(1 << ARM_EXIT_WITH_ABORT_BIT)
- eret
-
- .ltorg
-
- .popsection
diff --git a/arch/arm/kvm/hyp/s2-setup.c b/arch/arm/kvm/hyp/s2-setup.c
deleted file mode 100644
index 5dfbea5..0000000
--- a/arch/arm/kvm/hyp/s2-setup.c
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2016 - ARM Ltd
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- */
-
-#include <linux/types.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_asm.h>
-#include <asm/kvm_hyp.h>
-
-void __hyp_text __init_stage2_translation(void)
-{
- u64 val;
-
- val = read_sysreg(VTCR) & ~VTCR_MASK;
-
- val |= read_sysreg(HTCR) & VTCR_HTCR_SH;
- val |= KVM_VTCR_SL0 | KVM_VTCR_T0SZ | KVM_VTCR_S;
-
- write_sysreg(val, VTCR);
-}
diff --git a/arch/arm/kvm/hyp/switch.c b/arch/arm/kvm/hyp/switch.c
deleted file mode 100644
index 1efeef3..0000000
--- a/arch/arm/kvm/hyp/switch.c
+++ /dev/null
@@ -1,242 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2015 - ARM Ltd
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- */
-#include <linux/jump_label.h>
-
-#include <asm/kvm_asm.h>
-#include <asm/kvm_hyp.h>
-#include <asm/kvm_mmu.h>
-
-__asm__(".arch_extension virt");
-
-/*
- * Activate the traps, saving the host's fpexc register before
- * overwriting it. We'll restore it on VM exit.
- */
-static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu, u32 *fpexc_host)
-{
- u32 val;
-
- /*
- * We are about to set HCPTR.TCP10/11 to trap all floating point
- * register accesses to HYP, however, the ARM ARM clearly states that
- * traps are only taken to HYP if the operation would not otherwise
- * trap to SVC. Therefore, always make sure that for 32-bit guests,
- * we set FPEXC.EN to prevent traps to SVC, when setting the TCP bits.
- */
- val = read_sysreg(VFP_FPEXC);
- *fpexc_host = val;
- if (!(val & FPEXC_EN)) {
- write_sysreg(val | FPEXC_EN, VFP_FPEXC);
- isb();
- }
-
- write_sysreg(vcpu->arch.hcr, HCR);
- /* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */
- write_sysreg(HSTR_T(15), HSTR);
- write_sysreg(HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11), HCPTR);
- val = read_sysreg(HDCR);
- val |= HDCR_TPM | HDCR_TPMCR; /* trap performance monitors */
- val |= HDCR_TDRA | HDCR_TDOSA | HDCR_TDA; /* trap debug regs */
- write_sysreg(val, HDCR);
-}
-
-static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
-{
- u32 val;
-
- /*
- * If we pended a virtual abort, preserve it until it gets
- * cleared. See B1.9.9 (Virtual Abort exception) for details,
- * but the crucial bit is the zeroing of HCR.VA in the
- * pseudocode.
- */
- if (vcpu->arch.hcr & HCR_VA)
- vcpu->arch.hcr = read_sysreg(HCR);
-
- write_sysreg(0, HCR);
- write_sysreg(0, HSTR);
- val = read_sysreg(HDCR);
- write_sysreg(val & ~(HDCR_TPM | HDCR_TPMCR), HDCR);
- write_sysreg(0, HCPTR);
-}
-
-static void __hyp_text __activate_vm(struct kvm_vcpu *vcpu)
-{
- struct kvm *kvm = kern_hyp_va(vcpu->kvm);
- write_sysreg(kvm_get_vttbr(kvm), VTTBR);
- write_sysreg(vcpu->arch.midr, VPIDR);
-}
-
-static void __hyp_text __deactivate_vm(struct kvm_vcpu *vcpu)
-{
- write_sysreg(0, VTTBR);
- write_sysreg(read_sysreg(MIDR), VPIDR);
-}
-
-
-static void __hyp_text __vgic_save_state(struct kvm_vcpu *vcpu)
-{
- if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
- __vgic_v3_save_state(vcpu);
- __vgic_v3_deactivate_traps(vcpu);
- }
-}
-
-static void __hyp_text __vgic_restore_state(struct kvm_vcpu *vcpu)
-{
- if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
- __vgic_v3_activate_traps(vcpu);
- __vgic_v3_restore_state(vcpu);
- }
-}
-
-static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
-{
- u32 hsr = read_sysreg(HSR);
- u8 ec = hsr >> HSR_EC_SHIFT;
- u32 hpfar, far;
-
- vcpu->arch.fault.hsr = hsr;
-
- if (ec == HSR_EC_IABT)
- far = read_sysreg(HIFAR);
- else if (ec == HSR_EC_DABT)
- far = read_sysreg(HDFAR);
- else
- return true;
-
- /*
- * B3.13.5 Reporting exceptions taken to the Non-secure PL2 mode:
- *
- * Abort on the stage 2 translation for a memory access from a
- * Non-secure PL1 or PL0 mode:
- *
- * For any Access flag fault or Translation fault, and also for any
- * Permission fault on the stage 2 translation of a memory access
- * made as part of a translation table walk for a stage 1 translation,
- * the HPFAR holds the IPA that caused the fault. Otherwise, the HPFAR
- * is UNKNOWN.
- */
- if (!(hsr & HSR_DABT_S1PTW) && (hsr & HSR_FSC_TYPE) == FSC_PERM) {
- u64 par, tmp;
-
- par = read_sysreg(PAR);
- write_sysreg(far, ATS1CPR);
- isb();
-
- tmp = read_sysreg(PAR);
- write_sysreg(par, PAR);
-
- if (unlikely(tmp & 1))
- return false; /* Translation failed, back to guest */
-
- hpfar = ((tmp >> 12) & ((1UL << 28) - 1)) << 4;
- } else {
- hpfar = read_sysreg(HPFAR);
- }
-
- vcpu->arch.fault.hxfar = far;
- vcpu->arch.fault.hpfar = hpfar;
- return true;
-}
-
-int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
-{
- struct kvm_cpu_context *host_ctxt;
- struct kvm_cpu_context *guest_ctxt;
- bool fp_enabled;
- u64 exit_code;
- u32 fpexc;
-
- vcpu = kern_hyp_va(vcpu);
- write_sysreg(vcpu, HTPIDR);
-
- host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
- guest_ctxt = &vcpu->arch.ctxt;
-
- __sysreg_save_state(host_ctxt);
- __banked_save_state(host_ctxt);
-
- __activate_traps(vcpu, &fpexc);
- __activate_vm(vcpu);
-
- __vgic_restore_state(vcpu);
- __timer_enable_traps(vcpu);
-
- __sysreg_restore_state(guest_ctxt);
- __banked_restore_state(guest_ctxt);
-
- /* Jump in the fire! */
-again:
- exit_code = __guest_enter(vcpu, host_ctxt);
- /* And we're baaack! */
-
- if (exit_code == ARM_EXCEPTION_HVC && !__populate_fault_info(vcpu))
- goto again;
-
- fp_enabled = __vfp_enabled();
-
- __banked_save_state(guest_ctxt);
- __sysreg_save_state(guest_ctxt);
- __timer_disable_traps(vcpu);
-
- __vgic_save_state(vcpu);
-
- __deactivate_traps(vcpu);
- __deactivate_vm(vcpu);
-
- __banked_restore_state(host_ctxt);
- __sysreg_restore_state(host_ctxt);
-
- if (fp_enabled) {
- __vfp_save_state(&guest_ctxt->vfp);
- __vfp_restore_state(&host_ctxt->vfp);
- }
-
- write_sysreg(fpexc, VFP_FPEXC);
-
- return exit_code;
-}
-
-static const char * const __hyp_panic_string[] = {
- [ARM_EXCEPTION_RESET] = "\nHYP panic: RST PC:%08x CPSR:%08x",
- [ARM_EXCEPTION_UNDEFINED] = "\nHYP panic: UNDEF PC:%08x CPSR:%08x",
- [ARM_EXCEPTION_SOFTWARE] = "\nHYP panic: SVC PC:%08x CPSR:%08x",
- [ARM_EXCEPTION_PREF_ABORT] = "\nHYP panic: PABRT PC:%08x CPSR:%08x",
- [ARM_EXCEPTION_DATA_ABORT] = "\nHYP panic: DABRT PC:%08x ADDR:%08x",
- [ARM_EXCEPTION_IRQ] = "\nHYP panic: IRQ PC:%08x CPSR:%08x",
- [ARM_EXCEPTION_FIQ] = "\nHYP panic: FIQ PC:%08x CPSR:%08x",
- [ARM_EXCEPTION_HVC] = "\nHYP panic: HVC PC:%08x CPSR:%08x",
-};
-
-void __hyp_text __noreturn __hyp_panic(int cause)
-{
- u32 elr = read_special(ELR_hyp);
- u32 val;
-
- if (cause == ARM_EXCEPTION_DATA_ABORT)
- val = read_sysreg(HDFAR);
- else
- val = read_special(SPSR);
-
- if (read_sysreg(VTTBR)) {
- struct kvm_vcpu *vcpu;
- struct kvm_cpu_context *host_ctxt;
-
- vcpu = (struct kvm_vcpu *)read_sysreg(HTPIDR);
- host_ctxt = kern_hyp_va(vcpu->arch.host_cpu_context);
- __timer_disable_traps(vcpu);
- __deactivate_traps(vcpu);
- __deactivate_vm(vcpu);
- __banked_restore_state(host_ctxt);
- __sysreg_restore_state(host_ctxt);
- }
-
- /* Call panic for real */
- __hyp_do_panic(__hyp_panic_string[cause], elr, val);
-
- unreachable();
-}
diff --git a/arch/arm/kvm/hyp/tlb.c b/arch/arm/kvm/hyp/tlb.c
deleted file mode 100644
index 80e6710..0000000
--- a/arch/arm/kvm/hyp/tlb.c
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Original code:
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- *
- * Mostly rewritten in C by Marc Zyngier <marc.zyngier@arm.com>
- */
-
-#include <asm/kvm_hyp.h>
-#include <asm/kvm_mmu.h>
-
-/**
- * Flush per-VMID TLBs
- *
- * __kvm_tlb_flush_vmid(struct kvm *kvm);
- *
- * We rely on the hardware to broadcast the TLB invalidation to all CPUs
- * inside the inner-shareable domain (which is the case for all v7
- * implementations). If we come across a non-IS SMP implementation, we'll
- * have to use an IPI based mechanism. Until then, we stick to the simple
- * hardware assisted version.
- *
- * As v7 does not support flushing per IPA, just nuke the whole TLB
- * instead, ignoring the ipa value.
- */
-void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
-{
- dsb(ishst);
-
- /* Switch to requested VMID */
- kvm = kern_hyp_va(kvm);
- write_sysreg(kvm_get_vttbr(kvm), VTTBR);
- isb();
-
- write_sysreg(0, TLBIALLIS);
- dsb(ish);
- isb();
-
- write_sysreg(0, VTTBR);
-}
-
-void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
-{
- __kvm_tlb_flush_vmid(kvm);
-}
-
-void __hyp_text __kvm_flush_cpu_context(struct kvm_vcpu *vcpu)
-{
- struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm);
-
- /* Switch to requested VMID */
- write_sysreg(kvm_get_vttbr(kvm), VTTBR);
- isb();
-
- write_sysreg(0, TLBIALL);
- write_sysreg(0, ICIALLU);
- dsb(nsh);
- isb();
-
- write_sysreg(0, VTTBR);
-}
-
-void __hyp_text __kvm_flush_vm_context(void)
-{
- write_sysreg(0, TLBIALLNSNHIS);
- write_sysreg(0, ICIALLUIS);
- dsb(ish);
-}
diff --git a/arch/arm/kvm/hyp/vfp.S b/arch/arm/kvm/hyp/vfp.S
deleted file mode 100644
index 675a523..0000000
--- a/arch/arm/kvm/hyp/vfp.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#include <linux/linkage.h>
-#include <asm/vfpmacros.h>
-
- .text
- .pushsection .hyp.text, "ax"
-
-/* void __vfp_save_state(struct vfp_hard_struct *vfp); */
-ENTRY(__vfp_save_state)
- push {r4, r5}
- VFPFMRX r1, FPEXC
-
- @ Make sure *really* VFP is enabled so we can touch the registers.
- orr r5, r1, #FPEXC_EN
- tst r5, #FPEXC_EX @ Check for VFP Subarchitecture
- bic r5, r5, #FPEXC_EX @ FPEXC_EX disable
- VFPFMXR FPEXC, r5
- isb
-
- VFPFMRX r2, FPSCR
- beq 1f
-
- @ If FPEXC_EX is 0, then FPINST/FPINST2 reads are upredictable, so
- @ we only need to save them if FPEXC_EX is set.
- VFPFMRX r3, FPINST
- tst r5, #FPEXC_FP2V
- VFPFMRX r4, FPINST2, ne @ vmrsne
-1:
- VFPFSTMIA r0, r5 @ Save VFP registers
- stm r0, {r1-r4} @ Save FPEXC, FPSCR, FPINST, FPINST2
- pop {r4, r5}
- bx lr
-ENDPROC(__vfp_save_state)
-
-/* void __vfp_restore_state(struct vfp_hard_struct *vfp);
- * Assume FPEXC_EN is on and FPEXC_EX is off */
-ENTRY(__vfp_restore_state)
- VFPFLDMIA r0, r1 @ Load VFP registers
- ldm r0, {r0-r3} @ Load FPEXC, FPSCR, FPINST, FPINST2
-
- VFPFMXR FPSCR, r1
- tst r0, #FPEXC_EX @ Check for VFP Subarchitecture
- beq 1f
- VFPFMXR FPINST, r2
- tst r0, #FPEXC_FP2V
- VFPFMXR FPINST2, r3, ne
-1:
- VFPFMXR FPEXC, r0 @ FPEXC (last, in case !EN)
- bx lr
-ENDPROC(__vfp_restore_state)
-
- .popsection
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
deleted file mode 100644
index 33e34b6..0000000
--- a/arch/arm/kvm/init.S
+++ /dev/null
@@ -1,157 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/unified.h>
-#include <asm/asm-offsets.h>
-#include <asm/kvm_asm.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_mmu.h>
-#include <asm/virt.h>
-
-/********************************************************************
- * Hypervisor initialization
- * - should be called with:
- * r0 = top of Hyp stack (kernel VA)
- * r1 = pointer to hyp vectors
- * r2,r3 = Hypervisor pgd pointer
- *
- * The init scenario is:
- * - We jump in HYP with 3 parameters: runtime HYP pgd, runtime stack,
- * runtime vectors
- * - Invalidate TLBs
- * - Set stack and vectors
- * - Setup the page tables
- * - Enable the MMU
- * - Profit! (or eret, if you only care about the code).
- *
- * Another possibility is to get a HYP stub hypercall.
- * We discriminate between the two by checking if r0 contains a value
- * that is less than HVC_STUB_HCALL_NR.
- */
-
- .text
- .pushsection .hyp.idmap.text,"ax"
- .align 5
-__kvm_hyp_init:
- .globl __kvm_hyp_init
-
- @ Hyp-mode exception vector
- W(b) .
- W(b) .
- W(b) .
- W(b) .
- W(b) .
- W(b) __do_hyp_init
- W(b) .
- W(b) .
-
-__do_hyp_init:
- @ Check for a stub hypercall
- cmp r0, #HVC_STUB_HCALL_NR
- blo __kvm_handle_stub_hvc
-
- @ Set stack pointer
- mov sp, r0
-
- @ Set HVBAR to point to the HYP vectors
- mcr p15, 4, r1, c12, c0, 0 @ HVBAR
-
- @ Set the HTTBR to point to the hypervisor PGD pointer passed
- mcrr p15, 4, rr_lo_hi(r2, r3), c2
-
- @ Set the HTCR and VTCR to the same shareability and cacheability
- @ settings as the non-secure TTBCR and with T0SZ == 0.
- mrc p15, 4, r0, c2, c0, 2 @ HTCR
- ldr r2, =HTCR_MASK
- bic r0, r0, r2
- mrc p15, 0, r1, c2, c0, 2 @ TTBCR
- and r1, r1, #(HTCR_MASK & ~TTBCR_T0SZ)
- orr r0, r0, r1
- mcr p15, 4, r0, c2, c0, 2 @ HTCR
-
- @ Use the same memory attributes for hyp. accesses as the kernel
- @ (copy MAIRx ro HMAIRx).
- mrc p15, 0, r0, c10, c2, 0
- mcr p15, 4, r0, c10, c2, 0
- mrc p15, 0, r0, c10, c2, 1
- mcr p15, 4, r0, c10, c2, 1
-
- @ Invalidate the stale TLBs from Bootloader
- mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH
- dsb ish
-
- @ Set the HSCTLR to:
- @ - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
- @ - Endianness: Kernel config
- @ - Fast Interrupt Features: Kernel config
- @ - Write permission implies XN: disabled
- @ - Instruction cache: enabled
- @ - Data/Unified cache: enabled
- @ - MMU: enabled (this code must be run from an identity mapping)
- mrc p15, 4, r0, c1, c0, 0 @ HSCR
- ldr r2, =HSCTLR_MASK
- bic r0, r0, r2
- mrc p15, 0, r1, c1, c0, 0 @ SCTLR
- ldr r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
- and r1, r1, r2
- ARM( ldr r2, =(HSCTLR_M) )
- THUMB( ldr r2, =(HSCTLR_M | HSCTLR_TE) )
- orr r1, r1, r2
- orr r0, r0, r1
- mcr p15, 4, r0, c1, c0, 0 @ HSCR
- isb
-
- eret
-
-ENTRY(__kvm_handle_stub_hvc)
- cmp r0, #HVC_SOFT_RESTART
- bne 1f
-
- /* The target is expected in r1 */
- msr ELR_hyp, r1
- mrs r0, cpsr
- bic r0, r0, #MODE_MASK
- orr r0, r0, #HYP_MODE
-THUMB( orr r0, r0, #PSR_T_BIT )
- msr spsr_cxsf, r0
- b reset
-
-1: cmp r0, #HVC_RESET_VECTORS
- bne 1f
-
-reset:
- /* We're now in idmap, disable MMU */
- mrc p15, 4, r1, c1, c0, 0 @ HSCTLR
- ldr r0, =(HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I)
- bic r1, r1, r0
- mcr p15, 4, r1, c1, c0, 0 @ HSCTLR
-
- /*
- * Install stub vectors, using ardb's VA->PA trick.
- */
-0: adr r0, 0b @ PA(0)
- movw r1, #:lower16:__hyp_stub_vectors - 0b @ VA(stub) - VA(0)
- movt r1, #:upper16:__hyp_stub_vectors - 0b
- add r1, r1, r0 @ PA(stub)
- mcr p15, 4, r1, c12, c0, 0 @ HVBAR
- b exit
-
-1: ldr r0, =HVC_STUB_ERR
- eret
-
-exit:
- mov r0, #0
- eret
-ENDPROC(__kvm_handle_stub_hvc)
-
- .ltorg
-
- .globl __kvm_hyp_init_end
-__kvm_hyp_init_end:
-
- .popsection
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
deleted file mode 100644
index 064f4f1..0000000
--- a/arch/arm/kvm/interrupts.S
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-
-#include <linux/linkage.h>
-
- .text
-
-/********************************************************************
- * Call function in Hyp mode
- *
- *
- * unsigned long kvm_call_hyp(void *hypfn, ...);
- *
- * This is not really a variadic function in the classic C-way and care must
- * be taken when calling this to ensure parameters are passed in registers
- * only, since the stack will change between the caller and the callee.
- *
- * Call the function with the first argument containing a pointer to the
- * function you wish to call in Hyp mode, and subsequent arguments will be
- * passed as r0, r1, and r2 (a maximum of 3 arguments in addition to the
- * function pointer can be passed). The function being called must be mapped
- * in Hyp mode (see init_hyp_mode in arch/arm/kvm/arm.c). Return values are
- * passed in r0 (strictly 32bit).
- *
- * The calling convention follows the standard AAPCS:
- * r0 - r3: caller save
- * r12: caller save
- * rest: callee save
- */
-ENTRY(__kvm_call_hyp)
- hvc #0
- bx lr
-ENDPROC(__kvm_call_hyp)
diff --git a/arch/arm/kvm/irq.h b/arch/arm/kvm/irq.h
deleted file mode 100644
index 0d257de..0000000
--- a/arch/arm/kvm/irq.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * irq.h: in kernel interrupt controller related definitions
- * Copyright (c) 2016 Red Hat, Inc.
- *
- * This header is included by irqchip.c. However, on ARM, interrupt
- * controller declarations are located in include/kvm/arm_vgic.h since
- * they are mostly shared between arm and arm64.
- */
-
-#ifndef __IRQ_H
-#define __IRQ_H
-
-#include <kvm/arm_vgic.h>
-
-#endif
diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
deleted file mode 100644
index eb4174f..0000000
--- a/arch/arm/kvm/reset.c
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall <c.dall@virtualopensystems.com>
- */
-#include <linux/compiler.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kvm_host.h>
-#include <linux/kvm.h>
-
-#include <asm/unified.h>
-#include <asm/ptrace.h>
-#include <asm/cputype.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_coproc.h>
-#include <asm/kvm_emulate.h>
-
-#include <kvm/arm_arch_timer.h>
-
-/******************************************************************************
- * Cortex-A15 and Cortex-A7 Reset Values
- */
-
-static struct kvm_regs cortexa_regs_reset = {
- .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
-};
-
-
-/*******************************************************************************
- * Exported reset function
- */
-
-/**
- * kvm_reset_vcpu - sets core registers and cp15 registers to reset value
- * @vcpu: The VCPU pointer
- *
- * This function finds the right table above and sets the registers on the
- * virtual CPU struct to their architecturally defined reset values.
- */
-int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
-{
- struct kvm_regs *reset_regs;
-
- switch (vcpu->arch.target) {
- case KVM_ARM_TARGET_CORTEX_A7:
- case KVM_ARM_TARGET_CORTEX_A15:
- reset_regs = &cortexa_regs_reset;
- vcpu->arch.midr = read_cpuid_id();
- break;
- default:
- return -ENODEV;
- }
-
- /* Reset core registers */
- memcpy(&vcpu->arch.ctxt.gp_regs, reset_regs, sizeof(vcpu->arch.ctxt.gp_regs));
-
- /* Reset CP15 registers */
- kvm_reset_coprocs(vcpu);
-
- /*
- * Additional reset state handling that PSCI may have imposed on us.
- * Must be done after all the sys_reg reset.
- */
- if (READ_ONCE(vcpu->arch.reset_state.reset)) {
- unsigned long target_pc = vcpu->arch.reset_state.pc;
-
- /* Gracefully handle Thumb2 entry point */
- if (target_pc & 1) {
- target_pc &= ~1UL;
- vcpu_set_thumb(vcpu);
- }
-
- /* Propagate caller endianness */
- if (vcpu->arch.reset_state.be)
- kvm_vcpu_set_be(vcpu);
-
- *vcpu_pc(vcpu) = target_pc;
- vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0);
-
- vcpu->arch.reset_state.reset = false;
- }
-
- /* Reset arch_timer context */
- return kvm_timer_vcpu_reset(vcpu);
-}
diff --git a/arch/arm/kvm/trace.h b/arch/arm/kvm/trace.h
deleted file mode 100644
index 69a9d62..0000000
--- a/arch/arm/kvm/trace.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#if !defined(_TRACE_ARM_KVM_H) || defined(TRACE_HEADER_MULTI_READ)
-#define _TRACE_ARM_KVM_H
-
-#include <linux/tracepoint.h>
-
-#undef TRACE_SYSTEM
-#define TRACE_SYSTEM kvm
-
-/* Architecturally implementation defined CP15 register access */
-TRACE_EVENT(kvm_emulate_cp15_imp,
- TP_PROTO(unsigned long Op1, unsigned long Rt1, unsigned long CRn,
- unsigned long CRm, unsigned long Op2, bool is_write),
- TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write),
-
- TP_STRUCT__entry(
- __field( unsigned int, Op1 )
- __field( unsigned int, Rt1 )
- __field( unsigned int, CRn )
- __field( unsigned int, CRm )
- __field( unsigned int, Op2 )
- __field( bool, is_write )
- ),
-
- TP_fast_assign(
- __entry->is_write = is_write;
- __entry->Op1 = Op1;
- __entry->Rt1 = Rt1;
- __entry->CRn = CRn;
- __entry->CRm = CRm;
- __entry->Op2 = Op2;
- ),
-
- TP_printk("Implementation defined CP15: %s\tp15, %u, r%u, c%u, c%u, %u",
- (__entry->is_write) ? "mcr" : "mrc",
- __entry->Op1, __entry->Rt1, __entry->CRn,
- __entry->CRm, __entry->Op2)
-);
-
-TRACE_EVENT(kvm_wfx,
- TP_PROTO(unsigned long vcpu_pc, bool is_wfe),
- TP_ARGS(vcpu_pc, is_wfe),
-
- TP_STRUCT__entry(
- __field( unsigned long, vcpu_pc )
- __field( bool, is_wfe )
- ),
-
- TP_fast_assign(
- __entry->vcpu_pc = vcpu_pc;
- __entry->is_wfe = is_wfe;
- ),
-
- TP_printk("guest executed wf%c at: 0x%08lx",
- __entry->is_wfe ? 'e' : 'i', __entry->vcpu_pc)
-);
-
-TRACE_EVENT(kvm_hvc,
- TP_PROTO(unsigned long vcpu_pc, unsigned long r0, unsigned long imm),
- TP_ARGS(vcpu_pc, r0, imm),
-
- TP_STRUCT__entry(
- __field( unsigned long, vcpu_pc )
- __field( unsigned long, r0 )
- __field( unsigned long, imm )
- ),
-
- TP_fast_assign(
- __entry->vcpu_pc = vcpu_pc;
- __entry->r0 = r0;
- __entry->imm = imm;
- ),
-
- TP_printk("HVC at 0x%08lx (r0: 0x%08lx, imm: 0x%lx",
- __entry->vcpu_pc, __entry->r0, __entry->imm)
-);
-
-#endif /* _TRACE_ARM_KVM_H */
-
-#undef TRACE_INCLUDE_PATH
-#define TRACE_INCLUDE_PATH .
-#undef TRACE_INCLUDE_FILE
-#define TRACE_INCLUDE_FILE trace
-
-/* This part must be outside protection */
-#include <trace/define_trace.h>
diff --git a/arch/arm/kvm/vgic-v3-coproc.c b/arch/arm/kvm/vgic-v3-coproc.c
deleted file mode 100644
index ed3b2e4..0000000
--- a/arch/arm/kvm/vgic-v3-coproc.c
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * VGIC system registers handling functions for AArch32 mode
- */
-
-#include <linux/kvm.h>
-#include <linux/kvm_host.h>
-#include <asm/kvm_emulate.h>
-#include "vgic.h"
-
-int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
- u64 *reg)
-{
- /*
- * TODO: Implement for AArch32
- */
- return -ENXIO;
-}
-
-int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write, u64 id,
- u64 *reg)
-{
- /*
- * TODO: Implement for AArch32
- */
- return -ENXIO;
-}
diff --git a/arch/arm/lib/backtrace-clang.S b/arch/arm/lib/backtrace-clang.S
index 2ff3751..6174c45 100644
--- a/arch/arm/lib/backtrace-clang.S
+++ b/arch/arm/lib/backtrace-clang.S
@@ -17,6 +17,7 @@
#define sv_pc r6
#define mask r7
#define sv_lr r8
+#define loglvl r9
ENTRY(c_backtrace)
@@ -99,6 +100,7 @@
@ to ensure 8 byte alignment
movs frame, r0 @ if frame pointer is zero
beq no_frame @ we have no stack frames
+ mov loglvl, r2
tst r1, #0x10 @ 26 or 32-bit mode?
moveq mask, #0xfc000003
movne mask, #0 @ mask for 32-bit
@@ -167,6 +169,7 @@
mov r1, sv_lr
mov r2, frame
bic r1, r1, mask @ mask PC/LR for the mode
+ mov r3, loglvl
bl dump_backtrace_entry
/*
@@ -183,6 +186,7 @@
ldr r0, [frame] @ locals are stored in
@ the preceding frame
subeq r0, r0, #4
+ mov r2, loglvl
bleq dump_backtrace_stm @ dump saved registers
/*
@@ -196,7 +200,8 @@
bhi for_each_frame
1006: adr r0, .Lbad
- mov r1, frame
+ mov r1, loglvl
+ mov r2, frame
bl printk
no_frame: ldmfd sp!, {r4 - r9, fp, pc}
ENDPROC(c_backtrace)
@@ -209,7 +214,7 @@
.long 1005b, 1006b
.popsection
-.Lbad: .asciz "Backtrace aborted due to bad frame pointer <%p>\n"
+.Lbad: .asciz "%sBacktrace aborted due to bad frame pointer <%p>\n"
.align
.Lopcode: .word 0xe92d4800 >> 11 @ stmfd sp!, {... fp, lr}
.word 0x0b000000 @ bl if these bits are set
diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S
index 5829252..872f658 100644
--- a/arch/arm/lib/backtrace.S
+++ b/arch/arm/lib/backtrace.S
@@ -18,6 +18,7 @@
#define sv_pc r6
#define mask r7
#define offset r8
+#define loglvl r9
ENTRY(c_backtrace)
@@ -25,9 +26,10 @@
ret lr
ENDPROC(c_backtrace)
#else
- stmfd sp!, {r4 - r8, lr} @ Save an extra register so we have a location...
+ stmfd sp!, {r4 - r9, lr} @ Save an extra register so we have a location...
movs frame, r0 @ if frame pointer is zero
beq no_frame @ we have no stack frames
+ mov loglvl, r2
tst r1, #0x10 @ 26 or 32-bit mode?
ARM( moveq mask, #0xfc000003 )
@@ -73,6 +75,7 @@
ldr r1, [frame, #-4] @ get saved lr
mov r2, frame
bic r1, r1, mask @ mask PC/LR for the mode
+ mov r3, loglvl
bl dump_backtrace_entry
ldr r1, [sv_pc, #-4] @ if stmfd sp!, {args} exists,
@@ -80,12 +83,14 @@
teq r3, r1, lsr #11
ldreq r0, [frame, #-8] @ get sp
subeq r0, r0, #4 @ point at the last arg
+ mov r2, loglvl
bleq dump_backtrace_stm @ dump saved registers
1004: ldr r1, [sv_pc, #0] @ if stmfd sp!, {..., fp, ip, lr, pc}
ldr r3, .Ldsi @ instruction exists,
teq r3, r1, lsr #11
subeq r0, frame, #16
+ mov r2, loglvl
bleq dump_backtrace_stm @ dump saved registers
teq sv_fp, #0 @ zero saved fp means
@@ -96,9 +101,10 @@
bhi for_each_frame
1006: adr r0, .Lbad
- mov r1, frame
+ mov r1, loglvl
+ mov r2, frame
bl printk
-no_frame: ldmfd sp!, {r4 - r8, pc}
+no_frame: ldmfd sp!, {r4 - r9, pc}
ENDPROC(c_backtrace)
.pushsection __ex_table,"a"
@@ -109,7 +115,7 @@
.long 1004b, 1006b
.popsection
-.Lbad: .asciz "Backtrace aborted due to bad frame pointer <%p>\n"
+.Lbad: .asciz "%sBacktrace aborted due to bad frame pointer <%p>\n"
.align
.Ldsi: .word 0xe92dd800 >> 11 @ stmfd sp!, {... fp, ip, lr, pc}
.word 0xe92d0000 >> 11 @ stmfd sp!, {}
diff --git a/arch/arm/lib/csumpartialcopy.S b/arch/arm/lib/csumpartialcopy.S
index 184d972..1ca6aad 100644
--- a/arch/arm/lib/csumpartialcopy.S
+++ b/arch/arm/lib/csumpartialcopy.S
@@ -9,8 +9,8 @@
.text
-/* Function: __u32 csum_partial_copy_nocheck(const char *src, char *dst, int len, __u32 sum)
- * Params : r0 = src, r1 = dst, r2 = len, r3 = checksum
+/* Function: __u32 csum_partial_copy_nocheck(const char *src, char *dst, int len)
+ * Params : r0 = src, r1 = dst, r2 = len
* Returns : r0 = new checksum
*/
diff --git a/arch/arm/lib/csumpartialcopygeneric.S b/arch/arm/lib/csumpartialcopygeneric.S
index 0b706a3..0fd5c10 100644
--- a/arch/arm/lib/csumpartialcopygeneric.S
+++ b/arch/arm/lib/csumpartialcopygeneric.S
@@ -86,6 +86,7 @@
FN_ENTRY
save_regs
+ mov sum, #-1
cmp len, #8 @ Ensure that we have at least
blo .Lless8 @ 8 bytes to copy.
diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S
index 6bd3a93..6928781 100644
--- a/arch/arm/lib/csumpartialcopyuser.S
+++ b/arch/arm/lib/csumpartialcopyuser.S
@@ -62,9 +62,9 @@
/*
* unsigned int
- * csum_partial_copy_from_user(const char *src, char *dst, int len, int sum, int *err_ptr)
- * r0 = src, r1 = dst, r2 = len, r3 = sum, [sp] = *err_ptr
- * Returns : r0 = checksum, [[sp, #0], #0] = 0 or -EFAULT
+ * csum_partial_copy_from_user(const char *src, char *dst, int len)
+ * r0 = src, r1 = dst, r2 = len
+ * Returns : r0 = checksum or 0
*/
#define FN_ENTRY ENTRY(csum_partial_copy_from_user)
@@ -73,25 +73,11 @@
#include "csumpartialcopygeneric.S"
/*
- * FIXME: minor buglet here
- * We don't return the checksum for the data present in the buffer. To do
- * so properly, we would have to add in whatever registers were loaded before
- * the fault, which, with the current asm above is not predictable.
+ * We report fault by returning 0 csum - impossible in normal case, since
+ * we start with 0xffffffff for initial sum.
*/
.pushsection .text.fixup,"ax"
.align 4
-9001: mov r4, #-EFAULT
-#ifdef CONFIG_CPU_SW_DOMAIN_PAN
- ldr r5, [sp, #9*4] @ *err_ptr
-#else
- ldr r5, [sp, #8*4] @ *err_ptr
-#endif
- str r4, [r5]
- ldmia sp, {r1, r2} @ retrieve dst, len
- add r2, r2, r1
- mov r0, #0 @ zero the buffer
-9002: teq r2, r1
- strbne r0, [r1], #1
- bne 9002b
+9001: mov r0, #0
load_regs
.popsection
diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c
index c945098..106f83a 100644
--- a/arch/arm/lib/uaccess_with_memcpy.c
+++ b/arch/arm/lib/uaccess_with_memcpy.c
@@ -24,6 +24,7 @@
{
unsigned long addr = (unsigned long)_addr;
pgd_t *pgd;
+ p4d_t *p4d;
pmd_t *pmd;
pte_t *pte;
pud_t *pud;
@@ -33,7 +34,11 @@
if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd)))
return 0;
- pud = pud_offset(pgd, addr);
+ p4d = p4d_offset(pgd, addr);
+ if (unlikely(p4d_none(*p4d) || p4d_bad(*p4d)))
+ return 0;
+
+ pud = pud_offset(p4d, addr);
if (unlikely(pud_none(*pud) || pud_bad(*pud)))
return 0;
@@ -96,7 +101,7 @@
atomic = faulthandler_disabled();
if (!atomic)
- down_read(¤t->mm->mmap_sem);
+ mmap_read_lock(current->mm);
while (n) {
pte_t *pte;
spinlock_t *ptl;
@@ -104,11 +109,11 @@
while (!pin_page_for_write(to, &pte, &ptl)) {
if (!atomic)
- up_read(¤t->mm->mmap_sem);
+ mmap_read_unlock(current->mm);
if (__put_user(0, (char __user *)to))
goto out;
if (!atomic)
- down_read(¤t->mm->mmap_sem);
+ mmap_read_lock(current->mm);
}
tocopy = (~(unsigned long)to & ~PAGE_MASK) + 1;
@@ -128,7 +133,7 @@
spin_unlock(ptl);
}
if (!atomic)
- up_read(¤t->mm->mmap_sem);
+ mmap_read_unlock(current->mm);
out:
return n;
@@ -165,17 +170,17 @@
return 0;
}
- down_read(¤t->mm->mmap_sem);
+ mmap_read_lock(current->mm);
while (n) {
pte_t *pte;
spinlock_t *ptl;
int tocopy;
while (!pin_page_for_write(addr, &pte, &ptl)) {
- up_read(¤t->mm->mmap_sem);
+ mmap_read_unlock(current->mm);
if (__put_user(0, (char __user *)addr))
goto out;
- down_read(¤t->mm->mmap_sem);
+ mmap_read_lock(current->mm);
}
tocopy = (~(unsigned long)addr & ~PAGE_MASK) + 1;
@@ -193,7 +198,7 @@
else
spin_unlock(ptl);
}
- up_read(¤t->mm->mmap_sem);
+ mmap_read_unlock(current->mm);
out:
return n;
diff --git a/arch/arm/mach-actions/Kconfig b/arch/arm/mach-actions/Kconfig
index b5e0ac9..00fb4ba 100644
--- a/arch/arm/mach-actions/Kconfig
+++ b/arch/arm/mach-actions/Kconfig
@@ -7,7 +7,6 @@
select ARM_GLOBAL_TIMER
select CACHE_L2X0
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
- select COMMON_CLK
select GENERIC_IRQ_CHIP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
diff --git a/arch/arm/mach-alpine/Kconfig b/arch/arm/mach-alpine/Kconfig
index bc04c91..6a68a16 100644
--- a/arch/arm/mach-alpine/Kconfig
+++ b/arch/arm/mach-alpine/Kconfig
@@ -7,7 +7,6 @@
select ARM_GIC
select GENERIC_IRQ_CHIP
select HAVE_ARM_ARCH_TIMER
- select HAVE_SMP
select MFD_SYSCON
select FORCE_PCI
select PCI_HOST_GENERIC
diff --git a/arch/arm/mach-asm9260/Kconfig b/arch/arm/mach-asm9260/Kconfig
index e42dbaa..a2e1d0a 100644
--- a/arch/arm/mach-asm9260/Kconfig
+++ b/arch/arm/mach-asm9260/Kconfig
@@ -4,6 +4,5 @@
depends on ARCH_MULTI_V5
select CPU_ARM926T
select ASM9260_TIMER
- select GENERIC_CLOCKEVENTS
help
Support for Alphascale ASM9260 based platform.
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index e8d6e99..ea96d11 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -39,7 +39,6 @@
select PINCTRL_ASPEED_G6
select ARM_GIC
select HAVE_ARM_ARCH_TIMER
- select HAVE_SMP
help
Say yes if you intend to run on an Aspeed ast2600 or similar
sixth generation Aspeed BMCs.
diff --git a/arch/arm/mach-at91/.gitignore b/arch/arm/mach-at91/.gitignore
index 2ecd6f5..f6d4738 100644
--- a/arch/arm/mach-at91/.gitignore
+++ b/arch/arm/mach-at91/.gitignore
@@ -1 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
pm_data-offsets.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index af41725..ccd7e80 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -105,11 +105,28 @@
AT91SAM9X35
AT91SAM9XE
+config SOC_SAM9X60
+ bool "SAM9X60"
+ depends on ARCH_MULTI_V5
+ select ATMEL_AIC5_IRQ
+ select ATMEL_PM if PM
+ select ATMEL_SDRAMC
+ select CPU_ARM926T
+ select HAVE_AT91_USB_CLK
+ select HAVE_AT91_GENERATED_CLK
+ select HAVE_AT91_SAM9X60_PLL
+ select MEMORY
+ select PINCTRL_AT91
+ select SOC_SAM_V4_V5
+ select SRAM if PM
+ help
+ Select this if you are using Microchip's SAM9X60 SoC
+
comment "Clocksource driver selection"
config ATMEL_CLOCKSOURCE_PIT
bool "Periodic Interval Timer (PIT) support"
- depends on SOC_AT91SAM9 || SOC_SAMA5
+ depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
default SOC_AT91SAM9 || SOC_SAMA5
select ATMEL_PIT
help
@@ -119,7 +136,7 @@
config ATMEL_CLOCKSOURCE_TCB
bool "Timer Counter Blocks (TCB) support"
- default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAMA5
+ default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
select ATMEL_TCB_CLKSRC
help
Select this to get a high precision clocksource based on a
@@ -136,7 +153,6 @@
config COMMON_CLK_AT91
bool
- select COMMON_CLK
select MFD_SYSCON
config HAVE_AT91_SMD
@@ -154,6 +170,9 @@
config HAVE_AT91_I2S_MUX_CLK
bool
+config HAVE_AT91_SAM9X60_PLL
+ bool
+
config SOC_SAM_V4_V5
bool
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index de64301..f565490 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -6,6 +6,7 @@
# CPU-specific support
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
+obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
obj-$(CONFIG_SOC_SAMA5) += sama5.o
obj-$(CONFIG_SOC_SAMV7) += samv7.o
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index cec195d..5dde732 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
# Empty file waiting for deletion once Makefile.boot isn't needed any more.
# Patch waits for application at
-# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .
+# https://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .
diff --git a/arch/arm/mach-at91/at91sam9.c b/arch/arm/mach-at91/at91sam9.c
index bf629c9..7e57218 100644
--- a/arch/arm/mach-at91/at91sam9.c
+++ b/arch/arm/mach-at91/at91sam9.c
@@ -31,21 +31,3 @@
.init_machine = at91sam9_init,
.dt_compat = at91_dt_board_compat,
MACHINE_END
-
-static void __init sam9x60_init(void)
-{
- of_platform_default_populate(NULL, NULL, NULL);
-
- sam9x60_pm_init();
-}
-
-static const char *const sam9x60_dt_board_compat[] __initconst = {
- "microchip,sam9x60",
- NULL
-};
-
-DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60")
- /* Maintainer: Microchip */
- .init_machine = sam9x60_init,
- .dt_compat = sam9x60_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 676cc2a..3f015cb 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -51,10 +51,11 @@
};
static const match_table_t pm_modes __initconst = {
- { AT91_PM_STANDBY, "standby" },
- { AT91_PM_ULP0, "ulp0" },
- { AT91_PM_ULP1, "ulp1" },
- { AT91_PM_BACKUP, "backup" },
+ { AT91_PM_STANDBY, "standby" },
+ { AT91_PM_ULP0, "ulp0" },
+ { AT91_PM_ULP0_FAST, "ulp0-fast" },
+ { AT91_PM_ULP1, "ulp1" },
+ { AT91_PM_BACKUP, "backup" },
{ -1, NULL },
};
@@ -516,18 +517,22 @@
{ /*sentinel*/ }
};
-static __init void at91_dt_ramc(void)
+static __init int at91_dt_ramc(void)
{
struct device_node *np;
const struct of_device_id *of_id;
int idx = 0;
void *standby = NULL;
const struct ramc_info *ramc;
+ int ret;
for_each_matching_node_and_match(np, ramc_ids, &of_id) {
soc_pm.data.ramc[idx] = of_iomap(np, 0);
- if (!soc_pm.data.ramc[idx])
- panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
+ if (!soc_pm.data.ramc[idx]) {
+ pr_err("unable to map ramc[%d] cpu registers\n", idx);
+ ret = -ENOMEM;
+ goto unmap_ramc;
+ }
ramc = of_id->data;
if (!standby)
@@ -537,15 +542,26 @@
idx++;
}
- if (!idx)
- panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
+ if (!idx) {
+ pr_err("unable to find compatible ram controller node in dtb\n");
+ ret = -ENODEV;
+ goto unmap_ramc;
+ }
if (!standby) {
pr_warn("ramc no standby function available\n");
- return;
+ return 0;
}
at91_cpuidle_device.dev.platform_data = standby;
+
+ return 0;
+
+unmap_ramc:
+ while (idx)
+ iounmap(soc_pm.data.ramc[--idx]);
+
+ return ret;
}
static void at91rm9200_idle(void)
@@ -557,11 +573,6 @@
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
}
-static void at91sam9x60_idle(void)
-{
- cpu_do_idle();
-}
-
static void at91sam9_idle(void)
{
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
@@ -741,13 +752,36 @@
struct pmc_info {
unsigned long uhp_udp_mask;
+ unsigned long mckr;
+ unsigned long version;
};
static const struct pmc_info pmc_infos[] __initconst = {
- { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
- { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
- { .uhp_udp_mask = AT91SAM926x_PMC_UHP },
- { .uhp_udp_mask = 0 },
+ {
+ .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
+ .mckr = 0x30,
+ .version = AT91_PMC_V1,
+ },
+
+ {
+ .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
+ .mckr = 0x30,
+ .version = AT91_PMC_V1,
+ },
+ {
+ .uhp_udp_mask = AT91SAM926x_PMC_UHP,
+ .mckr = 0x30,
+ .version = AT91_PMC_V1,
+ },
+ { .uhp_udp_mask = 0,
+ .mckr = 0x30,
+ .version = AT91_PMC_V1,
+ },
+ {
+ .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
+ .mckr = 0x28,
+ .version = AT91_PMC_V2,
+ },
};
static const struct of_device_id atmel_pmc_ids[] __initconst = {
@@ -762,10 +796,55 @@
{ .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
- { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[1] },
+ { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
{ /* sentinel */ },
};
+static void __init at91_pm_modes_validate(const int *modes, int len)
+{
+ u8 i, standby = 0, suspend = 0;
+ int mode;
+
+ for (i = 0; i < len; i++) {
+ if (standby && suspend)
+ break;
+
+ if (modes[i] == soc_pm.data.standby_mode && !standby) {
+ standby = 1;
+ continue;
+ }
+
+ if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
+ suspend = 1;
+ continue;
+ }
+ }
+
+ if (!standby) {
+ if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
+ mode = AT91_PM_ULP0;
+ else
+ mode = AT91_PM_STANDBY;
+
+ pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
+ pm_modes[soc_pm.data.standby_mode].pattern,
+ pm_modes[mode].pattern);
+ soc_pm.data.standby_mode = mode;
+ }
+
+ if (!suspend) {
+ if (soc_pm.data.standby_mode == AT91_PM_ULP0)
+ mode = AT91_PM_STANDBY;
+ else
+ mode = AT91_PM_ULP0;
+
+ pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
+ pm_modes[soc_pm.data.suspend_mode].pattern,
+ pm_modes[mode].pattern);
+ soc_pm.data.suspend_mode = mode;
+ }
+}
+
static void __init at91_pm_init(void (*pm_idle)(void))
{
struct device_node *pmc_np;
@@ -785,6 +864,8 @@
pmc = of_id->data;
soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
+ soc_pm.data.pmc_mckr_offset = pmc->mckr;
+ soc_pm.data.pmc_version = pmc->version;
if (pm_idle)
arm_pm_idle = pm_idle;
@@ -803,10 +884,22 @@
void __init at91rm9200_pm_init(void)
{
+ int ret;
+
if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
return;
- at91_dt_ramc();
+ /*
+ * Force STANDBY and ULP0 mode to avoid calling
+ * at91_pm_modes_validate() which may increase booting time.
+ * Platform supports anyway only STANDBY and ULP0 modes.
+ */
+ soc_pm.data.standby_mode = AT91_PM_STANDBY;
+ soc_pm.data.suspend_mode = AT91_PM_ULP0;
+
+ ret = at91_dt_ramc();
+ if (ret)
+ return;
/*
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
@@ -818,12 +911,21 @@
void __init sam9x60_pm_init(void)
{
- if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
+ static const int modes[] __initconst = {
+ AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
+ };
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
return;
+ at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_pm_modes_init();
- at91_dt_ramc();
- at91_pm_init(at91sam9x60_idle);
+ ret = at91_dt_ramc();
+ if (ret)
+ return;
+
+ at91_pm_init(NULL);
soc_pm.ws_ids = sam9x60_ws_ids;
soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
@@ -831,29 +933,62 @@
void __init at91sam9_pm_init(void)
{
+ int ret;
+
if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
return;
- at91_dt_ramc();
+ /*
+ * Force STANDBY and ULP0 mode to avoid calling
+ * at91_pm_modes_validate() which may increase booting time.
+ * Platform supports anyway only STANDBY and ULP0 modes.
+ */
+ soc_pm.data.standby_mode = AT91_PM_STANDBY;
+ soc_pm.data.suspend_mode = AT91_PM_ULP0;
+
+ ret = at91_dt_ramc();
+ if (ret)
+ return;
+
at91_pm_init(at91sam9_idle);
}
void __init sama5_pm_init(void)
{
+ static const int modes[] __initconst = {
+ AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
+ };
+ int ret;
+
if (!IS_ENABLED(CONFIG_SOC_SAMA5))
return;
- at91_dt_ramc();
+ at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
+ ret = at91_dt_ramc();
+ if (ret)
+ return;
+
at91_pm_init(NULL);
}
void __init sama5d2_pm_init(void)
{
+ static const int modes[] __initconst = {
+ AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
+ AT91_PM_BACKUP,
+ };
+ int ret;
+
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
return;
+ at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_pm_modes_init();
- sama5_pm_init();
+ ret = at91_dt_ramc();
+ if (ret)
+ return;
+
+ at91_pm_init(NULL);
soc_pm.ws_ids = sama5d2_ws_ids;
soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 9fa4f48..bfb260b 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -19,8 +19,9 @@
#define AT91_PM_STANDBY 0x00
#define AT91_PM_ULP0 0x01
-#define AT91_PM_ULP1 0x02
-#define AT91_PM_BACKUP 0x03
+#define AT91_PM_ULP0_FAST 0x02
+#define AT91_PM_ULP1 0x03
+#define AT91_PM_BACKUP 0x04
#ifndef __ASSEMBLY__
struct at91_pm_data {
@@ -33,6 +34,8 @@
void __iomem *sfrbu;
unsigned int standby_mode;
unsigned int suspend_mode;
+ unsigned int pmc_mckr_offset;
+ unsigned int pmc_version;
};
#endif
diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c
index f2d893c..82089ff 100644
--- a/arch/arm/mach-at91/pm_data-offsets.c
+++ b/arch/arm/mach-at91/pm_data-offsets.c
@@ -12,6 +12,10 @@
DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode));
DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc));
DEFINE(PM_DATA_SFRBU, offsetof(struct at91_pm_data, sfrbu));
+ DEFINE(PM_DATA_PMC_MCKR_OFFSET, offsetof(struct at91_pm_data,
+ pmc_mckr_offset));
+ DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data,
+ pmc_version));
return 0;
}
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index 2591cba..b683c2c 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -18,6 +18,7 @@
pmc .req r0
tmp1 .req r4
tmp2 .req r5
+tmp3 .req r6
/*
* Wait until master clock is ready (after switching master clock source)
@@ -93,13 +94,17 @@
str tmp1, .memtype
ldr tmp1, [r0, #PM_DATA_MODE]
str tmp1, .pm_mode
+ ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
+ str tmp1, .mckr_offset
+ ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
+ str tmp1, .pmc_version
/* Both ldrne below are here to preload their address in the TLB */
ldr tmp1, [r0, #PM_DATA_SHDWC]
str tmp1, .shdwc
cmp tmp1, #0
ldrne tmp2, [tmp1, #0]
ldr tmp1, [r0, #PM_DATA_SFRBU]
- str tmp1, .sfr
+ str tmp1, .sfrbu
cmp tmp1, #0
ldrne tmp2, [tmp1, #0x10]
@@ -138,14 +143,15 @@
ENTRY(at91_backup_mode)
/* Switch the master clock source to slow clock. */
ldr pmc, .pmc_base
- ldr tmp1, [pmc, #AT91_PMC_MCKR]
+ ldr tmp2, .mckr_offset
+ ldr tmp1, [pmc, tmp2]
bic tmp1, tmp1, #AT91_PMC_CSS
- str tmp1, [pmc, #AT91_PMC_MCKR]
+ str tmp1, [pmc, tmp2]
wait_mckrdy
/*BUMEN*/
- ldr r0, .sfr
+ ldr r0, .sfrbu
mov tmp1, #0x1
str tmp1, [r0, #0x10]
@@ -158,7 +164,22 @@
.macro at91_pm_ulp0_mode
ldr pmc, .pmc_base
+ ldr tmp2, .pm_mode
+ ldr tmp3, .mckr_offset
+ /* Check if ULP0 fast variant has been requested. */
+ cmp tmp2, #AT91_PM_ULP0_FAST
+ bne 0f
+
+ /* Set highest prescaler for power saving */
+ ldr tmp1, [pmc, tmp3]
+ bic tmp1, tmp1, #AT91_PMC_PRES
+ orr tmp1, tmp1, #AT91_PMC_PRES_64
+ str tmp1, [pmc, tmp3]
+ wait_mckrdy
+ b 1f
+
+0:
/* Turn off the crystal oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
bic tmp1, tmp1, #AT91_PMC_MOSCEN
@@ -186,7 +207,18 @@
/* Wait for interrupt */
1: at91_cpu_idle
- /* Restore RC oscillator state */
+ /* Check if ULP0 fast variant has been requested. */
+ cmp tmp2, #AT91_PM_ULP0_FAST
+ bne 5f
+
+ /* Set lowest prescaler for fast resume. */
+ ldr tmp1, [pmc, tmp3]
+ bic tmp1, tmp1, #AT91_PMC_PRES
+ str tmp1, [pmc, tmp3]
+ wait_mckrdy
+ b 6f
+
+5: /* Restore RC oscillator state */
ldr tmp1, .saved_osc_status
tst tmp1, #AT91_PMC_MOSCRCS
beq 4f
@@ -210,6 +242,7 @@
str tmp1, [pmc, #AT91_CKGR_MOR]
wait_moscrdy
+6:
.endm
/**
@@ -218,6 +251,7 @@
*/
.macro at91_pm_ulp1_mode
ldr pmc, .pmc_base
+ ldr tmp2, .mckr_offset
/* Save RC oscillator state and check if it is enabled. */
ldr tmp1, [pmc, #AT91_PMC_SR]
@@ -254,10 +288,10 @@
str tmp1, [pmc, #AT91_CKGR_MOR]
/* Switch the master clock source to main clock */
- ldr tmp1, [pmc, #AT91_PMC_MCKR]
+ ldr tmp1, [pmc, tmp2]
bic tmp1, tmp1, #AT91_PMC_CSS
orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
- str tmp1, [pmc, #AT91_PMC_MCKR]
+ str tmp1, [pmc, tmp2]
wait_mckrdy
@@ -284,9 +318,9 @@
wait_moscrdy
/* Switch the master clock source to slow clock */
- ldr tmp1, [pmc, #AT91_PMC_MCKR]
+ ldr tmp1, [pmc, tmp2]
bic tmp1, tmp1, #AT91_PMC_CSS
- str tmp1, [pmc, #AT91_PMC_MCKR]
+ str tmp1, [pmc, tmp2]
wait_mckrdy
@@ -300,10 +334,10 @@
wait_moscsels
/* Switch the master clock source to main clock */
- ldr tmp1, [pmc, #AT91_PMC_MCKR]
+ ldr tmp1, [pmc, tmp2]
bic tmp1, tmp1, #AT91_PMC_CSS
orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
- str tmp1, [pmc, #AT91_PMC_MCKR]
+ str tmp1, [pmc, tmp2]
wait_mckrdy
@@ -327,23 +361,168 @@
3:
.endm
+.macro at91_plla_disable
+ /* Save PLLA setting and disable it */
+ ldr tmp1, .pmc_version
+ cmp tmp1, #AT91_PMC_V1
+ beq 1f
+
+#ifdef CONFIG_SOC_SAM9X60
+ /* Save PLLA settings. */
+ ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT]
+ bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
+ str tmp2, [pmc, #AT91_PMC_PLL_UPDT]
+
+ /* save div. */
+ mov tmp1, #0
+ ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
+ bic tmp2, tmp2, #0xffffff00
+ orr tmp1, tmp1, tmp2
+
+ /* save mul. */
+ ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1]
+ bic tmp2, tmp2, #0xffffff
+ orr tmp1, tmp1, tmp2
+ str tmp1, .saved_pllar
+
+ /* step 2. */
+ ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+ bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
+ bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
+ str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+
+ /* step 3. */
+ ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
+ bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
+ orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
+ str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
+
+ /* step 4. */
+ ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+ orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
+ bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
+ str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+
+ /* step 5. */
+ ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
+ bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
+ str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
+
+ /* step 7. */
+ ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+ orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
+ bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
+ str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+
+ b 2f
+#endif
+
+1: /* Save PLLA setting and disable it */
+ ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
+ str tmp1, .saved_pllar
+
+ /* Disable PLLA. */
+ mov tmp1, #AT91_PMC_PLLCOUNT
+ orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
+ str tmp1, [pmc, #AT91_CKGR_PLLAR]
+2:
+.endm
+
+.macro at91_plla_enable
+ ldr tmp2, .saved_pllar
+ ldr tmp3, .pmc_version
+ cmp tmp3, #AT91_PMC_V1
+ beq 4f
+
+#ifdef CONFIG_SOC_SAM9X60
+ /* step 1. */
+ ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+ bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
+ bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
+ str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+
+ /* step 2. */
+ ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
+ str tmp1, [pmc, #AT91_PMC_PLL_ACR]
+
+ /* step 3. */
+ ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
+ mov tmp3, tmp2
+ bic tmp3, tmp3, #0xffffff
+ orr tmp1, tmp1, tmp3
+ str tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
+
+ /* step 8. */
+ ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+ bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
+ orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
+ str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+
+ /* step 9. */
+ ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
+ orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK
+ orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
+ orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
+ bic tmp1, tmp1, #0xff
+ mov tmp3, tmp2
+ bic tmp3, tmp3, #0xffffff00
+ orr tmp1, tmp1, tmp3
+ str tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
+
+ /* step 10. */
+ ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+ orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
+ bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
+ str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
+
+ /* step 11. */
+3: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0]
+ tst tmp1, #0x1
+ beq 3b
+ b 2f
+#endif
+
+ /* Restore PLLA setting */
+4: str tmp2, [pmc, #AT91_CKGR_PLLAR]
+
+ /* Enable PLLA. */
+ tst tmp2, #(AT91_PMC_MUL & 0xff0000)
+ bne 1f
+ tst tmp2, #(AT91_PMC_MUL & ~0xff0000)
+ beq 2f
+
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
+ tst tmp1, #AT91_PMC_LOCKA
+ beq 1b
+2:
+.endm
+
ENTRY(at91_ulp_mode)
ldr pmc, .pmc_base
+ ldr tmp2, .mckr_offset
+ ldr tmp3, .pm_mode
/* Save Master clock setting */
- ldr tmp1, [pmc, #AT91_PMC_MCKR]
+ ldr tmp1, [pmc, tmp2]
str tmp1, .saved_mckr
/*
- * Set the Master clock source to slow clock
+ * Set master clock source to:
+ * - MAINCK if using ULP0 fast variant
+ * - slow clock, otherwise
*/
bic tmp1, tmp1, #AT91_PMC_CSS
- str tmp1, [pmc, #AT91_PMC_MCKR]
+ cmp tmp3, #AT91_PM_ULP0_FAST
+ bne save_mck
+ orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
+save_mck:
+ str tmp1, [pmc, tmp2]
wait_mckrdy
- ldr r0, .pm_mode
- cmp r0, #AT91_PM_ULP1
+ at91_plla_disable
+
+ cmp tmp3, #AT91_PM_ULP1
beq ulp1_mode
at91_pm_ulp0_mode
@@ -356,11 +535,14 @@
ulp_exit:
ldr pmc, .pmc_base
+ at91_plla_enable
+
/*
* Restore master clock setting
*/
- ldr tmp1, .saved_mckr
- str tmp1, [pmc, #AT91_PMC_MCKR]
+ ldr tmp1, .mckr_offset
+ ldr tmp2, .saved_mckr
+ str tmp2, [pmc, tmp1]
wait_mckrdy
@@ -500,14 +682,20 @@
.word 0
.shdwc:
.word 0
-.sfr:
+.sfrbu:
.word 0
.memtype:
.word 0
.pm_mode:
.word 0
+.mckr_offset:
+ .word 0
+.pmc_version:
+ .word 0
.saved_mckr:
.word 0
+.saved_pllar:
+ .word 0
.saved_sam9_lpr:
.word 0
.saved_sam9_lpr1:
diff --git a/arch/arm/mach-at91/sam9x60.c b/arch/arm/mach-at91/sam9x60.c
new file mode 100644
index 0000000..d8c739d
--- /dev/null
+++ b/arch/arm/mach-at91/sam9x60.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Setup code for SAM9X60.
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
+ */
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/system_misc.h>
+
+#include "generic.h"
+
+static void __init sam9x60_init(void)
+{
+ of_platform_default_populate(NULL, NULL, NULL);
+
+ sam9x60_pm_init();
+}
+
+static const char *const sam9x60_dt_board_compat[] __initconst = {
+ "microchip,sam9x60",
+ NULL
+};
+
+DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60")
+ /* Maintainer: Microchip */
+ .init_machine = sam9x60_init,
+ .dt_compat = sam9x60_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 5e5f1fa..ae79090 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -20,7 +20,6 @@
select GPIOLIB
select ARM_AMBA
select PINCTRL
- select PCI_DOMAINS_GENERIC if PCI
help
This enables support for systems based on Broadcom IPROC architected SoCs.
The IPROC complex contains one or more ARM CPUs along with common
@@ -54,7 +53,7 @@
select ARM_ERRATA_754322
select ARM_ERRATA_775420
select ARM_ERRATA_764369 if SMP
- select HAVE_SMP
+ select ARM_TIMER_SP804
select THERMAL
select THERMAL_OF
help
@@ -73,7 +72,6 @@
select ARM_ERRATA_754322
select ARM_ERRATA_775420
select ARM_ERRATA_764369 if SMP
- select HAVE_SMP
help
Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
@@ -109,7 +107,6 @@
bool "Broadcom BCM281XX SoC family"
depends on ARCH_MULTI_V7
select ARCH_BCM_MOBILE
- select HAVE_SMP
help
Enable support for the BCM281XX family, which includes
BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155
@@ -119,7 +116,6 @@
bool "Broadcom BCM21664 SoC family"
depends on ARCH_MULTI_V7
select ARCH_BCM_MOBILE
- select HAVE_SMP
help
Enable support for the BCM21664 family, which includes
BCM21663 and BCM21664 variants.
@@ -128,7 +124,6 @@
bool "Broadcom BCM23550 SoC"
depends on ARCH_MULTI_V7
select ARCH_BCM_MOBILE
- select HAVE_SMP
help
Enable support for the BCM23550.
@@ -161,15 +156,16 @@
select GPIOLIB
select ARM_AMBA
select ARM_ERRATA_411920 if ARCH_MULTI_V6
+ select ARM_GIC if ARCH_MULTI_V7
+ select ZONE_DMA if ARCH_MULTI_V7
select ARM_TIMER_SP804
select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
- select TIMER_OF
select BCM2835_TIMER
select PINCTRL
select PINCTRL_BCM2835
select MFD_CORE
help
- This enables support for the Broadcom BCM2835 and BCM2836 SoCs.
+ This enables support for the Broadcom BCM2711 and BCM283x SoCs.
This SoC is used in the Raspberry Pi and Roku 2 devices.
config ARCH_BCM_53573
@@ -199,7 +195,6 @@
select HAVE_ARM_ARCH_TIMER
select HAVE_ARM_TWD if SMP
select HAVE_ARM_SCU if SMP
- select HAVE_SMP
help
This enables support for systems based on Broadcom DSL SoCs.
It currently supports the 'BCM63XX' ARM-based family, which includes
@@ -209,9 +204,11 @@
bool "Broadcom BCM7XXX based boards"
depends on ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
+ select ARM_AMBA
select ARM_GIC
select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER
+ select BCM7038_L1_IRQ
select BRCMSTB_L2_IRQ
select BCM7120_L2_IRQ
select ARCH_HAS_HOLES_MEMORYMODEL
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index b59c813..7baa8c9 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -42,8 +42,9 @@
obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o
# BCM2835
-obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
ifeq ($(CONFIG_ARCH_BCM2835),y)
+obj-y += board_bcm2835.o
+obj-y += bcm2711.o
ifeq ($(CONFIG_ARM),y)
obj-$(CONFIG_SMP) += platsmp.o
endif
diff --git a/arch/arm/mach-bcm/bcm2711.c b/arch/arm/mach-bcm/bcm2711.c
new file mode 100644
index 0000000..fa0300d
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm2711.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Stefan Wahren
+ */
+
+#include <linux/of_address.h>
+
+#include <asm/mach/arch.h>
+
+#include "platsmp.h"
+
+static const char * const bcm2711_compat[] = {
+#ifdef CONFIG_ARCH_MULTI_V7
+ "brcm,bcm2711",
+#endif
+ NULL
+};
+
+DT_MACHINE_START(BCM2711, "BCM2711")
+#ifdef CONFIG_ZONE_DMA
+ .dma_zone_size = SZ_1G,
+#endif
+ .dt_compat = bcm2711_compat,
+ .smp = smp_ops(bcm2836_smp_ops),
+MACHINE_END
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c
index 541e850..43a16f9 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.c
+++ b/arch/arm/mach-bcm/bcm_kona_smc.c
@@ -140,7 +140,7 @@
static void __bcm_kona_smc(void *info)
{
struct bcm_kona_smc_data *data = info;
- u32 *args = bcm_smc_buffer;
+ u32 __iomem *args = bcm_smc_buffer;
BUG_ON(smp_processor_id() != 0);
BUG_ON(!args);
diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c
index 47f8053..c9db2a9 100644
--- a/arch/arm/mach-bcm/platsmp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -22,6 +22,8 @@
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
+#include "platsmp.h"
+
/* Size of mapped Cortex A9 SCU address space */
#define CORTEX_A9_SCU_SIZE 0x58
@@ -103,7 +105,7 @@
if (!secondary_boot_addr)
return -EINVAL;
- sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
+ sku_rom_lut = ioremap((phys_addr_t)secondary_boot_addr,
sizeof(phys_addr_t));
if (!sku_rom_lut) {
pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
@@ -172,7 +174,7 @@
if (!secondary_boot_addr)
return -EINVAL;
- boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr,
+ boot_reg = ioremap((phys_addr_t)secondary_boot_addr,
sizeof(phys_addr_t));
if (!boot_reg) {
pr_err("unable to map boot register for cpu %u\n", cpu_id);
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index 5b1f61f..01861fa 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -19,7 +19,6 @@
select CPU_PJ4B
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
- select HAVE_SMP
select PINCTRL_BERLIN_BG2
config MACH_BERLIN_BG2CD
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index fc9188b..314de94 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -2,15 +2,10 @@
menuconfig ARCH_CLPS711X
bool "Cirrus Logic EP721x/EP731x-based"
depends on ARCH_MULTI_V4T
- select AUTO_ZRELADDR
- select TIMER_OF
select CLPS711X_TIMER
- select COMMON_CLK
select CPU_ARM720T
- select GENERIC_CLOCKEVENTS
select GPIOLIB
select MFD_SYSCON
select OF_IRQ
- select USE_OF
help
Select this if you use ARMv4T Cirrus Logic chips.
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 1d61a77..e4f4b20 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -189,12 +189,6 @@
return IRQ_HANDLED;
}
-static struct irqaction cns3xxx_timer_irq = {
- .name = "timer",
- .flags = IRQF_TIMER | IRQF_IRQPOLL,
- .handler = cns3xxx_timer_interrupt,
-};
-
/*
* Set up the clock source and clock events devices
*/
@@ -245,7 +239,9 @@
writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
/* Make irqs happen for the system timer */
- setup_irq(timer_irq, &cns3xxx_timer_irq);
+ if (request_irq(timer_irq, cns3xxx_timer_interrupt,
+ IRQF_TIMER | IRQF_IRQPOLL, "timer", NULL))
+ pr_err("Failed to request irq %d (timer)\n", timer_irq);
cns3xxx_clockevents_init(timer_irq);
}
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 02b180a..f56ff8c 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -64,7 +64,6 @@
default y
depends on ARCH_DAVINCI_DA850
select PINCTRL
- select TIMER_OF
help
Say y here to include support for TI DaVinci DA850 based using
Flattened Device Tree. More information at Documentation/devicetree
@@ -202,15 +201,13 @@
help
Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
System on Module. Information on this SoM may be found at
- http://www.mitydsp.com
+ https://www.mitydsp.com
config MACH_OMAPL138_HAWKBOARD
bool "TI AM1808 / OMAPL-138 Hawkboard platform"
depends on ARCH_DAVINCI_DA850
help
Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform .
- Information of this board may be found at
- http://www.hawkboard.org/
config DAVINCI_MUX
bool "DAVINCI multiplexing support"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index a03d844..58838a9 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -7,8 +7,7 @@
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
# Common objects
-obj-y := time.o serial.o usb.o \
- common.o sram.o
+obj-y := serial.o usb.o common.o sram.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index a273ab2..a20ba12 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -266,7 +266,7 @@
}
};
-/* flash bbt decriptors */
+/* flash bbt descriptors */
static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' };
static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' };
@@ -306,7 +306,7 @@
.core_chipsel = 1,
.parts = da830_evm_nand_partitions,
.nr_parts = ARRAY_SIZE(da830_evm_nand_partitions),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.ecc_bits = 4,
.bbt_options = NAND_BBT_USE_FLASH,
.bbt_td = &da830_evm_nand_bbt_main_descr,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 5b3549f..4280126 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1,7 +1,7 @@
/*
* TI DA850/OMAP-L138 EVM board
*
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
*
* Derived from: arch/arm/mach-davinci/board-da830-evm.c
* Original Copyrights follow:
@@ -239,7 +239,7 @@
.core_chipsel = 1,
.parts = da850_evm_nandflash_partition,
.nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.ecc_bits = 4,
.bbt_options = NAND_BBT_USE_FLASH,
.timing = &da850_evm_nandflash_timing,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 5113273..3c5a9e3 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -82,7 +82,7 @@
.mask_chipsel = BIT(14),
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.bbt_options = NAND_BBT_USE_FLASH,
.ecc_bits = 4,
};
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index b9e9950..e475b21 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -76,7 +76,8 @@
.mask_chipsel = BIT(14),
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .ecc_mode = NAND_ECC_HW_SYNDROME,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
+ .ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED,
.ecc_bits = 4,
.bbt_options = NAND_BBT_USE_FLASH,
};
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 150a36f..bdf31eb 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -30,6 +30,8 @@
#include <linux/spi/eeprom.h>
#include <linux/v4l2-dv-timings.h>
#include <linux/platform_data/ti-aemif.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -144,7 +146,7 @@
.mask_chipsel = BIT(14),
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.bbt_options = NAND_BBT_USE_FLASH,
.ecc_bits = 4,
};
@@ -245,6 +247,19 @@
.bus_delay = 0 /* usec */,
};
+/* Fixed regulator support */
+static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
+ /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
+ REGULATOR_SUPPLY("AVDD", "1-0018"),
+ REGULATOR_SUPPLY("DRVDD", "1-0018"),
+ REGULATOR_SUPPLY("IOVDD", "1-0018"),
+};
+
+static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
+ /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
+ REGULATOR_SUPPLY("DVDD", "1-0018"),
+};
+
static int dm365evm_keyscan_enable(struct device *dev)
{
return davinci_cfg_reg(DM365_KEYSCAN);
@@ -800,6 +815,11 @@
if (ret)
pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
+ regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
+ ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
+ regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
+ ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
+
nvmem_add_cell_table(&davinci_nvmem_cell_table);
nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 9d87d4e..7755ccc 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -29,6 +29,8 @@
#include <linux/v4l2-dv-timings.h>
#include <linux/export.h>
#include <linux/leds.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
#include <media/i2c/tvp514x.h>
@@ -160,7 +162,7 @@
.core_chipsel = 0,
.parts = davinci_evm_nandflash_partition,
.nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.ecc_bits = 1,
.bbt_options = NAND_BBT_USE_FLASH,
.timing = &davinci_evm_nandflash_timing,
@@ -546,8 +548,7 @@
*/
static struct i2c_client *dm6446evm_msp;
-static int dm6446evm_msp_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
+static int dm6446evm_msp_probe(struct i2c_client *client)
{
dm6446evm_msp = client;
return 0;
@@ -567,7 +568,7 @@
static struct i2c_driver dm6446evm_msp_driver = {
.driver.name = "dm6446evm_msp",
.id_table = dm6446evm_msp_ids,
- .probe = dm6446evm_msp_probe,
+ .probe_new = dm6446evm_msp_probe,
.remove = dm6446evm_msp_remove,
};
@@ -685,6 +686,19 @@
}
#endif
+/* Fixed regulator support */
+static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
+ /* Baseboard 3.3V: 5V -> TPS54310PWP -> 3.3V */
+ REGULATOR_SUPPLY("AVDD", "1-001b"),
+ REGULATOR_SUPPLY("DRVDD", "1-001b"),
+};
+
+static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
+ /* Baseboard 1.8V: 5V -> TPS54310PWP -> 1.8V */
+ REGULATOR_SUPPLY("IOVDD", "1-001b"),
+ REGULATOR_SUPPLY("DVDD", "1-001b"),
+};
+
#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
/* venc standard timings */
@@ -823,6 +837,17 @@
#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
+#define GPIO_nVBUS_DRV 160
+
+static struct gpiod_lookup_table dm644evm_usb_gpio_table = {
+ .dev_id = "musb-davinci",
+ .table = {
+ GPIO_LOOKUP("davinci_gpio", GPIO_nVBUS_DRV, NULL,
+ GPIO_ACTIVE_HIGH),
+ { }
+ },
+};
+
static __init void davinci_evm_init(void)
{
int ret;
@@ -831,6 +856,11 @@
dm644x_register_clocks();
+ regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
+ ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
+ regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
+ ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
+
dm644x_init_devices();
ret = dm644x_gpio_register();
@@ -875,6 +905,7 @@
dm644x_init_asp();
/* irlml6401 switches over 1A, in under 8 msec */
+ gpiod_add_lookup_table(&dm644evm_usb_gpio_table);
davinci_setup_usb(1000, 8);
if (IS_BUILTIN(CONFIG_PHYLIB)) {
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 4600b61..952ddab 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -91,7 +91,7 @@
.mask_ale = 0x40000,
.parts = davinci_nand_partitions,
.nr_parts = ARRAY_SIZE(davinci_nand_partitions),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.ecc_bits = 1,
.options = 0,
};
@@ -160,8 +160,7 @@
#define DM646X_EVM_ATA_PWD BIT(1)
/* CPLD Register 0 Client: used for I/O Control */
-static int cpld_reg0_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
+static int cpld_reg0_probe(struct i2c_client *client)
{
if (HAS_ATA) {
u8 data;
@@ -197,7 +196,7 @@
static struct i2c_driver dm6467evm_cpld_driver = {
.driver.name = "cpld_reg0",
.id_table = cpld_reg_ids,
- .probe = cpld_reg0_probe,
+ .probe_new = cpld_reg0_probe,
};
/* LEDS */
@@ -267,20 +266,15 @@
evm_sw_gpio[i] = gpio++;
status = gpio_direction_input(evm_sw_gpio[i]);
- if (status) {
- gpio_free(evm_sw_gpio[i]);
- evm_sw_gpio[i] = -EINVAL;
+ if (status)
goto out_free;
- }
status = gpio_export(evm_sw_gpio[i], 0);
- if (status) {
- gpio_free(evm_sw_gpio[i]);
- evm_sw_gpio[i] = -EINVAL;
+ if (status)
goto out_free;
- }
}
- return status;
+ return 0;
+
out_free:
for (i = 0; i < 4; ++i) {
if (evm_sw_gpio[i] != -EINVAL) {
@@ -402,8 +396,7 @@
#ifdef CONFIG_I2C
static struct i2c_client *cpld_client;
-static int cpld_video_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
+static int cpld_video_probe(struct i2c_client *client)
{
cpld_client = client;
return 0;
@@ -424,7 +417,7 @@
.driver = {
.name = "cpld_video",
},
- .probe = cpld_video_probe,
+ .probe_new = cpld_video_probe,
.remove = cpld_video_remove,
.id_table = cpld_video_id,
};
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index dfce421..5205008 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -1,7 +1,7 @@
/*
* Critical Link MityOMAP-L138 SoM
*
- * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
+ * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of
@@ -432,7 +432,7 @@
.core_chipsel = 1,
.parts = mityomapl138_nandflash_partition,
.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.bbt_options = NAND_BBT_USE_FLASH,
.options = NAND_BUSWIDTH_16,
.ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index ce99f78..b4843f6 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -90,7 +90,7 @@
.core_chipsel = 0,
.parts = davinci_ntosd2_nandflash_partition,
.nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.ecc_bits = 1,
.bbt_options = NAND_BBT_USE_FLASH,
};
@@ -214,7 +214,7 @@
* Mux the pins to be GPIOs, VLYNQEN is already done at startup.
* The AEAWx are five new AEAW pins that can be muxed by separately.
* They are a bitmask for GPIO management. According TI
- * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ
+ * documentation (https://www.ti.com/lit/gpn/tms320dm6446) to employ
* gpio(10,11,12,13) for leds any combination of bits works except
* four last. So we are to reset all five.
*/
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 5390a86..88df801 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -3,7 +3,7 @@
*
* Initial code: Syed Mohammed Khasim
*
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of
@@ -206,7 +206,7 @@
.core_chipsel = 1,
.parts = omapl138_hawk_nandflash_partition,
.nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition),
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
.ecc_bits = 4,
.bbt_options = NAND_BBT_USE_FLASH,
.options = NAND_BUSWIDTH_16,
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index b795f67..dd38785 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -2,7 +2,7 @@
/*
* CPU idle for DaVinci SoCs
*
- * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments Incorporated. https://www.ti.com/
*
* Derived from Marvell Kirkwood CPU idle code
* (arch/arm/mach-kirkwood/cpuidle.c)
diff --git a/arch/arm/mach-davinci/cpuidle.h b/arch/arm/mach-davinci/cpuidle.h
index 74f088b..0d9193a 100644
--- a/arch/arm/mach-davinci/cpuidle.h
+++ b/arch/arm/mach-davinci/cpuidle.h
@@ -1,7 +1,7 @@
/*
* TI DaVinci cpuidle platform support
*
- * 2009 (C) Texas Instruments, Inc. http://www.ti.com/
+ * 2009 (C) Texas Instruments, Inc. https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 73b7cc5..68156e7 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1,7 +1,7 @@
/*
* TI DA850/OMAP-L138 chip specific setup
*
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
*
* Derived from: arch/arm/mach-davinci/da830.c
* Original Copyrights follow:
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 9c0dd02..0cd2f30 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* Modified from mach-omap/omap2/board-generic.c
*/
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 2d69e70..bb36893 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -10,7 +10,7 @@
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
-#include <linux/dma-contiguous.h>
+#include <linux/dma-map-ops.h>
#include <linux/dmaengine.h>
#include <linux/init.h>
#include <linux/io.h>
@@ -21,7 +21,6 @@
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
-#include <mach/time.h>
#include "asp.h"
#include "cpuidle.h"
@@ -885,6 +884,7 @@
void __init da8xx_rproc_reserve_cma(void)
{
+ struct cma *cma;
int ret;
if (!rproc_base || !rproc_size) {
@@ -898,13 +898,16 @@
pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
__func__, rproc_size, (unsigned long)rproc_base);
- ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
- if (ret)
- pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
- else
- rproc_mem_inited = true;
+ ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,
+ true);
+ if (ret) {
+ pr_err("%s: dma_contiguous_reserve_area failed %d\n",
+ __func__, ret);
+ return;
+ }
+ da8xx_dsp.dev.cma_area = cma;
+ rproc_mem_inited = true;
}
-
#else
void __init da8xx_rproc_reserve_cma(void)
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 3e447d4..849e811 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -17,7 +17,6 @@
#include <mach/hardware.h>
#include <mach/cputype.h>
#include <mach/mux.h>
-#include <mach/time.h>
#include "davinci.h"
#include "irqs.h"
@@ -34,7 +33,7 @@
void davinci_map_sysmod(void)
{
- davinci_sysmod_base = ioremap_nocache(DAVINCI_SYSTEM_MODULE_BASE,
+ davinci_sysmod_base = ioremap(DAVINCI_SYSTEM_MODULE_BASE,
0x800);
/*
* Throw a bug since a lot of board initialization code depends
@@ -303,21 +302,3 @@
davinci_gpio_device.dev.platform_data = pdata;
return platform_device_register(&davinci_gpio_device);
}
-
-/*-------------------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------------*/
-
-struct davinci_timer_instance davinci_timer_instance[2] = {
- {
- .base = DAVINCI_TIMER0_BASE,
- .bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12),
- .top_irq = DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34),
- },
- {
- .base = DAVINCI_TIMER1_BASE,
- .bottom_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT12),
- .top_irq = DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34),
- },
-};
-
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 9fc5c73..c1e0d46 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -35,7 +35,8 @@
#include <mach/cputype.h>
#include <mach/mux.h>
#include <mach/serial.h>
-#include <mach/time.h>
+
+#include <clocksource/timer-davinci.h>
#include "asp.h"
#include "davinci.h"
@@ -660,10 +661,16 @@
},
};
-static struct davinci_timer_info dm365_timer_info = {
- .timers = davinci_timer_instance,
- .clockevent_id = T0_BOT,
- .clocksource_id = T0_TOP,
+/*
+ * Bottom half of timer0 is used for clockevent, top half is used for
+ * clocksource.
+ */
+static const struct davinci_timer_cfg dm365_timer_cfg = {
+ .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
+ .irq = {
+ DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
+ DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
+ },
};
#define DM365_UART1_BASE (IO_PHYS + 0x106000)
@@ -723,7 +730,6 @@
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm365_pins,
.pinmux_pins_num = ARRAY_SIZE(dm365_pins),
- .timer_info = &dm365_timer_info,
.emac_pdata = &dm365_emac_pdata,
.sram_dma = 0x00010000,
.sram_len = SZ_32K,
@@ -771,6 +777,7 @@
{
void __iomem *pll1, *pll2, *psc;
struct clk *clk;
+ int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
@@ -789,7 +796,8 @@
return;
}
- davinci_timer_init(clk);
+ rv = davinci_timer_register(clk, &dm365_timer_cfg);
+ WARN(rv, "Unable to register the timer: %d\n", rv);
}
void __init dm365_register_clocks(void)
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 9526e5d..139b83d 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -22,22 +22,6 @@
#define DAVINCI_INTC_START NR_IRQS
#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum))
-void davinci_timer_init(struct clk *clk);
-
-struct davinci_timer_instance {
- u32 base;
- u32 bottom_irq;
- u32 top_irq;
- unsigned long cmp_off;
- unsigned int cmp_irq;
-};
-
-struct davinci_timer_info {
- struct davinci_timer_instance *timers;
- unsigned int clockevent_id;
- unsigned int clocksource_id;
-};
-
struct davinci_gpio_controller;
/*
@@ -58,7 +42,6 @@
u32 pinmux_base;
const struct mux_config *pinmux_pins;
unsigned long pinmux_pins_num;
- struct davinci_timer_info *timer_info;
int gpio_type;
u32 gpio_base;
unsigned gpio_num;
diff --git a/arch/arm/mach-davinci/include/mach/pm.h b/arch/arm/mach-davinci/include/mach/pm.h
index 37b19bf..5a5f0ec 100644
--- a/arch/arm/mach-davinci/include/mach/pm.h
+++ b/arch/arm/mach-davinci/include/mach/pm.h
@@ -1,7 +1,7 @@
/*
* TI DaVinci platform support for power management.
*
- * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h
deleted file mode 100644
index ba91373..0000000
--- a/arch/arm/mach-davinci/include/mach/time.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Local header file for DaVinci time code.
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
-#define __ARCH_ARM_MACH_DAVINCI_TIME_H
-
-#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
-
-enum {
- T0_BOT,
- T0_TOP,
- T1_BOT,
- T1_TOP,
- NUM_TIMERS
-};
-
-#define IS_TIMER1(id) (id & 0x2)
-#define IS_TIMER0(id) (!IS_TIMER1(id))
-#define IS_TIMER_TOP(id) ((id & 0x1))
-#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id))
-
-#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0)
-
-extern struct davinci_timer_instance davinci_timer_instance[];
-
-#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
index e33c6bc..323ee4e 100644
--- a/arch/arm/mach-davinci/pm.c
+++ b/arch/arm/mach-davinci/pm.c
@@ -2,7 +2,7 @@
/*
* DaVinci Power Management Routines
*
- * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/
*/
#include <linux/pm.h>
diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S
index 71262dc..d5affab 100644
--- a/arch/arm/mach-davinci/sleep.S
+++ b/arch/arm/mach-davinci/sleep.S
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * (C) Copyright 2009, Texas Instruments, Inc. http://www.ti.com/
+ * (C) Copyright 2009, Texas Instruments, Inc. https://www.ti.com/
*/
/* replicated define because linux/bitops.h cannot be included in assembly */
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
deleted file mode 100644
index 740410a..0000000
--- a/arch/arm/mach-davinci/time.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- * DaVinci timer subsystem
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/sched_clock.h>
-
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-
-#include <mach/cputype.h>
-#include <mach/hardware.h>
-#include <mach/time.h>
-
-static struct clock_event_device clockevent_davinci;
-static unsigned int davinci_clock_tick_rate;
-
-/*
- * This driver configures the 2 64-bit count-up timers as 4 independent
- * 32-bit count-up timers used as follows:
- */
-
-enum {
- TID_CLOCKEVENT,
- TID_CLOCKSOURCE,
-};
-
-/* Timer register offsets */
-#define PID12 0x0
-#define TIM12 0x10
-#define TIM34 0x14
-#define PRD12 0x18
-#define PRD34 0x1c
-#define TCR 0x20
-#define TGCR 0x24
-#define WDTCR 0x28
-
-/* Offsets of the 8 compare registers */
-#define CMP12_0 0x60
-#define CMP12_1 0x64
-#define CMP12_2 0x68
-#define CMP12_3 0x6c
-#define CMP12_4 0x70
-#define CMP12_5 0x74
-#define CMP12_6 0x78
-#define CMP12_7 0x7c
-
-/* Timer register bitfields */
-#define TCR_ENAMODE_DISABLE 0x0
-#define TCR_ENAMODE_ONESHOT 0x1
-#define TCR_ENAMODE_PERIODIC 0x2
-#define TCR_ENAMODE_MASK 0x3
-
-#define TGCR_TIMMODE_SHIFT 2
-#define TGCR_TIMMODE_64BIT_GP 0x0
-#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
-#define TGCR_TIMMODE_64BIT_WDOG 0x2
-#define TGCR_TIMMODE_32BIT_CHAINED 0x3
-
-#define TGCR_TIM12RS_SHIFT 0
-#define TGCR_TIM34RS_SHIFT 1
-#define TGCR_RESET 0x0
-#define TGCR_UNRESET 0x1
-#define TGCR_RESET_MASK 0x3
-
-struct timer_s {
- char *name;
- unsigned int id;
- unsigned long period;
- unsigned long opts;
- unsigned long flags;
- void __iomem *base;
- unsigned long tim_off;
- unsigned long prd_off;
- unsigned long enamode_shift;
- struct irqaction irqaction;
-};
-static struct timer_s timers[];
-
-/* values for 'opts' field of struct timer_s */
-#define TIMER_OPTS_DISABLED 0x01
-#define TIMER_OPTS_ONESHOT 0x02
-#define TIMER_OPTS_PERIODIC 0x04
-#define TIMER_OPTS_STATE_MASK 0x07
-
-#define TIMER_OPTS_USE_COMPARE 0x80000000
-#define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE)
-
-static char *id_to_name[] = {
- [T0_BOT] = "timer0_0",
- [T0_TOP] = "timer0_1",
- [T1_BOT] = "timer1_0",
- [T1_TOP] = "timer1_1",
-};
-
-static int timer32_config(struct timer_s *t)
-{
- u32 tcr;
- struct davinci_soc_info *soc_info = &davinci_soc_info;
-
- if (USING_COMPARE(t)) {
- struct davinci_timer_instance *dtip =
- soc_info->timer_info->timers;
- int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id);
-
- /*
- * Next interrupt should be the current time reg value plus
- * the new period (using 32-bit unsigned addition/wrapping
- * to 0 on overflow). This assumes that the clocksource
- * is setup to count to 2^32-1 before wrapping around to 0.
- */
- __raw_writel(__raw_readl(t->base + t->tim_off) + t->period,
- t->base + dtip[event_timer].cmp_off);
- } else {
- tcr = __raw_readl(t->base + TCR);
-
- /* disable timer */
- tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
- __raw_writel(tcr, t->base + TCR);
-
- /* reset counter to zero, set new period */
- __raw_writel(0, t->base + t->tim_off);
- __raw_writel(t->period, t->base + t->prd_off);
-
- /* Set enable mode */
- if (t->opts & TIMER_OPTS_ONESHOT)
- tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
- else if (t->opts & TIMER_OPTS_PERIODIC)
- tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
-
- __raw_writel(tcr, t->base + TCR);
- }
- return 0;
-}
-
-static inline u32 timer32_read(struct timer_s *t)
-{
- return __raw_readl(t->base + t->tim_off);
-}
-
-static irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = &clockevent_davinci;
-
- evt->event_handler(evt);
- return IRQ_HANDLED;
-}
-
-/* called when 32-bit counter wraps */
-static irqreturn_t freerun_interrupt(int irq, void *dev_id)
-{
- return IRQ_HANDLED;
-}
-
-static struct timer_s timers[] = {
- [TID_CLOCKEVENT] = {
- .name = "clockevent",
- .opts = TIMER_OPTS_DISABLED,
- .irqaction = {
- .flags = IRQF_TIMER,
- .handler = timer_interrupt,
- }
- },
- [TID_CLOCKSOURCE] = {
- .name = "free-run counter",
- .period = ~0,
- .opts = TIMER_OPTS_PERIODIC,
- .irqaction = {
- .flags = IRQF_TIMER,
- .handler = freerun_interrupt,
- }
- },
-};
-
-static void __init timer_init(void)
-{
- struct davinci_soc_info *soc_info = &davinci_soc_info;
- struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
- void __iomem *base[2];
- int i;
-
- /* Global init of each 64-bit timer as a whole */
- for(i=0; i<2; i++) {
- u32 tgcr;
-
- base[i] = ioremap(dtip[i].base, SZ_4K);
- if (WARN_ON(!base[i]))
- continue;
-
- /* Disabled, Internal clock source */
- __raw_writel(0, base[i] + TCR);
-
- /* reset both timers, no pre-scaler for timer34 */
- tgcr = 0;
- __raw_writel(tgcr, base[i] + TGCR);
-
- /* Set both timers to unchained 32-bit */
- tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
- __raw_writel(tgcr, base[i] + TGCR);
-
- /* Unreset timers */
- tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
- (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
- __raw_writel(tgcr, base[i] + TGCR);
-
- /* Init both counters to zero */
- __raw_writel(0, base[i] + TIM12);
- __raw_writel(0, base[i] + TIM34);
- }
-
- /* Init of each timer as a 32-bit timer */
- for (i=0; i< ARRAY_SIZE(timers); i++) {
- struct timer_s *t = &timers[i];
- int timer = ID_TO_TIMER(t->id);
- u32 irq;
-
- t->base = base[timer];
- if (!t->base)
- continue;
-
- if (IS_TIMER_BOT(t->id)) {
- t->enamode_shift = 6;
- t->tim_off = TIM12;
- t->prd_off = PRD12;
- irq = dtip[timer].bottom_irq;
- } else {
- t->enamode_shift = 22;
- t->tim_off = TIM34;
- t->prd_off = PRD34;
- irq = dtip[timer].top_irq;
- }
-
- /* Register interrupt */
- t->irqaction.name = t->name;
- t->irqaction.dev_id = (void *)t;
-
- if (t->irqaction.handler != NULL) {
- irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
- setup_irq(irq, &t->irqaction);
- }
- }
-}
-
-/*
- * clocksource
- */
-static u64 read_cycles(struct clocksource *cs)
-{
- struct timer_s *t = &timers[TID_CLOCKSOURCE];
-
- return (cycles_t)timer32_read(t);
-}
-
-static struct clocksource clocksource_davinci = {
- .rating = 300,
- .read = read_cycles,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-/*
- * Overwrite weak default sched_clock with something more precise
- */
-static u64 notrace davinci_read_sched_clock(void)
-{
- return timer32_read(&timers[TID_CLOCKSOURCE]);
-}
-
-/*
- * clockevent
- */
-static int davinci_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- struct timer_s *t = &timers[TID_CLOCKEVENT];
-
- t->period = cycles;
- timer32_config(t);
- return 0;
-}
-
-static int davinci_shutdown(struct clock_event_device *evt)
-{
- struct timer_s *t = &timers[TID_CLOCKEVENT];
-
- t->opts &= ~TIMER_OPTS_STATE_MASK;
- t->opts |= TIMER_OPTS_DISABLED;
- return 0;
-}
-
-static int davinci_set_oneshot(struct clock_event_device *evt)
-{
- struct timer_s *t = &timers[TID_CLOCKEVENT];
-
- t->opts &= ~TIMER_OPTS_STATE_MASK;
- t->opts |= TIMER_OPTS_ONESHOT;
- return 0;
-}
-
-static int davinci_set_periodic(struct clock_event_device *evt)
-{
- struct timer_s *t = &timers[TID_CLOCKEVENT];
-
- t->period = davinci_clock_tick_rate / (HZ);
- t->opts &= ~TIMER_OPTS_STATE_MASK;
- t->opts |= TIMER_OPTS_PERIODIC;
- timer32_config(t);
- return 0;
-}
-
-static struct clock_event_device clockevent_davinci = {
- .features = CLOCK_EVT_FEAT_PERIODIC |
- CLOCK_EVT_FEAT_ONESHOT,
- .set_next_event = davinci_set_next_event,
- .set_state_shutdown = davinci_shutdown,
- .set_state_periodic = davinci_set_periodic,
- .set_state_oneshot = davinci_set_oneshot,
-};
-
-void __init davinci_timer_init(struct clk *timer_clk)
-{
- struct davinci_soc_info *soc_info = &davinci_soc_info;
- unsigned int clockevent_id;
- unsigned int clocksource_id;
- int i;
-
- clockevent_id = soc_info->timer_info->clockevent_id;
- clocksource_id = soc_info->timer_info->clocksource_id;
-
- timers[TID_CLOCKEVENT].id = clockevent_id;
- timers[TID_CLOCKSOURCE].id = clocksource_id;
-
- /*
- * If using same timer for both clock events & clocksource,
- * a compare register must be used to generate an event interrupt.
- * This is equivalent to a oneshot timer only (not periodic).
- */
- if (clockevent_id == clocksource_id) {
- struct davinci_timer_instance *dtip =
- soc_info->timer_info->timers;
- int event_timer = ID_TO_TIMER(clockevent_id);
-
- /* Only bottom timers can use compare regs */
- if (IS_TIMER_TOP(clockevent_id))
- pr_warn("%s: Invalid use of system timers. Results unpredictable.\n",
- __func__);
- else if ((dtip[event_timer].cmp_off == 0)
- || (dtip[event_timer].cmp_irq == 0))
- pr_warn("%s: Invalid timer instance setup. Results unpredictable.\n",
- __func__);
- else {
- timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE;
- clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT;
- }
- }
-
- BUG_ON(IS_ERR(timer_clk));
- clk_prepare_enable(timer_clk);
-
- /* init timer hw */
- timer_init();
-
- davinci_clock_tick_rate = clk_get_rate(timer_clk);
-
- /* setup clocksource */
- clocksource_davinci.name = id_to_name[clocksource_id];
- if (clocksource_register_hz(&clocksource_davinci,
- davinci_clock_tick_rate))
- pr_err("%s: can't register clocksource!\n",
- clocksource_davinci.name);
-
- sched_clock_register(davinci_read_sched_clock, 32,
- davinci_clock_tick_rate);
-
- /* setup clockevent */
- clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
-
- clockevent_davinci.cpumask = cpumask_of(0);
- clockevents_config_and_register(&clockevent_davinci,
- davinci_clock_tick_rate, 1, 0xfffffffe);
-
- for (i=0; i< ARRAY_SIZE(timers); i++)
- timer32_config(&timers[i]);
-}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 01b830a..dbe970e 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -48,7 +48,7 @@
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
-static struct map_desc dove_io_desc[] __initdata = {
+static struct map_desc __maybe_unused dove_io_desc[] __initdata = {
{
.virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index da2ff4f..5960e3d 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -17,7 +17,6 @@
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/system_misc.h>
@@ -201,17 +200,13 @@
return IRQ_HANDLED;
}
-static struct irqaction ebsa110_timer_irq = {
- .name = "EBSA110 Timer Tick",
- .flags = IRQF_TIMER | IRQF_IRQPOLL,
- .handler = ebsa110_timer_interrupt,
-};
-
/*
* Set up timer interrupt.
*/
void __init ebsa110_timer_init(void)
{
+ int irq = IRQ_EBSA110_TIMER0;
+
arch_gettimeoffset = ebsa110_gettimeoffset;
/*
@@ -221,7 +216,9 @@
__raw_writeb(COUNT & 0xff, PIT_T1);
__raw_writeb(COUNT >> 8, PIT_T1);
- setup_irq(IRQ_EBSA110_TIMER0, &ebsa110_timer_irq);
+ if (request_irq(irq, ebsa110_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
+ "EBSA110 Timer Tick", NULL))
+ pr_err("Failed to request irq %d (EBSA110 Timer Tick)\n", irq);
}
static struct plat_serial8250_port serial_platform_data[] = {
diff --git a/arch/arm/mach-ep93xx/crunch.c b/arch/arm/mach-ep93xx/crunch.c
index 1c05c5b..757032d 100644
--- a/arch/arm/mach-ep93xx/crunch.c
+++ b/arch/arm/mach-ep93xx/crunch.c
@@ -49,7 +49,7 @@
* FALLTHROUGH: Ensure we don't try to overwrite our newly
* initialised state information on the first fault.
*/
- /* Fall through */
+ fallthrough;
case THREAD_NOTIFY_EXIT:
crunch_task_release(thread);
diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/timer-ep93xx.c
index de99883..dd4b164 100644
--- a/arch/arm/mach-ep93xx/timer-ep93xx.c
+++ b/arch/arm/mach-ep93xx/timer-ep93xx.c
@@ -117,15 +117,11 @@
return IRQ_HANDLED;
}
-static struct irqaction ep93xx_timer_irq = {
- .name = "ep93xx timer",
- .flags = IRQF_TIMER | IRQF_IRQPOLL,
- .handler = ep93xx_timer_interrupt,
- .dev_id = &ep93xx_clockevent,
-};
-
void __init ep93xx_timer_init(void)
{
+ int irq = IRQ_EP93XX_TIMER3;
+ unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL;
+
/* Enable and register clocksource and sched_clock on timer 4 */
writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
EP93XX_TIMER4_VALUE_HIGH);
@@ -136,7 +132,9 @@
EP93XX_TIMER4_RATE);
/* Set up clockevent on timer 3 */
- setup_irq(IRQ_EP93XX_TIMER3, &ep93xx_timer_irq);
+ if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer",
+ &ep93xx_clockevent))
+ pr_err("Failed to request irq %d (ep93xx timer)\n", irq);
clockevents_config_and_register(&ep93xx_clockevent,
EP93XX_TIMER123_RATE,
1,
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 9dab1f5..d2d2497 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -3,26 +3,27 @@
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
-# Configuration options for the EXYNOS
+# Configuration options for the Samsung Exynos
menuconfig ARCH_EXYNOS
- bool "Samsung EXYNOS"
+ bool "Samsung Exynos"
depends on ARCH_MULTI_V7
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select ARM_GIC
+ select EXYNOS_IRQ_COMBINER
select COMMON_CLK_SAMSUNG
+ select EXYNOS_ASV
select EXYNOS_CHIPID
select EXYNOS_THERMAL
select EXYNOS_PMU
select EXYNOS_SROM
select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
select GPIOLIB
- select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 && VIRTUALIZATION
+ select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5
select HAVE_ARM_SCU if SMP
select HAVE_S3C2410_I2C if I2C
- select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL
select PINCTRL_EXYNOS
@@ -40,7 +41,7 @@
select POWER_RESET_SYSCON
select POWER_RESET_SYSCON_POWEROFF
help
- Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
+ Support for Samsung Exynos SoCs
if ARCH_EXYNOS
@@ -50,63 +51,62 @@
Compile in setup memory (init) code for MFC
config ARCH_EXYNOS3
- bool "SAMSUNG EXYNOS3"
+ bool "Samsung Exynos3"
default y
select ARM_CPU_SUSPEND if PM
help
- Samsung EXYNOS3 (Cortex-A7) SoC based systems
+ Samsung Exynos3 (Cortex-A7) SoC based systems
config ARCH_EXYNOS4
- bool "SAMSUNG EXYNOS4"
+ bool "Samsung Exynos4"
default y
select ARM_CPU_SUSPEND if PM_SLEEP
select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
select CPU_EXYNOS4210
select GIC_NON_BANKED
- select MIGHT_HAVE_CACHE_L2X0
help
- Samsung EXYNOS4 (Cortex-A9) SoC based systems
+ Samsung Exynos4 (Cortex-A9) SoC based systems
config ARCH_EXYNOS5
- bool "SAMSUNG EXYNOS5"
+ bool "Samsung Exynos5"
default y
help
- Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems
+ Samsung Exynos5 (Cortex-A15/A7) SoC based systems
-comment "EXYNOS SoCs"
+comment "Exynos SoCs"
config SOC_EXYNOS3250
- bool "SAMSUNG EXYNOS3250"
+ bool "Samsung Exynos3250"
default y
depends on ARCH_EXYNOS3
config CPU_EXYNOS4210
- bool "SAMSUNG EXYNOS4210"
+ bool "Samsung Exynos4210"
default y
depends on ARCH_EXYNOS4
config SOC_EXYNOS4412
- bool "SAMSUNG EXYNOS4412"
+ bool "Samsung Exynos4412"
default y
depends on ARCH_EXYNOS4
config SOC_EXYNOS5250
- bool "SAMSUNG EXYNOS5250"
+ bool "Samsung Exynos5250"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5260
- bool "SAMSUNG EXYNOS5260"
+ bool "Samsung Exynos5260"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5410
- bool "SAMSUNG EXYNOS5410"
+ bool "Samsung Exynos5410"
default y
depends on ARCH_EXYNOS5
config SOC_EXYNOS5420
- bool "SAMSUNG EXYNOS5420"
+ bool "Samsung Exynos5420"
default y
depends on ARCH_EXYNOS5
select EXYNOS_MCPM if SMP
@@ -114,9 +114,10 @@
select ARM_CPU_SUSPEND
config SOC_EXYNOS5800
- bool "SAMSUNG EXYNOS5800"
+ bool "Samsung EXYNOS5800"
default y
depends on SOC_EXYNOS5420
+ select EXYNOS_REGULATOR_COUPLER
config EXYNOS_MCPM
bool
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 0fd3fcf..53fa363 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -3,10 +3,6 @@
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
-
-# Core
-
obj-$(CONFIG_ARCH_EXYNOS) += exynos.o exynos-smc.o firmware.o
obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 56411bb..29eb075 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -3,7 +3,7 @@
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
- * Common Header for EXYNOS machines
+ * Common Header for Exynos machines
*/
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
@@ -24,12 +24,12 @@
#define EXYNOS5800_SOC_ID 0xE5422000
#define EXYNOS5_SOC_MASK 0xFFFFF000
-extern unsigned long samsung_cpu_id;
+extern unsigned long exynos_cpu_id;
#define IS_SAMSUNG_CPU(name, id, mask) \
static inline int is_samsung_##name(void) \
{ \
- return ((samsung_cpu_id & mask) == (id & mask)); \
+ return ((exynos_cpu_id & mask) == (id & mask)); \
}
IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
@@ -147,7 +147,7 @@
extern void exynos_set_delayed_reset_assertion(bool enable);
-extern unsigned int samsung_rev(void);
+extern unsigned int exynos_rev(void);
extern void exynos_core_restart(u32 core_id);
extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr);
extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index f226d4f..83d1d13 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
//
-// SAMSUNG EXYNOS Flattened Device Tree enabled machine
+// Samsung Exynos Flattened Device Tree enabled machine
//
// Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com
@@ -19,11 +19,12 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/map.h>
-#include <plat/cpu.h>
-
#include "common.h"
+#define S3C_ADDR_BASE 0xF6000000
+#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
+#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
+
static struct platform_device exynos_cpuidle = {
.name = "exynos_cpuidle",
#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
@@ -36,6 +37,14 @@
phys_addr_t sysram_base_phys __ro_after_init;
void __iomem *sysram_ns_base_addr __ro_after_init;
+unsigned long exynos_cpu_id;
+static unsigned int exynos_cpu_rev;
+
+unsigned int exynos_rev(void)
+{
+ return exynos_cpu_rev;
+}
+
void __init exynos_sysram_init(void)
{
struct device_node *node;
@@ -88,7 +97,11 @@
of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
/* detect cpu id and rev. */
- s5p_init_cpu(S5P_VA_CHIPID);
+ exynos_cpu_id = readl_relaxed(S5P_VA_CHIPID);
+ exynos_cpu_rev = exynos_cpu_id & 0xFF;
+
+ pr_info("Samsung CPU ID: 0x%08lx\n", exynos_cpu_id);
+
}
/*
@@ -194,9 +207,9 @@
of_fdt_limit_memory(8);
}
-DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
- .l2c_aux_val = 0x3c400001,
- .l2c_aux_mask = 0xc20fffff,
+DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)")
+ .l2c_aux_val = 0x38400000,
+ .l2c_aux_mask = 0xc60fffff,
.smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
.init_early = exynos_firmware_init,
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
deleted file mode 100644
index 22ebe36..0000000
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * EXYNOS - Memory map definitions
- */
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-
-#include <plat/map-s5p.h>
-
-#define EXYNOS_PA_CHIPID 0x10000000
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 0cbbae8..d7fedbb 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -22,8 +22,6 @@
#include <asm/smp_scu.h>
#include <asm/firmware.h>
-#include <mach/map.h>
-
#include "common.h"
extern void exynos4_secondary_startup(void);
@@ -188,7 +186,7 @@
static void __iomem *cpu_boot_reg_base(void)
{
- if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+ if (soc_is_exynos4210() && exynos_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM5;
return sysram_base_addr;
}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 48e7fb3..30f4e55 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -3,7 +3,7 @@
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
-// EXYNOS - Power Management support
+// Exynos - Power Management support
//
// Based on arch/arm/mach-s3c2410/pm.c
// Copyright (c) 2006 Simtec Electronics
@@ -26,18 +26,18 @@
static inline void __iomem *exynos_boot_vector_addr(void)
{
- if (samsung_rev() == EXYNOS4210_REV_1_1)
+ if (exynos_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM7;
- else if (samsung_rev() == EXYNOS4210_REV_1_0)
+ else if (exynos_rev() == EXYNOS4210_REV_1_0)
return sysram_base_addr + 0x24;
return pmu_base_addr + S5P_INFORM0;
}
static inline void __iomem *exynos_boot_vector_flag(void)
{
- if (samsung_rev() == EXYNOS4210_REV_1_1)
+ if (exynos_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM6;
- else if (samsung_rev() == EXYNOS4210_REV_1_0)
+ else if (exynos_rev() == EXYNOS4210_REV_1_0)
return sysram_base_addr + 0x20;
return pmu_base_addr + S5P_INFORM1;
}
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
index 98832e5..5c30feb 100644
--- a/arch/arm/mach-exynos/smc.h
+++ b/arch/arm/mach-exynos/smc.h
@@ -2,7 +2,7 @@
/*
* Copyright (c) 2012 Samsung Electronics.
*
- * EXYNOS - SMC Call
+ * Exynos - SMC Call
*/
#ifndef __ASM_ARCH_EXYNOS_SMC_H
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 6a0d344..3bf14ca 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -3,7 +3,7 @@
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
-// EXYNOS - Suspend support
+// Exynos - Suspend support
//
// Based on arch/arm/mach-s3c2410/pm.c
// Copyright (c) 2006 Simtec Electronics
diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig
index 1730ee8..844aa58 100644
--- a/arch/arm/mach-footbridge/Kconfig
+++ b/arch/arm/mach-footbridge/Kconfig
@@ -22,7 +22,7 @@
select ISA
select ISA_DMA
select FORCE_PCI
- ---help---
+ help
Say Y here if you intend to run this kernel on the Compaq
Personal Server.
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 015f75d..eee095f 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -14,7 +14,6 @@
#include <linux/spinlock.h>
#include <video/vga.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index f76212d..2908c9e 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -101,13 +101,6 @@
return IRQ_HANDLED;
}
-static struct irqaction footbridge_timer_irq = {
- .name = "dc21285_timer1",
- .handler = timer1_interrupt,
- .flags = IRQF_TIMER | IRQF_IRQPOLL,
- .dev_id = &ckevt_dc21285,
-};
-
/*
* Set up timer interrupt.
*/
@@ -118,7 +111,9 @@
clocksource_register_hz(&cksrc_dc21285, rate);
- setup_irq(ce->irq, &footbridge_timer_irq);
+ if (request_irq(ce->irq, timer1_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
+ "dc21285_timer1", &ckevt_dc21285))
+ pr_err("Failed to request irq %d (dc21285_timer1)", ce->irq);
ce->cpumask = cpumask_of(smp_processor_id());
clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index e17ec92..f9713dc 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -31,7 +31,6 @@
PCI_STATUS_PARITY) << 16)
extern int setup_arm_irq(int, struct irqaction *);
-extern void pcibios_report_status(u_int status_mask, int warn);
static unsigned long
dc21285_base_address(struct pci_bus *bus, unsigned int devfn)
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index 88a5539..842ddb4 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -96,11 +96,6 @@
generic_handle_irq(isa_irq);
}
-static struct irqaction irq_cascade = {
- .handler = no_action,
- .name = "cascade",
-};
-
static struct resource pic1_resource = {
.name = "pic1",
.start = 0x20,
@@ -160,7 +155,10 @@
request_resource(&ioport_resource, &pic1_resource);
request_resource(&ioport_resource, &pic2_resource);
- setup_irq(IRQ_ISA_CASCADE, &irq_cascade);
+
+ irq = IRQ_ISA_CASCADE;
+ if (request_irq(irq, no_action, 0, "cascade", NULL))
+ pr_err("Failed to request irq %u (cascade)\n", irq);
irq_set_chained_handler(host_irq, isa_irq_handler);
diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c
index 82f4559..723e3ea 100644
--- a/arch/arm/mach-footbridge/isa-timer.c
+++ b/arch/arm/mach-footbridge/isa-timer.c
@@ -25,17 +25,12 @@
return IRQ_HANDLED;
}
-static struct irqaction pit_timer_irq = {
- .name = "pit",
- .handler = pit_timer_interrupt,
- .flags = IRQF_TIMER | IRQF_IRQPOLL,
- .dev_id = &i8253_clockevent,
-};
-
void __init isa_timer_init(void)
{
clocksource_i8253_init();
- setup_irq(i8253_clockevent.irq, &pit_timer_irq);
+ if (request_irq(i8253_clockevent.irq, pit_timer_interrupt,
+ IRQF_TIMER | IRQF_IRQPOLL, "pit", &i8253_clockevent))
+ pr_err("Failed to request irq %d(pit)\n", i8253_clockevent.irq);
clockevent_i8253_init(false);
}
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 56bf295..db60795 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -5,7 +5,7 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clocksource.h>
-#include <linux/dma-mapping.h>
+#include <linux/dma-map-ops.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/irqchip.h>
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 98338a4..2e980f8 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only
config ARCH_HISI
bool "Hisilicon SoC Support"
- depends on ARCH_MULTI_V7
+ depends on ARCH_MULTI_V7 || ARCH_MULTI_V5
select ARM_AMBA
- select ARM_GIC
+ select ARM_GIC if ARCH_MULTI_V7
select ARM_TIMER_SP804
select POWER_RESET
select POWER_RESET_HISI
@@ -25,13 +25,13 @@
Support for Hisilicon Hi36xx SoC family
config ARCH_HIP01
- bool "Hisilicon HIP01 family"
- depends on ARCH_MULTI_V7
- select HAVE_ARM_SCU if SMP
- select HAVE_ARM_TWD if SMP
- select ARM_GLOBAL_TIMER
- help
- Support for Hisilicon HIP01 SoC family
+ bool "Hisilicon HIP01 family"
+ depends on ARCH_MULTI_V7
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if SMP
+ select ARM_GLOBAL_TIMER
+ help
+ Support for Hisilicon HIP01 SoC family
config ARCH_HIP04
bool "Hisilicon HiP04 Cortex A15 family"
@@ -54,6 +54,14 @@
select PINCTRL_SINGLE
help
Support for Hisilicon HIX5HD2 SoC family
+
+config ARCH_SD5203
+ bool "Hisilicon SD5203 family"
+ depends on ARCH_MULTI_V5
+ select DW_APB_ICTL
+ help
+ Support for Hisilicon SD5203 SoC family
+
endmenu
endif
diff --git a/arch/arm/mach-imx/3ds_debugboard.c b/arch/arm/mach-imx/3ds_debugboard.c
deleted file mode 100644
index 0e01800..0000000
--- a/arch/arm/mach-imx/3ds_debugboard.c
+++ /dev/null
@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
- */
-
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/module.h>
-#include <linux/smsc911x.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include "3ds_debugboard.h"
-#include "hardware.h"
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR(n) (n + 0x0)
-/* External UART */
-#define UARTA_BASE_ADDR(n) (n + 0x8000)
-#define UARTB_BASE_ADDR(n) (n + 0x10000)
-
-#define BOARD_IO_ADDR(n) (n + 0x20000)
-/* LED switchs */
-#define LED_SWITCH_REG 0x00
-/* buttons */
-#define SWITCH_BUTTONS_REG 0x08
-/* status, interrupt */
-#define INTR_STATUS_REG 0x10
-#define INTR_MASK_REG 0x38
-#define INTR_RESET_REG 0x20
-/* magic word for debug CPLD */
-#define MAGIC_NUMBER1_REG 0x40
-#define MAGIC_NUMBER2_REG 0x48
-/* CPLD code version */
-#define CPLD_CODE_VER_REG 0x50
-/* magic word for debug CPLD */
-#define MAGIC_NUMBER3_REG 0x58
-/* module reset register*/
-#define MODULE_RESET_REG 0x60
-/* CPU ID and Personality ID */
-#define MCU_BOARD_ID_REG 0x68
-
-#define MXC_MAX_EXP_IO_LINES 16
-
-/* interrupts like external uart , external ethernet etc*/
-#define EXPIO_INT_ENET 0
-#define EXPIO_INT_XUART_A 1
-#define EXPIO_INT_XUART_B 2
-#define EXPIO_INT_BUTTON_A 3
-#define EXPIO_INT_BUTTON_B 4
-
-static void __iomem *brd_io;
-static struct irq_domain *domain;
-
-static struct resource smsc911x_resources[] = {
- {
- .flags = IORESOURCE_MEM,
- } , {
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
-};
-
-static struct platform_device smsc_lan9217_device = {
- .name = "smsc911x",
- .id = -1,
- .dev = {
- .platform_data = &smsc911x_config,
- },
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
-};
-
-static void mxc_expio_irq_handler(struct irq_desc *desc)
-{
- u32 imr_val;
- u32 int_valid;
- u32 expio_irq;
-
- /* irq = gpio irq number */
- desc->irq_data.chip->irq_mask(&desc->irq_data);
-
- imr_val = imx_readw(brd_io + INTR_MASK_REG);
- int_valid = imx_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
-
- expio_irq = 0;
- for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
- if ((int_valid & 1) == 0)
- continue;
- generic_handle_irq(irq_find_mapping(domain, expio_irq));
- }
-
- desc->irq_data.chip->irq_ack(&desc->irq_data);
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * Irq is an expio virtual irq number
- */
-static void expio_mask_irq(struct irq_data *d)
-{
- u16 reg;
- u32 expio = d->hwirq;
-
- reg = imx_readw(brd_io + INTR_MASK_REG);
- reg |= (1 << expio);
- imx_writew(reg, brd_io + INTR_MASK_REG);
-}
-
-static void expio_ack_irq(struct irq_data *d)
-{
- u32 expio = d->hwirq;
-
- imx_writew(1 << expio, brd_io + INTR_RESET_REG);
- imx_writew(0, brd_io + INTR_RESET_REG);
- expio_mask_irq(d);
-}
-
-static void expio_unmask_irq(struct irq_data *d)
-{
- u16 reg;
- u32 expio = d->hwirq;
-
- reg = imx_readw(brd_io + INTR_MASK_REG);
- reg &= ~(1 << expio);
- imx_writew(reg, brd_io + INTR_MASK_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
- .irq_ack = expio_ack_irq,
- .irq_mask = expio_mask_irq,
- .irq_unmask = expio_unmask_irq,
-};
-
-static struct regulator_consumer_supply dummy_supplies[] = {
- REGULATOR_SUPPLY("vdd33a", "smsc911x"),
- REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
-int __init mxc_expio_init(u32 base, u32 intr_gpio)
-{
- u32 p_irq = gpio_to_irq(intr_gpio);
- int irq_base;
- int i;
-
- brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
- if (brd_io == NULL)
- return -ENOMEM;
-
- if ((imx_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
- (imx_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
- (imx_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
- pr_info("3-Stack Debug board not detected\n");
- iounmap(brd_io);
- brd_io = NULL;
- return -ENODEV;
- }
-
- pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
- readw(brd_io + CPLD_CODE_VER_REG));
-
- /*
- * Configure INT line as GPIO input
- */
- gpio_request(intr_gpio, "expio_pirq");
- gpio_direction_input(intr_gpio);
-
- /* disable the interrupt and clear the status */
- imx_writew(0, brd_io + INTR_MASK_REG);
- imx_writew(0xFFFF, brd_io + INTR_RESET_REG);
- imx_writew(0, brd_io + INTR_RESET_REG);
- imx_writew(0x1F, brd_io + INTR_MASK_REG);
-
- irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
- WARN_ON(irq_base < 0);
-
- domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
- &irq_domain_simple_ops, NULL);
- WARN_ON(!domain);
-
- for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
- irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
- irq_clear_status_flags(i, IRQ_NOREQUEST);
- }
- irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
- irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
-
- /* Register Lan device on the debugboard */
- regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
- smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
- smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
- smsc911x_resources[1].start = irq_find_mapping(domain, EXPIO_INT_ENET);
- smsc911x_resources[1].end = irq_find_mapping(domain, EXPIO_INT_ENET);
- platform_device_register(&smsc_lan9217_device);
-
- return 0;
-}
diff --git a/arch/arm/mach-imx/3ds_debugboard.h b/arch/arm/mach-imx/3ds_debugboard.h
deleted file mode 100644
index a4d04d0..0000000
--- a/arch/arm/mach-imx/3ds_debugboard.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#ifndef __ASM_ARCH_MXC_3DS_DB_H__
-#define __ASM_ARCH_MXC_3DS_DB_H__
-
-extern int __init mxc_expio_init(u32 base, u32 intr_gpio);
-
-#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 95584ee..5290278 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -47,371 +47,26 @@
def_bool y if SMP
select ARCH_HAS_RESET_CONTROLLER
-config IMX_HAVE_IOMUX_V1
- bool
-
-config ARCH_MXC_IOMUX_V3
- bool
-
-config SOC_IMX21
- bool
- select CPU_ARM926T
- select IMX_HAVE_IOMUX_V1
- select MXC_AVIC
-
-config SOC_IMX27
- bool
- select CPU_ARM926T
- select IMX_HAVE_IOMUX_V1
- select MXC_AVIC
- select PINCTRL_IMX27
-
-config SOC_IMX31
- bool
- select CPU_V6
- select MXC_AVIC
-
-config SOC_IMX35
- bool
- select ARCH_MXC_IOMUX_V3
- select MXC_AVIC
- select PINCTRL_IMX35
-
-if ARCH_MULTI_V5
-
-comment "MX21 platforms:"
-
-config MACH_MX21ADS
- bool "MX21ADS platform"
- select IMX_HAVE_PLATFORM_IMX_FB
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_MXC_NAND
- select SOC_IMX21
- help
- Include support for MX21ADS platform. This includes specific
- configurations for the board and its peripherals.
-
-comment "MX27 platforms:"
-
-config MACH_MX27ADS
- bool "MX27ADS platform"
- select IMX_HAVE_PLATFORM_IMX_FB
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_MXC_W1
- select SOC_IMX27
- help
- Include support for MX27ADS platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX27_3DS
- bool "MX27PDK platform"
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_FB
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_KEYPAD
- select IMX_HAVE_PLATFORM_IMX_SSI
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MX2_CAMERA
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_SPI_IMX
- select MXC_DEBUG_BOARD
- select USB_ULPI_VIEWPORT if USB_ULPI
- select SOC_IMX27
- help
- Include support for MX27PDK platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_IMX27_VISSTRIM_M10
- bool "Vista Silicon i.MX27 Visstrim_m10"
- select IMX_HAVE_PLATFORM_GPIO_KEYS
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_SSI
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MX2_CAMERA
- select IMX_HAVE_PLATFORM_MX2_EMMA
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select LEDS_GPIO_REGISTER
- select SOC_IMX27
- help
- Include support for Visstrim_m10 platform and its different variants.
- This includes specific configurations for the board and its
- peripherals.
-
-config MACH_PCA100
- bool "Phytec phyCARD-s (pca100)"
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_FB
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_SSI
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_MXC_W1
- select IMX_HAVE_PLATFORM_SPI_IMX
- select USB_ULPI_VIEWPORT if USB_ULPI
- select SOC_IMX27
- help
- Include support for phyCARD-s (aka pca100) platform. This
- includes specific configurations for the module and its peripherals.
-
-config MACH_IMX27_DT
- bool "Support i.MX27 platforms from device tree"
- select SOC_IMX27
- help
- Include support for Freescale i.MX27 based platforms
- using the device tree for discovery
-
-endif
-
if ARCH_MULTI_V6
-comment "MX31 platforms:"
+comment "ARM1136 platforms"
-config MACH_MX31ADS
- bool "Support MX31ADS platforms"
- default y
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_SSI
- select IMX_HAVE_PLATFORM_IMX_UART
- select SOC_IMX31
+config SOC_IMX31
+ bool "i.MX31 support"
+ select CPU_V6
+ select MXC_AVIC
help
- Include support for MX31ADS platform. This includes specific
- configurations for the board and its peripherals.
+ This enables support for Freescale i.MX31 processor
-config MACH_MX31ADS_WM1133_EV1
- bool "Support Wolfson Microelectronics 1133-EV1 module"
- depends on MACH_MX31ADS
- depends on MFD_WM8350_I2C
- depends on REGULATOR_WM8350 = y
+config SOC_IMX35
+ bool "i.MX35 support"
+ select MXC_AVIC
+ select PINCTRL_IMX35
help
- Include support for the Wolfson Microelectronics 1133-EV1 PMU
- and audio module for the MX31ADS platform.
-
-config MACH_MX31LILLY
- bool "Support MX31 LILLY-1131 platforms (INCO startec)"
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_IPU_CORE
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_SPI_IMX
- select USB_ULPI_VIEWPORT if USB_ULPI
- select SOC_IMX31
- help
- Include support for mx31 based LILLY1131 modules. This includes
- specific configurations for the board and its peripherals.
-
-config MACH_MX31LITE
- bool "Support MX31 LITEKIT (LogicPD)"
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_MXC_RTC
- select IMX_HAVE_PLATFORM_SPI_IMX
- select LEDS_GPIO_REGISTER
- select USB_ULPI_VIEWPORT if USB_ULPI
- select SOC_IMX31
- help
- Include support for MX31 LITEKIT platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_PCM037
- bool "Support Phytec pcm037 (i.MX31) platforms"
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_IPU_CORE
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_MXC_W1
- select USB_ULPI_VIEWPORT if USB_ULPI
- select SOC_IMX31
- help
- Include support for Phytec pcm037 platform. This includes
- specific configurations for the board and its peripherals.
-
-config MACH_PCM037_EET
- bool "Support pcm037 EET board extensions"
- depends on MACH_PCM037
- select IMX_HAVE_PLATFORM_GPIO_KEYS
- select IMX_HAVE_PLATFORM_SPI_IMX
- help
- Add support for PCM037 EET baseboard extensions. If you are using the
- OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
- command-line parameter.
-
-config MACH_MX31_3DS
- bool "Support MX31PDK (3DS)"
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_KEYPAD
- select IMX_HAVE_PLATFORM_IMX_SSI
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_IPU_CORE
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SPI_IMX
- select MXC_DEBUG_BOARD
- select USB_ULPI_VIEWPORT if USB_ULPI
- select SOC_IMX31
- help
- Include support for MX31PDK (3DS) platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX31_3DS_MXC_NAND_USE_BBT
- bool "Make the MXC NAND driver use the in flash Bad Block Table"
- depends on MACH_MX31_3DS
- depends on MTD_NAND_MXC
- help
- Enable this if you want that the MXC NAND driver uses the in flash
- Bad Block Table to know what blocks are bad instead of scanning the
- entire flash looking for bad block markers.
-
-config MACH_MX31MOBOARD
- bool "Support mx31moboard platforms (EPFL Mobots group)"
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_SSI
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_IPU_CORE
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_SPI_IMX
- select LEDS_GPIO_REGISTER
- select USB_ULPI_VIEWPORT if USB_ULPI
- select SOC_IMX31
- help
- Include support for mx31moboard platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_QONG
- bool "Support Dave/DENX QongEVB-LITE platform"
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_UART
- select SOC_IMX31
- help
- Include support for Dave/DENX QongEVB-LITE platform. This includes
- specific configurations for the board and its peripherals.
-
-config MACH_ARMADILLO5X0
- bool "Support Atmark Armadillo-500 Development Base Board"
- select IMX_HAVE_PLATFORM_GPIO_KEYS
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_IPU_CORE
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_MXC_NAND
- select USB_ULPI_VIEWPORT if USB_ULPI
- select SOC_IMX31
- help
- Include support for Atmark Armadillo-500 platform. This includes
- specific configurations for the board and its peripherals.
-
-config MACH_KZM_ARM11_01
- bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
- select IMX_HAVE_PLATFORM_IMX_UART
- select SOC_IMX31
- help
- Include support for KZM-ARM11-01. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_BUG
- bool "Support Buglabs BUGBase platform"
- default y
- select IMX_HAVE_PLATFORM_IMX_UART
- select SOC_IMX31
- help
- Include support for BUGBase 1.3 platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_IMX31_DT
- bool "Support i.MX31 platforms from device tree"
- select SOC_IMX31
- help
- Include support for Freescale i.MX31 based platforms
- using the device tree for discovery.
-
-comment "MX35 platforms:"
-
-config MACH_IMX35_DT
- bool "Support i.MX35 platforms from device tree"
- select SOC_IMX35
- help
- Include support for Freescale i.MX35 based platforms
- using the device tree for discovery.
-
-config MACH_PCM043
- bool "Support Phytec pcm043 (i.MX35) platforms"
- select IMX_HAVE_PLATFORM_FLEXCAN
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_SSI
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_IPU_CORE
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select USB_ULPI_VIEWPORT if USB_ULPI
- select SOC_IMX35
- help
- Include support for Phytec pcm043 platform. This includes
- specific configurations for the board and its peripherals.
-
-config MACH_MX35_3DS
- bool "Support MX35PDK platform"
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_FB
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_IPU_CORE
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_MXC_RTC
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select MXC_DEBUG_BOARD
- select SOC_IMX35
- help
- Include support for MX35PDK platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_VPR200
- bool "Support VPR200 platform"
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_GPIO_KEYS
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_IPU_CORE
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select SOC_IMX35
- help
- Include support for VPR200 platform. This includes specific
- configurations for the board and its peripherals.
+ This enables support for Freescale i.MX31 processor
endif
-comment "Device tree only"
-
if ARCH_MULTI_V4T
config SOC_IMX1
@@ -428,12 +83,20 @@
config SOC_IMX25
bool "i.MX25 support"
- select ARCH_MXC_IOMUX_V3
select CPU_ARM926T
select MXC_AVIC
select PINCTRL_IMX25
help
This enables support for Freescale i.MX25 processor
+
+config SOC_IMX27
+ bool "i.MX27 support"
+ select CPU_ARM926T
+ select MXC_AVIC
+ select PINCTRL_IMX27
+ help
+ This enables support for Freescale i.MX27 processor
+
endif
if ARCH_MULTI_V7
@@ -471,8 +134,6 @@
config SOC_IMX6
bool
select ARM_CPU_SUSPEND if (PM || CPU_IDLE)
- select ARM_ERRATA_754322
- select ARM_ERRATA_775420
select ARM_GIC
select HAVE_IMX_ANATOP
select HAVE_IMX_GPC
@@ -484,6 +145,8 @@
config SOC_IMX6Q
bool "i.MX6 Quad/DualLite support"
select ARM_ERRATA_764369 if SMP
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD
select PINCTRL_IMX6Q
@@ -494,6 +157,8 @@
config SOC_IMX6SL
bool "i.MX6 SoloLite support"
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
select PINCTRL_IMX6SL
select SOC_IMX6
@@ -502,6 +167,8 @@
config SOC_IMX6SLL
bool "i.MX6 SoloLiteLite support"
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
select PINCTRL_IMX6SLL
select SOC_IMX6
@@ -510,6 +177,8 @@
config SOC_IMX6SX
bool "i.MX6 SoloX support"
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
select PINCTRL_IMX6SX
select SOC_IMX6
@@ -535,10 +204,10 @@
endif
-comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
-
if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
+
config SOC_IMX7D_CA7
bool
select ARM_GIC
@@ -601,6 +270,4 @@
endif
-source "arch/arm/mach-imx/devices/Kconfig"
-
endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e7364e6..9cebd36 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,22 +1,16 @@
# SPDX-License-Identifier: GPL-2.0
obj-y := cpu.o system.o irq-common.o
-obj-$(CONFIG_SOC_IMX21) += mm-imx21.o
-
obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
-obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
-obj-$(CONFIG_SOC_IMX27) += mm-imx27.o ehci-imx27.o
+obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o
-obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o iomux-imx31.o ehci-imx31.o
-obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o ehci-imx35.o
+obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o mach-imx31.o
+obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o
imx5-pm-$(CONFIG_PM) += pm-imx5.o
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y)
-obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
-obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
-
obj-$(CONFIG_MXC_TZIC) += tzic.o
obj-$(CONFIG_MXC_AVIC) += avic.o
@@ -37,37 +31,6 @@
obj-y += ssi-fiq-ksym.o
endif
-# i.MX21 based machines
-obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
-
-# i.MX27 based machines
-obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
-obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
-obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
-obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
-obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
-
-# i.MX31 based machines
-obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
-obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
-obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
-obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
-obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
-obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
-obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
- mx31moboard-marxbot.o mx31moboard-smartbot.o
-obj-$(CONFIG_MACH_QONG) += mach-qong.o
-obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
-obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
-obj-$(CONFIG_MACH_BUG) += mach-bug.o
-obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o
-
-# i.MX35 based machines
-obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
-obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
-obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
-obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
-
obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
@@ -105,5 +68,3 @@
obj-$(CONFIG_SOC_VF610) += mach-vf610.o
obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
-
-obj-y += devices/
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 777d8c2..7bb47eb 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -19,8 +19,6 @@
#define ANADIG_REG_2P5 0x130
#define ANADIG_REG_CORE 0x140
#define ANADIG_ANA_MISC0 0x150
-#define ANADIG_USB1_CHRG_DETECT 0x1b0
-#define ANADIG_USB2_CHRG_DETECT 0x210
#define ANADIG_DIGPROG 0x260
#define ANADIG_DIGPROG_IMX6SL 0x280
#define ANADIG_DIGPROG_IMX7D 0x800
@@ -33,8 +31,6 @@
#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
-#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
-#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
static struct regmap *anatop;
@@ -93,22 +89,11 @@
if (cpu_is_imx6sl())
imx_anatop_disconnect_high_snvs(false);
-
-}
-
-static void imx_anatop_usb_chrg_detect_disable(void)
-{
- regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
- BM_ANADIG_USB_CHRG_DETECT_EN_B
- | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
- regmap_write(anatop, ANADIG_USB2_CHRG_DETECT,
- BM_ANADIG_USB_CHRG_DETECT_EN_B |
- BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
}
void __init imx_init_revision_from_anatop(void)
{
- struct device_node *np;
+ struct device_node *np, *src_np;
void __iomem *anatop_base;
unsigned int revision;
u32 digprog;
@@ -149,9 +134,10 @@
void __iomem *src_base;
u32 sbmr2;
- np = of_find_compatible_node(NULL, NULL,
+ src_np = of_find_compatible_node(NULL, NULL,
"fsl,imx6ul-src");
- src_base = of_iomap(np, 0);
+ src_base = of_iomap(src_np, 0);
+ of_node_put(src_np);
WARN_ON(!src_base);
sbmr2 = readl_relaxed(src_base + SRC_SBMR2);
iounmap(src_base);
@@ -163,6 +149,7 @@
}
}
}
+ of_node_put(np);
mxc_set_cpu_type(digprog >> 16 & 0xff);
imx_set_soc_revision(revision);
@@ -171,10 +158,6 @@
void __init imx_anatop_init(void)
{
anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
- if (IS_ERR(anatop)) {
+ if (IS_ERR(anatop))
pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
- return;
- }
-
- imx_anatop_usb_chrg_detect_disable();
}
diff --git a/arch/arm/mach-imx/board-mx31lilly.h b/arch/arm/mach-imx/board-mx31lilly.h
deleted file mode 100644
index 3508c59..0000000
--- a/arch/arm/mach-imx/board-mx31lilly.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * Based on code for mobots boards,
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
-#define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
-
-#ifndef __ASSEMBLY__
-
-enum mx31lilly_boards {
- MX31LILLY_NOBOARD = 0,
- MX31LILLY_DB = 1,
-};
-
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls the baseboard's init function.
- */
-
-extern void mx31lilly_db_init(void);
-
-#endif
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ */
diff --git a/arch/arm/mach-imx/board-mx31lite.h b/arch/arm/mach-imx/board-mx31lite.h
deleted file mode 100644
index 7d7c621..0000000
--- a/arch/arm/mach-imx/board-mx31lite.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * Based on code for mobots boards,
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
-#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
-
-#ifndef __ASSEMBLY__
-
-enum mx31lite_boards {
- MX31LITE_NOBOARD = 0,
- MX31LITE_DB = 1,
-};
-
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls the baseboard's init function.
- */
-
-extern void mx31lite_db_init(void);
-
-#endif
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
diff --git a/arch/arm/mach-imx/board-mx31moboard.h b/arch/arm/mach-imx/board-mx31moboard.h
deleted file mode 100644
index 6f3ff4d..0000000
--- a/arch/arm/mach-imx/board-mx31moboard.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
-#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
-
-#ifndef __ASSEMBLY__
-
-enum mx31moboard_boards {
- MX31NOBOARD = 0,
- MX31DEVBOARD = 1,
- MX31MARXBOT = 2,
- MX31SMARTBOT = 3,
- MX31EYEBOT = 4,
-};
-
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls the baseboard's init function.
- */
-
-extern void mx31moboard_devboard_init(void);
-extern void mx31moboard_marxbot_init(void);
-extern void mx31moboard_smartbot_init(int board);
-
-#endif
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5aa5796..2d76e2c 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -17,29 +17,14 @@
enum mxc_cpu_pwr_mode;
struct of_device_id;
-void mx21_map_io(void);
-void mx27_map_io(void);
void mx31_map_io(void);
void mx35_map_io(void);
void imx21_init_early(void);
-void imx27_init_early(void);
void imx31_init_early(void);
void imx35_init_early(void);
void mxc_init_irq(void __iomem *);
-void mx21_init_irq(void);
-void mx27_init_irq(void);
void mx31_init_irq(void);
void mx35_init_irq(void);
-void imx21_soc_init(void);
-void imx27_soc_init(void);
-void imx31_soc_init(void);
-void imx35_soc_init(void);
-int mx21_clocks_init(unsigned long lref, unsigned long fref);
-int mx27_clocks_init(unsigned long fref);
-int mx31_clocks_init(unsigned long fref);
-int mx35_clocks_init(void);
-struct platform_device *mxc_register_gpio(char *name, int id,
- resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
void mxc_set_cpu_type(unsigned int type);
void mxc_restart(enum reboot_mode, const char *);
void mxc_arch_reset_init(void __iomem *);
@@ -49,7 +34,6 @@
int mxc_device_init(void);
void imx_set_soc_revision(unsigned int rev);
void imx_init_revision_from_anatop(void);
-struct device *imx_soc_device_init(void);
void imx6_enable_rbc(bool enable);
void imx_gpc_check_dt(void);
void imx_gpc_set_arm_power_in_lpm(bool power_off);
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index a969aa7..bf70e13 100644
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -9,6 +9,7 @@
*/
#include <linux/io.h>
+#include <linux/of_address.h>
#include <linux/module.h>
#include "hardware.h"
@@ -17,16 +18,23 @@
static int mx27_cpu_partnumber;
#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
+#define SYSCTRL_OFFSET 0x800 /* Offset from CCM base address */
static int mx27_read_cpu_rev(void)
{
+ void __iomem *ccm_base;
+ struct device_node *np;
u32 val;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
+ ccm_base = of_iomap(np, 0);
+ BUG_ON(!ccm_base);
/*
* now we have access to the IO registers. As we need
* the silicon revision very early we read it here to
* avoid any further hooks
*/
- val = imx_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID));
+ val = imx_readl(ccm_base + SYSCTRL_OFFSET + SYS_CHIP_ID);
mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF);
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
index 3ee684b..b9c24b8 100644
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -6,6 +6,7 @@
*/
#include <linux/module.h>
+#include <linux/of_address.h>
#include <linux/io.h>
#include "common.h"
@@ -32,10 +33,16 @@
static int mx31_read_cpu_rev(void)
{
+ void __iomem *iim_base;
+ struct device_node *np;
u32 i, srev;
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
+ iim_base = of_iomap(np, 0);
+ BUG_ON(!iim_base);
+
/* read SREV register from IIM module */
- srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
+ srev = imx_readl(iim_base + MXC_IIMSREV);
srev &= 0xff;
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c
index ebb3cda..80e7d8a 100644
--- a/arch/arm/mach-imx/cpu-imx35.c
+++ b/arch/arm/mach-imx/cpu-imx35.c
@@ -5,6 +5,7 @@
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*/
#include <linux/module.h>
+#include <linux/of_address.h>
#include <linux/io.h>
#include "hardware.h"
@@ -14,9 +15,15 @@
static int mx35_read_cpu_rev(void)
{
+ void __iomem *iim_base;
+ struct device_node *np;
u32 rev;
- rev = imx_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx35-iim");
+ iim_base = of_iomap(np, 0);
+ BUG_ON(!iim_base);
+
+ rev = imx_readl(iim_base + MXC_IIMSREV);
switch (rev) {
case 0x00:
return IMX_CHIP_REVISION_1_0;
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 0b137ee..65c7224 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -4,8 +4,6 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/slab.h>
-#include <linux/sys_soc.h>
#include "hardware.h"
#include "common.h"
@@ -72,102 +70,3 @@
imx_set_aips(aips_base_addr);
}
}
-
-struct device * __init imx_soc_device_init(void)
-{
- struct soc_device_attribute *soc_dev_attr;
- struct soc_device *soc_dev;
- struct device_node *root;
- const char *soc_id;
- int ret;
-
- soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
- if (!soc_dev_attr)
- return NULL;
-
- soc_dev_attr->family = "Freescale i.MX";
-
- root = of_find_node_by_path("/");
- ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
- of_node_put(root);
- if (ret)
- goto free_soc;
-
- switch (__mxc_cpu_type) {
- case MXC_CPU_MX1:
- soc_id = "i.MX1";
- break;
- case MXC_CPU_MX21:
- soc_id = "i.MX21";
- break;
- case MXC_CPU_MX25:
- soc_id = "i.MX25";
- break;
- case MXC_CPU_MX27:
- soc_id = "i.MX27";
- break;
- case MXC_CPU_MX31:
- soc_id = "i.MX31";
- break;
- case MXC_CPU_MX35:
- soc_id = "i.MX35";
- break;
- case MXC_CPU_MX51:
- soc_id = "i.MX51";
- break;
- case MXC_CPU_MX53:
- soc_id = "i.MX53";
- break;
- case MXC_CPU_IMX6SL:
- soc_id = "i.MX6SL";
- break;
- case MXC_CPU_IMX6DL:
- soc_id = "i.MX6DL";
- break;
- case MXC_CPU_IMX6SX:
- soc_id = "i.MX6SX";
- break;
- case MXC_CPU_IMX6Q:
- soc_id = "i.MX6Q";
- break;
- case MXC_CPU_IMX6UL:
- soc_id = "i.MX6UL";
- break;
- case MXC_CPU_IMX6ULL:
- soc_id = "i.MX6ULL";
- break;
- case MXC_CPU_IMX6ULZ:
- soc_id = "i.MX6ULZ";
- break;
- case MXC_CPU_IMX6SLL:
- soc_id = "i.MX6SLL";
- break;
- case MXC_CPU_IMX7D:
- soc_id = "i.MX7D";
- break;
- case MXC_CPU_IMX7ULP:
- soc_id = "i.MX7ULP";
- break;
- default:
- soc_id = "Unknown";
- }
- soc_dev_attr->soc_id = soc_id;
-
- soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
- (imx_soc_revision >> 4) & 0xf,
- imx_soc_revision & 0xf);
- if (!soc_dev_attr->revision)
- goto free_soc;
-
- soc_dev = soc_device_register(soc_dev_attr);
- if (IS_ERR(soc_dev))
- goto free_rev;
-
- return soc_device_to_device(soc_dev);
-
-free_rev:
- kfree(soc_dev_attr->revision);
-free_soc:
- kfree(soc_dev_attr);
- return NULL;
-}
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 39a7d93..094337d 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -24,7 +24,9 @@
imx6_set_lpm(WAIT_UNCLOCKED);
raw_spin_unlock(&cpuidle_lock);
+ rcu_idle_enter();
cpu_do_idle();
+ rcu_idle_exit();
raw_spin_lock(&cpuidle_lock);
if (num_idle_cpus-- == num_online_cpus())
@@ -44,7 +46,7 @@
{
.exit_latency = 50,
.target_residency = 75,
- .flags = CPUIDLE_FLAG_TIMER_STOP,
+ .flags = CPUIDLE_FLAG_TIMER_STOP | CPUIDLE_FLAG_RCU_IDLE,
.enter = imx6q_enter_wait,
.name = "WAIT",
.desc = "Clock off",
@@ -62,13 +64,13 @@
*/
void imx6q_cpuidle_fec_irqs_used(void)
{
- imx6q_cpuidle_driver.states[1].disabled = true;
+ cpuidle_driver_state_disabled(&imx6q_cpuidle_driver, 1, true);
}
EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_used);
void imx6q_cpuidle_fec_irqs_unused(void)
{
- imx6q_cpuidle_driver.states[1].disabled = false;
+ cpuidle_driver_state_disabled(&imx6q_cpuidle_driver, 1, false);
}
EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_unused);
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
deleted file mode 100644
index 3679d1d..0000000
--- a/arch/arm/mach-imx/devices-imx21.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "devices/devices-common.h"
-
-extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
-#define imx21_add_imx21_hcd(pdata) \
- imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
-
-extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data;
-#define imx21_add_imx2_wdt() \
- imx_add_imx2_wdt(&imx21_imx2_wdt_data)
-
-extern const struct imx_imx_fb_data imx21_imx_fb_data;
-#define imx21_add_imx_fb(pdata) \
- imx_add_imx_fb(&imx21_imx_fb_data, pdata)
-
-extern const struct imx_imx_i2c_data imx21_imx_i2c_data;
-#define imx21_add_imx_i2c(pdata) \
- imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
-
-extern const struct imx_imx_keypad_data imx21_imx_keypad_data;
-#define imx21_add_imx_keypad(pdata) \
- imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
-
-extern const struct imx_imx_ssi_data imx21_imx_ssi_data[];
-#define imx21_add_imx_ssi(id, pdata) \
- imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[];
-#define imx21_add_imx_uart(id, pdata) \
- imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
-#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata)
-#define imx21_add_imx_uart1(pdata) imx21_add_imx_uart(1, pdata)
-#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
-#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
-
-extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[];
-#define imx21_add_mxc_mmc(id, pdata) \
- imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
-
-extern const struct imx_mxc_nand_data imx21_mxc_nand_data;
-#define imx21_add_mxc_nand(pdata) \
- imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
-
-extern const struct imx_mxc_w1_data imx21_mxc_w1_data;
-#define imx21_add_mxc_w1() \
- imx_add_mxc_w1(&imx21_mxc_w1_data)
-
-extern const struct imx_spi_imx_data imx21_cspi_data[];
-#define imx21_add_cspi(id, pdata) \
- imx_add_spi_imx(&imx21_cspi_data[id], pdata)
-#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata)
-#define imx21_add_spi_imx1(pdata) imx21_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
deleted file mode 100644
index f89f4ae..0000000
--- a/arch/arm/mach-imx/devices-imx27.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "devices/devices-common.h"
-
-extern const struct imx_fec_data imx27_fec_data;
-#define imx27_add_fec(pdata) \
- imx_add_fec(&imx27_fec_data, pdata)
-
-extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
-#define imx27_add_fsl_usb2_udc(pdata) \
- imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
-
-extern const struct imx_imx27_coda_data imx27_coda_data;
-#define imx27_add_coda() \
- imx_add_imx27_coda(&imx27_coda_data)
-
-extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
-#define imx27_add_imx2_wdt() \
- imx_add_imx2_wdt(&imx27_imx2_wdt_data)
-
-extern const struct imx_imx_fb_data imx27_imx_fb_data;
-#define imx27_add_imx_fb(pdata) \
- imx_add_imx_fb(&imx27_imx_fb_data, pdata)
-
-extern const struct imx_imx_i2c_data imx27_imx_i2c_data[];
-#define imx27_add_imx_i2c(id, pdata) \
- imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
-
-extern const struct imx_imx_keypad_data imx27_imx_keypad_data;
-#define imx27_add_imx_keypad(pdata) \
- imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
-
-extern const struct imx_imx_ssi_data imx27_imx_ssi_data[];
-#define imx27_add_imx_ssi(id, pdata) \
- imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
-#define imx27_add_imx_uart(id, pdata) \
- imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
-#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata)
-#define imx27_add_imx_uart1(pdata) imx27_add_imx_uart(1, pdata)
-#define imx27_add_imx_uart2(pdata) imx27_add_imx_uart(2, pdata)
-#define imx27_add_imx_uart3(pdata) imx27_add_imx_uart(3, pdata)
-#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
-#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
-
-extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
-#define imx27_add_mx2_camera(pdata) \
- imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
-
-extern const struct imx_mx2_emma_data imx27_mx2_emmaprp_data;
-#define imx27_add_mx2_emmaprp() \
- imx_add_mx2_emmaprp(&imx27_mx2_emmaprp_data)
-
-extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
-#define imx27_add_mxc_ehci_otg(pdata) \
- imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[];
-#define imx27_add_mxc_ehci_hs(id, pdata) \
- imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
-
-extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[];
-#define imx27_add_mxc_mmc(id, pdata) \
- imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
-
-extern const struct imx_mxc_nand_data imx27_mxc_nand_data;
-#define imx27_add_mxc_nand(pdata) \
- imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
-
-extern const struct imx_mxc_w1_data imx27_mxc_w1_data;
-#define imx27_add_mxc_w1() \
- imx_add_mxc_w1(&imx27_mxc_w1_data)
-
-extern const struct imx_spi_imx_data imx27_cspi_data[];
-#define imx27_add_cspi(id, pdata) \
- imx_add_spi_imx(&imx27_cspi_data[id], pdata)
-#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata)
-#define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata)
-#define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata)
-
-extern const struct imx_pata_imx_data imx27_pata_imx_data;
-#define imx27_add_pata_imx() \
- imx_add_pata_imx(&imx27_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
deleted file mode 100644
index 5a4ba35..0000000
--- a/arch/arm/mach-imx/devices-imx31.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "devices/devices-common.h"
-
-extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
-#define imx31_add_fsl_usb2_udc(pdata) \
- imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
-
-extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data;
-#define imx31_add_imx2_wdt() \
- imx_add_imx2_wdt(&imx31_imx2_wdt_data)
-
-extern const struct imx_imx_i2c_data imx31_imx_i2c_data[];
-#define imx31_add_imx_i2c(id, pdata) \
- imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
-#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata)
-#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
-#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
-
-extern const struct imx_imx_keypad_data imx31_imx_keypad_data;
-#define imx31_add_imx_keypad(pdata) \
- imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
-
-extern const struct imx_imx_ssi_data imx31_imx_ssi_data[];
-#define imx31_add_imx_ssi(id, pdata) \
- imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
-#define imx31_add_imx_uart(id, pdata) \
- imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
-#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata)
-#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata)
-#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata)
-#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
-#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
-
-extern const struct imx_ipu_core_data imx31_ipu_core_data;
-#define imx31_add_ipu_core() \
- imx_add_ipu_core(&imx31_ipu_core_data)
-#define imx31_alloc_mx3_camera(pdata) \
- imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
-#define imx31_add_mx3_sdc_fb(pdata) \
- imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata)
-
-extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data;
-#define imx31_add_mxc_ehci_otg(pdata) \
- imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[];
-#define imx31_add_mxc_ehci_hs(id, pdata) \
- imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
-
-extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[];
-#define imx31_add_mxc_mmc(id, pdata) \
- imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
-
-extern const struct imx_mxc_nand_data imx31_mxc_nand_data;
-#define imx31_add_mxc_nand(pdata) \
- imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
-
-extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data;
-#define imx31_add_mxc_rtc() \
- imx_add_mxc_rtc(&imx31_mxc_rtc_data)
-
-extern const struct imx_mxc_w1_data imx31_mxc_w1_data;
-#define imx31_add_mxc_w1() \
- imx_add_mxc_w1(&imx31_mxc_w1_data)
-
-extern const struct imx_spi_imx_data imx31_cspi_data[];
-#define imx31_add_cspi(id, pdata) \
- imx_add_spi_imx(&imx31_cspi_data[id], pdata)
-#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata)
-#define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata)
-#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata)
-
-extern const struct imx_pata_imx_data imx31_pata_imx_data;
-#define imx31_add_pata_imx() \
- imx_add_pata_imx(&imx31_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
deleted file mode 100644
index 1b1bdad..0000000
--- a/arch/arm/mach-imx/devices-imx35.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "devices/devices-common.h"
-
-extern const struct imx_fec_data imx35_fec_data;
-#define imx35_add_fec(pdata) \
- imx_add_fec(&imx35_fec_data, pdata)
-
-extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data;
-#define imx35_add_fsl_usb2_udc(pdata) \
- imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
-
-extern const struct imx_flexcan_data imx35_flexcan_data[];
-#define imx35_add_flexcan(id) \
- imx_add_flexcan(&imx35_flexcan_data[id])
-#define imx35_add_flexcan0() imx35_add_flexcan(0)
-#define imx35_add_flexcan1() imx35_add_flexcan(1)
-
-extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
-#define imx35_add_imx2_wdt() \
- imx_add_imx2_wdt(&imx35_imx2_wdt_data)
-
-extern const struct imx_imx_i2c_data imx35_imx_i2c_data[];
-#define imx35_add_imx_i2c(id, pdata) \
- imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
-#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata)
-#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
-#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
-
-extern const struct imx_imx_keypad_data imx35_imx_keypad_data;
-#define imx35_add_imx_keypad(pdata) \
- imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
-
-extern const struct imx_imx_ssi_data imx35_imx_ssi_data[];
-#define imx35_add_imx_ssi(id, pdata) \
- imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
-#define imx35_add_imx_uart(id, pdata) \
- imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
-#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata)
-#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
-#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
-
-extern const struct imx_ipu_core_data imx35_ipu_core_data;
-#define imx35_add_ipu_core() \
- imx_add_ipu_core(&imx35_ipu_core_data)
-#define imx35_alloc_mx3_camera(pdata) \
- imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
-#define imx35_add_mx3_sdc_fb(pdata) \
- imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata)
-
-extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data;
-#define imx35_add_mxc_ehci_otg(pdata) \
- imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data;
-#define imx35_add_mxc_ehci_hs(pdata) \
- imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
-
-extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
-#define imx35_add_mxc_nand(pdata) \
- imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
-
-extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data;
-#define imx35_add_mxc_rtc() \
- imx_add_mxc_rtc(&imx35_mxc_rtc_data)
-
-extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
-#define imx35_add_mxc_w1() \
- imx_add_mxc_w1(&imx35_mxc_w1_data)
-
-extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[];
-#define imx35_add_sdhci_esdhc_imx(id, pdata) \
- imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx35_cspi_data[];
-#define imx35_add_cspi(id, pdata) \
- imx_add_spi_imx(&imx35_cspi_data[id], pdata)
-#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
-#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
-
-extern const struct imx_pata_imx_data imx35_pata_imx_data;
-#define imx35_add_pata_imx() \
- imx_add_pata_imx(&imx35_pata_imx_data)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
deleted file mode 100644
index fdca73d..0000000
--- a/arch/arm/mach-imx/devices/Kconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-config IMX_HAVE_PLATFORM_FEC
- bool
- default y if SOC_IMX25 || SOC_IMX27 || SOC_IMX35
-
-config IMX_HAVE_PLATFORM_FLEXCAN
- bool
-
-config IMX_HAVE_PLATFORM_FSL_USB2_UDC
- bool
-
-config IMX_HAVE_PLATFORM_GPIO_KEYS
- bool
-
-config IMX_HAVE_PLATFORM_IMX21_HCD
- bool
-
-config IMX_HAVE_PLATFORM_IMX27_CODA
- bool
- default y if SOC_IMX27
-
-config IMX_HAVE_PLATFORM_IMX2_WDT
- bool
-
-config IMX_HAVE_PLATFORM_IMX_FB
- bool
-
-config IMX_HAVE_PLATFORM_IMX_I2C
- bool
-
-config IMX_HAVE_PLATFORM_IMX_KEYPAD
- bool
-
-config IMX_HAVE_PLATFORM_PATA_IMX
- bool
-
-config IMX_HAVE_PLATFORM_IMX_SSI
- bool
-
-config IMX_HAVE_PLATFORM_IMX_UART
- bool
-
-config IMX_HAVE_PLATFORM_IPU_CORE
- bool
-
-config IMX_HAVE_PLATFORM_MX2_CAMERA
- bool
-
-config IMX_HAVE_PLATFORM_MX2_EMMA
- bool
-
-config IMX_HAVE_PLATFORM_MXC_EHCI
- bool
-
-config IMX_HAVE_PLATFORM_MXC_MMC
- bool
-
-config IMX_HAVE_PLATFORM_MXC_NAND
- bool
-
-config IMX_HAVE_PLATFORM_MXC_RTC
- bool
-
-config IMX_HAVE_PLATFORM_MXC_W1
- bool
-
-config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- bool
-
-config IMX_HAVE_PLATFORM_SPI_IMX
- bool
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
deleted file mode 100644
index e44758a..0000000
--- a/arch/arm/mach-imx/devices/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-y := devices.o
-
-obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
-obj-y += platform-gpio-mxc.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
-obj-y += platform-imx-dma.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
deleted file mode 100644
index 2a685ad..0000000
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/platform_data/dma-imx-sdma.h>
-
-extern struct device mxc_aips_bus;
-extern struct device mxc_ahb_bus;
-
-static inline struct platform_device *imx_add_platform_device_dmamask(
- const char *name, int id,
- const struct resource *res, unsigned int num_resources,
- const void *data, size_t size_data, u64 dmamask)
-{
- struct platform_device_info pdevinfo = {
- .name = name,
- .id = id,
- .res = res,
- .num_res = num_resources,
- .data = data,
- .size_data = size_data,
- .dma_mask = dmamask,
- };
- return platform_device_register_full(&pdevinfo);
-}
-
-static inline struct platform_device *imx_add_platform_device(
- const char *name, int id,
- const struct resource *res, unsigned int num_resources,
- const void *data, size_t size_data)
-{
- return imx_add_platform_device_dmamask(
- name, id, res, num_resources, data, size_data, 0);
-}
-
-#include <linux/fec.h>
-struct imx_fec_data {
- const char *devid;
- resource_size_t iobase;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_fec(
- const struct imx_fec_data *data,
- const struct fec_platform_data *pdata);
-
-struct imx_flexcan_data {
- int id;
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_flexcan(
- const struct imx_flexcan_data *data);
-
-#include <linux/fsl_devices.h>
-struct imx_fsl_usb2_udc_data {
- const char *devid;
- resource_size_t iobase;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_fsl_usb2_udc(
- const struct imx_fsl_usb2_udc_data *data,
- const struct fsl_usb2_platform_data *pdata);
-
-#include <linux/gpio_keys.h>
-struct platform_device *__init imx_add_gpio_keys(
- const struct gpio_keys_platform_data *pdata);
-
-#include <linux/platform_data/usb-mx2.h>
-struct imx_imx21_hcd_data {
- resource_size_t iobase;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx21_hcd(
- const struct imx_imx21_hcd_data *data,
- const struct mx21_usbh_platform_data *pdata);
-
-struct imx_imx27_coda_data {
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx27_coda(
- const struct imx_imx27_coda_data *data);
-
-struct imx_imx2_wdt_data {
- int id;
- resource_size_t iobase;
- resource_size_t iosize;
-};
-struct platform_device *__init imx_add_imx2_wdt(
- const struct imx_imx2_wdt_data *data);
-
-struct imx_imxdi_rtc_data {
- resource_size_t iobase;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_imxdi_rtc(
- const struct imx_imxdi_rtc_data *data);
-
-#include <linux/platform_data/video-imxfb.h>
-struct imx_imx_fb_data {
- const char *devid;
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx_fb(
- const struct imx_imx_fb_data *data,
- const struct imx_fb_platform_data *pdata);
-
-#include <linux/platform_data/i2c-imx.h>
-struct imx_imx_i2c_data {
- const char *devid;
- int id;
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx_i2c(
- const struct imx_imx_i2c_data *data,
- const struct imxi2c_platform_data *pdata);
-
-#include <linux/input/matrix_keypad.h>
-struct imx_imx_keypad_data {
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx_keypad(
- const struct imx_imx_keypad_data *data,
- const struct matrix_keymap_data *pdata);
-
-#include <linux/platform_data/asoc-imx-ssi.h>
-struct imx_imx_ssi_data {
- int id;
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
- resource_size_t dmatx0;
- resource_size_t dmarx0;
- resource_size_t dmatx1;
- resource_size_t dmarx1;
-};
-struct platform_device *__init imx_add_imx_ssi(
- const struct imx_imx_ssi_data *data,
- const struct imx_ssi_platform_data *pdata);
-
-#include <linux/platform_data/serial-imx.h>
-struct imx_imx_uart_1irq_data {
- int id;
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_imx_uart_1irq(
- const struct imx_imx_uart_1irq_data *data,
- const struct imxuart_platform_data *pdata);
-
-#include <linux/platform_data/video-mx3fb.h>
-#include <linux/platform_data/media/camera-mx3.h>
-struct imx_ipu_core_data {
- resource_size_t iobase;
- resource_size_t synirq;
- resource_size_t errirq;
-};
-struct platform_device *__init imx_add_ipu_core(
- const struct imx_ipu_core_data *data);
-struct platform_device *__init imx_alloc_mx3_camera(
- const struct imx_ipu_core_data *data,
- const struct mx3_camera_pdata *pdata);
-struct platform_device *__init imx_add_mx3_sdc_fb(
- const struct imx_ipu_core_data *data,
- struct mx3fb_platform_data *pdata);
-
-#include <linux/platform_data/media/camera-mx2.h>
-struct imx_mx2_camera_data {
- const char *devid;
- resource_size_t iobasecsi;
- resource_size_t iosizecsi;
- resource_size_t irqcsi;
- resource_size_t iobaseemmaprp;
- resource_size_t iosizeemmaprp;
- resource_size_t irqemmaprp;
-};
-struct platform_device *__init imx_add_mx2_camera(
- const struct imx_mx2_camera_data *data,
- const struct mx2_camera_platform_data *pdata);
-
-
-struct imx_mx2_emma_data {
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_mx2_emmaprp(
- const struct imx_mx2_emma_data *data);
-
-#include <linux/platform_data/usb-ehci-mxc.h>
-struct imx_mxc_ehci_data {
- int id;
- resource_size_t iobase;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_ehci(
- const struct imx_mxc_ehci_data *data,
- const struct mxc_usbh_platform_data *pdata);
-
-#include <linux/platform_data/mmc-mxcmmc.h>
-struct imx_mxc_mmc_data {
- const char *devid;
- int id;
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
- resource_size_t dmareq;
-};
-struct platform_device *__init imx_add_mxc_mmc(
- const struct imx_mxc_mmc_data *data,
- const struct imxmmc_platform_data *pdata);
-
-#include <linux/platform_data/mtd-mxc_nand.h>
-struct imx_mxc_nand_data {
- const char *devid;
- /*
- * id is traditionally 0, but -1 is more appropriate. We use -1 for new
- * machines but don't change existing devices as the nand device usually
- * appears in the kernel command line to pass its partitioning.
- */
- int id;
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t axibase;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_nand(
- const struct imx_mxc_nand_data *data,
- const struct mxc_nand_platform_data *pdata);
-
-struct imx_pata_imx_data {
- resource_size_t iobase;
- resource_size_t iosize;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_pata_imx(
- const struct imx_pata_imx_data *data);
-
-/* mxc_rtc */
-struct imx_mxc_rtc_data {
- const char *devid;
- resource_size_t iobase;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_rtc(
- const struct imx_mxc_rtc_data *data);
-
-/* mxc_w1 */
-struct imx_mxc_w1_data {
- resource_size_t iobase;
-};
-struct platform_device *__init imx_add_mxc_w1(
- const struct imx_mxc_w1_data *data);
-
-#include <linux/platform_data/mmc-esdhc-imx.h>
-struct imx_sdhci_esdhc_imx_data {
- const char *devid;
- int id;
- resource_size_t iobase;
- resource_size_t irq;
-};
-struct platform_device *__init imx_add_sdhci_esdhc_imx(
- const struct imx_sdhci_esdhc_imx_data *data,
- const struct esdhc_platform_data *pdata);
-
-#include <linux/platform_data/spi-imx.h>
-struct imx_spi_imx_data {
- const char *devid;
- int id;
- resource_size_t iobase;
- resource_size_t iosize;
- int irq;
-};
-struct platform_device *__init imx_add_spi_imx(
- const struct imx_spi_imx_data *data,
- const struct spi_imx_master *pdata);
-
-struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase,
- int irq, int irq_err);
-struct platform_device *imx_add_imx_sdma(char *name,
- resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
diff --git a/arch/arm/mach-imx/devices/devices.c b/arch/arm/mach-imx/devices/devices.c
deleted file mode 100644
index cd72f08..0000000
--- a/arch/arm/mach-imx/devices/devices.c
+++ /dev/null
@@ -1,35 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-
-#include "../common.h"
-#include "devices-common.h"
-
-struct device mxc_aips_bus = {
- .init_name = "mxc_aips",
-};
-
-struct device mxc_ahb_bus = {
- .init_name = "mxc_ahb",
-};
-
-int __init mxc_device_init(void)
-{
- int ret;
-
- ret = device_register(&mxc_aips_bus);
- if (ret < 0)
- goto done;
-
- ret = device_register(&mxc_ahb_bus);
-
-done:
- return ret;
-}
diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c
deleted file mode 100644
index 88e853d..0000000
--- a/arch/arm/mach-imx/devices/platform-fec.c
+++ /dev/null
@@ -1,49 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include <linux/dma-mapping.h>
-#include <linux/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_fec_data_entry_single(soc, _devid) \
- { \
- .devid = _devid, \
- .iobase = soc ## _FEC_BASE_ADDR, \
- .irq = soc ## _INT_FEC, \
- }
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_fec_data imx27_fec_data __initconst =
- imx_fec_data_entry_single(MX27, "imx27-fec");
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX35
-/* i.mx35 has the i.mx27 type fec */
-const struct imx_fec_data imx35_fec_data __initconst =
- imx_fec_data_entry_single(MX35, "imx27-fec");
-#endif
-
-struct platform_device *__init imx_add_fec(
- const struct imx_fec_data *data,
- const struct fec_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return imx_add_platform_device_dmamask(data->devid, 0,
- res, ARRAY_SIZE(res),
- pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-flexcan.c b/arch/arm/mach-imx/devices/platform-flexcan.c
deleted file mode 100644
index e4eed35..0000000
--- a/arch/arm/mach-imx/devices/platform-flexcan.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \
- { \
- .id = _id, \
- .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_CAN ## _hwid, \
- }
-
-#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \
- [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_flexcan_data imx35_flexcan_data[] __initconst = {
-#define imx35_flexcan_data_entry(_id, _hwid) \
- imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K)
- imx35_flexcan_data_entry(0, 1),
- imx35_flexcan_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_flexcan(
- const struct imx_flexcan_data *data)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return imx_add_platform_device("flexcan", data->id,
- res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
deleted file mode 100644
index cc86de4..0000000
--- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c
+++ /dev/null
@@ -1,51 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include <linux/dma-mapping.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_fsl_usb2_udc_data_entry_single(soc, _devid) \
- { \
- .devid = _devid, \
- .iobase = soc ## _USB_OTG_BASE_ADDR, \
- .irq = soc ## _INT_USB_OTG, \
- }
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
- imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27");
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst =
- imx_fsl_usb2_udc_data_entry_single(MX31, "imx-udc-mx27");
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
- imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27");
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_fsl_usb2_udc(
- const struct imx_fsl_usb2_udc_data *data,
- const struct fsl_usb2_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + SZ_512 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
- return imx_add_platform_device_dmamask(data->devid, -1,
- res, ARRAY_SIZE(res),
- pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-gpio-mxc.c b/arch/arm/mach-imx/devices/platform-gpio-mxc.c
deleted file mode 100644
index 78628ef..0000000
--- a/arch/arm/mach-imx/devices/platform-gpio-mxc.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Linaro Limited
- */
-#include "devices-common.h"
-#include "../common.h"
-
-struct platform_device *__init mxc_register_gpio(char *name, int id,
- resource_size_t iobase, resource_size_t iosize, int irq, int irq_high)
-{
- struct resource res[] = {
- {
- .start = iobase,
- .end = iobase + iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = irq,
- .end = irq,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = irq_high,
- .end = irq_high,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return platform_device_register_resndata(&mxc_aips_bus,
- name, id, res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-gpio_keys.c b/arch/arm/mach-imx/devices/platform-gpio_keys.c
deleted file mode 100644
index 4886784..0000000
--- a/arch/arm/mach-imx/devices/platform-gpio_keys.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-#include <linux/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-struct platform_device *__init imx_add_gpio_keys(
- const struct gpio_keys_platform_data *pdata)
-{
- return imx_add_platform_device("gpio-keys", -1, NULL,
- 0, pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-dma.c b/arch/arm/mach-imx/devices/platform-imx-dma.c
deleted file mode 100644
index 26b47b3..0000000
--- a/arch/arm/mach-imx/devices/platform-imx-dma.c
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "devices-common.h"
-
-struct platform_device __init __maybe_unused *imx_add_imx_dma(char *name,
- resource_size_t iobase, int irq, int irq_err)
-{
- struct resource res[] = {
- {
- .start = iobase,
- .end = iobase + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = irq,
- .end = irq,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = irq_err,
- .end = irq_err,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return platform_device_register_resndata(&mxc_ahb_bus,
- name, -1, res, ARRAY_SIZE(res), NULL, 0);
-}
-
-struct platform_device __init __maybe_unused *imx_add_imx_sdma(char *name,
- resource_size_t iobase, int irq, struct sdma_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = iobase,
- .end = iobase + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = irq,
- .end = irq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return platform_device_register_resndata(&mxc_ahb_bus, name,
- -1, res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c
deleted file mode 100644
index e553d01..0000000
--- a/arch/arm/mach-imx/devices/platform-imx-fb.c
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include <linux/dma-mapping.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_fb_data_entry_single(soc, _devid, _size) \
- { \
- .devid = _devid, \
- .iobase = soc ## _LCDC_BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_LCDC, \
- }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
- imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
- imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-struct platform_device *__init imx_add_imx_fb(
- const struct imx_imx_fb_data *data,
- const struct imx_fb_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
- return imx_add_platform_device_dmamask(data->devid, 0,
- res, ARRAY_SIZE(res),
- pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c
deleted file mode 100644
index 81d317b..0000000
--- a/arch/arm/mach-imx/devices/platform-imx-i2c.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size) \
- { \
- .devid = _devid, \
- .id = _id, \
- .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_I2C ## _hwid, \
- }
-
-#define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size) \
- [_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
- imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
-#define imx27_imx_i2c_data_entry(_id, _hwid) \
- imx_imx_i2c_data_entry(MX27, "imx21-i2c", _id, _hwid, SZ_4K)
- imx27_imx_i2c_data_entry(0, 1),
- imx27_imx_i2c_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
-#define imx31_imx_i2c_data_entry(_id, _hwid) \
- imx_imx_i2c_data_entry(MX31, "imx21-i2c", _id, _hwid, SZ_4K)
- imx31_imx_i2c_data_entry(0, 1),
- imx31_imx_i2c_data_entry(1, 2),
- imx31_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
-#define imx35_imx_i2c_data_entry(_id, _hwid) \
- imx_imx_i2c_data_entry(MX35, "imx21-i2c", _id, _hwid, SZ_4K)
- imx35_imx_i2c_data_entry(0, 1),
- imx35_imx_i2c_data_entry(1, 2),
- imx35_imx_i2c_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_imx_i2c(
- const struct imx_imx_i2c_data *data,
- const struct imxi2c_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return imx_add_platform_device(data->devid, data->id,
- res, ARRAY_SIZE(res),
- pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c
deleted file mode 100644
index de2e03e..0000000
--- a/arch/arm/mach-imx/devices/platform-imx-keypad.c
+++ /dev/null
@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_keypad_data_entry_single(soc, _size) \
- { \
- .iobase = soc ## _KPP_BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_KPP, \
- }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
- imx_imx_keypad_data_entry_single(MX21, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
- imx_imx_keypad_data_entry_single(MX27, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst =
- imx_imx_keypad_data_entry_single(MX31, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst =
- imx_imx_keypad_data_entry_single(MX35, SZ_16);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_imx_keypad(
- const struct imx_imx_keypad_data *data,
- const struct matrix_keymap_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return imx_add_platform_device("imx-keypad", -1,
- res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c
deleted file mode 100644
index ed8c664..0000000
--- a/arch/arm/mach-imx/devices/platform-imx-ssi.c
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size) \
- [_id] = { \
- .id = _id, \
- .iobase = soc ## _SSI ## _hwid ## _BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_SSI ## _hwid, \
- .dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0, \
- .dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0, \
- .dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1, \
- .dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1, \
- }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
-#define imx21_imx_ssi_data_entry(_id, _hwid) \
- imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K)
- imx21_imx_ssi_data_entry(0, 1),
- imx21_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
-#define imx27_imx_ssi_data_entry(_id, _hwid) \
- imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K)
- imx27_imx_ssi_data_entry(0, 1),
- imx27_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = {
-#define imx31_imx_ssi_data_entry(_id, _hwid) \
- imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K)
- imx31_imx_ssi_data_entry(0, 1),
- imx31_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
-#define imx35_imx_ssi_data_entry(_id, _hwid) \
- imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K)
- imx35_imx_ssi_data_entry(0, 1),
- imx35_imx_ssi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_imx_ssi(
- const struct imx_imx_ssi_data *data,
- const struct imx_ssi_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
-#define DMARES(_name) { \
- .name = #_name, \
- .start = data->dma ## _name, \
- .end = data->dma ## _name, \
- .flags = IORESOURCE_DMA, \
-}
- DMARES(tx0),
- DMARES(rx0),
- DMARES(tx1),
- DMARES(rx1),
- };
-
- return imx_add_platform_device("imx-ssi", data->id,
- res, ARRAY_SIZE(res),
- pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c
deleted file mode 100644
index c8f01de..0000000
--- a/arch/arm/mach-imx/devices/platform-imx-uart.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size) \
- [_id] = { \
- .id = _id, \
- .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \
- .iosize = _size, \
- .irqrx = soc ## _INT_UART ## _hwid ## RX, \
- .irqtx = soc ## _INT_UART ## _hwid ## TX, \
- .irqrts = soc ## _INT_UART ## _hwid ## RTS, \
- }
-
-#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size) \
- [_id] = { \
- .id = _id, \
- .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_UART ## _hwid, \
- }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
-#define imx21_imx_uart_data_entry(_id, _hwid) \
- imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K)
- imx21_imx_uart_data_entry(0, 1),
- imx21_imx_uart_data_entry(1, 2),
- imx21_imx_uart_data_entry(2, 3),
- imx21_imx_uart_data_entry(3, 4),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
-#define imx27_imx_uart_data_entry(_id, _hwid) \
- imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K)
- imx27_imx_uart_data_entry(0, 1),
- imx27_imx_uart_data_entry(1, 2),
- imx27_imx_uart_data_entry(2, 3),
- imx27_imx_uart_data_entry(3, 4),
- imx27_imx_uart_data_entry(4, 5),
- imx27_imx_uart_data_entry(5, 6),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
-#define imx31_imx_uart_data_entry(_id, _hwid) \
- imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K)
- imx31_imx_uart_data_entry(0, 1),
- imx31_imx_uart_data_entry(1, 2),
- imx31_imx_uart_data_entry(2, 3),
- imx31_imx_uart_data_entry(3, 4),
- imx31_imx_uart_data_entry(4, 5),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
-#define imx35_imx_uart_data_entry(_id, _hwid) \
- imx_imx_uart_1irq_data_entry(MX35, _id, _hwid, SZ_16K)
- imx35_imx_uart_data_entry(0, 1),
- imx35_imx_uart_data_entry(1, 2),
- imx35_imx_uart_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_imx_uart_1irq(
- const struct imx_imx_uart_1irq_data *data,
- const struct imxuart_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- /* i.mx21 type uart runs on all i.mx except i.mx1 */
- return imx_add_platform_device("imx21-uart", data->id,
- res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c
deleted file mode 100644
index fdd355a..0000000
--- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c
+++ /dev/null
@@ -1,52 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include <linux/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) \
- { \
- .id = _id, \
- .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR, \
- .iosize = _size, \
- }
-#define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size) \
- [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
- imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
- imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst =
- imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst =
- imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_imx2_wdt(
- const struct imx_imx2_wdt_data *data)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- },
- };
- return imx_add_platform_device("imx2-wdt", data->id,
- res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx21-hcd.c b/arch/arm/mach-imx/devices/platform-imx21-hcd.c
deleted file mode 100644
index f55763c..0000000
--- a/arch/arm/mach-imx/devices/platform-imx21-hcd.c
+++ /dev/null
@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_imx21_hcd_data_entry_single(soc) \
- { \
- .iobase = soc ## _USBOTG_BASE_ADDR, \
- .irq = soc ## _INT_USBHOST, \
- }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst =
- imx_imx21_hcd_data_entry_single(MX21);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-struct platform_device *__init imx_add_imx21_hcd(
- const struct imx_imx21_hcd_data *data,
- const struct mx21_usbh_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
- return imx_add_platform_device_dmamask("imx21-hcd", 0,
- res, ARRAY_SIZE(res),
- pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-imx27-coda.c b/arch/arm/mach-imx/devices/platform-imx27-coda.c
deleted file mode 100644
index 66a116e..0000000
--- a/arch/arm/mach-imx/devices/platform-imx27-coda.c
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Vista Silicon
- * Javier Martin <javier.martin@vista-silicon.com>
- */
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_imx27_coda_data imx27_coda_data __initconst = {
- .iobase = MX27_VPU_BASE_ADDR,
- .iosize = SZ_512,
- .irq = MX27_INT_VPU,
-};
-#endif
-
-struct platform_device *__init imx_add_imx27_coda(
- const struct imx_imx27_coda_data *data)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
- return imx_add_platform_device_dmamask("coda-imx27", 0, res, 2, NULL,
- 0, DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-ipu-core.c b/arch/arm/mach-imx/devices/platform-ipu-core.c
deleted file mode 100644
index b429076..0000000
--- a/arch/arm/mach-imx/devices/platform-ipu-core.c
+++ /dev/null
@@ -1,127 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2011 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include <linux/dma-mapping.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_ipu_core_entry_single(soc) \
-{ \
- .iobase = soc ## _IPU_CTRL_BASE_ADDR, \
- .synirq = soc ## _INT_IPU_SYN, \
- .errirq = soc ## _INT_IPU_ERR, \
-}
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_ipu_core_data imx31_ipu_core_data __initconst =
- imx_ipu_core_entry_single(MX31);
-#endif
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_ipu_core_data imx35_ipu_core_data __initconst =
- imx_ipu_core_entry_single(MX35);
-#endif
-
-static struct platform_device *imx_ipu_coredev __initdata;
-
-struct platform_device *__init imx_add_ipu_core(
- const struct imx_ipu_core_data *data)
-{
- /* The resource order is important! */
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + 0x5f,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->iobase + 0x88,
- .end = data->iobase + 0xb3,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->synirq,
- .end = data->synirq,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = data->errirq,
- .end = data->errirq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1,
- res, ARRAY_SIZE(res), NULL, 0);
-}
-
-struct platform_device *__init imx_alloc_mx3_camera(
- const struct imx_ipu_core_data *data,
- const struct mx3_camera_pdata *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase + 0x60,
- .end = data->iobase + 0x87,
- .flags = IORESOURCE_MEM,
- },
- };
- int ret = -ENOMEM;
- struct platform_device *pdev;
-
- if (IS_ERR_OR_NULL(imx_ipu_coredev))
- return ERR_PTR(-ENODEV);
-
- pdev = platform_device_alloc("mx3-camera", 0);
- if (!pdev)
- return ERR_PTR(-ENOMEM);
-
- pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
- if (!pdev->dev.dma_mask)
- goto err;
-
- *pdev->dev.dma_mask = DMA_BIT_MASK(32);
- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-
- ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
- if (ret)
- goto err;
-
- if (pdata) {
- struct mx3_camera_pdata *copied_pdata;
-
- ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
- if (ret) {
-err:
- kfree(pdev->dev.dma_mask);
- platform_device_put(pdev);
- return ERR_PTR(-ENODEV);
- }
- copied_pdata = dev_get_platdata(&pdev->dev);
- copied_pdata->dma_dev = &imx_ipu_coredev->dev;
- }
-
- return pdev;
-}
-
-struct platform_device *__init imx_add_mx3_sdc_fb(
- const struct imx_ipu_core_data *data,
- struct mx3fb_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase + 0xb4,
- .end = data->iobase + 0x1bf,
- .flags = IORESOURCE_MEM,
- },
- };
-
- if (IS_ERR_OR_NULL(imx_ipu_coredev))
- return ERR_PTR(-ENODEV);
-
- pdata->dma_dev = &imx_ipu_coredev->dev;
-
- return imx_add_platform_device_dmamask("mx3_sdc_fb", -1,
- res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
- DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c
deleted file mode 100644
index 5375f8b..0000000
--- a/arch/arm/mach-imx/devices/platform-mx2-camera.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mx2_camera_data_entry_single(soc, _devid) \
- { \
- .devid = _devid, \
- .iobasecsi = soc ## _CSI_BASE_ADDR, \
- .iosizecsi = SZ_4K, \
- .irqcsi = soc ## _INT_CSI, \
- }
-#define imx_mx2_camera_data_entry_single_emma(soc, _devid) \
- { \
- .devid = _devid, \
- .iobasecsi = soc ## _CSI_BASE_ADDR, \
- .iosizecsi = SZ_32, \
- .irqcsi = soc ## _INT_CSI, \
- .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \
- .iosizeemmaprp = SZ_32, \
- .irqemmaprp = soc ## _INT_EMMAPRP, \
- }
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
- imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera");
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-struct platform_device *__init imx_add_mx2_camera(
- const struct imx_mx2_camera_data *data,
- const struct mx2_camera_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobasecsi,
- .end = data->iobasecsi + data->iosizecsi - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irqcsi,
- .end = data->irqcsi,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = data->iobaseemmaprp,
- .end = data->iobaseemmaprp + data->iosizeemmaprp - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irqemmaprp,
- .end = data->irqemmaprp,
- .flags = IORESOURCE_IRQ,
- },
- };
- return imx_add_platform_device_dmamask(data->devid, 0,
- res, data->iobaseemmaprp ? 4 : 2,
- pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
-
diff --git a/arch/arm/mach-imx/devices/platform-mx2-emma.c b/arch/arm/mach-imx/devices/platform-mx2-emma.c
deleted file mode 100644
index 20f28ba..0000000
--- a/arch/arm/mach-imx/devices/platform-mx2-emma.c
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mx2_emmaprp_data_entry_single(soc) \
- { \
- .iobase = soc ## _EMMAPRP_BASE_ADDR, \
- .iosize = SZ_256, \
- .irq = soc ## _INT_EMMAPRP, \
- }
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mx2_emma_data imx27_mx2_emmaprp_data __initconst =
- imx_mx2_emmaprp_data_entry_single(MX27);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-struct platform_device *__init imx_add_mx2_emmaprp(
- const struct imx_mx2_emma_data *data)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
- return imx_add_platform_device_dmamask("m2m-emmaprp", 0,
- res, 2, NULL, 0, DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c
deleted file mode 100644
index d9d7cc7..0000000
--- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include <linux/dma-mapping.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \
- { \
- .id = _id, \
- .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \
- .irq = soc ## _INT_USB_ ## hs, \
- }
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
- imx_mxc_ehci_data_entry_single(MX27, 0, OTG);
-const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = {
- imx_mxc_ehci_data_entry_single(MX27, 1, HS1),
- imx_mxc_ehci_data_entry_single(MX27, 2, HS2),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst =
- imx_mxc_ehci_data_entry_single(MX31, 0, OTG);
-const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = {
- imx_mxc_ehci_data_entry_single(MX31, 1, HS1),
- imx_mxc_ehci_data_entry_single(MX31, 2, HS2),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst =
- imx_mxc_ehci_data_entry_single(MX35, 0, OTG);
-const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
- imx_mxc_ehci_data_entry_single(MX35, 1, HS);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_mxc_ehci(
- const struct imx_mxc_ehci_data *data,
- const struct mxc_usbh_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + SZ_512 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
- return imx_add_platform_device_dmamask("mxc-ehci", data->id,
- res, ARRAY_SIZE(res),
- pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc-mmc.c b/arch/arm/mach-imx/devices/platform-mxc-mmc.c
deleted file mode 100644
index cd4c502..0000000
--- a/arch/arm/mach-imx/devices/platform-mxc-mmc.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include <linux/dma-mapping.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size) \
- { \
- .devid = _devid, \
- .id = _id, \
- .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_SDHC ## _hwid, \
- .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \
- }
-#define imx_mxc_mmc_data_entry(soc, _devid, _id, _hwid, _size) \
- [_id] = imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = {
-#define imx21_mxc_mmc_data_entry(_id, _hwid) \
- imx_mxc_mmc_data_entry(MX21, "imx21-mmc", _id, _hwid, SZ_4K)
- imx21_mxc_mmc_data_entry(0, 1),
- imx21_mxc_mmc_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = {
-#define imx27_mxc_mmc_data_entry(_id, _hwid) \
- imx_mxc_mmc_data_entry(MX27, "imx21-mmc", _id, _hwid, SZ_4K)
- imx27_mxc_mmc_data_entry(0, 1),
- imx27_mxc_mmc_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = {
-#define imx31_mxc_mmc_data_entry(_id, _hwid) \
- imx_mxc_mmc_data_entry(MX31, "imx31-mmc", _id, _hwid, SZ_16K)
- imx31_mxc_mmc_data_entry(0, 1),
- imx31_mxc_mmc_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-struct platform_device *__init imx_add_mxc_mmc(
- const struct imx_mxc_mmc_data *data,
- const struct imxmmc_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = data->dmareq,
- .end = data->dmareq,
- .flags = IORESOURCE_DMA,
- },
- };
- return imx_add_platform_device_dmamask(data->devid, data->id,
- res, ARRAY_SIZE(res),
- pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
deleted file mode 100644
index 0f5f741..0000000
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include <linux/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_nand_data_entry_single(soc, _devid, _size) \
- { \
- .devid = _devid, \
- .iobase = soc ## _NFC_BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_NFC \
- }
-
-#define imx_mxc_nandv3_data_entry_single(soc, _devid, _size) \
- { \
- .devid = _devid, \
- .id = -1, \
- .iobase = soc ## _NFC_BASE_ADDR, \
- .iosize = _size, \
- .axibase = soc ## _NFC_AXI_BASE_ADDR, \
- .irq = soc ## _INT_NFC \
- }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
- imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
- imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
- imx_mxc_nand_data_entry_single(MX31, "imx27-nand", SZ_4K);
-#endif
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
- imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K);
-#endif
-
-struct platform_device *__init imx_add_mxc_nand(
- const struct imx_mxc_nand_data *data,
- const struct mxc_nand_platform_data *pdata)
-{
- /* AXI has to come first, that's how the mxc_nand driver expect it */
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = data->axibase,
- .end = data->axibase + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- },
- };
- return imx_add_platform_device(data->devid, data->id,
- res, ARRAY_SIZE(res) - !data->axibase,
- pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc_rtc.c b/arch/arm/mach-imx/devices/platform-mxc_rtc.c
deleted file mode 100644
index 0c746de..0000000
--- a/arch/arm/mach-imx/devices/platform-mxc_rtc.c
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010-2011 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_rtc_data_entry_single(soc, _devid) \
- { \
- .devid = _devid, \
- .iobase = soc ## _RTC_BASE_ADDR, \
- .irq = soc ## _INT_RTC, \
- }
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst =
- imx_mxc_rtc_data_entry_single(MX31, "imx21-rtc");
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst =
- imx_mxc_rtc_data_entry_single(MX35, "imx21-rtc");
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_mxc_rtc(
- const struct imx_mxc_rtc_data *data)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return imx_add_platform_device(data->devid, -1,
- res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-mxc_w1.c b/arch/arm/mach-imx/devices/platform-mxc_w1.c
deleted file mode 100644
index ab42c6b..0000000
--- a/arch/arm/mach-imx/devices/platform-mxc_w1.c
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_w1_data_entry_single(soc) \
- { \
- .iobase = soc ## _OWIRE_BASE_ADDR, \
- }
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst =
- imx_mxc_w1_data_entry_single(MX21);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst =
- imx_mxc_w1_data_entry_single(MX27);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst =
- imx_mxc_w1_data_entry_single(MX31);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst =
- imx_mxc_w1_data_entry_single(MX35);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_mxc_w1(
- const struct imx_mxc_w1_data *data)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- };
-
- return imx_add_platform_device("mxc_w1", 0,
- res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/devices/platform-pata_imx.c b/arch/arm/mach-imx/devices/platform-pata_imx.c
deleted file mode 100644
index 0e985ff..0000000
--- a/arch/arm/mach-imx/devices/platform-pata_imx.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_pata_imx_data_entry_single(soc, _size) \
- { \
- .iobase = soc ## _ATA_BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_ATA, \
- }
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_pata_imx_data imx27_pata_imx_data __initconst =
- imx_pata_imx_data_entry_single(MX27, SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_pata_imx_data imx31_pata_imx_data __initconst =
- imx_pata_imx_data_entry_single(MX31, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_pata_imx_data imx35_pata_imx_data __initconst =
- imx_pata_imx_data_entry_single(MX35, SZ_16K);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_pata_imx(
- const struct imx_pata_imx_data *data)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
- return imx_add_platform_device("pata_imx", -1,
- res, ARRAY_SIZE(res), NULL, 0);
-}
-
diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
deleted file mode 100644
index 40c2610..0000000
--- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
+++ /dev/null
@@ -1,64 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2010 Pengutronix, Wolfram Sang <kernel@pengutronix.de>
- */
-
-#include <linux/platform_data/mmc-esdhc-imx.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_sdhci_esdhc_imx_data_entry_single(soc, _devid, _id, hwid) \
- { \
- .devid = _devid, \
- .id = _id, \
- .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \
- .irq = soc ## _INT_ESDHC ## hwid, \
- }
-
-#define imx_sdhci_esdhc_imx_data_entry(soc, devid, id, hwid) \
- [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, devid, id, hwid)
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_sdhci_esdhc_imx_data
-imx35_sdhci_esdhc_imx_data[] __initconst = {
-#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \
- imx_sdhci_esdhc_imx_data_entry(MX35, "sdhci-esdhc-imx35", _id, _hwid)
- imx35_sdhci_esdhc_imx_data_entry(0, 1),
- imx35_sdhci_esdhc_imx_data_entry(1, 2),
- imx35_sdhci_esdhc_imx_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-static const struct esdhc_platform_data default_esdhc_pdata __initconst = {
- .wp_type = ESDHC_WP_NONE,
- .cd_type = ESDHC_CD_NONE,
-};
-
-struct platform_device *__init imx_add_sdhci_esdhc_imx(
- const struct imx_sdhci_esdhc_imx_data *data,
- const struct esdhc_platform_data *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- /*
- * If machine does not provide pdata, use the default one
- * which means no WP/CD support
- */
- if (!pdata)
- pdata = &default_esdhc_pdata;
-
- return imx_add_platform_device_dmamask(data->devid, data->id, res,
- ARRAY_SIZE(res), pdata, sizeof(*pdata),
- DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c
deleted file mode 100644
index f2cafa5..0000000
--- a/arch/arm/mach-imx/devices/platform-spi_imx.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \
- { \
- .devid = _devid, \
- .id = _id, \
- .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR, \
- .iosize = _size, \
- .irq = soc ## _INT_ ## type ## hwid, \
- }
-
-#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \
- [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
-#define imx21_cspi_data_entry(_id, _hwid) \
- imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K)
- imx21_cspi_data_entry(0, 1),
- imx21_cspi_data_entry(1, 2),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
-#define imx27_cspi_data_entry(_id, _hwid) \
- imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K)
- imx27_cspi_data_entry(0, 1),
- imx27_cspi_data_entry(1, 2),
- imx27_cspi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX31
-const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
-#define imx31_cspi_data_entry(_id, _hwid) \
- imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
- imx31_cspi_data_entry(0, 1),
- imx31_cspi_data_entry(1, 2),
- imx31_cspi_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
-#define imx35_cspi_data_entry(_id, _hwid) \
- imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
- imx35_cspi_data_entry(0, 1),
- imx35_cspi_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-struct platform_device *__init imx_add_spi_imx(
- const struct imx_spi_imx_data *data,
- const struct spi_imx_master *pdata)
-{
- struct resource res[] = {
- {
- .start = data->iobase,
- .end = data->iobase + data->iosize - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = data->irq,
- .end = data->irq,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- return imx_add_platform_device(data->devid, data->id,
- res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
deleted file mode 100644
index 83962ce..0000000
--- a/arch/arm/mach-imx/ehci-imx27.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
-
-#include "ehci.h"
-#include "hardware.h"
-
-#define USBCTRL_OTGBASE_OFFSET 0x600
-
-#define MX27_OTG_SIC_SHIFT 29
-#define MX27_OTG_SIC_MASK (0x3 << MX27_OTG_SIC_SHIFT)
-#define MX27_OTG_PM_BIT (1 << 24)
-
-#define MX27_H2_SIC_SHIFT 21
-#define MX27_H2_SIC_MASK (0x3 << MX27_H2_SIC_SHIFT)
-#define MX27_H2_PM_BIT (1 << 16)
-#define MX27_H2_DT_BIT (1 << 5)
-
-#define MX27_H1_SIC_SHIFT 13
-#define MX27_H1_SIC_MASK (0x3 << MX27_H1_SIC_SHIFT)
-#define MX27_H1_PM_BIT (1 << 8)
-#define MX27_H1_DT_BIT (1 << 4)
-
-int mx27_initialize_usb_hw(int port, unsigned int flags)
-{
- unsigned int v;
-
- v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
- switch (port) {
- case 0: /* OTG port */
- v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX27_OTG_PM_BIT;
- break;
- case 1: /* H1 port */
- v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX27_H1_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX27_H1_DT_BIT;
-
- break;
- case 2: /* H2 port */
- v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX27_H2_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX27_H2_DT_BIT;
-
- break;
- default:
- return -EINVAL;
- }
-
- writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
- return 0;
-}
-
diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
deleted file mode 100644
index d6d794d..0000000
--- a/arch/arm/mach-imx/ehci-imx31.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
-
-#include "ehci.h"
-#include "hardware.h"
-
-#define USBCTRL_OTGBASE_OFFSET 0x600
-
-#define MX31_OTG_SIC_SHIFT 29
-#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT (1 << 24)
-
-#define MX31_H2_SIC_SHIFT 21
-#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
-#define MX31_H2_PM_BIT (1 << 16)
-#define MX31_H2_DT_BIT (1 << 5)
-
-#define MX31_H1_SIC_SHIFT 13
-#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
-#define MX31_H1_PM_BIT (1 << 8)
-#define MX31_H1_DT_BIT (1 << 4)
-
-int mx31_initialize_usb_hw(int port, unsigned int flags)
-{
- unsigned int v;
-
- v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
- switch (port) {
- case 0: /* OTG port */
- v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_OTG_PM_BIT;
-
- break;
- case 1: /* H1 port */
- v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_H1_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX31_H1_DT_BIT;
-
- break;
- case 2: /* H2 port */
- v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_H2_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX31_H2_DT_BIT;
-
- break;
- default:
- return -EINVAL;
- }
-
- writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
- return 0;
-}
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
deleted file mode 100644
index e6ba965..0000000
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ /dev/null
@@ -1,89 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/platform_data/usb-ehci-mxc.h>
-
-#include "ehci.h"
-#include "hardware.h"
-
-#define USBCTRL_OTGBASE_OFFSET 0x600
-
-#define MX35_OTG_SIC_SHIFT 29
-#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
-#define MX35_OTG_PM_BIT (1 << 24)
-#define MX35_OTG_PP_BIT (1 << 11)
-#define MX35_OTG_OCPOL_BIT (1 << 3)
-
-#define MX35_H1_SIC_SHIFT 21
-#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
-#define MX35_H1_PP_BIT (1 << 18)
-#define MX35_H1_PM_BIT (1 << 16)
-#define MX35_H1_IPPUE_UP_BIT (1 << 7)
-#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
-#define MX35_H1_TLL_BIT (1 << 5)
-#define MX35_H1_USBTE_BIT (1 << 4)
-#define MX35_H1_OCPOL_BIT (1 << 2)
-
-int mx35_initialize_usb_hw(int port, unsigned int flags)
-{
- unsigned int v;
-
- v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
- switch (port) {
- case 0: /* OTG port */
- v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
- MX35_OTG_OCPOL_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX35_OTG_PM_BIT;
-
- if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
- v |= MX35_OTG_PP_BIT;
-
- if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
- v |= MX35_OTG_OCPOL_BIT;
-
- break;
- case 1: /* H1 port */
- v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
- MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
- MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX35_H1_PM_BIT;
-
- if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
- v |= MX35_H1_PP_BIT;
-
- if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
- v |= MX35_H1_OCPOL_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX35_H1_TLL_BIT;
-
- if (flags & MXC_EHCI_INTERNAL_PHY)
- v |= MX35_H1_USBTE_BIT;
-
- if (flags & MXC_EHCI_IPPUE_DOWN)
- v |= MX35_H1_IPPUE_DOWN_BIT;
-
- if (flags & MXC_EHCI_IPPUE_UP)
- v |= MX35_H1_IPPUE_UP_BIT;
-
- break;
- default:
- return -EINVAL;
- }
-
- writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
- return 0;
-}
diff --git a/arch/arm/mach-imx/ehci.h b/arch/arm/mach-imx/ehci.h
deleted file mode 100644
index b7ad617..0000000
--- a/arch/arm/mach-imx/ehci.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MACH_IMX_EHCI_H
-#define __MACH_IMX_EHCI_H
-
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
-#define MXC_EHCI_FORCE_FS (1 << 24)
-#define MXC_EHCI_UTMI_8BIT (0 << 28)
-#define MXC_EHCI_UTMI_16BIT (1 << 28)
-#define MXC_EHCI_SERIAL (1 << 29)
-#define MXC_EHCI_MODE_UTMI (0 << 30)
-#define MXC_EHCI_MODE_PHILIPS (1 << 30)
-#define MXC_EHCI_MODE_ULPI (2 << 30)
-#define MXC_EHCI_MODE_SERIAL (3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
-#define MXC_EHCI_INTERFACE_MASK (0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
-#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
-#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
-#define MXC_EHCI_TTL_ENABLED (1 << 8)
-
-#define MXC_EHCI_INTERNAL_PHY (1 << 9)
-#define MXC_EHCI_IPPUE_DOWN (1 << 10)
-#define MXC_EHCI_IPPUE_UP (1 << 11)
-#define MXC_EHCI_WAKEUP_ENABLED (1 << 12)
-#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13)
-
-#define MXC_USBCTRL_OFFSET 0
-#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
-#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
-#define MXC_USBH2CTRL_OFFSET 0x14
-
-int mx25_initialize_usb_hw(int port, unsigned int flags);
-int mx31_initialize_usb_hw(int port, unsigned int flags);
-int mx35_initialize_usb_hw(int port, unsigned int flags);
-int mx27_initialize_usb_hw(int port, unsigned int flags);
-
-#endif /* __MACH_IMX_EHCI_H */
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index b5b557f..ebc4339 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -10,7 +10,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#include <linux/irqchip/arm-gic.h>
+
#include "common.h"
#include "hardware.h"
@@ -111,7 +111,6 @@
gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
writel_relaxed(~0, reg_imr1 + i * 4);
}
-
}
void imx_gpc_restore_all(void)
@@ -282,4 +281,5 @@
/* map GPC, so that at least CPUidle and WARs keep working */
gpc_base = of_iomap(np, 0);
}
+ of_node_put(np);
}
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 92c5a9c..7acf7ce 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -97,7 +97,6 @@
#include "mx31.h"
#include "mx35.h"
#include "mx2x.h"
-#include "mx21.h"
#include "mx27.h"
#define imx_map_entry(soc, name, _type) { \
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 089d11f..82e2239 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -6,32 +6,12 @@
#include <linux/errno.h>
#include <linux/jiffies.h>
+#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/proc-fns.h>
#include "common.h"
-static inline void cpu_enter_lowpower(void)
-{
- unsigned int v;
-
- asm volatile(
- "mcr p15, 0, %1, c7, c5, 0\n"
- " mcr p15, 0, %1, c7, c10, 4\n"
- /*
- * Turn off coherency
- */
- " mrc p15, 0, %0, c1, c0, 1\n"
- " bic %0, %0, %3\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- " mrc p15, 0, %0, c1, c0, 0\n"
- " bic %0, %0, %2\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- : "=&r" (v)
- : "r" (0), "Ir" (CR_C), "Ir" (0x40)
- : "cc");
-}
-
/*
* platform-specific code to shutdown a CPU
*
@@ -39,7 +19,7 @@
*/
void imx_cpu_die(unsigned int cpu)
{
- cpu_enter_lowpower();
+ v7_exit_coherency_flush(louis);
/*
* We use the cpu jumping argument register to sync with
* imx_cpu_kill() which is running on cpu0 and waiting for
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
deleted file mode 100644
index 29d97bd..0000000
--- a/arch/arm/mach-imx/imx27-dt.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix
- */
-
-#include <linux/irq.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "mx27.h"
-
-static const char * const imx27_dt_board_compat[] __initconst = {
- "fsl,imx27",
- NULL
-};
-
-DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
- .map_io = mx27_map_io,
- .init_early = imx27_init_early,
- .init_irq = mx27_init_irq,
- .init_late = imx27_pm_init,
- .dt_compat = imx27_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
deleted file mode 100644
index abfc306..0000000
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
- */
-#include <linux/gpio.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-
-#include "hardware.h"
-#include "iomux-mx3.h"
-
-/*
- * IOMUX register (base) addresses
- */
-#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
-#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
-#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
-#define IOMUXGPR (IOMUX_BASE + 0x008)
-#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
-#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
-
-static DEFINE_SPINLOCK(gpio_mux_lock);
-
-#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
-
-static DECLARE_BITMAP(mxc_pin_alloc_map, NB_PORTS * 32);
-/*
- * set the mode for a IOMUX pin.
- */
-void mxc_iomux_mode(unsigned int pin_mode)
-{
- u32 field;
- u32 l;
- u32 mode;
- void __iomem *reg;
-
- reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
- field = pin_mode & 0x3;
- mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
-
- spin_lock(&gpio_mux_lock);
-
- l = imx_readl(reg);
- l &= ~(0xff << (field * 8));
- l |= mode << (field * 8);
- imx_writel(l, reg);
-
- spin_unlock(&gpio_mux_lock);
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- */
-void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
-{
- u32 field, l;
- void __iomem *reg;
-
- pin &= IOMUX_PADNUM_MASK;
- reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
- field = (pin + 2) % 3;
-
- pr_debug("%s: reg offset = 0x%x, field = %d\n",
- __func__, (pin + 2) / 3, field);
-
- spin_lock(&gpio_mux_lock);
-
- l = imx_readl(reg);
- l &= ~(0x1ff << (field * 10));
- l |= config << (field * 10);
- imx_writel(l, reg);
-
- spin_unlock(&gpio_mux_lock);
-}
-
-/*
- * allocs a single pin:
- * - reserves the pin so that it is not claimed by another driver
- * - setups the iomux according to the configuration
- */
-int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
-{
- unsigned pad = pin & IOMUX_PADNUM_MASK;
-
- if (pad >= (PIN_MAX + 1)) {
- printk(KERN_ERR "mxc_iomux: Attempt to request nonexistent pin %u for \"%s\"\n",
- pad, label ? label : "?");
- return -EINVAL;
- }
-
- if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
- printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
- pad, label ? label : "?");
- return -EBUSY;
- }
- mxc_iomux_mode(pin);
-
- return 0;
-}
-
-int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
- const char *label)
-{
- const unsigned int *p = pin_list;
- int i;
- int ret = -EINVAL;
-
- for (i = 0; i < count; i++) {
- ret = mxc_iomux_alloc_pin(*p, label);
- if (ret)
- goto setup_error;
- p++;
- }
- return 0;
-
-setup_error:
- mxc_iomux_release_multiple_pins(pin_list, i);
- return ret;
-}
-
-void mxc_iomux_release_pin(unsigned int pin)
-{
- unsigned pad = pin & IOMUX_PADNUM_MASK;
-
- if (pad < (PIN_MAX + 1))
- clear_bit(pad, mxc_pin_alloc_map);
-}
-
-void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
-{
- const unsigned int *p = pin_list;
- int i;
-
- for (i = 0; i < count; i++) {
- mxc_iomux_release_pin(*p);
- p++;
- }
-}
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- */
-void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
-{
- u32 l;
-
- spin_lock(&gpio_mux_lock);
- l = imx_readl(IOMUXGPR);
- if (en)
- l |= gp;
- else
- l &= ~gp;
-
- imx_writel(l, IOMUXGPR);
- spin_unlock(&gpio_mux_lock);
-}
diff --git a/arch/arm/mach-imx/iomux-mx21.h b/arch/arm/mach-imx/iomux-mx21.h
deleted file mode 100644
index 6eab347..0000000
--- a/arch/arm/mach-imx/iomux-mx21.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
- */
-#ifndef __MACH_IOMUX_MX21_H__
-#define __MACH_IOMUX_MX21_H__
-
-#include "iomux-mx2x.h"
-#include "iomux-v1.h"
-
-/* Primary GPIO pin functions */
-
-#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22)
-#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25)
-#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5)
-#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6)
-#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7)
-#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8)
-#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9)
-#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10)
-#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11)
-#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12)
-#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13)
-#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16)
-#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17)
-#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18)
-#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19)
-#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0)
-#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1)
-#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2)
-#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1)
-#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3)
-#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7)
-#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8)
-#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9)
-#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10)
-#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11)
-#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12)
-#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13)
-#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14)
-#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16)
-
-/* Alternate GPIO pin functions */
-
-#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5)
-#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6)
-#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7)
-#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8)
-#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9)
-#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10)
-#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11)
-#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12)
-#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13)
-#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14)
-#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15)
-#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16)
-#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17)
-#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18)
-#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19)
-#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20)
-#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21)
-#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22)
-#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23)
-#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29)
-#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30)
-
-/* AIN GPIO pin functions */
-
-#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
-#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
-#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
-#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
-#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
-#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
-#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
-#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
-#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
-#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
-#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
-#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
-
-/* BIN GPIO pin functions */
-
-#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
-#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
-
-/* CIN GPIO pin functions */
-
-#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
-
-/* AOUT GPIO pin functions */
-
-#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
-#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
-#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
-#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
-#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
-#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
-#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
-#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
-#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
-#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
-#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
-#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
-#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
-#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
-#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
-
-#endif /* ifndef __MACH_IOMUX_MX21_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx27.h b/arch/arm/mach-imx/iomux-mx27.h
deleted file mode 100644
index 4d848d1..0000000
--- a/arch/arm/mach-imx/iomux-mx27.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
- */
-#ifndef __MACH_IOMUX_MX27_H__
-#define __MACH_IOMUX_MX27_H__
-
-#include "iomux-mx2x.h"
-#include "iomux-v1.h"
-
-/* Primary GPIO pin functions */
-
-#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
-#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
-#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
-#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
-#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
-#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
-#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
-#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
-#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
-#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
-#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
-#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
-#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
-#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
-#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
-#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
-#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
-#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
-#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
-#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
-#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0)
-#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1)
-#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2)
-#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3)
-#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4)
-#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5)
-#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6)
-#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7)
-#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8)
-#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9)
-#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10)
-#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11)
-#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12)
-#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13)
-#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14)
-#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15)
-#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16)
-#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
-#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
-#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
-#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
-#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
-#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1)
-#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3)
-#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7)
-#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8)
-#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9)
-#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10)
-#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11)
-#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12)
-#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13)
-#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14)
-#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16)
-#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17)
-#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18)
-#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19)
-#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20)
-#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23)
-
-/* Alternate GPIO pin functions */
-
-#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4)
-#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5)
-#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6)
-#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7)
-#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8)
-#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9)
-#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10)
-#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11)
-#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12)
-#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13)
-#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18)
-#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19)
-#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20)
-#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
-#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
-#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24)
-#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25)
-#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26)
-#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27)
-#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1)
-#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6)
-#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7)
-#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9)
-#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2)
-#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3)
-#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4)
-#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5)
-#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8)
-#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10)
-#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11)
-#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12)
-#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13)
-#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14)
-#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15)
-#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16)
-#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1)
-#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3)
-#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5)
-#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7)
-#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8)
-#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9)
-#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10)
-#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11)
-#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12)
-#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13)
-#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14)
-#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15)
-#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16)
-#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17)
-#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18)
-#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19)
-#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20)
-#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22)
-#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23)
-
-/* AIN GPIO pin functions */
-
-#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
-#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15)
-#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0)
-#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1)
-#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2)
-#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3)
-#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9)
-#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16)
-#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27)
-#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23)
-
-/* BIN GPIO pin functions */
-
-#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
-
-/* CIN GPIO pin functions */
-
-#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2)
-#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3)
-#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4)
-#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5)
-#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6)
-#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7)
-#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8)
-#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9)
-#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10)
-#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11)
-#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12)
-#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13)
-#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14)
-#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15)
-#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16)
-#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23)
-#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27)
-/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */
-
-/* AOUT GPIO pin functions */
-
-#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14)
-#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4)
-#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5)
-#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6)
-#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7)
-#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10)
-#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11)
-#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12)
-#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13)
-#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
-#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
-
-/* BOUT GPIO pin functions */
-
-#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
-#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
-#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
-#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28)
-#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29)
-#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
-#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
-
-#endif /* __MACH_IOMUX_MX27_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx2x.h b/arch/arm/mach-imx/iomux-mx2x.h
deleted file mode 100644
index ce6b6d2..0000000
--- a/arch/arm/mach-imx/iomux-mx2x.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
- */
-#ifndef __MACH_IOMUX_MX2x_H__
-#define __MACH_IOMUX_MX2x_H__
-
-/* Primary GPIO pin functions */
-
-#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
-#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
-#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
-#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
-#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
-#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
-#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
-#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
-#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
-#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
-#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
-#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
-#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
-#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
-#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
-#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
-#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
-#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
-#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
-#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
-#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
-#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
-#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
-#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
-#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
-#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
-#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
-#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
-#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
-#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
-#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
-#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
-#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
-#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10)
-#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11)
-#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12)
-#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13)
-#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14)
-#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15)
-#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16)
-#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17)
-#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18)
-#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19)
-#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20)
-#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21)
-#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23)
-#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24)
-#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26)
-#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27)
-#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28)
-#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29)
-#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30)
-#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31)
-#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14)
-#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15)
-#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20)
-#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21)
-#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22)
-#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23)
-#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24)
-#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25)
-#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26)
-#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27)
-#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28)
-#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29)
-#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30)
-#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
-#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
-#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
-#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
-#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
-#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
-#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
-#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 23)
-#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
-#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
-#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
-#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
-#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
-#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
-#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30)
-#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31)
-#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3)
-#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4)
-#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5)
-#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6)
-#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7)
-#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8)
-#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9)
-#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10)
-#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11)
-#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12)
-#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13)
-#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14)
-#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15)
-#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16)
-#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17)
-#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
-#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
-#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
-#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
-#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
-#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
-#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0)
-#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2)
-#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4)
-#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5)
-#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6)
-#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15)
-#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21)
-#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22)
-
-/* Alternate GPIO pin functions */
-
-#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26)
-#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28)
-#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29)
-#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31)
-#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28)
-#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29)
-#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30)
-#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31)
-#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
-#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
-#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
-#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
-#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
-#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
-#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
-#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0)
-#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1)
-#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2)
-#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3)
-#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4)
-#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6)
-#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7)
-#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16)
-#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18)
-#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21)
-#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22)
-#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23)
-
-/* AIN GPIO pin functions */
-
-#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6)
-#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7)
-#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8)
-#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
-#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11)
-#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13)
-#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15)
-#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
-#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19)
-#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21)
-#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22)
-#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24)
-#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25)
-#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26)
-#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27)
-#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6)
-#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7)
-#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8)
-#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9)
-#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25)
-#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26)
-#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27)
-#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28)
-#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29)
-#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30)
-#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31)
-#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5)
-#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6)
-#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7)
-#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8)
-#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9)
-#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10)
-#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11)
-#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12)
-#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13)
-#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5)
-
-/* BIN GPIO pin functions */
-
-#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5)
-
-/* CIN GPIO pin functions */
-
-#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14)
-#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15)
-#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16)
-#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17)
-#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18)
-#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19)
-#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20)
-#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21)
-#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30)
-#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5)
-
-/* AOUT GPIO pin functions */
-
-#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29)
-#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31)
-#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8)
-#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
-#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
-
-#endif /* ifndef __MACH_IOMUX_MX2x_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
deleted file mode 100644
index 99270a1..0000000
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ /dev/null
@@ -1,706 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- */
-#ifndef __MACH_IOMUX_MX3_H__
-#define __MACH_IOMUX_MX3_H__
-
-#include <linux/types.h>
-/*
- * various IOMUX output functions
- */
-
-#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
-#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
-#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
-#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
-#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
-#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
-#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
-#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
-#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
-#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
-#define IOMUX_ICONFIG_FUNC 2 /* used as function */
-#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
-#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
-
-#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
-#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
-#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
-#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
-
-/*
- * various IOMUX pad functions
- */
-enum iomux_pad_config {
- PAD_CTL_NOLOOPBACK = 0x0 << 9,
- PAD_CTL_LOOPBACK = 0x1 << 9,
- PAD_CTL_PKE_NONE = 0x0 << 8,
- PAD_CTL_PKE_ENABLE = 0x1 << 8,
- PAD_CTL_PUE_KEEPER = 0x0 << 7,
- PAD_CTL_PUE_PUD = 0x1 << 7,
- PAD_CTL_100K_PD = 0x0 << 5,
- PAD_CTL_100K_PU = 0x1 << 5,
- PAD_CTL_47K_PU = 0x2 << 5,
- PAD_CTL_22K_PU = 0x3 << 5,
- PAD_CTL_HYS_CMOS = 0x0 << 4,
- PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
- PAD_CTL_ODE_CMOS = 0x0 << 3,
- PAD_CTL_ODE_OpenDrain = 0x1 << 3,
- PAD_CTL_DRV_NORMAL = 0x0 << 1,
- PAD_CTL_DRV_HIGH = 0x1 << 1,
- PAD_CTL_DRV_MAX = 0x2 << 1,
- PAD_CTL_SRE_SLOW = 0x0 << 0,
- PAD_CTL_SRE_FAST = 0x1 << 0
-};
-
-/*
- * various IOMUX general purpose functions
- */
-enum iomux_gp_func {
- MUX_PGP_FIRI = 1 << 0,
- MUX_DDR_MODE = 1 << 1,
- MUX_PGP_CSPI_BB = 1 << 2,
- MUX_PGP_ATA_1 = 1 << 3,
- MUX_PGP_ATA_2 = 1 << 4,
- MUX_PGP_ATA_3 = 1 << 5,
- MUX_PGP_ATA_4 = 1 << 6,
- MUX_PGP_ATA_5 = 1 << 7,
- MUX_PGP_ATA_6 = 1 << 8,
- MUX_PGP_ATA_7 = 1 << 9,
- MUX_PGP_ATA_8 = 1 << 10,
- MUX_PGP_UH2 = 1 << 11,
- MUX_SDCTL_CSD0_SEL = 1 << 12,
- MUX_SDCTL_CSD1_SEL = 1 << 13,
- MUX_CSPI1_UART3 = 1 << 14,
- MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
- MUX_TAMPER_DETECT_EN = 1 << 16,
- MUX_PGP_USB_4WIRE = 1 << 17,
- MUX_PGP_USB_COMMON = 1 << 18,
- MUX_SDHC_MEMSTICK1 = 1 << 19,
- MUX_SDHC_MEMSTICK2 = 1 << 20,
- MUX_PGP_SPLL_BYP = 1 << 21,
- MUX_PGP_UPLL_BYP = 1 << 22,
- MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
- MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
- MUX_CSPI3_UART5_SEL = 1 << 25,
- MUX_PGP_ATA_9 = 1 << 26,
- MUX_PGP_USB_SUSPEND = 1 << 27,
- MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
- MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
- MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
- MUX_CLKO_DDR_MODE = 1 << 31,
-};
-
-/*
- * setups a single pin:
- * - reserves the pin so that it is not claimed by another driver
- * - setups the iomux according to the configuration
- * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
- */
-int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
-/*
- * setups multiple pins
- * convenient way to call the above function with tables
- */
-int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
- const char *label);
-
-/*
- * releases a single pin:
- * - make it available for a future use by another driver
- * - frees the GPIO if the pin was configured as GPIO
- * - DOES NOT reconfigure the IOMUX in its reset state
- */
-void mxc_iomux_release_pin(unsigned int pin);
-/*
- * releases multiple pins
- * convenvient way to call the above function with tables
- */
-void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- */
-void mxc_iomux_set_gpr(enum iomux_gp_func, bool en);
-
-/*
- * This function only configures the iomux hardware.
- * It is called by the setup functions and should not be called directly anymore.
- * It is here visible for backward compatibility
- */
-void mxc_iomux_mode(unsigned int pin_mode);
-
-#define IOMUX_PADNUM_MASK 0x1ff
-#define IOMUX_GPIONUM_SHIFT 9
-#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
-#define IOMUX_MODE_SHIFT 17
-#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT)
-
-#define IOMUX_PIN(gpionum, padnum) \
- (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
- (padnum & IOMUX_PADNUM_MASK))
-
-#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
-
-#define IOMUX_TO_GPIO(iomux_pin) \
- ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-
-enum iomux_pins {
- MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
- MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
- MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
- MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
- MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
- MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
- MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
- MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
- MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
- MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
- MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
- MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
- MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
- MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
- MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
- MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
- MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
- MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
- MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
- MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
- MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
- MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
- MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
- MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
- MX31_PIN_READ = IOMUX_PIN(0xff, 24),
- MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
- MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
- MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
- MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
- MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
- MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
- MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
- MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
- MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
- MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
- MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
- MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
- MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
- MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
- MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
- MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
- MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
- MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
- MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
- MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
- MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
- MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
- MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
- MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
- MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
- MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
- MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
- MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
- MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
- MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
- MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
- MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
- MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
- MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
- MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
- MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
- MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
- MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
- MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
- MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
- MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
- MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
- MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
- MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
- MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
- MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
- MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
- MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
- MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
- MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
- MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
- MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
- MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
- MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
- MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
- MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
- MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
- MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
- MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
- MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
- MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
- MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
- MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
- MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
- MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
- MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
- MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
- MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
- MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
- MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
- MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
- MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
- MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
- MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
- MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
- MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
- MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
- MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
- MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
- MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
- MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
- MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
- MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
- MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
- MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
- MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
- MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
- MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
- MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
- MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
- MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
- MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
- MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
- MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
- MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
- MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
- MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
- MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
- MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
- MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
- MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
- MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
- MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
- MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
- MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
- MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
- MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
- MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
- MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
- MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
- MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
- MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
- MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
- MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
- MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
- MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
- MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
- MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
- MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
- MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
- MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
- MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
- MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
- MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
- MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
- MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
- MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
- MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
- MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
- MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
- MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
- MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
- MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
- MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
- MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
- MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
- MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
- MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
- MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
- MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
- MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
- MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
- MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
- MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
- MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
- MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
- MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
- MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
- MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
- MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
- MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
- MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
- MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
- MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
- MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
- MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
- MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
- MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
- MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
- MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
- MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
- MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
- MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
- MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
- MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
- MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
- MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
- MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
- MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
- MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
- MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
- MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
- MX31_PIN_NFRB = IOMUX_PIN(16, 197),
- MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
- MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
- MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
- MX31_PIN_NFALE = IOMUX_PIN(12, 201),
- MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
- MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
- MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
- MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
- MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
- MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
- MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
- MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
- MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
- MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
- MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
- MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
- MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
- MX31_PIN_RW = IOMUX_PIN(0xff, 215),
- MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
- MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
- MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
- MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
- MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
- MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
- MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
- MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
- MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
- MX31_PIN_OE = IOMUX_PIN(0xff, 225),
- MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
- MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
- MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
- MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
- MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
- MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
- MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
- MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
- MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
- MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
- MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
- MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
- MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
- MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
- MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
- MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
- MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
- MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
- MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
- MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
- MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
- MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
- MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
- MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
- MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
- MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
- MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
- MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
- MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
- MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
- MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
- MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
- MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
- MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
- MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
- MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
- MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
- MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
- MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
- MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
- MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
- MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
- MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
- MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
- MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
- MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
- MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
- MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
- MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
- MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
- MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
- MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
- MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
- MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
- MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
- MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
- MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
- MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
- MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
- MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
- MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
- MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
- MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
- MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
- MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
- MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
- MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
- MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
- MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
- MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
- MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
- MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
- MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
- MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
- MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
- MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
- MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
- MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
- MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
- MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
- MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
- MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
- MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
- MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
- MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
- MX31_PIN_STX0 = IOMUX_PIN(33, 311),
- MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
- MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
- MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
- MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
- MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
- MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317),
- MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318),
- MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319),
- MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320),
- MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321),
- MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322),
- MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323),
- MX31_PIN_PWMO = IOMUX_PIN( 9, 324),
- MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
- MX31_PIN_COMPARE = IOMUX_PIN( 8, 326),
- MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327),
-};
-
-#define PIN_MAX 327
-#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */
-
-/*
- * Convenience values for use with mxc_iomux_mode()
- *
- * Format here is MX31_PIN_(pin name)__(function)
- */
-#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI3_SCLK__RTS3 IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RTS1__SFS IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_TXD1__SCK IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RXD1__STXDA IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DTR_DCE1__SRXDA IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
-#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI2_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2)
-#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI2_SCLK__I2C3_SCL IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
-#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW4_GPIO IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
-#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC)
-#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC)
-
-
-/*
- * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
- * cspi2_ss1, cspi1_ss0 cspi1_ss1
- */
-
-/*
- * This function configures the pad value for a IOMUX pin.
- */
-void mxc_iomux_set_pad(enum iomux_pins, u32);
-
-#endif /* ifndef __MACH_IOMUX_MX3_H__ */
diff --git a/arch/arm/mach-imx/iomux-mx35.h b/arch/arm/mach-imx/iomux-mx35.h
deleted file mode 100644
index 7fb5259..0000000
--- a/arch/arm/mach-imx/iomux-mx35.h
+++ /dev/null
@@ -1,1254 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
- */
-
-#ifndef __MACH_IOMUX_MX35_H__
-#define __MACH_IOMUX_MX35_H__
-
-#include "iomux-v3.h"
-
-/*
- * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num> see also iomux-v3.h
- */
-
-/* PAD MUX ALT INPSE PATH */
-#define MX35_PAD_CAPTURE__GPT_CAPIN1 IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__GPT_CMPOUT2 IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__CSPI2_SS1 IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__EPIT1_EPITO IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__CCM_CLK32K IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CAPTURE__GPIO1_4 IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_COMPARE__GPT_CMPOUT1 IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__GPT_CAPIN2 IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__GPT_CMPOUT3 IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__EPIT2_EPITO IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__GPIO1_5 IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL)
-#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_WDOG_RST__WDOG_WDOG_B IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_WDOG_RST__GPIO1_6 IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_0__OWIRE_LINE IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__PWM_PWMO IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__CSPI1_SS2 IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO2_0__GPIO2_0 IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_GPIO3_0__GPIO3_0 IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL)
-#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_POR_B__CCM_POR_B IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CLKO__CCM_CLKO IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CLKO__GPIO1_8 IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_VSTBY__CCM_VSTBY IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_VSTBY__GPIO1_7 IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A0__EMI_EIM_DA_L_0 IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A1__EMI_EIM_DA_L_1 IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A2__EMI_EIM_DA_L_2 IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A3__EMI_EIM_DA_L_3 IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A4__EMI_EIM_DA_L_4 IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A5__EMI_EIM_DA_L_5 IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A6__EMI_EIM_DA_L_6 IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A7__EMI_EIM_DA_L_7 IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A8__EMI_EIM_DA_H_8 IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A9__EMI_EIM_DA_H_9 IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A10__EMI_EIM_DA_H_10 IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_MA10__EMI_MA10 IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A11__EMI_EIM_DA_H_11 IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A12__EMI_EIM_DA_H_12 IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A13__EMI_EIM_DA_H_13 IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A14__EMI_EIM_DA_H2_14 IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A15__EMI_EIM_DA_H2_15 IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A16__EMI_EIM_A_16 IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A17__EMI_EIM_A_17 IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A18__EMI_EIM_A_18 IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A19__EMI_EIM_A_19 IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A20__EMI_EIM_A_20 IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A21__EMI_EIM_A_21 IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A22__EMI_EIM_A_22 IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A23__EMI_EIM_A_23 IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A24__EMI_EIM_A_24 IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_A25__EMI_EIM_A_25 IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD0__EMI_DRAM_D_0 IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1__EMI_DRAM_D_1 IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2__EMI_DRAM_D_2 IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD3__EMI_DRAM_D_3 IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD4__EMI_DRAM_D_4 IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD5__EMI_DRAM_D_5 IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD6__EMI_DRAM_D_6 IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD7__EMI_DRAM_D_7 IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD8__EMI_DRAM_D_8 IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD9__EMI_DRAM_D_9 IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD10__EMI_DRAM_D_10 IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD11__EMI_DRAM_D_11 IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD12__EMI_DRAM_D_12 IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD13__EMI_DRAM_D_13 IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD14__EMI_DRAM_D_14 IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD15__EMI_DRAM_D_15 IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD16__EMI_DRAM_D_16 IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD17__EMI_DRAM_D_17 IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD18__EMI_DRAM_D_18 IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD19__EMI_DRAM_D_19 IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD20__EMI_DRAM_D_20 IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD21__EMI_DRAM_D_21 IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD22__EMI_DRAM_D_22 IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD23__EMI_DRAM_D_23 IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD24__EMI_DRAM_D_24 IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD25__EMI_DRAM_D_25 IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD26__EMI_DRAM_D_26 IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD27__EMI_DRAM_D_27 IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD28__EMI_DRAM_D_28 IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD29__EMI_DRAM_D_29 IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD30__EMI_DRAM_D_30 IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD31__EMI_DRAM_D_31 IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_EB0__EMI_EIM_EB0_B IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_EB1__EMI_EIM_EB1_B IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_OE__EMI_EIM_OE IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS0__EMI_EIM_CS0 IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS1__EMI_EIM_CS1 IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS1__EMI_NANDF_CE3 IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS2__EMI_EIM_CS2 IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS3__EMI_EIM_CS3 IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS4__EMI_EIM_CS4 IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS4__EMI_DTACK_B IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS4__EMI_NANDF_CE1 IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS4__GPIO1_20 IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CS5__EMI_EIM_CS5 IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS5__CSPI2_SS2 IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS5__CSPI1_SS2 IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL)
-#define MX35_PAD_CS5__EMI_NANDF_CE2 IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CS5__GPIO1_21 IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NF_CE0__GPIO1_22 IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ECB__EMI_EIM_ECB IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LBA__EMI_EIM_LBA IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_BCLK__EMI_EIM_BCLK IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_RW__EMI_EIM_RW IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_RAS__EMI_DRAM_RAS IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CAS__EMI_DRAM_CAS IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDWE__EMI_DRAM_SDWE IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__GPIO2_18 IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__GPIO2_19 IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFALE__EMI_NANDF_ALE IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__USB_TOP_USBH2_STP IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__IPU_DISPB_CS0 IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__GPIO2_20 IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFCLE__EMI_NANDF_CLE IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__GPIO2_21 IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__IPU_DISPB_WR IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__GPIO2_22 IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_NFRB__EMI_NANDF_RB IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRB__IPU_DISPB_RD IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRB__GPIO2_23 IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL)
-#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D15__EMI_EIM_D_15 IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D14__EMI_EIM_D_14 IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D13__EMI_EIM_D_13 IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D12__EMI_EIM_D_12 IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D11__EMI_EIM_D_11 IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D10__EMI_EIM_D_10 IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D9__EMI_EIM_D_9 IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D8__EMI_EIM_D_8 IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D7__EMI_EIM_D_7 IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D6__EMI_EIM_D_6 IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D5__EMI_EIM_D_5 IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D4__EMI_EIM_D_4 IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3__EMI_EIM_D_3 IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D2__EMI_EIM_D_2 IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D1__EMI_EIM_D_1 IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D0__EMI_EIM_D_0 IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D8__IPU_CSI_D_8 IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D8__KPP_COL_0 IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D8__GPIO1_20 IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D9__IPU_CSI_D_9 IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D9__KPP_COL_1 IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D9__GPIO1_21 IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D10__IPU_CSI_D_10 IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D10__KPP_COL_2 IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D10__GPIO1_22 IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D11__IPU_CSI_D_11 IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D11__KPP_COL_3 IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D11__GPIO1_23 IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D12__IPU_CSI_D_12 IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D12__KPP_ROW_0 IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D12__GPIO1_24 IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D13__IPU_CSI_D_13 IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D13__KPP_ROW_1 IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D13__GPIO1_25 IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D14__IPU_CSI_D_14 IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D14__KPP_ROW_2 IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D14__GPIO1_26 IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_D15__IPU_CSI_D_15 IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D15__KPP_ROW_3 IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_D15__GPIO1_27 IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_MCLK__GPIO1_28 IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_VSYNC__GPIO1_29 IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_HSYNC__GPIO1_30 IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSI_PIXCLK__GPIO1_31 IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C1_CLK__I2C1_SCL IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C1_CLK__GPIO2_24 IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C1_DAT__I2C1_SDA IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C1_DAT__GPIO2_25 IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C2_CLK__I2C2_SCL IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__CAN1_TXCAN IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__GPIO2_26 IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_I2C2_DAT__I2C2_SDA IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__CAN1_RXCAN IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__GPIO2_27 IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL)
-#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXD4__GPIO2_28 IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD4__GPIO2_29 IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK4__GPIO2_30 IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS4__GPIO2_31 IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__CSPI2_MOSI IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__GPIO1_0 IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL)
-#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__CSPI2_MISO IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__GPIO1_1 IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL)
-#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__CSPI2_SCLK IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__GPIO1_2 IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS5__CSPI2_RDY IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS5__GPIO1_3 IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL)
-#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCKR__ESAI_SCKR IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCKR__GPIO1_4 IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL)
-#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FSR__ESAI_FSR IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FSR__GPIO1_5 IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL)
-#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_HCKR__ESAI_HCKR IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__CSPI2_SS0 IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__IPU_FLASH_STROBE IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__GPIO1_6 IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL)
-#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SCKT__ESAI_SCKT IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCKT__GPIO1_7 IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL)
-#define MX35_PAD_SCKT__IPU_CSI_D_0 IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL)
-#define MX35_PAD_SCKT__KPP_ROW_2 IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_FST__ESAI_FST IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FST__GPIO1_8 IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL)
-#define MX35_PAD_FST__IPU_CSI_D_1 IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL)
-#define MX35_PAD_FST__KPP_ROW_3 IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_HCKT__ESAI_HCKT IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__GPIO1_9 IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__IPU_CSI_D_2 IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL)
-#define MX35_PAD_HCKT__KPP_COL_3 IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__CSPI2_SS2 IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__CAN2_TXCAN IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__UART2_DTR IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__GPIO1_10 IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__CSPI2_SS3 IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__CAN2_RXCAN IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__UART2_DSR IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__GPIO1_11 IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX4_RX1__KPP_ROW_0 IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__I2C3_SCL IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__GPIO1_12 IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX3_RX2__KPP_ROW_1 IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__I2C3_SDA IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__GPIO1_13 IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX2_RX3__KPP_COL_0 IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX1__ESAI_TX1 IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__CCM_PMIC_RDY IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX1__CSPI1_SS2 IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL)
-#define MX35_PAD_TX1__EMI_NANDF_CE3 IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__UART2_RI IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__GPIO1_14 IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__IPU_CSI_D_6 IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX1__KPP_COL_1 IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_TX0__ESAI_TX0 IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX0__CSPI1_SS3 IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__EMI_DTACK_B IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL)
-#define MX35_PAD_TX0__UART2_DCD IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__GPIO1_15 IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__IPU_CSI_D_7 IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL)
-#define MX35_PAD_TX0__KPP_COL_2 IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MOSI__GPIO1_16 IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MISO__GPIO1_17 IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__OWIRE_LINE IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__GPIO1_18 IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__PWM_PWMO IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__CCM_CLK32K IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__GPIO1_19 IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SCLK__GPIO3_4 IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_RXD1__UART1_RXD_MUX IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__CSPI2_MOSI IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__KPP_COL_4 IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__GPIO3_6 IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TXD1__UART1_TXD_MUX IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__CSPI2_MISO IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__KPP_COL_5 IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__GPIO3_7 IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_RTS1__UART1_RTS IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__CSPI2_SCLK IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__I2C3_SCL IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__IPU_CSI_D_0 IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__KPP_COL_6 IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__GPIO3_8 IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__EMI_NANDF_CE1 IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CTS1__UART1_CTS IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__CSPI2_RDY IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__I2C3_SDA IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__IPU_CSI_D_1 IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__KPP_COL_7 IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__GPIO3_9 IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__EMI_NANDF_CE2 IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_RXD2__UART2_RXD_MUX IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD2__KPP_ROW_4 IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL)
-#define MX35_PAD_RXD2__GPIO3_10 IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TXD2__UART2_TXD_MUX IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL)
-#define MX35_PAD_TXD2__KPP_ROW_5 IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL)
-#define MX35_PAD_TXD2__GPIO3_11 IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_RTS2__UART2_RTS IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__CAN2_RXCAN IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__IPU_CSI_D_2 IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__KPP_ROW_6 IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__GPIO3_12 IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_RTS2__UART3_RXD_MUX IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CTS2__UART2_CTS IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__CAN2_TXCAN IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__IPU_CSI_D_3 IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__KPP_ROW_7 IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__GPIO3_13 IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CTS2__UART3_TXD_MUX IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_RTCK__ARM11P_TOP_RTCK IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TCK__SJC_TCK IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TMS__SJC_TMS IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TDI__SJC_TDI IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TDO__SJC_TDO IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TRSTB__SJC_TRSTB IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_DE_B__SJC_DE_B IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SJC_MOD__SJC_MOD IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_PWR__GPIO3_14 IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL)
-#define MX35_PAD_USBOTG_OC__GPIO3_15 IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD0__IPU_DISPB_DAT_0 IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD0__GPIO2_0 IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD1__IPU_DISPB_DAT_1 IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD1__GPIO2_1 IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD2__IPU_DISPB_DAT_2 IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD2__GPIO2_2 IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD3__IPU_DISPB_DAT_3 IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD3__GPIO2_3 IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD4__IPU_DISPB_DAT_4 IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD4__GPIO2_4 IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD5__IPU_DISPB_DAT_5 IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD5__GPIO2_5 IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD6__IPU_DISPB_DAT_6 IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD6__GPIO2_6 IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD7__IPU_DISPB_DAT_7 IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD7__GPIO2_7 IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD8__IPU_DISPB_DAT_8 IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD8__GPIO2_8 IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD10__GPIO2_10 IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD11__IPU_DISPB_DAT_11 IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD11__GPIO2_11 IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD12__IPU_DISPB_DAT_12 IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD12__GPIO2_12 IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD13__IPU_DISPB_DAT_13 IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD13__GPIO2_13 IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD14__IPU_DISPB_DAT_14 IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD14__GPIO2_14 IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD15__IPU_DISPB_DAT_15 IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD15__GPIO2_15 IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD16__IPU_DISPB_DAT_16 IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__GPIO2_16 IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD17__IPU_DISPB_DAT_17 IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__IPU_DISPB_CS2 IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__GPIO2_17 IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD18__IPU_DISPB_DAT_18 IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD18__ESDHC3_CMD IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__GPIO3_24 IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD19__IPU_DISPB_DAT_19 IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__IPU_DISPB_BCLK IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__IPU_DISPB_CS1 IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__ESDHC3_CLK IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__GPIO3_25 IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD20__IPU_DISPB_DAT_20 IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__IPU_DISPB_CS0 IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__IPU_DISPB_SD_CLK IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__ESDHC3_DAT0 IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__GPIO3_26 IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD21__IPU_DISPB_DAT_21 IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__IPU_DISPB_PAR_RS IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__IPU_DISPB_SER_RS IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__ESDHC3_DAT1 IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__USB_TOP_USBOTG_STP IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__GPIO3_27 IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD22__IPU_DISPB_DAT_22 IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__IPU_DISPB_WR IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__IPU_DISPB_SD_D_I IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__ESDHC3_DAT2 IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__GPIO3_28 IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD22__ARM11P_TOP_TRCTL IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_LD23__IPU_DISPB_DAT_23 IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__IPU_DISPB_RD IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL)
-#define MX35_PAD_LD23__ESDHC3_DAT3 IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__GPIO3_29 IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_LD23__ARM11P_TOP_TRCLK IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__GPIO3_30 IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__GPIO3_31 IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__GPIO1_0 IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CONTRAST__GPIO1_1 IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL)
-#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__GPIO1_2 IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__GPIO1_3 IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__GPIO1_4 IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__GPIO1_5 IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__MSHC_SCLK IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__GPIO1_6 IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__MSHC_BS IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__GPIO1_7 IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__GPIO1_8 IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__GPIO1_9 IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__GPIO1_10 IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__GPIO1_11 IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__I2C3_SCL IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__GPIO2_0 IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__I2C3_SDA IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__GPIO2_1 IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL)
-#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__GPIO2_2 IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA1__GPIO2_3 IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__UART3_RTS IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__CAN1_RXCAN IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA2__GPIO2_4 IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__UART3_CTS IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__CAN1_TXCAN IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD2_DATA3__GPIO2_5 IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_CS0__ATA_CS0 IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__CSPI1_SS3 IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__GPIO2_6 IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_CS1__ATA_CS1 IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__CSPI2_SS0 IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__GPIO2_7 IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DIOR__ATA_DIOR IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__CSPI2_SS1 IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__GPIO2_8 IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DIOW__ATA_DIOW IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__CSPI2_MOSI IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__GPIO2_9 IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DMACK__ATA_DMACK IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__CSPI2_MISO IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__GPIO2_10 IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_RESET_B__ATA_RESET_B IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__CSPI2_RDY IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__GPIO2_11 IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_IORDY__ATA_IORDY IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__GPIO2_12 IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA0__ATA_DATA_0 IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__GPIO2_13 IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA1__ATA_DATA_1 IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__GPIO2_14 IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA2__ATA_DATA_2 IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__GPIO2_15 IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__GPIO2_17 IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA5__ATA_DATA_5 IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__GPIO2_18 IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA6__ATA_DATA_6 IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__CAN1_TXCAN IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__UART1_DTR IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__GPIO2_19 IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA7__ATA_DATA_7 IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__CAN1_RXCAN IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__UART1_DSR IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__GPIO2_20 IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA8__ATA_DATA_8 IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__UART3_RTS IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__UART1_RI IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__GPIO2_21 IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA9__ATA_DATA_9 IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__UART3_CTS IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__UART1_DCD IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__GPIO2_22 IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA10__ATA_DATA_10 IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__GPIO2_23 IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA11__ATA_DATA_11 IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__GPIO2_24 IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA12__ATA_DATA_12 IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA12__I2C3_SCL IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA12__GPIO2_25 IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA13__ATA_DATA_13 IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA13__I2C3_SDA IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA13__GPIO2_26 IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA14__ATA_DATA_14 IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__KPP_ROW_0 IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__GPIO2_27 IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DATA15__ATA_DATA_15 IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__KPP_ROW_1 IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__GPIO2_28 IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_INTRQ__ATA_INTRQ IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__GPIO2_29 IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DMARQ__ATA_DMARQ IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__KPP_COL_0 IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__GPIO2_31 IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DA0__ATA_DA_0 IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__KPP_COL_1 IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__GPIO3_0 IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DA1__ATA_DA_1 IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__KPP_COL_2 IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__GPIO3_1 IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_ATA_DA2__ATA_DA_2 IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__KPP_COL_3 IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__GPIO3_2 IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_MLB_CLK__MLB_MLBCLK IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_MLB_CLK__GPIO3_3 IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_MLB_DAT__MLB_MLBDAT IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_MLB_DAT__GPIO3_4 IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_MLB_SIG__MLB_MLBSIG IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_MLB_SIG__GPIO3_5 IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__GPIO3_6 IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__GPIO3_7 IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__UART3_RTS IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__GPIO3_8 IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_COL__FEC_COL IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__ESDHC1_DAT7 IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__UART3_CTS IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__CSPI2_RDY IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__GPIO3_9 IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__PWM_PWMO IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__UART3_DTR IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__GPIO3_10 IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__UART3_DSR IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__GPIO3_11 IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__UART3_RI IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__GPIO3_12 IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__CAN2_TXCAN IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__UART3_DCD IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__GPIO3_13 IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__IPU_DISPB_WR IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__CAN2_RXCAN IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__GPIO3_14 IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__GPIO3_15 IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__GPIO3_16 IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_CRS__FEC_CRS IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__KPP_COL_5 IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__GPIO3_17 IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__KPP_COL_6 IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__GPIO3_18 IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__KPP_COL_7 IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__GPIO3_19 IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA2__GPIO3_20 IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA2__GPIO3_21 IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_RDATA3__GPIO3_22 IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL)
-#define MX35_PAD_FEC_TDATA3__GPIO3_23 IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-#define MX35_PAD_TEST_MODE__TCU_TEST_MODE IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-
-
-#endif /* __MACH_IOMUX_MX35_H__ */
diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c
deleted file mode 100644
index a4bec3b..0000000
--- a/arch/arm/mach-imx/iomux-v1.c
+++ /dev/null
@@ -1,174 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/plat-mxc/iomux-v1.c
- *
- * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
- * Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix
- *
- * Common code for i.MX1, i.MX21 and i.MX27
- */
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/map.h>
-
-#include "hardware.h"
-#include "iomux-v1.h"
-
-static void __iomem *imx_iomuxv1_baseaddr;
-static unsigned imx_iomuxv1_numports;
-
-static inline unsigned long imx_iomuxv1_readl(unsigned offset)
-{
- return imx_readl(imx_iomuxv1_baseaddr + offset);
-}
-
-static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset)
-{
- imx_writel(val, imx_iomuxv1_baseaddr + offset);
-}
-
-static inline void imx_iomuxv1_rmwl(unsigned offset,
- unsigned long mask, unsigned long value)
-{
- unsigned long reg = imx_iomuxv1_readl(offset);
-
- reg &= ~mask;
- reg |= value;
-
- imx_iomuxv1_writel(reg, offset);
-}
-
-static inline void imx_iomuxv1_set_puen(
- unsigned int port, unsigned int pin, int on)
-{
- unsigned long mask = 1 << pin;
-
- imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0);
-}
-
-static inline void imx_iomuxv1_set_ddir(
- unsigned int port, unsigned int pin, int out)
-{
- unsigned long mask = 1 << pin;
-
- imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0);
-}
-
-static inline void imx_iomuxv1_set_gpr(
- unsigned int port, unsigned int pin, int af)
-{
- unsigned long mask = 1 << pin;
-
- imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0);
-}
-
-static inline void imx_iomuxv1_set_gius(
- unsigned int port, unsigned int pin, int inuse)
-{
- unsigned long mask = 1 << pin;
-
- imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0);
-}
-
-static inline void imx_iomuxv1_set_ocr(
- unsigned int port, unsigned int pin, unsigned int ocr)
-{
- unsigned long shift = (pin & 0xf) << 1;
- unsigned long mask = 3 << shift;
- unsigned long value = ocr << shift;
- unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port);
-
- imx_iomuxv1_rmwl(offset, mask, value);
-}
-
-static inline void imx_iomuxv1_set_iconfa(
- unsigned int port, unsigned int pin, unsigned int aout)
-{
- unsigned long shift = (pin & 0xf) << 1;
- unsigned long mask = 3 << shift;
- unsigned long value = aout << shift;
- unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port);
-
- imx_iomuxv1_rmwl(offset, mask, value);
-}
-
-static inline void imx_iomuxv1_set_iconfb(
- unsigned int port, unsigned int pin, unsigned int bout)
-{
- unsigned long shift = (pin & 0xf) << 1;
- unsigned long mask = 3 << shift;
- unsigned long value = bout << shift;
- unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port);
-
- imx_iomuxv1_rmwl(offset, mask, value);
-}
-
-int mxc_gpio_mode(int gpio_mode)
-{
- unsigned int pin = gpio_mode & GPIO_PIN_MASK;
- unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
- unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
- unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3;
- unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3;
-
- if (port >= imx_iomuxv1_numports)
- return -EINVAL;
-
- /* Pullup enable */
- imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN);
-
- /* Data direction */
- imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT);
-
- /* Primary / alternate function */
- imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF);
-
- /* use as gpio? */
- imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF)));
-
- imx_iomuxv1_set_ocr(port, pin, ocr);
-
- imx_iomuxv1_set_iconfa(port, pin, aout);
-
- imx_iomuxv1_set_iconfb(port, pin, bout);
-
- return 0;
-}
-
-static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
-{
- size_t i;
- int ret = 0;
-
- for (i = 0; i < count; ++i) {
- ret = mxc_gpio_mode(list[i]);
-
- if (ret)
- return ret;
- }
-
- return ret;
-}
-
-int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
- const char *label)
-{
- int ret;
-
- ret = imx_iomuxv1_setup_multiple(pin_list, count);
- return ret;
-}
-
-int __init imx_iomuxv1_init(void __iomem *base, int numports)
-{
- imx_iomuxv1_baseaddr = base;
- imx_iomuxv1_numports = numports;
-
- return 0;
-}
diff --git a/arch/arm/mach-imx/iomux-v1.h b/arch/arm/mach-imx/iomux-v1.h
deleted file mode 100644
index b948529..0000000
--- a/arch/arm/mach-imx/iomux-v1.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
- */
-#ifndef __MACH_IOMUX_V1_H__
-#define __MACH_IOMUX_V1_H__
-
-/*
-* GPIO Module and I/O Multiplexer
-* x = 0..3 for reg_A, reg_B, reg_C, reg_D
-*/
-#define MXC_DDIR(x) (0x00 + ((x) << 8))
-#define MXC_OCR1(x) (0x04 + ((x) << 8))
-#define MXC_OCR2(x) (0x08 + ((x) << 8))
-#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
-#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
-#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
-#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
-#define MXC_DR(x) (0x1c + ((x) << 8))
-#define MXC_GIUS(x) (0x20 + ((x) << 8))
-#define MXC_SSR(x) (0x24 + ((x) << 8))
-#define MXC_ICR1(x) (0x28 + ((x) << 8))
-#define MXC_ICR2(x) (0x2c + ((x) << 8))
-#define MXC_IMR(x) (0x30 + ((x) << 8))
-#define MXC_ISR(x) (0x34 + ((x) << 8))
-#define MXC_GPR(x) (0x38 + ((x) << 8))
-#define MXC_SWR(x) (0x3c + ((x) << 8))
-#define MXC_PUEN(x) (0x40 + ((x) << 8))
-
-#define MX1_NUM_GPIO_PORT 4
-#define MX21_NUM_GPIO_PORT 6
-#define MX27_NUM_GPIO_PORT 6
-
-#define GPIO_PIN_MASK 0x1f
-
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
-
-#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
-#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
-#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
-#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
-#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
-#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-
-#define GPIO_OUT (1 << 8)
-#define GPIO_IN (0 << 8)
-#define GPIO_PUEN (1 << 9)
-
-#define GPIO_PF (1 << 10)
-#define GPIO_AF (1 << 11)
-
-#define GPIO_OCR_SHIFT 12
-#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
-#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
-#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
-#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
-#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
-
-#define GPIO_AOUT_SHIFT 14
-#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
-#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
-
-#define GPIO_BOUT_SHIFT 16
-#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
-#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
-
-extern int mxc_gpio_mode(int gpio_mode);
-extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
- const char *label);
-
-extern int imx_iomuxv1_init(void __iomem *base, int numports);
-
-#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c
deleted file mode 100644
index 043cf3c..0000000
--- a/arch/arm/mach-imx/iomux-v3.c
+++ /dev/null
@@ -1,65 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- * <armlinux@phytec.de>
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/map.h>
-
-#include "hardware.h"
-#include "iomux-v3.h"
-
-static void __iomem *base;
-
-/*
- * configures a single pad in the iomuxer
- */
-int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
-{
- u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
- u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
- u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
- u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
- u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
- u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
-
- if (mux_ctrl_ofs)
- imx_writel(mux_mode, base + mux_ctrl_ofs);
-
- if (sel_input_ofs)
- imx_writel(sel_input, base + sel_input_ofs);
-
- if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
- imx_writel(pad_ctrl, base + pad_ctrl_ofs);
-
- return 0;
-}
-
-int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
- unsigned count)
-{
- const iomux_v3_cfg_t *p = pad_list;
- int i;
- int ret;
-
- for (i = 0; i < count; i++) {
- ret = mxc_iomux_v3_setup_pad(*p);
- if (ret)
- return ret;
- p++;
- }
- return 0;
-}
-
-void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
-{
- base = iomux_v3_base;
-}
diff --git a/arch/arm/mach-imx/iomux-v3.h b/arch/arm/mach-imx/iomux-v3.h
deleted file mode 100644
index 7db8ec9..0000000
--- a/arch/arm/mach-imx/iomux-v3.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- * <armlinux@phytec.de>
- */
-
-#ifndef __MACH_IOMUX_V3_H__
-#define __MACH_IOMUX_V3_H__
-
-/*
- * build IOMUX_PAD structure
- *
- * This iomux scheme is based around pads, which are the physical balls
- * on the processor.
- *
- * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
- * things like driving strength and pullup/pulldown.
- * - Each pad can have but not necessarily does have an output routing register
- * (IOMUXC_SW_MUX_CTL_PAD_x).
- * - Each pad can have but not necessarily does have an input routing register
- * (IOMUXC_x_SELECT_INPUT)
- *
- * The three register sets do not have a fixed offset to each other,
- * hence we order this table by pad control registers (which all pads
- * have) and put the optional i/o routing registers into additional
- * fields.
- *
- * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num>
- *
- * IOMUX/PAD Bit field definitions
- *
- * MUX_CTRL_OFS: 0..11 (12)
- * PAD_CTRL_OFS: 12..23 (12)
- * SEL_INPUT_OFS: 24..35 (12)
- * MUX_MODE + SION: 36..40 (5)
- * PAD_CTRL + NO_PAD_CTRL: 41..57 (17)
- * SEL_INP: 58..61 (4)
- * reserved: 63 (1)
-*/
-
-typedef u64 iomux_v3_cfg_t;
-
-#define MUX_CTRL_OFS_SHIFT 0
-#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
-#define MUX_PAD_CTRL_OFS_SHIFT 12
-#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)
-#define MUX_SEL_INPUT_OFS_SHIFT 24
-#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)
-
-#define MUX_MODE_SHIFT 36
-#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
-#define MUX_PAD_CTRL_SHIFT 41
-#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
-#define MUX_SEL_INPUT_SHIFT 58
-#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
-
-#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
-
-#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
- _sel_input, _pad_ctrl) \
- (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
- ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \
- ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
- ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
- ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
- ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
-
-#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))
-/*
- * Use to set PAD control
- */
-
-#define NO_PAD_CTRL (1 << 16)
-#define PAD_CTL_DVS (1 << 13)
-#define PAD_CTL_HYS (1 << 8)
-
-#define PAD_CTL_PKE (1 << 7)
-#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
-
-#define PAD_CTL_ODE (1 << 3)
-
-#define PAD_CTL_DSE_LOW (0 << 1)
-#define PAD_CTL_DSE_MED (1 << 1)
-#define PAD_CTL_DSE_HIGH (2 << 1)
-#define PAD_CTL_DSE_MAX (3 << 1)
-
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
-#define IOMUX_CONFIG_SION (0x1 << 4)
-
-#define MX51_NUM_GPIO_PORT 4
-
-#define GPIO_PIN_MASK 0x1f
-
-#define GPIO_PORT_SHIFT 5
-#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
-
-#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
-#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
-#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
-#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
-#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
-#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-
-/*
- * setups a single pad in the iomuxer
- */
-int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-
-/*
- * setups multiple pads
- * convenient way to call the above function with tables
- */
-int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,
- unsigned count);
-
-/*
- * Initialise the iomux controller
- */
-void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
-
-#endif /* __MACH_IOMUX_V3_H__*/
-
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
deleted file mode 100644
index 4d9a56f..0000000
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ /dev/null
@@ -1,562 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * armadillo5x0.c
- *
- * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
- * updates in http://alberdroid.blogspot.com/
- *
- * Based on Atmark Techno, Inc. armadillo 500 BSP 2008
- * Based on mx31ads.c and pcm037.c Great Work!
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/smsc911x.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/delay.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices-imx31.h"
-#include "crmregs-imx3.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
-
-static int armadillo5x0_pins[] = {
- /* UART1 */
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
- /* UART2 */
- MX31_PIN_CTS2__CTS2,
- MX31_PIN_RTS2__RTS2,
- MX31_PIN_TXD2__TXD2,
- MX31_PIN_RXD2__RXD2,
- /* LAN9118_IRQ */
- IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO),
- /* SDHC1 */
- MX31_PIN_SD1_DATA3__SD1_DATA3,
- MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA1__SD1_DATA1,
- MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_CLK__SD1_CLK,
- MX31_PIN_SD1_CMD__SD1_CMD,
- /* Framebuffer */
- MX31_PIN_LD0__LD0,
- MX31_PIN_LD1__LD1,
- MX31_PIN_LD2__LD2,
- MX31_PIN_LD3__LD3,
- MX31_PIN_LD4__LD4,
- MX31_PIN_LD5__LD5,
- MX31_PIN_LD6__LD6,
- MX31_PIN_LD7__LD7,
- MX31_PIN_LD8__LD8,
- MX31_PIN_LD9__LD9,
- MX31_PIN_LD10__LD10,
- MX31_PIN_LD11__LD11,
- MX31_PIN_LD12__LD12,
- MX31_PIN_LD13__LD13,
- MX31_PIN_LD14__LD14,
- MX31_PIN_LD15__LD15,
- MX31_PIN_LD16__LD16,
- MX31_PIN_LD17__LD17,
- MX31_PIN_VSYNC3__VSYNC3,
- MX31_PIN_HSYNC__HSYNC,
- MX31_PIN_FPSHIFT__FPSHIFT,
- MX31_PIN_DRDY0__DRDY0,
- IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/
- /* I2C2 */
- MX31_PIN_CSPI2_MOSI__SCL,
- MX31_PIN_CSPI2_MISO__SDA,
- /* OTG */
- MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
- MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
- MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
- MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
- MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
- MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
- MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
- MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
- MX31_PIN_USBOTG_CLK__USBOTG_CLK,
- MX31_PIN_USBOTG_DIR__USBOTG_DIR,
- MX31_PIN_USBOTG_NXT__USBOTG_NXT,
- MX31_PIN_USBOTG_STP__USBOTG_STP,
- /* USB host 2 */
- IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
-};
-
-/* USB */
-
-#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
-#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
-#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)
-
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int usbotg_init(struct platform_device *pdev)
-{
- int err;
-
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
-
- /* Chip already enabled by hardware */
- /* OTG phy reset*/
- err = gpio_request(OTG_RESET, "USB-OTG-RESET");
- if (err) {
- pr_err("Failed to request the usb otg reset gpio\n");
- return err;
- }
-
- err = gpio_direction_output(OTG_RESET, 1/*HIGH*/);
- if (err) {
- pr_err("Failed to reset the usb otg phy\n");
- goto otg_free_reset;
- }
-
- gpio_set_value(OTG_RESET, 0/*LOW*/);
- mdelay(5);
- gpio_set_value(OTG_RESET, 1/*HIGH*/);
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
- MXC_EHCI_INTERFACE_DIFF_UNI);
-
-otg_free_reset:
- gpio_free(OTG_RESET);
- return err;
-}
-
-static int usbh2_init(struct platform_device *pdev)
-{
- int err;
-
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
-
- mxc_iomux_set_gpr(MUX_PGP_UH2, true);
-
-
- /* Enable the chip */
- err = gpio_request(USBH2_CS, "USB-H2-CS");
- if (err) {
- pr_err("Failed to request the usb host 2 CS gpio\n");
- return err;
- }
-
- err = gpio_direction_output(USBH2_CS, 0/*Enabled*/);
- if (err) {
- pr_err("Failed to drive the usb host 2 CS gpio\n");
- goto h2_free_cs;
- }
-
- /* H2 phy reset*/
- err = gpio_request(USBH2_RESET, "USB-H2-RESET");
- if (err) {
- pr_err("Failed to request the usb host 2 reset gpio\n");
- goto h2_free_cs;
- }
-
- err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/);
- if (err) {
- pr_err("Failed to reset the usb host 2 phy\n");
- goto h2_free_reset;
- }
-
- gpio_set_value(USBH2_RESET, 0/*LOW*/);
- mdelay(5);
- gpio_set_value(USBH2_RESET, 1/*HIGH*/);
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
- MXC_EHCI_INTERFACE_DIFF_UNI);
-
-h2_free_reset:
- gpio_free(USBH2_RESET);
-h2_free_cs:
- gpio_free(USBH2_CS);
- return err;
-}
-
-static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
- .init = usbotg_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = usbh2_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-/* RTC over I2C*/
-#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
-
-static struct i2c_board_info armadillo5x0_i2c_rtc = {
- I2C_BOARD_INFO("s35390a", 0x30),
-};
-
-/* GPIO BUTTONS */
-static struct gpio_keys_button armadillo5x0_buttons[] = {
- {
- .code = KEY_ENTER, /*28*/
- .gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0),
- .active_low = 1,
- .desc = "menu",
- .wakeup = 1,
- }, {
- .code = KEY_BACK, /*158*/
- .gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0),
- .active_low = 1,
- .desc = "back",
- .wakeup = 1,
- }
-};
-
-static const struct gpio_keys_platform_data
- armadillo5x0_button_data __initconst = {
- .buttons = armadillo5x0_buttons,
- .nbuttons = ARRAY_SIZE(armadillo5x0_buttons),
-};
-
-/*
- * NAND Flash
- */
-static const struct mxc_nand_platform_data
-armadillo5x0_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-/*
- * MTD NOR Flash
- */
-static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
- {
- .name = "nor.bootloader",
- .offset = 0x00000000,
- .size = 4*32*1024,
- }, {
- .name = "nor.kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = 16*128*1024,
- }, {
- .name = "nor.userland",
- .offset = MTDPART_OFS_APPEND,
- .size = 110*128*1024,
- }, {
- .name = "nor.config",
- .offset = MTDPART_OFS_APPEND,
- .size = 1*128*1024,
- },
-};
-
-static const struct physmap_flash_data
- armadillo5x0_nor_flash_pdata __initconst = {
- .width = 2,
- .parts = armadillo5x0_nor_flash_partitions,
- .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions),
-};
-
-static const struct resource armadillo5x0_nor_flash_resource __initconst = {
- .flags = IORESOURCE_MEM,
- .start = MX31_CS0_BASE_ADDR,
- .end = MX31_CS0_BASE_ADDR + SZ_64M - 1,
-};
-
-/*
- * FB support
- */
-static const struct fb_videomode fb_modedb[] = {
- { /* 640x480 @ 60 Hz */
- .name = "CRT-VGA",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = 39721,
- .left_margin = 35,
- .right_margin = 115,
- .upper_margin = 43,
- .lower_margin = 1,
- .hsync_len = 10,
- .vsync_len = 1,
- .sync = FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }, {/* 800x600 @ 56 Hz */
- .name = "CRT-SVGA",
- .refresh = 56,
- .xres = 800,
- .yres = 600,
- .pixclock = 30000,
- .left_margin = 30,
- .right_margin = 108,
- .upper_margin = 13,
- .lower_margin = 10,
- .hsync_len = 10,
- .vsync_len = 1,
- .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_VERT_HIGH_ACT,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
-};
-
-static struct mx3fb_platform_data mx3fb_pdata __initdata = {
- .name = "CRT-VGA",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-/*
- * SDHC 1
- * MMC support
- */
-static int armadillo5x0_sdhc1_get_ro(struct device *dev)
-{
- return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
-}
-
-static int armadillo5x0_sdhc1_init(struct device *dev,
- irq_handler_t detect_irq, void *data)
-{
- int ret;
- int gpio_det, gpio_wp;
-
- gpio_det = IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK);
- gpio_wp = IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B);
-
- ret = gpio_request(gpio_det, "sdhc-card-detect");
- if (ret)
- return ret;
-
- gpio_direction_input(gpio_det);
-
- ret = gpio_request(gpio_wp, "sdhc-write-protect");
- if (ret)
- goto err_gpio_free;
-
- gpio_direction_input(gpio_wp);
-
- /* When supported the trigger type have to be BOTH */
- ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)),
- detect_irq, IRQF_TRIGGER_FALLING,
- "sdhc-detect", data);
-
- if (ret)
- goto err_gpio_free_2;
-
- return 0;
-
-err_gpio_free_2:
- gpio_free(gpio_wp);
-
-err_gpio_free:
- gpio_free(gpio_det);
-
- return ret;
-
-}
-
-static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), data);
- gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK));
- gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
-}
-
-static const struct imxmmc_platform_data sdhc_pdata __initconst = {
- .get_ro = armadillo5x0_sdhc1_get_ro,
- .init = armadillo5x0_sdhc1_init,
- .exit = armadillo5x0_sdhc1_exit,
-};
-
-/*
- * SMSC 9118
- * Network support
- */
-static struct resource armadillo5x0_smc911x_resources[] = {
- {
- .start = MX31_CS3_BASE_ADDR,
- .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- /* irq number is run-time assigned */
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_info = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
-};
-
-static struct platform_device armadillo5x0_smc911x_device = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(armadillo5x0_smc911x_resources),
- .resource = armadillo5x0_smc911x_resources,
- .dev = {
- .platform_data = &smsc911x_info,
- },
-};
-
-/* UART device data */
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct platform_device *devices[] __initdata = {
- &armadillo5x0_smc911x_device,
-};
-
-static struct regulator_consumer_supply dummy_supplies[] = {
- REGULATOR_SUPPLY("vdd33a", "smsc911x"),
- REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
-/*
- * Perform board specific initializations
- */
-static void __init armadillo5x0_init(void)
-{
- imx31_soc_init();
-
- mxc_iomux_setup_multiple_pins(armadillo5x0_pins,
- ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
-
- regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
- imx31_add_imx_i2c1(NULL);
-
- /* Register UART */
- imx31_add_imx_uart0(&uart_pdata);
- imx31_add_imx_uart1(&uart_pdata);
-
- /* Register FB */
- imx31_add_ipu_core();
- imx31_add_mx3_sdc_fb(&mx3fb_pdata);
-
- /* Register NOR Flash */
- platform_device_register_resndata(NULL, "physmap-flash", -1,
- &armadillo5x0_nor_flash_resource, 1,
- &armadillo5x0_nor_flash_pdata,
- sizeof(armadillo5x0_nor_flash_pdata));
-
- /* Register NAND Flash */
- imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
-
- /* set NAND page size to 2k if not configured via boot mode pins */
- imx_writel(imx_readl(mx3_ccm_base + MXC_CCM_RCSR) | (1 << 30),
- mx3_ccm_base + MXC_CCM_RCSR);
-}
-
-static void __init armadillo5x0_late(void)
-{
- armadillo5x0_smc911x_resources[1].start =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
- armadillo5x0_smc911x_resources[1].end =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- imx_add_gpio_keys(&armadillo5x0_button_data);
-
- /* SMSC9118 IRQ pin */
- gpio_direction_input(MX31_PIN_GPIO1_0);
-
- /* Register SDHC */
- imx31_add_mxc_mmc(0, &sdhc_pdata);
-
- /* RTC */
- /* Get RTC IRQ and register the chip */
- if (!gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc")) {
- if (!gpio_direction_input(ARMADILLO5X0_RTC_GPIO))
- armadillo5x0_i2c_rtc.irq =
- gpio_to_irq(ARMADILLO5X0_RTC_GPIO);
- else
- gpio_free(ARMADILLO5X0_RTC_GPIO);
- }
-
- if (armadillo5x0_i2c_rtc.irq == 0)
- pr_warn("armadillo5x0_init: failed to get RTC IRQ\n");
- i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
-
- /* USB */
- usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbotg_pdata.otg)
- imx31_add_mxc_ehci_otg(&usbotg_pdata);
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbh2_pdata.otg)
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-}
-
-static void __init armadillo5x0_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-MACHINE_START(ARMADILLO5X0, "Armadillo-500")
- /* Maintainer: Alberto Panizzo */
- .atag_offset = 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .init_time = armadillo5x0_timer_init,
- .init_machine = armadillo5x0_init,
- .init_late = armadillo5x0_late,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
deleted file mode 100644
index 3929208..0000000
--- a/arch/arm/mach-imx/mach-bug.c
+++ /dev/null
@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach/time.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include "common.h"
-#include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const unsigned int bug_pins[] __initconst = {
- MX31_PIN_PC_RST__CTS5,
- MX31_PIN_PC_VS2__RTS5,
- MX31_PIN_PC_BVD2__TXD5,
- MX31_PIN_PC_BVD1__RXD5,
-};
-
-static void __init bug_board_init(void)
-{
- imx31_soc_init();
-
- mxc_iomux_setup_multiple_pins(bug_pins,
- ARRAY_SIZE(bug_pins), "uart-4");
- imx31_add_imx_uart4(&uart_pdata);
-}
-
-static void __init bug_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-MACHINE_START(BUG, "BugLabs BUGBase")
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .init_time = bug_timer_init,
- .init_machine = bug_board_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27.c b/arch/arm/mach-imx/mach-imx27.c
new file mode 100644
index 0000000..262422a
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx27.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/mm.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+#include "common.h"
+#include "hardware.h"
+#include "mx27.h"
+
+/* MX27 memory map definition */
+static struct map_desc imx27_io_desc[] __initdata = {
+ /*
+ * this fixed mapping covers:
+ * - AIPI1
+ * - AIPI2
+ * - AITC
+ * - ROM Patch
+ * - and some reserved space
+ */
+ imx_map_entry(MX27, AIPI, MT_DEVICE),
+ /*
+ * this fixed mapping covers:
+ * - CSI
+ * - ATA
+ */
+ imx_map_entry(MX27, SAHB1, MT_DEVICE),
+ /*
+ * this fixed mapping covers:
+ * - EMI
+ */
+ imx_map_entry(MX27, X_MEMC, MT_DEVICE),
+};
+
+/*
+ * Initialize the memory map. It is called during the
+ * system startup to create static physical to virtual
+ * memory map for the IO modules.
+ */
+static void __init mx27_map_io(void)
+{
+ iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
+}
+
+static void __init imx27_init_early(void)
+{
+ mxc_set_cpu_type(MXC_CPU_MX27);
+}
+
+static void __init mx27_init_irq(void)
+{
+ void __iomem *avic_base;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,avic");
+ avic_base = of_iomap(np, 0);
+ BUG_ON(!avic_base);
+ mxc_init_irq(avic_base);
+}
+
+static const char * const imx27_dt_board_compat[] __initconst = {
+ "fsl,imx27",
+ NULL
+};
+
+DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
+ .map_io = mx27_map_io,
+ .init_early = imx27_init_early,
+ .init_irq = mx27_init_irq,
+ .init_late = imx27_pm_init,
+ .dt_compat = imx27_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
deleted file mode 100644
index c0350bc..0000000
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ /dev/null
@@ -1,593 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * mach-imx27_visstrim_m10.c
- *
- * Copyright 2010 Javier Martin <javier.martin@vista-silicon.com>
- *
- * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others.
- */
-
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/pca953x.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/leds.h>
-#include <linux/platform_data/asoc-mx27vis.h>
-#include <media/soc_camera.h>
-#include <sound/tlv320aic32x4.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/system_info.h>
-#include <asm/memblock.h>
-
-#include "common.h"
-#include "devices-imx27.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-
-#define TVP5150_RSTN (GPIO_PORTC + 18)
-#define TVP5150_PWDN (GPIO_PORTC + 19)
-#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
-#define SDHC1_IRQ_GPIO IMX_GPIO_NR(2, 25)
-
-#define VERSION_MASK 0x7
-#define MOTHERBOARD_SHIFT 4
-#define EXPBOARD_SHIFT 0
-
-#define MOTHERBOARD_BIT2 (GPIO_PORTD + 31)
-#define MOTHERBOARD_BIT1 (GPIO_PORTD + 30)
-#define MOTHERBOARD_BIT0 (GPIO_PORTD + 29)
-
-#define EXPBOARD_BIT2 (GPIO_PORTD + 25)
-#define EXPBOARD_BIT1 (GPIO_PORTD + 27)
-#define EXPBOARD_BIT0 (GPIO_PORTD + 28)
-
-#define AMP_GAIN_0 (GPIO_PORTF + 9)
-#define AMP_GAIN_1 (GPIO_PORTF + 8)
-#define AMP_MUTE_SDL (GPIO_PORTE + 5)
-#define AMP_MUTE_SDR (GPIO_PORTF + 7)
-
-static const int visstrim_m10_pins[] __initconst = {
- /* UART1 (console) */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
- /* SSI1 */
- PC20_PF_SSI1_FS,
- PC21_PF_SSI1_RXD,
- PC22_PF_SSI1_TXD,
- PC23_PF_SSI1_CLK,
- /* SDHC1 */
- PE18_PF_SD1_D0,
- PE19_PF_SD1_D1,
- PE20_PF_SD1_D2,
- PE21_PF_SD1_D3,
- PE22_PF_SD1_CMD,
- PE23_PF_SD1_CLK,
- /* Both I2Cs */
- PD17_PF_I2C_DATA,
- PD18_PF_I2C_CLK,
- PC5_PF_I2C2_SDA,
- PC6_PF_I2C2_SCL,
- /* USB OTG */
- OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
- PC9_PF_USBOTG_DATA0,
- PC11_PF_USBOTG_DATA1,
- PC10_PF_USBOTG_DATA2,
- PC13_PF_USBOTG_DATA3,
- PC12_PF_USBOTG_DATA4,
- PC7_PF_USBOTG_DATA5,
- PC8_PF_USBOTG_DATA6,
- PE25_PF_USBOTG_DATA7,
- PE24_PF_USBOTG_CLK,
- PE2_PF_USBOTG_DIR,
- PE0_PF_USBOTG_NXT,
- PE1_PF_USBOTG_STP,
- PB23_PF_USB_PWR,
- PB24_PF_USB_OC,
- /* CSI */
- TVP5150_RSTN | GPIO_GPIO | GPIO_OUT,
- TVP5150_PWDN | GPIO_GPIO | GPIO_OUT,
- PB10_PF_CSI_D0,
- PB11_PF_CSI_D1,
- PB12_PF_CSI_D2,
- PB13_PF_CSI_D3,
- PB14_PF_CSI_D4,
- PB15_PF_CSI_MCLK,
- PB16_PF_CSI_PIXCLK,
- PB17_PF_CSI_D5,
- PB18_PF_CSI_D6,
- PB19_PF_CSI_D7,
- PB20_PF_CSI_VSYNC,
- PB21_PF_CSI_HSYNC,
- /* mother board version */
- MOTHERBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
- MOTHERBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
- MOTHERBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
- /* expansion board version */
- EXPBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
- EXPBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
- EXPBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
- /* Audio AMP control */
- AMP_GAIN_0 | GPIO_GPIO | GPIO_OUT,
- AMP_GAIN_1 | GPIO_GPIO | GPIO_OUT,
- AMP_MUTE_SDL | GPIO_GPIO | GPIO_OUT,
- AMP_MUTE_SDR | GPIO_GPIO | GPIO_OUT,
-};
-
-static struct gpio visstrim_m10_version_gpios[] = {
- { EXPBOARD_BIT0, GPIOF_IN, "exp-version-0" },
- { EXPBOARD_BIT1, GPIOF_IN, "exp-version-1" },
- { EXPBOARD_BIT2, GPIOF_IN, "exp-version-2" },
- { MOTHERBOARD_BIT0, GPIOF_IN, "mother-version-0" },
- { MOTHERBOARD_BIT1, GPIOF_IN, "mother-version-1" },
- { MOTHERBOARD_BIT2, GPIOF_IN, "mother-version-2" },
-};
-
-static const struct gpio visstrim_m10_gpios[] __initconst = {
- {
- .gpio = TVP5150_RSTN,
- .flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH,
- .label = "tvp5150_rstn",
- },
- {
- .gpio = TVP5150_PWDN,
- .flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW,
- .label = "tvp5150_pwdn",
- },
- {
- .gpio = OTG_PHY_CS_GPIO,
- .flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW,
- .label = "usbotg_cs",
- },
- {
- .gpio = AMP_GAIN_0,
- .flags = GPIOF_DIR_OUT,
- .label = "amp-gain-0",
- },
- {
- .gpio = AMP_GAIN_1,
- .flags = GPIOF_DIR_OUT,
- .label = "amp-gain-1",
- },
- {
- .gpio = AMP_MUTE_SDL,
- .flags = GPIOF_DIR_OUT,
- .label = "amp-mute-sdl",
- },
- {
- .gpio = AMP_MUTE_SDR,
- .flags = GPIOF_DIR_OUT,
- .label = "amp-mute-sdr",
- },
-};
-
-/* Camera */
-static int visstrim_camera_power(struct device *dev, int on)
-{
- gpio_set_value(TVP5150_PWDN, on);
-
- return 0;
-};
-
-static int visstrim_camera_reset(struct device *dev)
-{
- gpio_set_value(TVP5150_RSTN, 0);
- ndelay(500);
- gpio_set_value(TVP5150_RSTN, 1);
-
- return 0;
-};
-
-static struct i2c_board_info visstrim_i2c_camera = {
- I2C_BOARD_INFO("tvp5150", 0x5d),
-};
-
-static struct soc_camera_link iclink_tvp5150 = {
- .bus_id = 0,
- .board_info = &visstrim_i2c_camera,
- .i2c_adapter_id = 0,
- .power = visstrim_camera_power,
- .reset = visstrim_camera_reset,
-};
-
-static struct mx2_camera_platform_data visstrim_camera = {
- .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE |
- MX2_CAMERA_PCLK_SAMPLE_RISING,
- .clk = 100000,
-};
-
-static phys_addr_t mx2_camera_base __initdata;
-#define MX2_CAMERA_BUF_SIZE SZ_8M
-
-static void __init visstrim_analog_camera_init(void)
-{
- struct platform_device *pdev;
-
- gpio_set_value(TVP5150_PWDN, 1);
- ndelay(1);
- gpio_set_value(TVP5150_RSTN, 0);
- ndelay(500);
- gpio_set_value(TVP5150_RSTN, 1);
- ndelay(200000);
-
- pdev = imx27_add_mx2_camera(&visstrim_camera);
- if (IS_ERR(pdev))
- return;
-
- dma_declare_coherent_memory(&pdev->dev, mx2_camera_base,
- mx2_camera_base, MX2_CAMERA_BUF_SIZE);
-}
-
-static void __init visstrim_reserve(void)
-{
- /* reserve 4 MiB for mx2-camera */
- mx2_camera_base = arm_memblock_steal(3 * MX2_CAMERA_BUF_SIZE,
- MX2_CAMERA_BUF_SIZE);
-}
-
-/* GPIOs used as events for applications */
-static struct gpio_keys_button visstrim_gpio_keys[] = {
- {
- .type = EV_KEY,
- .code = KEY_RESTART,
- .gpio = (GPIO_PORTC + 15),
- .desc = "Default config",
- .active_low = 0,
- .wakeup = 1,
- },
- {
- .type = EV_KEY,
- .code = KEY_RECORD,
- .gpio = (GPIO_PORTF + 14),
- .desc = "Record",
- .active_low = 0,
- .wakeup = 1,
- },
- {
- .type = EV_KEY,
- .code = KEY_STOP,
- .gpio = (GPIO_PORTF + 13),
- .desc = "Stop",
- .active_low = 0,
- .wakeup = 1,
- }
-};
-
-static const struct gpio_keys_platform_data
- visstrim_gpio_keys_platform_data __initconst = {
- .buttons = visstrim_gpio_keys,
- .nbuttons = ARRAY_SIZE(visstrim_gpio_keys),
-};
-
-/* led */
-static const struct gpio_led visstrim_m10_leds[] __initconst = {
- {
- .name = "visstrim:ld0",
- .default_trigger = "nand-disk",
- .gpio = (GPIO_PORTC + 29),
- },
- {
- .name = "visstrim:ld1",
- .default_trigger = "nand-disk",
- .gpio = (GPIO_PORTC + 24),
- },
- {
- .name = "visstrim:ld2",
- .default_trigger = "nand-disk",
- .gpio = (GPIO_PORTC + 28),
- },
- {
- .name = "visstrim:ld3",
- .default_trigger = "nand-disk",
- .gpio = (GPIO_PORTC + 25),
- },
-};
-
-static const struct gpio_led_platform_data visstrim_m10_led_data __initconst = {
- .leds = visstrim_m10_leds,
- .num_leds = ARRAY_SIZE(visstrim_m10_leds),
-};
-
-/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
-static int visstrim_m10_sdhc1_init(struct device *dev,
- irq_handler_t detect_irq, void *data)
-{
- int ret;
-
- ret = request_irq(gpio_to_irq(SDHC1_IRQ_GPIO), detect_irq,
- IRQF_TRIGGER_FALLING, "mmc-detect", data);
- return ret;
-}
-
-static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(SDHC1_IRQ_GPIO), data);
-}
-
-static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {
- .init = visstrim_m10_sdhc1_init,
- .exit = visstrim_m10_sdhc1_exit,
-};
-
-/* Visstrim_SM10 NOR flash */
-static struct physmap_flash_data visstrim_m10_flash_data = {
- .width = 2,
-};
-
-static struct resource visstrim_m10_flash_resource = {
- .start = 0xc0000000,
- .end = 0xc0000000 + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device visstrim_m10_nor_mtd_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &visstrim_m10_flash_data,
- },
- .num_resources = 1,
- .resource = &visstrim_m10_flash_resource,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &visstrim_m10_nor_mtd_device,
-};
-
-/* Visstrim_M10 uses UART0 as console */
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-/* I2C */
-static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = {
- .bitrate = 100000,
-};
-
-static struct pca953x_platform_data visstrim_m10_pca9555_pdata = {
- .gpio_base = 240, /* After MX27 internal GPIOs */
- .invert = 0,
-};
-
-static struct aic32x4_pdata visstrim_m10_aic32x4_pdata = {
- .power_cfg = AIC32X4_PWR_MICBIAS_2075_LDOIN |
- AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE |
- AIC32X4_PWR_AIC32X4_LDO_ENABLE |
- AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36 |
- AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED,
- .micpga_routing = AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K |
- AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K,
- .swapdacs = false,
-};
-
-static struct i2c_board_info visstrim_m10_i2c_devices[] = {
- {
- I2C_BOARD_INFO("pca9555", 0x20),
- .platform_data = &visstrim_m10_pca9555_pdata,
- },
- {
- I2C_BOARD_INFO("tlv320aic32x4", 0x18),
- .platform_data = &visstrim_m10_aic32x4_pdata,
- },
- {
- I2C_BOARD_INFO("m41t00", 0x68),
- }
-};
-
-/* USB OTG */
-static int otg_phy_init(struct platform_device *pdev)
-{
- return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static const struct mxc_usbh_platform_data
-visstrim_m10_usbotg_pdata __initconst = {
- .init = otg_phy_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-/* SSI */
-static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
- .flags = IMX_SSI_DMA | IMX_SSI_SYN,
-};
-
-/* coda */
-
-static void __init visstrim_coda_init(void)
-{
- struct platform_device *pdev;
-
- pdev = imx27_add_coda();
- dma_declare_coherent_memory(&pdev->dev,
- mx2_camera_base + MX2_CAMERA_BUF_SIZE,
- mx2_camera_base + MX2_CAMERA_BUF_SIZE,
- MX2_CAMERA_BUF_SIZE);
-}
-
-/* DMA deinterlace */
-static struct platform_device visstrim_deinterlace = {
- .name = "m2m-deinterlace",
- .id = 0,
-};
-
-static void __init visstrim_deinterlace_init(void)
-{
- int ret = -ENOMEM;
- struct platform_device *pdev = &visstrim_deinterlace;
-
- ret = platform_device_register(pdev);
-
- dma_declare_coherent_memory(&pdev->dev,
- mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
- mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE,
- MX2_CAMERA_BUF_SIZE);
-}
-
-/* Emma-PrP for format conversion */
-static void __init visstrim_emmaprp_init(void)
-{
- struct platform_device *pdev;
- int ret;
-
- pdev = imx27_add_mx2_emmaprp();
- if (IS_ERR(pdev))
- return;
-
- /*
- * Use the same memory area as the analog camera since both
- * devices are, by nature, exclusive.
- */
- ret = dma_declare_coherent_memory(&pdev->dev,
- mx2_camera_base, mx2_camera_base,
- MX2_CAMERA_BUF_SIZE);
- if (ret)
- pr_err("Failed to declare memory for emmaprp\n");
-}
-
-/* Audio */
-static const struct snd_mx27vis_platform_data snd_mx27vis_pdata __initconst = {
- .amp_gain0_gpio = AMP_GAIN_0,
- .amp_gain1_gpio = AMP_GAIN_1,
- .amp_mutel_gpio = AMP_MUTE_SDL,
- .amp_muter_gpio = AMP_MUTE_SDR,
-};
-
-static void __init visstrim_m10_revision(void)
-{
- int exp_version = 0;
- int mo_version = 0;
- int ret;
-
- ret = gpio_request_array(visstrim_m10_version_gpios,
- ARRAY_SIZE(visstrim_m10_version_gpios));
- if (ret) {
- pr_err("Failed to request version gpios");
- return;
- }
-
- /* Get expansion board version (negative logic) */
- exp_version |= !gpio_get_value(EXPBOARD_BIT2) << 2;
- exp_version |= !gpio_get_value(EXPBOARD_BIT1) << 1;
- exp_version |= !gpio_get_value(EXPBOARD_BIT0);
-
- /* Get mother board version (negative logic) */
- mo_version |= !gpio_get_value(MOTHERBOARD_BIT2) << 2;
- mo_version |= !gpio_get_value(MOTHERBOARD_BIT1) << 1;
- mo_version |= !gpio_get_value(MOTHERBOARD_BIT0);
-
- system_rev = 0x27000;
- system_rev |= (mo_version << MOTHERBOARD_SHIFT);
- system_rev |= (exp_version << EXPBOARD_SHIFT);
-}
-
-static void __init visstrim_m10_board_init(void)
-{
- int ret;
-
- imx27_soc_init();
- visstrim_m10_revision();
-
- ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
- ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
- if (ret)
- pr_err("Failed to setup pins (%d)\n", ret);
-
- imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
- imx27_add_imx_uart0(&uart_pdata);
-
- imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
- imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
- i2c_register_board_info(0, visstrim_m10_i2c_devices,
- ARRAY_SIZE(visstrim_m10_i2c_devices));
-
- imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
- imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
- imx27_add_fec(NULL);
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
-
-static void __init visstrim_m10_late_init(void)
-{
- int mo_version, ret;
-
- ret = gpio_request_array(visstrim_m10_gpios,
- ARRAY_SIZE(visstrim_m10_gpios));
- if (ret)
- pr_err("Failed to request gpios (%d)\n", ret);
-
- imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
-
- imx_add_platform_device("mx27vis", 0, NULL, 0, &snd_mx27vis_pdata,
- sizeof(snd_mx27vis_pdata));
- platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
- &iclink_tvp5150, sizeof(iclink_tvp5150));
-
- gpio_led_register_device(0, &visstrim_m10_led_data);
-
- /* Use mother board version to decide what video devices we shall use */
- mo_version = (system_rev >> MOTHERBOARD_SHIFT) & VERSION_MASK;
- if (mo_version & 0x1) {
- visstrim_emmaprp_init();
-
- /*
- * Despite not being used, tvp5150 must be
- * powered on to avoid I2C problems. To minimize
- * power consupmtion keep reset enabled.
- */
- gpio_set_value(TVP5150_PWDN, 1);
- ndelay(1);
- gpio_set_value(TVP5150_RSTN, 0);
- } else {
- visstrim_deinterlace_init();
- visstrim_analog_camera_init();
- }
-
- visstrim_coda_init();
-}
-
-static void __init visstrim_m10_timer_init(void)
-{
- mx27_clocks_init((unsigned long)25000000);
-}
-
-MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
- .atag_offset = 0x100,
- .reserve = visstrim_reserve,
- .map_io = mx27_map_io,
- .init_early = imx27_init_early,
- .init_irq = mx27_init_irq,
- .init_time = visstrim_m10_timer_init,
- .init_machine = visstrim_m10_board_init,
- .init_late = visstrim_m10_late_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/mach-imx31.c
similarity index 100%
rename from arch/arm/mach-imx/imx31-dt.c
rename to arch/arm/mach-imx/mach-imx31.c
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/mach-imx35.c
similarity index 100%
rename from arch/arm/mach-imx/imx35-dt.c
rename to arch/arm/mach-imx/mach-imx35.c
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index edd26e0..85c084a 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -5,29 +5,16 @@
*/
#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/cpu.h>
-#include <linux/delay.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
#include <linux/irqchip.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
#include <linux/of_platform.h>
-#include <linux/pm_opp.h>
#include <linux/pci.h>
#include <linux/phy.h>
-#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <asm/system_misc.h>
#include "common.h"
#include "cpuidle.h"
@@ -258,21 +245,15 @@
static void __init imx6q_init_machine(void)
{
- struct device *parent;
-
if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
else
imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
imx_get_soc_revision());
- parent = imx_soc_device_init();
- if (parent == NULL)
- pr_warn("failed to initialize soc device\n");
-
imx6q_enet_phy_init();
- of_platform_default_populate(NULL, NULL, parent);
+ of_platform_default_populate(NULL, NULL, NULL);
imx_anatop_init();
cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index e00818a..f6e8736 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -4,7 +4,6 @@
*/
#include <linux/irqchip.h>
-#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
@@ -46,13 +45,7 @@
static void __init imx6sl_init_machine(void)
{
- struct device *parent;
-
- parent = imx_soc_device_init();
- if (parent == NULL)
- pr_warn("failed to initialize soc device\n");
-
- of_platform_default_populate(NULL, NULL, parent);
+ of_platform_default_populate(NULL, NULL, NULL);
if (cpu_is_imx6sl())
imx6sl_fec_init();
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index d5310bf..781e2a9 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -63,13 +63,7 @@
static void __init imx6sx_init_machine(void)
{
- struct device *parent;
-
- parent = imx_soc_device_init();
- if (parent == NULL)
- pr_warn("failed to initialize soc device\n");
-
- of_platform_default_populate(NULL, NULL, parent);
+ of_platform_default_populate(NULL, NULL, NULL);
imx6sx_enet_init();
imx_anatop_init();
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
index 311f5e4..e018e71 100644
--- a/arch/arm/mach-imx/mach-imx6ul.c
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -25,7 +25,6 @@
IMX6UL_GPR1_ENET_CLK_OUTPUT);
else
pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
-
}
static int ksz8081_phy_fixup(struct phy_device *dev)
@@ -56,13 +55,7 @@
static void __init imx6ul_init_machine(void)
{
- struct device *parent;
-
- parent = imx_soc_device_init();
- if (parent == NULL)
- pr_warn("failed to initialize soc device\n");
-
- of_platform_default_populate(NULL, NULL, parent);
+ of_platform_default_populate(NULL, NULL, NULL);
imx6ul_enet_init();
imx_anatop_init();
imx6ul_pm_init();
diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c
index ebb2759..879c359 100644
--- a/arch/arm/mach-imx/mach-imx7d.c
+++ b/arch/arm/mach-imx/mach-imx7d.c
@@ -78,12 +78,6 @@
static void __init imx7d_init_machine(void)
{
- struct device *parent;
-
- parent = imx_soc_device_init();
- if (parent == NULL)
- pr_warn("failed to initialize soc device\n");
-
imx_anatop_init();
imx7d_enet_init();
}
diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c
index 11ac71a..445256e 100644
--- a/arch/arm/mach-imx/mach-imx7ulp.c
+++ b/arch/arm/mach-imx/mach-imx7ulp.c
@@ -57,7 +57,7 @@
mxc_set_cpu_type(MXC_CPU_IMX7ULP);
imx7ulp_set_revision();
- of_platform_default_populate(NULL, NULL, imx_soc_device_init());
+ of_platform_default_populate(NULL, NULL, NULL);
}
static const char *const imx7ulp_dt_compat[] __initconst = {
@@ -67,6 +67,9 @@
static void __init imx7ulp_init_late(void)
{
+ if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
+ platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
+
imx7ulp_cpuidle_init();
}
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
deleted file mode 100644
index 63f7f78..0000000
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ /dev/null
@@ -1,291 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * KZM-ARM11-01 support
- * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * based on code for MX31ADS,
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/smsc911x.h>
-#include <linux/types.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/memory.h>
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-
-#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
- IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
- IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
- MX31_IO_ADDRESS(x))
-
-/*
- * KZM-ARM11-01 Board Control Registers on FPGA
- */
-#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
-#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
-#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
-#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
-#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
-#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
-#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
-#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
-
-/*
- * External UART for touch panel on FPGA
- */
-#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
-
-#if IS_ENABLED(CONFIG_SERIAL_8250)
-/*
- * KZM-ARM11-01 has an external UART on FPGA
- */
-static struct plat_serial8250_port serial_platform_data[] = {
- {
- .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
- .mapbase = KZM_ARM11_16550,
- /* irq number is run-time assigned */
- .irqflags = IRQ_TYPE_EDGE_RISING,
- .uartclk = 14745600,
- .regshift = 0,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_BUGGY_UART,
- },
- {},
-};
-
-static struct resource serial8250_resources[] = {
- {
- .start = KZM_ARM11_16550,
- .end = KZM_ARM11_16550 + 0x10,
- .flags = IORESOURCE_MEM,
- },
- {
- /* irq number is run-time assigned */
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = serial_platform_data,
- },
- .num_resources = ARRAY_SIZE(serial8250_resources),
- .resource = serial8250_resources,
-};
-
-static int __init kzm_init_ext_uart(void)
-{
- u8 tmp;
-
- /*
- * GPIO 1-1: external UART interrupt line
- */
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
- /*
- * Unmask UART interrupt
- */
- tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
- tmp |= 0x2;
- __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
-
- serial_platform_data[0].irq =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
- serial8250_resources[1].start =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
- serial8250_resources[1].end =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
- return platform_device_register(&serial_device);
-}
-#else
-static inline int kzm_init_ext_uart(void)
-{
- return 0;
-}
-#endif
-
-/*
- * SMSC LAN9118
- */
-#if IS_ENABLED(CONFIG_SMSC911X)
-static struct smsc911x_platform_config kzm_smsc9118_config = {
- .phy_interface = PHY_INTERFACE_MODE_MII,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
- .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
-};
-
-static struct resource kzm_smsc9118_resources[] = {
- {
- .start = MX31_CS5_BASE_ADDR,
- .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- /* irq number is run-time assigned */
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static struct platform_device kzm_smsc9118_device = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(kzm_smsc9118_resources),
- .resource = kzm_smsc9118_resources,
- .dev = {
- .platform_data = &kzm_smsc9118_config,
- },
-};
-
-static struct regulator_consumer_supply dummy_supplies[] = {
- REGULATOR_SUPPLY("vdd33a", "smsc911x"),
- REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
-static int __init kzm_init_smsc9118(void)
-{
- /*
- * GPIO 1-2: SMSC9118 interrupt line
- */
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
-
- regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
- kzm_smsc9118_resources[1].start =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
- kzm_smsc9118_resources[1].end =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
-
- return platform_device_register(&kzm_smsc9118_device);
-}
-#else
-static inline int kzm_init_smsc9118(void)
-{
- return 0;
-}
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_IMX)
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static void __init kzm_init_imx_uart(void)
-{
- imx31_add_imx_uart0(&uart_pdata);
- imx31_add_imx_uart1(&uart_pdata);
-}
-#else
-static inline void kzm_init_imx_uart(void)
-{
-}
-#endif
-
-static int kzm_pins[] __initdata = {
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
- MX31_PIN_DCD_DCE1__DCD_DCE1,
- MX31_PIN_RI_DCE1__RI_DCE1,
- MX31_PIN_DSR_DCE1__DSR_DCE1,
- MX31_PIN_DTR_DCE1__DTR_DCE1,
- MX31_PIN_CTS2__CTS2,
- MX31_PIN_RTS2__RTS2,
- MX31_PIN_TXD2__TXD2,
- MX31_PIN_RXD2__RXD2,
- MX31_PIN_DCD_DTE1__DCD_DTE2,
- MX31_PIN_RI_DTE1__RI_DTE2,
- MX31_PIN_DSR_DTE1__DSR_DTE2,
- MX31_PIN_DTR_DTE1__DTR_DTE2,
-};
-
-/*
- * Board specific initialization.
- */
-static void __init kzm_board_init(void)
-{
- imx31_soc_init();
-
- mxc_iomux_setup_multiple_pins(kzm_pins,
- ARRAY_SIZE(kzm_pins), "kzm");
- kzm_init_imx_uart();
-
- pr_info("Clock input source is 26MHz\n");
-}
-
-static void __init kzm_late_init(void)
-{
- kzm_init_ext_uart();
- kzm_init_smsc9118();
-}
-
-/*
- * This structure defines static mappings for the kzm-arm11-01 board.
- */
-static struct map_desc kzm_io_desc[] __initdata = {
- {
- .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
- .length = MX31_CS4_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = (unsigned long)MX31_CS5_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
- .length = MX31_CS5_SIZE,
- .type = MT_DEVICE
- },
-};
-
-/*
- * Set up static virtual mappings.
- */
-static void __init kzm_map_io(void)
-{
- mx31_map_io();
- iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
-}
-
-static void __init kzm_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
- .atag_offset = 0x100,
- .map_io = kzm_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .init_time = kzm_timer_init,
- .init_machine = kzm_board_init,
- .init_late = kzm_late_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
deleted file mode 100644
index ec011e8..0000000
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ /dev/null
@@ -1,338 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/gpio/driver.h>
-#include <linux/gpio/machine.h>
-#include <linux/gpio.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "common.h"
-#include "devices-imx21.h"
-#include "hardware.h"
-#include "iomux-mx21.h"
-
-#define MX21ADS_CS8900A_REG (MX21_CS1_BASE_ADDR + 0x000000)
-#define MX21ADS_ST16C255_IOBASE_REG (MX21_CS1_BASE_ADDR + 0x200000)
-#define MX21ADS_VERSION_REG (MX21_CS1_BASE_ADDR + 0x400000)
-#define MX21ADS_IO_REG (MX21_CS1_BASE_ADDR + 0x800000)
-
-#define MX21ADS_MMC_CD IMX_GPIO_NR(4, 25)
-#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11)
-#define MX21ADS_MMGPIO_BASE (6 * 32)
-
-/* MX21ADS_IO_REG bit definitions */
-#define MX21ADS_IO_SD_WP (MX21ADS_MMGPIO_BASE + 0)
-#define MX21ADS_IO_TP6 (MX21ADS_IO_SD_WP)
-#define MX21ADS_IO_SW_SEL (MX21ADS_MMGPIO_BASE + 1)
-#define MX21ADS_IO_TP7 (MX21ADS_IO_SW_SEL)
-#define MX21ADS_IO_RESET_E_UART (MX21ADS_MMGPIO_BASE + 2)
-#define MX21ADS_IO_RESET_BASE (MX21ADS_MMGPIO_BASE + 3)
-#define MX21ADS_IO_CSI_CTL2 (MX21ADS_MMGPIO_BASE + 4)
-#define MX21ADS_IO_CSI_CTL1 (MX21ADS_MMGPIO_BASE + 5)
-#define MX21ADS_IO_CSI_CTL0 (MX21ADS_MMGPIO_BASE + 6)
-#define MX21ADS_IO_UART1_EN (MX21ADS_MMGPIO_BASE + 7)
-#define MX21ADS_IO_UART4_EN (MX21ADS_MMGPIO_BASE + 8)
-#define MX21ADS_IO_LCDON (MX21ADS_MMGPIO_BASE + 9)
-#define MX21ADS_IO_IRDA_EN (MX21ADS_MMGPIO_BASE + 10)
-#define MX21ADS_IO_IRDA_FIR_SEL (MX21ADS_MMGPIO_BASE + 11)
-#define MX21ADS_IO_IRDA_MD0_B (MX21ADS_MMGPIO_BASE + 12)
-#define MX21ADS_IO_IRDA_MD1 (MX21ADS_MMGPIO_BASE + 13)
-#define MX21ADS_IO_LED4_ON (MX21ADS_MMGPIO_BASE + 14)
-#define MX21ADS_IO_LED3_ON (MX21ADS_MMGPIO_BASE + 15)
-
-static const int mx21ads_pins[] __initconst = {
-
- /* CS8900A */
- (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
-
- /* UART1 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
-
- /* UART3 (IrDA) - only TXD and RXD */
- PE8_PF_UART3_TXD,
- PE9_PF_UART3_RXD,
-
- /* UART4 */
- PB26_AF_UART4_RTS,
- PB28_AF_UART4_TXD,
- PB29_AF_UART4_CTS,
- PB31_AF_UART4_RXD,
-
- /* LCDC */
- PA5_PF_LSCLK,
- PA6_PF_LD0,
- PA7_PF_LD1,
- PA8_PF_LD2,
- PA9_PF_LD3,
- PA10_PF_LD4,
- PA11_PF_LD5,
- PA12_PF_LD6,
- PA13_PF_LD7,
- PA14_PF_LD8,
- PA15_PF_LD9,
- PA16_PF_LD10,
- PA17_PF_LD11,
- PA18_PF_LD12,
- PA19_PF_LD13,
- PA20_PF_LD14,
- PA21_PF_LD15,
- PA22_PF_LD16,
- PA24_PF_REV, /* Sharp panel dedicated signal */
- PA25_PF_CLS, /* Sharp panel dedicated signal */
- PA26_PF_PS, /* Sharp panel dedicated signal */
- PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
- PA28_PF_HSYNC,
- PA29_PF_VSYNC,
- PA30_PF_CONTRAST,
- PA31_PF_OE_ACD,
-
- /* MMC/SDHC */
- PE18_PF_SD1_D0,
- PE19_PF_SD1_D1,
- PE20_PF_SD1_D2,
- PE21_PF_SD1_D3,
- PE22_PF_SD1_CMD,
- PE23_PF_SD1_CLK,
-
- /* NFC */
- PF0_PF_NRFB,
- PF1_PF_NFCE,
- PF2_PF_NFWP,
- PF3_PF_NFCLE,
- PF4_PF_NFALE,
- PF5_PF_NFRE,
- PF6_PF_NFWE,
- PF7_PF_NFIO0,
- PF8_PF_NFIO1,
- PF9_PF_NFIO2,
- PF10_PF_NFIO3,
- PF11_PF_NFIO4,
- PF12_PF_NFIO5,
- PF13_PF_NFIO6,
- PF14_PF_NFIO7,
-};
-
-/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
-static struct physmap_flash_data mx21ads_flash_data = {
- .width = 4,
-};
-
-static struct resource mx21ads_flash_resource =
- DEFINE_RES_MEM(MX21_CS0_BASE_ADDR, SZ_32M);
-
-static struct platform_device mx21ads_nor_mtd_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &mx21ads_flash_data,
- },
- .num_resources = 1,
- .resource = &mx21ads_flash_resource,
-};
-
-static struct resource mx21ads_cs8900_resources[] __initdata = {
- DEFINE_RES_MEM(MX21ADS_CS8900A_REG, SZ_1K),
- /* irq number is run-time assigned */
- DEFINE_RES_IRQ(-1),
-};
-
-static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
- .name = "cs89x0",
- .id = 0,
- .res = mx21ads_cs8900_resources,
- .num_res = ARRAY_SIZE(mx21ads_cs8900_resources),
-};
-
-static const struct imxuart_platform_data uart_pdata_rts __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxuart_platform_data uart_pdata_norts __initconst = {
-};
-
-static struct resource mx21ads_mmgpio_resource =
- DEFINE_RES_MEM_NAMED(MX21ADS_IO_REG, SZ_2, "dat");
-
-static struct bgpio_pdata mx21ads_mmgpio_pdata = {
- .label = "mx21ads-mmgpio",
- .base = MX21ADS_MMGPIO_BASE,
- .ngpio = 16,
-};
-
-static struct platform_device mx21ads_mmgpio = {
- .name = "basic-mmio-gpio",
- .id = PLATFORM_DEVID_AUTO,
- .resource = &mx21ads_mmgpio_resource,
- .num_resources = 1,
- .dev = {
- .platform_data = &mx21ads_mmgpio_pdata,
- },
-};
-
-static struct regulator_consumer_supply mx21ads_lcd_regulator_consumer =
- REGULATOR_SUPPLY("lcd", "imx-fb.0");
-
-static struct regulator_init_data mx21ads_lcd_regulator_init_data = {
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
- .consumer_supplies = &mx21ads_lcd_regulator_consumer,
- .num_consumer_supplies = 1,
-};
-
-static struct fixed_voltage_config mx21ads_lcd_regulator_pdata = {
- .supply_name = "LCD",
- .microvolts = 3300000,
- .init_data = &mx21ads_lcd_regulator_init_data,
-};
-
-static struct platform_device mx21ads_lcd_regulator = {
- .name = "reg-fixed-voltage",
- .id = PLATFORM_DEVID_AUTO,
- .dev = {
- .platform_data = &mx21ads_lcd_regulator_pdata,
- },
-};
-
-static struct gpiod_lookup_table mx21ads_lcd_regulator_gpiod_table = {
- .dev_id = "reg-fixed-voltage.0", /* Let's hope ID 0 is what we get */
- .table = {
- GPIO_LOOKUP("mx21ads-mmgpio", 9, NULL, GPIO_ACTIVE_HIGH),
- { },
- },
-};
-
-/*
- * Connected is a portrait Sharp-QVGA display
- * of type: LQ035Q7DB02
- */
-static struct imx_fb_videomode mx21ads_modes[] = {
- {
- .mode = {
- .name = "Sharp-LQ035Q7",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 188679, /* in ps (5.3MHz) */
- .hsync_len = 2,
- .left_margin = 6,
- .right_margin = 16,
- .vsync_len = 1,
- .upper_margin = 8,
- .lower_margin = 10,
- },
- .pcr = 0xfb108bc7,
- .bpp = 16,
- },
-};
-
-static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
- .mode = mx21ads_modes,
- .num_modes = ARRAY_SIZE(mx21ads_modes),
-
- .pwmr = 0x00a903ff,
- .lscr1 = 0x00120300,
- .dmacr = 0x00020008,
-};
-
-static int mx21ads_sdhc_get_ro(struct device *dev)
-{
- return gpio_get_value(MX21ADS_IO_SD_WP);
-}
-
-static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request(MX21ADS_IO_SD_WP, "mmc-ro");
- if (ret)
- return ret;
-
- return request_irq(gpio_to_irq(MX21ADS_MMC_CD), detect_irq,
- IRQF_TRIGGER_FALLING, "mmc-detect", data);
-}
-
-static void mx21ads_sdhc_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(MX21ADS_MMC_CD), data);
- gpio_free(MX21ADS_IO_SD_WP);
-}
-
-static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
- .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
- .get_ro = mx21ads_sdhc_get_ro,
- .init = mx21ads_sdhc_init,
- .exit = mx21ads_sdhc_exit,
-};
-
-static const struct mxc_nand_platform_data
-mx21ads_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &mx21ads_mmgpio,
- &mx21ads_lcd_regulator,
- &mx21ads_nor_mtd_device,
-};
-
-static void __init mx21ads_board_init(void)
-{
- imx21_soc_init();
-
- mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
- "mx21ads");
-
- imx21_add_imx_uart0(&uart_pdata_rts);
- imx21_add_imx_uart2(&uart_pdata_norts);
- imx21_add_imx_uart3(&uart_pdata_rts);
- imx21_add_mxc_nand(&mx21ads_nand_board_info);
-
- imx21_add_imx_fb(&mx21ads_fb_data);
-}
-
-static void __init mx21ads_late_init(void)
-{
- imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
-
- gpiod_add_lookup_table(&mx21ads_lcd_regulator_gpiod_table);
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-
- mx21ads_cs8900_resources[1].start =
- gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
- mx21ads_cs8900_resources[1].end =
- gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
- platform_device_register_full(&mx21ads_cs8900_devinfo);
-}
-
-static void __init mx21ads_timer_init(void)
-{
- mx21_clocks_init(32768, 26000000);
-}
-
-MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
- /* maintainer: Freescale Semiconductor, Inc. */
- .atag_offset = 0x100,
- .map_io = mx21_map_io,
- .init_early = imx21_init_early,
- .init_irq = mx21_init_irq,
- .init_time = mx21ads_timer_init,
- .init_machine = mx21ads_board_init,
- .init_late = mx21ads_late_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
deleted file mode 100644
index 7b8325f..0000000
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ /dev/null
@@ -1,445 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- */
-
-/*
- * This machine is known as:
- * - i.MX27 3-Stack Development System
- * - i.MX27 Platform Development Kit (i.MX27 PDK)
- */
-
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/delay.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/spi/spi.h>
-#include <linux/regulator/machine.h>
-#include <linux/spi/l4f00242t03.h>
-
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "3ds_debugboard.h"
-#include "common.h"
-#include "devices-imx27.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-#include "ulpi.h"
-
-#define SD1_EN_GPIO IMX_GPIO_NR(2, 25)
-#define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23)
-#define SPI2_SS0 IMX_GPIO_NR(4, 21)
-#define PMIC_INT IMX_GPIO_NR(3, 14)
-#define SPI1_SS0 IMX_GPIO_NR(4, 28)
-#define SD1_CD IMX_GPIO_NR(2, 26)
-#define LCD_RESET IMX_GPIO_NR(1, 3)
-#define LCD_ENABLE IMX_GPIO_NR(1, 31)
-
-static const int mx27pdk_pins[] __initconst = {
- /* UART1 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
- /* SDHC1 */
- PE18_PF_SD1_D0,
- PE19_PF_SD1_D1,
- PE20_PF_SD1_D2,
- PE21_PF_SD1_D3,
- PE22_PF_SD1_CMD,
- PE23_PF_SD1_CLK,
- SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
- /* OTG */
- OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT,
- PC7_PF_USBOTG_DATA5,
- PC8_PF_USBOTG_DATA6,
- PC9_PF_USBOTG_DATA0,
- PC10_PF_USBOTG_DATA2,
- PC11_PF_USBOTG_DATA1,
- PC12_PF_USBOTG_DATA4,
- PC13_PF_USBOTG_DATA3,
- PE0_PF_USBOTG_NXT,
- PE1_PF_USBOTG_STP,
- PE2_PF_USBOTG_DIR,
- PE24_PF_USBOTG_CLK,
- PE25_PF_USBOTG_DATA7,
- /* CSPI1 */
- PD31_PF_CSPI1_MOSI,
- PD30_PF_CSPI1_MISO,
- PD29_PF_CSPI1_SCLK,
- PD25_PF_CSPI1_RDY,
- SPI1_SS0 | GPIO_GPIO | GPIO_OUT,
- /* CSPI2 */
- PD22_PF_CSPI2_SCLK,
- PD23_PF_CSPI2_MISO,
- PD24_PF_CSPI2_MOSI,
- SPI2_SS0 | GPIO_GPIO | GPIO_OUT,
- /* I2C1 */
- PD17_PF_I2C_DATA,
- PD18_PF_I2C_CLK,
- /* PMIC INT */
- PMIC_INT | GPIO_GPIO | GPIO_IN,
- /* LCD */
- PA5_PF_LSCLK,
- PA6_PF_LD0,
- PA7_PF_LD1,
- PA8_PF_LD2,
- PA9_PF_LD3,
- PA10_PF_LD4,
- PA11_PF_LD5,
- PA12_PF_LD6,
- PA13_PF_LD7,
- PA14_PF_LD8,
- PA15_PF_LD9,
- PA16_PF_LD10,
- PA17_PF_LD11,
- PA18_PF_LD12,
- PA19_PF_LD13,
- PA20_PF_LD14,
- PA21_PF_LD15,
- PA22_PF_LD16,
- PA23_PF_LD17,
- PA28_PF_HSYNC,
- PA29_PF_VSYNC,
- PA30_PF_CONTRAST,
- LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
- LCD_RESET | GPIO_GPIO | GPIO_OUT,
- /* SSI4 */
- PC16_PF_SSI4_FS,
- PC17_PF_SSI4_RXD,
- PC18_PF_SSI4_TXD,
- PC19_PF_SSI4_CLK,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-/*
- * Matrix keyboard
- */
-
-static const uint32_t mx27_3ds_keymap[] = {
- KEY(0, 0, KEY_UP),
- KEY(0, 1, KEY_DOWN),
- KEY(1, 0, KEY_RIGHT),
- KEY(1, 1, KEY_LEFT),
- KEY(1, 2, KEY_ENTER),
- KEY(2, 0, KEY_F6),
- KEY(2, 1, KEY_F8),
- KEY(2, 2, KEY_F9),
- KEY(2, 3, KEY_F10),
-};
-
-static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = {
- .keymap = mx27_3ds_keymap,
- .keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
-};
-
-static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- return request_irq(gpio_to_irq(SD1_CD), detect_irq,
- IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
-}
-
-static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(SD1_CD), data);
-}
-
-static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
- .init = mx27_3ds_sdhc1_init,
- .exit = mx27_3ds_sdhc1_exit,
-};
-
-static void mx27_3ds_sdhc1_enable_level_translator(void)
-{
- /* Turn on TXB0108 OE pin */
- gpio_request(SD1_EN_GPIO, "sd1_enable");
- gpio_direction_output(SD1_EN_GPIO, 1);
-}
-
-
-static int otg_phy_init(void)
-{
- gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset");
- gpio_direction_output(OTG_PHY_RESET_GPIO, 0);
- mdelay(1);
- gpio_set_value(OTG_PHY_RESET_GPIO, 1);
- return 0;
-}
-
-static int mx27_3ds_otg_init(struct platform_device *pdev)
-{
- return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
- .init = mx27_3ds_otg_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-static bool otg_mode_host __initdata;
-
-static int __init mx27_3ds_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = true;
- else if (!strcmp(options, "device"))
- otg_mode_host = false;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 1;
-}
-__setup("otg_mode=", mx27_3ds_otg_mode);
-
-/* Regulators */
-static struct regulator_init_data gpo_init = {
- .constraints = {
- .boot_on = 1,
- .always_on = 1,
- }
-};
-
-static struct regulator_consumer_supply vmmc1_consumers[] = {
- REGULATOR_SUPPLY("vcore", "spi0.0"),
-};
-
-static struct regulator_init_data vmmc1_init = {
- .constraints = {
- .min_uV = 2800000,
- .max_uV = 2800000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
- .consumer_supplies = vmmc1_consumers,
-};
-
-static struct regulator_consumer_supply vgen_consumers[] = {
- REGULATOR_SUPPLY("vdd", "spi0.0"),
-};
-
-static struct regulator_init_data vgen_init = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- },
- .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
- .consumer_supplies = vgen_consumers,
-};
-
-static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
- {
- .id = MC13783_REG_VMMC1,
- .init_data = &vmmc1_init,
- }, {
- .id = MC13783_REG_VGEN,
- .init_data = &vgen_init,
- }, {
- .id = MC13783_REG_GPO1, /* Turn on 1.8V */
- .init_data = &gpo_init,
- }, {
- .id = MC13783_REG_GPO3, /* Turn on 3.3V */
- .init_data = &gpo_init,
- },
-};
-
-/* MC13783 */
-static struct mc13xxx_codec_platform_data mx27_3ds_codec = {
- .dac_ssi_port = MC13783_SSI1_PORT,
- .adc_ssi_port = MC13783_SSI1_PORT,
-};
-
-static struct mc13xxx_platform_data mc13783_pdata = {
- .regulators = {
- .regulators = mx27_3ds_regulators,
- .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
-
- },
- .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC |
- MC13XXX_USE_CODEC,
- .codec = &mx27_3ds_codec,
-};
-
-static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
- .flags = IMX_SSI_DMA | IMX_SSI_NET,
-};
-
-/* SPI */
-static int spi1_chipselect[] = {SPI1_SS0};
-
-static const struct spi_imx_master spi1_pdata __initconst = {
- .chipselect = spi1_chipselect,
- .num_chipselect = ARRAY_SIZE(spi1_chipselect),
-};
-
-static int spi2_chipselect[] = {SPI2_SS0};
-
-static const struct spi_imx_master spi2_pdata __initconst = {
- .chipselect = spi2_chipselect,
- .num_chipselect = ARRAY_SIZE(spi2_chipselect),
-};
-
-static struct imx_fb_videomode mx27_3ds_modes[] = {
- { /* 480x640 @ 60 Hz */
- .mode = {
- .name = "Epson-VGA",
- .refresh = 60,
- .xres = 480,
- .yres = 640,
- .pixclock = 41701,
- .left_margin = 20,
- .right_margin = 41,
- .upper_margin = 10,
- .lower_margin = 5,
- .hsync_len = 20,
- .vsync_len = 10,
- .sync = FB_SYNC_OE_ACT_HIGH |
- FB_SYNC_CLK_INVERT,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
- .bpp = 16,
- .pcr = 0xFAC08B82,
- },
-};
-
-static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = {
- .mode = mx27_3ds_modes,
- .num_modes = ARRAY_SIZE(mx27_3ds_modes),
- .pwmr = 0x00A903FF,
- .lscr1 = 0x00120300,
- .dmacr = 0x00020010,
-};
-
-/* LCD */
-static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = {
- .reset_gpio = LCD_RESET,
- .data_enable_gpio = LCD_ENABLE,
-};
-
-static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
- {
- .modalias = "mc13783",
- .max_speed_hz = 1000000,
- .bus_num = 1,
- .chip_select = 0, /* SS0 */
- .platform_data = &mc13783_pdata,
- /* irq number is run-time assigned */
- .mode = SPI_CS_HIGH,
- }, {
- .modalias = "l4f00242t03",
- .max_speed_hz = 5000000,
- .bus_num = 0,
- .chip_select = 0, /* SS0 */
- .platform_data = &mx27_3ds_lcd_pdata,
- },
-};
-
-static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
- .bitrate = 100000,
-};
-
-static void __init mx27pdk_init(void)
-{
- imx27_soc_init();
-
- mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
- "mx27pdk");
- imx27_add_imx_uart0(&uart_pdata);
- imx27_add_fec(NULL);
- imx27_add_imx_keypad(&mx27_3ds_keymap_data);
- imx27_add_imx2_wdt();
-
- imx27_add_spi_imx1(&spi2_pdata);
- imx27_add_spi_imx0(&spi1_pdata);
-
- imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
- imx27_add_imx_fb(&mx27_3ds_fb_data);
-
- imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);
-}
-
-static void __init mx27pdk_late_init(void)
-{
- mx27_3ds_sdhc1_enable_level_translator();
- imx27_add_mxc_mmc(0, &sdhc1_pdata);
-
- otg_phy_init();
-
- if (otg_mode_host) {
- otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
-
- if (otg_pdata.otg)
- imx27_add_mxc_ehci_otg(&otg_pdata);
- }
-
- if (!otg_mode_host)
- imx27_add_fsl_usb2_udc(&otg_device_pdata);
-
- mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
- spi_register_board_info(mx27_3ds_spi_devs,
- ARRAY_SIZE(mx27_3ds_spi_devs));
-
- if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
- pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
-
-
- imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
-}
-
-static void __init mx27pdk_timer_init(void)
-{
- mx27_clocks_init(26000000);
-}
-
-MACHINE_START(MX27_3DS, "Freescale MX27PDK")
- /* maintainer: Freescale Semiconductor, Inc. */
- .atag_offset = 0x100,
- .map_io = mx27_map_io,
- .init_early = imx27_init_early,
- .init_irq = mx27_init_irq,
- .init_time = mx27pdk_timer_init,
- .init_machine = mx27pdk_init,
- .init_late = mx27pdk_late_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
deleted file mode 100644
index ba202f9..0000000
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ /dev/null
@@ -1,407 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-#include <linux/gpio/driver.h>
-/* Needed for gpio_to_irq() */
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices-imx27.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-
-/*
- * Base address of PBC controller, CS4
- */
-#define PBC_BASE_ADDRESS 0xf4300000
-#define PBC_REG_ADDR(offset) (void __force __iomem *) \
- (PBC_BASE_ADDRESS + (offset))
-
-/* When the PBC address connection is fixed in h/w, defined as 1 */
-#define PBC_ADDR_SH 0
-
-/* Offsets for the PBC Controller register */
-/*
- * PBC Board version register offset
- */
-#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 set address.
- */
-#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 clear address.
- */
-#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
-
-/* PBC Board Control Register 1 bit definitions */
-#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
-
-/* to determine the correct external crystal reference */
-#define CKIH_27MHZ_BIT_SET (1 << 3)
-
-static const int mx27ads_pins[] __initconst = {
- /* UART0 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* UART1 */
- PE3_PF_UART2_CTS,
- PE4_PF_UART2_RTS,
- PE6_PF_UART2_TXD,
- PE7_PF_UART2_RXD,
- /* UART2 */
- PE8_PF_UART3_TXD,
- PE9_PF_UART3_RXD,
- PE10_PF_UART3_CTS,
- PE11_PF_UART3_RTS,
- /* UART3 */
- PB26_AF_UART4_RTS,
- PB28_AF_UART4_TXD,
- PB29_AF_UART4_CTS,
- PB31_AF_UART4_RXD,
- /* UART4 */
- PB18_AF_UART5_TXD,
- PB19_AF_UART5_RXD,
- PB20_AF_UART5_CTS,
- PB21_AF_UART5_RTS,
- /* UART5 */
- PB10_AF_UART6_TXD,
- PB12_AF_UART6_CTS,
- PB11_AF_UART6_RXD,
- PB13_AF_UART6_RTS,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
- /* I2C2 */
- PC5_PF_I2C2_SDA,
- PC6_PF_I2C2_SCL,
- /* FB */
- PA5_PF_LSCLK,
- PA6_PF_LD0,
- PA7_PF_LD1,
- PA8_PF_LD2,
- PA9_PF_LD3,
- PA10_PF_LD4,
- PA11_PF_LD5,
- PA12_PF_LD6,
- PA13_PF_LD7,
- PA14_PF_LD8,
- PA15_PF_LD9,
- PA16_PF_LD10,
- PA17_PF_LD11,
- PA18_PF_LD12,
- PA19_PF_LD13,
- PA20_PF_LD14,
- PA21_PF_LD15,
- PA22_PF_LD16,
- PA23_PF_LD17,
- PA24_PF_REV,
- PA25_PF_CLS,
- PA26_PF_PS,
- PA27_PF_SPL_SPR,
- PA28_PF_HSYNC,
- PA29_PF_VSYNC,
- PA30_PF_CONTRAST,
- PA31_PF_OE_ACD,
- /* OWIRE */
- PE16_AF_OWIRE,
- /* SDHC1*/
- PE18_PF_SD1_D0,
- PE19_PF_SD1_D1,
- PE20_PF_SD1_D2,
- PE21_PF_SD1_D3,
- PE22_PF_SD1_CMD,
- PE23_PF_SD1_CLK,
- /* SDHC2*/
- PB4_PF_SD2_D0,
- PB5_PF_SD2_D1,
- PB6_PF_SD2_D2,
- PB7_PF_SD2_D3,
- PB8_PF_SD2_CMD,
- PB9_PF_SD2_CLK,
-};
-
-static const struct mxc_nand_platform_data
-mx27ads_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-/* ADS's NOR flash */
-static struct physmap_flash_data mx27ads_flash_data = {
- .width = 2,
-};
-
-static struct resource mx27ads_flash_resource = {
- .start = 0xc0000000,
- .end = 0xc0000000 + 0x02000000 - 1,
- .flags = IORESOURCE_MEM,
-
-};
-
-static struct platform_device mx27ads_nor_mtd_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &mx27ads_flash_data,
- },
- .num_resources = 1,
- .resource = &mx27ads_flash_resource,
-};
-
-static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
- .bitrate = 100000,
-};
-
-static struct i2c_board_info mx27ads_i2c_devices[] = {
-};
-
-static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
- if (value)
- imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
- else
- imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
-}
-
-static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
-{
- return 0;
-}
-
-#define MX27ADS_LCD_GPIO (6 * 32)
-
-static struct regulator_consumer_supply mx27ads_lcd_regulator_consumer =
- REGULATOR_SUPPLY("lcd", "imx-fb.0");
-
-static struct regulator_init_data mx27ads_lcd_regulator_init_data = {
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-},
- .consumer_supplies = &mx27ads_lcd_regulator_consumer,
- .num_consumer_supplies = 1,
-};
-
-static struct fixed_voltage_config mx27ads_lcd_regulator_pdata = {
- .supply_name = "LCD",
- .microvolts = 3300000,
- .init_data = &mx27ads_lcd_regulator_init_data,
-};
-
-static struct gpiod_lookup_table mx27ads_lcd_regulator_gpiod_table = {
- .dev_id = "reg-fixed-voltage.0", /* Let's hope ID 0 is what we get */
- .table = {
- GPIO_LOOKUP("LCD", 0, NULL, GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init mx27ads_regulator_init(void)
-{
- struct gpio_chip *vchip;
-
- vchip = kzalloc(sizeof(*vchip), GFP_KERNEL);
- vchip->owner = THIS_MODULE;
- vchip->label = "LCD";
- vchip->base = MX27ADS_LCD_GPIO;
- vchip->ngpio = 1;
- vchip->direction_output = vgpio_dir_out;
- vchip->set = vgpio_set;
- gpiochip_add_data(vchip, NULL);
-
- gpiod_add_lookup_table(&mx27ads_lcd_regulator_gpiod_table);
-
- platform_device_register_data(NULL, "reg-fixed-voltage",
- PLATFORM_DEVID_AUTO,
- &mx27ads_lcd_regulator_pdata,
- sizeof(mx27ads_lcd_regulator_pdata));
-}
-
-static struct imx_fb_videomode mx27ads_modes[] = {
- {
- .mode = {
- .name = "Sharp-LQ035Q7",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 188679, /* in ps (5.3MHz) */
- .hsync_len = 1,
- .left_margin = 9,
- .right_margin = 16,
- .vsync_len = 1,
- .upper_margin = 7,
- .lower_margin = 9,
- },
- .bpp = 16,
- .pcr = 0xFB008BC0,
- },
-};
-
-static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
- .mode = mx27ads_modes,
- .num_modes = ARRAY_SIZE(mx27ads_modes),
-
- /*
- * - HSYNC active high
- * - VSYNC active high
- * - clk notenabled while idle
- * - clock inverted
- * - data not inverted
- * - data enable low active
- * - enable sharp mode
- */
- .pwmr = 0x00A903FF,
- .lscr1 = 0x00120300,
- .dmacr = 0x00020010,
-};
-
-static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq,
- IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
-}
-
-static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq,
- IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
-}
-
-static void mx27ads_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data);
-}
-
-static void mx27ads_sdhc2_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data);
-}
-
-static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
- .init = mx27ads_sdhc1_init,
- .exit = mx27ads_sdhc1_exit,
-};
-
-static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
- .init = mx27ads_sdhc2_init,
- .exit = mx27ads_sdhc2_exit,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &mx27ads_nor_mtd_device,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static void __init mx27ads_board_init(void)
-{
- imx27_soc_init();
-
- mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
- "mx27ads");
-
- imx27_add_imx_uart0(&uart_pdata);
- imx27_add_imx_uart1(&uart_pdata);
- imx27_add_imx_uart2(&uart_pdata);
- imx27_add_imx_uart3(&uart_pdata);
- imx27_add_imx_uart4(&uart_pdata);
- imx27_add_imx_uart5(&uart_pdata);
- imx27_add_mxc_nand(&mx27ads_nand_board_info);
-
- /* only the i2c master 1 is used on this CPU card */
- i2c_register_board_info(1, mx27ads_i2c_devices,
- ARRAY_SIZE(mx27ads_i2c_devices));
- imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
- imx27_add_imx_fb(&mx27ads_fb_data);
-
- imx27_add_fec(NULL);
- imx27_add_mxc_w1();
-}
-
-static void __init mx27ads_late_init(void)
-{
- mx27ads_regulator_init();
-
- imx27_add_mxc_mmc(0, &sdhc1_pdata);
- imx27_add_mxc_mmc(1, &sdhc2_pdata);
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
-
-static void __init mx27ads_timer_init(void)
-{
- unsigned long fref = 26000000;
-
- if ((imx_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
- fref = 27000000;
-
- mx27_clocks_init(fref);
-}
-
-static struct map_desc mx27ads_io_desc[] __initdata = {
- {
- .virtual = PBC_BASE_ADDRESS,
- .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
- .length = SZ_1M,
- .type = MT_DEVICE,
- },
-};
-
-static void __init mx27ads_map_io(void)
-{
- mx27_map_io();
- iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
-}
-
-MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
- /* maintainer: Freescale Semiconductor, Inc. */
- .atag_offset = 0x100,
- .map_io = mx27ads_map_io,
- .init_early = imx27_init_early,
- .init_irq = mx27_init_irq,
- .init_time = mx27ads_timer_init,
- .init_machine = mx27ads_board_init,
- .init_late = mx27ads_late_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
deleted file mode 100644
index 716d2ad..0000000
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ /dev/null
@@ -1,610 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/l4f00242t03.h>
-#include <linux/regulator/machine.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-
-#include "3ds_debugboard.h"
-#include "common.h"
-#include "devices-imx31.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
-
-static int mx31_3ds_pins[] = {
- /* UART1 */
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
- IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
- /*SPI0*/
- IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
- /* SPI 1 */
- MX31_PIN_CSPI2_SCLK__SCLK,
- MX31_PIN_CSPI2_MOSI__MOSI,
- MX31_PIN_CSPI2_MISO__MISO,
- MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI2_SS0__SS0,
- MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
- /* MC13783 IRQ */
- IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
- /* USB OTG reset */
- IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
- /* USB OTG */
- MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
- MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
- MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
- MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
- MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
- MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
- MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
- MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
- MX31_PIN_USBOTG_CLK__USBOTG_CLK,
- MX31_PIN_USBOTG_DIR__USBOTG_DIR,
- MX31_PIN_USBOTG_NXT__USBOTG_NXT,
- MX31_PIN_USBOTG_STP__USBOTG_STP,
- /*Keyboard*/
- MX31_PIN_KEY_ROW0_KEY_ROW0,
- MX31_PIN_KEY_ROW1_KEY_ROW1,
- MX31_PIN_KEY_ROW2_KEY_ROW2,
- MX31_PIN_KEY_COL0_KEY_COL0,
- MX31_PIN_KEY_COL1_KEY_COL1,
- MX31_PIN_KEY_COL2_KEY_COL2,
- MX31_PIN_KEY_COL3_KEY_COL3,
- /* USB Host 2 */
- IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
- /* USB Host2 reset */
- IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
- /* I2C1 */
- MX31_PIN_I2C_CLK__I2C1_SCL,
- MX31_PIN_I2C_DAT__I2C1_SDA,
- /* SDHC1 */
- MX31_PIN_SD1_DATA3__SD1_DATA3,
- MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA1__SD1_DATA1,
- MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_CLK__SD1_CLK,
- MX31_PIN_SD1_CMD__SD1_CMD,
- MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
- MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
- /* Framebuffer */
- MX31_PIN_LD0__LD0,
- MX31_PIN_LD1__LD1,
- MX31_PIN_LD2__LD2,
- MX31_PIN_LD3__LD3,
- MX31_PIN_LD4__LD4,
- MX31_PIN_LD5__LD5,
- MX31_PIN_LD6__LD6,
- MX31_PIN_LD7__LD7,
- MX31_PIN_LD8__LD8,
- MX31_PIN_LD9__LD9,
- MX31_PIN_LD10__LD10,
- MX31_PIN_LD11__LD11,
- MX31_PIN_LD12__LD12,
- MX31_PIN_LD13__LD13,
- MX31_PIN_LD14__LD14,
- MX31_PIN_LD15__LD15,
- MX31_PIN_LD16__LD16,
- MX31_PIN_LD17__LD17,
- MX31_PIN_VSYNC3__VSYNC3,
- MX31_PIN_HSYNC__HSYNC,
- MX31_PIN_FPSHIFT__FPSHIFT,
- MX31_PIN_CONTRAST__CONTRAST,
- /* SSI */
- MX31_PIN_STXD4__STXD4,
- MX31_PIN_SRXD4__SRXD4,
- MX31_PIN_SCK4__SCK4,
- MX31_PIN_SFS4__SFS4,
-};
-
-/*
- * FB support
- */
-static const struct fb_videomode fb_modedb[] = {
- { /* 480x640 @ 60 Hz */
- .name = "Epson-VGA",
- .refresh = 60,
- .xres = 480,
- .yres = 640,
- .pixclock = 41701,
- .left_margin = 20,
- .right_margin = 41,
- .upper_margin = 10,
- .lower_margin = 5,
- .hsync_len = 20,
- .vsync_len = 10,
- .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
-};
-
-static struct mx3fb_platform_data mx3fb_pdata __initdata = {
- .name = "Epson-VGA",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-/* LCD */
-static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
- .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
- .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
-};
-
-/*
- * Support for SD card slot in personality board
- */
-#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
-#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
-
-static struct gpio mx31_3ds_sdhc1_gpios[] = {
- { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
- { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
-};
-
-static int mx31_3ds_sdhc1_init(struct device *dev,
- irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
- ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
- if (ret) {
- pr_warn("Unable to request the SD/MMC GPIOs.\n");
- return ret;
- }
-
- ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
- detect_irq,
- IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
- "sdhc1-detect", data);
- if (ret) {
- pr_warn("Unable to request the SD/MMC card-detect IRQ.\n");
- goto gpio_free;
- }
-
- return 0;
-
-gpio_free:
- gpio_free_array(mx31_3ds_sdhc1_gpios,
- ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
- return ret;
-}
-
-static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data);
- gpio_free_array(mx31_3ds_sdhc1_gpios,
- ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
-}
-
-static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
-{
- /*
- * While the voltage stuff is done by the driver, activate the
- * Buffer Enable Pin only if there is a card in slot to fix the card
- * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
- * Done here because at this stage we have for sure a debounced value
- * of the presence of the card, showed by the value of vdd.
- * 7 == ilog2(MMC_VDD_165_195)
- */
- if (vdd > 7)
- gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
- else
- gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
-}
-
-static struct imxmmc_platform_data sdhc1_pdata = {
- .init = mx31_3ds_sdhc1_init,
- .exit = mx31_3ds_sdhc1_exit,
- .setpower = mx31_3ds_sdhc1_setpower,
-};
-
-/*
- * Matrix keyboard
- */
-
-static const uint32_t mx31_3ds_keymap[] = {
- KEY(0, 0, KEY_UP),
- KEY(0, 1, KEY_DOWN),
- KEY(1, 0, KEY_RIGHT),
- KEY(1, 1, KEY_LEFT),
- KEY(1, 2, KEY_ENTER),
- KEY(2, 0, KEY_F6),
- KEY(2, 1, KEY_F8),
- KEY(2, 2, KEY_F9),
- KEY(2, 3, KEY_F10),
-};
-
-static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
- .keymap = mx31_3ds_keymap,
- .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
-};
-
-/* Regulators */
-static struct regulator_init_data pwgtx_init = {
- .constraints = {
- .boot_on = 1,
- .always_on = 1,
- },
-};
-
-static struct regulator_init_data gpo_init = {
- .constraints = {
- .boot_on = 1,
- .always_on = 1,
- }
-};
-
-static struct regulator_consumer_supply vmmc2_consumers[] = {
- REGULATOR_SUPPLY("vmmc", "imx31-mmc.0"),
-};
-
-static struct regulator_init_data vmmc2_init = {
- .constraints = {
- .min_uV = 3000000,
- .max_uV = 3000000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
- .consumer_supplies = vmmc2_consumers,
-};
-
-static struct regulator_consumer_supply vmmc1_consumers[] = {
- REGULATOR_SUPPLY("vcore", "spi0.0"),
-};
-
-static struct regulator_init_data vmmc1_init = {
- .constraints = {
- .min_uV = 2800000,
- .max_uV = 2800000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
- .consumer_supplies = vmmc1_consumers,
-};
-
-static struct regulator_consumer_supply vgen_consumers[] = {
- REGULATOR_SUPPLY("vdd", "spi0.0"),
-};
-
-static struct regulator_init_data vgen_init = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
- .consumer_supplies = vgen_consumers,
-};
-
-static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
- {
- .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
- .init_data = &pwgtx_init,
- }, {
- .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
- .init_data = &pwgtx_init,
- }, {
-
- .id = MC13783_REG_GPO1, /* Turn on 1.8V */
- .init_data = &gpo_init,
- }, {
- .id = MC13783_REG_GPO3, /* Turn on 3.3V */
- .init_data = &gpo_init,
- }, {
- .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
- .init_data = &vmmc2_init,
- }, {
- .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
- .init_data = &vmmc1_init,
- }, {
- .id = MC13783_REG_VGEN, /* Power LCD */
- .init_data = &vgen_init,
- },
-};
-
-/* MC13783 */
-static struct mc13xxx_codec_platform_data mx31_3ds_codec = {
- .dac_ssi_port = MC13783_SSI1_PORT,
- .adc_ssi_port = MC13783_SSI1_PORT,
-};
-
-static struct mc13xxx_platform_data mc13783_pdata = {
- .regulators = {
- .regulators = mx31_3ds_regulators,
- .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
- },
- .codec = &mx31_3ds_codec,
- .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC,
-
-};
-
-static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = {
- .flags = IMX_SSI_DMA | IMX_SSI_NET,
-};
-
-/* SPI */
-static const struct spi_imx_master spi0_pdata __initconst = {
- .num_chipselect = 3,
-};
-
-static const struct spi_imx_master spi1_pdata __initconst = {
- .num_chipselect = 3,
-};
-
-static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
- {
- .modalias = "mc13783",
- .max_speed_hz = 1000000,
- .bus_num = 1,
- .chip_select = 2, /* SS2 */
- .platform_data = &mc13783_pdata,
- /* irq number is run-time assigned */
- .mode = SPI_CS_HIGH,
- }, {
- .modalias = "l4f00242t03",
- .max_speed_hz = 5000000,
- .bus_num = 0,
- .chip_select = 2, /* SS2 */
- .platform_data = &mx31_3ds_l4f00242t03_pdata,
- },
-};
-
-/*
- * NAND Flash
- */
-static const struct mxc_nand_platform_data
-mx31_3ds_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT
- .flash_bbt = 1,
-#endif
-};
-
-/*
- * USB OTG
- */
-
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
-#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
-
-static int mx31_3ds_usbotg_init(void)
-{
- int err;
-
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
-
- err = gpio_request(USBOTG_RST_B, "otgusb-reset");
- if (err) {
- pr_err("Failed to request the USB OTG reset gpio\n");
- return err;
- }
-
- err = gpio_direction_output(USBOTG_RST_B, 0);
- if (err) {
- pr_err("Failed to drive the USB OTG reset gpio\n");
- goto usbotg_free_reset;
- }
-
- mdelay(1);
- gpio_set_value(USBOTG_RST_B, 1);
- return 0;
-
-usbotg_free_reset:
- gpio_free(USBOTG_RST_B);
- return err;
-}
-
-static int mx31_3ds_otg_init(struct platform_device *pdev)
-{
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static int mx31_3ds_host2_init(struct platform_device *pdev)
-{
- int err;
-
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
-
- err = gpio_request(USBH2_RST_B, "usbh2-reset");
- if (err) {
- pr_err("Failed to request the USB Host 2 reset gpio\n");
- return err;
- }
-
- err = gpio_direction_output(USBH2_RST_B, 0);
- if (err) {
- pr_err("Failed to drive the USB Host 2 reset gpio\n");
- goto usbotg_free_reset;
- }
-
- mdelay(1);
- gpio_set_value(USBH2_RST_B, 1);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-
-usbotg_free_reset:
- gpio_free(USBH2_RST_B);
- return err;
-}
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
- .init = mx31_3ds_otg_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = mx31_3ds_host2_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-static bool otg_mode_host __initdata;
-
-static int __init mx31_3ds_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = true;
- else if (!strcmp(options, "device"))
- otg_mode_host = false;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 1;
-}
-__setup("otg_mode=", mx31_3ds_otg_mode);
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
- .bitrate = 100000,
-};
-
-static void __init mx31_3ds_init(void)
-{
- imx31_soc_init();
-
- /* Configure SPI1 IOMUX */
- mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
-
- mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
- "mx31_3ds");
-
- imx31_add_imx_uart0(&uart_pdata);
- imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
-
- imx31_add_spi_imx1(&spi1_pdata);
-
- imx31_add_imx_keypad(&mx31_3ds_keymap_data);
-
- imx31_add_imx2_wdt();
- imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
-
- imx31_add_spi_imx0(&spi0_pdata);
- imx31_add_ipu_core();
- imx31_add_mx3_sdc_fb(&mx3fb_pdata);
-
- imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata);
-
- imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
-}
-
-static void __init mx31_3ds_late(void)
-{
- mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
- spi_register_board_info(mx31_3ds_spi_devs,
- ARRAY_SIZE(mx31_3ds_spi_devs));
-
- mx31_3ds_usbotg_init();
- if (otg_mode_host) {
- otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (otg_pdata.otg)
- imx31_add_mxc_ehci_otg(&otg_pdata);
- }
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbh2_pdata.otg)
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-
- if (!otg_mode_host)
- imx31_add_fsl_usb2_udc(&usbotg_pdata);
-
- if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)))
- printk(KERN_WARNING "Init of the debug board failed, all "
- "devices on the debug board are unusable.\n");
-
- imx31_add_mxc_mmc(0, &sdhc1_pdata);
-}
-
-static void __init mx31_3ds_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
- /* Maintainer: Freescale Semiconductor, Inc. */
- .atag_offset = 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .init_time = mx31_3ds_timer_init,
- .init_machine = mx31_3ds_init,
- .init_late = mx31_3ds_late,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
deleted file mode 100644
index 4978338..0000000
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ /dev/null
@@ -1,579 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/serial_8250.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
-#include <linux/mfd/wm8350/audio.h>
-#include <linux/mfd/wm8350/core.h>
-#include <linux/mfd/wm8350/pmic.h>
-#endif
-
-#include "common.h"
-#include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-
-/* Base address of PBC controller */
-#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
-
-/* PBC Board interrupt status register */
-#define PBC_INTSTATUS 0x000016
-
-/* PBC Board interrupt current status register */
-#define PBC_INTCURR_STATUS 0x000018
-
-/* PBC Interrupt mask register set address */
-#define PBC_INTMASK_SET 0x00001A
-
-/* PBC Interrupt mask register clear address */
-#define PBC_INTMASK_CLEAR 0x00001C
-
-/* External UART A */
-#define PBC_SC16C652_UARTA 0x010000
-
-/* External UART B */
-#define PBC_SC16C652_UARTB 0x010010
-
-#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
-
-#define EXPIO_INT_XUART_INTA 10
-#define EXPIO_INT_XUART_INTB 11
-
-#define MXC_MAX_EXP_IO_LINES 16
-
-/* CS8900 */
-#define EXPIO_INT_ENET_INT 8
-#define CS4_CS8900_MMIO_START 0x20000
-
-static struct irq_domain *domain;
-
-/*
- * The serial port definition structure.
- */
-static struct plat_serial8250_port serial_platform_data[] = {
- {
- .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
- .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
- .uartclk = 14745600,
- .regshift = 0,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
- }, {
- .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
- .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
- .uartclk = 14745600,
- .regshift = 0,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
- },
- {},
-};
-
-static struct platform_device serial_device = {
- .name = "serial8250",
- .id = 0,
- .dev = {
- .platform_data = serial_platform_data,
- },
-};
-
-static struct resource mx31ads_cs8900_resources[] __initdata = {
- DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
- DEFINE_RES_IRQ(-1),
-};
-
-static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
- .name = "cs89x0",
- .id = 0,
- .res = mx31ads_cs8900_resources,
- .num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
-};
-
-static int __init mxc_init_extuart(void)
-{
- serial_platform_data[0].irq = irq_find_mapping(domain,
- EXPIO_INT_XUART_INTA);
- serial_platform_data[1].irq = irq_find_mapping(domain,
- EXPIO_INT_XUART_INTB);
- return platform_device_register(&serial_device);
-}
-
-static void __init mxc_init_ext_ethernet(void)
-{
- mx31ads_cs8900_resources[1].start =
- irq_find_mapping(domain, EXPIO_INT_ENET_INT);
- mx31ads_cs8900_resources[1].end =
- irq_find_mapping(domain, EXPIO_INT_ENET_INT);
- platform_device_register_full(
- (struct platform_device_info *)&mx31ads_cs8900_devinfo);
-}
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static unsigned int uart_pins[] = {
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1
-};
-
-static inline void mxc_init_imx_uart(void)
-{
- mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
- imx31_add_imx_uart0(&uart_pdata);
-}
-
-static void mx31ads_expio_irq_handler(struct irq_desc *desc)
-{
- u32 imr_val;
- u32 int_valid;
- u32 expio_irq;
-
- imr_val = imx_readw(PBC_INTMASK_SET_REG);
- int_valid = imx_readw(PBC_INTSTATUS_REG) & imr_val;
-
- expio_irq = 0;
- for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
- if ((int_valid & 1) == 0)
- continue;
-
- generic_handle_irq(irq_find_mapping(domain, expio_irq));
- }
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param d an expio virtual irq description
- */
-static void expio_mask_irq(struct irq_data *d)
-{
- u32 expio = d->hwirq;
- /* mask the interrupt */
- imx_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
- imx_readw(PBC_INTMASK_CLEAR_REG);
-}
-
-/*
- * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param d an expio virtual irq description
- */
-static void expio_ack_irq(struct irq_data *d)
-{
- u32 expio = d->hwirq;
- /* clear the interrupt status */
- imx_writew(1 << expio, PBC_INTSTATUS_REG);
-}
-
-/*
- * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param d an expio virtual irq description
- */
-static void expio_unmask_irq(struct irq_data *d)
-{
- u32 expio = d->hwirq;
- /* unmask the interrupt */
- imx_writew(1 << expio, PBC_INTMASK_SET_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
- .name = "EXPIO(CPLD)",
- .irq_ack = expio_ack_irq,
- .irq_mask = expio_mask_irq,
- .irq_unmask = expio_unmask_irq,
-};
-
-static void __init mx31ads_init_expio(void)
-{
- int irq_base;
- int i, irq;
-
- printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
-
- /*
- * Configure INT line as GPIO input
- */
- mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
-
- /* disable the interrupt and clear the status */
- imx_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
- imx_writew(0xFFFF, PBC_INTSTATUS_REG);
-
- irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
- WARN_ON(irq_base < 0);
-
- domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
- &irq_domain_simple_ops, NULL);
- WARN_ON(!domain);
-
- for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
- irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
- irq_clear_status_flags(i, IRQ_NOREQUEST);
- }
- irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
- irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
- irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
-}
-
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
-/* This section defines setup for the Wolfson Microelectronics
- * 1133-EV1 PMU/audio board. When other PMU boards are supported the
- * regulator definitions may be shared with them, but for now they can
- * only be used with this board so would generate warnings about
- * unused statics and some of the configuration is specific to this
- * module.
- */
-
-/* CPU */
-static struct regulator_consumer_supply sw1a_consumers[] = {
- {
- .supply = "cpu_vcc",
- }
-};
-
-static struct regulator_init_data sw1a_data = {
- .constraints = {
- .name = "SW1A",
- .min_uV = 1275000,
- .max_uV = 1600000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_FAST,
- .state_mem = {
- .uV = 1400000,
- .mode = REGULATOR_MODE_NORMAL,
- .enabled = 1,
- },
- .initial_state = PM_SUSPEND_MEM,
- .always_on = 1,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
- .consumer_supplies = sw1a_consumers,
-};
-
-/* System IO - High */
-static struct regulator_init_data viohi_data = {
- .constraints = {
- .name = "VIOHO",
- .min_uV = 2800000,
- .max_uV = 2800000,
- .state_mem = {
- .uV = 2800000,
- .mode = REGULATOR_MODE_NORMAL,
- .enabled = 1,
- },
- .initial_state = PM_SUSPEND_MEM,
- .always_on = 1,
- .boot_on = 1,
- },
-};
-
-/* System IO - Low */
-static struct regulator_init_data violo_data = {
- .constraints = {
- .name = "VIOLO",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .state_mem = {
- .uV = 1800000,
- .mode = REGULATOR_MODE_NORMAL,
- .enabled = 1,
- },
- .initial_state = PM_SUSPEND_MEM,
- .always_on = 1,
- .boot_on = 1,
- },
-};
-
-/* DDR RAM */
-static struct regulator_init_data sw2a_data = {
- .constraints = {
- .name = "SW2A",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .state_mem = {
- .uV = 1800000,
- .mode = REGULATOR_MODE_NORMAL,
- .enabled = 1,
- },
- .state_disk = {
- .mode = REGULATOR_MODE_NORMAL,
- .enabled = 0,
- },
- .always_on = 1,
- .boot_on = 1,
- .initial_state = PM_SUSPEND_MEM,
- },
-};
-
-static struct regulator_init_data ldo1_data = {
- .constraints = {
- .name = "VCAM/VMMC1/VMMC2",
- .min_uV = 2800000,
- .max_uV = 2800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = 1,
- },
-};
-
-static struct regulator_consumer_supply ldo2_consumers[] = {
- { .supply = "AVDD", .dev_name = "1-001a" },
- { .supply = "HPVDD", .dev_name = "1-001a" },
-};
-
-/* CODEC and SIM */
-static struct regulator_init_data ldo2_data = {
- .constraints = {
- .name = "VESIM/VSIM/AVDD",
- .min_uV = 3300000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
- .consumer_supplies = ldo2_consumers,
-};
-
-/* General */
-static struct regulator_init_data vdig_data = {
- .constraints = {
- .name = "VDIG",
- .min_uV = 1500000,
- .max_uV = 1500000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .apply_uV = 1,
- .always_on = 1,
- .boot_on = 1,
- },
-};
-
-/* Tranceivers */
-static struct regulator_init_data ldo4_data = {
- .constraints = {
- .name = "VRF1/CVDD_2.775",
- .min_uV = 2500000,
- .max_uV = 2500000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .apply_uV = 1,
- .always_on = 1,
- .boot_on = 1,
- },
-};
-
-static struct wm8350_led_platform_data wm8350_led_data = {
- .name = "wm8350:white",
- .default_trigger = "heartbeat",
- .max_uA = 27899,
-};
-
-static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
- .vmid_discharge_msecs = 1000,
- .drain_msecs = 30,
- .cap_discharge_msecs = 700,
- .vmid_charge_msecs = 700,
- .vmid_s_curve = WM8350_S_CURVE_SLOW,
- .dis_out4 = WM8350_DISCHARGE_SLOW,
- .dis_out3 = WM8350_DISCHARGE_SLOW,
- .dis_out2 = WM8350_DISCHARGE_SLOW,
- .dis_out1 = WM8350_DISCHARGE_SLOW,
- .vroi_out4 = WM8350_TIE_OFF_500R,
- .vroi_out3 = WM8350_TIE_OFF_500R,
- .vroi_out2 = WM8350_TIE_OFF_500R,
- .vroi_out1 = WM8350_TIE_OFF_500R,
- .vroi_enable = 0,
- .codec_current_on = WM8350_CODEC_ISEL_1_0,
- .codec_current_standby = WM8350_CODEC_ISEL_0_5,
- .codec_current_charge = WM8350_CODEC_ISEL_1_5,
-};
-
-static int mx31_wm8350_init(struct wm8350 *wm8350)
-{
- wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
- WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
- WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_ON);
-
- wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
- WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
- WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_ON);
-
- wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
- WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
- WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_OFF);
-
- wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
- WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
- WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_OFF);
-
- wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
- WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
- WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_OFF);
-
- wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
- WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
- WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_OFF);
-
- wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
- WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
- WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_OFF);
-
- wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
- wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
- wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
- wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
- wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
- wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
- wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
- wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
-
- /* LEDs */
- wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
- WM8350_DC5_ERRACT_SHUTDOWN_CONV);
- wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
- WM8350_ISINK_FLASH_DISABLE,
- WM8350_ISINK_FLASH_TRIG_BIT,
- WM8350_ISINK_FLASH_DUR_32MS,
- WM8350_ISINK_FLASH_ON_INSTANT,
- WM8350_ISINK_FLASH_OFF_INSTANT,
- WM8350_ISINK_FLASH_MODE_EN);
- wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
- WM8350_ISINK_MODE_BOOST,
- WM8350_ISINK_ILIM_NORMAL,
- WM8350_DC5_RMP_20V,
- WM8350_DC5_FBSRC_ISINKA);
- wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
- &wm8350_led_data);
-
- wm8350->codec.platform_data = &imx32ads_wm8350_setup;
-
- regulator_has_full_constraints();
-
- return 0;
-}
-
-static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
- .init = mx31_wm8350_init,
-};
-#endif
-
-static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
- {
- I2C_BOARD_INFO("wm8350", 0x1a),
- .platform_data = &mx31_wm8350_pdata,
- /* irq number is run-time assigned */
- },
-#endif
-};
-
-static void __init mxc_init_i2c(void)
-{
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
- mx31ads_i2c1_devices[0].irq =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
-#endif
- i2c_register_board_info(1, mx31ads_i2c1_devices,
- ARRAY_SIZE(mx31ads_i2c1_devices));
-
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
-
- imx31_add_imx_i2c1(NULL);
-}
-
-static unsigned int ssi_pins[] = {
- MX31_PIN_SFS5__SFS5,
- MX31_PIN_SCK5__SCK5,
- MX31_PIN_SRXD5__SRXD5,
- MX31_PIN_STXD5__STXD5,
-};
-
-static void __init mxc_init_audio(void)
-{
- imx31_add_imx_ssi(0, NULL);
- mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
-}
-
-/*
- * Static mappings, starting from the CS4 start address up to the start address
- * of the CS8900.
- */
-static struct map_desc mx31ads_io_desc[] __initdata = {
- {
- .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
- .length = CS4_CS8900_MMIO_START,
- .type = MT_DEVICE
- },
-};
-
-static void __init mx31ads_map_io(void)
-{
- mx31_map_io();
- iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
-}
-
-static void __init mx31ads_init(void)
-{
- imx31_soc_init();
-
- mxc_init_imx_uart();
- mxc_init_audio();
-}
-
-static void __init mx31ads_late(void)
-{
- mx31ads_init_expio();
- mxc_init_extuart();
- mxc_init_i2c();
- mxc_init_ext_ethernet();
-}
-
-static void __init mx31ads_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-MACHINE_START(MX31ADS, "Freescale MX31ADS")
- /* Maintainer: Freescale Semiconductor, Inc. */
- .atag_offset = 0x100,
- .map_io = mx31ads_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .init_time = mx31ads_timer_init,
- .init_machine = mx31ads_init,
- .init_late = mx31ads_late,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
deleted file mode 100644
index 8f72524..0000000
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ /dev/null
@@ -1,322 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * LILLY-1131 module support
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * based on code for other MX31 boards,
- *
- * Copyright 2005-2007 Freescale Semiconductor
- * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/moduleparam.h>
-#include <linux/smsc911x.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include "board-mx31lilly.h"
-#include "common.h"
-#include "devices-imx31.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
-
-/*
- * This file contains module-specific initialization routines for LILLY-1131.
- * Initialization of peripherals found on the baseboard is implemented in the
- * appropriate baseboard support code.
- */
-
-static unsigned int mx31lilly_pins[] __initdata = {
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
- MX31_PIN_CTS2__CTS2,
- MX31_PIN_RTS2__RTS2,
- MX31_PIN_TXD2__TXD2,
- MX31_PIN_RXD2__RXD2,
- MX31_PIN_CSPI3_MOSI__RXD3,
- MX31_PIN_CSPI3_MISO__TXD3,
- MX31_PIN_CSPI3_SCLK__RTS3,
- MX31_PIN_CSPI3_SPI_RDY__CTS3,
-};
-
-/* UART */
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-/* SMSC ethernet support */
-
-static struct resource smsc91x_resources[] = {
- {
- .start = MX31_CS4_BASE_ADDR,
- .end = MX31_CS4_BASE_ADDR + 0xffff,
- .flags = IORESOURCE_MEM,
- },
- {
- /* irq number is run-time assigned */
- .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
- }
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .phy_interface = PHY_INTERFACE_MODE_MII,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .flags = SMSC911X_USE_32BIT |
- SMSC911X_SAVE_MAC_ADDRESS |
- SMSC911X_FORCE_INTERNAL_PHY,
-};
-
-static struct platform_device smsc91x_device = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(smsc91x_resources),
- .resource = smsc91x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- }
-};
-
-/* NOR flash */
-static struct physmap_flash_data nor_flash_data = {
- .width = 2,
-};
-
-static struct resource nor_flash_resource = {
- .start = 0xa0000000,
- .end = 0xa1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device physmap_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &nor_flash_data,
- },
- .resource = &nor_flash_resource,
- .num_resources = 1,
-};
-
-/* USB */
-
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int usbh1_init(struct platform_device *pdev)
-{
- int pins[] = {
- MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
- MX31_PIN_CSPI1_MISO__USBH1_RXDP,
- MX31_PIN_CSPI1_SS0__USBH1_TXDM,
- MX31_PIN_CSPI1_SS1__USBH1_TXDP,
- MX31_PIN_CSPI1_SS2__USBH1_RCV,
- MX31_PIN_CSPI1_SCLK__USBH1_OEB,
- MX31_PIN_CSPI1_SPI_RDY__USBH1_FS,
- };
-
- mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1");
-
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
-
- mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
- MXC_EHCI_INTERFACE_SINGLE_UNI);
-}
-
-static int usbh2_init(struct platform_device *pdev)
-{
- int pins[] = {
- MX31_PIN_USBH2_DATA0__USBH2_DATA0,
- MX31_PIN_USBH2_DATA1__USBH2_DATA1,
- MX31_PIN_USBH2_CLK__USBH2_CLK,
- MX31_PIN_USBH2_DIR__USBH2_DIR,
- MX31_PIN_USBH2_NXT__USBH2_NXT,
- MX31_PIN_USBH2_STP__USBH2_STP,
- };
-
- mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
-
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
-
- mxc_iomux_set_gpr(MUX_PGP_UH2, true);
-
- /* chip select */
- mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
- "USBH2_CS");
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
- gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
- .init = usbh1_init,
- .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-};
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = usbh2_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-static void __init lilly1131_usb_init(void)
-{
- imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
-
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbh2_pdata.otg)
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-}
-
-/* SPI */
-
-static const struct spi_imx_master spi0_pdata __initconst = {
- .num_chipselect = 3,
-};
-
-static const struct spi_imx_master spi1_pdata __initconst = {
- .num_chipselect = 3,
-};
-
-static struct mc13xxx_platform_data mc13783_pdata __initdata = {
- .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
-};
-
-static struct spi_board_info mc13783_dev __initdata = {
- .modalias = "mc13783",
- .max_speed_hz = 1000000,
- .bus_num = 1,
- .chip_select = 0,
- .platform_data = &mc13783_pdata,
- /* irq number is run-time assigned */
-};
-
-static struct platform_device *devices[] __initdata = {
- &smsc91x_device,
- &physmap_flash_device,
-};
-
-static int mx31lilly_baseboard;
-core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
-
-static struct regulator_consumer_supply dummy_supplies[] = {
- REGULATOR_SUPPLY("vdd33a", "smsc911x"),
- REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
-static void __init mx31lilly_board_init(void)
-{
- imx31_soc_init();
-
- mxc_iomux_setup_multiple_pins(mx31lilly_pins,
- ARRAY_SIZE(mx31lilly_pins), "mx31lily");
-
- imx31_add_imx_uart0(&uart_pdata);
- imx31_add_imx_uart1(&uart_pdata);
- imx31_add_imx_uart2(&uart_pdata);
-
- mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS");
-
- /* SPI */
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2");
-
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
-
- imx31_add_spi_imx0(&spi0_pdata);
- imx31_add_spi_imx1(&spi1_pdata);
-
- regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-}
-
-static void __init mx31lilly_late_init(void)
-{
- if (mx31lilly_baseboard == MX31LILLY_DB)
- mx31lilly_db_init();
-
- mc13783_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
- spi_register_board_info(&mc13783_dev, 1);
-
- smsc91x_resources[1].start =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
- smsc91x_resources[1].end =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- /* USB */
- lilly1131_usb_init();
-}
-
-static void __init mx31lilly_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
- .atag_offset = 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .init_time = mx31lilly_timer_init,
- .init_machine = mx31lilly_board_init,
- .init_late = mx31lilly_late_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
deleted file mode 100644
index c0055f5..0000000
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ /dev/null
@@ -1,305 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/memory.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/moduleparam.h>
-#include <linux/smsc911x.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/spi/spi.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/mtd/physmap.h>
-#include <linux/delay.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-
-#include "board-mx31lite.h"
-#include "common.h"
-#include "devices-imx31.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
-
-/*
- * This file contains the module-specific initialization routines.
- */
-
-static unsigned int mx31lite_pins[] = {
- /* UART1 */
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
- /* SPI 0 */
- MX31_PIN_CSPI1_SCLK__SCLK,
- MX31_PIN_CSPI1_MOSI__MOSI,
- MX31_PIN_CSPI1_MISO__MISO,
- MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI1_SS0__SS0,
- MX31_PIN_CSPI1_SS1__SS1,
- MX31_PIN_CSPI1_SS2__SS2,
- /* LAN9117 IRQ pin */
- IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
- /* SPI 1 */
- MX31_PIN_CSPI2_SCLK__SCLK,
- MX31_PIN_CSPI2_MOSI__MOSI,
- MX31_PIN_CSPI2_MISO__MISO,
- MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI2_SS0__SS0,
- MX31_PIN_CSPI2_SS1__SS1,
- MX31_PIN_CSPI2_SS2__SS2,
-};
-
-/* UART */
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-/* SPI */
-static const struct spi_imx_master spi0_pdata __initconst = {
- .num_chipselect = 3,
-};
-
-static const struct mxc_nand_platform_data
-mx31lite_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
- .flags = SMSC911X_USE_16BIT,
-};
-
-static struct resource smsc911x_resources[] = {
- {
- .start = MX31_CS4_BASE_ADDR,
- .end = MX31_CS4_BASE_ADDR + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- /* irq number is run-time assigned */
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-
-/*
- * SPI
- *
- * The MC13783 is the only hard-wired SPI device on the module.
- */
-
-static const struct spi_imx_master spi1_pdata __initconst = {
- .num_chipselect = 1,
-};
-
-static struct mc13xxx_platform_data mc13783_pdata __initdata = {
- .flags = MC13XXX_USE_RTC,
-};
-
-static struct spi_board_info mc13783_spi_dev __initdata = {
- .modalias = "mc13783",
- .max_speed_hz = 1000000,
- .bus_num = 1,
- .chip_select = 0,
- .platform_data = &mc13783_pdata,
- /* irq number is run-time assigned */
-};
-
-/*
- * USB
- */
-
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int usbh2_init(struct platform_device *pdev)
-{
- int pins[] = {
- MX31_PIN_USBH2_DATA0__USBH2_DATA0,
- MX31_PIN_USBH2_DATA1__USBH2_DATA1,
- MX31_PIN_USBH2_CLK__USBH2_CLK,
- MX31_PIN_USBH2_DIR__USBH2_DIR,
- MX31_PIN_USBH2_NXT__USBH2_NXT,
- MX31_PIN_USBH2_STP__USBH2_STP,
- };
-
- mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
-
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
-
- mxc_iomux_set_gpr(MUX_PGP_UH2, true);
-
- /* chip select */
- mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
- "USBH2_CS");
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
- gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = usbh2_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-/*
- * NOR flash
- */
-
-static struct physmap_flash_data nor_flash_data = {
- .width = 2,
-};
-
-static struct resource nor_flash_resource = {
- .start = 0xa0000000,
- .end = 0xa1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device physmap_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &nor_flash_data,
- },
- .resource = &nor_flash_resource,
- .num_resources = 1,
-};
-
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc mx31lite_io_desc[] __initdata = {
- {
- .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
- .length = MX31_CS4_SIZE,
- .type = MT_DEVICE
- }
-};
-
-/*
- * Set up static virtual mappings.
- */
-static void __init mx31lite_map_io(void)
-{
- mx31_map_io();
- iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
-}
-
-static int mx31lite_baseboard;
-core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
-
-static struct regulator_consumer_supply dummy_supplies[] = {
- REGULATOR_SUPPLY("vdd33a", "smsc911x"),
- REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
-static void __init mx31lite_init(void)
-{
- imx31_soc_init();
-
- mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
- "mx31lite");
-
- imx31_add_imx_uart0(&uart_pdata);
- imx31_add_spi_imx0(&spi0_pdata);
-
- /* NOR and NAND flash */
- platform_device_register(&physmap_flash_device);
- imx31_add_mxc_nand(&mx31lite_nand_board_info);
-
- imx31_add_spi_imx1(&spi1_pdata);
-
- regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-}
-
-static void __init mx31lite_late(void)
-{
- int ret;
-
- if (mx31lite_baseboard == MX31LITE_DB)
- mx31lite_db_init();
-
- mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
- spi_register_board_info(&mc13783_spi_dev, 1);
-
- /* USB */
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbh2_pdata.otg)
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-
- /* SMSC9117 IRQ pin */
- ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
- if (ret)
- pr_warn("could not get LAN irq gpio\n");
- else {
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
- smsc911x_resources[1].start =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
- smsc911x_resources[1].end =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
- platform_device_register(&smsc911x_device);
- }
-}
-
-static void __init mx31lite_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
- /* Maintainer: Freescale Semiconductor, Inc. */
- .atag_offset = 0x100,
- .map_io = mx31lite_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .init_time = mx31lite_timer_init,
- .init_machine = mx31lite_init,
- .init_late = mx31lite_late,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
deleted file mode 100644
index 36f08f4..0000000
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ /dev/null
@@ -1,589 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group
- */
-
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/gfp.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/moduleparam.h>
-#include <linux/leds.h>
-#include <linux/memory.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/spi/spi.h>
-#include <linux/types.h>
-#include <linux/memblock.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/input.h>
-
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <asm/memblock.h>
-#include <linux/platform_data/asoc-imx-ssi.h>
-
-#include "board-mx31moboard.h"
-#include "common.h"
-#include "devices-imx31.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
-
-static unsigned int moboard_pins[] = {
- /* UART0 */
- MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
- MX31_PIN_CTS1__GPIO2_7,
- /* UART4 */
- MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
- MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
- /* I2C0 */
- MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL,
- /* I2C1 */
- MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL,
- /* SDHC1 */
- MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD,
- MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
- /* USB reset */
- MX31_PIN_GPIO1_0__GPIO1_0,
- /* USB OTG */
- MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
- MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
- MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
- MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
- MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
- MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
- MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
- MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
- MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
- MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
- MX31_PIN_USB_OC__GPIO1_30,
- /* USB H2 */
- MX31_PIN_USBH2_DATA0__USBH2_DATA0,
- MX31_PIN_USBH2_DATA1__USBH2_DATA1,
- MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3,
- MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5,
- MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7,
- MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR,
- MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP,
- MX31_PIN_SCK6__GPIO1_25,
- /* LEDs */
- MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
- MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
- /* SPI1 */
- MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO,
- MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2,
- /* Atlas IRQ */
- MX31_PIN_GPIO1_3__GPIO1_3,
- /* SPI2 */
- MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
- MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI2_SS1__CSPI3_SS1,
- /* SSI */
- MX31_PIN_STXD4__STXD4, MX31_PIN_SRXD4__SRXD4,
- MX31_PIN_SCK4__SCK4, MX31_PIN_SFS4__SFS4,
-};
-
-static struct physmap_flash_data mx31moboard_flash_data = {
- .width = 2,
-};
-
-static struct resource mx31moboard_flash_resource = {
- .start = 0xa0000000,
- .end = 0xa1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mx31moboard_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &mx31moboard_flash_data,
- },
- .resource = &mx31moboard_flash_resource,
- .num_resources = 1,
-};
-
-static void __init moboard_uart0_init(void)
-{
- if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack")) {
- gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
- gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
- }
-}
-
-static const struct imxuart_platform_data uart0_pdata __initconst = {
-};
-
-static const struct imxuart_platform_data uart4_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxi2c_platform_data moboard_i2c0_data __initconst = {
- .bitrate = 400000,
-};
-
-static const struct imxi2c_platform_data moboard_i2c1_data __initconst = {
- .bitrate = 100000,
-};
-
-static const struct spi_imx_master moboard_spi1_pdata __initconst = {
- .num_chipselect = 3,
-};
-
-static struct regulator_consumer_supply sdhc_consumers[] = {
- {
- .dev_name = "imx31-mmc.0",
- .supply = "sdhc0_vcc",
- },
- {
- .dev_name = "imx31-mmc.1",
- .supply = "sdhc1_vcc",
- },
-};
-
-static struct regulator_init_data sdhc_vreg_data = {
- .constraints = {
- .min_uV = 2700000,
- .max_uV = 3000000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
- .valid_modes_mask = REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_FAST,
- .always_on = 0,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers),
- .consumer_supplies = sdhc_consumers,
-};
-
-static struct regulator_consumer_supply cam_consumers[] = {
- {
- .dev_name = "mx3_camera.0",
- .supply = "cam_vcc",
- },
-};
-
-static struct regulator_init_data cam_vreg_data = {
- .constraints = {
- .min_uV = 2700000,
- .max_uV = 3000000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
- .valid_modes_mask = REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_FAST,
- .always_on = 0,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
- .consumer_supplies = cam_consumers,
-};
-
-static struct mc13xxx_regulator_init_data moboard_regulators[] = {
- {
- .id = MC13783_REG_VMMC1,
- .init_data = &sdhc_vreg_data,
- },
- {
- .id = MC13783_REG_VCAM,
- .init_data = &cam_vreg_data,
- },
-};
-
-static struct mc13xxx_led_platform_data moboard_led[] = {
- {
- .id = MC13783_LED_R1,
- .name = "coreboard-led-4:red",
- },
- {
- .id = MC13783_LED_G1,
- .name = "coreboard-led-4:green",
- },
- {
- .id = MC13783_LED_B1,
- .name = "coreboard-led-4:blue",
- },
- {
- .id = MC13783_LED_R2,
- .name = "coreboard-led-5:red",
- },
- {
- .id = MC13783_LED_G2,
- .name = "coreboard-led-5:green",
- },
- {
- .id = MC13783_LED_B2,
- .name = "coreboard-led-5:blue",
- },
-};
-
-static struct mc13xxx_leds_platform_data moboard_leds = {
- .num_leds = ARRAY_SIZE(moboard_led),
- .led = moboard_led,
- .led_control[0] = MC13783_LED_C0_ENABLE | MC13783_LED_C0_ABMODE(0),
- .led_control[1] = MC13783_LED_C1_SLEWLIM,
- .led_control[2] = MC13783_LED_C2_SLEWLIM,
- .led_control[3] = MC13783_LED_C3_PERIOD(0) |
- MC13783_LED_C3_CURRENT_R1(2) |
- MC13783_LED_C3_CURRENT_G1(2) |
- MC13783_LED_C3_CURRENT_B1(2),
- .led_control[4] = MC13783_LED_C4_PERIOD(0) |
- MC13783_LED_C4_CURRENT_R2(3) |
- MC13783_LED_C4_CURRENT_G2(3) |
- MC13783_LED_C4_CURRENT_B2(3),
-};
-
-static struct mc13xxx_buttons_platform_data moboard_buttons = {
- .b1on_flags = MC13783_BUTTON_DBNC_750MS | MC13783_BUTTON_ENABLE |
- MC13783_BUTTON_POL_INVERT,
- .b1on_key = KEY_POWER,
-};
-
-static struct mc13xxx_codec_platform_data moboard_codec = {
- .dac_ssi_port = MC13783_SSI1_PORT,
- .adc_ssi_port = MC13783_SSI1_PORT,
-};
-
-static struct mc13xxx_platform_data moboard_pmic = {
- .regulators = {
- .regulators = moboard_regulators,
- .num_regulators = ARRAY_SIZE(moboard_regulators),
- },
- .leds = &moboard_leds,
- .buttons = &moboard_buttons,
- .codec = &moboard_codec,
- .flags = MC13XXX_USE_RTC | MC13XXX_USE_ADC | MC13XXX_USE_CODEC,
-};
-
-static struct imx_ssi_platform_data moboard_ssi_pdata = {
- .flags = IMX_SSI_DMA | IMX_SSI_NET,
-};
-
-static struct spi_board_info moboard_spi_board_info[] __initdata = {
- {
- .modalias = "mc13783",
- /* irq number is run-time assigned */
- .max_speed_hz = 300000,
- .bus_num = 1,
- .chip_select = 0,
- .platform_data = &moboard_pmic,
- .mode = SPI_CS_HIGH,
- },
-};
-
-static const struct spi_imx_master moboard_spi2_pdata __initconst = {
- .num_chipselect = 2,
-};
-
-#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0)
-#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1)
-
-static int moboard_sdhc1_get_ro(struct device *dev)
-{
- return !gpio_get_value(SDHC1_WP);
-}
-
-static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request(SDHC1_CD, "sdhc-detect");
- if (ret)
- return ret;
-
- gpio_direction_input(SDHC1_CD);
-
- ret = gpio_request(SDHC1_WP, "sdhc-wp");
- if (ret)
- goto err_gpio_free;
- gpio_direction_input(SDHC1_WP);
-
- ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "sdhc1-card-detect", data);
- if (ret)
- goto err_gpio_free_2;
-
- return 0;
-
-err_gpio_free_2:
- gpio_free(SDHC1_WP);
-err_gpio_free:
- gpio_free(SDHC1_CD);
-
- return ret;
-}
-
-static void moboard_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(SDHC1_CD), data);
- gpio_free(SDHC1_WP);
- gpio_free(SDHC1_CD);
-}
-
-static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
- .get_ro = moboard_sdhc1_get_ro,
- .init = moboard_sdhc1_init,
- .exit = moboard_sdhc1_exit,
-};
-
-/*
- * this pin is dedicated for all mx31moboard systems, so we do it here
- */
-#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS)
-
-#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
-#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
-
-static void usb_xcvr_reset(void)
-{
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
-
- mxc_iomux_set_gpr(MUX_PGP_UH2, true);
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
-
- gpio_request(OTG_EN_B, "usb-udc-en");
- gpio_direction_output(OTG_EN_B, 0);
- gpio_request(USBH2_EN_B, "usbh2-en");
- gpio_direction_output(USBH2_EN_B, 0);
-
- gpio_request(USB_RESET_B, "usb-reset");
- gpio_direction_output(USB_RESET_B, 0);
- mdelay(1);
- gpio_set_value(USB_RESET_B, 1);
- mdelay(1);
-}
-
-static int moboard_usbh2_init_hw(struct platform_device *pdev)
-{
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = moboard_usbh2_init_hw,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-static int __init moboard_usbh2_init(void)
-{
- struct platform_device *pdev;
-
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (!usbh2_pdata.otg)
- return -ENODEV;
-
- pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-
- return PTR_ERR_OR_ZERO(pdev);
-}
-
-static const struct gpio_led mx31moboard_leds[] __initconst = {
- {
- .name = "coreboard-led-0:red:running",
- .default_trigger = "heartbeat",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
- }, {
- .name = "coreboard-led-1:red",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0),
- }, {
- .name = "coreboard-led-2:red",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0),
- }, {
- .name = "coreboard-led-3:red",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
- },
-};
-
-static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = {
- .num_leds = ARRAY_SIZE(mx31moboard_leds),
- .leds = mx31moboard_leds,
-};
-
-static struct platform_device *devices[] __initdata = {
- &mx31moboard_flash,
-};
-
-static struct mx3_camera_pdata camera_pdata __initdata = {
- .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
- .mclk_10khz = 4800,
-};
-
-static phys_addr_t mx3_camera_base __initdata;
-#define MX3_CAMERA_BUF_SIZE SZ_4M
-
-static int __init mx31moboard_init_cam(void)
-{
- int ret;
- struct platform_device *pdev;
-
- imx31_add_ipu_core();
-
- pdev = imx31_alloc_mx3_camera(&camera_pdata);
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
-
- ret = dma_declare_coherent_memory(&pdev->dev,
- mx3_camera_base, mx3_camera_base,
- MX3_CAMERA_BUF_SIZE);
- if (ret)
- goto err;
-
- ret = platform_device_add(pdev);
- if (ret)
-err:
- platform_device_put(pdev);
-
- return ret;
-
-}
-
-static void mx31moboard_poweroff(void)
-{
- struct clk *clk = clk_get_sys("imx2-wdt.0", NULL);
-
- if (!IS_ERR(clk))
- clk_prepare_enable(clk);
-
- mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
-
- imx_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-}
-
-static int mx31moboard_baseboard;
-core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
-
-/*
- * Board specific initialization.
- */
-static void __init mx31moboard_init(void)
-{
- imx31_soc_init();
-
- mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
- "moboard");
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- imx31_add_imx2_wdt();
-
- imx31_add_imx_uart0(&uart0_pdata);
- imx31_add_imx_uart4(&uart4_pdata);
-
- imx31_add_imx_i2c0(&moboard_i2c0_data);
- imx31_add_imx_i2c1(&moboard_i2c1_data);
-
- imx31_add_spi_imx1(&moboard_spi1_pdata);
- imx31_add_spi_imx2(&moboard_spi2_pdata);
-
- mx31moboard_init_cam();
-
- imx31_add_imx_ssi(0, &moboard_ssi_pdata);
-
- pm_power_off = mx31moboard_poweroff;
-}
-
-static void __init mx31moboard_late(void)
-{
- gpio_led_register_device(-1, &mx31moboard_led_pdata);
-
- moboard_uart0_init();
-
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
- moboard_spi_board_info[0].irq =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
- spi_register_board_info(moboard_spi_board_info,
- ARRAY_SIZE(moboard_spi_board_info));
-
- imx31_add_mxc_mmc(0, &sdhc1_pdata);
-
- usb_xcvr_reset();
- moboard_usbh2_init();
-
- imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
-
- switch (mx31moboard_baseboard) {
- case MX31NOBOARD:
- break;
- case MX31DEVBOARD:
- mx31moboard_devboard_init();
- break;
- case MX31MARXBOT:
- mx31moboard_marxbot_init();
- break;
- case MX31SMARTBOT:
- case MX31EYEBOT:
- mx31moboard_smartbot_init(mx31moboard_baseboard);
- break;
- default:
- printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n",
- mx31moboard_baseboard);
- }
-}
-
-static void __init mx31moboard_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-static void __init mx31moboard_reserve(void)
-{
- /* reserve 4 MiB for mx3-camera */
- mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
- MX3_CAMERA_BUF_SIZE);
-}
-
-MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
- /* Maintainer: Philippe Retornaz, EPFL Mobots group */
- .atag_offset = 0x100,
- .reserve = mx31moboard_reserve,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .init_time = mx31moboard_timer_init,
- .init_machine = mx31moboard_init,
- .init_late = mx31moboard_late,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
deleted file mode 100644
index 802e0ab..0000000
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ /dev/null
@@ -1,516 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * Copyright (C) 2011 Meprolight, Ltd.
- * Alex Gershgorin <alexg@meprolight.com>
- *
- * Modified from i.MX31 3-Stack Development System
- */
-
-/*
- * This machine is known as:
- * - i.MX35 3-Stack Development System
- * - i.MX35 Platform Development Kit (i.MX35 PDK)
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/memory.h>
-#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-
-#include <linux/mtd/physmap.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <video/platform_lcd.h>
-
-#include "3ds_debugboard.h"
-#include "common.h"
-#include "devices-imx35.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx35.h"
-
-#define GPIO_MC9S08DZ60_GPS_ENABLE 0
-#define GPIO_MC9S08DZ60_HDD_ENABLE 4
-#define GPIO_MC9S08DZ60_WIFI_ENABLE 5
-#define GPIO_MC9S08DZ60_LCD_ENABLE 6
-#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8
-
-static const struct fb_videomode fb_modedb[] = {
- {
- /* 800x480 @ 55 Hz */
- .name = "Ceramate-CLAA070VC01",
- .refresh = 55,
- .xres = 800,
- .yres = 480,
- .pixclock = 40000,
- .left_margin = 40,
- .right_margin = 40,
- .upper_margin = 5,
- .lower_margin = 5,
- .hsync_len = 20,
- .vsync_len = 10,
- .sync = FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
-};
-
-static struct mx3fb_platform_data mx3fb_pdata __initdata = {
- .name = "Ceramate-CLAA070VC01",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-static struct i2c_board_info __initdata i2c_devices_3ds[] = {
- {
- I2C_BOARD_INFO("mc9s08dz60", 0x69),
- },
-};
-
-static int lcd_power_gpio = -ENXIO;
-
-static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip, void *data)
-{
- return !strcmp(chip->label, data);
-}
-
-static void mx35_3ds_lcd_set_power(
- struct plat_lcd_data *pd, unsigned int power)
-{
- struct gpio_chip *chip;
-
- if (!gpio_is_valid(lcd_power_gpio)) {
- chip = gpiochip_find(
- "mc9s08dz60", mc9s08dz60_gpiochip_match);
- if (chip) {
- lcd_power_gpio =
- chip->base + GPIO_MC9S08DZ60_LCD_ENABLE;
- if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
- pr_err("error: gpio already requested!\n");
- lcd_power_gpio = -ENXIO;
- }
- } else {
- pr_err("error: didn't find mc9s08dz60 gpio chip\n");
- }
- }
-
- if (gpio_is_valid(lcd_power_gpio))
- gpio_set_value_cansleep(lcd_power_gpio, power);
-}
-
-static struct plat_lcd_data mx35_3ds_lcd_data = {
- .set_power = mx35_3ds_lcd_set_power,
-};
-
-static struct platform_device mx35_3ds_lcd = {
- .name = "platform-lcd",
- .dev.platform_data = &mx35_3ds_lcd_data,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct physmap_flash_data mx35pdk_flash_data = {
- .width = 2,
-};
-
-static struct resource mx35pdk_flash_resource = {
- .start = MX35_CS0_BASE_ADDR,
- .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mx35pdk_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &mx35pdk_flash_data,
- },
- .resource = &mx35pdk_flash_resource,
- .num_resources = 1,
-};
-
-static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
- .flash_bbt = 1,
-};
-
-static struct platform_device *devices[] __initdata = {
- &mx35pdk_flash,
-};
-
-static const iomux_v3_cfg_t mx35pdk_pads[] __initconst = {
- /* UART1 */
- MX35_PAD_CTS1__UART1_CTS,
- MX35_PAD_RTS1__UART1_RTS,
- MX35_PAD_TXD1__UART1_TXD_MUX,
- MX35_PAD_RXD1__UART1_RXD_MUX,
- /* FEC */
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
- MX35_PAD_FEC_RX_DV__FEC_RX_DV,
- MX35_PAD_FEC_COL__FEC_COL,
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
- MX35_PAD_FEC_TX_EN__FEC_TX_EN,
- MX35_PAD_FEC_MDC__FEC_MDC,
- MX35_PAD_FEC_MDIO__FEC_MDIO,
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
- MX35_PAD_FEC_CRS__FEC_CRS,
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
- /* USBOTG */
- MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
- MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
- /* USBH1 */
- MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
- MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
- /* SDCARD */
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- /* I2C1 */
- MX35_PAD_I2C1_CLK__I2C1_SCL,
- MX35_PAD_I2C1_DAT__I2C1_SDA,
- /* Display */
- MX35_PAD_LD0__IPU_DISPB_DAT_0,
- MX35_PAD_LD1__IPU_DISPB_DAT_1,
- MX35_PAD_LD2__IPU_DISPB_DAT_2,
- MX35_PAD_LD3__IPU_DISPB_DAT_3,
- MX35_PAD_LD4__IPU_DISPB_DAT_4,
- MX35_PAD_LD5__IPU_DISPB_DAT_5,
- MX35_PAD_LD6__IPU_DISPB_DAT_6,
- MX35_PAD_LD7__IPU_DISPB_DAT_7,
- MX35_PAD_LD8__IPU_DISPB_DAT_8,
- MX35_PAD_LD9__IPU_DISPB_DAT_9,
- MX35_PAD_LD10__IPU_DISPB_DAT_10,
- MX35_PAD_LD11__IPU_DISPB_DAT_11,
- MX35_PAD_LD12__IPU_DISPB_DAT_12,
- MX35_PAD_LD13__IPU_DISPB_DAT_13,
- MX35_PAD_LD14__IPU_DISPB_DAT_14,
- MX35_PAD_LD15__IPU_DISPB_DAT_15,
- MX35_PAD_LD16__IPU_DISPB_DAT_16,
- MX35_PAD_LD17__IPU_DISPB_DAT_17,
- MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
- MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
- MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
- MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
- MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
- MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
- MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
- /*PMIC IRQ*/
- MX35_PAD_GPIO2_0__GPIO2_0,
-};
-
-static struct regulator_consumer_supply sw1_consumers[] = {
- {
- .supply = "cpu_vcc",
- }
-};
-
-static struct regulator_consumer_supply vcam_consumers[] = {
- /* sgtl5000 */
- REGULATOR_SUPPLY("VDDA", "0-000a"),
-};
-
-static struct regulator_init_data sw1_init = {
- .constraints = {
- .name = "SW1",
- .min_uV = 600000,
- .max_uV = 1375000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- .valid_modes_mask = 0,
- .always_on = 1,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
- .consumer_supplies = sw1_consumers,
-};
-
-static struct regulator_init_data sw2_init = {
- .constraints = {
- .name = "SW2",
- .always_on = 1,
- .boot_on = 1,
- }
-};
-
-static struct regulator_init_data sw3_init = {
- .constraints = {
- .name = "SW3",
- .always_on = 1,
- .boot_on = 1,
- }
-};
-
-static struct regulator_init_data sw4_init = {
- .constraints = {
- .name = "SW4",
- .always_on = 1,
- .boot_on = 1,
- }
-};
-
-static struct regulator_init_data viohi_init = {
- .constraints = {
- .name = "VIOHI",
- .boot_on = 1,
- }
-};
-
-static struct regulator_init_data vusb_init = {
- .constraints = {
- .name = "VUSB",
- .boot_on = 1,
- }
-};
-
-static struct regulator_init_data vdig_init = {
- .constraints = {
- .name = "VDIG",
- .boot_on = 1,
- }
-};
-
-static struct regulator_init_data vpll_init = {
- .constraints = {
- .name = "VPLL",
- .boot_on = 1,
- }
-};
-
-static struct regulator_init_data vusb2_init = {
- .constraints = {
- .name = "VUSB2",
- .boot_on = 1,
- }
-};
-
-static struct regulator_init_data vvideo_init = {
- .constraints = {
- .name = "VVIDEO",
- .boot_on = 1
- }
-};
-
-static struct regulator_init_data vcam_init = {
- .constraints = {
- .name = "VCAM",
- .min_uV = 2500000,
- .max_uV = 3000000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
- .boot_on = 1
- },
- .num_consumer_supplies = ARRAY_SIZE(vcam_consumers),
- .consumer_supplies = vcam_consumers,
-};
-
-static struct regulator_init_data vgen1_init = {
- .constraints = {
- .name = "VGEN1",
- }
-};
-
-static struct regulator_init_data vgen2_init = {
- .constraints = {
- .name = "VGEN2",
- .boot_on = 1,
- }
-};
-
-static struct regulator_init_data vgen3_init = {
- .constraints = {
- .name = "VGEN3",
- }
-};
-
-static struct mc13xxx_regulator_init_data mx35_3ds_regulators[] = {
- { .id = MC13892_SW1, .init_data = &sw1_init },
- { .id = MC13892_SW2, .init_data = &sw2_init },
- { .id = MC13892_SW3, .init_data = &sw3_init },
- { .id = MC13892_SW4, .init_data = &sw4_init },
- { .id = MC13892_VIOHI, .init_data = &viohi_init },
- { .id = MC13892_VPLL, .init_data = &vpll_init },
- { .id = MC13892_VDIG, .init_data = &vdig_init },
- { .id = MC13892_VUSB2, .init_data = &vusb2_init },
- { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
- { .id = MC13892_VCAM, .init_data = &vcam_init },
- { .id = MC13892_VGEN1, .init_data = &vgen1_init },
- { .id = MC13892_VGEN2, .init_data = &vgen2_init },
- { .id = MC13892_VGEN3, .init_data = &vgen3_init },
- { .id = MC13892_VUSB, .init_data = &vusb_init },
-};
-
-static struct mc13xxx_platform_data mx35_3ds_mc13892_data = {
- .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
- .regulators = {
- .num_regulators = ARRAY_SIZE(mx35_3ds_regulators),
- .regulators = mx35_3ds_regulators,
- },
-};
-
-#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
-
-static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
-
- I2C_BOARD_INFO("mc13892", 0x08),
- .platform_data = &mx35_3ds_mc13892_data,
- /* irq number is run-time assigned */
-};
-
-static void __init imx35_3ds_init_mc13892(void)
-{
- int ret = gpio_request_one(GPIO_PMIC_INT, GPIOF_DIR_IN, "pmic irq");
-
- if (ret) {
- pr_err("failed to get pmic irq: %d\n", ret);
- return;
- }
-
- mx35_3ds_i2c_mc13892.irq = gpio_to_irq(GPIO_PMIC_INT);
- i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
-}
-
-static int mx35_3ds_otg_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
-}
-
-/* OTG config */
-static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
- .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
-/*
- * ENGCM09152 also requires a hardware change.
- * Please check the MX35 Chip Errata document for details.
- */
-};
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
- .init = mx35_3ds_otg_init,
- .portsc = MXC_EHCI_MODE_UTMI,
-};
-
-static int mx35_3ds_usbh_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
- MXC_EHCI_INTERNAL_PHY);
-}
-
-/* USB HOST config */
-static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
- .init = mx35_3ds_usbh_init,
- .portsc = MXC_EHCI_MODE_SERIAL,
-};
-
-static bool otg_mode_host __initdata;
-
-static int __init mx35_3ds_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = true;
- else if (!strcmp(options, "device"))
- otg_mode_host = false;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 1;
-}
-__setup("otg_mode=", mx35_3ds_otg_mode);
-
-static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
- .bitrate = 100000,
-};
-
-/*
- * Board specific initialization.
- */
-static void __init mx35_3ds_init(void)
-{
- imx35_soc_init();
-
- mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
-
- imx35_add_fec(NULL);
- imx35_add_imx2_wdt();
- imx35_add_mxc_rtc();
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- imx35_add_imx_uart0(&uart_pdata);
-
- if (otg_mode_host)
- imx35_add_mxc_ehci_otg(&otg_pdata);
-
- imx35_add_mxc_ehci_hs(&usb_host_pdata);
-
- if (!otg_mode_host)
- imx35_add_fsl_usb2_udc(&usb_otg_pdata);
-
- imx35_add_mxc_nand(&mx35pdk_nand_board_info);
- imx35_add_sdhci_esdhc_imx(0, NULL);
-
- imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
-
- i2c_register_board_info(
- 0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
-
- imx35_add_ipu_core();
-}
-
-static void __init mx35_3ds_late_init(void)
-{
- struct platform_device *imx35_fb_pdev;
-
- if (mxc_expio_init(MX35_CS5_BASE_ADDR, IMX_GPIO_NR(1, 1)))
- pr_warn("Init of the debugboard failed, all "
- "devices on the debugboard are unusable.\n");
-
- imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
- mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
- platform_device_register(&mx35_3ds_lcd);
-
- imx35_3ds_init_mc13892();
-}
-
-static void __init mx35pdk_timer_init(void)
-{
- mx35_clocks_init();
-}
-
-MACHINE_START(MX35_3DS, "Freescale MX35PDK")
- /* Maintainer: Freescale Semiconductor, Inc */
- .atag_offset = 0x100,
- .map_io = mx35_map_io,
- .init_early = imx35_init_early,
- .init_irq = mx35_init_irq,
- .init_time = mx35pdk_timer_init,
- .init_machine = mx35_3ds_init,
- .init_late = mx35_3ds_late_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
deleted file mode 100644
index 2e28e1b..0000000
--- a/arch/arm/mach-imx/mach-pca100.c
+++ /dev/null
@@ -1,417 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/property.h>
-#include <linux/dma-mapping.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-#include "devices-imx27.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx27.h"
-#include "ulpi.h"
-
-#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
-#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
-#define SPI1_SS0 (GPIO_PORTD + 28)
-#define SPI1_SS1 (GPIO_PORTD + 27)
-#define SD2_CD (GPIO_PORTC + 29)
-
-static const int pca100_pins[] __initconst = {
- /* UART1 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* SDHC */
- PB4_PF_SD2_D0,
- PB5_PF_SD2_D1,
- PB6_PF_SD2_D2,
- PB7_PF_SD2_D3,
- PB8_PF_SD2_CMD,
- PB9_PF_SD2_CLK,
- SD2_CD | GPIO_GPIO | GPIO_IN,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
- /* SSI1 */
- PC20_PF_SSI1_FS,
- PC21_PF_SSI1_RXD,
- PC22_PF_SSI1_TXD,
- PC23_PF_SSI1_CLK,
- /* onboard I2C */
- PC5_PF_I2C2_SDA,
- PC6_PF_I2C2_SCL,
- /* external I2C */
- PD17_PF_I2C_DATA,
- PD18_PF_I2C_CLK,
- /* SPI1 */
- PD25_PF_CSPI1_RDY,
- PD29_PF_CSPI1_SCLK,
- PD30_PF_CSPI1_MISO,
- PD31_PF_CSPI1_MOSI,
- /* OTG */
- OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
- PC7_PF_USBOTG_DATA5,
- PC8_PF_USBOTG_DATA6,
- PC9_PF_USBOTG_DATA0,
- PC10_PF_USBOTG_DATA2,
- PC11_PF_USBOTG_DATA1,
- PC12_PF_USBOTG_DATA4,
- PC13_PF_USBOTG_DATA3,
- PE0_PF_USBOTG_NXT,
- PE1_PF_USBOTG_STP,
- PE2_PF_USBOTG_DIR,
- PE24_PF_USBOTG_CLK,
- PE25_PF_USBOTG_DATA7,
- /* USBH2 */
- USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
- PA0_PF_USBH2_CLK,
- PA1_PF_USBH2_DIR,
- PA2_PF_USBH2_DATA7,
- PA3_PF_USBH2_NXT,
- PA4_PF_USBH2_STP,
- PD19_AF_USBH2_DATA4,
- PD20_AF_USBH2_DATA3,
- PD21_AF_USBH2_DATA6,
- PD22_AF_USBH2_DATA0,
- PD23_AF_USBH2_DATA2,
- PD24_AF_USBH2_DATA1,
- PD26_AF_USBH2_DATA5,
- /* display */
- PA5_PF_LSCLK,
- PA6_PF_LD0,
- PA7_PF_LD1,
- PA8_PF_LD2,
- PA9_PF_LD3,
- PA10_PF_LD4,
- PA11_PF_LD5,
- PA12_PF_LD6,
- PA13_PF_LD7,
- PA14_PF_LD8,
- PA15_PF_LD9,
- PA16_PF_LD10,
- PA17_PF_LD11,
- PA18_PF_LD12,
- PA19_PF_LD13,
- PA20_PF_LD14,
- PA21_PF_LD15,
- PA22_PF_LD16,
- PA23_PF_LD17,
- PA26_PF_PS,
- PA28_PF_HSYNC,
- PA29_PF_VSYNC,
- PA31_PF_OE_ACD,
- /* free GPIO */
- GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
- GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
- GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct mxc_nand_platform_data
-pca100_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
- .bitrate = 100000,
-};
-
-static const struct property_entry board_eeprom_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 32),
- { }
-};
-
-static struct i2c_board_info pca100_i2c_devices[] = {
- {
- I2C_BOARD_INFO("24c32", 0x52), /* E0=0, E1=1, E2=0 */
- .properties = board_eeprom_properties,
- }, {
- I2C_BOARD_INFO("pcf8563", 0x51),
- }, {
- I2C_BOARD_INFO("lm75", 0x4a),
- }
-};
-
-static struct spi_eeprom at25320 = {
- .name = "at25320an",
- .byte_len = 4096,
- .page_size = 32,
- .flags = EE_ADDR2,
-};
-
-static struct spi_board_info pca100_spi_board_info[] __initdata = {
- {
- .modalias = "at25",
- .max_speed_hz = 30000,
- .bus_num = 0,
- .chip_select = 1,
- .platform_data = &at25320,
- },
-};
-
-static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
-
-static const struct spi_imx_master pca100_spi0_data __initconst = {
- .chipselect = pca100_spi_cs,
- .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
-};
-
-static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
-{
- mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);
- gpio_set_value(GPIO_PORTC + 20, 1);
- udelay(2);
- gpio_set_value(GPIO_PORTC + 20, 0);
- mxc_gpio_mode(PC20_PF_SSI1_FS);
- msleep(2);
-}
-
-static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
-{
- mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */
- gpio_set_value(GPIO_PORTC + 20, 0);
- mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */
- gpio_set_value(GPIO_PORTC + 22, 0);
- mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */
- gpio_set_value(GPIO_PORTC + 28, 0);
- udelay(10);
- gpio_set_value(GPIO_PORTC + 28, 1);
- mxc_gpio_mode(PC20_PF_SSI1_FS);
- mxc_gpio_mode(PC22_PF_SSI1_TXD);
- msleep(2);
-}
-
-static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = {
- .ac97_reset = pca100_ac97_cold_reset,
- .ac97_warm_reset = pca100_ac97_warm_reset,
- .flags = IMX_SSI_USE_AC97,
-};
-
-static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
- IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
- if (ret)
- printk(KERN_ERR
- "pca100: Failed to request irq for sd/mmc detection\n");
-
- return ret;
-}
-
-static void pca100_sdhc2_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
-}
-
-static const struct imxmmc_platform_data sdhc_pdata __initconst = {
- .init = pca100_sdhc2_init,
- .exit = pca100_sdhc2_exit,
-};
-
-static int otg_phy_init(struct platform_device *pdev)
-{
- gpio_set_value(OTG_PHY_CS_GPIO, 0);
-
- mdelay(10);
-
- return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
- .init = otg_phy_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static int usbh2_phy_init(struct platform_device *pdev)
-{
- gpio_set_value(USBH2_PHY_CS_GPIO, 0);
-
- mdelay(10);
-
- return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = usbh2_phy_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-static bool otg_mode_host __initdata;
-
-static int __init pca100_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = true;
- else if (!strcmp(options, "device"))
- otg_mode_host = false;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 1;
-}
-__setup("otg_mode=", pca100_otg_mode);
-
-/* framebuffer info */
-static struct imx_fb_videomode pca100_fb_modes[] = {
- {
- .mode = {
- .name = "EMERGING-ETV570G0DHU",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = 39722, /* in ps (25.175 MHz) */
- .hsync_len = 30,
- .left_margin = 114,
- .right_margin = 16,
- .vsync_len = 3,
- .upper_margin = 32,
- .lower_margin = 0,
- },
- /*
- * TFT
- * Pixel pol active high
- * HSYNC active low
- * VSYNC active low
- * use HSYNC for ACD count
- * line clock disable while idle
- * always enable line clock even if no data
- */
- .pcr = 0xf0c08080,
- .bpp = 16,
- },
-};
-
-static const struct imx_fb_platform_data pca100_fb_data __initconst = {
- .mode = pca100_fb_modes,
- .num_modes = ARRAY_SIZE(pca100_fb_modes),
-
- .pwmr = 0x00A903FF,
- .lscr1 = 0x00120300,
- .dmacr = 0x00020010,
-};
-
-static void __init pca100_init(void)
-{
- int ret;
-
- imx27_soc_init();
-
- ret = mxc_gpio_setup_multiple_pins(pca100_pins,
- ARRAY_SIZE(pca100_pins), "PCA100");
- if (ret)
- printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
-
- imx27_add_imx_uart0(&uart_pdata);
-
- imx27_add_mxc_nand(&pca100_nand_board_info);
-
- /* only the i2c master 1 is used on this CPU card */
- i2c_register_board_info(1, pca100_i2c_devices,
- ARRAY_SIZE(pca100_i2c_devices));
-
- imx27_add_imx_i2c(1, &pca100_i2c1_data);
-
- mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
- mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
- spi_register_board_info(pca100_spi_board_info,
- ARRAY_SIZE(pca100_spi_board_info));
- imx27_add_spi_imx0(&pca100_spi0_data);
-
- imx27_add_imx_fb(&pca100_fb_data);
-
- imx27_add_fec(NULL);
- imx27_add_imx2_wdt();
- imx27_add_mxc_w1();
-}
-
-static void __init pca100_late_init(void)
-{
- imx27_add_imx_ssi(0, &pca100_ssi_pdata);
-
- imx27_add_mxc_mmc(1, &sdhc_pdata);
-
- gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
- gpio_direction_output(OTG_PHY_CS_GPIO, 1);
- gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
- gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
-
- if (otg_mode_host) {
- otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
-
- if (otg_pdata.otg)
- imx27_add_mxc_ehci_otg(&otg_pdata);
- } else {
- gpio_set_value(OTG_PHY_CS_GPIO, 0);
- imx27_add_fsl_usb2_udc(&otg_device_pdata);
- }
-
- usbh2_pdata.otg = imx_otg_ulpi_create(
- ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
-
- if (usbh2_pdata.otg)
- imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
-}
-
-static void __init pca100_timer_init(void)
-{
- mx27_clocks_init(26000000);
-}
-
-MACHINE_START(PCA100, "phyCARD-i.MX27")
- .atag_offset = 0x100,
- .map_io = mx27_map_io,
- .init_early = imx27_init_early,
- .init_irq = mx27_init_irq,
- .init_machine = pca100_init,
- .init_late = pca100_late_init,
- .init_time = pca100_timer_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
deleted file mode 100644
index bd9443f..0000000
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ /dev/null
@@ -1,585 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2008 Sascha Hauer, Pengutronix
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/memory.h>
-#include <linux/gpio.h>
-#include <linux/smsc911x.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/property.h>
-#include <linux/delay.h>
-#include <linux/spi/spi.h>
-#include <linux/irq.h>
-#include <linux/can/platform/sja1000.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/gfp.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices-imx31.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "pcm037.h"
-#include "ulpi.h"
-
-static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
-
-static int __init pcm037_variant_setup(char *str)
-{
- if (!strcmp("eet", str))
- pcm037_instance = PCM037_EET;
- else if (strcmp("pcm970", str))
- pr_warn("Unknown pcm037 baseboard variant %s\n", str);
-
- return 1;
-}
-
-/* Supported values: "pcm970" (default) and "eet" */
-__setup("pcm037_variant=", pcm037_variant_setup);
-
-enum pcm037_board_variant pcm037_variant(void)
-{
- return pcm037_instance;
-}
-
-/* UART1 with RTS/CTS handshake signals */
-static unsigned int pcm037_uart1_handshake_pins[] = {
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
-};
-
-/* UART1 without RTS/CTS handshake signals */
-static unsigned int pcm037_uart1_pins[] = {
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
-};
-
-static unsigned int pcm037_pins[] = {
- /* I2C */
- MX31_PIN_CSPI2_MOSI__SCL,
- MX31_PIN_CSPI2_MISO__SDA,
- MX31_PIN_CSPI2_SS2__I2C3_SDA,
- MX31_PIN_CSPI2_SCLK__I2C3_SCL,
- /* SDHC1 */
- MX31_PIN_SD1_DATA3__SD1_DATA3,
- MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA1__SD1_DATA1,
- MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_CLK__SD1_CLK,
- MX31_PIN_SD1_CMD__SD1_CMD,
- IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
- IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
- /* SPI1 */
- MX31_PIN_CSPI1_MOSI__MOSI,
- MX31_PIN_CSPI1_MISO__MISO,
- MX31_PIN_CSPI1_SCLK__SCLK,
- MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI1_SS0__SS0,
- MX31_PIN_CSPI1_SS1__SS1,
- MX31_PIN_CSPI1_SS2__SS2,
- /* UART2 */
- MX31_PIN_TXD2__TXD2,
- MX31_PIN_RXD2__RXD2,
- MX31_PIN_CTS2__CTS2,
- MX31_PIN_RTS2__RTS2,
- /* UART3 */
- MX31_PIN_CSPI3_MOSI__RXD3,
- MX31_PIN_CSPI3_MISO__TXD3,
- MX31_PIN_CSPI3_SCLK__RTS3,
- MX31_PIN_CSPI3_SPI_RDY__CTS3,
- /* LAN9217 irq pin */
- IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
- /* Onewire */
- MX31_PIN_BATT_LINE__OWIRE,
- /* Framebuffer */
- MX31_PIN_LD0__LD0,
- MX31_PIN_LD1__LD1,
- MX31_PIN_LD2__LD2,
- MX31_PIN_LD3__LD3,
- MX31_PIN_LD4__LD4,
- MX31_PIN_LD5__LD5,
- MX31_PIN_LD6__LD6,
- MX31_PIN_LD7__LD7,
- MX31_PIN_LD8__LD8,
- MX31_PIN_LD9__LD9,
- MX31_PIN_LD10__LD10,
- MX31_PIN_LD11__LD11,
- MX31_PIN_LD12__LD12,
- MX31_PIN_LD13__LD13,
- MX31_PIN_LD14__LD14,
- MX31_PIN_LD15__LD15,
- MX31_PIN_LD16__LD16,
- MX31_PIN_LD17__LD17,
- MX31_PIN_VSYNC3__VSYNC3,
- MX31_PIN_HSYNC__HSYNC,
- MX31_PIN_FPSHIFT__FPSHIFT,
- MX31_PIN_DRDY0__DRDY0,
- MX31_PIN_D3_REV__D3_REV,
- MX31_PIN_CONTRAST__CONTRAST,
- MX31_PIN_D3_SPL__D3_SPL,
- MX31_PIN_D3_CLS__D3_CLS,
- MX31_PIN_LCS0__GPIO3_23,
- /* GPIO */
- IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
- /* OTG */
- MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
- MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
- MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
- MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
- MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
- MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
- MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
- MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
- MX31_PIN_USBOTG_CLK__USBOTG_CLK,
- MX31_PIN_USBOTG_DIR__USBOTG_DIR,
- MX31_PIN_USBOTG_NXT__USBOTG_NXT,
- MX31_PIN_USBOTG_STP__USBOTG_STP,
- /* USB host 2 */
- IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
-};
-
-static struct physmap_flash_data pcm037_flash_data = {
- .width = 2,
-};
-
-static struct resource pcm037_flash_resource = {
- .start = 0xa0000000,
- .end = 0xa1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm037_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &pcm037_flash_data,
- },
- .resource = &pcm037_flash_resource,
- .num_resources = 1,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct resource smsc911x_resources[] = {
- {
- .start = MX31_CS1_BASE_ADDR + 0x300,
- .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- /* irq number is run-time assigned */
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_info = {
- .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
- SMSC911X_SAVE_MAC_ADDRESS,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device pcm037_eth = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_info,
- },
-};
-
-static struct platdata_mtd_ram pcm038_sram_data = {
- .bankwidth = 2,
-};
-
-static struct resource pcm038_sram_resource = {
- .start = MX31_CS4_BASE_ADDR,
- .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm037_sram_device = {
- .name = "mtd-ram",
- .id = 0,
- .dev = {
- .platform_data = &pcm038_sram_data,
- },
- .num_resources = 1,
- .resource = &pcm038_sram_resource,
-};
-
-static const struct mxc_nand_platform_data
-pcm037_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
- .bitrate = 100000,
-};
-
-static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
- .bitrate = 20000,
-};
-
-static const struct property_entry board_eeprom_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 32),
- { }
-};
-
-static struct i2c_board_info pcm037_i2c_devices[] = {
- {
- I2C_BOARD_INFO("24c32", 0x52), /* E0=0, E1=1, E2=0 */
- .properties = board_eeprom_properties,
- }, {
- I2C_BOARD_INFO("pcf8563", 0x51),
- }
-};
-
-/* Not connected by default */
-#ifdef PCM970_SDHC_RW_SWITCH
-static int pcm970_sdhc1_get_ro(struct device *dev)
-{
- return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
-}
-#endif
-
-#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
-#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
-
-static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
- if (ret)
- return ret;
-
- gpio_direction_input(SDHC1_GPIO_DET);
-
-#ifdef PCM970_SDHC_RW_SWITCH
- ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
- if (ret)
- goto err_gpio_free;
- gpio_direction_input(SDHC1_GPIO_WP);
-#endif
-
- ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
- IRQF_TRIGGER_FALLING, "sdhc-detect", data);
- if (ret)
- goto err_gpio_free_2;
-
- return 0;
-
-err_gpio_free_2:
-#ifdef PCM970_SDHC_RW_SWITCH
- gpio_free(SDHC1_GPIO_WP);
-err_gpio_free:
-#endif
- gpio_free(SDHC1_GPIO_DET);
-
- return ret;
-}
-
-static void pcm970_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
- gpio_free(SDHC1_GPIO_DET);
- gpio_free(SDHC1_GPIO_WP);
-}
-
-static const struct imxmmc_platform_data sdhc_pdata __initconst = {
-#ifdef PCM970_SDHC_RW_SWITCH
- .get_ro = pcm970_sdhc1_get_ro,
-#endif
- .init = pcm970_sdhc1_init,
- .exit = pcm970_sdhc1_exit,
-};
-
-static struct platform_device *devices[] __initdata = {
- &pcm037_flash,
- &pcm037_sram_device,
-};
-
-static const struct fb_videomode fb_modedb[] = {
- {
- /* 240x320 @ 60 Hz Sharp */
- .name = "Sharp-LQ035Q7DH06-QVGA",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 185925,
- .left_margin = 9,
- .right_margin = 16,
- .upper_margin = 7,
- .lower_margin = 9,
- .hsync_len = 1,
- .vsync_len = 1,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
- FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }, {
- /* 240x320 @ 60 Hz */
- .name = "TX090",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 38255,
- .left_margin = 144,
- .right_margin = 0,
- .upper_margin = 7,
- .lower_margin = 40,
- .hsync_len = 96,
- .vsync_len = 1,
- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }, {
- /* 240x320 @ 60 Hz */
- .name = "CMEL-OLED",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 185925,
- .left_margin = 9,
- .right_margin = 16,
- .upper_margin = 7,
- .lower_margin = 9,
- .hsync_len = 1,
- .vsync_len = 1,
- .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
-};
-
-static struct mx3fb_platform_data mx3fb_pdata = {
- .name = "Sharp-LQ035Q7DH06-QVGA",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-static struct resource pcm970_sja1000_resources[] = {
- {
- .start = MX31_CS5_BASE_ADDR,
- .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- /* irq number is run-time assigned */
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-struct sja1000_platform_data pcm970_sja1000_platform_data = {
- .osc_freq = 16000000,
- .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
- .cdr = CDR_CBP,
-};
-
-static struct platform_device pcm970_sja1000 = {
- .name = "sja1000_platform",
- .dev = {
- .platform_data = &pcm970_sja1000_platform_data,
- },
- .resource = pcm970_sja1000_resources,
- .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
-};
-
-static int pcm037_otg_init(struct platform_device *pdev)
-{
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
- .init = pcm037_otg_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static int pcm037_usbh2_init(struct platform_device *pdev)
-{
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = pcm037_usbh2_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-static bool otg_mode_host __initdata;
-
-static int __init pcm037_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = true;
- else if (!strcmp(options, "device"))
- otg_mode_host = false;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 1;
-}
-__setup("otg_mode=", pcm037_otg_mode);
-
-static struct regulator_consumer_supply dummy_supplies[] = {
- REGULATOR_SUPPLY("vdd33a", "smsc911x"),
- REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
-/*
- * Board specific initialization.
- */
-static void __init pcm037_init(void)
-{
- imx31_soc_init();
-
- regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
- mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
-
- mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
- "pcm037");
-
-#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
- | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
- mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
- mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
- mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
- mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
- mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
- mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
-
- if (pcm037_variant() == PCM037_EET)
- mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
- ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
- else
- mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
- ARRAY_SIZE(pcm037_uart1_handshake_pins),
- "pcm037_uart1");
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- imx31_add_imx2_wdt();
- imx31_add_imx_uart0(&uart_pdata);
- /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
- imx31_add_imx_uart1(&uart_pdata);
- imx31_add_imx_uart2(&uart_pdata);
-
- imx31_add_mxc_w1();
-
- /* I2C adapters and devices */
- i2c_register_board_info(1, pcm037_i2c_devices,
- ARRAY_SIZE(pcm037_i2c_devices));
-
- imx31_add_imx_i2c1(&pcm037_i2c1_data);
- imx31_add_imx_i2c2(&pcm037_i2c2_data);
-
- imx31_add_mxc_nand(&pcm037_nand_board_info);
- imx31_add_ipu_core();
- imx31_add_mx3_sdc_fb(&mx3fb_pdata);
-
- if (otg_mode_host) {
- otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (otg_pdata.otg)
- imx31_add_mxc_ehci_otg(&otg_pdata);
- }
-
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbh2_pdata.otg)
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-
- if (!otg_mode_host)
- imx31_add_fsl_usb2_udc(&otg_device_pdata);
-}
-
-static void __init pcm037_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-static void __init pcm037_init_late(void)
-{
- int ret;
-
- /* LAN9217 IRQ pin */
- ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
- if (!ret) {
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
- smsc911x_resources[1].start =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
- smsc911x_resources[1].end =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
- platform_device_register(&pcm037_eth);
- } else {
- pr_warn("could not get LAN irq gpio\n");
- }
-
- imx31_add_mxc_mmc(0, &sdhc_pdata);
-
- pcm970_sja1000_resources[1].start =
- gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
- pcm970_sja1000_resources[1].end =
- gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
- platform_device_register(&pcm970_sja1000);
-
- pcm037_eet_init_devices();
-}
-
-MACHINE_START(PCM037, "Phytec Phycore pcm037")
- /* Maintainer: Pengutronix */
- .atag_offset = 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .init_time = pcm037_timer_init,
- .init_machine = pcm037_init,
- .init_late = pcm037_init_late,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c
deleted file mode 100644
index 51f5142..0000000
--- a/arch/arm/mach-imx/mach-pcm037_eet.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2009
- * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
- */
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-
-#include <asm/mach-types.h>
-
-#include "pcm037.h"
-#include "common.h"
-#include "devices-imx31.h"
-#include "iomux-mx3.h"
-
-static unsigned int pcm037_eet_pins[] = {
- /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
- IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO),
- /* GPIO keys */
- IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), /* 0 */
- IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), /* 1 */
- IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO), /* 2 */
- IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), /* 3 */
- IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO), /* 32 */
- IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO), /* 33 */
- IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO), /* 34 */
- IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO), /* 35 */
- IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO), /* 38 */
- IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO), /* 39 */
- IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO), /* 50 */
- IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_GPIO), /* 51 */
- IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_GPIO), /* 52 */
- IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_GPIO), /* 53 */
-
- /* LEDs */
- IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_CONFIG_GPIO), /* 44 */
- IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_GPIO), /* 45 */
- IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_GPIO), /* 55 */
- IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_GPIO), /* 56 */
-};
-
-/* SPI */
-static struct spi_board_info pcm037_spi_dev[] = {
- {
- .modalias = "dac124s085",
- .max_speed_hz = 400000,
- .bus_num = 0,
- .chip_select = 1, /* Index in pcm037_spi1_cs[] */
- .mode = SPI_CPHA,
- },
-};
-
-/* Platform Data for MXC CSPI */
-static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
- .num_chipselect = 2,
-};
-
-/* GPIO-keys input device */
-static struct gpio_keys_button pcm037_gpio_keys[] = {
- {
- .type = EV_KEY,
- .code = KEY_L,
- .gpio = 0,
- .desc = "Wheel Manual",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_A,
- .gpio = 1,
- .desc = "Wheel AF",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_V,
- .gpio = 2,
- .desc = "Wheel View",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_M,
- .gpio = 3,
- .desc = "Wheel Menu",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_UP,
- .gpio = 32,
- .desc = "Nav Pad Up",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_RIGHT,
- .gpio = 33,
- .desc = "Nav Pad Right",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_DOWN,
- .gpio = 34,
- .desc = "Nav Pad Down",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_LEFT,
- .gpio = 35,
- .desc = "Nav Pad Left",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_ENTER,
- .gpio = 38,
- .desc = "Nav Pad Ok",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_O,
- .gpio = 39,
- .desc = "Wheel Off",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = BTN_FORWARD,
- .gpio = 50,
- .desc = "Focus Forward",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = BTN_BACK,
- .gpio = 51,
- .desc = "Focus Backward",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = BTN_MIDDLE,
- .gpio = 52,
- .desc = "Release Half",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = BTN_EXTRA,
- .gpio = 53,
- .desc = "Release Full",
- .wakeup = 0,
- },
-};
-
-static const struct gpio_keys_platform_data
- pcm037_gpio_keys_platform_data __initconst = {
- .buttons = pcm037_gpio_keys,
- .nbuttons = ARRAY_SIZE(pcm037_gpio_keys),
- .rep = 0, /* No auto-repeat */
-};
-
-int __init pcm037_eet_init_devices(void)
-{
- if (pcm037_variant() != PCM037_EET)
- return 0;
-
- mxc_iomux_setup_multiple_pins(pcm037_eet_pins,
- ARRAY_SIZE(pcm037_eet_pins), "pcm037_eet");
-
- /* SPI */
- spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
- imx31_add_spi_imx0(&pcm037_spi1_pdata);
-
- imx_add_gpio_keys(&pcm037_gpio_keys_platform_data);
-
- return 0;
-}
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
deleted file mode 100644
index 017a501..0000000
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ /dev/null
@@ -1,412 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2009 Sascha Hauer, Pengutronix
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/memory.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/smc911x.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/property.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices-imx35.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx35.h"
-#include "ulpi.h"
-
-static const struct fb_videomode fb_modedb[] = {
- {
- /* 240x320 @ 60 Hz */
- .name = "Sharp-LQ035Q7",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 185925,
- .left_margin = 9,
- .right_margin = 16,
- .upper_margin = 7,
- .lower_margin = 9,
- .hsync_len = 1,
- .vsync_len = 1,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }, {
- /* 240x320 @ 60 Hz */
- .name = "TX090",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 38255,
- .left_margin = 144,
- .right_margin = 0,
- .upper_margin = 7,
- .lower_margin = 40,
- .hsync_len = 96,
- .vsync_len = 1,
- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
-};
-
-static struct mx3fb_platform_data mx3fb_pdata __initdata = {
- .name = "Sharp-LQ035Q7",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-static struct physmap_flash_data pcm043_flash_data = {
- .width = 2,
-};
-
-static struct resource pcm043_flash_resource = {
- .start = 0xa0000000,
- .end = 0xa1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm043_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &pcm043_flash_data,
- },
- .resource = &pcm043_flash_resource,
- .num_resources = 1,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
- .bitrate = 50000,
-};
-
-static const struct property_entry board_eeprom_properties[] = {
- PROPERTY_ENTRY_U32("pagesize", 32),
- { }
-};
-
-static struct i2c_board_info pcm043_i2c_devices[] = {
- {
- I2C_BOARD_INFO("24c32", 0x52), /* E0=0, E1=1, E2=0 */
- .properties = board_eeprom_properties,
- }, {
- I2C_BOARD_INFO("pcf8563", 0x51),
- },
-};
-
-static struct platform_device *devices[] __initdata = {
- &pcm043_flash,
-};
-
-static const iomux_v3_cfg_t pcm043_pads[] __initconst = {
- /* UART1 */
- MX35_PAD_CTS1__UART1_CTS,
- MX35_PAD_RTS1__UART1_RTS,
- MX35_PAD_TXD1__UART1_TXD_MUX,
- MX35_PAD_RXD1__UART1_RXD_MUX,
- /* UART2 */
- MX35_PAD_CTS2__UART2_CTS,
- MX35_PAD_RTS2__UART2_RTS,
- MX35_PAD_TXD2__UART2_TXD_MUX,
- MX35_PAD_RXD2__UART2_RXD_MUX,
- /* FEC */
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
- MX35_PAD_FEC_RX_DV__FEC_RX_DV,
- MX35_PAD_FEC_COL__FEC_COL,
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
- MX35_PAD_FEC_TX_EN__FEC_TX_EN,
- MX35_PAD_FEC_MDC__FEC_MDC,
- MX35_PAD_FEC_MDIO__FEC_MDIO,
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
- MX35_PAD_FEC_CRS__FEC_CRS,
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
- /* I2C1 */
- MX35_PAD_I2C1_CLK__I2C1_SCL,
- MX35_PAD_I2C1_DAT__I2C1_SDA,
- /* Display */
- MX35_PAD_LD0__IPU_DISPB_DAT_0,
- MX35_PAD_LD1__IPU_DISPB_DAT_1,
- MX35_PAD_LD2__IPU_DISPB_DAT_2,
- MX35_PAD_LD3__IPU_DISPB_DAT_3,
- MX35_PAD_LD4__IPU_DISPB_DAT_4,
- MX35_PAD_LD5__IPU_DISPB_DAT_5,
- MX35_PAD_LD6__IPU_DISPB_DAT_6,
- MX35_PAD_LD7__IPU_DISPB_DAT_7,
- MX35_PAD_LD8__IPU_DISPB_DAT_8,
- MX35_PAD_LD9__IPU_DISPB_DAT_9,
- MX35_PAD_LD10__IPU_DISPB_DAT_10,
- MX35_PAD_LD11__IPU_DISPB_DAT_11,
- MX35_PAD_LD12__IPU_DISPB_DAT_12,
- MX35_PAD_LD13__IPU_DISPB_DAT_13,
- MX35_PAD_LD14__IPU_DISPB_DAT_14,
- MX35_PAD_LD15__IPU_DISPB_DAT_15,
- MX35_PAD_LD16__IPU_DISPB_DAT_16,
- MX35_PAD_LD17__IPU_DISPB_DAT_17,
- MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
- MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
- MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
- MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
- MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
- MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
- MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
- /* gpio */
- MX35_PAD_ATA_CS0__GPIO2_6,
- /* USB host */
- MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
- MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
- /* SSI */
- MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
- MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
- MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
- MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
- /* CAN2 */
- MX35_PAD_TX5_RX0__CAN2_TXCAN,
- MX35_PAD_TX4_RX1__CAN2_RXCAN,
- /* esdhc */
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
- MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
-};
-
-#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
-#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
-#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
-
-static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
-{
- iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
- iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
- int ret;
-
- ret = gpio_request(AC97_GPIO_TXFS, "SSI");
- if (ret) {
- printk("failed to get GPIO_TXFS: %d\n", ret);
- return;
- }
-
- mxc_iomux_v3_setup_pad(txfs_gpio);
-
- /* warm reset */
- gpio_direction_output(AC97_GPIO_TXFS, 1);
- udelay(2);
- gpio_set_value(AC97_GPIO_TXFS, 0);
-
- gpio_free(AC97_GPIO_TXFS);
- mxc_iomux_v3_setup_pad(txfs);
-}
-
-static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
-{
- iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
- iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
- iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
- iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
- iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
- int ret;
-
- ret = gpio_request(AC97_GPIO_TXFS, "SSI");
- if (ret)
- goto err1;
-
- ret = gpio_request(AC97_GPIO_TXD, "SSI");
- if (ret)
- goto err2;
-
- ret = gpio_request(AC97_GPIO_RESET, "SSI");
- if (ret)
- goto err3;
-
- mxc_iomux_v3_setup_pad(txfs_gpio);
- mxc_iomux_v3_setup_pad(txd_gpio);
- mxc_iomux_v3_setup_pad(reset_gpio);
-
- gpio_direction_output(AC97_GPIO_TXFS, 0);
- gpio_direction_output(AC97_GPIO_TXD, 0);
-
- /* cold reset */
- gpio_direction_output(AC97_GPIO_RESET, 0);
- udelay(10);
- gpio_direction_output(AC97_GPIO_RESET, 1);
-
- mxc_iomux_v3_setup_pad(txd);
- mxc_iomux_v3_setup_pad(txfs);
-
- gpio_free(AC97_GPIO_RESET);
-err3:
- gpio_free(AC97_GPIO_TXD);
-err2:
- gpio_free(AC97_GPIO_TXFS);
-err1:
- if (ret)
- printk("%s failed with %d\n", __func__, ret);
- mdelay(1);
-}
-
-static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
- .ac97_reset = pcm043_ac97_cold_reset,
- .ac97_warm_reset = pcm043_ac97_warm_reset,
- .flags = IMX_SSI_USE_AC97,
-};
-
-static const struct mxc_nand_platform_data
-pcm037_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static int pcm043_otg_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
- .init = pcm043_otg_init,
- .portsc = MXC_EHCI_MODE_UTMI,
-};
-
-static int pcm043_usbh1_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
- MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
-}
-
-static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
- .init = pcm043_usbh1_init,
- .portsc = MXC_EHCI_MODE_SERIAL,
-};
-
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_UTMI,
-};
-
-static bool otg_mode_host __initdata;
-
-static int __init pcm043_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = true;
- else if (!strcmp(options, "device"))
- otg_mode_host = false;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 1;
-}
-__setup("otg_mode=", pcm043_otg_mode);
-
-static struct esdhc_platform_data sd1_pdata = {
- .wp_type = ESDHC_WP_GPIO,
- .cd_type = ESDHC_CD_GPIO,
-};
-
-static struct gpiod_lookup_table sd1_gpio_table = {
- .dev_id = "sdhci-esdhc-imx35.0",
- .table = {
- /* Card detect: bank 2 offset 24 */
- GPIO_LOOKUP("imx35-gpio.2", 24, "cd", GPIO_ACTIVE_LOW),
- /* Write protect: bank 2 offset 23 */
- GPIO_LOOKUP("imx35-gpio.2", 23, "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-/*
- * Board specific initialization.
- */
-static void __init pcm043_init(void)
-{
- imx35_soc_init();
-
- mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
-
- imx35_add_fec(NULL);
- platform_add_devices(devices, ARRAY_SIZE(devices));
- imx35_add_imx2_wdt();
-
- imx35_add_imx_uart0(&uart_pdata);
- imx35_add_mxc_nand(&pcm037_nand_board_info);
-
- imx35_add_imx_uart1(&uart_pdata);
-
- i2c_register_board_info(0, pcm043_i2c_devices,
- ARRAY_SIZE(pcm043_i2c_devices));
-
- imx35_add_imx_i2c0(&pcm043_i2c0_data);
-
- imx35_add_ipu_core();
- imx35_add_mx3_sdc_fb(&mx3fb_pdata);
-
- if (otg_mode_host) {
- otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (otg_pdata.otg)
- imx35_add_mxc_ehci_otg(&otg_pdata);
- }
- imx35_add_mxc_ehci_hs(&usbh1_pdata);
-
- if (!otg_mode_host)
- imx35_add_fsl_usb2_udc(&otg_device_pdata);
-
- imx35_add_flexcan1();
-}
-
-static void __init pcm043_late_init(void)
-{
- imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
-
- gpiod_add_lookup_table(&sd1_gpio_table);
- imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
-}
-
-static void __init pcm043_timer_init(void)
-{
- mx35_clocks_init();
-}
-
-MACHINE_START(PCM043, "Phytec Phycore pcm043")
- /* Maintainer: Pengutronix */
- .atag_offset = 0x100,
- .map_io = mx35_map_io,
- .init_early = imx35_init_early,
- .init_irq = mx35_init_irq,
- .init_time = pcm043_timer_init,
- .init_machine = pcm043_init,
- .init_late = pcm043_late_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
deleted file mode 100644
index 5b362da..0000000
--- a/arch/arm/mach-imx/mach-qong.c
+++ /dev/null
@@ -1,262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/memory.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/platnand.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-
-#include "common.h"
-#include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-
-/* FPGA defines */
-#define QONG_FPGA_VERSION(major, minor, rev) \
- (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
-
-#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
-#define QONG_FPGA_PERIPH_SIZE (1 << 24)
-
-#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
-#define QONG_FPGA_CTRL_SIZE 0x10
-/* FPGA control registers */
-#define QONG_FPGA_CTRL_VERSION 0x00
-
-#define QONG_DNET_ID 1
-#define QONG_DNET_BASEADDR \
- (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
-#define QONG_DNET_SIZE 0x00001000
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static int uart_pins[] = {
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1
-};
-
-static inline void __init mxc_init_imx_uart(void)
-{
- mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
- "uart-0");
- imx31_add_imx_uart0(&uart_pdata);
-}
-
-static struct resource dnet_resources[] = {
- {
- .name = "dnet-memory",
- .start = QONG_DNET_BASEADDR,
- .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }, {
- /* irq number is run-time assigned */
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dnet_device = {
- .name = "dnet",
- .id = -1,
- .num_resources = ARRAY_SIZE(dnet_resources),
- .resource = dnet_resources,
-};
-
-static int __init qong_init_dnet(void)
-{
- int ret;
-
- dnet_resources[1].start =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
- dnet_resources[1].end =
- gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
- ret = platform_device_register(&dnet_device);
- return ret;
-}
-
-/* MTD NOR flash */
-
-static struct physmap_flash_data qong_flash_data = {
- .width = 2,
-};
-
-static struct resource qong_flash_resource = {
- .start = MX31_CS0_BASE_ADDR,
- .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device qong_nor_mtd_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &qong_flash_data,
- },
- .resource = &qong_flash_resource,
- .num_resources = 1,
-};
-
-static void qong_init_nor_mtd(void)
-{
- (void)platform_device_register(&qong_nor_mtd_device);
-}
-
-/*
- * Hardware specific access to control-lines
- */
-static void qong_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
- unsigned int ctrl)
-{
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, nand_chip->legacy.IO_ADDR_W + (1 << 24));
- else
- writeb(cmd, nand_chip->legacy.IO_ADDR_W + (1 << 23));
-}
-
-/*
- * Read the Device Ready pin.
- */
-static int qong_nand_device_ready(struct nand_chip *chip)
-{
- return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
-}
-
-static void qong_nand_select_chip(struct nand_chip *chip, int cs)
-{
- if (cs >= 0)
- gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
- else
- gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
-}
-
-static struct platform_nand_data qong_nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_delay = 20,
- .options = 0,
- },
- .ctrl = {
- .cmd_ctrl = qong_nand_cmd_ctrl,
- .dev_ready = qong_nand_device_ready,
- .select_chip = qong_nand_select_chip,
- }
-};
-
-static struct resource qong_nand_resource = {
- .start = MX31_CS3_BASE_ADDR,
- .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device qong_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .dev = {
- .platform_data = &qong_nand_data,
- },
- .num_resources = 1,
- .resource = &qong_nand_resource,
-};
-
-static void __init qong_init_nand_mtd(void)
-{
- /* init CS */
- imx_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3)));
- imx_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3)));
- imx_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3)));
-
- mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
-
- /* enable pin */
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
- if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
- gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
-
- /* ready/busy pin */
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
- if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
-
- /* write protect pin */
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
- if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
-
- platform_device_register(&qong_nand_device);
-}
-
-static void __init qong_init_fpga(void)
-{
- void __iomem *regs;
- u32 fpga_ver;
-
- regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
- if (!regs) {
- printk(KERN_ERR "%s: failed to map registers, aborting.\n",
- __func__);
- return;
- }
-
- fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
- iounmap(regs);
- printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
- (fpga_ver & 0xF000) >> 12,
- (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
- if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
- printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
- "devices won't be registered!\n");
- return;
- }
-
- /* register FPGA-based devices */
- qong_init_nand_mtd();
- qong_init_dnet();
-}
-
-/*
- * Board specific initialization.
- */
-static void __init qong_init(void)
-{
- imx31_soc_init();
-
- mxc_init_imx_uart();
- qong_init_nor_mtd();
- imx31_add_imx2_wdt();
-}
-
-static void __init qong_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
- /* Maintainer: DENX Software Engineering GmbH */
- .atag_offset = 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .init_time = qong_timer_init,
- .init_machine = qong_init,
- .init_late = qong_init_fpga,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index 9c929b0..208ff64 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -3,11 +3,57 @@
* Copyright 2012-2013 Freescale Semiconductor, Inc.
*/
+#include <linux/of_address.h>
#include <linux/of_platform.h>
+#include <linux/io.h>
+
#include <linux/irqchip.h>
#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>
+#include "common.h"
+#include "hardware.h"
+
+#define MSCM_CPxCOUNT 0x00c
+#define MSCM_CPxCFG1 0x014
+
+static void __init vf610_detect_cpu(void)
+{
+ struct device_node *np;
+ u32 cpxcount, cpxcfg1;
+ unsigned int cpu_type;
+ void __iomem *mscm;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,vf610-mscm-cpucfg");
+ if (WARN_ON(!np))
+ return;
+
+ mscm = of_iomap(np, 0);
+ of_node_put(np);
+
+ if (WARN_ON(!mscm))
+ return;
+
+ cpxcount = readl_relaxed(mscm + MSCM_CPxCOUNT);
+ cpxcfg1 = readl_relaxed(mscm + MSCM_CPxCFG1);
+
+ iounmap(mscm);
+
+ cpu_type = cpxcount ? MXC_CPU_VF600 : MXC_CPU_VF500;
+
+ if (cpxcfg1)
+ cpu_type |= MXC_CPU_VFx10;
+
+ mxc_set_cpu_type(cpu_type);
+}
+
+static void __init vf610_init_machine(void)
+{
+ vf610_detect_cpu();
+
+ of_platform_default_populate(NULL, NULL, NULL);
+}
+
static const char * const vf610_dt_compat[] __initconst = {
"fsl,vf500",
"fsl,vf510",
@@ -20,5 +66,6 @@
DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF5xx/VF6xx (Device Tree)")
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
+ .init_machine = vf610_init_machine,
.dt_compat = vf610_dt_compat,
MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
deleted file mode 100644
index fae5a41..0000000
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ /dev/null
@@ -1,306 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
- * Copyright 2010 Creative Product Design
- *
- * Derived from mx35 3stack.
- * Original author: Fabio Estevam <fabio.estevam@freescale.com>
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/memory.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <linux/i2c.h>
-#include <linux/mfd/mc13xxx.h>
-
-#include "common.h"
-#include "devices-imx35.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx35.h"
-
-#define GPIO_LCDPWR IMX_GPIO_NR(1, 2)
-#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
-
-#define GPIO_BUTTON1 IMX_GPIO_NR(1, 4)
-#define GPIO_BUTTON2 IMX_GPIO_NR(1, 5)
-#define GPIO_BUTTON3 IMX_GPIO_NR(1, 7)
-#define GPIO_BUTTON4 IMX_GPIO_NR(1, 8)
-#define GPIO_BUTTON5 IMX_GPIO_NR(1, 9)
-#define GPIO_BUTTON6 IMX_GPIO_NR(1, 10)
-#define GPIO_BUTTON7 IMX_GPIO_NR(1, 11)
-#define GPIO_BUTTON8 IMX_GPIO_NR(1, 12)
-
-static const struct fb_videomode fb_modedb[] = {
- {
- /* 800x480 @ 60 Hz */
- .name = "PT0708048",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = KHZ2PICOS(33260),
- .left_margin = 50,
- .right_margin = 156,
- .upper_margin = 10,
- .lower_margin = 10,
- .hsync_len = 1, /* note: DE only display */
- .vsync_len = 1, /* note: DE only display */
- .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }, {
- /* 800x480 @ 60 Hz */
- .name = "CTP-CLAA070LC0ACW",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = KHZ2PICOS(27000),
- .left_margin = 50,
- .right_margin = 50, /* whole line should have 900 clocks */
- .upper_margin = 10,
- .lower_margin = 10, /* whole frame should have 500 lines */
- .hsync_len = 1, /* note: DE only display */
- .vsync_len = 1, /* note: DE only display */
- .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }
-};
-
-static struct mx3fb_platform_data mx3fb_pdata __initdata = {
- .name = "PT0708048",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-static struct physmap_flash_data vpr200_flash_data = {
- .width = 2,
-};
-
-static struct resource vpr200_flash_resource = {
- .start = MX35_CS0_BASE_ADDR,
- .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device vpr200_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &vpr200_flash_data,
- },
- .resource = &vpr200_flash_resource,
- .num_resources = 1,
-};
-
-static const struct mxc_nand_platform_data
- vpr200_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
- .flash_bbt = 1,
-};
-
-#define VPR_KEY_DEBOUNCE 500
-static struct gpio_keys_button vpr200_gpio_keys_table[] = {
- {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE},
- {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE},
- {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE},
- {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE},
- {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE},
- {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE},
- {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE},
- {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
-};
-
-static const struct gpio_keys_platform_data
- vpr200_gpio_keys_data __initconst = {
- .buttons = vpr200_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
-};
-
-static struct mc13xxx_platform_data vpr200_pmic = {
- .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
-};
-
-static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = {
- .bitrate = 50000,
-};
-
-static struct i2c_board_info vpr200_i2c_devices[] = {
- {
- I2C_BOARD_INFO("24c02", 0x50), /* E0=0, E1=0, E2=0 */
- }, {
- I2C_BOARD_INFO("mc13892", 0x08),
- .platform_data = &vpr200_pmic,
- /* irq number is run-time assigned */
- }
-};
-
-static const iomux_v3_cfg_t vpr200_pads[] __initconst = {
- /* UART1 */
- MX35_PAD_TXD1__UART1_TXD_MUX,
- MX35_PAD_RXD1__UART1_RXD_MUX,
- /* UART3 */
- MX35_PAD_ATA_DATA10__UART3_RXD_MUX,
- MX35_PAD_ATA_DATA11__UART3_TXD_MUX,
- /* FEC */
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
- MX35_PAD_FEC_RX_DV__FEC_RX_DV,
- MX35_PAD_FEC_COL__FEC_COL,
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
- MX35_PAD_FEC_TX_EN__FEC_TX_EN,
- MX35_PAD_FEC_MDC__FEC_MDC,
- MX35_PAD_FEC_MDIO__FEC_MDIO,
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
- MX35_PAD_FEC_CRS__FEC_CRS,
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
- /* Display */
- MX35_PAD_LD0__IPU_DISPB_DAT_0,
- MX35_PAD_LD1__IPU_DISPB_DAT_1,
- MX35_PAD_LD2__IPU_DISPB_DAT_2,
- MX35_PAD_LD3__IPU_DISPB_DAT_3,
- MX35_PAD_LD4__IPU_DISPB_DAT_4,
- MX35_PAD_LD5__IPU_DISPB_DAT_5,
- MX35_PAD_LD6__IPU_DISPB_DAT_6,
- MX35_PAD_LD7__IPU_DISPB_DAT_7,
- MX35_PAD_LD8__IPU_DISPB_DAT_8,
- MX35_PAD_LD9__IPU_DISPB_DAT_9,
- MX35_PAD_LD10__IPU_DISPB_DAT_10,
- MX35_PAD_LD11__IPU_DISPB_DAT_11,
- MX35_PAD_LD12__IPU_DISPB_DAT_12,
- MX35_PAD_LD13__IPU_DISPB_DAT_13,
- MX35_PAD_LD14__IPU_DISPB_DAT_14,
- MX35_PAD_LD15__IPU_DISPB_DAT_15,
- MX35_PAD_LD16__IPU_DISPB_DAT_16,
- MX35_PAD_LD17__IPU_DISPB_DAT_17,
- MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
- MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
- MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
- /* LCD Enable */
- MX35_PAD_D3_VSYNC__GPIO1_2,
- /* USBOTG */
- MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
- MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
- /* SDCARD */
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- /* PMIC */
- MX35_PAD_GPIO2_0__GPIO2_0,
- /* GPIO keys */
- MX35_PAD_SCKR__GPIO1_4,
- MX35_PAD_COMPARE__GPIO1_5,
- MX35_PAD_SCKT__GPIO1_7,
- MX35_PAD_FST__GPIO1_8,
- MX35_PAD_HCKT__GPIO1_9,
- MX35_PAD_TX5_RX0__GPIO1_10,
- MX35_PAD_TX4_RX1__GPIO1_11,
- MX35_PAD_TX3_RX2__GPIO1_12,
-};
-
-/* USB Device config */
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_UTMI,
- .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
-};
-
-static int vpr200_usbh_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id,
- MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY);
-}
-
-/* USB HOST config */
-static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
- .init = vpr200_usbh_init,
- .portsc = MXC_EHCI_MODE_SERIAL,
-};
-
-static struct platform_device *devices[] __initdata = {
- &vpr200_flash,
-};
-
-/*
- * Board specific initialization.
- */
-static void __init vpr200_board_init(void)
-{
- imx35_soc_init();
-
- mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
-
- imx35_add_fec(NULL);
- imx35_add_imx2_wdt();
-
- imx35_add_imx_uart0(NULL);
- imx35_add_imx_uart2(NULL);
-
- imx35_add_ipu_core();
- imx35_add_mx3_sdc_fb(&mx3fb_pdata);
-
- imx35_add_fsl_usb2_udc(&otg_device_pdata);
- imx35_add_mxc_ehci_hs(&usb_host_pdata);
-
- imx35_add_mxc_nand(&vpr200_nand_board_info);
- imx35_add_sdhci_esdhc_imx(0, NULL);
-}
-
-static void __init vpr200_late_init(void)
-{
- imx_add_gpio_keys(&vpr200_gpio_keys_data);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR"))
- printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n");
- else
- gpio_direction_output(GPIO_LCDPWR, 0);
-
- if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT"))
- printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n");
- else
- gpio_direction_input(GPIO_PMIC_INT);
-
- vpr200_i2c_devices[1].irq = gpio_to_irq(GPIO_PMIC_INT);
- i2c_register_board_info(0, vpr200_i2c_devices,
- ARRAY_SIZE(vpr200_i2c_devices));
-
- imx35_add_imx_i2c0(&vpr200_i2c0_data);
-}
-
-static void __init vpr200_timer_init(void)
-{
- mx35_clocks_init();
-}
-
-MACHINE_START(VPR200, "VPR200")
- /* Maintainer: Creative Product Design */
- .map_io = mx35_map_io,
- .init_early = imx35_init_early,
- .init_irq = mx35_init_irq,
- .init_time = vpr200_timer_init,
- .init_machine = vpr200_board_init,
- .init_late = vpr200_late_init,
- .restart = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
deleted file mode 100644
index e117d28..0000000
--- a/arch/arm/mach-imx/mm-imx21.c
+++ /dev/null
@@ -1,86 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-imx/mm-imx21.c
- *
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/pinctrl/machine.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v1.h"
-
-/* MX21 memory map definition */
-static struct map_desc imx21_io_desc[] __initdata = {
- /*
- * this fixed mapping covers:
- * - AIPI1
- * - AIPI2
- * - AITC
- * - ROM Patch
- * - and some reserved space
- */
- imx_map_entry(MX21, AIPI, MT_DEVICE),
- /*
- * this fixed mapping covers:
- * - CSI
- * - ATA
- */
- imx_map_entry(MX21, SAHB1, MT_DEVICE),
- /*
- * this fixed mapping covers:
- * - EMI
- */
- imx_map_entry(MX21, X_MEMC, MT_DEVICE),
-};
-
-/*
- * Initialize the memory map. It is called during the
- * system startup to create static physical to virtual
- * memory map for the IO modules.
- */
-void __init mx21_map_io(void)
-{
- iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
-}
-
-void __init imx21_init_early(void)
-{
- mxc_set_cpu_type(MXC_CPU_MX21);
- imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
- MX21_NUM_GPIO_PORT);
-}
-
-void __init mx21_init_irq(void)
-{
- mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
-}
-
-static const struct resource imx21_audmux_res[] __initconst = {
- DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K),
-};
-
-void __init imx21_soc_init(void)
-{
- mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
- mxc_device_init();
-
- mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
-
- pinctrl_provide_dummies();
- imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR,
- MX21_INT_DMACH0, 0); /* No ERR irq */
- platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
- ARRAY_SIZE(imx21_audmux_res));
-}
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
deleted file mode 100644
index dcbe7ec..0000000
--- a/arch/arm/mach-imx/mm-imx27.c
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-imx/mm-imx27.c
- *
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/pinctrl/machine.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "devices/devices-common.h"
-#include "hardware.h"
-#include "iomux-v1.h"
-
-/* MX27 memory map definition */
-static struct map_desc imx27_io_desc[] __initdata = {
- /*
- * this fixed mapping covers:
- * - AIPI1
- * - AIPI2
- * - AITC
- * - ROM Patch
- * - and some reserved space
- */
- imx_map_entry(MX27, AIPI, MT_DEVICE),
- /*
- * this fixed mapping covers:
- * - CSI
- * - ATA
- */
- imx_map_entry(MX27, SAHB1, MT_DEVICE),
- /*
- * this fixed mapping covers:
- * - EMI
- */
- imx_map_entry(MX27, X_MEMC, MT_DEVICE),
-};
-
-/*
- * Initialize the memory map. It is called during the
- * system startup to create static physical to virtual
- * memory map for the IO modules.
- */
-void __init mx27_map_io(void)
-{
- iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
-}
-
-void __init imx27_init_early(void)
-{
- mxc_set_cpu_type(MXC_CPU_MX27);
- imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
- MX27_NUM_GPIO_PORT);
-}
-
-void __init mx27_init_irq(void)
-{
- mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
-}
-
-static const struct resource imx27_audmux_res[] __initconst = {
- DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K),
-};
-
-void __init imx27_soc_init(void)
-{
- mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
- mxc_device_init();
-
- /* i.mx27 has the i.mx21 type gpio */
- mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
- mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
-
- pinctrl_provide_dummies();
- imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR,
- MX27_INT_DMACH0, 0); /* No ERR irq */
- /* imx27 has the imx21 type audmux */
- platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
- ARRAY_SIZE(imx27_audmux_res));
-
- imx27_pm_init();
-}
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 67264c4..5056438 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -11,18 +11,16 @@
#include <linux/init.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/of_address.h>
#include <linux/pinctrl/machine.h>
-#include <asm/pgtable.h>
#include <asm/system_misc.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include "common.h"
#include "crmregs-imx3.h"
-#include "devices/devices-common.h"
#include "hardware.h"
-#include "iomux-v3.h"
void __iomem *mx3_ccm_base;
@@ -72,40 +70,6 @@
return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}
-static void __init imx3_init_l2x0(void)
-{
-#ifdef CONFIG_CACHE_L2X0
- void __iomem *l2x0_base;
- void __iomem *clkctl_base;
-
-/*
- * First of all, we must repair broken chip settings. There are some
- * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
- * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
- * Workaraound is to setup the correct register setting prior enabling the
- * L2 cache. This should not hurt already working CPUs, as they are using the
- * same value.
- */
-#define L2_MEM_VAL 0x10
-
- clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
- if (clkctl_base != NULL) {
- writel(0x00000515, clkctl_base + L2_MEM_VAL);
- iounmap(clkctl_base);
- } else {
- pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
- }
-
- l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
- if (!l2x0_base) {
- printk(KERN_ERR "remapping L2 cache area failed\n");
- return;
- }
-
- l2x0_init(l2x0_base, 0x00030024, 0x00000000);
-#endif
-}
-
#ifdef CONFIG_SOC_IMX31
static struct map_desc mx31_io_desc[] __initdata = {
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
@@ -136,70 +100,26 @@
void __init imx31_init_early(void)
{
+ struct device_node *np;
+
mxc_set_cpu_type(MXC_CPU_MX31);
arch_ioremap_caller = imx3_ioremap_caller;
arm_pm_idle = imx31_idle;
- mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
+ mx3_ccm_base = of_iomap(np, 0);
+ BUG_ON(!mx3_ccm_base);
}
void __init mx31_init_irq(void)
{
- mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
-}
+ void __iomem *avic_base;
+ struct device_node *np;
-static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
- .per_2_per_addr = 1677,
-};
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx31-avic");
+ avic_base = of_iomap(np, 0);
+ BUG_ON(!avic_base);
-static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
- .ap_2_ap_addr = 423,
- .ap_2_bp_addr = 829,
- .bp_2_ap_addr = 1029,
-};
-
-static struct sdma_platform_data imx31_sdma_pdata __initdata = {
- .fw_name = "sdma-imx31-to2.bin",
- .script_addrs = &imx31_to2_sdma_script,
-};
-
-static const struct resource imx31_audmux_res[] __initconst = {
- DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
-static const struct resource imx31_rnga_res[] __initconst = {
- DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
-};
-
-void __init imx31_soc_init(void)
-{
- int to_version = mx31_revision() >> 4;
-
- imx3_init_l2x0();
-
- mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
- mxc_device_init();
-
- mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
- mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
- mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
-
- pinctrl_provide_dummies();
-
- if (to_version == 1) {
- strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
- strlen(imx31_sdma_pdata.fw_name));
- imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
- }
-
- imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
-
- imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
- imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
-
- platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
- ARRAY_SIZE(imx31_audmux_res));
- platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res,
- ARRAY_SIZE(imx31_rnga_res));
+ mxc_init_irq(avic_base);
}
#endif /* ifdef CONFIG_SOC_IMX31 */
@@ -229,85 +149,25 @@
void __init imx35_init_early(void)
{
+ struct device_node *np;
+
mxc_set_cpu_type(MXC_CPU_MX35);
- mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
arm_pm_idle = imx35_idle;
arch_ioremap_caller = imx3_ioremap_caller;
- mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx35-ccm");
+ mx3_ccm_base = of_iomap(np, 0);
+ BUG_ON(!mx3_ccm_base);
}
void __init mx35_init_irq(void)
{
- mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
-}
+ void __iomem *avic_base;
+ struct device_node *np;
-static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
- .ap_2_ap_addr = 642,
- .uart_2_mcu_addr = 817,
- .mcu_2_app_addr = 747,
- .uartsh_2_mcu_addr = 1183,
- .per_2_shp_addr = 1033,
- .mcu_2_shp_addr = 961,
- .ata_2_mcu_addr = 1333,
- .mcu_2_ata_addr = 1252,
- .app_2_mcu_addr = 683,
- .shp_2_per_addr = 1111,
- .shp_2_mcu_addr = 892,
-};
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx35-avic");
+ avic_base = of_iomap(np, 0);
+ BUG_ON(!avic_base);
-static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
- .ap_2_ap_addr = 729,
- .uart_2_mcu_addr = 904,
- .per_2_app_addr = 1597,
- .mcu_2_app_addr = 834,
- .uartsh_2_mcu_addr = 1270,
- .per_2_shp_addr = 1120,
- .mcu_2_shp_addr = 1048,
- .ata_2_mcu_addr = 1429,
- .mcu_2_ata_addr = 1339,
- .app_2_per_addr = 1531,
- .app_2_mcu_addr = 770,
- .shp_2_per_addr = 1198,
- .shp_2_mcu_addr = 979,
-};
-
-static struct sdma_platform_data imx35_sdma_pdata __initdata = {
- .fw_name = "sdma-imx35-to2.bin",
- .script_addrs = &imx35_to2_sdma_script,
-};
-
-static const struct resource imx35_audmux_res[] __initconst = {
- DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
-void __init imx35_soc_init(void)
-{
- int to_version = mx35_revision() >> 4;
-
- imx3_init_l2x0();
-
- mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
- mxc_device_init();
-
- mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
- mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
- mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
-
- pinctrl_provide_dummies();
- if (to_version == 1) {
- strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
- strlen(imx35_sdma_pdata.fw_name));
- imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
- }
-
- imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
-
- /* Setup AIPS registers */
- imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
- imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
-
- /* i.mx35 has the i.mx31 type audmux */
- platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
- ARRAY_SIZE(imx35_audmux_res));
+ mxc_init_irq(avic_base);
}
#endif /* ifdef CONFIG_SOC_IMX35 */
diff --git a/arch/arm/mach-imx/mx21.h b/arch/arm/mach-imx/mx21.h
deleted file mode 100644
index 38be12a..0000000
--- a/arch/arm/mach-imx/mx21.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
- *
- * This contains i.MX21-specific hardware definitions. For those
- * hardware pieces that are common between i.MX21 and i.MX27, have a
- * look at mx2x.h.
- */
-
-#ifndef __MACH_MX21_H__
-#define __MACH_MX21_H__
-
-#define MX21_AIPI_BASE_ADDR 0x10000000
-#define MX21_AIPI_SIZE SZ_1M
-#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
-#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
-#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
-#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
-#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
-#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
-#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
-#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
-#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
-#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
-#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
-#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
-#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
-#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
-#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
-#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
-#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
-#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
-#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
-#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
-#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
-#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000)
-#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100)
-#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200)
-#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300)
-#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400)
-#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500)
-#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
-#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
-#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
-#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
-#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
-#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
-#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
-#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
-#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
-#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
-#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX21_AVIC_BASE_ADDR 0x10040000
-
-#define MX21_SAHB1_BASE_ADDR 0x80000000
-#define MX21_SAHB1_SIZE SZ_1M
-#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
-
-/* Memory regions and CS */
-#define MX21_SDRAM_BASE_ADDR 0xc0000000
-#define MX21_CSD1_BASE_ADDR 0xc4000000
-
-#define MX21_CS0_BASE_ADDR 0xc8000000
-#define MX21_CS1_BASE_ADDR 0xcc000000
-#define MX21_CS2_BASE_ADDR 0xd0000000
-#define MX21_CS3_BASE_ADDR 0xd1000000
-#define MX21_CS4_BASE_ADDR 0xd2000000
-#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
-#define MX21_CS5_BASE_ADDR 0xdd000000
-
-/* NAND, SDRAM, WEIM etc controllers */
-#define MX21_X_MEMC_BASE_ADDR 0xdf000000
-#define MX21_X_MEMC_SIZE SZ_256K
-
-#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
-#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
-#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
-#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
-
-#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
-
-#define MX21_IO_P2V(x) IMX_IO_P2V(x)
-#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
-
-/* fixed interrupt numbers */
-#include <asm/irq.h>
-#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)
-#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)
-#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)
-#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)
-#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)
-#define MX21_INT_I2C (NR_IRQS_LEGACY + 12)
-#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)
-#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)
-#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)
-#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)
-#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17)
-#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19)
-#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20)
-#define MX21_INT_KPP (NR_IRQS_LEGACY + 21)
-#define MX21_INT_RTC (NR_IRQS_LEGACY + 22)
-#define MX21_INT_PWM (NR_IRQS_LEGACY + 23)
-#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24)
-#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25)
-#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
-#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27)
-#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28)
-#define MX21_INT_NFC (NR_IRQS_LEGACY + 29)
-#define MX21_INT_BMI (NR_IRQS_LEGACY + 30)
-#define MX21_INT_CSI (NR_IRQS_LEGACY + 31)
-#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32)
-#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33)
-#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34)
-#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35)
-#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36)
-#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37)
-#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38)
-#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39)
-#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40)
-#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41)
-#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42)
-#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43)
-#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44)
-#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45)
-#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46)
-#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47)
-#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49)
-#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50)
-#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
-#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52)
-#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53)
-#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54)
-#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55)
-#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56)
-#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57)
-#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58)
-#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60)
-#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61)
-
-/* fixed DMA request numbers */
-#define MX21_DMA_REQ_CSPI3_RX 1
-#define MX21_DMA_REQ_CSPI3_TX 2
-#define MX21_DMA_REQ_EXT 3
-#define MX21_DMA_REQ_FIRI_RX 4
-#define MX21_DMA_REQ_SDHC2 6
-#define MX21_DMA_REQ_SDHC1 7
-#define MX21_DMA_REQ_SSI2_RX0 8
-#define MX21_DMA_REQ_SSI2_TX0 9
-#define MX21_DMA_REQ_SSI2_RX1 10
-#define MX21_DMA_REQ_SSI2_TX1 11
-#define MX21_DMA_REQ_SSI1_RX0 12
-#define MX21_DMA_REQ_SSI1_TX0 13
-#define MX21_DMA_REQ_SSI1_RX1 14
-#define MX21_DMA_REQ_SSI1_TX1 15
-#define MX21_DMA_REQ_CSPI2_RX 16
-#define MX21_DMA_REQ_CSPI2_TX 17
-#define MX21_DMA_REQ_CSPI1_RX 18
-#define MX21_DMA_REQ_CSPI1_TX 19
-#define MX21_DMA_REQ_UART4_RX 20
-#define MX21_DMA_REQ_UART4_TX 21
-#define MX21_DMA_REQ_UART3_RX 22
-#define MX21_DMA_REQ_UART3_TX 23
-#define MX21_DMA_REQ_UART2_RX 24
-#define MX21_DMA_REQ_UART2_TX 25
-#define MX21_DMA_REQ_UART1_RX 26
-#define MX21_DMA_REQ_UART1_TX 27
-#define MX21_DMA_REQ_BMI_TX 28
-#define MX21_DMA_REQ_BMI_RX 29
-#define MX21_DMA_REQ_CSI_STAT 30
-#define MX21_DMA_REQ_CSI_RX 31
-
-#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/mach-imx/mx27.h b/arch/arm/mach-imx/mx27.h
index c6f7aae..241c04d 100644
--- a/arch/arm/mach-imx/mx27.h
+++ b/arch/arm/mach-imx/mx27.h
@@ -13,209 +13,13 @@
#define MX27_AIPI_BASE_ADDR 0x10000000
#define MX27_AIPI_SIZE SZ_1M
-#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
-#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
-#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
-#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
-#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
-#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
-#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
-#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
-#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
-#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
-#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
-#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
-#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
-#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
-#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
-#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
-#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
-#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
-#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
-#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
-#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
-#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
-#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
-#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
-#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
-#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
-#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
-#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
-#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
-#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
-#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
-#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
-#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
-#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
-#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
-#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
-#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
-#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
-#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
-#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
-#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
-#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
-#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
-#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
-#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
-#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
-#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
-#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
-#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
-#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
-#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
-#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
-#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
-#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
-#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
-#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
-#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
-
-#define MX27_AVIC_BASE_ADDR 0x10040000
-
-/* ROM patch */
-#define MX27_ROMP_BASE_ADDR 0x10041000
#define MX27_SAHB1_BASE_ADDR 0x80000000
#define MX27_SAHB1_SIZE SZ_1M
-#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
-#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
-/* Memory regions and CS */
-#define MX27_SDRAM_BASE_ADDR 0xa0000000
-#define MX27_CSD1_BASE_ADDR 0xb0000000
-
-#define MX27_CS0_BASE_ADDR 0xc0000000
-#define MX27_CS1_BASE_ADDR 0xc8000000
-#define MX27_CS2_BASE_ADDR 0xd0000000
-#define MX27_CS3_BASE_ADDR 0xd2000000
-#define MX27_CS4_BASE_ADDR 0xd4000000
-#define MX27_CS5_BASE_ADDR 0xd6000000
-
-/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
#define MX27_X_MEMC_BASE_ADDR 0xd8000000
#define MX27_X_MEMC_SIZE SZ_1M
-#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
-#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
-#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
-#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
-#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
-
-#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
-#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
-#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
-#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
-
-#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
-
-/* IRAM */
-#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
#define MX27_IO_P2V(x) IMX_IO_P2V(x)
-#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
-
-/* fixed interrupt numbers */
-#include <asm/irq.h>
-#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
-#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
-#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
-#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
-#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
-#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
-#define MX27_INT_MSHC (NR_IRQS_LEGACY + 7)
-#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
-#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
-#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
-#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
-#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
-#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
-#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
-#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
-#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
-#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
-#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
-#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
-#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
-#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
-#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
-#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
-#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
-#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
-#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
-#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
-#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
-#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
-#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
-#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
-#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
-#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
-#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
-#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
-#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
-#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
-#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
-#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
-#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
-#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
-#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
-#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
-#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
-#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
-#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
-#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
-#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
-#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
-#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
-#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
-#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
-#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
-#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
-#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
-#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
-#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
-#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
-#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
-#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
-#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
-#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
-
-/* fixed DMA request numbers */
-#define MX27_DMA_REQ_CSPI3_RX 1
-#define MX27_DMA_REQ_CSPI3_TX 2
-#define MX27_DMA_REQ_EXT 3
-#define MX27_DMA_REQ_MSHC 4
-#define MX27_DMA_REQ_SDHC2 6
-#define MX27_DMA_REQ_SDHC1 7
-#define MX27_DMA_REQ_SSI2_RX0 8
-#define MX27_DMA_REQ_SSI2_TX0 9
-#define MX27_DMA_REQ_SSI2_RX1 10
-#define MX27_DMA_REQ_SSI2_TX1 11
-#define MX27_DMA_REQ_SSI1_RX0 12
-#define MX27_DMA_REQ_SSI1_TX0 13
-#define MX27_DMA_REQ_SSI1_RX1 14
-#define MX27_DMA_REQ_SSI1_TX1 15
-#define MX27_DMA_REQ_CSPI2_RX 16
-#define MX27_DMA_REQ_CSPI2_TX 17
-#define MX27_DMA_REQ_CSPI1_RX 18
-#define MX27_DMA_REQ_CSPI1_TX 19
-#define MX27_DMA_REQ_UART4_RX 20
-#define MX27_DMA_REQ_UART4_TX 21
-#define MX27_DMA_REQ_UART3_RX 22
-#define MX27_DMA_REQ_UART3_TX 23
-#define MX27_DMA_REQ_UART2_RX 24
-#define MX27_DMA_REQ_UART2_TX 25
-#define MX27_DMA_REQ_UART1_RX 26
-#define MX27_DMA_REQ_UART1_TX 27
-#define MX27_DMA_REQ_ATA_TX 28
-#define MX27_DMA_REQ_ATA_RCV 29
-#define MX27_DMA_REQ_CSI_STAT 30
-#define MX27_DMA_REQ_CSI_RX 31
-#define MX27_DMA_REQ_UART5_TX 32
-#define MX27_DMA_REQ_UART5_RX 33
-#define MX27_DMA_REQ_UART6_TX 34
-#define MX27_DMA_REQ_UART6_RX 35
-#define MX27_DMA_REQ_SDHC3 36
-#define MX27_DMA_REQ_NFC 37
#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/mach-imx/mx31.h b/arch/arm/mach-imx/mx31.h
index d957467..08a72e2 100644
--- a/arch/arm/mach-imx/mx31.h
+++ b/arch/arm/mach-imx/mx31.h
@@ -2,196 +2,17 @@
#ifndef __MACH_MX31_H__
#define __MACH_MX31_H__
-/*
- * IRAM
- */
-#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
-#define MX31_IRAM_SIZE SZ_16K
-
-#define MX31_L2CC_BASE_ADDR 0x30000000
-#define MX31_L2CC_SIZE SZ_1M
-
#define MX31_AIPS1_BASE_ADDR 0x43f00000
#define MX31_AIPS1_SIZE SZ_1M
-#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
-#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
-#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
-#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
-#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
-#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
-#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
-#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
-#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
-#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
-#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
-#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
-#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
-#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
-#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
-#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
-#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
-#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
-#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
-#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
-#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
-#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
-#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
-#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
-#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
-
#define MX31_SPBA0_BASE_ADDR 0x50000000
#define MX31_SPBA0_SIZE SZ_1M
-#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
-#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
-#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
-#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
-#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
-#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
-#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
-#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
-#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
-#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
-
#define MX31_AIPS2_BASE_ADDR 0x53f00000
#define MX31_AIPS2_SIZE SZ_1M
-#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
-#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
-#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
-#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
-#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
-#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
-#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
-#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
-#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
-#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
-#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
-#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
-#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
-#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
-#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
-#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
-#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
-#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
-#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
-#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
-#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
-
-#define MX31_ROMP_BASE_ADDR 0x60000000
-#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000)
-#define MX31_ROMP_SIZE SZ_1M
-
#define MX31_AVIC_BASE_ADDR 0x68000000
#define MX31_AVIC_SIZE SZ_1M
-
-#define MX31_IPU_MEM_BASE_ADDR 0x70000000
-#define MX31_CSD0_BASE_ADDR 0x80000000
-#define MX31_CSD1_BASE_ADDR 0x90000000
-
-#define MX31_CS0_BASE_ADDR 0xa0000000
-#define MX31_CS1_BASE_ADDR 0xa8000000
-#define MX31_CS2_BASE_ADDR 0xb0000000
-#define MX31_CS3_BASE_ADDR 0xb2000000
-
-#define MX31_CS4_BASE_ADDR 0xb4000000
-#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000)
-#define MX31_CS4_SIZE SZ_32M
-
-#define MX31_CS5_BASE_ADDR 0xb6000000
-#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000)
-#define MX31_CS5_SIZE SZ_32M
-
#define MX31_X_MEMC_BASE_ADDR 0xb8000000
#define MX31_X_MEMC_SIZE SZ_64K
-#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
-#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
-#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
-#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
-#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
-#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
-
-#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
-#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
-#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
-#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
-
-#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
#define MX31_IO_P2V(x) IMX_IO_P2V(x)
-#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)
-#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)
-#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)
-#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)
-#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)
-#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)
-#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)
-#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)
-#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)
-#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)
-#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13)
-#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14)
-#define MX31_INT_ATA (NR_IRQS_LEGACY + 15)
-#define MX31_INT_MBX (NR_IRQS_LEGACY + 16)
-#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17)
-#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX31_INT_IIM (NR_IRQS_LEGACY + 19)
-#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20)
-#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21)
-#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22)
-#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23)
-#define MX31_INT_KPP (NR_IRQS_LEGACY + 24)
-#define MX31_INT_RTC (NR_IRQS_LEGACY + 25)
-#define MX31_INT_PWM (NR_IRQS_LEGACY + 26)
-#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27)
-#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28)
-#define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
-#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
-#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31)
-#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX31_INT_NFC (NR_IRQS_LEGACY + 33)
-#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34)
-#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35)
-#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36)
-#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37)
-#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39)
-#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40)
-#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
-#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
-#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45)
-#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46)
-#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47)
-#define MX31_INT_ECT (NR_IRQS_LEGACY + 48)
-#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
-#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
-#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51)
-#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52)
-#define MX31_INT_CCM (NR_IRQS_LEGACY + 53)
-#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54)
-#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55)
-#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56)
-#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
-#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
-#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
-#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
-#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
-#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63)
-
-#define MX31_DMA_REQ_SDHC1 20
-#define MX31_DMA_REQ_SDHC2 21
-#define MX31_DMA_REQ_SSI2_RX1 22
-#define MX31_DMA_REQ_SSI2_TX1 23
-#define MX31_DMA_REQ_SSI2_RX0 24
-#define MX31_DMA_REQ_SSI2_TX0 25
-#define MX31_DMA_REQ_SSI1_RX1 26
-#define MX31_DMA_REQ_SSI1_TX1 27
-#define MX31_DMA_REQ_SSI1_RX0 28
-#define MX31_DMA_REQ_SSI1_TX0 29
-
-#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
deleted file mode 100644
index 00a5ee3..0000000
--- a/arch/arm/mach-imx/mx31lilly-db.c
+++ /dev/null
@@ -1,182 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * LILLY-1131 development board support
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * based on code for other MX31 boards,
- *
- * Copyright 2005-2007 Freescale Semiconductor
- * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "board-mx31lilly.h"
-#include "common.h"
-#include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-
-/*
- * This file contains board-specific initialization routines for the
- * LILLY-1131 development board. If you design an own baseboard for the
- * module, use this file as base for support code.
- */
-
-static unsigned int lilly_db_board_pins[] __initdata = {
- MX31_PIN_SD1_DATA3__SD1_DATA3,
- MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA1__SD1_DATA1,
- MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_CLK__SD1_CLK,
- MX31_PIN_SD1_CMD__SD1_CMD,
- MX31_PIN_LD0__LD0,
- MX31_PIN_LD1__LD1,
- MX31_PIN_LD2__LD2,
- MX31_PIN_LD3__LD3,
- MX31_PIN_LD4__LD4,
- MX31_PIN_LD5__LD5,
- MX31_PIN_LD6__LD6,
- MX31_PIN_LD7__LD7,
- MX31_PIN_LD8__LD8,
- MX31_PIN_LD9__LD9,
- MX31_PIN_LD10__LD10,
- MX31_PIN_LD11__LD11,
- MX31_PIN_LD12__LD12,
- MX31_PIN_LD13__LD13,
- MX31_PIN_LD14__LD14,
- MX31_PIN_LD15__LD15,
- MX31_PIN_LD16__LD16,
- MX31_PIN_LD17__LD17,
- MX31_PIN_VSYNC3__VSYNC3,
- MX31_PIN_HSYNC__HSYNC,
- MX31_PIN_FPSHIFT__FPSHIFT,
- MX31_PIN_DRDY0__DRDY0,
- MX31_PIN_CONTRAST__CONTRAST,
-};
-
-/* MMC support */
-
-static int mxc_mmc1_get_ro(struct device *dev)
-{
- return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0));
-}
-
-static int gpio_det, gpio_wp;
-
-#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int mxc_mmc1_init(struct device *dev,
- irq_handler_t detect_irq, void *data)
-{
- int ret;
-
- gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
- gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
-
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
-
- ret = gpio_request(gpio_det, "MMC detect");
- if (ret)
- return ret;
-
- ret = gpio_request(gpio_wp, "MMC w/p");
- if (ret)
- goto exit_free_det;
-
- gpio_direction_input(gpio_det);
- gpio_direction_input(gpio_wp);
-
- ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)),
- detect_irq, IRQF_TRIGGER_FALLING,
- "MMC detect", data);
- if (ret)
- goto exit_free_wp;
-
- return 0;
-
-exit_free_wp:
- gpio_free(gpio_wp);
-
-exit_free_det:
- gpio_free(gpio_det);
-
- return ret;
-}
-
-static void mxc_mmc1_exit(struct device *dev, void *data)
-{
- gpio_free(gpio_det);
- gpio_free(gpio_wp);
- free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), data);
-}
-
-static const struct imxmmc_platform_data mmc_pdata __initconst = {
- .get_ro = mxc_mmc1_get_ro,
- .init = mxc_mmc1_init,
- .exit = mxc_mmc1_exit,
-};
-
-/* Framebuffer support */
-static const struct fb_videomode fb_modedb = {
- /* 640x480 TFT panel (IPS-056T) */
- .name = "CRT-VGA",
- .refresh = 64,
- .xres = 640,
- .yres = 480,
- .pixclock = 30000,
- .left_margin = 200,
- .right_margin = 2,
- .upper_margin = 2,
- .lower_margin = 2,
- .hsync_len = 3,
- .vsync_len = 1,
- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
-};
-
-static struct mx3fb_platform_data fb_pdata __initdata = {
- .name = "CRT-VGA",
- .mode = &fb_modedb,
- .num_modes = 1,
-};
-
-#define LCD_VCC_EN_GPIO (7)
-
-static void __init mx31lilly_init_fb(void)
-{
- if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) {
- printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n");
- return;
- }
-
- imx31_add_ipu_core();
- imx31_add_mx3_sdc_fb(&fb_pdata);
- gpio_direction_output(LCD_VCC_EN_GPIO, 1);
-}
-
-void __init mx31lilly_db_init(void)
-{
- mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
- ARRAY_SIZE(lilly_db_board_pins),
- "development board pins");
- imx31_add_mxc_mmc(0, &mmc_pdata);
- mx31lilly_init_fb();
-}
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
deleted file mode 100644
index 13da732..0000000
--- a/arch/arm/mach-imx/mx31lite-db.c
+++ /dev/null
@@ -1,154 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * LogicPD i.MX31 SOM-LV development board support
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * based on code for other MX31 boards,
- *
- * Copyright 2005-2007 Freescale Semiconductor
- * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "board-mx31lite.h"
-#include "common.h"
-#include "devices-imx31.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-
-/*
- * This file contains board-specific initialization routines for the
- * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'.
- * If you design an own baseboard for the module, use this file as base
- * for support code.
- */
-
-static unsigned int litekit_db_board_pins[] __initdata = {
- /* SDHC1 */
- MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_DATA1__SD1_DATA1,
- MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA3__SD1_DATA3,
- MX31_PIN_SD1_CLK__SD1_CLK,
- MX31_PIN_SD1_CMD__SD1_CMD,
-};
-
-/* MMC */
-
-static int gpio_det, gpio_wp;
-
-#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS)
-
-static int mxc_mmc1_get_ro(struct device *dev)
-{
- return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6));
-}
-
-static int mxc_mmc1_init(struct device *dev,
- irq_handler_t detect_irq, void *data)
-{
- int ret;
-
- gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
- gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
-
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
- MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
- MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
- MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
- MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
- MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
-
- ret = gpio_request(gpio_det, "MMC detect");
- if (ret)
- return ret;
-
- ret = gpio_request(gpio_wp, "MMC w/p");
- if (ret)
- goto exit_free_det;
-
- gpio_direction_input(gpio_det);
- gpio_direction_input(gpio_wp);
-
- ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)),
- detect_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "MMC detect", data);
- if (ret)
- goto exit_free_wp;
-
- return 0;
-
-exit_free_wp:
- gpio_free(gpio_wp);
-
-exit_free_det:
- gpio_free(gpio_det);
-
- return ret;
-}
-
-static void mxc_mmc1_exit(struct device *dev, void *data)
-{
- gpio_free(gpio_det);
- gpio_free(gpio_wp);
- free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), data);
-}
-
-static const struct imxmmc_platform_data mmc_pdata __initconst = {
- .get_ro = mxc_mmc1_get_ro,
- .init = mxc_mmc1_init,
- .exit = mxc_mmc1_exit,
-};
-
-/* GPIO LEDs */
-
-static const struct gpio_led litekit_leds[] __initconst = {
- {
- .name = "GPIO0",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE),
- .active_low = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
- {
- .name = "GPIO1",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE),
- .active_low = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- }
-};
-
-static const struct gpio_led_platform_data
- litekit_led_platform_data __initconst = {
- .leds = litekit_leds,
- .num_leds = ARRAY_SIZE(litekit_leds),
-};
-
-void __init mx31lite_db_init(void)
-{
- mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
- ARRAY_SIZE(litekit_db_board_pins),
- "development board pins");
- imx31_add_mxc_mmc(0, &mmc_pdata);
- gpio_led_register_device(-1, &litekit_led_platform_data);
- imx31_add_imx2_wdt();
- imx31_add_mxc_rtc();
-}
diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
deleted file mode 100644
index 6a9db06..0000000
--- a/arch/arm/mach-imx/mx31moboard-devboard.c
+++ /dev/null
@@ -1,238 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-
-#include <linux/usb/otg.h>
-
-#include "board-mx31moboard.h"
-#include "common.h"
-#include "devices-imx31.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
-
-static unsigned int devboard_pins[] = {
- /* UART1 */
- MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
- MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
- /* SDHC2 */
- MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
- MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
- MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
- MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
- /* USB H1 */
- MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
- MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
- MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
- MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
- MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
- /* SEL */
- MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
- MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
-#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
-
-static int devboard_sdhc2_get_ro(struct device *dev)
-{
- return !gpio_get_value(SDHC2_WP);
-}
-
-static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request(SDHC2_CD, "sdhc-detect");
- if (ret)
- return ret;
-
- gpio_direction_input(SDHC2_CD);
-
- ret = gpio_request(SDHC2_WP, "sdhc-wp");
- if (ret)
- goto err_gpio_free;
- gpio_direction_input(SDHC2_WP);
-
- ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "sdhc2-card-detect", data);
- if (ret)
- goto err_gpio_free_2;
-
- return 0;
-
-err_gpio_free_2:
- gpio_free(SDHC2_WP);
-err_gpio_free:
- gpio_free(SDHC2_CD);
-
- return ret;
-}
-
-static void devboard_sdhc2_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(SDHC2_CD), data);
- gpio_free(SDHC2_WP);
- gpio_free(SDHC2_CD);
-}
-
-static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
- .get_ro = devboard_sdhc2_get_ro,
- .init = devboard_sdhc2_init,
- .exit = devboard_sdhc2_exit,
-};
-
-#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
-#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
-#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
-#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
-
-static void devboard_init_sel_gpios(void)
-{
- if (!gpio_request(SEL0, "sel0")) {
- gpio_direction_input(SEL0);
- gpio_export(SEL0, true);
- }
-
- if (!gpio_request(SEL1, "sel1")) {
- gpio_direction_input(SEL1);
- gpio_export(SEL1, true);
- }
-
- if (!gpio_request(SEL2, "sel2")) {
- gpio_direction_input(SEL2);
- gpio_export(SEL2, true);
- }
-
- if (!gpio_request(SEL3, "sel3")) {
- gpio_direction_input(SEL3);
- gpio_export(SEL3, true);
- }
-}
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int devboard_usbh1_hw_init(struct platform_device *pdev)
-{
- mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
-
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
- MXC_EHCI_INTERFACE_SINGLE_UNI);
-}
-
-#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
-#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
-
-static int devboard_isp1105_init(struct usb_phy *otg)
-{
- int ret = gpio_request(USBH1_MODE, "usbh1-mode");
- if (ret)
- return ret;
- /* single ended */
- gpio_direction_output(USBH1_MODE, 0);
-
- ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
- if (ret) {
- gpio_free(USBH1_MODE);
- return ret;
- }
- gpio_direction_output(USBH1_VBUSEN_B, 1);
-
- return 0;
-}
-
-
-static int devboard_isp1105_set_vbus(struct usb_otg *otg, bool on)
-{
- if (on)
- gpio_set_value(USBH1_VBUSEN_B, 0);
- else
- gpio_set_value(USBH1_VBUSEN_B, 1);
-
- return 0;
-}
-
-static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
- .init = devboard_usbh1_hw_init,
- .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-};
-
-static int __init devboard_usbh1_init(void)
-{
- struct usb_phy *phy;
- struct platform_device *pdev;
-
- phy = kzalloc(sizeof(*phy), GFP_KERNEL);
- if (!phy)
- return -ENOMEM;
-
- phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
- if (!phy->otg) {
- kfree(phy);
- return -ENOMEM;
- }
-
- phy->label = "ISP1105";
- phy->init = devboard_isp1105_init;
- phy->otg->set_vbus = devboard_isp1105_set_vbus;
-
- usbh1_pdata.otg = phy;
-
- pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
-
- return PTR_ERR_OR_ZERO(pdev);
-}
-
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-/*
- * system init for baseboard usage. Will be called by mx31moboard init.
- */
-void __init mx31moboard_devboard_init(void)
-{
- printk(KERN_INFO "Initializing mx31devboard peripherals\n");
-
- mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
- "devboard");
-
- imx31_add_imx_uart1(&uart_pdata);
-
- imx31_add_mxc_mmc(1, &sdhc2_pdata);
-
- devboard_init_sel_gpios();
-
- imx31_add_fsl_usb2_udc(&usb_pdata);
-
- devboard_usbh1_init();
-}
diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
deleted file mode 100644
index c269000..0000000
--- a/arch/arm/mach-imx/mx31moboard-marxbot.c
+++ /dev/null
@@ -1,270 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- */
-
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/spi/spi.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-
-#include <linux/usb/otg.h>
-
-#include "board-mx31moboard.h"
-#include "common.h"
-#include "devices-imx31.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
-
-static unsigned int marxbot_pins[] = {
- /* SDHC2 */
- MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
- MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
- MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
- MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
- /* dsPIC resets */
- MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
- /*battery detection */
- MX31_PIN_LCS0__GPIO3_23,
- /* USB H1 */
- MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
- MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
- MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
- MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
- MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
- /* SEL */
- MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
- MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
-};
-
-#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
-#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
-
-static int marxbot_sdhc2_get_ro(struct device *dev)
-{
- return !gpio_get_value(SDHC2_WP);
-}
-
-static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request(SDHC2_CD, "sdhc-detect");
- if (ret)
- return ret;
-
- gpio_direction_input(SDHC2_CD);
-
- ret = gpio_request(SDHC2_WP, "sdhc-wp");
- if (ret)
- goto err_gpio_free;
- gpio_direction_input(SDHC2_WP);
-
- ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "sdhc2-card-detect", data);
- if (ret)
- goto err_gpio_free_2;
-
- return 0;
-
-err_gpio_free_2:
- gpio_free(SDHC2_WP);
-err_gpio_free:
- gpio_free(SDHC2_CD);
-
- return ret;
-}
-
-static void marxbot_sdhc2_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(SDHC2_CD), data);
- gpio_free(SDHC2_WP);
- gpio_free(SDHC2_CD);
-}
-
-static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
- .get_ro = marxbot_sdhc2_get_ro,
- .init = marxbot_sdhc2_init,
- .exit = marxbot_sdhc2_exit,
-};
-
-#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_STXD5)
-#define DSPICS_RST_B IOMUX_TO_GPIO(MX31_PIN_SRXD5)
-
-static void dspics_resets_init(void)
-{
- if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
- gpio_direction_output(TRSLAT_RST_B, 0);
- gpio_export(TRSLAT_RST_B, false);
- }
-
- if (!gpio_request(DSPICS_RST_B, "dspics-rst")) {
- gpio_direction_output(DSPICS_RST_B, 0);
- gpio_export(DSPICS_RST_B, false);
- }
-}
-
-static struct spi_board_info marxbot_spi_board_info[] __initdata = {
- {
- .modalias = "spidev",
- .max_speed_hz = 300000,
- .bus_num = 1,
- .chip_select = 1, /* according spi1_cs[] ! */
- },
-};
-
-#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
-#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
-#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
-#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
-
-static void marxbot_init_sel_gpios(void)
-{
- if (!gpio_request(SEL0, "sel0")) {
- gpio_direction_input(SEL0);
- gpio_export(SEL0, true);
- }
-
- if (!gpio_request(SEL1, "sel1")) {
- gpio_direction_input(SEL1);
- gpio_export(SEL1, true);
- }
-
- if (!gpio_request(SEL2, "sel2")) {
- gpio_direction_input(SEL2);
- gpio_export(SEL2, true);
- }
-
- if (!gpio_request(SEL3, "sel3")) {
- gpio_direction_input(SEL3);
- gpio_export(SEL3, true);
- }
-}
-
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int marxbot_usbh1_hw_init(struct platform_device *pdev)
-{
- mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
-
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
- MXC_EHCI_INTERFACE_SINGLE_UNI);
-}
-
-#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
-#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
-
-static int marxbot_isp1105_init(struct usb_phy *otg)
-{
- int ret = gpio_request(USBH1_MODE, "usbh1-mode");
- if (ret)
- return ret;
- /* single ended */
- gpio_direction_output(USBH1_MODE, 0);
-
- ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
- if (ret) {
- gpio_free(USBH1_MODE);
- return ret;
- }
- gpio_direction_output(USBH1_VBUSEN_B, 1);
-
- return 0;
-}
-
-
-static int marxbot_isp1105_set_vbus(struct usb_otg *otg, bool on)
-{
- if (on)
- gpio_set_value(USBH1_VBUSEN_B, 0);
- else
- gpio_set_value(USBH1_VBUSEN_B, 1);
-
- return 0;
-}
-
-static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
- .init = marxbot_usbh1_hw_init,
- .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-};
-
-static int __init marxbot_usbh1_init(void)
-{
- struct usb_phy *phy;
- struct platform_device *pdev;
-
- phy = kzalloc(sizeof(*phy), GFP_KERNEL);
- if (!phy)
- return -ENOMEM;
-
- phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
- if (!phy->otg) {
- kfree(phy);
- return -ENOMEM;
- }
-
- phy->label = "ISP1105";
- phy->init = marxbot_isp1105_init;
- phy->otg->set_vbus = marxbot_isp1105_set_vbus;
-
- usbh1_pdata.otg = phy;
-
- pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
-
- return PTR_ERR_OR_ZERO(pdev);
-}
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-/*
- * system init for baseboard usage. Will be called by mx31moboard init.
- */
-void __init mx31moboard_marxbot_init(void)
-{
- printk(KERN_INFO "Initializing mx31marxbot peripherals\n");
-
- mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
- "marxbot");
-
- marxbot_init_sel_gpios();
-
- dspics_resets_init();
-
- imx31_add_mxc_mmc(1, &sdhc2_pdata);
-
- spi_register_board_info(marxbot_spi_board_info,
- ARRAY_SIZE(marxbot_spi_board_info));
-
- /* battery present pin */
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present");
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
- gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
-
- imx31_add_fsl_usb2_udc(&usb_pdata);
-
- marxbot_usbh1_init();
-}
diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c
deleted file mode 100644
index d165bd9..0000000
--- a/arch/arm/mach-imx/mx31moboard-smartbot.c
+++ /dev/null
@@ -1,124 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- */
-
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include "board-mx31moboard.h"
-#include "common.h"
-#include "devices-imx31.h"
-#include "ehci.h"
-#include "hardware.h"
-#include "iomux-mx3.h"
-#include "ulpi.h"
-
-static unsigned int smartbot_pins[] = {
- /* UART1 */
- MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
- MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
- /* ENABLES */
- MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
- MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-#if defined(CONFIG_USB_ULPI)
-
-static int smartbot_otg_init(struct platform_device *pdev)
-{
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
- .init = smartbot_otg_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-static int __init smartbot_otg_host_init(void)
-{
- struct platform_device *pdev;
-
- otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (!otg_host_pdata.otg)
- return -ENODEV;
-
- pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
-
- return PTR_ERR_OR_ZERO(pdev);
-}
-#else
-static inline int smartbot_otg_host_init(void) { return 0; }
-#endif
-
-#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
-#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
-#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
-#define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
-
-static void smartbot_resets_init(void)
-{
- if (!gpio_request(POWER_EN, "power-enable")) {
- gpio_direction_output(POWER_EN, 0);
- gpio_export(POWER_EN, false);
- }
-
- if (!gpio_request(DSPIC_RST_B, "dspic-rst")) {
- gpio_direction_output(DSPIC_RST_B, 0);
- gpio_export(DSPIC_RST_B, false);
- }
-
- if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
- gpio_direction_output(TRSLAT_RST_B, 0);
- gpio_export(TRSLAT_RST_B, false);
- }
-
- if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) {
- gpio_direction_output(TRSLAT_SRC_CHOICE, 0);
- gpio_export(TRSLAT_SRC_CHOICE, false);
- }
-}
-/*
- * system init for baseboard usage. Will be called by mx31moboard init.
- */
-void __init mx31moboard_smartbot_init(int board)
-{
- printk(KERN_INFO "Initializing mx31smartbot peripherals\n");
-
- mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
- "smartbot");
-
- imx31_add_imx_uart1(&uart_pdata);
-
- switch (board) {
- case MX31SMARTBOT:
- imx31_add_fsl_usb2_udc(&usb_pdata);
- break;
- case MX31EYEBOT:
- smartbot_otg_host_init();
- break;
- default:
- printk(KERN_WARNING "Unknown board %d, USB OTG not initialized",
- board);
- }
-
- smartbot_resets_init();
-}
diff --git a/arch/arm/mach-imx/mx35.h b/arch/arm/mach-imx/mx35.h
index 760de6a..5a8a87a 100644
--- a/arch/arm/mach-imx/mx35.h
+++ b/arch/arm/mach-imx/mx35.h
@@ -2,190 +2,17 @@
#ifndef __MACH_MX35_H__
#define __MACH_MX35_H__
-/*
- * IRAM
- */
-#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
-#define MX35_IRAM_SIZE SZ_128K
-
-#define MX35_L2CC_BASE_ADDR 0x30000000
-#define MX35_L2CC_SIZE SZ_1M
-
#define MX35_AIPS1_BASE_ADDR 0x43f00000
#define MX35_AIPS1_SIZE SZ_1M
-#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
-#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
-#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
-#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
-#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
-#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
-#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
-#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
-#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
-#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
-#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
-#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
-#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
-#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
-#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
-#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
-#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
-#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
-
#define MX35_SPBA0_BASE_ADDR 0x50000000
#define MX35_SPBA0_SIZE SZ_1M
-#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
-#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
-#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
-#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
-#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
-#define MX35_FEC_BASE_ADDR 0x50038000
-#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
-
#define MX35_AIPS2_BASE_ADDR 0x53f00000
#define MX35_AIPS2_SIZE SZ_1M
-#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
-#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
-#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
-#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
-#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
-#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
-#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
-#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
-#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
-#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
-#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
-#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
-#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
-#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
-#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
-#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
-#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
-#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
-#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
-#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
-#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
-#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
-#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
-#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
-/*
- * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
- * HS. When host support was implemented only a preliminary document was
- * available, which told 0x400. This works fine.
- */
-#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
-
-#define MX35_ROMP_BASE_ADDR 0x60000000
-#define MX35_ROMP_SIZE SZ_1M
-
#define MX35_AVIC_BASE_ADDR 0x68000000
#define MX35_AVIC_SIZE SZ_1M
-
-/*
- * Memory regions and CS
- */
-#define MX35_IPU_MEM_BASE_ADDR 0x70000000
-#define MX35_CSD0_BASE_ADDR 0x80000000
-#define MX35_CSD1_BASE_ADDR 0x90000000
-
-#define MX35_CS0_BASE_ADDR 0xa0000000
-#define MX35_CS1_BASE_ADDR 0xa8000000
-#define MX35_CS2_BASE_ADDR 0xb0000000
-#define MX35_CS3_BASE_ADDR 0xb2000000
-
-#define MX35_CS4_BASE_ADDR 0xb4000000
-#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
-#define MX35_CS4_SIZE SZ_32M
-
-#define MX35_CS5_BASE_ADDR 0xb6000000
-#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
-#define MX35_CS5_SIZE SZ_32M
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
#define MX35_X_MEMC_BASE_ADDR 0xb8000000
#define MX35_X_MEMC_SIZE SZ_64K
-#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
-#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
-#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
-#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
-#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
-
-#define MX35_NFC_BASE_ADDR 0xbb000000
-#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
#define MX35_IO_P2V(x) IMX_IO_P2V(x)
-#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#include <asm/irq.h>
-#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
-#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
-#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
-#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
-#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
-#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
-#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
-#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
-#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
-#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
-#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
-#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
-#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
-#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
-#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
-#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
-#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
-#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
-#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
-#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
-#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
-#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
-#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
-#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
-#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
-#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
-#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
-#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
-#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
-#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
-#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
-#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
-#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
-#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
-#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
-#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
-#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
-#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
-#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
-#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
-#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
-#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
-#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
-#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
-#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
-#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
-#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
-#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
-#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
-#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
-#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
-#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
-#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
-#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
-
-#define MX35_DMA_REQ_SSI2_RX1 22
-#define MX35_DMA_REQ_SSI2_TX1 23
-#define MX35_DMA_REQ_SSI2_RX0 24
-#define MX35_DMA_REQ_SSI2_TX0 25
-#define MX35_DMA_REQ_SSI1_RX1 26
-#define MX35_DMA_REQ_SSI1_TX1 27
-#define MX35_DMA_REQ_SSI1_RX0 28
-#define MX35_DMA_REQ_SSI1_TX0 29
-
-#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 2bfd2d5..fe2d0f5 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -8,35 +8,15 @@
#define __ASM_ARCH_MXC_H__
#include <linux/types.h>
+#include <soc/imx/cpu.h>
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
-#define MXC_CPU_MX1 1
-#define MXC_CPU_MX21 21
-#define MXC_CPU_MX25 25
-#define MXC_CPU_MX27 27
-#define MXC_CPU_MX31 31
-#define MXC_CPU_MX35 35
-#define MXC_CPU_MX51 51
-#define MXC_CPU_MX53 53
-#define MXC_CPU_IMX6SL 0x60
-#define MXC_CPU_IMX6DL 0x61
-#define MXC_CPU_IMX6SX 0x62
-#define MXC_CPU_IMX6Q 0x63
-#define MXC_CPU_IMX6UL 0x64
-#define MXC_CPU_IMX6ULL 0x65
-/* virtual cpu id for i.mx6ulz */
-#define MXC_CPU_IMX6ULZ 0x6b
-#define MXC_CPU_IMX6SLL 0x67
-#define MXC_CPU_IMX7D 0x72
-#define MXC_CPU_IMX7ULP 0xff
-
#define IMX_DDR_TYPE_LPDDR2 1
#ifndef __ASSEMBLY__
-extern unsigned int __mxc_cpu_type;
#ifdef CONFIG_SOC_IMX6SL
static inline bool cpu_is_imx6sl(void)
diff --git a/arch/arm/mach-imx/pcm037.h b/arch/arm/mach-imx/pcm037.h
deleted file mode 100644
index 470d3c8..0000000
--- a/arch/arm/mach-imx/pcm037.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __PCM037_H__
-#define __PCM037_H__
-
-enum pcm037_board_variant {
- PCM037_PCM970,
- PCM037_EET,
-};
-
-extern enum pcm037_board_variant pcm037_variant(void);
-
-#ifdef CONFIG_MACH_PCM037_EET
-int pcm037_eet_init_devices(void);
-#else
-static inline int pcm037_eet_init_devices(void) { return 0; }
-#endif
-
-#endif
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 2aa2692..cf4e933 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -109,6 +109,7 @@
np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
dcfg_base = of_iomap(np, 0);
+ of_node_put(np);
BUG_ON(!dcfg_base);
paddr = __pa_symbol(secondary_startup);
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index d943535..020e6de 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -7,6 +7,7 @@
* modify it under the terms of the GNU General Public License.
*/
+#include <linux/of_address.h>
#include <linux/kernel.h>
#include <linux/suspend.h>
#include <linux/io.h>
@@ -15,13 +16,20 @@
static int mx27_suspend_enter(suspend_state_t state)
{
+ void __iomem *ccm_base;
+ struct device_node *np;
u32 cscr;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
+ ccm_base = of_iomap(np, 0);
+ BUG_ON(!ccm_base);
+
switch (state) {
case PM_SUSPEND_MEM:
/* Clear MPEN and SPEN to disable MPLL/SPLL */
- cscr = imx_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+ cscr = imx_readl(ccm_base);
cscr &= 0xFFFFFFFC;
- imx_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+ imx_writel(cscr, ccm_base);
/* Executes WFI */
cpu_do_idle();
break;
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index baf3b47..e24409c 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -9,6 +9,7 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/genalloc.h>
+#include <linux/irqchip/arm-gic.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of.h>
@@ -618,6 +619,7 @@
static void imx6_pm_stby_poweroff(void)
{
+ gic_cpu_if_down(0);
imx6_set_lpm(STOP_POWER_OFF);
imx6q_suspend_finish(0);
@@ -657,6 +659,8 @@
if (of_property_read_bool(np, "fsl,pmic-stby-poweroff"))
imx6_pm_stby_poweroff_probe();
+
+ of_node_put(np);
}
void __init imx6q_pm_init(void)
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
index 7b2f738..2e756d8 100644
--- a/arch/arm/mach-imx/pm-imx7ulp.c
+++ b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -62,6 +62,7 @@
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
smc1_base = of_iomap(np, 0);
+ of_node_put(np);
WARN_ON(!smc1_base);
imx7ulp_set_lpm(ULP_PM_RUN);
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 0beea6d..f52f371 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -43,9 +43,6 @@
int bit;
u32 val;
- if (!src_base)
- return -ENODEV;
-
if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
return -EINVAL;
diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h
deleted file mode 100644
index b367902..0000000
--- a/arch/arm/mach-imx/ulpi.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MACH_ULPI_H
-#define __MACH_ULPI_H
-
-#include <linux/usb/ulpi.h>
-
-#ifdef CONFIG_USB_ULPI_VIEWPORT
-static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
-{
- return otg_ulpi_create(&ulpi_viewport_access_ops, flags);
-}
-#else
-static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
-{
- return NULL;
-}
-#endif
-
-#endif /* __MACH_ULPI_H */
-
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index 2406cab..7a9808b 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -3,7 +3,6 @@
bool "ARM Ltd. Integrator family"
depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V6
select ARM_AMBA
- select COMMON_CLK_VERSATILE
select CMA
select DMA_CMA
select HAVE_TCM
@@ -14,7 +13,6 @@
select POWER_RESET_VERSATILE
select POWER_SUPPLY
select SOC_INTEGRATOR_CM
- select SPARSE_IRQ
select VERSATILE_FPGA_IRQ
help
Support for ARM's Integrator platform.
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index 71b97ff..7857a55 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -5,7 +5,6 @@
# Object file lists.
-obj-y := core.o lm.o
+obj-y := core.o
obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o
-obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 9da3ae2..0fe5e1d 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -21,10 +21,10 @@
#include <linux/stat.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/pgtable.h>
#include <asm/mach-types.h>
#include <asm/mach/time.h>
-#include <asm/pgtable.h>
#include "hardware.h"
#include "cm.h"
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
deleted file mode 100644
index 1ecbea5..0000000
--- a/arch/arm/mach-integrator/impd1.c
+++ /dev/null
@@ -1,478 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-integrator/impd1.c
- *
- * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
- *
- * This file provides the core support for the IM-PD1 module.
- *
- * Module / boot parameters.
- * lmid=n impd1.lmid=n - set the logic module position in stack to 'n'
- */
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/mm.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/clcd.h>
-#include <linux/amba/mmci.h>
-#include <linux/io.h>
-#include <linux/platform_data/clk-integrator.h>
-#include <linux/slab.h>
-#include <linux/irqchip/arm-vic.h>
-#include <linux/gpio/machine.h>
-
-#include <linux/sizes.h>
-#include "lm.h"
-#include "impd1.h"
-
-static int module_id;
-
-module_param_named(lmid, module_id, int, 0444);
-MODULE_PARM_DESC(lmid, "logic module stack position");
-
-struct impd1_module {
- void __iomem *base;
- void __iomem *vic_base;
-};
-
-void impd1_tweak_control(struct device *dev, u32 mask, u32 val)
-{
- struct impd1_module *impd1 = dev_get_drvdata(dev);
- u32 cur;
-
- val &= mask;
- cur = readl(impd1->base + IMPD1_CTRL) & ~mask;
- writel(cur | val, impd1->base + IMPD1_CTRL);
-}
-
-EXPORT_SYMBOL(impd1_tweak_control);
-
-/*
- * MMC support
- */
-static struct mmci_platform_data mmc_data = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-};
-
-/*
- * CLCD support
- */
-#define PANEL PROSPECTOR
-
-#define LTM10C209 1
-#define PROSPECTOR 2
-#define SVGA 3
-#define VGA 4
-
-#if PANEL == VGA
-#define PANELTYPE vga
-static struct clcd_panel vga = {
- .mode = {
- .name = "VGA",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = 39721,
- .left_margin = 40,
- .right_margin = 24,
- .upper_margin = 32,
- .lower_margin = 11,
- .hsync_len = 96,
- .vsync_len = 2,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED,
- },
- .width = -1,
- .height = -1,
- .tim2 = TIM2_BCD | TIM2_IPC,
- .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
- .caps = CLCD_CAP_5551,
- .connector = IMPD1_CTRL_DISP_VGA,
- .bpp = 16,
- .grayscale = 0,
-};
-
-#elif PANEL == SVGA
-#define PANELTYPE svga
-static struct clcd_panel svga = {
- .mode = {
- .name = "SVGA",
- .refresh = 0,
- .xres = 800,
- .yres = 600,
- .pixclock = 27778,
- .left_margin = 20,
- .right_margin = 20,
- .upper_margin = 5,
- .lower_margin = 5,
- .hsync_len = 164,
- .vsync_len = 62,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED,
- },
- .width = -1,
- .height = -1,
- .tim2 = TIM2_BCD,
- .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
- .connector = IMPD1_CTRL_DISP_VGA,
- .caps = CLCD_CAP_5551,
- .bpp = 16,
- .grayscale = 0,
-};
-
-#elif PANEL == PROSPECTOR
-#define PANELTYPE prospector
-static struct clcd_panel prospector = {
- .mode = {
- .name = "PROSPECTOR",
- .refresh = 0,
- .xres = 640,
- .yres = 480,
- .pixclock = 40000,
- .left_margin = 33,
- .right_margin = 64,
- .upper_margin = 36,
- .lower_margin = 7,
- .hsync_len = 64,
- .vsync_len = 25,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- .vmode = FB_VMODE_NONINTERLACED,
- },
- .width = -1,
- .height = -1,
- .tim2 = TIM2_BCD,
- .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
- .caps = CLCD_CAP_5551,
- .fixedtimings = 1,
- .connector = IMPD1_CTRL_DISP_LCD,
- .bpp = 16,
- .grayscale = 0,
-};
-
-#elif PANEL == LTM10C209
-#define PANELTYPE ltm10c209
-/*
- * Untested.
- */
-static struct clcd_panel ltm10c209 = {
- .mode = {
- .name = "LTM10C209",
- .refresh = 0,
- .xres = 640,
- .yres = 480,
- .pixclock = 40000,
- .left_margin = 20,
- .right_margin = 20,
- .upper_margin = 19,
- .lower_margin = 19,
- .hsync_len = 20,
- .vsync_len = 10,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- .vmode = FB_VMODE_NONINTERLACED,
- },
- .width = -1,
- .height = -1,
- .tim2 = TIM2_BCD,
- .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
- .caps = CLCD_CAP_5551,
- .fixedtimings = 1,
- .connector = IMPD1_CTRL_DISP_LCD,
- .bpp = 16,
- .grayscale = 0,
-};
-#endif
-
-/*
- * Disable all display connectors on the interface module.
- */
-static void impd1fb_clcd_disable(struct clcd_fb *fb)
-{
- impd1_tweak_control(fb->dev->dev.parent, IMPD1_CTRL_DISP_MASK, 0);
-}
-
-/*
- * Enable the relevant connector on the interface module.
- */
-static void impd1fb_clcd_enable(struct clcd_fb *fb)
-{
- impd1_tweak_control(fb->dev->dev.parent, IMPD1_CTRL_DISP_MASK,
- fb->panel->connector | IMPD1_CTRL_DISP_ENABLE);
-}
-
-static int impd1fb_clcd_setup(struct clcd_fb *fb)
-{
- unsigned long framebase = fb->dev->res.start + 0x01000000;
- unsigned long framesize = SZ_1M;
- int ret = 0;
-
- fb->panel = &PANELTYPE;
-
- if (!request_mem_region(framebase, framesize, "clcd framebuffer")) {
- printk(KERN_ERR "IM-PD1: unable to reserve framebuffer\n");
- return -EBUSY;
- }
-
- fb->fb.screen_base = ioremap(framebase, framesize);
- if (!fb->fb.screen_base) {
- printk(KERN_ERR "IM-PD1: unable to map framebuffer\n");
- ret = -ENOMEM;
- goto free_buffer;
- }
-
- fb->fb.fix.smem_start = framebase;
- fb->fb.fix.smem_len = framesize;
-
- return 0;
-
- free_buffer:
- release_mem_region(framebase, framesize);
- return ret;
-}
-
-static int impd1fb_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
-{
- unsigned long start, size;
-
- start = vma->vm_pgoff + (fb->fb.fix.smem_start >> PAGE_SHIFT);
- size = vma->vm_end - vma->vm_start;
-
- return remap_pfn_range(vma, vma->vm_start, start, size,
- vma->vm_page_prot);
-}
-
-static void impd1fb_clcd_remove(struct clcd_fb *fb)
-{
- iounmap(fb->fb.screen_base);
- release_mem_region(fb->fb.fix.smem_start, fb->fb.fix.smem_len);
-}
-
-static struct clcd_board impd1_clcd_data = {
- .name = "IM-PD/1",
- .caps = CLCD_CAP_5551 | CLCD_CAP_888,
- .check = clcdfb_check,
- .decode = clcdfb_decode,
- .disable = impd1fb_clcd_disable,
- .enable = impd1fb_clcd_enable,
- .setup = impd1fb_clcd_setup,
- .mmap = impd1fb_clcd_mmap,
- .remove = impd1fb_clcd_remove,
-};
-
-struct impd1_device {
- unsigned long offset;
- unsigned int irq[2];
- unsigned int id;
- void *platform_data;
-};
-
-static struct impd1_device impd1_devs[] = {
- {
- .offset = 0x00100000,
- .irq = { 1 },
- .id = 0x00141011,
- }, {
- .offset = 0x00200000,
- .irq = { 2 },
- .id = 0x00141011,
- }, {
- .offset = 0x00300000,
- .irq = { 3 },
- .id = 0x00041022,
- }, {
- .offset = 0x00400000,
- .irq = { 4 },
- .id = 0x00041061,
- }, {
- .offset = 0x00500000,
- .irq = { 5 },
- .id = 0x00041061,
- }, {
- .offset = 0x00600000,
- .irq = { 6 },
- .id = 0x00041130,
- }, {
- .offset = 0x00700000,
- .irq = { 7, 8 },
- .id = 0x00041181,
- .platform_data = &mmc_data,
- }, {
- .offset = 0x00800000,
- .irq = { 9 },
- .id = 0x00041041,
- }, {
- .offset = 0x01000000,
- .irq = { 11 },
- .id = 0x00041110,
- .platform_data = &impd1_clcd_data,
- }
-};
-
-/*
- * Valid IRQs: 0 thru 9 and 11, 10 unused.
- */
-#define IMPD1_VALID_IRQS 0x00000bffU
-
-/*
- * As this module is bool, it is OK to have this as __ref() - no
- * probe calls will be done after the initial system bootup, as devices
- * are discovered as part of the machine startup.
- */
-static int __ref impd1_probe(struct lm_device *dev)
-{
- struct impd1_module *impd1;
- int irq_base;
- int i;
-
- if (dev->id != module_id)
- return -EINVAL;
-
- if (!devm_request_mem_region(&dev->dev, dev->resource.start,
- SZ_4K, "LM registers"))
- return -EBUSY;
-
- impd1 = devm_kzalloc(&dev->dev, sizeof(struct impd1_module),
- GFP_KERNEL);
- if (!impd1)
- return -ENOMEM;
-
- impd1->base = devm_ioremap(&dev->dev, dev->resource.start, SZ_4K);
- if (!impd1->base)
- return -ENOMEM;
-
- integrator_impd1_clk_init(impd1->base, dev->id);
-
- if (!devm_request_mem_region(&dev->dev,
- dev->resource.start + 0x03000000,
- SZ_4K, "VIC"))
- return -EBUSY;
-
- impd1->vic_base = devm_ioremap(&dev->dev,
- dev->resource.start + 0x03000000,
- SZ_4K);
- if (!impd1->vic_base)
- return -ENOMEM;
-
- irq_base = vic_init_cascaded(impd1->vic_base, dev->irq,
- IMPD1_VALID_IRQS, 0);
-
- lm_set_drvdata(dev, impd1);
-
- dev_info(&dev->dev, "IM-PD1 found at 0x%08lx\n",
- (unsigned long)dev->resource.start);
-
- for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) {
- struct impd1_device *idev = impd1_devs + i;
- struct amba_device *d;
- unsigned long pc_base;
- char devname[32];
- int irq1 = idev->irq[0];
- int irq2 = idev->irq[1];
-
- /* Translate IRQs to IM-PD1 local numberspace */
- if (irq1)
- irq1 += irq_base;
- if (irq2)
- irq2 += irq_base;
-
- pc_base = dev->resource.start + idev->offset;
- snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
-
- /* Add GPIO descriptor lookup table for the PL061 block */
- if (idev->offset == 0x00400000) {
- struct gpiod_lookup_table *lookup;
- char *chipname;
- char *mmciname;
-
- lookup = devm_kzalloc(&dev->dev,
- struct_size(lookup, table, 3),
- GFP_KERNEL);
- chipname = devm_kstrdup(&dev->dev, devname, GFP_KERNEL);
- mmciname = devm_kasprintf(&dev->dev, GFP_KERNEL,
- "lm%x:00700", dev->id);
- if (!lookup || !chipname || !mmciname)
- return -ENOMEM;
-
- lookup->dev_id = mmciname;
- /*
- * Offsets on GPIO block 1:
- * 3 = MMC WP (write protect)
- * 4 = MMC CD (card detect)
- *
- * Offsets on GPIO block 2:
- * 0 = Up key
- * 1 = Down key
- * 2 = Left key
- * 3 = Right key
- * 4 = Key lower left
- * 5 = Key lower right
- */
- /* We need the two MMCI GPIO entries */
- lookup->table[0].chip_label = chipname;
- lookup->table[0].chip_hwnum = 3;
- lookup->table[0].con_id = "wp";
- lookup->table[1].chip_label = chipname;
- lookup->table[1].chip_hwnum = 4;
- lookup->table[1].con_id = "cd";
- lookup->table[1].flags = GPIO_ACTIVE_LOW;
- gpiod_add_lookup_table(lookup);
- }
-
- d = amba_ahb_device_add_res(&dev->dev, devname, pc_base, SZ_4K,
- irq1, irq2,
- idev->platform_data, idev->id,
- &dev->resource);
- if (IS_ERR(d)) {
- dev_err(&dev->dev, "unable to register device: %ld\n", PTR_ERR(d));
- continue;
- }
- }
-
- return 0;
-}
-
-static int impd1_remove_one(struct device *dev, void *data)
-{
- device_unregister(dev);
- return 0;
-}
-
-static void impd1_remove(struct lm_device *dev)
-{
- device_for_each_child(&dev->dev, NULL, impd1_remove_one);
- integrator_impd1_clk_exit(dev->id);
-
- lm_set_drvdata(dev, NULL);
-}
-
-static struct lm_driver impd1_driver = {
- .drv = {
- .name = "impd1",
- /*
- * As we're dropping the probe() function, suppress driver
- * binding from sysfs.
- */
- .suppress_bind_attrs = true,
- },
- .probe = impd1_probe,
- .remove = impd1_remove,
-};
-
-static int __init impd1_init(void)
-{
- return lm_driver_register(&impd1_driver);
-}
-
-static void __exit impd1_exit(void)
-{
- lm_driver_unregister(&impd1_driver);
-}
-
-module_init(impd1_init);
-module_exit(impd1_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Integrator/IM-PD1 logic module core driver");
-MODULE_AUTHOR("Deep Blue Solutions Ltd");
diff --git a/arch/arm/mach-integrator/impd1.h b/arch/arm/mach-integrator/impd1.h
deleted file mode 100644
index 36124d3..0000000
--- a/arch/arm/mach-integrator/impd1.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#define IMPD1_LEDS 0x0c
-#define IMPD1_INT 0x10
-#define IMPD1_SW 0x14
-#define IMPD1_CTRL 0x18
-
-#define IMPD1_CTRL_DISP_LCD (0 << 0)
-#define IMPD1_CTRL_DISP_VGA (1 << 0)
-#define IMPD1_CTRL_DISP_LCD1 (2 << 0)
-#define IMPD1_CTRL_DISP_ENABLE (1 << 2)
-#define IMPD1_CTRL_DISP_MASK (7 << 0)
-
-struct device;
-
-void impd1_tweak_control(struct device *dev, u32 mask, u32 val);
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 035069e..58b02cb 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -23,7 +23,6 @@
#include "hardware.h"
#include "cm.h"
#include "common.h"
-#include "lm.h"
/* Regmap to the AP system controller */
static struct regmap *ap_syscon_map;
@@ -174,10 +173,7 @@
static void __init ap_init_of(void)
{
- u32 sc_dec;
struct device_node *syscon;
- int ret;
- int i;
of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
@@ -189,33 +185,6 @@
pr_crit("could not find Integrator/AP system controller\n");
return;
}
-
- ret = regmap_read(ap_syscon_map,
- INTEGRATOR_SC_DEC_OFFSET,
- &sc_dec);
- if (ret) {
- pr_crit("could not read from Integrator/AP syscon\n");
- return;
- }
-
- for (i = 0; i < 4; i++) {
- struct lm_device *lmdev;
-
- if ((sc_dec & (16 << i)) == 0)
- continue;
-
- lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
- if (!lmdev)
- continue;
-
- lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
- lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
- lmdev->resource.flags = IORESOURCE_MEM;
- lmdev->irq = irq_of_parse_and_map(syscon, i);
- lmdev->id = i;
-
- lm_device_register(lmdev);
- }
}
static const char * ap_dt_board_compat[] = {
diff --git a/arch/arm/mach-integrator/lm.c b/arch/arm/mach-integrator/lm.c
deleted file mode 100644
index 55cd173..0000000
--- a/arch/arm/mach-integrator/lm.c
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-integrator/lm.c
- *
- * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/slab.h>
-
-#include "lm.h"
-
-#define to_lm_device(d) container_of(d, struct lm_device, dev)
-#define to_lm_driver(d) container_of(d, struct lm_driver, drv)
-
-static int lm_match(struct device *dev, struct device_driver *drv)
-{
- return 1;
-}
-
-static int lm_bus_probe(struct device *dev)
-{
- struct lm_device *lmdev = to_lm_device(dev);
- struct lm_driver *lmdrv = to_lm_driver(dev->driver);
-
- return lmdrv->probe(lmdev);
-}
-
-static int lm_bus_remove(struct device *dev)
-{
- struct lm_device *lmdev = to_lm_device(dev);
- struct lm_driver *lmdrv = to_lm_driver(dev->driver);
-
- if (lmdrv->remove)
- lmdrv->remove(lmdev);
- return 0;
-}
-
-static struct bus_type lm_bustype = {
- .name = "logicmodule",
- .match = lm_match,
- .probe = lm_bus_probe,
- .remove = lm_bus_remove,
-// .suspend = lm_bus_suspend,
-// .resume = lm_bus_resume,
-};
-
-static int __init lm_init(void)
-{
- return bus_register(&lm_bustype);
-}
-
-postcore_initcall(lm_init);
-
-int lm_driver_register(struct lm_driver *drv)
-{
- drv->drv.bus = &lm_bustype;
- return driver_register(&drv->drv);
-}
-
-void lm_driver_unregister(struct lm_driver *drv)
-{
- driver_unregister(&drv->drv);
-}
-
-static void lm_device_release(struct device *dev)
-{
- struct lm_device *d = to_lm_device(dev);
-
- kfree(d);
-}
-
-int lm_device_register(struct lm_device *dev)
-{
- int ret;
-
- dev->dev.release = lm_device_release;
- dev->dev.bus = &lm_bustype;
-
- ret = dev_set_name(&dev->dev, "lm%d", dev->id);
- if (ret)
- return ret;
- dev->resource.name = dev_name(&dev->dev);
-
- ret = request_resource(&iomem_resource, &dev->resource);
- if (ret == 0) {
- ret = device_register(&dev->dev);
- if (ret)
- release_resource(&dev->resource);
- }
- return ret;
-}
-
-EXPORT_SYMBOL(lm_driver_register);
-EXPORT_SYMBOL(lm_driver_unregister);
diff --git a/arch/arm/mach-integrator/lm.h b/arch/arm/mach-integrator/lm.h
deleted file mode 100644
index 172966a..0000000
--- a/arch/arm/mach-integrator/lm.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-struct lm_device {
- struct device dev;
- struct resource resource;
- unsigned int irq;
- unsigned int id;
-};
-
-struct lm_driver {
- struct device_driver drv;
- int (*probe)(struct lm_device *);
- void (*remove)(struct lm_device *);
- int (*suspend)(struct lm_device *, pm_message_t);
- int (*resume)(struct lm_device *);
-};
-
-int lm_driver_register(struct lm_driver *drv);
-void lm_driver_unregister(struct lm_driver *drv);
-
-int lm_device_register(struct lm_device *dev);
-
-#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
-#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
diff --git a/arch/arm/mach-iop32x/i2c.c b/arch/arm/mach-iop32x/i2c.c
index dc9f6a1..e422286 100644
--- a/arch/arm/mach-iop32x/i2c.c
+++ b/arch/arm/mach-iop32x/i2c.c
@@ -17,7 +17,6 @@
#include <linux/serial_core.h>
#include <linux/io.h>
#include <linux/gpio/machine.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <asm/setup.h>
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 04a7d38..49caaa7 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -31,7 +31,6 @@
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
-#include <asm/pgtable.h>
#include "hardware.h"
#include "irqs.h"
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 4bd596d..b455d70 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -27,7 +27,6 @@
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
-#include <asm/pgtable.h>
#include "hardware.h"
#include "irqs.h"
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 5382a93..78b9a5e 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -35,7 +35,6 @@
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
-#include <asm/pgtable.h>
#include "hardware.h"
#include "irqs.h"
diff --git a/arch/arm/mach-iop32x/time.c b/arch/arm/mach-iop32x/time.c
index 18a4df5..ae533b6 100644
--- a/arch/arm/mach-iop32x/time.c
+++ b/arch/arm/mach-iop32x/time.c
@@ -137,13 +137,6 @@
return IRQ_HANDLED;
}
-static struct irqaction iop_timer_irq = {
- .name = "IOP Timer Tick",
- .handler = iop_timer_interrupt,
- .flags = IRQF_TIMER | IRQF_IRQPOLL,
- .dev_id = &iop_clockevent,
-};
-
static unsigned long iop_tick_rate;
unsigned long get_iop_tick_rate(void)
{
@@ -154,6 +147,7 @@
void __init iop_init_time(unsigned long tick_rate)
{
u32 timer_ctl;
+ int irq = IRQ_IOP32X_TIMER0;
sched_clock_register(iop_read_sched_clock, 32, tick_rate);
@@ -168,7 +162,9 @@
*/
write_tmr0(timer_ctl & ~IOP_TMR_EN);
write_tisr(1);
- setup_irq(IRQ_IOP32X_TIMER0, &iop_timer_irq);
+ if (request_irq(irq, iop_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
+ "IOP Timer Tick", &iop_clockevent))
+ pr_err("Failed to request irq() %d (IOP Timer Tick)\n", irq);
iop_clockevent.cpumask = cpumask_of(0);
clockevents_config_and_register(&iop_clockevent, tick_rate,
0xf, 0xfffffffe);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 381f452..000f672 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -29,11 +29,11 @@
#include <linux/sched_clock.h>
#include <linux/irqchip/irq-ixp4xx.h>
#include <linux/platform_data/timer-ixp4xx.h>
+#include <linux/dma-map-ops.h>
#include <mach/udc.h>
#include <mach/hardware.h>
#include <mach/io.h>
#include <linux/uaccess.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/exception.h>
#include <asm/irq.h>
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 648932d..507ee38 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -132,6 +132,22 @@
};
/* Built-in 10/100 Ethernet MAC interfaces */
+static struct resource fsg_eth_npeb_resources[] = {
+ {
+ .start = IXP4XX_EthB_BASE_PHYS,
+ .end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource fsg_eth_npec_resources[] = {
+ {
+ .start = IXP4XX_EthC_BASE_PHYS,
+ .end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static struct eth_plat_info fsg_plat_eth[] = {
{
.phy = 5,
@@ -151,12 +167,16 @@
.dev = {
.platform_data = fsg_plat_eth,
},
+ .num_resources = ARRAY_SIZE(fsg_eth_npeb_resources),
+ .resource = fsg_eth_npeb_resources,
}, {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEC,
.dev = {
.platform_data = fsg_plat_eth + 1,
},
+ .num_resources = ARRAY_SIZE(fsg_eth_npec_resources),
+ .resource = fsg_eth_npec_resources,
}
};
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index a0e0b6b..07b50df 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -11,6 +11,7 @@
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pci.h>
+#include <linux/platform_data/wan_ixp4xx_hss.h>
#include <linux/serial_8250.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -272,6 +273,22 @@
/* Built-in 10/100 Ethernet MAC interfaces */
+static struct resource eth_npeb_resources[] = {
+ {
+ .start = IXP4XX_EthB_BASE_PHYS,
+ .end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource eth_npec_resources[] = {
+ {
+ .start = IXP4XX_EthC_BASE_PHYS,
+ .end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static struct eth_plat_info eth_plat[] = {
{
.phy = 0,
@@ -289,10 +306,14 @@
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev.platform_data = eth_plat,
+ .num_resources = ARRAY_SIZE(eth_npeb_resources),
+ .resource = eth_npeb_resources,
}, {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEC,
.dev.platform_data = eth_plat + 1,
+ .num_resources = ARRAY_SIZE(eth_npec_resources),
+ .resource = eth_npec_resources,
}
};
@@ -405,6 +426,9 @@
if (hw_bits & CFG_HW_HAS_HSS1)
device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
+ hss_plat[0].timer_freq = ixp4xx_timer_freq;
+ hss_plat[1].timer_freq = ixp4xx_timer_freq;
+
gpio_request(GPIO_SCL, "SCL/clock");
gpio_request(GPIO_SDA, "SDA/data");
gpio_request(GPIO_STR, "strobe");
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
deleted file mode 100644
index d792130..0000000
--- a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * PTP 1588 clock using the IXP46X
- *
- * Copyright (C) 2010 OMICRON electronics GmbH
- */
-
-#ifndef _IXP46X_TS_H_
-#define _IXP46X_TS_H_
-
-#define DEFAULT_ADDEND 0xF0000029
-#define TICKS_NS_SHIFT 4
-
-struct ixp46x_channel_ctl {
- u32 ch_control; /* 0x40 Time Synchronization Channel Control */
- u32 ch_event; /* 0x44 Time Synchronization Channel Event */
- u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
- u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
- u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
- u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
- u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
- u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
-};
-
-struct ixp46x_ts_regs {
- u32 control; /* 0x00 Time Sync Control Register */
- u32 event; /* 0x04 Time Sync Event Register */
- u32 addend; /* 0x08 Time Sync Addend Register */
- u32 accum; /* 0x0C Time Sync Accumulator Register */
- u32 test; /* 0x10 Time Sync Test Register */
- u32 unused; /* 0x14 */
- u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
- u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
- u32 systime_lo; /* 0x20 SystemTime_Low Register */
- u32 systime_hi; /* 0x24 SystemTime_High Register */
- u32 trgt_lo; /* 0x28 TargetTime_Low Register */
- u32 trgt_hi; /* 0x2C TargetTime_High Register */
- u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
- u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
- u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
- u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
-
- struct ixp46x_channel_ctl channel[3];
-};
-
-/* 0x00 Time Sync Control Register Bits */
-#define TSCR_AMM (1<<3)
-#define TSCR_ASM (1<<2)
-#define TSCR_TTM (1<<1)
-#define TSCR_RST (1<<0)
-
-/* 0x04 Time Sync Event Register Bits */
-#define TSER_SNM (1<<3)
-#define TSER_SNS (1<<2)
-#define TTIPEND (1<<1)
-
-/* 0x40 Time Synchronization Channel Control Register Bits */
-#define MASTER_MODE (1<<0)
-#define TIMESTAMP_ALL (1<<1)
-
-/* 0x44 Time Synchronization Channel Event Register Bits */
-#define TX_SNAPSHOT_LOCKED (1<<0)
-#define RX_SNAPSHOT_LOCKED (1<<1)
-
-/* The ptp_ixp46x module will set this variable */
-extern int ixp46x_phc_index;
-
-#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index 342acbe..6d403fe 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -15,6 +15,7 @@
#ifndef __ASSEMBLY__
#include <linux/reboot.h>
+#include <linux/platform_data/eth_ixp4xx.h>
#include <asm/types.h>
@@ -92,27 +93,6 @@
void __iomem *cs1;
};
-#define IXP4XX_ETH_NPEA 0x00
-#define IXP4XX_ETH_NPEB 0x10
-#define IXP4XX_ETH_NPEC 0x20
-
-/* Information about built-in Ethernet MAC interfaces */
-struct eth_plat_info {
- u8 phy; /* MII PHY ID, 0 - 31 */
- u8 rxq; /* configurable, currently 0 - 31 only */
- u8 txreadyq;
- u8 hwaddr[6];
-};
-
-/* Information about built-in HSS (synchronous serial) interfaces */
-struct hss_plat_info {
- int (*set_clock)(int port, unsigned int clock_type);
- int (*open)(int port, void *pdev,
- void (*set_carrier_cb)(void *pdev, int carrier));
- void (*close)(int port, void *pdev);
- u8 txreadyq;
-};
-
/*
* Frequency of clock used for primary clocksource
*/
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 6f0f7ed..45d5b72 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -187,6 +187,22 @@
};
/* Built-in 10/100 Ethernet MAC interfaces */
+static struct resource ixp425_npeb_resources[] = {
+ {
+ .start = IXP4XX_EthB_BASE_PHYS,
+ .end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource ixp425_npec_resources[] = {
+ {
+ .start = IXP4XX_EthC_BASE_PHYS,
+ .end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static struct eth_plat_info ixdp425_plat_eth[] = {
{
.phy = 0,
@@ -204,10 +220,14 @@
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev.platform_data = ixdp425_plat_eth,
+ .num_resources = ARRAY_SIZE(ixp425_npeb_resources),
+ .resource = ixp425_npeb_resources,
}, {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEC,
.dev.platform_data = ixdp425_plat_eth + 1,
+ .num_resources = ARRAY_SIZE(ixp425_npec_resources),
+ .resource = ixp425_npec_resources,
}
};
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index c142cfa..6959ad2 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -165,6 +165,14 @@
};
/* Built-in 10/100 Ethernet MAC interfaces */
+static struct resource nas100d_eth_resources[] = {
+ {
+ .start = IXP4XX_EthB_BASE_PHYS,
+ .end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static struct eth_plat_info nas100d_plat_eth[] = {
{
.phy = 0,
@@ -178,6 +186,8 @@
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev.platform_data = nas100d_plat_eth,
+ .num_resources = ARRAY_SIZE(nas100d_eth_resources),
+ .resource = nas100d_eth_resources,
}
};
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index ee1877f..a428bb9 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -185,6 +185,14 @@
};
/* Built-in 10/100 Ethernet MAC interfaces */
+static struct resource nslu2_eth_resources[] = {
+ {
+ .start = IXP4XX_EthB_BASE_PHYS,
+ .end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static struct eth_plat_info nslu2_plat_eth[] = {
{
.phy = 1,
@@ -198,6 +206,8 @@
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev.platform_data = nslu2_plat_eth,
+ .num_resources = ARRAY_SIZE(nslu2_eth_resources),
+ .resource = nslu2_eth_resources,
}
};
diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c
index 6ed5a9a..8f2b8c4 100644
--- a/arch/arm/mach-ixp4xx/omixp-setup.c
+++ b/arch/arm/mach-ixp4xx/omixp-setup.c
@@ -170,6 +170,22 @@
};
/* Built-in 10/100 Ethernet MAC interfaces */
+static struct resource ixp425_npeb_resources[] = {
+ {
+ .start = IXP4XX_EthB_BASE_PHYS,
+ .end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource ixp425_npec_resources[] = {
+ {
+ .start = IXP4XX_EthC_BASE_PHYS,
+ .end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static struct eth_plat_info ixdp425_plat_eth[] = {
{
.phy = 0,
@@ -187,10 +203,14 @@
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEB,
.dev.platform_data = ixdp425_plat_eth,
+ .num_resources = ARRAY_SIZE(ixp425_npeb_resources),
+ .resource = ixp425_npeb_resources,
}, {
.name = "ixp4xx_eth",
.id = IXP4XX_ETH_NPEC,
.dev.platform_data = ixdp425_plat_eth + 1,
+ .num_resources = ARRAY_SIZE(ixp425_npec_resources),
+ .resource = ixp425_npec_resources,
},
};
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index d2ebb7c..e506d2a 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -124,6 +124,22 @@
.num_resources = ARRAY_SIZE(vulcan_uart_resources),
};
+static struct resource vulcan_npeb_resources[] = {
+ {
+ .start = IXP4XX_EthB_BASE_PHYS,
+ .end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource vulcan_npec_resources[] = {
+ {
+ .start = IXP4XX_EthC_BASE_PHYS,
+ .end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static struct eth_plat_info vulcan_plat_eth[] = {
[0] = {
.phy = 0,
@@ -144,6 +160,8 @@
.dev = {
.platform_data = &vulcan_plat_eth[0],
},
+ .num_resources = ARRAY_SIZE(vulcan_npeb_resources),
+ .resource = vulcan_npeb_resources,
},
[1] = {
.name = "ixp4xx_eth",
@@ -151,6 +169,8 @@
.dev = {
.platform_data = &vulcan_plat_eth[1],
},
+ .num_resources = ARRAY_SIZE(vulcan_npec_resources),
+ .resource = vulcan_npec_resources,
},
};
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
index 697aded..b8fa01f 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -8,6 +8,7 @@
*/
#include <linux/io.h>
#include <linux/of.h>
+#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
@@ -24,8 +25,7 @@
#include "keystone.h"
-static unsigned long keystone_dma_pfn_offset __read_mostly;
-
+#ifdef CONFIG_ARM_LPAE
static int keystone_platform_notifier(struct notifier_block *nb,
unsigned long event, void *data)
{
@@ -38,9 +38,12 @@
return NOTIFY_BAD;
if (!dev->of_node) {
- dev->dma_pfn_offset = keystone_dma_pfn_offset;
- dev_err(dev, "set dma_pfn_offset%08lx\n",
- dev->dma_pfn_offset);
+ int ret = dma_direct_set_offset(dev, KEYSTONE_HIGH_PHYS_START,
+ KEYSTONE_LOW_PHYS_START,
+ KEYSTONE_HIGH_PHYS_SIZE);
+ dev_err(dev, "set dma_offset%08llx%s\n",
+ KEYSTONE_HIGH_PHYS_START - KEYSTONE_LOW_PHYS_START,
+ ret ? " failed" : "");
}
return NOTIFY_OK;
}
@@ -48,14 +51,14 @@
static struct notifier_block platform_nb = {
.notifier_call = keystone_platform_notifier,
};
+#endif /* CONFIG_ARM_LPAE */
static void __init keystone_init(void)
{
- if (PHYS_OFFSET >= KEYSTONE_HIGH_PHYS_START) {
- keystone_dma_pfn_offset = PFN_DOWN(KEYSTONE_HIGH_PHYS_START -
- KEYSTONE_LOW_PHYS_START);
+#ifdef CONFIG_ARM_LPAE
+ if (PHYS_OFFSET >= KEYSTONE_HIGH_PHYS_START)
bus_register_notifier(&platform_bus_type, &platform_nb);
- }
+#endif
keystone_pm_runtime_init();
}
diff --git a/arch/arm/mach-keystone/memory.h b/arch/arm/mach-keystone/memory.h
index 9147565..1b9ed12 100644
--- a/arch/arm/mach-keystone/memory.h
+++ b/arch/arm/mach-keystone/memory.h
@@ -6,9 +6,6 @@
#ifndef __MEMORY_H
#define __MEMORY_H
-#define MAX_PHYSMEM_BITS 36
-#define SECTION_SIZE_BITS 34
-
#define KEYSTONE_LOW_PHYS_START 0x80000000ULL
#define KEYSTONE_LOW_PHYS_SIZE 0x80000000ULL /* 2G */
#define KEYSTONE_LOW_PHYS_END (KEYSTONE_LOW_PHYS_START + \
diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c
index c810e23..673fcf3 100644
--- a/arch/arm/mach-keystone/platsmp.c
+++ b/arch/arm/mach-keystone/platsmp.c
@@ -12,11 +12,11 @@
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/io.h>
+#include <linux/pgtable.h>
#include <asm/smp_plat.h>
#include <asm/prom.h>
#include <asm/tlbflush.h>
-#include <asm/pgtable.h>
#include "keystone.h"
diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
index f6f102f..e6e9f93 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -9,7 +9,7 @@
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <linux/of.h>
-#include <linux/clk-provider.h>
+#include <linux/of_clk.h>
#include <linux/clocksource.h>
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 01f0f4b..75034fe 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -9,7 +9,6 @@
select CACHE_L2X0
select PINCTRL
select PINCTRL_MESON
- select COMMON_CLK
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 0440109..0dd9992 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -1,13 +1,13 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_MMP
- bool "Marvell PXA168/910/MMP2"
+ bool "Marvell PXA168/910/MMP2/MMP3"
depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
select GPIO_PXA
select GPIOLIB
select PINCTRL
select PLAT_PXA
help
- Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
+ Support for Marvell's PXA168/PXA910(MMP), MMP2, and MMP3 processor lines.
if ARCH_MMP
@@ -110,7 +110,6 @@
depends on ARCH_MULTI_V5
select PINCTRL
select PINCTRL_SINGLE
- select COMMON_CLK
select ARCH_HAS_RESET_CONTROLLER
select CPU_MOHAWK
help
@@ -125,10 +124,30 @@
select PINCTRL_SINGLE
select ARCH_HAS_RESET_CONTROLLER
select CPU_PJ4
+ select PM_GENERIC_DOMAINS if PM
+ select PM_GENERIC_DOMAINS_OF if PM && OF
help
Include support for Marvell MMP2 based platforms using
the device tree.
+config MACH_MMP3_DT
+ bool "Support MMP3 (ARMv7) platforms"
+ depends on ARCH_MULTI_V7
+ select ARM_GIC
+ select HAVE_ARM_SCU if SMP
+ select HAVE_ARM_TWD if SMP
+ select CACHE_L2X0
+ select PINCTRL
+ select PINCTRL_SINGLE
+ select ARCH_HAS_RESET_CONTROLLER
+ select CPU_PJ4B
+ select PM_GENERIC_DOMAINS if PM
+ select PM_GENERIC_DOMAINS_OF if PM && OF
+ help
+ Say 'Y' here if you want to include support for platforms
+ with Marvell MMP3 processor, also known as PXA2128 or
+ Armada 620.
+
endmenu
config CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 8f267c7..e3758f7 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -12,16 +12,13 @@
obj-$(CONFIG_CPU_MMP2) += mmp2.o
obj-$(CONFIG_MMP_SRAM) += sram.o
-ifeq ($(CONFIG_COMMON_CLK), )
-obj-y += clock.o
-obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o
-obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o
-obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o
-endif
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
endif
+ifeq ($(CONFIG_SMP),y)
+obj-$(CONFIG_MACH_MMP3_DT) += platsmp.o
+endif
# board support
obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
@@ -34,5 +31,6 @@
obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o
obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o
+obj-$(CONFIG_MACH_MMP3_DT) += mmp3.o
obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
obj-$(CONFIG_MACH_GPLUGD) += gplugd.o
diff --git a/arch/arm/mach-mmp/addr-map.h b/arch/arm/mach-mmp/addr-map.h
index 25edf6a..3dc2f0b 100644
--- a/arch/arm/mach-mmp/addr-map.h
+++ b/arch/arm/mach-mmp/addr-map.h
@@ -20,6 +20,10 @@
#define AXI_VIRT_BASE IOMEM(0xfe200000)
#define AXI_PHYS_SIZE 0x00200000
+#define PGU_PHYS_BASE 0xe0000000
+#define PGU_VIRT_BASE IOMEM(0xfe400000)
+#define PGU_PHYS_SIZE 0x00100000
+
/* Static Memory Controller - Chip Select 0 and 1 */
#define SMC_CS0_PHYS_BASE 0x80000000
#define SMC_CS0_PHYS_SIZE 0x10000000
@@ -38,4 +42,7 @@
#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00)
#define CIU_REG(x) (CIU_VIRT_BASE + (x))
+#define SCU_VIRT_BASE (PGU_VIRT_BASE)
+#define SCU_REG(x) (SCU_VIRT_BASE + (x))
+
#endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c
deleted file mode 100644
index 7536398..0000000
--- a/arch/arm/mach-mmp/clock-mmp2.c
+++ /dev/null
@@ -1,114 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clk/mmp.h>
-
-#include "addr-map.h"
-
-#include "common.h"
-#include "clock.h"
-
-/*
- * APB Clock register offsets for MMP2
- */
-#define APBC_RTC APBC_REG(0x000)
-#define APBC_TWSI1 APBC_REG(0x004)
-#define APBC_TWSI2 APBC_REG(0x008)
-#define APBC_TWSI3 APBC_REG(0x00c)
-#define APBC_TWSI4 APBC_REG(0x010)
-#define APBC_KPC APBC_REG(0x018)
-#define APBC_UART1 APBC_REG(0x02c)
-#define APBC_UART2 APBC_REG(0x030)
-#define APBC_UART3 APBC_REG(0x034)
-#define APBC_GPIO APBC_REG(0x038)
-#define APBC_PWM0 APBC_REG(0x03c)
-#define APBC_PWM1 APBC_REG(0x040)
-#define APBC_PWM2 APBC_REG(0x044)
-#define APBC_PWM3 APBC_REG(0x048)
-#define APBC_SSP0 APBC_REG(0x04c)
-#define APBC_SSP1 APBC_REG(0x050)
-#define APBC_SSP2 APBC_REG(0x054)
-#define APBC_SSP3 APBC_REG(0x058)
-#define APBC_SSP4 APBC_REG(0x05c)
-#define APBC_SSP5 APBC_REG(0x060)
-#define APBC_TWSI5 APBC_REG(0x07c)
-#define APBC_TWSI6 APBC_REG(0x080)
-#define APBC_UART4 APBC_REG(0x088)
-
-#define APMU_USB APMU_REG(0x05c)
-#define APMU_NAND APMU_REG(0x060)
-#define APMU_SDH0 APMU_REG(0x054)
-#define APMU_SDH1 APMU_REG(0x058)
-#define APMU_SDH2 APMU_REG(0x0e8)
-#define APMU_SDH3 APMU_REG(0x0ec)
-
-static void sdhc_clk_enable(struct clk *clk)
-{
- uint32_t clk_rst;
-
- clk_rst = __raw_readl(clk->clk_rst);
- clk_rst |= clk->enable_val;
- __raw_writel(clk_rst, clk->clk_rst);
-}
-
-static void sdhc_clk_disable(struct clk *clk)
-{
- uint32_t clk_rst;
-
- clk_rst = __raw_readl(clk->clk_rst);
- clk_rst &= ~clk->enable_val;
- __raw_writel(clk_rst, clk->clk_rst);
-}
-
-struct clkops sdhc_clk_ops = {
- .enable = sdhc_clk_enable,
- .disable = sdhc_clk_disable,
-};
-
-/* APB peripheral clocks */
-static APBC_CLK(uart1, UART1, 1, 26000000);
-static APBC_CLK(uart2, UART2, 1, 26000000);
-static APBC_CLK(uart3, UART3, 1, 26000000);
-static APBC_CLK(uart4, UART4, 1, 26000000);
-static APBC_CLK(twsi1, TWSI1, 0, 26000000);
-static APBC_CLK(twsi2, TWSI2, 0, 26000000);
-static APBC_CLK(twsi3, TWSI3, 0, 26000000);
-static APBC_CLK(twsi4, TWSI4, 0, 26000000);
-static APBC_CLK(twsi5, TWSI5, 0, 26000000);
-static APBC_CLK(twsi6, TWSI6, 0, 26000000);
-static APBC_CLK(gpio, GPIO, 0, 26000000);
-
-static APMU_CLK(nand, NAND, 0xbf, 100000000);
-static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
-
-static struct clk_lookup mmp2_clkregs[] = {
- INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
- INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
- INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
- INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
- INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
- INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
- INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
- INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
- INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
- INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
- INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
- INIT_CLKREG(&clk_gpio, "mmp2-gpio", NULL),
- INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
-};
-
-void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
- phys_addr_t apbc_phys)
-{
- clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
-}
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
deleted file mode 100644
index 2d4a5d9..0000000
--- a/arch/arm/mach-mmp/clock-pxa168.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clk/mmp.h>
-
-#include "addr-map.h"
-
-#include "common.h"
-#include "clock.h"
-
-/*
- * APB clock register offsets for PXA168
- */
-#define APBC_UART1 APBC_REG(0x000)
-#define APBC_UART2 APBC_REG(0x004)
-#define APBC_GPIO APBC_REG(0x008)
-#define APBC_PWM1 APBC_REG(0x00c)
-#define APBC_PWM2 APBC_REG(0x010)
-#define APBC_PWM3 APBC_REG(0x014)
-#define APBC_PWM4 APBC_REG(0x018)
-#define APBC_RTC APBC_REG(0x028)
-#define APBC_TWSI0 APBC_REG(0x02c)
-#define APBC_KPC APBC_REG(0x030)
-#define APBC_TWSI1 APBC_REG(0x06c)
-#define APBC_UART3 APBC_REG(0x070)
-#define APBC_SSP1 APBC_REG(0x81c)
-#define APBC_SSP2 APBC_REG(0x820)
-#define APBC_SSP3 APBC_REG(0x84c)
-#define APBC_SSP4 APBC_REG(0x858)
-#define APBC_SSP5 APBC_REG(0x85c)
-
-#define APMU_NAND APMU_REG(0x060)
-#define APMU_LCD APMU_REG(0x04c)
-#define APMU_ETH APMU_REG(0x0fc)
-#define APMU_USB APMU_REG(0x05c)
-
-/* APB peripheral clocks */
-static APBC_CLK(uart1, UART1, 1, 14745600);
-static APBC_CLK(uart2, UART2, 1, 14745600);
-static APBC_CLK(uart3, UART3, 1, 14745600);
-static APBC_CLK(twsi0, TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PWM4, 1, 13000000);
-static APBC_CLK(ssp1, SSP1, 4, 0);
-static APBC_CLK(ssp2, SSP2, 4, 0);
-static APBC_CLK(ssp3, SSP3, 4, 0);
-static APBC_CLK(ssp4, SSP4, 4, 0);
-static APBC_CLK(ssp5, SSP5, 4, 0);
-static APBC_CLK(gpio, GPIO, 0, 13000000);
-static APBC_CLK(keypad, KPC, 0, 32000);
-static APBC_CLK(rtc, RTC, 8, 32768);
-
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(lcd, LCD, 0x7f, 312000000);
-static APMU_CLK(eth, ETH, 0x09, 0);
-static APMU_CLK(usb, USB, 0x12, 0);
-
-/* device and clock bindings */
-static struct clk_lookup pxa168_clkregs[] = {
- INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
- INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
- INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
- INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
- INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
- INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
- INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
- INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
- INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
- INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
- INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
- INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
- INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
- INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
- INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
- INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
- INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL),
- INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
- INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
- INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
- INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
-
-void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
- phys_addr_t apbc_phys)
-{
- clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
-}
diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c
deleted file mode 100644
index 3cd83ff..0000000
--- a/arch/arm/mach-mmp/clock-pxa910.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clk/mmp.h>
-
-#include "addr-map.h"
-
-#include "common.h"
-#include "clock.h"
-
-/*
- * APB Clock register offsets for PXA910
- */
-#define APBC_UART0 APBC_REG(0x000)
-#define APBC_UART1 APBC_REG(0x004)
-#define APBC_GPIO APBC_REG(0x008)
-#define APBC_PWM1 APBC_REG(0x00c)
-#define APBC_PWM2 APBC_REG(0x010)
-#define APBC_PWM3 APBC_REG(0x014)
-#define APBC_PWM4 APBC_REG(0x018)
-#define APBC_SSP1 APBC_REG(0x01c)
-#define APBC_SSP2 APBC_REG(0x020)
-#define APBC_RTC APBC_REG(0x028)
-#define APBC_TWSI0 APBC_REG(0x02c)
-#define APBC_KPC APBC_REG(0x030)
-#define APBC_SSP3 APBC_REG(0x04c)
-#define APBC_TWSI1 APBC_REG(0x06c)
-
-#define APMU_NAND APMU_REG(0x060)
-#define APMU_USB APMU_REG(0x05c)
-
-static APBC_CLK(uart1, UART0, 1, 14745600);
-static APBC_CLK(uart2, UART1, 1, 14745600);
-static APBC_CLK(twsi0, TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PWM4, 1, 13000000);
-static APBC_CLK(gpio, GPIO, 0, 13000000);
-static APBC_CLK(rtc, RTC, 8, 32768);
-
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(u2o, USB, 0x1b, 480000000);
-
-/* device and clock bindings */
-static struct clk_lookup pxa910_clkregs[] = {
- INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
- INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
- INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
- INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
- INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
- INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
- INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
- INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
- INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
- INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL),
- INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
- INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
-
-void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
- phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
-{
- clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
-}
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
deleted file mode 100644
index 291fe41..0000000
--- a/arch/arm/mach-mmp/clock.c
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-mmp/clock.c
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include "regs-apbc.h"
-#include "clock.h"
-
-static void apbc_clk_enable(struct clk *clk)
-{
- uint32_t clk_rst;
-
- clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel);
- __raw_writel(clk_rst, clk->clk_rst);
-}
-
-static void apbc_clk_disable(struct clk *clk)
-{
- __raw_writel(0, clk->clk_rst);
-}
-
-struct clkops apbc_clk_ops = {
- .enable = apbc_clk_enable,
- .disable = apbc_clk_disable,
-};
-
-static void apmu_clk_enable(struct clk *clk)
-{
- __raw_writel(clk->enable_val, clk->clk_rst);
-}
-
-static void apmu_clk_disable(struct clk *clk)
-{
- __raw_writel(0, clk->clk_rst);
-}
-
-struct clkops apmu_clk_ops = {
- .enable = apmu_clk_enable,
- .disable = apmu_clk_disable,
-};
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-int clk_enable(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clocks_lock, flags);
- if (clk->enabled++ == 0)
- clk->ops->enable(clk);
- spin_unlock_irqrestore(&clocks_lock, flags);
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- unsigned long flags;
-
- if (!clk)
- return;
-
- WARN_ON(clk->enabled == 0);
-
- spin_lock_irqsave(&clocks_lock, flags);
- if (--clk->enabled == 0)
- clk->ops->disable(clk);
- spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long rate;
-
- if (clk->ops->getrate)
- rate = clk->ops->getrate(clk);
- else
- rate = clk->rate;
-
- return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- int ret = -EINVAL;
-
- if (clk->ops->setrate) {
- spin_lock_irqsave(&clocks_lock, flags);
- ret = clk->ops->setrate(clk, rate);
- spin_unlock_irqrestore(&clocks_lock, flags);
- }
-
- return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
deleted file mode 100644
index 0256c89..0000000
--- a/arch/arm/mach-mmp/clock.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <linux/clkdev.h>
-
-struct clkops {
- void (*enable)(struct clk *);
- void (*disable)(struct clk *);
- unsigned long (*getrate)(struct clk *);
- int (*setrate)(struct clk *, unsigned long);
-};
-
-struct clk {
- const struct clkops *ops;
-
- void __iomem *clk_rst; /* clock reset control register */
- int fnclksel; /* functional clock select (APBC) */
- uint32_t enable_val; /* value for clock enable (APMU) */
- unsigned long rate;
- int enabled;
-};
-
-extern struct clkops apbc_clk_ops;
-extern struct clkops apmu_clk_ops;
-
-#define APBC_CLK(_name, _reg, _fnclksel, _rate) \
-struct clk clk_##_name = { \
- .clk_rst = APBC_##_reg, \
- .fnclksel = _fnclksel, \
- .rate = _rate, \
- .ops = &apbc_clk_ops, \
-}
-
-#define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \
-struct clk clk_##_name = { \
- .clk_rst = APBC_##_reg, \
- .fnclksel = _fnclksel, \
- .rate = _rate, \
- .ops = _ops, \
-}
-
-#define APMU_CLK(_name, _reg, _eval, _rate) \
-struct clk clk_##_name = { \
- .clk_rst = APMU_##_reg, \
- .enable_val = _eval, \
- .rate = _rate, \
- .ops = &apmu_clk_ops, \
-}
-
-#define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \
-struct clk clk_##_name = { \
- .clk_rst = APMU_##_reg, \
- .enable_val = _eval, \
- .rate = _rate, \
- .ops = _ops, \
-}
-
-#define INIT_CLKREG(_clk, _devname, _conname) \
- { \
- .clk = _clk, \
- .dev_id = _devname, \
- .con_id = _conname, \
- }
-
-extern struct clk clk_pxa168_gpio;
-extern struct clk clk_pxa168_timers;
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 6684abc..e94349d 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -13,11 +13,11 @@
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include "addr-map.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
#include "common.h"
-#define MMP_CHIPID (AXI_VIRT_BASE + 0x82c00)
+#define MMP_CHIPID CIU_REG(0x00)
unsigned int mmp_chip_id;
EXPORT_SYMBOL(mmp_chip_id);
@@ -36,6 +36,15 @@
},
};
+static struct map_desc mmp2_io_desc[] __initdata = {
+ {
+ .pfn = __phys_to_pfn(PGU_PHYS_BASE),
+ .virtual = (unsigned long)PGU_VIRT_BASE,
+ .length = PGU_PHYS_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
void __init mmp_map_io(void)
{
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
@@ -44,6 +53,12 @@
mmp_chip_id = __raw_readl(MMP_CHIPID);
}
+void __init mmp2_map_io(void)
+{
+ mmp_map_io();
+ iotable_init(mmp2_io_desc, ARRAY_SIZE(mmp2_io_desc));
+}
+
void mmp_restart(enum reboot_mode mode, const char *cmd)
{
soft_restart(0);
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 483b8b6..ed56b3f 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -5,4 +5,5 @@
extern void mmp_timer_init(int irq, unsigned long rate);
extern void __init mmp_map_io(void);
+extern void __init mmp2_map_io(void);
extern void mmp_restart(enum reboot_mode, const char *);
diff --git a/arch/arm/mach-mmp/cputype.h b/arch/arm/mach-mmp/cputype.h
deleted file mode 100644
index a96abcf..0000000
--- a/arch/arm/mach-mmp/cputype.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_MACH_CPUTYPE_H
-#define __ASM_MACH_CPUTYPE_H
-
-#include <asm/cputype.h>
-
-/*
- * CPU Stepping CPU_ID CHIP_ID
- *
- * PXA168 S0 0x56158400 0x0000C910
- * PXA168 A0 0x56158400 0x00A0A168
- * PXA910 Y1 0x56158400 0x00F2C920
- * PXA910 A0 0x56158400 0x00F2C910
- * PXA910 A1 0x56158400 0x00A0C910
- * PXA920 Y0 0x56158400 0x00F2C920
- * PXA920 A0 0x56158400 0x00A0C920
- * PXA920 A1 0x56158400 0x00A1C920
- * MMP2 Z0 0x560f5811 0x00F00410
- * MMP2 Z1 0x560f5811 0x00E00410
- * MMP2 A0 0x560f5811 0x00A0A610
- */
-
-extern unsigned int mmp_chip_id;
-
-#ifdef CONFIG_CPU_PXA168
-static inline int cpu_is_pxa168(void)
-{
- return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
- ((mmp_chip_id & 0xfff) == 0x168);
-}
-#else
-#define cpu_is_pxa168() (0)
-#endif
-
-/* cpu_is_pxa910() is shared on both pxa910 and pxa920 */
-#ifdef CONFIG_CPU_PXA910
-static inline int cpu_is_pxa910(void)
-{
- return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
- (((mmp_chip_id & 0xfff) == 0x910) ||
- ((mmp_chip_id & 0xfff) == 0x920));
-}
-#else
-#define cpu_is_pxa910() (0)
-#endif
-
-#if defined(CONFIG_CPU_MMP2) || defined(CONFIG_MACH_MMP2_DT)
-static inline int cpu_is_mmp2(void)
-{
- return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&
- (((mmp_chip_id & 0xfff) == 0x410) ||
- ((mmp_chip_id & 0xfff) == 0x610));
-}
-#else
-#define cpu_is_mmp2() (0)
-#endif
-
-#endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
index 130c1a6..18bee66 100644
--- a/arch/arm/mach-mmp/devices.c
+++ b/arch/arm/mach-mmp/devices.c
@@ -11,7 +11,7 @@
#include <asm/irq.h>
#include "irqs.h"
#include "devices.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
#include "regs-usb.h"
int __init pxa_register_device(struct pxa_device_desc *desc,
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index 3555979..3f43c08 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -8,15 +8,14 @@
#include <linux/irqchip.h>
#include <linux/of_platform.h>
-#include <linux/clk-provider.h>
+#include <linux/of_clk.h>
+#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/hardware/cache-tauros2.h>
#include "common.h"
-extern void __init mmp_dt_init_timer(void);
-
static const char *const pxa168_dt_board_compat[] __initconst = {
"mrvl,pxa168-aspenite",
NULL,
@@ -32,8 +31,8 @@
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init(0);
#endif
- mmp_dt_init_timer();
of_clk_init(NULL);
+ timer_probe();
}
DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index 305a9da..34a5fe4 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -9,22 +9,21 @@
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/of_platform.h>
-#include <linux/clk-provider.h>
+#include <linux/of_clk.h>
+#include <linux/clocksource.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/hardware/cache-tauros2.h>
#include "common.h"
-extern void __init mmp_dt_init_timer(void);
-
static void __init mmp_init_time(void)
{
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init(0);
#endif
of_clk_init(NULL);
- mmp_dt_init_timer();
+ timer_probe();
}
static const char *const mmp2_dt_board_compat[] __initconst = {
@@ -33,7 +32,7 @@
};
DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
- .map_io = mmp_map_io,
+ .map_io = mmp2_map_io,
.init_time = mmp_init_time,
.dt_compat = mmp2_dt_board_compat,
MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 18ea3e1..bbc4c22 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -20,7 +20,7 @@
#include <asm/mach/time.h>
#include "addr-map.h"
#include "regs-apbc.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
#include "irqs.h"
#include "mfp.h"
#include "devices.h"
diff --git a/arch/arm/mach-mmp/mmp3.c b/arch/arm/mach-mmp/mmp3.c
new file mode 100644
index 0000000..b0e8696
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp3.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Marvell MMP3 aka PXA2128 aka 88AP2128 support
+ *
+ * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include "common.h"
+
+static const char *const mmp3_dt_board_compat[] __initconst = {
+ "marvell,mmp3",
+ NULL,
+};
+
+DT_MACHINE_START(MMP2_DT, "Marvell MMP3")
+ .map_io = mmp2_map_io,
+ .dt_compat = mmp3_dt_board_compat,
+ .l2c_aux_val = 1 << L310_AUX_CTRL_FWA_SHIFT |
+ L310_AUX_CTRL_DATA_PREFETCH |
+ L310_AUX_CTRL_INSTR_PREFETCH,
+ .l2c_aux_mask = 0xc20fffff,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/platsmp.c b/arch/arm/mach-mmp/platsmp.c
new file mode 100644
index 0000000..c994054
--- /dev/null
+++ b/arch/arm/mach-mmp/platsmp.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
+ */
+#include <linux/io.h>
+#include <asm/smp_scu.h>
+#include <asm/smp.h>
+#include "addr-map.h"
+
+#define SW_BRANCH_VIRT_ADDR CIU_REG(0x24)
+
+static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ /*
+ * Apparently, the boot ROM on the second core spins on this
+ * register becoming non-zero and then jumps to the address written
+ * there. No IPIs involved.
+ */
+ __raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR);
+ return 0;
+}
+
+static void mmp3_smp_prepare_cpus(unsigned int max_cpus)
+{
+ scu_enable(SCU_VIRT_BASE);
+}
+
+static const struct smp_operations mmp3_smp_ops __initconst = {
+ .smp_prepare_cpus = mmp3_smp_prepare_cpus,
+ .smp_boot_secondary = mmp3_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp", &mmp3_smp_ops);
diff --git a/arch/arm/mach-mmp/pm-mmp2.c b/arch/arm/mach-mmp/pm-mmp2.c
index 2923dd5..7a6f74c 100644
--- a/arch/arm/mach-mmp/pm-mmp2.c
+++ b/arch/arm/mach-mmp/pm-mmp2.c
@@ -17,7 +17,7 @@
#include <linux/interrupt.h>
#include <asm/mach-types.h>
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
#include "addr-map.h"
#include "pm-mmp2.h"
#include "regs-icu.h"
@@ -123,19 +123,19 @@
case POWER_MODE_SYS_SLEEP:
apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */
apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */
- /* fall through */
+ fallthrough;
case POWER_MODE_CHIP_SLEEP:
apcr |= MPMU_PCR_PJ_SLPEN;
- /* fall through */
+ fallthrough;
case POWER_MODE_APPS_SLEEP:
apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */
- /* fall through */
+ fallthrough;
case POWER_MODE_APPS_IDLE:
apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */
apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */
idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN; /* PJ power down */
apcr |= MPMU_PCR_PJ_SPSD;
- /* fall through */
+ fallthrough;
case POWER_MODE_CORE_EXTIDLE:
idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE; /* set the IDLE bit */
idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK;
diff --git a/arch/arm/mach-mmp/pm-pxa910.c b/arch/arm/mach-mmp/pm-pxa910.c
index 58535ce..1d71d73 100644
--- a/arch/arm/mach-mmp/pm-pxa910.c
+++ b/arch/arm/mach-mmp/pm-pxa910.c
@@ -18,7 +18,7 @@
#include <asm/mach-types.h>
#include <asm/outercache.h>
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
#include "addr-map.h"
#include "pm-pxa910.h"
#include "regs-icu.h"
@@ -145,23 +145,23 @@
case POWER_MODE_UDR:
/* only shutdown APB in UDR */
apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD;
- /* fall through */
+ fallthrough;
case POWER_MODE_SYS_SLEEP:
apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */
apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */
- /* fall through */
+ fallthrough;
case POWER_MODE_APPS_SLEEP:
apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */
- /* fall through */
+ fallthrough;
case POWER_MODE_APPS_IDLE:
apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */
- /* fall through */
+ fallthrough;
case POWER_MODE_CORE_EXTIDLE:
idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE;
idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN;
idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3)
| APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3);
- /* fall through */
+ fallthrough;
case POWER_MODE_CORE_INTIDLE:
break;
}
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 6e02774..1e93892 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -19,9 +19,8 @@
#include <asm/system_misc.h>
#include "addr-map.h"
-#include "clock.h"
#include "common.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
#include "devices.h"
#include "irqs.h"
#include "mfp.h"
diff --git a/arch/arm/mach-mmp/pxa168.h b/arch/arm/mach-mmp/pxa168.h
index 0331c58..dff651b 100644
--- a/arch/arm/mach-mmp/pxa168.h
+++ b/arch/arm/mach-mmp/pxa168.h
@@ -17,9 +17,9 @@
#include <linux/platform_data/keypad-pxa27x.h>
#include <linux/pxa168_eth.h>
#include <linux/platform_data/mv_usb.h>
+#include <linux/soc/mmp/cputype.h>
#include "devices.h"
-#include "cputype.h"
extern struct pxa_device_desc pxa168_device_uart1;
extern struct pxa_device_desc pxa168_device_uart2;
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index cba31c7..b19a069 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -18,7 +18,7 @@
#include <asm/mach/time.h>
#include "addr-map.h"
#include "regs-apbc.h"
-#include "cputype.h"
+#include <linux/soc/mmp/cputype.h>
#include "irqs.h"
#include "mfp.h"
#include "devices.h"
diff --git a/arch/arm/mach-mmp/regs-usb.h b/arch/arm/mach-mmp/regs-usb.h
index d9f08c1..ed0d1aa 100644
--- a/arch/arm/mach-mmp/regs-usb.h
+++ b/arch/arm/mach-mmp/regs-usb.h
@@ -121,100 +121,6 @@
#define UTMI_OTG_ADDON_OTG_ON (1 << 0)
-/* For MMP3 USB Phy */
-#define USB2_PLL_REG0 0x4
-#define USB2_PLL_REG1 0x8
-#define USB2_TX_REG0 0x10
-#define USB2_TX_REG1 0x14
-#define USB2_TX_REG2 0x18
-#define USB2_RX_REG0 0x20
-#define USB2_RX_REG1 0x24
-#define USB2_RX_REG2 0x28
-#define USB2_ANA_REG0 0x30
-#define USB2_ANA_REG1 0x34
-#define USB2_ANA_REG2 0x38
-#define USB2_DIG_REG0 0x3C
-#define USB2_DIG_REG1 0x40
-#define USB2_DIG_REG2 0x44
-#define USB2_DIG_REG3 0x48
-#define USB2_TEST_REG0 0x4C
-#define USB2_TEST_REG1 0x50
-#define USB2_TEST_REG2 0x54
-#define USB2_CHARGER_REG0 0x58
-#define USB2_OTG_REG0 0x5C
-#define USB2_PHY_MON0 0x60
-#define USB2_RESETVE_REG0 0x64
-#define USB2_ICID_REG0 0x78
-#define USB2_ICID_REG1 0x7C
-
-/* USB2_PLL_REG0 */
-/* This is for Ax stepping */
-#define USB2_PLL_FBDIV_SHIFT_MMP3 0
-#define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0)
-
-#define USB2_PLL_REFDIV_SHIFT_MMP3 8
-#define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8)
-
-#define USB2_PLL_VDD12_SHIFT_MMP3 12
-#define USB2_PLL_VDD18_SHIFT_MMP3 14
-
-/* This is for B0 stepping */
-#define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0
-#define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9
-#define USB2_PLL_VDD18_SHIFT_MMP3_B0 14
-#define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF
-#define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00
-
-#define USB2_PLL_CAL12_SHIFT_MMP3 0
-#define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0)
-
-#define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2
-
-#define USB2_PLL_KVCO_SHIFT_MMP3 4
-#define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4)
-
-#define USB2_PLL_ICP_SHIFT_MMP3 8
-#define USB2_PLL_ICP_MASK_MMP3 (0x7<<8)
-
-#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12
-
-#define USB2_PLL_PU_PLL_SHIFT_MMP3 13
-#define USB2_PLL_PU_PLL_MASK (0x1 << 13)
-
-#define USB2_PLL_READY_MASK_MMP3 (0x1 << 15)
-
-/* USB2_TX_REG0 */
-#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8
-#define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8)
-
-#define USB2_TX_RCAL_START_SHIFT_MMP3 13
-
-/* USB2_TX_REG1 */
-#define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0
-#define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0)
-
-#define USB2_TX_AMP_SHIFT_MMP3 4
-#define USB2_TX_AMP_MASK_MMP3 (0x7 << 4)
-
-#define USB2_TX_VDD12_SHIFT_MMP3 8
-#define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8)
-
-/* USB2_TX_REG2 */
-#define USB2_TX_DRV_SLEWRATE_SHIFT 10
-
-/* USB2_RX_REG0 */
-#define USB2_RX_SQ_THRESH_SHIFT_MMP3 4
-#define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4)
-
-#define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10
-#define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10)
-
-/* USB2_ANA_REG1*/
-#define USB2_ANA_PU_ANA_SHIFT_MMP3 14
-
-/* USB2_OTG_REG0 */
-#define USB2_OTG_PU_OTG_SHIFT_MMP3 3
-
/* fsic registers */
#define FSIC_MISC 0x4
#define FSIC_INT 0x28
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 483df32..41b2e8a 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -33,8 +33,7 @@
#include "regs-timers.h"
#include "regs-apbc.h"
#include "irqs.h"
-#include "cputype.h"
-#include "clock.h"
+#include <linux/soc/mmp/cputype.h>
#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
@@ -155,7 +154,8 @@
__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
- ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
+ ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
+ (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
__raw_writel(ccr, mmp_timer_base + TMR_CCR);
@@ -174,13 +174,6 @@
__raw_writel(0x2, mmp_timer_base + TMR_CER);
}
-static struct irqaction timer_irq = {
- .name = "timer",
- .flags = IRQF_TIMER | IRQF_IRQPOLL,
- .handler = timer_interrupt,
- .dev_id = &ckevt,
-};
-
void __init mmp_timer_init(int irq, unsigned long rate)
{
timer_config();
@@ -189,37 +182,26 @@
ckevt.cpumask = cpumask_of(0);
- setup_irq(irq, &timer_irq);
+ if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
+ "timer", &ckevt))
+ pr_err("Failed to request irq %d (timer)\n", irq);
clocksource_register_hz(&cksrc, rate);
clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
}
-#ifdef CONFIG_OF
-static const struct of_device_id mmp_timer_dt_ids[] = {
- { .compatible = "mrvl,mmp-timer", },
- {}
-};
-
-void __init mmp_dt_init_timer(void)
+static int __init mmp_dt_init_timer(struct device_node *np)
{
- struct device_node *np;
struct clk *clk;
int irq, ret;
unsigned long rate;
- np = of_find_matching_node(NULL, mmp_timer_dt_ids);
- if (!np) {
- ret = -ENODEV;
- goto out;
- }
-
clk = of_clk_get(np, 0);
if (!IS_ERR(clk)) {
ret = clk_prepare_enable(clk);
if (ret)
- goto out;
- rate = clk_get_rate(clk) / 2;
+ return ret;
+ rate = clk_get_rate(clk);
} else if (cpu_is_pj4()) {
rate = 6500000;
} else {
@@ -227,18 +209,15 @@
}
irq = irq_of_parse_and_map(np, 0);
- if (!irq) {
- ret = -EINVAL;
- goto out;
- }
+ if (!irq)
+ return -EINVAL;
+
mmp_timer_base = of_iomap(np, 0);
- if (!mmp_timer_base) {
- ret = -ENOMEM;
- goto out;
- }
+ if (!mmp_timer_base)
+ return -ENOMEM;
+
mmp_timer_init(irq, rate);
- return;
-out:
- pr_err("Failed to get timer from device tree with error:%d\n", ret);
+ return 0;
}
-#endif
+
+TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer);
diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig
new file mode 100644
index 0000000..576d1ab
--- /dev/null
+++ b/arch/arm/mach-mstar/Kconfig
@@ -0,0 +1,27 @@
+menuconfig ARCH_MSTARV7
+ bool "MStar/Sigmastar Armv7 SoC Support"
+ depends on ARCH_MULTI_V7
+ select ARM_GIC
+ select ARM_HEAVY_MB
+ select MST_IRQ
+ help
+ Support for newer MStar/Sigmastar SoC families that are
+ based on Armv7 cores like the Cortex A7 and share the same
+ basic hardware like the infinity and mercury series.
+
+if ARCH_MSTARV7
+
+config MACH_INFINITY
+ bool "MStar/Sigmastar infinity SoC support"
+ default ARCH_MSTARV7
+ help
+ Support for MStar/Sigmastar infinity IP camera SoCs.
+
+config MACH_MERCURY
+ bool "MStar/Sigmastar mercury SoC support"
+ default ARCH_MSTARV7
+ help
+ Support for MStar/Sigmastar mercury dash camera SoCs.
+ Note that older Mercury2 SoCs are ARM9 based and not supported.
+
+endif
diff --git a/arch/arm/mach-mstar/Makefile b/arch/arm/mach-mstar/Makefile
new file mode 100644
index 0000000..93b0391
--- /dev/null
+++ b/arch/arm/mach-mstar/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_MSTARV7) += mstarv7.o
diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c
new file mode 100644
index 0000000..81a4cbc
--- /dev/null
+++ b/arch/arm/mach-mstar/mstarv7.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree support for MStar/Sigmastar Armv7 SoCs
+ *
+ * Copyright (c) 2020 thingy.jp
+ * Author: Daniel Palmer <daniel@thingy.jp>
+ */
+
+#include <linux/init.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+/*
+ * In the u-boot code the area these registers are in is
+ * called "L3 bridge" and there are register descriptions
+ * for something in the same area called "AXI".
+ *
+ * It's not exactly known what this is but the vendor code
+ * for both u-boot and linux share calls to "flush the miu pipe".
+ * This seems to be to force pending CPU writes to memory so that
+ * the state is right before DMA capable devices try to read
+ * descriptors and data the CPU has prepared. Without doing this
+ * ethernet doesn't work reliably for example.
+ */
+
+#define MSTARV7_L3BRIDGE_FLUSH 0x14
+#define MSTARV7_L3BRIDGE_STATUS 0x40
+#define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0)
+#define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12)
+
+static void __iomem *l3bridge;
+
+static const char * const mstarv7_board_dt_compat[] __initconst = {
+ "mstar,infinity",
+ "mstar,infinity3",
+ "mstar,mercury5",
+ NULL,
+};
+
+/*
+ * This may need locking to deal with situations where an interrupt
+ * happens while we are in here and mb() gets called by the interrupt handler.
+ *
+ * The vendor code did have a spin lock but it doesn't seem to be needed and
+ * removing it hasn't caused any side effects so far.
+ *
+ * [writel|readl]_relaxed have to be used here because otherwise
+ * we'd end up right back in here.
+ */
+static void mstarv7_mb(void)
+{
+ /* toggle the flush miu pipe fire bit */
+ writel_relaxed(0, l3bridge + MSTARV7_L3BRIDGE_FLUSH);
+ writel_relaxed(MSTARV7_L3BRIDGE_FLUSH_TRIGGER, l3bridge
+ + MSTARV7_L3BRIDGE_FLUSH);
+ while (!(readl_relaxed(l3bridge + MSTARV7_L3BRIDGE_STATUS)
+ & MSTARV7_L3BRIDGE_STATUS_DONE)) {
+ /* wait for flush to complete */
+ }
+}
+
+static void __init mstarv7_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "mstar,l3bridge");
+ l3bridge = of_iomap(np, 0);
+ if (l3bridge)
+ soc_mb = mstarv7_mb;
+ else
+ pr_warn("Failed to install memory barrier, DMA will be broken!\n");
+}
+
+DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)")
+ .dt_compat = mstarv7_board_dt_compat,
+ .init_machine = mstarv7_init,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 7a5629b..34dbeaa 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -47,7 +47,6 @@
select ARMADA_375_CLK
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
- select HAVE_SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_375
help
@@ -66,7 +65,6 @@
select ARMADA_38X_CLK
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
- select HAVE_SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_38X
help
@@ -82,7 +80,6 @@
select CACHE_L2X0
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
- select HAVE_SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_39X
help
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 8f8748a..49e3c8d 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -25,7 +25,7 @@
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/smp.h>
-#include <linux/dma-mapping.h>
+#include <linux/dma-map-ops.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mbus.h>
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 2d962fe..a3a64bf 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -35,13 +35,8 @@
/*
* MMU is disabled, use the physical address of the coherency
- * base address. However, if the coherency fabric isn't mapped
- * (i.e its virtual address is zero), it means coherency is
- * not enabled, so we return 0.
+ * base address, (or 0x0 if the coherency fabric is not mapped)
*/
- ldr r1, =coherency_base
- cmp r1, #0
- beq 2f
adr r1, 3f
ldr r3, [r1]
ldr r1, [r1, r3]
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 2a17dc1..9536b8f 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -4,30 +4,25 @@
menu "TI OMAP1 specific features"
comment "OMAP Core Type"
- depends on ARCH_OMAP1
config ARCH_OMAP730
- depends on ARCH_OMAP1
bool "OMAP730 Based System"
select ARCH_OMAP_OTG
select CPU_ARM926T
select OMAP_MPU_TIMER
config ARCH_OMAP850
- depends on ARCH_OMAP1
bool "OMAP850 Based System"
select ARCH_OMAP_OTG
select CPU_ARM926T
config ARCH_OMAP15XX
- depends on ARCH_OMAP1
default y
bool "OMAP15xx Based System"
select CPU_ARM925T
select OMAP_MPU_TIMER
config ARCH_OMAP16XX
- depends on ARCH_OMAP1
bool "OMAP16xx Based System"
select ARCH_OMAP_OTG
select CPU_ARM926T
@@ -35,7 +30,6 @@
config OMAP_MUX
bool "OMAP multiplexing support"
- depends on ARCH_OMAP
default y
help
Pin multiplexing support for OMAP boards. If your bootloader
@@ -60,25 +54,24 @@
printed, it's safe to deselect OMAP_MUX for your product.
comment "OMAP Board Type"
- depends on ARCH_OMAP1
config MACH_OMAP_INNOVATOR
bool "TI Innovator"
- depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
+ depends on ARCH_OMAP15XX || ARCH_OMAP16XX
help
TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
have such a board.
config MACH_OMAP_H2
bool "TI H2 Support"
- depends on ARCH_OMAP1 && ARCH_OMAP16XX
+ depends on ARCH_OMAP16XX
help
TI OMAP 1610/1611B H2 board support. Say Y here if you have such
a board.
config MACH_OMAP_H3
bool "TI H3 Support"
- depends on ARCH_OMAP1 && ARCH_OMAP16XX
+ depends on ARCH_OMAP16XX
help
TI OMAP 1710 H3 board support. Say Y here if you have such
a board.
@@ -91,7 +84,7 @@
config MACH_OMAP_OSK
bool "TI OSK Support"
- depends on ARCH_OMAP1 && ARCH_OMAP16XX
+ depends on ARCH_OMAP16XX
help
TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here
if you have such a board.
@@ -106,21 +99,21 @@
config MACH_OMAP_PERSEUS2
bool "TI Perseus2"
- depends on ARCH_OMAP1 && ARCH_OMAP730
+ depends on ARCH_OMAP730
help
Support for TI OMAP 730 Perseus2 board. Say Y here if you have such
a board.
config MACH_OMAP_FSAMPLE
bool "TI F-Sample"
- depends on ARCH_OMAP1 && ARCH_OMAP730
+ depends on ARCH_OMAP730
help
Support for TI OMAP 850 F-Sample board. Say Y here if you have such
a board.
config MACH_OMAP_PALMTE
bool "Palm Tungsten E"
- depends on ARCH_OMAP1 && ARCH_OMAP15XX
+ depends on ARCH_OMAP15XX
help
Support for the Palm Tungsten E PDA. To boot the kernel, you'll
need a PalmOS compatible bootloader; check out
@@ -129,7 +122,7 @@
config MACH_OMAP_PALMZ71
bool "Palm Zire71"
- depends on ARCH_OMAP1 && ARCH_OMAP15XX
+ depends on ARCH_OMAP15XX
help
Support for the Palm Zire71 PDA. To boot the kernel,
you'll need a PalmOS compatible bootloader; check out
@@ -138,7 +131,7 @@
config MACH_OMAP_PALMTT
bool "Palm Tungsten|T"
- depends on ARCH_OMAP1 && ARCH_OMAP15XX
+ depends on ARCH_OMAP15XX
help
Support for the Palm Tungsten|T PDA. To boot the kernel, you'll
need a PalmOS compatible bootloader (Garux); check out
@@ -147,26 +140,26 @@
config MACH_SX1
bool "Siemens SX1"
- depends on ARCH_OMAP1 && ARCH_OMAP15XX
+ depends on ARCH_OMAP15XX
select I2C
help
Support for the Siemens SX1 phone. To boot the kernel,
you'll need a SX1 compatible bootloader; check out
http://forum.oslik.ru and
- http://www.handhelds.org/moin/moin.cgi/SiemensSX1
+ https://www.handhelds.org/moin/moin.cgi/SiemensSX1
for more information.
Say Y here if you have such a phone, say NO otherwise.
config MACH_NOKIA770
bool "Nokia 770"
- depends on ARCH_OMAP1 && ARCH_OMAP16XX
+ depends on ARCH_OMAP16XX
help
Support for the Nokia 770 Internet Tablet. Say Y here if you
have such a device.
config MACH_AMS_DELTA
bool "Amstrad E3 (Delta)"
- depends on ARCH_OMAP1 && ARCH_OMAP15XX
+ depends on ARCH_OMAP15XX
select FIQ
select GPIO_GENERIC_PLATFORM
select LEDS_GPIO_REGISTER
@@ -178,7 +171,7 @@
config MACH_OMAP_GENERIC
bool "Generic OMAP board"
- depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
+ depends on ARCH_OMAP15XX || ARCH_OMAP16XX
help
Support for generic OMAP-1510, 1610 or 1710 board with
no FPGA. Can be used as template for porting Linux to
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index 0254eb9..4eea3e3 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -110,7 +110,7 @@
/*
* FIQ handler takes full control over serio data and clk GPIO
- * pins. Initiaize them and keep requested so nobody can
+ * pins. Initialize them and keep requested so nobody can
* interfere. Fail if any of those two couldn't be requested.
*/
switch (i) {
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index a2aa7a1..1026a81 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -17,6 +17,8 @@
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/leds.h>
+#include <linux/mtd/nand-gpio.h>
+#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/regulator/fixed.h>
@@ -27,8 +29,6 @@
#include <linux/io.h>
#include <linux/platform_data/gpio-omap.h>
-#include <media/soc_camera.h>
-
#include <asm/serial.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -38,7 +38,6 @@
#include <mach/mux.h>
#include <mach/hardware.h>
-#include "camera.h"
#include <mach/usb.h>
#include "ams-delta-fiq.h"
@@ -294,9 +293,42 @@
static struct modem_private_data modem_priv;
+/*
+ * Define partitions for flash device
+ */
+
+static struct mtd_partition partition_info[] = {
+ { .name = "Kernel",
+ .offset = 0,
+ .size = 3 * SZ_1M + SZ_512K },
+ { .name = "u-boot",
+ .offset = 3 * SZ_1M + SZ_512K,
+ .size = SZ_256K },
+ { .name = "u-boot params",
+ .offset = 3 * SZ_1M + SZ_512K + SZ_256K,
+ .size = SZ_256K },
+ { .name = "Amstrad LDR",
+ .offset = 4 * SZ_1M,
+ .size = SZ_256K },
+ { .name = "File system",
+ .offset = 4 * SZ_1M + 1 * SZ_256K,
+ .size = 27 * SZ_1M },
+ { .name = "PBL reserved",
+ .offset = 32 * SZ_1M - 3 * SZ_256K,
+ .size = 3 * SZ_256K },
+};
+
+static struct gpio_nand_platdata nand_platdata = {
+ .parts = partition_info,
+ .num_parts = ARRAY_SIZE(partition_info),
+};
+
static struct platform_device ams_delta_nand_device = {
.name = "ams-delta-nand",
.id = -1,
+ .dev = {
+ .platform_data = &nand_platdata,
+ },
};
#define OMAP_GPIO_LABEL "gpio-0-15"
@@ -306,10 +338,14 @@
.table = {
GPIO_LOOKUP(OMAP_GPIO_LABEL, AMS_DELTA_GPIO_PIN_NAND_RB, "rdy",
0),
- GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NCE, "nce", 0),
- GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NRE, "nre", 0),
- GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWP, "nwp", 0),
- GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWE, "nwe", 0),
+ GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NCE, "nce",
+ GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NRE, "nre",
+ GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWP, "nwp",
+ GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_NWE, "nwe",
+ GPIO_ACTIVE_LOW),
GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_ALE, "ale", 0),
GPIO_LOOKUP(LATCH2_LABEL, LATCH2_PIN_NAND_CLE, "cle", 0),
GPIO_LOOKUP_IDX(OMAP_MPUIO_LABEL, 0, "data", 0, 0),
@@ -420,51 +456,10 @@
},
};
-static struct i2c_board_info ams_delta_camera_board_info[] = {
- {
- I2C_BOARD_INFO("ov6650", 0x60),
- },
-};
-
#ifdef CONFIG_LEDS_TRIGGERS
DEFINE_LED_TRIGGER(ams_delta_camera_led_trigger);
-
-static int ams_delta_camera_power(struct device *dev, int power)
-{
- /*
- * turn on camera LED
- */
- if (power)
- led_trigger_event(ams_delta_camera_led_trigger, LED_FULL);
- else
- led_trigger_event(ams_delta_camera_led_trigger, LED_OFF);
- return 0;
-}
-#else
-#define ams_delta_camera_power NULL
#endif
-static struct soc_camera_link ams_delta_iclink = {
- .bus_id = 0, /* OMAP1 SoC camera bus */
- .i2c_adapter_id = 1,
- .board_info = &ams_delta_camera_board_info[0],
- .module_name = "ov6650",
- .power = ams_delta_camera_power,
-};
-
-static struct platform_device ams_delta_camera_device = {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &ams_delta_iclink,
- },
-};
-
-static struct omap1_cam_platform_data ams_delta_camera_platform_data = {
- .camexclk_khz = 12000, /* default 12MHz clock, no extra DPLL */
- .lclk_khz_max = 1334, /* results in 5fps CIF, 10fps QCIF */
-};
-
static struct platform_device ams_delta_audio_device = {
.name = "ams-delta-audio",
.id = -1,
@@ -559,7 +554,6 @@
&latch1_gpio_device,
&latch2_gpio_device,
&ams_delta_kp_device,
- &ams_delta_camera_device,
&ams_delta_audio_device,
&ams_delta_serio_device,
&ams_delta_nand_device,
@@ -711,7 +705,6 @@
omap_register_i2c_bus(1, 100, NULL, 0);
omap1_usb_init(&ams_delta_usb_config);
- omap1_set_camera_info(&ams_delta_camera_platform_data);
#ifdef CONFIG_LEDS_TRIGGERS
led_trigger_register_simple("ams_delta_camera",
&ams_delta_camera_led_trigger);
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 4df15e6..0a4c9b0 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -26,6 +26,7 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/gpio.h>
+#include <linux/gpio/machine.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
@@ -55,6 +56,9 @@
#include "common.h"
+/* Name of the GPIO chip used by the OMAP for GPIOs 0..15 */
+#define OMAP_GPIO_LABEL "gpio-0-15"
+
/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
#define OMAP_OSK_ETHR_START 0x04800300
@@ -199,6 +203,8 @@
*/
gpio_request(OSK_TPS_GPIO_USB_PWR_EN, "n_vbus_en");
gpio_direction_output(OSK_TPS_GPIO_USB_PWR_EN, 1);
+ /* Free the GPIO again as the driver will request it */
+ gpio_free(OSK_TPS_GPIO_USB_PWR_EN);
/* Set GPIO 2 high so LED D3 is off by default */
tps65010_set_gpio_out_value(GPIO2, HIGH);
@@ -240,7 +246,9 @@
static struct i2c_board_info __initdata osk_i2c_board_info[] = {
{
+ /* This device will get the name "i2c-tps65010" */
I2C_BOARD_INFO("tps65010", 0x48),
+ .dev_name = "tps65010",
.platform_data = &tps_board,
},
@@ -278,6 +286,16 @@
irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
}
+static struct gpiod_lookup_table osk_usb_gpio_table = {
+ .dev_id = "ohci",
+ .table = {
+ /* Power GPIO on the I2C-attached TPS65010 */
+ GPIO_LOOKUP("tps65010", 0, "power", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP(OMAP_GPIO_LABEL, 9, "overcurrent",
+ GPIO_ACTIVE_HIGH),
+ },
+};
+
static struct omap_usb_config osk_usb_config __initdata = {
/* has usb host connector (A) ... for development it can also
* be used, with a NONSTANDARD gender-bending cable/dongle, as
@@ -581,6 +599,7 @@
l |= (3 << 1);
omap_writel(l, USB_TRANSCEIVER_CTRL);
+ gpiod_add_lookup_table(&osk_usb_gpio_table);
omap1_usb_init(&osk_usb_config);
/* irq for tps65010 chip */
diff --git a/arch/arm/mach-omap1/camera.h b/arch/arm/mach-omap1/camera.h
deleted file mode 100644
index 8018f41..0000000
--- a/arch/arm/mach-omap1/camera.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARCH_CAMERA_H_
-#define __ASM_ARCH_CAMERA_H_
-
-#include <linux/platform_data/media/omap1_camera.h>
-
-void omap1_camera_init(void *);
-
-static inline void omap1_set_camera_info(struct omap1_cam_platform_data *info)
-{
- omap1_camera_init(info);
-}
-
-#endif /* __ASM_ARCH_CAMERA_H_ */
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 3c4900a..eb0f09e 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -21,7 +21,6 @@
#include <mach/mux.h>
#include <mach/omap7xx.h>
-#include "camera.h"
#include <mach/hardware.h>
#include "common.h"
@@ -258,48 +257,6 @@
}
#endif
-
-#define OMAP1_CAMERA_BASE 0xfffb6800
-#define OMAP1_CAMERA_IOSIZE 0x1c
-
-static struct resource omap1_camera_resources[] = {
- [0] = {
- .start = OMAP1_CAMERA_BASE,
- .end = OMAP1_CAMERA_BASE + OMAP1_CAMERA_IOSIZE - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = INT_CAMERA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 omap1_camera_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device omap1_camera_device = {
- .name = "omap1-camera",
- .id = 0, /* This is used to put cameras on this interface */
- .dev = {
- .dma_mask = &omap1_camera_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(omap1_camera_resources),
- .resource = omap1_camera_resources,
-};
-
-void __init omap1_camera_init(void *info)
-{
- struct platform_device *dev = &omap1_camera_device;
- int ret;
-
- dev->dev.platform_data = info;
-
- ret = platform_device_register(dev);
- if (ret)
- dev_err(&dev->dev, "unable to register device: %d\n", ret);
-}
-
-
/*-------------------------------------------------------------------------*/
static inline void omap_init_sti(void) {}
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 0ad8bdc..2bf659f 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -10,7 +10,7 @@
* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Converted DMA library into platform driver
* - G, Manjunath Kondaiah <manjugk@ti.com>
*/
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 312a092..3ec08bd 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -1,7 +1,7 @@
/*
* OMAP15xx specific gpio init
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Author:
* Charulatha V <charu@ti.com>
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 5b7a29b..500cfd4 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -1,7 +1,7 @@
/*
* OMAP16xx specific gpio init
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Author:
* Charulatha V <charu@ti.com>
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 0e5f68d..aeb81c1 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -1,7 +1,7 @@
/*
* OMAP7xx specific gpio init
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Author:
* Charulatha V <charu@ti.com>
diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h
index 1142560..36bc000 100644
--- a/arch/arm/mach-omap1/include/mach/memory.h
+++ b/arch/arm/mach-omap1/include/mach/memory.h
@@ -14,42 +14,11 @@
* OMAP-1510 bus address is translated into a Local Bus address if the
* OMAP bus type is lbus. We do the address translation based on the
* device overriding the defaults used in the dma-mapping API.
- * Note that the is_lbus_device() test is not very efficient on 1510
- * because of the strncmp().
*/
-#if defined(CONFIG_ARCH_OMAP15XX) && !defined(__ASSEMBLER__)
/*
* OMAP-1510 Local Bus address offset
*/
#define OMAP1510_LB_OFFSET UL(0x30000000)
-#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
-#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
-#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
-
-#define __arch_pfn_to_dma(dev, pfn) \
- ({ dma_addr_t __dma = __pfn_to_phys(pfn); \
- if (is_lbus_device(dev)) \
- __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
- __dma; })
-
-#define __arch_dma_to_pfn(dev, addr) \
- ({ dma_addr_t __dma = addr; \
- if (is_lbus_device(dev)) \
- __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \
- __phys_to_pfn(__dma); \
- })
-
-#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
- lbus_to_virt(addr) : \
- __phys_to_virt(addr)); })
-
-#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
- (dma_addr_t) (is_lbus_device(dev) ? \
- virt_to_lbus(__addr) : \
- __virt_to_phys(__addr)); })
-
-#endif /* CONFIG_ARCH_OMAP15XX */
-
#endif
diff --git a/arch/arm/mach-omap1/include/mach/mux.h b/arch/arm/mach-omap1/include/mach/mux.h
index adfe1f6..3f6dc55 100644
--- a/arch/arm/mach-omap1/include/mach/mux.h
+++ b/arch/arm/mach-omap1/include/mach/mux.h
@@ -88,7 +88,7 @@
* OMAP730/850 has a slightly different config for the pin mux.
* - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and
* not the FUNC_MUX_CTRL_x regs from hardware.h
- * - for pull-up/down, only has one enable bit which is is in the same register
+ * - for pull-up/down, only has one enable bit which is in the same register
* as mux config
*/
#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 2c1e2b3..a745d64 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -655,9 +655,13 @@
irq = INT_7XX_WAKE_UP_REQ;
else if (cpu_is_omap16xx())
irq = INT_1610_WAKE_UP_REQ;
- if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup",
- NULL))
- pr_err("Failed to request irq %d (peripheral wakeup)\n", irq);
+ else
+ irq = -1;
+
+ if (irq >= 0) {
+ if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup", NULL))
+ pr_err("Failed to request irq %d (peripheral wakeup)\n", irq);
+ }
/* Program new power ramp-up time
* (0 for most boards since we don't lower voltage when in deep sleep)
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 4447210..97fc209 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -6,7 +6,7 @@
* device model. It also has a low level function to change the timer
* input clock source.
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
* Tarun Kanti DebBarma <tarun.kanti@ti.com>
* Thara Gopinath <thara@ti.com>
*
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index d8e9bbd..ba85662 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -9,6 +9,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <asm/irq.h>
@@ -542,6 +543,25 @@
/* ULPD_APLL_CTRL */
#define APLL_NDPLL_SWITCH (1 << 0)
+static int omap_1510_usb_ohci_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct device *dev = data;
+
+ if (event != BUS_NOTIFY_ADD_DEVICE)
+ return NOTIFY_DONE;
+
+ if (strncmp(dev_name(dev), "ohci", 4) == 0 &&
+ dma_direct_set_offset(dev, PHYS_OFFSET, OMAP1510_LB_OFFSET,
+ (u64)-1))
+ WARN_ONCE(1, "failed to set DMA offset\n");
+ return NOTIFY_OK;
+}
+
+static struct notifier_block omap_1510_usb_ohci_nb = {
+ .notifier_call = omap_1510_usb_ohci_notifier,
+};
+
static void __init omap_1510_usb_init(struct omap_usb_config *config)
{
unsigned int val;
@@ -600,6 +620,8 @@
if (config->register_host) {
int status;
+ bus_register_notifier(&platform_bus_type,
+ &omap_1510_usb_ohci_nb);
ohci_device.dev.platform_data = config;
status = platform_device_register(&ohci_device);
if (status)
diff --git a/arch/arm/mach-omap2/.gitignore b/arch/arm/mach-omap2/.gitignore
index 79a8d6e..dc7be75 100644
--- a/arch/arm/mach-omap2/.gitignore
+++ b/arch/arm/mach-omap2/.gitignore
@@ -1 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
pm-asm-offsets.h
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index fdb6743..3f62a0c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -66,7 +66,6 @@
select ARCH_OMAP2PLUS
select ARM_GIC
select MACH_OMAP_GENERIC
- select MIGHT_HAVE_CACHE_L2X0
select HAVE_ARM_SCU
select GENERIC_CLOCKEVENTS_BROADCAST
select HAVE_ARM_TWD
@@ -95,6 +94,7 @@
bool
select ARCH_HAS_BANDGAP
select ARCH_HAS_HOLES_MEMORYMODEL
+ select ARCH_HAS_RESET_CONTROLLER
select ARCH_OMAP
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
@@ -105,6 +105,9 @@
select OMAP_DM_TIMER
select OMAP_GPMC
select PINCTRL
+ select PM_GENERIC_DOMAINS if PM
+ select PM_GENERIC_DOMAINS_OF if PM
+ select RESET_CONTROLLER
select SOC_BUS
select TI_SYSC
select OMAP_IRQCHIP
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8f20819..732e614 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -7,7 +7,7 @@
-I$(srctree)/arch/arm/plat-omap/include
# Common support
-obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \
+obj-y := id.o io.o control.o devices.o fb.o pm.o \
common.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
omap_device.o omap-headsmp.o sram.o
@@ -19,8 +19,8 @@
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
-obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common)
-obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
@@ -29,6 +29,11 @@
endif
obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
+
+ifneq ($(CONFIG_MFD_CPCAP),)
+obj-y += pmic-cpcap.o
+endif
+
obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
# SMP support ONLY available for OMAP4
@@ -41,6 +46,10 @@
obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o
+omap5-dra7-common-$(CONFIG_SOC_HAS_REALTIME_COUNTER) = timer.o
+obj-$(CONFIG_SOC_OMAP5) += $(omap5-dra7-common-y)
+obj-$(CONFIG_SOC_DRA7XX) += $(omap5-dra7-common-y)
+
# Functions loaded to SRAM
obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
@@ -216,9 +225,6 @@
# Platform specific device init code
-omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
-obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
-
obj-y += omap_phy_internal.o
obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index 5eef093..bf2b5f8 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -1,7 +1,7 @@
/*
* This file contains the address info for various AM33XX modules.
*
- * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments, Inc. - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index ad512f0..1610c56 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -3,7 +3,7 @@
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* Modified from the original mach-omap/omap2/board-generic.c did by Paul
* to support the OMAP2+ device tree boards with an unique board file.
@@ -12,6 +12,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/irqdomain.h>
+#include <linux/clocksource.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
@@ -31,6 +32,20 @@
omap_soc_device_init();
}
+/* Clocks are needed early, see drivers/clocksource for the rest */
+static void __init __maybe_unused omap_init_time_of(void)
+{
+ omap_clk_init();
+ timer_probe();
+}
+
+/* Used by am437x for ARM timer in non-SMP configurations */
+#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
+void tick_broadcast(const struct cpumask *mask)
+{
+}
+#endif
+
#ifdef CONFIG_SOC_OMAP2420
static const char *const omap242x_boards_compat[] __initconst = {
"ti,omap2420",
@@ -42,7 +57,7 @@
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_machine = omap_generic_init,
- .init_time = omap_init_time,
+ .init_time = omap_init_time_of,
.dt_compat = omap242x_boards_compat,
.restart = omap2xxx_restart,
MACHINE_END
@@ -59,7 +74,7 @@
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_machine = omap_generic_init,
- .init_time = omap_init_time,
+ .init_time = omap_init_time_of,
.dt_compat = omap243x_boards_compat,
.restart = omap2xxx_restart,
MACHINE_END
@@ -106,7 +121,7 @@
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
- .init_time = omap_init_time,
+ .init_time = omap_init_time_of,
.dt_compat = n900_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@@ -124,7 +139,7 @@
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
- .init_time = omap_init_time,
+ .init_time = omap_init_time_of,
.dt_compat = omap3_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@@ -141,7 +156,7 @@
.init_early = omap3630_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
- .init_time = omap_init_time,
+ .init_time = omap_init_time_of,
.dt_compat = omap36xx_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@@ -158,7 +173,7 @@
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
- .init_time = omap3_secure_sync32k_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = omap3_gp_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@@ -174,7 +189,7 @@
.init_early = am35xx_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = am3517_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@@ -193,7 +208,7 @@
.init_early = ti814x_init_early,
.init_machine = omap_generic_init,
.init_late = ti81xx_init_late,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = ti814x_boards_compat,
.restart = ti81xx_restart,
MACHINE_END
@@ -210,7 +225,7 @@
.init_early = ti816x_init_early,
.init_machine = omap_generic_init,
.init_late = ti81xx_init_late,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = ti816x_boards_compat,
.restart = ti81xx_restart,
MACHINE_END
@@ -228,7 +243,7 @@
.init_early = am33xx_init_early,
.init_machine = omap_generic_init,
.init_late = am33xx_init_late,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = am33xx_boards_compat,
.restart = am33xx_restart,
MACHINE_END
@@ -253,7 +268,7 @@
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
.init_late = omap4430_init_late,
- .init_time = omap4_local_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = omap4_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
@@ -300,7 +315,7 @@
.init_late = am43xx_init_late,
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = am43_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
@@ -327,7 +342,7 @@
.init_late = dra7xx_init_late,
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap5_realtime_timer_init,
.dt_compat = dra74x_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
@@ -350,7 +365,7 @@
.init_late = dra7xx_init_late,
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap5_realtime_timer_init,
.dt_compat = dra72x_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index f98c8ec..dedd47e 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -1147,7 +1147,21 @@
/* Clockdomain-to-clock/hwmod framework interface code */
-static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
+/**
+ * clkdm_clk_enable - add an enabled downstream clock to this clkdm
+ * @clkdm: struct clockdomain *
+ * @clk: struct clk * of the enabled downstream clock
+ *
+ * Increment the usecount of the clockdomain @clkdm and ensure that it
+ * is awake before @clk is enabled. Intended to be called by
+ * clk_enable() code. If the clockdomain is in software-supervised
+ * idle mode, force the clockdomain to wake. If the clockdomain is in
+ * hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
+ * ensure that devices in the clockdomain can be read from/written to
+ * by on-chip processors. Returns -EINVAL if passed null pointers;
+ * returns 0 upon success or if the clockdomain is in hwsup idle mode.
+ */
+int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *unused)
{
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
return -EINVAL;
@@ -1175,33 +1189,6 @@
}
/**
- * clkdm_clk_enable - add an enabled downstream clock to this clkdm
- * @clkdm: struct clockdomain *
- * @clk: struct clk * of the enabled downstream clock
- *
- * Increment the usecount of the clockdomain @clkdm and ensure that it
- * is awake before @clk is enabled. Intended to be called by
- * clk_enable() code. If the clockdomain is in software-supervised
- * idle mode, force the clockdomain to wake. If the clockdomain is in
- * hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
- * ensure that devices in the clockdomain can be read from/written to
- * by on-chip processors. Returns -EINVAL if passed null pointers;
- * returns 0 upon success or if the clockdomain is in hwsup idle mode.
- */
-int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
-{
- /*
- * XXX Rewrite this code to maintain a list of enabled
- * downstream clocks for debugging purposes?
- */
-
- if (!clk)
- return -EINVAL;
-
- return _clkdm_clk_hwmod_enable(clkdm);
-}
-
-/**
* clkdm_clk_disable - remove an enabled downstream clock from this clkdm
* @clkdm: struct clockdomain *
* @clk: struct clk * of the disabled downstream clock
@@ -1216,13 +1203,13 @@
*/
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
{
- if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+ if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
pwrdm_lock(clkdm->pwrdm.ptr);
/* corner case: disabling unused clocks */
- if ((__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0)
+ if (clk && (__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0)
goto ccd_exit;
if (clkdm->usecount == 0) {
@@ -1277,7 +1264,7 @@
if (!oh)
return -EINVAL;
- return _clkdm_clk_hwmod_enable(clkdm);
+ return clkdm_clk_enable(clkdm, NULL);
}
/**
@@ -1300,35 +1287,10 @@
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
- /*
- * XXX Rewrite this code to maintain a list of enabled
- * downstream hwmods for debugging purposes?
- */
-
- if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+ if (!oh)
return -EINVAL;
- pwrdm_lock(clkdm->pwrdm.ptr);
-
- if (clkdm->usecount == 0) {
- pwrdm_unlock(clkdm->pwrdm.ptr);
- WARN_ON(1); /* underflow */
- return -ERANGE;
- }
-
- clkdm->usecount--;
- if (clkdm->usecount > 0) {
- pwrdm_unlock(clkdm->pwrdm.ptr);
- return 0;
- }
-
- arch_clkdm->clkdm_clk_disable(clkdm);
- pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
- pwrdm_unlock(clkdm->pwrdm.ptr);
-
- pr_debug("clockdomain: %s: disabled\n", clkdm->name);
-
- return 0;
+ return clkdm_clk_disable(clkdm, NULL);
}
/**
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
index 32c90fd..b4d5144 100644
--- a/arch/arm/mach-omap2/clockdomains33xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
@@ -1,7 +1,7 @@
/*
* AM33XX Clock Domain data.
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* This program is free software; you can redistribute it and/or
diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c
index 751708d..c96a2b1 100644
--- a/arch/arm/mach-omap2/clockdomains43xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains43xx_data.c
@@ -84,6 +84,15 @@
.flags = CLKDM_CAN_SWSUP,
};
+static struct clockdomain lcdc_43xx_clkdm = {
+ .name = "lcdc_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_PER_INST,
+ .clkdm_offs = AM43XX_CM_PER_LCDC_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
static struct clockdomain dss_43xx_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "per_pwrdm" },
@@ -173,6 +182,7 @@
&pruss_ocp_43xx_clkdm,
&ocpwp_l3_43xx_clkdm,
&l3s_tsc_43xx_clkdm,
+ &lcdc_43xx_clkdm,
&dss_43xx_clkdm,
&l3_aon_43xx_clkdm,
&emif_43xx_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 6005c4e..8285be7 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -214,7 +214,7 @@
.dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
.wkdep_srcs = l4_secure_wkup_sleep_deps,
.sleepdep_srcs = l4_secure_wkup_sleep_deps,
- .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4_per_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
index 3ab41fc..5611e08 100644
--- a/arch/arm/mach-omap2/clockdomains54xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -170,7 +170,7 @@
.dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT,
.wkdep_srcs = l4sec_wkup_sleep_deps,
.sleepdep_srcs = l4sec_wkup_sleep_deps,
- .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain iva_54xx_clkdm = {
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
index 3068802..27835c4 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -606,7 +606,7 @@
.dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
.wkdep_srcs = cam_wkup_sleep_deps,
.sleepdep_srcs = cam_wkup_sleep_deps,
- .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4per_7xx_clkdm = {
diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
index 65fbd13..127dc7a 100644
--- a/arch/arm/mach-omap2/clockdomains81xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -1,7 +1,7 @@
/*
* TI81XX Clock Domain data.
*
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
*
* This program is free software; you can redistribute it and/or
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index c0823fd..e7ae2bb 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -4,7 +4,7 @@
* This file is automatically generated from the AM33XX hardware databases.
* Vaibhav Hiremath <hvaibhav@ti.com>
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h
index 44663b5..fc88688 100644
--- a/arch/arm/mach-omap2/cm-regbits-54xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54xx Clock Management register bits
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
diff --git a/arch/arm/mach-omap2/cm-regbits-7xx.h b/arch/arm/mach-omap2/cm-regbits-7xx.h
index a78ccba..2725af4 100644
--- a/arch/arm/mach-omap2/cm-regbits-7xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-7xx.h
@@ -2,7 +2,7 @@
/*
* DRA7xx Clock Management register bits
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
index 7be363a..eb86bbd 100644
--- a/arch/arm/mach-omap2/cm1_54xx.h
+++ b/arch/arm/mach-omap2/cm1_54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54xx CM1 instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
index 28660ed..aae3831 100644
--- a/arch/arm/mach-omap2/cm1_7xx.h
+++ b/arch/arm/mach-omap2/cm1_7xx.h
@@ -2,7 +2,7 @@
/*
* DRA7xx CM1 instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
index c5da1f5..8e49765 100644
--- a/arch/arm/mach-omap2/cm2_54xx.h
+++ b/arch/arm/mach-omap2/cm2_54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54xx CM2 instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index e16fc58..f873460 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -2,7 +2,7 @@
/*
* DRA7xx CM2 instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 084d454..ac4882e 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -1,7 +1,7 @@
/*
* AM33XX CM functions
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* Reference taken from from OMAP4 cminst44xx.c
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index a91f7d2..63b362b 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -1,7 +1,7 @@
/*
* AM33XX CM offset macros
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* This program is free software; you can redistribute it and/or
diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h
index 5d73a10..bd91223 100644
--- a/arch/arm/mach-omap2/cm81xx.h
+++ b/arch/arm/mach-omap2/cm81xx.h
@@ -1,7 +1,7 @@
/*
* Clock domain register offsets for TI81XX.
*
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
*
* This program is free software; you can redistribute it and/or
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 6316da3..49926ec 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -111,7 +111,14 @@
#define OMAP_L2C_AUX_CTRL 0
#define omap4_l2c310_write_sec NULL
#endif
+
+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
extern void omap5_realtime_timer_init(void);
+#else
+static inline void omap5_realtime_timer_init(void)
+{
+}
+#endif
void omap2420_init_early(void);
void omap2430_init_early(void);
@@ -255,7 +262,7 @@
extern void gic_dist_enable(void);
extern bool gic_dist_disabled(void);
extern void gic_timer_retrigger(void);
-extern void omap_smc1(u32 fn, u32 arg);
+extern void _omap_smc1(u32 fn, u32 arg);
extern void omap4_sar_ram_init(void);
extern void __iomem *omap4_get_sar_ram_base(void);
extern void omap4_mpuss_early_init(void);
@@ -345,14 +352,16 @@
}
#endif
+struct omap_system_dma_plat_info;
+
void pdata_quirks_init(const struct of_device_id *);
void omap_auxdata_legacy_init(struct device *dev);
void omap_pcs_legacy_init(int irq, void (*rearm)(void));
+extern struct omap_system_dma_plat_info dma_plat_info;
struct omap_sdrc_params;
extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1);
-struct omap2_hsmmc_info;
extern void omap_reserve(void);
struct omap_hwmod;
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index c84b5e2..73338cf 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -684,7 +684,7 @@
*
* Save the wkup domain registers
*/
-void am43xx_control_save_context(void)
+static void am43xx_control_save_context(void)
{
int i;
@@ -698,7 +698,7 @@
*
* Restore the wkup domain registers
*/
-void am43xx_control_restore_context(void)
+static void am43xx_control_restore_context(void)
{
int i;
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 393b421..eceb4b0 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -195,6 +195,7 @@
#define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243
#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246
#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB 0x24C
#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 46012ca..6098666 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -1,7 +1,7 @@
/*
* OMAP2plus display device setup / initialization.
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Senthilvadivu Guruswamy
* Sumit Semwal
*
@@ -263,9 +263,9 @@
}
r = of_platform_populate(node, NULL, NULL, &pdev->dev);
+ put_device(&pdev->dev);
if (r) {
pr_err("Unable to populate DSS submodule devices\n");
- put_device(&pdev->dev);
return r;
}
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 0c105ba..dfc9b21 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -13,7 +13,7 @@
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Converted DMA library into platform driver
* - G, Manjunath Kondaiah <manjugk@ti.com>
*/
@@ -30,10 +30,6 @@
#include <linux/omap-dma.h>
#include "soc.h"
-#include "omap_hwmod.h"
-#include "omap_device.h"
-
-static enum omap_reg_offsets dma_common_ch_end;
static const struct omap_dma_reg reg_map[] = {
[REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
@@ -81,42 +77,6 @@
[CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
};
-static void __iomem *dma_base;
-static inline void dma_write(u32 val, int reg, int lch)
-{
- void __iomem *addr = dma_base;
-
- addr += reg_map[reg].offset;
- addr += reg_map[reg].stride * lch;
-
- writel_relaxed(val, addr);
-}
-
-static inline u32 dma_read(int reg, int lch)
-{
- void __iomem *addr = dma_base;
-
- addr += reg_map[reg].offset;
- addr += reg_map[reg].stride * lch;
-
- return readl_relaxed(addr);
-}
-
-static void omap2_clear_dma(int lch)
-{
- int i;
-
- for (i = CSDP; i <= dma_common_ch_end; i += 1)
- dma_write(0, i, lch);
-}
-
-static void omap2_show_dma_caps(void)
-{
- u8 revision = dma_read(REVISION, 0) & 0xff;
- printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
- revision >> 4, revision & 0xf);
-}
-
static unsigned configure_dma_errata(void)
{
unsigned errata = 0;
@@ -211,82 +171,35 @@
{ "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
};
-static struct omap_system_dma_plat_info dma_plat_info __initdata = {
- .reg_map = reg_map,
- .channel_stride = 0x60,
- .show_dma_caps = omap2_show_dma_caps,
- .clear_dma = omap2_clear_dma,
- .dma_write = dma_write,
- .dma_read = dma_read,
+static struct omap_dma_dev_attr dma_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+ IS_CSSA_32 | IS_CDSA_32,
+ .lch_count = 32,
};
-static struct platform_device_info omap_dma_dev_info __initdata = {
- .name = "omap-dma-engine",
- .id = -1,
- .dma_mask = DMA_BIT_MASK(32),
+struct omap_system_dma_plat_info dma_plat_info = {
+ .reg_map = reg_map,
+ .channel_stride = 0x60,
+ .dma_attr = &dma_attr,
};
/* One time initializations */
-static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
+static int __init omap2_system_dma_init(void)
{
- struct platform_device *pdev;
- struct omap_system_dma_plat_info p;
- struct omap_dma_dev_attr *d;
- struct resource *mem;
- char *name = "omap_dma_system";
-
- p = dma_plat_info;
- p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
- p.errata = configure_dma_errata();
+ dma_plat_info.errata = configure_dma_errata();
if (soc_is_omap24xx()) {
/* DMA slave map for drivers not yet converted to DT */
- p.slave_map = omap24xx_sdma_dt_map;
- p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
+ dma_plat_info.slave_map = omap24xx_sdma_dt_map;
+ dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
}
- pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
- if (IS_ERR(pdev)) {
- pr_err("%s: Can't build omap_device for %s:%s.\n",
- __func__, name, oh->name);
- return PTR_ERR(pdev);
- }
+ if (!soc_is_omap242x())
+ dma_attr.dev_caps |= IS_RW_PRIORITY;
- omap_dma_dev_info.res = pdev->resource;
- omap_dma_dev_info.num_res = pdev->num_resources;
-
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!mem) {
- dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
- return -EINVAL;
- }
-
- dma_base = ioremap(mem->start, resource_size(mem));
- if (!dma_base) {
- dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
- return -ENOMEM;
- }
-
- d = oh->dev_attr;
-
- if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
- d->dev_caps |= HS_CHANNELS_RESERVED;
-
- if (platform_get_irq_byname(pdev, "0") < 0)
- d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
-
- /* Check the capabilities register for descriptor loading feature */
- if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
- dma_common_ch_end = CCDN;
- else
- dma_common_ch_end = CCFN;
+ if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+ dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
return 0;
}
-
-static int __init omap2_system_dma_init(void)
-{
- return omap_hwmod_for_each_by_class("dma",
- omap2_system_dma_init_dev, NULL);
-}
omap_arch_initcall(omap2_system_dma_init);
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
deleted file mode 100644
index 63423ea..0000000
--- a/arch/arm/mach-omap2/hsmmc.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap2/hsmmc.c
- *
- * Copyright (C) 2007-2008 Texas Instruments
- * Copyright (C) 2008 Nokia Corporation
- * Author: Texas Instruments
- */
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_data/hsmmc-omap.h>
-
-#include "soc.h"
-#include "omap_device.h"
-
-#include "hsmmc.h"
-#include "control.h"
-
-#if IS_ENABLED(CONFIG_MMC_OMAP_HS)
-
-static u16 control_pbias_offset;
-static u16 control_devconf1_offset;
-
-#define HSMMC_NAME_LEN 9
-
-static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
- struct omap_hsmmc_platform_data *mmc)
-{
- char *hc_name;
-
- hc_name = kzalloc(HSMMC_NAME_LEN + 1, GFP_KERNEL);
- if (!hc_name)
- return -ENOMEM;
-
- snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", c->mmc, 1);
- mmc->name = hc_name;
- mmc->caps = c->caps;
- mmc->reg_offset = 0;
-
- return 0;
-}
-
-static int omap_hsmmc_done;
-
-void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
-{
- struct platform_device *pdev;
- int res;
-
- if (omap_hsmmc_done)
- return;
-
- omap_hsmmc_done = 1;
-
- for (; c->mmc; c++) {
- pdev = c->pdev;
- if (!pdev)
- continue;
- res = omap_device_register(pdev);
- if (res)
- pr_err("Could not late init MMC\n");
- }
-}
-
-#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
-
-static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
- int ctrl_nr)
-{
- struct omap_hwmod *oh;
- struct omap_hwmod *ohs[1];
- struct omap_device *od;
- struct platform_device *pdev;
- char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
- struct omap_hsmmc_platform_data *mmc_data;
- struct omap_hsmmc_dev_attr *mmc_dev_attr;
- char *name;
- int res;
-
- mmc_data = kzalloc(sizeof(*mmc_data), GFP_KERNEL);
- if (!mmc_data)
- return;
-
- res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
- if (res < 0)
- goto free_mmc;
-
- name = "omap_hsmmc";
- res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
- "mmc%d", ctrl_nr);
- WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
- "String buffer overflow in MMC%d device setup\n", ctrl_nr);
-
- oh = omap_hwmod_lookup(oh_name);
- if (!oh) {
- pr_err("Could not look up %s\n", oh_name);
- goto free_name;
- }
- ohs[0] = oh;
- if (oh->dev_attr != NULL) {
- mmc_dev_attr = oh->dev_attr;
- mmc_data->controller_flags = mmc_dev_attr->flags;
- }
-
- pdev = platform_device_alloc(name, ctrl_nr - 1);
- if (!pdev) {
- pr_err("Could not allocate pdev for %s\n", name);
- goto free_name;
- }
- dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
-
- od = omap_device_alloc(pdev, ohs, 1);
- if (IS_ERR(od)) {
- pr_err("Could not allocate od for %s\n", name);
- goto put_pdev;
- }
-
- res = platform_device_add_data(pdev, mmc_data,
- sizeof(struct omap_hsmmc_platform_data));
- if (res) {
- pr_err("Could not add pdata for %s\n", name);
- goto put_pdev;
- }
-
- hsmmcinfo->pdev = pdev;
-
- res = omap_device_register(pdev);
- if (res) {
- pr_err("Could not register od for %s\n", name);
- goto free_od;
- }
-
- goto free_mmc;
-
-free_od:
- omap_device_delete(od);
-
-put_pdev:
- platform_device_put(pdev);
-
-free_name:
- kfree(mmc_data->name);
-
-free_mmc:
- kfree(mmc_data);
-}
-
-void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
-{
- if (omap_hsmmc_done)
- return;
-
- omap_hsmmc_done = 1;
-
- if (cpu_is_omap2430()) {
- control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
- control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
- } else {
- control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
- control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
- }
-
- for (; controllers->mmc; controllers++)
- omap_hsmmc_init_one(controllers, controllers->mmc);
-
-}
-
-#endif
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
deleted file mode 100644
index 76c5ed2..0000000
--- a/arch/arm/mach-omap2/hsmmc.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * MMC definitions for OMAP2
- */
-
-struct mmc_card;
-
-struct omap2_hsmmc_info {
- u8 mmc; /* controller 1/2/3 */
- u32 caps; /* 4/8 wires and any additional host
- * capabilities OR'd (ref. linux/mmc/host.h) */
- struct platform_device *pdev; /* mmc controller instance */
- /* init some special card */
- void (*init_card)(struct mmc_card *card);
-};
-
-#if IS_ENABLED(CONFIG_MMC_OMAP_HS)
-
-void omap_hsmmc_init(struct omap2_hsmmc_info *);
-void omap_hsmmc_late_init(struct omap2_hsmmc_info *);
-
-#else
-
-static inline void omap_hsmmc_init(struct omap2_hsmmc_info *info)
-{
-}
-
-static inline void omap_hsmmc_late_init(struct omap2_hsmmc_info *info)
-{
-}
-
-#endif
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 188ea52..59755b5 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -396,7 +396,6 @@
cpu_rev = "3.1";
break;
case 7:
- /* FALLTHROUGH */
default:
/* Use the latest known revision as default */
omap_revision = OMAP3430_REV_ES3_1_2;
@@ -416,7 +415,6 @@
cpu_rev = "1.0";
break;
case 1:
- /* FALLTHROUGH */
default:
omap_revision = AM35XX_REV_ES1_1;
cpu_rev = "1.1";
@@ -435,7 +433,6 @@
cpu_rev = "1.1";
break;
case 2:
- /* FALLTHROUGH */
default:
omap_revision = OMAP3630_REV_ES1_2;
cpu_rev = "1.2";
@@ -456,7 +453,6 @@
cpu_rev = "2.0";
break;
case 3:
- /* FALLTHROUGH */
default:
omap_revision = TI8168_REV_ES2_1;
cpu_rev = "2.1";
@@ -473,7 +469,6 @@
cpu_rev = "2.0";
break;
case 2:
- /* FALLTHROUGH */
default:
omap_revision = AM335X_REV_ES2_1;
cpu_rev = "2.1";
@@ -491,7 +486,6 @@
cpu_rev = "1.1";
break;
case 2:
- /* FALLTHROUGH */
default:
omap_revision = AM437X_REV_ES1_2;
cpu_rev = "1.2";
@@ -502,7 +496,6 @@
case 0xb968:
switch (rev) {
case 0:
- /* FALLTHROUGH */
case 1:
omap_revision = TI8148_REV_ES1_0;
cpu_rev = "1.0";
@@ -512,7 +505,6 @@
cpu_rev = "2.0";
break;
case 3:
- /* FALLTHROUGH */
default:
omap_revision = TI8148_REV_ES2_1;
cpu_rev = "2.1";
@@ -775,19 +767,23 @@
return kasprintf(GFP_KERNEL, "Unknown");
}
-static ssize_t omap_get_type(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t
+type_show(struct device *dev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%s\n", omap_types[omap_type()]);
}
-static struct device_attribute omap_soc_attr =
- __ATTR(type, S_IRUGO, omap_get_type, NULL);
+static DEVICE_ATTR_RO(type);
+
+static struct attribute *omap_soc_attrs[] = {
+ &dev_attr_type.attr,
+ NULL
+};
+
+ATTRIBUTE_GROUPS(omap_soc);
void __init omap_soc_device_init(void)
{
- struct device *parent;
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
@@ -798,14 +794,12 @@
soc_dev_attr->machine = soc_name;
soc_dev_attr->family = omap_get_family();
soc_dev_attr->revision = soc_rev;
+ soc_dev_attr->custom_attr_group = omap_soc_groups[0];
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr);
return;
}
-
- parent = soc_device_to_device(soc_dev);
- device_create_file(parent, &omap_soc_attr);
}
#endif /* CONFIG_SOC_BUS */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 349e480..27608d1 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -51,6 +51,7 @@
#include "prm33xx.h"
#include "prm44xx.h"
#include "opp2xxx.h"
+#include "omap-secure.h"
/*
* omap_clk_soc_init: points to a function that does the SoC-specific
@@ -481,6 +482,7 @@
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
+ omap_secure_init();
}
void __init omap3430_init_early(void)
@@ -533,6 +535,7 @@
dm814x_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = dm814x_dt_clk_init;
+ omap_secure_init();
}
void __init ti816x_init_early(void)
@@ -549,6 +552,7 @@
dm816x_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = dm816x_dt_clk_init;
+ omap_secure_init();
}
#endif
@@ -566,6 +570,7 @@
am33xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = am33xx_dt_clk_init;
+ omap_secure_init();
}
void __init am33xx_init_late(void)
@@ -589,6 +594,7 @@
omap_hwmod_init_postsetup();
omap_l2_cache_init();
omap_clk_soc_init = am43xx_dt_clk_init;
+ omap_secure_init();
}
void __init am43xx_init_late(void)
@@ -617,6 +623,7 @@
omap_hwmod_init_postsetup();
omap_l2_cache_init();
omap_clk_soc_init = omap4xxx_dt_clk_init;
+ omap_secure_init();
}
void __init omap4430_init_late(void)
@@ -643,6 +650,7 @@
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap5xxx_dt_clk_init;
+ omap_secure_init();
}
void __init omap5_init_late(void)
@@ -666,6 +674,7 @@
dra7xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = dra7xx_dt_clk_init;
+ omap_secure_init();
}
void __init dra7xx_init_late(void)
diff --git a/arch/arm/mach-omap2/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h
index c2bd8d8..6297c62 100644
--- a/arch/arm/mach-omap2/l3_2xxx.h
+++ b/arch/arm/mach-omap2/l3_2xxx.h
@@ -2,7 +2,7 @@
/*
* arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Sumit Semwal
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
diff --git a/arch/arm/mach-omap2/l3_3xxx.h b/arch/arm/mach-omap2/l3_3xxx.h
index 995ebcc..60ea7b2 100644
--- a/arch/arm/mach-omap2/l3_3xxx.h
+++ b/arch/arm/mach-omap2/l3_3xxx.h
@@ -2,7 +2,7 @@
/*
* arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Sumit Semwal
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
diff --git a/arch/arm/mach-omap2/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h
index 556e69c..418e107 100644
--- a/arch/arm/mach-omap2/l4_2xxx.h
+++ b/arch/arm/mach-omap2/l4_2xxx.h
@@ -2,7 +2,7 @@
/*
* arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Sumit Semwal
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h
index 7f4e053..b5533e9 100644
--- a/arch/arm/mach-omap2/mmc.h
+++ b/arch/arm/mach-omap2/mmc.h
@@ -16,7 +16,3 @@
return 0;
}
#endif
-
-/* called from board-specific card detection service routine */
-extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
- int is_closed);
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 78247e6..93c20bb 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -2,25 +2,33 @@
/*
* OMAP IOMMU quirks for various TI SoCs
*
- * Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2019 Texas Instruments Incorporated - https://www.ti.com/
* Suman Anna <s-anna@ti.com>
*/
#include <linux/platform_device.h>
#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/list.h>
-#include "omap_hwmod.h"
-#include "omap_device.h"
#include "clockdomain.h"
#include "powerdomain.h"
+struct pwrdm_link {
+ struct device *dev;
+ struct powerdomain *pwrdm;
+ struct list_head node;
+};
+
+static DEFINE_SPINLOCK(iommu_lock);
+static struct clockdomain *emu_clkdm;
+static atomic_t emu_count;
+
static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev,
bool enable)
{
- static struct clockdomain *emu_clkdm;
- static DEFINE_SPINLOCK(emu_lock);
- static atomic_t count;
struct device_node *np = pdev->dev.of_node;
+ unsigned long flags;
if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
return;
@@ -31,34 +39,87 @@
return;
}
- spin_lock(&emu_lock);
+ spin_lock_irqsave(&iommu_lock, flags);
- if (enable && (atomic_inc_return(&count) == 1))
+ if (enable && (atomic_inc_return(&emu_count) == 1))
clkdm_deny_idle(emu_clkdm);
- else if (!enable && (atomic_dec_return(&count) == 0))
+ else if (!enable && (atomic_dec_return(&emu_count) == 0))
clkdm_allow_idle(emu_clkdm);
- spin_unlock(&emu_lock);
+ spin_unlock_irqrestore(&iommu_lock, flags);
+}
+
+static struct powerdomain *_get_pwrdm(struct device *dev)
+{
+ struct clk *clk;
+ struct clk_hw_omap *hwclk;
+ struct clockdomain *clkdm;
+ struct powerdomain *pwrdm = NULL;
+ struct pwrdm_link *entry;
+ unsigned long flags;
+ static LIST_HEAD(cache);
+
+ spin_lock_irqsave(&iommu_lock, flags);
+
+ list_for_each_entry(entry, &cache, node) {
+ if (entry->dev == dev) {
+ pwrdm = entry->pwrdm;
+ break;
+ }
+ }
+
+ spin_unlock_irqrestore(&iommu_lock, flags);
+
+ if (pwrdm)
+ return pwrdm;
+
+ clk = of_clk_get(dev->of_node->parent, 0);
+ if (IS_ERR(clk)) {
+ dev_err(dev, "no fck found\n");
+ return NULL;
+ }
+
+ hwclk = to_clk_hw_omap(__clk_get_hw(clk));
+ clk_put(clk);
+ if (!hwclk || !hwclk->clkdm_name) {
+ dev_err(dev, "no hwclk data\n");
+ return NULL;
+ }
+
+ clkdm = clkdm_lookup(hwclk->clkdm_name);
+ if (!clkdm) {
+ dev_err(dev, "clkdm not found: %s\n", hwclk->clkdm_name);
+ return NULL;
+ }
+
+ pwrdm = clkdm_get_pwrdm(clkdm);
+ if (!pwrdm) {
+ dev_err(dev, "pwrdm not found: %s\n", clkdm->name);
+ return NULL;
+ }
+
+ entry = kmalloc(sizeof(*entry), GFP_KERNEL);
+ if (entry) {
+ entry->dev = dev;
+ entry->pwrdm = pwrdm;
+ spin_lock_irqsave(&iommu_lock, flags);
+ list_add(&entry->node, &cache);
+ spin_unlock_irqrestore(&iommu_lock, flags);
+ }
+
+ return pwrdm;
}
int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
u8 *pwrst)
{
struct powerdomain *pwrdm;
- struct omap_device *od;
u8 next_pwrst;
int ret = 0;
- od = to_omap_device(pdev);
- if (!od)
- return -ENODEV;
-
- if (od->hwmods_cnt != 1)
- return -EINVAL;
-
- pwrdm = omap_hwmod_get_pwrdm(od->hwmods[0]);
+ pwrdm = _get_pwrdm(&pdev->dev);
if (!pwrdm)
- return -EINVAL;
+ return -ENODEV;
if (request) {
*pwrst = pwrdm_read_next_pwrst(pwrdm);
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 2d8f905..9fba98c 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -42,7 +42,6 @@
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/smp_scu.h>
-#include <asm/pgalloc.h>
#include <asm/suspend.h>
#include <asm/virt.h>
#include <asm/hardware/cache-l2x0.h>
@@ -227,7 +226,6 @@
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
- unsigned int wakeup_cpu;
if (omap_rev() == OMAP4430_REV_ES1_0)
return -ENXIO;
@@ -292,7 +290,6 @@
* secure devices, CPUx does WFI which can result in
* domain transition
*/
- wakeup_cpu = smp_processor_id();
pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
pwrdm_post_transition(NULL);
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index 24298e4..0659ab4 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -5,21 +5,47 @@
* Copyright (C) 2011 Texas Instruments, Inc.
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
- * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
+ * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
*/
+#include <linux/arm-smccc.h>
+#include <linux/cpu_pm.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/memblock.h>
+#include <linux/of.h>
#include <asm/cacheflush.h>
#include <asm/memblock.h>
+#include "common.h"
#include "omap-secure.h"
+#include "soc.h"
static phys_addr_t omap_secure_memblock_base;
+bool optee_available;
+
+#define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \
+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \
+ ARM_SMCCC_OWNER_SIP, (func_num))
+
+static void __init omap_optee_init_check(void)
+{
+ struct device_node *np;
+
+ /*
+ * We only check that the OP-TEE node is present and available. The
+ * OP-TEE kernel driver is not needed for the type of interaction made
+ * with OP-TEE here so the driver's status is not checked.
+ */
+ np = of_find_node_by_path("/firmware/optee");
+ if (np && of_device_is_available(np))
+ optee_available = true;
+ of_node_put(np);
+}
+
/**
* omap_sec_dispatcher: Routine to dispatch low power secure
* service routines
@@ -53,6 +79,27 @@
return ret;
}
+void omap_smccc_smc(u32 fn, u32 arg)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg,
+ 0, 0, 0, 0, 0, 0, &res);
+ WARN(res.a0, "Secure function call 0x%08x failed\n", fn);
+}
+
+void omap_smc1(u32 fn, u32 arg)
+{
+ /*
+ * If this platform has OP-TEE installed we use ARM SMC calls
+ * otherwise fall back to the OMAP ROM style calls.
+ */
+ if (optee_available)
+ omap_smccc_smc(fn, arg);
+ else
+ _omap_smc1(fn, arg);
+}
+
/* Allocate the memory to save secure ram */
int __init omap_secure_ram_reserve_memblock(void)
{
@@ -163,3 +210,45 @@
NO_FLAG,
3, ptr, count, flag, 0);
}
+
+void __init omap_secure_init(void)
+{
+ omap_optee_init_check();
+}
+
+/*
+ * Dummy dispatcher call after core OSWR and MPU off. Updates the ROM return
+ * address after MMU has been re-enabled after CPU1 has been woken up again.
+ * Otherwise the ROM code will attempt to use the earlier physical return
+ * address that got set with MMU off when waking up CPU1. Only used on secure
+ * devices.
+ */
+static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
+{
+ switch (cmd) {
+ case CPU_CLUSTER_PM_EXIT:
+ omap_secure_dispatcher(OMAP4_PPA_SERVICE_0,
+ FLAG_START_CRITICAL,
+ 0, 0, 0, 0, 0);
+ break;
+ default:
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block secure_notifier_block = {
+ .notifier_call = cpu_notifier,
+};
+
+static int __init secure_pm_init(void)
+{
+ if (omap_type() == OMAP2_DEVICE_TYPE_GP || !soc_is_omap44xx())
+ return 0;
+
+ cpu_pm_register_notifier(&secure_notifier_block);
+
+ return 0;
+}
+omap_arch_initcall(secure_pm_init);
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 20046e8..172069f 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -5,11 +5,13 @@
* Copyright (C) 2011 Texas Instruments, Inc.
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
- * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
+ * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
*/
#ifndef OMAP_ARCH_OMAP_SECURE_H
#define OMAP_ARCH_OMAP_SECURE_H
+#include <linux/types.h>
+
/* Monitor error code */
#define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
#define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
@@ -48,9 +50,13 @@
#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
/* Secure PPA(Primary Protected Application) APIs */
+#define OMAP4_PPA_SERVICE_0 0x21
#define OMAP4_PPA_L2_POR_INDEX 0x23
#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
+#define AM43xx_PPA_SVC_PM_SUSPEND 0x71
+#define AM43xx_PPA_SVC_PM_RESUME 0x72
+
/* Secure RX-51 PPA (Primary Protected Application) APIs */
#define RX51_PPA_HWRNG 29
#define RX51_PPA_L2_INVAL 40
@@ -60,6 +66,8 @@
extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
u32 arg1, u32 arg2, u32 arg3, u32 arg4);
+extern void omap_smccc_smc(u32 fn, u32 arg);
+extern void omap_smc1(u32 fn, u32 arg);
extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
extern phys_addr_t omap_secure_ram_mempool_base(void);
@@ -72,6 +80,9 @@
extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
+extern bool optee_available;
+void omap_secure_init(void);
+
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
void set_cntfreq(void);
#else
diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S
index fd2bcd9..7376f52 100644
--- a/arch/arm/mach-omap2/omap-smc.S
+++ b/arch/arm/mach-omap2/omap-smc.S
@@ -6,7 +6,7 @@
* Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
- * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
+ * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
*/
#include <linux/linkage.h>
@@ -18,18 +18,18 @@
* the monitor API number. It uses few CPU registers
* internally and hence they need be backed up including
* link register "lr".
- * Function signature : void omap_smc1(u32 fn, u32 arg)
+ * Function signature : void _omap_smc1(u32 fn, u32 arg)
*/
.arch armv7-a
.arch_extension sec
-ENTRY(omap_smc1)
+ENTRY(_omap_smc1)
stmfd sp!, {r2-r12, lr}
mov r12, r0
mov r0, r1
dsb
smc #0
ldmfd sp!, {r2-r12, pc}
-ENDPROC(omap_smc1)
+ENDPROC(_omap_smc1)
/**
* u32 omap_smc2(u32 id, u32 falg, u32 pargs)
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 6a82fce..570a987 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -72,7 +72,7 @@
}
#ifdef CONFIG_OMAP5_ERRATA_801819
-void omap5_erratum_workaround_801819(void)
+static void omap5_erratum_workaround_801819(void)
{
u32 acr, revidr;
u32 acr_mask;
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index f85a0fd..64b23b0 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -119,11 +119,7 @@
/**
* omap_device_build_from_dt - build an omap_device with multiple hwmods
- * @pdev_name: name of the platform_device driver to use
- * @pdev_id: this platform_device's connection ID
- * @oh: ptr to the single omap_hwmod that backs this omap_device
- * @pdata: platform_data ptr to associate with the platform_device
- * @pdata_len: amount of memory pointed to by @pdata
+ * @pdev: The platform device to update.
*
* Function for building an omap_device already registered from device-tree
*
@@ -246,7 +242,7 @@
if (pdev->dev.of_node)
omap_device_build_from_dt(pdev);
omap_auxdata_legacy_init(dev);
- /* fall through */
+ fallthrough;
default:
od = to_omap_device(pdev);
if (od)
@@ -294,7 +290,7 @@
/**
* omap_device_get_context_loss_count - get lost context count
- * @od: struct omap_device *
+ * @pdev: The platform device to update.
*
* Using the primary hwmod, query the context loss count for this
* device.
@@ -323,9 +319,8 @@
/**
* omap_device_alloc - allocate an omap_device
* @pdev: platform_device that will be included in this omap_device
- * @oh: ptr to the single omap_hwmod that backs this omap_device
- * @pdata: platform_data ptr to associate with the platform_device
- * @pdata_len: amount of memory pointed to by @pdata
+ * @ohs: ptr to the omap_hwmod for this omap_device
+ * @oh_cnt: the size of the ohs list
*
* Convenience function for allocating an omap_device structure and filling
* hwmods, and resources.
@@ -380,176 +375,6 @@
kfree(od);
}
-/**
- * omap_device_copy_resources - Add legacy IO and IRQ resources
- * @oh: interconnect target module
- * @pdev: platform device to copy resources to
- *
- * We still have legacy DMA and smartreflex needing resources.
- * Let's populate what they need until we can eventually just
- * remove this function. Note that there should be no need to
- * call this from omap_device_build_from_dt(), nor should there
- * be any need to call it for other devices.
- */
-static int
-omap_device_copy_resources(struct omap_hwmod *oh,
- struct platform_device *pdev)
-{
- struct device_node *np, *child;
- struct property *prop;
- struct resource *res;
- const char *name;
- int error, irq = 0;
-
- if (!oh || !oh->od || !oh->od->pdev)
- return -EINVAL;
-
- np = oh->od->pdev->dev.of_node;
- if (!np) {
- error = -ENODEV;
- goto error;
- }
-
- res = kcalloc(2, sizeof(*res), GFP_KERNEL);
- if (!res)
- return -ENOMEM;
-
- /* Do we have a dts range for the interconnect target module? */
- error = omap_hwmod_parse_module_range(oh, np, res);
-
- /* No ranges, rely on device reg entry */
- if (error)
- error = of_address_to_resource(np, 0, res);
- if (error)
- goto free;
-
- /* SmartReflex needs first IO resource name to be "mpu" */
- res[0].name = "mpu";
-
- /*
- * We may have a configured "ti,sysc" interconnect target with a
- * dts child with the interrupt. If so use the first child's
- * first interrupt for "ti-hwmods" legacy support.
- */
- of_property_for_each_string(np, "compatible", prop, name)
- if (!strncmp("ti,sysc-", name, 8))
- break;
-
- child = of_get_next_available_child(np, NULL);
-
- if (name)
- irq = irq_of_parse_and_map(child, 0);
- if (!irq)
- irq = irq_of_parse_and_map(np, 0);
- if (!irq) {
- error = -EINVAL;
- goto free;
- }
-
- /* Legacy DMA code needs interrupt name to be "0" */
- res[1].start = irq;
- res[1].end = irq;
- res[1].flags = IORESOURCE_IRQ;
- res[1].name = "0";
-
- error = platform_device_add_resources(pdev, res, 2);
-
-free:
- kfree(res);
-
-error:
- WARN(error, "%s: %s device %s failed: %i\n",
- __func__, oh->name, dev_name(&pdev->dev),
- error);
-
- return error;
-}
-
-/**
- * omap_device_build - build and register an omap_device with one omap_hwmod
- * @pdev_name: name of the platform_device driver to use
- * @pdev_id: this platform_device's connection ID
- * @oh: ptr to the single omap_hwmod that backs this omap_device
- * @pdata: platform_data ptr to associate with the platform_device
- * @pdata_len: amount of memory pointed to by @pdata
- *
- * Convenience function for building and registering a single
- * omap_device record, which in turn builds and registers a
- * platform_device record. See omap_device_build_ss() for more
- * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
- * passes along the return value of omap_device_build_ss().
- */
-struct platform_device __init *omap_device_build(const char *pdev_name,
- int pdev_id,
- struct omap_hwmod *oh,
- void *pdata, int pdata_len)
-{
- int ret = -ENOMEM;
- struct platform_device *pdev;
- struct omap_device *od;
-
- if (!oh || !pdev_name)
- return ERR_PTR(-EINVAL);
-
- if (!pdata && pdata_len > 0)
- return ERR_PTR(-EINVAL);
-
- if (strncmp(oh->name, "smartreflex", 11) &&
- strncmp(oh->name, "dma", 3)) {
- pr_warn("%s need to update %s to probe with dt\na",
- __func__, pdev_name);
- ret = -ENODEV;
- goto odbs_exit;
- }
-
- pdev = platform_device_alloc(pdev_name, pdev_id);
- if (!pdev) {
- ret = -ENOMEM;
- goto odbs_exit;
- }
-
- /* Set the dev_name early to allow dev_xxx in omap_device_alloc */
- if (pdev->id != -1)
- dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
- else
- dev_set_name(&pdev->dev, "%s", pdev->name);
-
- /*
- * Must be called before omap_device_alloc() as oh->od
- * only contains the currently registered omap_device
- * and will get overwritten by omap_device_alloc().
- */
- ret = omap_device_copy_resources(oh, pdev);
- if (ret)
- goto odbs_exit1;
-
- od = omap_device_alloc(pdev, &oh, 1);
- if (IS_ERR(od)) {
- ret = PTR_ERR(od);
- goto odbs_exit1;
- }
-
- ret = platform_device_add_data(pdev, pdata, pdata_len);
- if (ret)
- goto odbs_exit2;
-
- ret = omap_device_register(pdev);
- if (ret)
- goto odbs_exit2;
-
- return pdev;
-
-odbs_exit2:
- omap_device_delete(od);
-odbs_exit1:
- platform_device_put(pdev);
-odbs_exit:
-
- pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
-
- return ERR_PTR(ret);
-}
-
#ifdef CONFIG_PM
static int _od_runtime_suspend(struct device *dev)
{
@@ -651,7 +476,7 @@
/**
* omap_device_register - register an omap_device with one omap_hwmod
- * @od: struct omap_device * to register
+ * @pdev: the platform device (omap_device) to register.
*
* Register the omap_device structure. This currently just calls
* platform_device_register() on the underlying platform_device.
@@ -670,7 +495,7 @@
/**
* omap_device_enable - fully activate an omap_device
- * @od: struct omap_device * to activate
+ * @pdev: the platform device to activate
*
* Do whatever is necessary for the hwmods underlying omap_device @od
* to be accessible and ready to operate. This generally involves
@@ -704,7 +529,7 @@
/**
* omap_device_idle - idle an omap_device
- * @od: struct omap_device * to idle
+ * @pdev: The platform_device (omap_device) to idle
*
* Idle omap_device @od. Device drivers call this function indirectly
* via pm_runtime_put*(). Returns -EINVAL if the omap_device is not
diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h
index ced775e..f77e76a 100644
--- a/arch/arm/mach-omap2/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -68,10 +68,6 @@
/* Core code interface */
-struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
- struct omap_hwmod *oh, void *pdata,
- int pdata_len);
-
struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_hwmod **ohs, int oh_cnt);
void omap_device_delete(struct omap_device *od);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index eb74aa1..1fd67ab 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -623,39 +623,6 @@
return 0;
}
-/**
- * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
- * @oh: struct omap_hwmod *
- *
- * Prevent the hardware module @oh to send wakeups. Returns -EINVAL
- * upon error or 0 upon success.
- */
-static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
-{
- if (!oh->class->sysc ||
- !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
- (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
- (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
- return -EINVAL;
-
- if (!oh->class->sysc->sysc_fields) {
- WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
- return -EINVAL;
- }
-
- if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
- *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
-
- if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
- _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
- if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
- _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v);
-
- /* XXX test pwrdm_get_wken for this hwmod's subsystem */
-
- return 0;
-}
-
static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
{
struct clk_hw_omap *clk;
@@ -782,8 +749,10 @@
for_each_matching_node(np, ti_clkctrl_match_table) {
ret = _setup_clkctrl_provider(np);
- if (ret)
+ if (ret) {
+ of_node_put(np);
break;
+ }
}
return ret;
@@ -1886,23 +1855,6 @@
}
/**
- * _enable_preprogram - Pre-program an IP block during the _enable() process
- * @oh: struct omap_hwmod *
- *
- * Some IP blocks (such as AESS) require some additional programming
- * after enable before they can enter idle. If a function pointer to
- * do so is present in the hwmod data, then call it and pass along the
- * return value; otherwise, return 0.
- */
-static int _enable_preprogram(struct omap_hwmod *oh)
-{
- if (!oh->class->enable_preprogram)
- return 0;
-
- return oh->class->enable_preprogram(oh);
-}
-
-/**
* _enable - enable an omap_hwmod
* @oh: struct omap_hwmod *
*
@@ -1985,7 +1937,6 @@
_update_sysc_cache(oh);
_enable_sysc(oh);
}
- r = _enable_preprogram(oh);
} else {
if (soc_ops.disable_module)
soc_ops.disable_module(oh);
@@ -3199,15 +3150,14 @@
/**
* omap_hwmod_init_regbits - init sysconfig specific register bits
* @dev: struct device
+ * @oh: module
* @data: module data
* @sysc_fields: new sysc configuration
*/
-static int omap_hwmod_init_regbits(struct device *dev,
+static int omap_hwmod_init_regbits(struct device *dev, struct omap_hwmod *oh,
const struct ti_sysc_module_data *data,
struct sysc_regbits **sysc_fields)
{
- *sysc_fields = NULL;
-
switch (data->cap->type) {
case TI_SYSC_OMAP2:
case TI_SYSC_OMAP2_TIMER:
@@ -3242,6 +3192,12 @@
*sysc_fields = &omap_hwmod_sysc_type_usb_host_fs;
break;
default:
+ *sysc_fields = NULL;
+ if (!oh->class->sysc->sysc_fields)
+ return 0;
+
+ dev_err(dev, "sysc_fields not found\n");
+
return -EINVAL;
}
@@ -3407,9 +3363,9 @@
if (!oh->class->sysc)
return -ENODEV;
- if (sysc_fields != oh->class->sysc->sysc_fields)
- dev_warn(dev, "sysc_fields %p != %p\n", sysc_fields,
- oh->class->sysc->sysc_fields);
+ if (oh->class->sysc->sysc_fields &&
+ sysc_fields != oh->class->sysc->sysc_fields)
+ dev_warn(dev, "sysc_fields mismatch\n");
if (rev_offs != oh->class->sysc->rev_offs)
dev_warn(dev, "rev_offs %08x != %08x\n", rev_offs,
@@ -3481,7 +3437,7 @@
regs = ioremap(data->module_pa,
data->module_size);
if (!regs)
- return -ENOMEM;
+ goto out_free_sysc;
}
/*
@@ -3491,13 +3447,13 @@
if (oh->class->name && strcmp(oh->class->name, data->name)) {
class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL);
if (!class)
- return -ENOMEM;
+ goto out_unmap;
}
if (list_empty(&oh->slave_ports)) {
oi = kcalloc(1, sizeof(*oi), GFP_KERNEL);
if (!oi)
- return -ENOMEM;
+ goto out_free_class;
/*
* Note that we assume interconnect interface clocks will be
@@ -3524,6 +3480,14 @@
spin_unlock_irqrestore(&oh->_lock, flags);
return 0;
+
+out_free_class:
+ kfree(class);
+out_unmap:
+ iounmap(regs);
+out_free_sysc:
+ kfree(sysc);
+ return -ENOMEM;
}
static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
@@ -3625,7 +3589,7 @@
cookie->data = oh;
- error = omap_hwmod_init_regbits(dev, data, &sysc_fields);
+ error = omap_hwmod_init_regbits(dev, oh, data, &sysc_fields);
if (error)
return error;
@@ -3656,6 +3620,8 @@
oh->flags |= HWMOD_SWSUP_SIDLE_ACT;
if (data->cfg->quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
oh->flags |= HWMOD_SWSUP_MSTANDBY;
+ if (data->cfg->quirks & SYSC_QUIRK_CLKDM_NOAUTO)
+ oh->flags |= HWMOD_CLKDM_NOAUTO;
error = omap_hwmod_check_module(dev, oh, data, sysc_fields,
rev_offs, sysc_offs, syss_offs,
@@ -3815,6 +3781,7 @@
struct omap_hwmod_ocp_if *oi;
struct clockdomain *clkdm;
struct clk_hw_omap *clk;
+ struct clk_hw *hw;
if (!oh)
return NULL;
@@ -3831,7 +3798,14 @@
c = oi->_clk;
}
- clk = to_clk_hw_omap(__clk_get_hw(c));
+ hw = __clk_get_hw(c);
+ if (!hw)
+ return NULL;
+
+ clk = to_clk_hw_omap(hw);
+ if (!clk)
+ return NULL;
+
clkdm = clk->clkdm;
if (!clkdm)
return NULL;
@@ -3868,70 +3842,6 @@
*/
/**
- * omap_hwmod_enable_wakeup - allow device to wake up the system
- * @oh: struct omap_hwmod *
- *
- * Sets the module OCP socket ENAWAKEUP bit to allow the module to
- * send wakeups to the PRCM, and enable I/O ring wakeup events for
- * this IP block if it has dynamic mux entries. Eventually this
- * should set PRCM wakeup registers to cause the PRCM to receive
- * wakeup events from the module. Does not set any wakeup routing
- * registers beyond this point - if the module is to wake up any other
- * module or subsystem, that must be set separately. Called by
- * omap_device code. Returns -EINVAL on error or 0 upon success.
- */
-int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
-{
- unsigned long flags;
- u32 v;
-
- spin_lock_irqsave(&oh->_lock, flags);
-
- if (oh->class->sysc &&
- (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
- v = oh->_sysc_cache;
- _enable_wakeup(oh, &v);
- _write_sysconfig(v, oh);
- }
-
- spin_unlock_irqrestore(&oh->_lock, flags);
-
- return 0;
-}
-
-/**
- * omap_hwmod_disable_wakeup - prevent device from waking the system
- * @oh: struct omap_hwmod *
- *
- * Clears the module OCP socket ENAWAKEUP bit to prevent the module
- * from sending wakeups to the PRCM, and disable I/O ring wakeup
- * events for this IP block if it has dynamic mux entries. Eventually
- * this should clear PRCM wakeup registers to cause the PRCM to ignore
- * wakeup events from the module. Does not set any wakeup routing
- * registers beyond this point - if the module is to wake up any other
- * module or subsystem, that must be set separately. Called by
- * omap_device code. Returns -EINVAL on error or 0 upon success.
- */
-int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
-{
- unsigned long flags;
- u32 v;
-
- spin_lock_irqsave(&oh->_lock, flags);
-
- if (oh->class->sysc &&
- (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
- v = oh->_sysc_cache;
- _disable_wakeup(oh, &v);
- _write_sysconfig(v, oh);
- }
-
- spin_unlock_irqrestore(&oh->_lock, flags);
-
- return 0;
-}
-
-/**
* omap_hwmod_assert_hardreset - assert the HW reset line of submodules
* contained in the hwmod module.
* @oh: struct omap_hwmod *
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index ef1bb08..eebf2fd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -501,7 +501,6 @@
* @sysc: device SYSCONFIG/SYSSTATUS register data
* @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
* @reset: ptr to fn to be executed in place of the standard hwmod reset fn
- * @enable_preprogram: ptr to fn to be executed during device enable
* @lock: ptr to fn to be executed to lock IP registers
* @unlock: ptr to fn to be executed to unlock IP registers
*
@@ -526,7 +525,6 @@
struct omap_hwmod_class_sysconfig *sysc;
int (*pre_shutdown)(struct omap_hwmod *oh);
int (*reset)(struct omap_hwmod *oh);
- int (*enable_preprogram)(struct omap_hwmod *oh);
void (*lock)(struct omap_hwmod *oh);
void (*unlock)(struct omap_hwmod *oh);
};
@@ -646,9 +644,6 @@
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
-int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
-int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
-
int omap_hwmod_for_each_by_class(const char *classname,
int (*fn)(struct omap_hwmod *oh,
void *user),
@@ -665,7 +660,6 @@
*
*/
-extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh);
void omap_hwmod_rtc_unlock(struct omap_hwmod *oh);
void omap_hwmod_rtc_lock(struct omap_hwmod *oh);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index d49df96..558fae4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -11,7 +11,6 @@
*/
#include <linux/platform_data/i2c-omap.h>
-#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
@@ -126,21 +125,6 @@
.flags = HWMOD_16BIT_REG,
};
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32,
- .lch_count = 32,
-};
-
-static struct omap_hwmod omap2420_dma_system_hwmod = {
- .name = "dma",
- .class = &omap2xxx_dma_hwmod_class,
- .main_clk = "core_l3_ck",
- .dev_attr = &dma_dev_attr,
- .flags = HWMOD_NO_IDLEST,
-};
-
/* mailbox */
static struct omap_hwmod omap2420_mailbox_hwmod = {
.name = "mailbox",
@@ -280,14 +264,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_timer1_hwmod,
- .clk = "gpt1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
.master = &omap2xxx_l4_wkup_hwmod,
@@ -328,22 +304,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
- .master = &omap2420_dma_system_hwmod,
- .slave = &omap2xxx_l3_main_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dma_system */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_dma_system_hwmod,
- .clk = "sdma_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
.master = &omap2xxx_l4_core_hwmod,
@@ -384,15 +344,6 @@
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
-
-/* l4_wkup -> 32ksync_counter */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_counter_32k_hwmod,
- .clk = "sync_32k_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
.master = &omap2xxx_l3_main_hwmod,
.slave = &omap2xxx_gpmc_hwmod,
@@ -414,8 +365,6 @@
&omap2420_l4_core__i2c2,
&omap2420_l3__iva,
&omap2420_l3__dsp,
- &omap2420_l4_wkup__timer1,
- &omap2xxx_l4_core__timer2,
&omap2xxx_l4_core__timer3,
&omap2xxx_l4_core__timer4,
&omap2xxx_l4_core__timer5,
@@ -435,8 +384,6 @@
&omap2420_l4_wkup__gpio2,
&omap2420_l4_wkup__gpio3,
&omap2420_l4_wkup__gpio4,
- &omap2420_dma_system__l3,
- &omap2420_l4_core__dma_system,
&omap2420_l4_core__mailbox,
&omap2420_l4_core__mcbsp1,
&omap2420_l4_core__mcbsp2,
@@ -445,7 +392,6 @@
&omap2xxx_l4_core__sham,
&omap2xxx_l4_core__aes,
&omap2420_l4_core__hdq1w,
- &omap2420_l4_wkup__counter_32k,
&omap2420_l3__gpmc,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c51ef84..c932008 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -12,7 +12,6 @@
#include <linux/platform_data/i2c-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
-#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
@@ -121,21 +120,6 @@
.class = &omap2xxx_gpio_hwmod_class,
};
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-static struct omap_hwmod omap2430_dma_system_hwmod = {
- .name = "dma",
- .class = &omap2xxx_dma_hwmod_class,
- .main_clk = "core_l3_ck",
- .dev_attr = &dma_dev_attr,
- .flags = HWMOD_NO_IDLEST,
-};
-
/* mailbox */
static struct omap_hwmod omap2430_mailbox_hwmod = {
.name = "mailbox",
@@ -452,14 +436,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_timer1_hwmod,
- .clk = "gpt1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
.master = &omap2xxx_l4_wkup_hwmod,
@@ -508,22 +484,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
- .master = &omap2430_dma_system_hwmod,
- .slave = &omap2xxx_l3_main_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dma_system */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_dma_system_hwmod,
- .clk = "sdma_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
.master = &omap2xxx_l4_core_hwmod,
@@ -580,14 +540,6 @@
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
-/* l4_wkup -> 32ksync_counter */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_counter_32k_hwmod,
- .clk = "sync_32k_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
.master = &omap2xxx_l3_main_hwmod,
.slave = &omap2xxx_gpmc_hwmod,
@@ -613,8 +565,6 @@
&omap2xxx_l4_core__mcspi2,
&omap2430_l4_core__mcspi3,
&omap2430_l3__iva,
- &omap2430_l4_wkup__timer1,
- &omap2xxx_l4_core__timer2,
&omap2xxx_l4_core__timer3,
&omap2xxx_l4_core__timer4,
&omap2xxx_l4_core__timer5,
@@ -635,8 +585,6 @@
&omap2430_l4_wkup__gpio3,
&omap2430_l4_wkup__gpio4,
&omap2430_l4_core__gpio5,
- &omap2430_dma_system__l3,
- &omap2430_l4_core__dma_system,
&omap2430_l4_core__mailbox,
&omap2430_l4_core__mcbsp1,
&omap2430_l4_core__mcbsp2,
@@ -647,7 +595,6 @@
&omap2xxx_l4_core__rng,
&omap2xxx_l4_core__sham,
&omap2xxx_l4_core__aes,
- &omap2430_l4_wkup__counter_32k,
&omap2430_l3__gpmc,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index eef96ad..518e877 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -95,14 +95,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_core -> timer2 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer2_hwmod,
- .clk = "gpt2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_core -> timer3 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
.master = &omap2xxx_l4_core_hwmod,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index f767524..9156f2b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -7,7 +7,6 @@
*/
#include <linux/types.h>
-#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
@@ -95,23 +94,6 @@
.sysc = &omap2xxx_gpio_sysc,
};
-/* system dma */
-static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap2xxx_dma_sysc,
-};
-
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors
@@ -213,36 +195,6 @@
.class = &iva_hwmod_class,
};
-/* timer1 */
-struct omap_hwmod omap2xxx_timer1_hwmod = {
- .name = "timer1",
- .main_clk = "gpt1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer2 */
-struct omap_hwmod omap2xxx_timer2_hwmod = {
- .name = "timer2",
- .main_clk = "gpt2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
/* timer3 */
struct omap_hwmod omap2xxx_timer3_hwmod = {
.name = "timer3",
@@ -613,23 +565,6 @@
.class = &omap2xxx_mcspi_class,
};
-static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
- .name = "counter",
-};
-
-struct omap_hwmod omap2xxx_counter_32k_hwmod = {
- .name = "counter_32k",
- .main_clk = "func_32k_ck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
- },
- },
- .class = &omap2xxx_counter_hwmod_class,
-};
-
/* gpmc */
struct omap_hwmod omap2xxx_gpmc_hwmod = {
.name = "gpmc",
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
index 3de3d7a..e298410 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
@@ -24,37 +24,11 @@
extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr;
extern struct omap_hwmod_ocp_if am33xx_mpu__prcm;
extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main;
-extern struct omap_hwmod_ocp_if am33xx_pruss__l3_main;
extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main;
extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
-extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2;
extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__mailbox;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer3;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer4;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer5;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer6;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer7;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__tpcc;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc0;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc1;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2;
extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__rng;
extern struct omap_hwmod am33xx_l3_main_hwmod;
extern struct omap_hwmod am33xx_l3_s_hwmod;
@@ -62,48 +36,18 @@
extern struct omap_hwmod am33xx_l4_ls_hwmod;
extern struct omap_hwmod am33xx_l4_wkup_hwmod;
extern struct omap_hwmod am33xx_mpu_hwmod;
-extern struct omap_hwmod am33xx_pruss_hwmod;
extern struct omap_hwmod am33xx_gfx_hwmod;
extern struct omap_hwmod am33xx_prcm_hwmod;
-extern struct omap_hwmod am33xx_aes0_hwmod;
-extern struct omap_hwmod am33xx_sha0_hwmod;
-extern struct omap_hwmod am33xx_rng_hwmod;
extern struct omap_hwmod am33xx_ocmcram_hwmod;
extern struct omap_hwmod am33xx_smartreflex0_hwmod;
extern struct omap_hwmod am33xx_smartreflex1_hwmod;
-extern struct omap_hwmod am33xx_dcan0_hwmod;
-extern struct omap_hwmod am33xx_dcan1_hwmod;
-extern struct omap_hwmod am33xx_elm_hwmod;
-extern struct omap_hwmod am33xx_epwmss0_hwmod;
-extern struct omap_hwmod am33xx_epwmss1_hwmod;
-extern struct omap_hwmod am33xx_epwmss2_hwmod;
extern struct omap_hwmod am33xx_gpmc_hwmod;
-extern struct omap_hwmod am33xx_mailbox_hwmod;
-extern struct omap_hwmod am33xx_mcasp0_hwmod;
-extern struct omap_hwmod am33xx_mcasp1_hwmod;
-extern struct omap_hwmod am33xx_rtc_hwmod;
-extern struct omap_hwmod am33xx_spi0_hwmod;
-extern struct omap_hwmod am33xx_spi1_hwmod;
-extern struct omap_hwmod am33xx_spinlock_hwmod;
-extern struct omap_hwmod am33xx_timer1_hwmod;
-extern struct omap_hwmod am33xx_timer2_hwmod;
-extern struct omap_hwmod am33xx_timer3_hwmod;
-extern struct omap_hwmod am33xx_timer4_hwmod;
-extern struct omap_hwmod am33xx_timer5_hwmod;
-extern struct omap_hwmod am33xx_timer6_hwmod;
-extern struct omap_hwmod am33xx_timer7_hwmod;
-extern struct omap_hwmod am33xx_tpcc_hwmod;
-extern struct omap_hwmod am33xx_tptc0_hwmod;
-extern struct omap_hwmod am33xx_tptc1_hwmod;
-extern struct omap_hwmod am33xx_tptc2_hwmod;
-extern struct omap_hwmod am33xx_wd_timer1_hwmod;
extern struct omap_hwmod_class am33xx_emif_hwmod_class;
extern struct omap_hwmod_class am33xx_l4_hwmod_class;
extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class;
extern struct omap_hwmod_class am33xx_control_hwmod_class;
extern struct omap_hwmod_class am33xx_timer_hwmod_class;
-extern struct omap_hwmod_class am33xx_epwmss_hwmod_class;
extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class;
extern struct omap_hwmod_class am33xx_spi_hwmod_class;
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
index 63698ff..ab5146b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
@@ -74,82 +74,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* pru-icss -> l3 main */
-struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
- .master = &am33xx_pruss_hwmod,
- .slave = &am33xx_l3_main_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gfx -> l3 main */
-struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
- .master = &am33xx_gfx_hwmod,
- .slave = &am33xx_l3_main_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3 main -> gfx */
-struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_gfx_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 wkup -> rtc */
-struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_rtc_hwmod,
- .clk = "clkdiv32k_ick",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per/ls -> DCAN0 */
-struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_dcan0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 per/ls -> DCAN1 */
-struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_dcan1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_elm_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_epwmss0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_epwmss1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_epwmss2_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
/* l3s cfg -> gpmc */
struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.master = &am33xx_l3_s_hwmod,
@@ -158,161 +82,9 @@
.user = OCP_USER_MPU,
};
-/* l4 ls -> mailbox */
-struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_mailbox_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 ls -> spinlock */
-struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_spinlock_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcasp0 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_mcasp0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcasp1 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_mcasp1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcspi0 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_spi0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcspi1 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_spi1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer2 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer2_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer3 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer3_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer4 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer4_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer5 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer5_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer6 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer6_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer7 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer7_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc */
-struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_tpcc_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc0 */
-struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_tptc0_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc1 */
-struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_tptc1_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc2 */
-struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_tptc2_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU,
-};
-
/* l3 main -> ocmc */
struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_ocmcram_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-
-/* l3 main -> sha0 HIB2 */
-struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_sha0_hwmod,
- .clk = "sha0_fck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3 main -> AES0 HIB2 */
-struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_aes0_hwmod,
- .clk = "aes0_fck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 per -> rng */
-struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_rng_hwmod,
- .clk = "rng_fck",
- .user = OCP_USER_MPU,
-};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index 29fd136..bcc120e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -17,7 +17,6 @@
#include <linux/types.h>
#include "omap_hwmod.h"
-#include "wd_timer.h"
#include "cm33xx.h"
#include "prm33xx.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
@@ -27,7 +26,6 @@
#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
-#define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
/*
* 'l3' class
@@ -135,58 +133,6 @@
};
/*
- * 'pru-icss' class
- * Programmable Real-Time Unit and Industrial Communication Subsystem
- */
-static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
- .name = "pruss",
-};
-
-static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
- { .name = "pruss", .rst_shift = 1 },
-};
-
-/* pru-icss */
-/* Pseudo hwmod for reset control purpose only */
-struct omap_hwmod am33xx_pruss_hwmod = {
- .name = "pruss",
- .class = &am33xx_pruss_hwmod_class,
- .clkdm_name = "pruss_ocp_clkdm",
- .main_clk = "pruss_ocp_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .rst_lines = am33xx_pruss_resets,
- .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
-};
-
-/* gfx */
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
- .name = "gfx",
-};
-
-static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
- { .name = "gfx", .rst_shift = 0, .st_shift = 0},
-};
-
-struct omap_hwmod am33xx_gfx_hwmod = {
- .name = "gfx",
- .class = &am33xx_gfx_hwmod_class,
- .clkdm_name = "gfx_l3_clkdm",
- .main_clk = "gfx_fck_div_ck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .rst_lines = am33xx_gfx_resets,
- .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
-};
-
-/*
* 'prcm' class
* power and reset manager (whole prcm infrastructure)
*/
@@ -214,84 +160,7 @@
.sysc = &am33xx_emif_sysc,
};
-/*
- * 'aes0' class
- */
-static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
- .rev_offs = 0x80,
- .sysc_offs = 0x84,
- .syss_offs = 0x88,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
- .name = "aes0",
- .sysc = &am33xx_aes0_sysc,
-};
-
-struct omap_hwmod am33xx_aes0_hwmod = {
- .name = "aes",
- .class = &am33xx_aes0_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .main_clk = "aes0_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* sha0 HIB2 (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
- .rev_offs = 0x100,
- .sysc_offs = 0x110,
- .syss_offs = 0x114,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
- .name = "sha0",
- .sysc = &am33xx_sha0_sysc,
-};
-
-struct omap_hwmod am33xx_sha0_hwmod = {
- .name = "sham",
- .class = &am33xx_sha0_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* rng */
-static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
- .rev_offs = 0x1fe0,
- .sysc_offs = 0x1fe4,
- .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
- .idlemodes = SIDLE_FORCE | SIDLE_NO,
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_rng_hwmod_class = {
- .name = "rng",
- .sysc = &am33xx_rng_sysc,
-};
-
-struct omap_hwmod am33xx_rng_hwmod = {
- .name = "rng",
- .class = &am33xx_rng_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "rng_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
@@ -349,202 +218,6 @@
.name = "control",
};
-/*
- * dcan class
- */
-static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
- .name = "d_can",
-};
-
-/* dcan0 */
-struct omap_hwmod am33xx_dcan0_hwmod = {
- .name = "d_can0",
- .class = &am33xx_dcan_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dcan0_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* dcan1 */
-struct omap_hwmod am33xx_dcan1_hwmod = {
- .name = "d_can1",
- .class = &am33xx_dcan_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dcan1_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* elm */
-static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_elm_hwmod_class = {
- .name = "elm",
- .sysc = &am33xx_elm_sysc,
-};
-
-struct omap_hwmod am33xx_elm_hwmod = {
- .name = "elm",
- .class = &am33xx_elm_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* pwmss */
-static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x4,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
- .name = "epwmss",
- .sysc = &am33xx_epwmss_sysc,
-};
-
-/* epwmss0 */
-struct omap_hwmod am33xx_epwmss0_hwmod = {
- .name = "epwmss0",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* epwmss1 */
-struct omap_hwmod am33xx_epwmss1_hwmod = {
- .name = "epwmss1",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* epwmss2 */
-struct omap_hwmod am33xx_epwmss2_hwmod = {
- .name = "epwmss2",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'gpio' class: for gpio 0,1,2,3
- */
-static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0114,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
- .name = "gpio",
- .sysc = &am33xx_gpio_sysc,
-};
-
-/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio1_dbclk" },
-};
-
-static struct omap_hwmod am33xx_gpio1_hwmod = {
- .name = "gpio2",
- .class = &am33xx_gpio_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = gpio1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
-};
-
-/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio2_dbclk" },
-};
-
-static struct omap_hwmod am33xx_gpio2_hwmod = {
- .name = "gpio3",
- .class = &am33xx_gpio_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = gpio2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
-};
-
-/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio3_dbclk" },
-};
-
-static struct omap_hwmod am33xx_gpio3_hwmod = {
- .name = "gpio4",
- .class = &am33xx_gpio_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = gpio3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
-};
/* gpmc */
static struct omap_hwmod_class_sysconfig gpmc_sysc = {
@@ -576,535 +249,42 @@
},
};
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors using a
- * queued mailbox-interrupt mechanism.
- */
-static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &am33xx_mailbox_sysc,
-};
-
-struct omap_hwmod am33xx_mailbox_hwmod = {
- .name = "mailbox",
- .class = &am33xx_mailbox_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mcasp' class
- */
-static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x4,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
- .name = "mcasp",
- .sysc = &am33xx_mcasp_sysc,
-};
-
-/* mcasp0 */
-struct omap_hwmod am33xx_mcasp0_hwmod = {
- .name = "mcasp0",
- .class = &am33xx_mcasp_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .main_clk = "mcasp0_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* mcasp1 */
-struct omap_hwmod am33xx_mcasp1_hwmod = {
- .name = "mcasp1",
- .class = &am33xx_mcasp_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .main_clk = "mcasp1_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'rtc' class
- * rtc subsystem
- */
-static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
- .rev_offs = 0x0074,
- .sysc_offs = 0x0078,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO |
- SIDLE_SMART | SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
- .name = "rtc",
- .sysc = &am33xx_rtc_sysc,
- .unlock = &omap_hwmod_rtc_unlock,
- .lock = &omap_hwmod_rtc_lock,
-};
-
-struct omap_hwmod am33xx_rtc_hwmod = {
- .name = "rtc",
- .class = &am33xx_rtc_hwmod_class,
- .clkdm_name = "l4_rtc_clkdm",
- .main_clk = "clk_32768_ck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* 'spi' class */
-static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0110,
- .syss_offs = 0x0114,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class am33xx_spi_hwmod_class = {
- .name = "mcspi",
- .sysc = &am33xx_mcspi_sysc,
-};
-
-/* spi0 */
-struct omap_hwmod am33xx_spi0_hwmod = {
- .name = "spi0",
- .class = &am33xx_spi_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* spi1 */
-struct omap_hwmod am33xx_spi1_hwmod = {
- .name = "spi1",
- .class = &am33xx_spi_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'spinlock' class
- * spinlock provides hardware assistance for synchronizing the
- * processes running on multiple processors
- */
-
-static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
- .name = "spinlock",
- .sysc = &am33xx_spinlock_sysc,
-};
-
-struct omap_hwmod am33xx_spinlock_hwmod = {
- .name = "spinlock",
- .class = &am33xx_spinlock_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* 'timer 2-7' class */
-static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_RESET_STATUS,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-struct omap_hwmod_class am33xx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &am33xx_timer_sysc,
-};
-
-/* timer1 1ms */
-static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
- .name = "timer",
- .sysc = &am33xx_timer1ms_sysc,
-};
-
-struct omap_hwmod am33xx_timer1_hwmod = {
- .name = "timer1",
- .class = &am33xx_timer1ms_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .main_clk = "timer1_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer2_hwmod = {
- .name = "timer2",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer2_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer3_hwmod = {
- .name = "timer3",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer3_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer4_hwmod = {
- .name = "timer4",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer4_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer5_hwmod = {
- .name = "timer5",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer5_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer6_hwmod = {
- .name = "timer6",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer6_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer7_hwmod = {
- .name = "timer7",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer7_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* tpcc */
-static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
- .name = "tpcc",
-};
-
-struct omap_hwmod am33xx_tpcc_hwmod = {
- .name = "tpcc",
- .class = &am33xx_tpcc_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_MIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-/* 'tptc' class */
-static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
- .name = "tptc",
- .sysc = &am33xx_tptc_sysc,
-};
-
-/* tptc0 */
-struct omap_hwmod am33xx_tptc0_hwmod = {
- .name = "tptc0",
- .class = &am33xx_tptc_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* tptc1 */
-struct omap_hwmod am33xx_tptc1_hwmod = {
- .name = "tptc1",
- .class = &am33xx_tptc_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* tptc2 */
-struct omap_hwmod am33xx_tptc2_hwmod = {
- .name = "tptc2",
- .class = &am33xx_tptc_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* 'wd_timer' class */
-static struct omap_hwmod_class_sysconfig wdt_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x10,
- .syss_offs = 0x14,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &wdt_sysc,
- .pre_shutdown = &omap2_wd_timer_disable,
-};
-
-/*
- * XXX: device.c file uses hardcoded name for watchdog timer
- * driver "wd_timer2, so we are also using same name as of now...
- */
-struct omap_hwmod am33xx_wd_timer1_hwmod = {
- .name = "wd_timer2",
- .class = &am33xx_wd_timer_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wdt1_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
static void omap_hwmod_am33xx_clkctrl(void)
{
- CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex0_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex1_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
- PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
-}
-
-static void omap_hwmod_am33xx_rst(void)
-{
- RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
- RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
- RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
}
void omap_hwmod_am33xx_reg(void)
{
omap_hwmod_am33xx_clkctrl();
- omap_hwmod_am33xx_rst();
}
static void omap_hwmod_am43xx_clkctrl(void)
{
- CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex0_hwmod,
AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex1_hwmod,
AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
-}
-
-static void omap_hwmod_am43xx_rst(void)
-{
- RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
- RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
- RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
- RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
}
void omap_hwmod_am43xx_reg(void)
{
omap_hwmod_am43xx_clkctrl();
- omap_hwmod_am43xx_rst();
}
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 5452477..b232f6c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -1,7 +1,7 @@
/*
* omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
*
- * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) {2012} Texas Instruments Incorporated - https://www.ti.com/
*
* This file is automatically generated from the AM33XX hardware databases.
* This program is free software; you can redistribute it and/or
@@ -21,7 +21,6 @@
#include "cm33xx.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
-#include "wd_timer.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
/*
@@ -82,36 +81,6 @@
.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
};
-/*
- * 'adc/tsc' class
- * TouchScreen Controller (Anolog-To-Digital Converter)
- */
-static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x10,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
- .name = "adc_tsc",
- .sysc = &am33xx_adc_tsc_sysc,
-};
-
-static struct omap_hwmod am33xx_adc_tsc_hwmod = {
- .name = "adc_tsc",
- .class = &am33xx_adc_tsc_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .main_clk = "adc_tsc_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
/*
* Modules omap_hwmod structures
@@ -227,67 +196,6 @@
},
};
-/* lcdc */
-static struct omap_hwmod_class_sysconfig lcdc_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x54,
- .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE,
- .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART,
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
- .name = "lcdc",
- .sysc = &lcdc_sysc,
-};
-
-static struct omap_hwmod am33xx_lcdc_hwmod = {
- .name = "lcdc",
- .class = &am33xx_lcdc_hwmod_class,
- .clkdm_name = "lcdc_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "lcd_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'usb_otg' class
- * high-speed on-the-go universal serial bus (usb_otg) controller
- */
-static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_usbotg_class = {
- .name = "usbotg",
- .sysc = &am33xx_usbhsotg_sysc,
-};
-
-static struct omap_hwmod am33xx_usbss_hwmod = {
- .name = "usb_otg_hs",
- .class = &am33xx_usbotg_class,
- .clkdm_name = "l3s_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "usbotg_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
/*
* Interfaces
@@ -325,14 +233,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4 hs -> pru-icss */
-static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
- .master = &am33xx_l4_hs_hwmod,
- .slave = &am33xx_pruss_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main -> debugss */
static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
.master = &am33xx_l3_main_hwmod,
@@ -365,47 +265,6 @@
.user = OCP_USER_MPU,
};
-/* L4 WKUP -> ADC_TSC */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_adc_tsc_hwmod,
- .clk = "dpll_core_m4_div2_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_lcdc_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l4 wkup -> timer1 */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_timer1_hwmod,
- .clk = "dpll_core_m4_div2_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l4 wkup -> wd_timer1 */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_wd_timer1_hwmod,
- .clk = "dpll_core_m4_div2_ck",
- .user = OCP_USER_MPU,
-};
-
-/* usbss */
-/* l3 s -> USBSS interface */
-static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am33xx_usbss_hwmod,
- .clk = "l3s_gclk",
- .user = OCP_USER_MPU,
- .flags = OCPIF_SWSUP_IDLE,
-};
-
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__emif,
&am33xx_mpu__l3_main,
@@ -415,50 +274,15 @@
&am33xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
- &am33xx_l3_main__gfx,
&am33xx_l3_s__l3_main,
- &am33xx_pruss__l3_main,
&am33xx_wkup_m3__l4_wkup,
- &am33xx_gfx__l3_main,
&am33xx_l3_main__debugss,
&am33xx_l4_wkup__wkup_m3,
&am33xx_l4_wkup__control,
&am33xx_l4_wkup__smartreflex0,
&am33xx_l4_wkup__smartreflex1,
- &am33xx_l4_wkup__timer1,
- &am33xx_l4_wkup__rtc,
- &am33xx_l4_wkup__adc_tsc,
- &am33xx_l4_wkup__wd_timer1,
- &am33xx_l4_hs__pruss,
- &am33xx_l4_per__dcan0,
- &am33xx_l4_per__dcan1,
- &am33xx_l4_per__mailbox,
- &am33xx_l4_ls__mcasp0,
- &am33xx_l4_ls__mcasp1,
- &am33xx_l4_ls__timer2,
- &am33xx_l4_ls__timer3,
- &am33xx_l4_ls__timer4,
- &am33xx_l4_ls__timer5,
- &am33xx_l4_ls__timer6,
- &am33xx_l4_ls__timer7,
- &am33xx_l3_main__tpcc,
- &am33xx_l4_ls__spinlock,
- &am33xx_l4_ls__elm,
- &am33xx_l4_ls__epwmss0,
- &am33xx_l4_ls__epwmss1,
- &am33xx_l4_ls__epwmss2,
&am33xx_l3_s__gpmc,
- &am33xx_l3_main__lcdc,
- &am33xx_l4_ls__mcspi0,
- &am33xx_l4_ls__mcspi1,
- &am33xx_l3_main__tptc0,
- &am33xx_l3_main__tptc1,
- &am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
- &am33xx_l3_s__usbss,
- &am33xx_l3_main__sha0,
- &am33xx_l3_main__aes0,
- &am33xx_l4_per__rng,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index f52438b..b6c7d98 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -16,7 +16,6 @@
#include <linux/power/smartreflex.h>
#include <linux/platform_data/hsmmc-omap.h>
-#include <linux/omap-dma.h>
#include "l3_3xxx.h"
#include "l4_3xxx.h"
@@ -148,36 +147,6 @@
.sysc = &omap3xxx_timer_sysc,
};
-/* timer1 */
-static struct omap_hwmod omap3xxx_timer1_hwmod = {
- .name = "timer1",
- .main_clk = "gpt1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
- },
- },
- .class = &omap3xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer2 */
-static struct omap_hwmod omap3xxx_timer2_hwmod = {
- .name = "timer2",
- .main_clk = "gpt2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
- },
- },
- .class = &omap3xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
/* timer3 */
static struct omap_hwmod omap3xxx_timer3_hwmod = {
.name = "timer3",
@@ -313,21 +282,6 @@
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
-/* timer12 */
-static struct omap_hwmod omap3xxx_timer12_hwmod = {
- .name = "timer12",
- .main_clk = "gpt12_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
- },
- },
- .class = &omap3xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
@@ -833,47 +787,6 @@
.class = &omap3xxx_gpio_hwmod_class,
};
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap3xxx_dma_sysc,
-};
-
-/* dma_system */
-static struct omap_hwmod omap3xxx_dma_system_hwmod = {
- .name = "dma",
- .class = &omap3xxx_dma_hwmod_class,
- .main_clk = "core_l3_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
- },
- },
- .dev_attr = &dma_dev_attr,
- .flags = HWMOD_NO_IDLEST,
-};
-
/*
* 'mcbsp' class
* multi channel buffered serial port controller
@@ -1567,38 +1480,6 @@
};
/*
- * '32K sync counter' class
- * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
- */
-static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0004,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
- .name = "counter",
- .sysc = &omap3xxx_counter_sysc,
-};
-
-static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
- .name = "counter_32k",
- .class = &omap3xxx_counter_hwmod_class,
- .clkdm_name = "wkup_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wkup_32k_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
- },
- },
-};
-
-/*
* 'gpmc' class
* general purpose memory controller
*/
@@ -1910,25 +1791,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
- .master = &omap3xxx_l4_wkup_hwmod,
- .slave = &omap3xxx_timer1_hwmod,
- .clk = "gpt1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_timer2_hwmod,
- .clk = "gpt2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-
/* l4_per -> timer3 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
.master = &omap3xxx_l4_per_hwmod,
@@ -2007,15 +1869,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
- .master = &omap3xxx_l4_sec_hwmod,
- .slave = &omap3xxx_timer12_hwmod,
- .clk = "gpt12_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
@@ -2233,23 +2086,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
- .master = &omap3xxx_dma_system_hwmod,
- .slave = &omap3xxx_l3_main_hwmod,
- .clk = "core_l3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_dma_system_hwmod,
- .clk = "core_l4_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-
/* l4_core -> mcbsp1 */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
.master = &omap3xxx_l4_core_hwmod,
@@ -2384,16 +2220,6 @@
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
-/* l4_wkup -> 32ksync_counter */
-
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
- .master = &omap3xxx_l4_wkup_hwmod,
- .slave = &omap3xxx_counter_32k_hwmod,
- .clk = "omap_32ksync_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* am35xx has Davinci MDIO & EMAC */
static struct omap_hwmod_class am35xx_mdio_class = {
.name = "davinci_mdio",
@@ -2516,44 +2342,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_core -> AES */
-static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
- .rev_offs = 0x44,
- .sysc_offs = 0x48,
- .syss_offs = 0x4c,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap3xxx_aes_sysc_fields,
-};
-
-static struct omap_hwmod_class omap3xxx_aes_class = {
- .name = "aes",
- .sysc = &omap3_aes_sysc,
-};
-
-
-static struct omap_hwmod omap3xxx_aes_hwmod = {
- .name = "aes",
- .main_clk = "aes2_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
- },
- },
- .class = &omap3xxx_aes_class,
-};
-
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_aes_hwmod,
- .clk = "aes2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/*
* 'ssi' class
* synchronous serial interface (multichannel and full-duplex serial if)
@@ -2610,8 +2398,6 @@
&omap3_l4_core__i2c2,
&omap3_l4_core__i2c3,
&omap3xxx_l4_wkup__l4_sec,
- &omap3xxx_l4_wkup__timer1,
- &omap3xxx_l4_per__timer2,
&omap3xxx_l4_per__timer3,
&omap3xxx_l4_per__timer4,
&omap3xxx_l4_per__timer5,
@@ -2628,8 +2414,6 @@
&omap3xxx_l4_per__gpio4,
&omap3xxx_l4_per__gpio5,
&omap3xxx_l4_per__gpio6,
- &omap3xxx_dma_system__l3,
- &omap3xxx_l4_core__dma_system,
&omap3xxx_l4_core__mcbsp1,
&omap3xxx_l4_per__mcbsp2,
&omap3xxx_l4_per__mcbsp3,
@@ -2641,47 +2425,21 @@
&omap34xx_l4_core__mcspi2,
&omap34xx_l4_core__mcspi3,
&omap34xx_l4_core__mcspi4,
- &omap3xxx_l4_wkup__counter_32k,
&omap3xxx_l3_main__gpmc,
NULL,
};
-/* GP-only hwmod links */
-static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_sec__timer12,
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_sec__timer12,
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_sec__timer12,
- NULL,
-};
-
/* crypto hwmod links */
static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__sham,
NULL,
};
-static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_core__aes,
- NULL,
-};
-
static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__sham,
NULL
};
-static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_core__aes,
- NULL
-};
/*
* Apparently the SHA/MD5 and AES accelerator IP blocks are
@@ -2696,11 +2454,6 @@
NULL
};
-static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
- /* &omap3xxx_l4_core__aes, */
- NULL,
-};
-
/* 3430ES1-only hwmod links */
static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
&omap3430es1_dss__l3,
@@ -2835,8 +2588,7 @@
int __init omap3xxx_hwmod_init(void)
{
int r;
- struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
- struct omap_hwmod_ocp_if **h_aes = NULL;
+ struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL;
struct device_node *bus;
unsigned int rev;
@@ -2858,20 +2610,14 @@
rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
h = omap34xx_hwmod_ocp_ifs;
- h_gp = omap34xx_gp_hwmod_ocp_ifs;
h_sham = omap34xx_sham_hwmod_ocp_ifs;
- h_aes = omap34xx_aes_hwmod_ocp_ifs;
} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
h = am35xx_hwmod_ocp_ifs;
- h_gp = am35xx_gp_hwmod_ocp_ifs;
h_sham = am35xx_sham_hwmod_ocp_ifs;
- h_aes = am35xx_aes_hwmod_ocp_ifs;
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
rev == OMAP3630_REV_ES1_2) {
h = omap36xx_hwmod_ocp_ifs;
- h_gp = omap36xx_gp_hwmod_ocp_ifs;
h_sham = omap36xx_sham_hwmod_ocp_ifs;
- h_aes = omap36xx_aes_hwmod_ocp_ifs;
} else {
WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
return -EINVAL;
@@ -2881,13 +2627,6 @@
if (r < 0)
return r;
- /* Register GP-only hwmod links. */
- if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
- r = omap_hwmod_register_links(h_gp);
- if (r < 0)
- return r;
- }
-
/*
* Register crypto hwmod links only if they are not disabled in DT.
* If DT information is missing, enable them only for GP devices.
@@ -2901,11 +2640,6 @@
goto put_node;
}
- if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
- r = omap_hwmod_register_links(h_aes);
- if (r < 0)
- goto put_node;
- }
of_node_put(bus);
/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 5c3db6b..b97cb74 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -18,8 +18,6 @@
#include "omap_hwmod_33xx_43xx_common_data.h"
#include "prcm43xx.h"
#include "omap_hwmod_common_data.h"
-#include "hdq1w.h"
-
/* IP blocks */
static struct omap_hwmod am43xx_emif_hwmod = {
@@ -87,452 +85,6 @@
},
};
-static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x4,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
- .name = "synctimer",
- .sysc = &am43xx_synctimer_sysc,
-};
-
-static struct omap_hwmod am43xx_synctimer_hwmod = {
- .name = "counter_32k",
- .class = &am43xx_synctimer_hwmod_class,
- .clkdm_name = "l4_wkup_aon_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "synctimer_32kclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_timer8_hwmod = {
- .name = "timer8",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer8_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_timer9_hwmod = {
- .name = "timer9",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer9_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_timer10_hwmod = {
- .name = "timer10",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer10_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_timer11_hwmod = {
- .name = "timer11",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer11_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_epwmss3_hwmod = {
- .name = "epwmss3",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_epwmss4_hwmod = {
- .name = "epwmss4",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_epwmss5_hwmod = {
- .name = "epwmss5",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_spi2_hwmod = {
- .name = "spi2",
- .class = &am33xx_spi_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_spi3_hwmod = {
- .name = "spi3",
- .class = &am33xx_spi_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_spi4_hwmod = {
- .name = "spi4",
- .class = &am33xx_spi_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
- .name = "ocp2scp",
-};
-
-static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
- .name = "ocp2scp0",
- .class = &am43xx_ocp2scp_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
- .name = "ocp2scp1",
- .class = &am43xx_ocp2scp_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE |
- MSTANDBY_NO | MSTANDBY_SMART |
- MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
- .name = "usb_otg_ss",
- .sysc = &am43xx_usb_otg_ss_sysc,
-};
-
-static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
- .name = "usb_otg_ss0",
- .class = &am43xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .main_clk = "l3s_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
- .name = "usb_otg_ss1",
- .class = &am43xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .main_clk = "l3s_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
- .rev_offs = 0,
- .sysc_offs = 0x0010,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
- .name = "qspi",
- .sysc = &am43xx_qspi_sysc,
-};
-
-static struct omap_hwmod am43xx_qspi_hwmod = {
- .name = "qspi",
- .class = &am43xx_qspi_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .main_clk = "l3s_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'adc/tsc' class
- * TouchScreen Controller (Analog-To-Digital Converter)
- */
-static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x10,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
- .name = "adc_tsc",
- .sysc = &am43xx_adc_tsc_sysc,
-};
-
-static struct omap_hwmod am43xx_adc_tsc_hwmod = {
- .name = "adc_tsc",
- .class = &am43xx_adc_tsc_hwmod_class,
- .clkdm_name = "l3s_tsc_clkdm",
- .main_clk = "adc_tsc_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class_sysconfig am43xx_des_sysc = {
- .rev_offs = 0x30,
- .sysc_offs = 0x34,
- .syss_offs = 0x38,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class am43xx_des_hwmod_class = {
- .name = "des",
- .sysc = &am43xx_des_sysc,
-};
-
-static struct omap_hwmod am43xx_des_hwmod = {
- .name = "des",
- .class = &am43xx_des_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_DES_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* dss */
-
-static struct omap_hwmod am43xx_dss_core_hwmod = {
- .name = "dss_core",
- .class = &omap2_dss_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "disp_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* dispc */
-
-static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
- .manager_count = 1,
- .has_framedonetv_irq = 0
-};
-
-static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &am43xx_dispc_sysc,
-};
-
-static struct omap_hwmod am43xx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &am43xx_dispc_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "disp_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
- },
- },
- .dev_attr = &am43xx_dss_dispc_dev_attr,
- .parent_hwmod = &am43xx_dss_core_hwmod,
-};
-
-/* rfbi */
-
-static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap2_rfbi_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "disp_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
- },
- },
- .parent_hwmod = &am43xx_dss_core_hwmod,
-};
-
-/* HDQ1W */
-static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0014,
- .syss_offs = 0x0018,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
- .name = "hdq1w",
- .sysc = &am43xx_hdq1w_sysc,
- .reset = &omap_hdq1w_reset,
-};
-
-static struct omap_hwmod am43xx_hdq1w_hwmod = {
- .name = "hdq1w",
- .class = &am43xx_hdq1w_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x104,
- .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
- .name = "vpfe",
- .sysc = &am43xx_vpfe_sysc,
-};
-
-static struct omap_hwmod am43xx_vpfe0_hwmod = {
- .name = "vpfe0",
- .class = &am43xx_vpfe_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
- },
- },
-};
-
-static struct omap_hwmod am43xx_vpfe1_hwmod = {
- .name = "vpfe1",
- .class = &am43xx_vpfe_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
- },
- },
-};
-
/* Interfaces */
static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
.master = &am33xx_l3_main_hwmod,
@@ -562,13 +114,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_pruss_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex0_hwmod,
@@ -590,222 +135,7 @@
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am43xx_adc_tsc_hwmod,
- .clk = "dpll_core_m4_div2_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_timer1_hwmod,
- .clk = "sys_clkin_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_wd_timer1_hwmod,
- .clk = "sys_clkin_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am43xx_synctimer_hwmod,
- .clk = "sys_clkin_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_timer8_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_timer9_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_timer10_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_timer11_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_epwmss3_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_epwmss4_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_epwmss5_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_spi2_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_spi3_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_spi4_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_ocp2scp0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_ocp2scp1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am43xx_usb_otg_ss0_hwmod,
- .clk = "l3s_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am43xx_usb_otg_ss1_hwmod,
- .clk = "l3s_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am43xx_qspi_hwmod,
- .clk = "l3s_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
- .master = &am43xx_dss_core_hwmod,
- .slave = &am33xx_l3_main_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_dss_core_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_dss_dispc_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_dss_rfbi_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_hdq1w_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
- .master = &am43xx_vpfe0_hwmod,
- .slave = &am33xx_l3_main_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
- .master = &am43xx_vpfe1_hwmod,
- .slave = &am33xx_l3_main_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_vpfe0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_vpfe1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3_main__des = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am43xx_des_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
- &am33xx_l4_wkup__synctimer,
- &am43xx_l4_ls__timer8,
- &am43xx_l4_ls__timer9,
- &am43xx_l4_ls__timer10,
- &am43xx_l4_ls__timer11,
- &am43xx_l4_ls__epwmss3,
- &am43xx_l4_ls__epwmss4,
- &am43xx_l4_ls__epwmss5,
- &am43xx_l4_ls__mcspi2,
- &am43xx_l4_ls__mcspi3,
- &am43xx_l4_ls__mcspi4,
- &am43xx_l3_main__pruss,
&am33xx_mpu__l3_main,
&am33xx_mpu__prcm,
&am33xx_l3_s__l4_ls,
@@ -813,66 +143,15 @@
&am43xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
- &am33xx_l3_main__gfx,
&am33xx_l3_s__l3_main,
&am43xx_l3_main__emif,
- &am33xx_pruss__l3_main,
&am43xx_wkup_m3__l4_wkup,
- &am33xx_gfx__l3_main,
&am43xx_l4_wkup__wkup_m3,
&am43xx_l4_wkup__control,
&am43xx_l4_wkup__smartreflex0,
&am43xx_l4_wkup__smartreflex1,
- &am43xx_l4_wkup__timer1,
- &am43xx_l4_wkup__wd_timer1,
- &am43xx_l4_wkup__adc_tsc,
- &am43xx_l3_s__qspi,
- &am33xx_l4_per__dcan0,
- &am33xx_l4_per__dcan1,
- &am33xx_l4_per__mailbox,
- &am33xx_l4_per__rng,
- &am33xx_l4_ls__mcasp0,
- &am33xx_l4_ls__mcasp1,
- &am33xx_l4_ls__timer2,
- &am33xx_l4_ls__timer3,
- &am33xx_l4_ls__timer4,
- &am33xx_l4_ls__timer5,
- &am33xx_l4_ls__timer6,
- &am33xx_l4_ls__timer7,
- &am33xx_l3_main__tpcc,
- &am33xx_l4_ls__spinlock,
- &am33xx_l4_ls__elm,
- &am33xx_l4_ls__epwmss0,
- &am33xx_l4_ls__epwmss1,
- &am33xx_l4_ls__epwmss2,
&am33xx_l3_s__gpmc,
- &am33xx_l4_ls__mcspi0,
- &am33xx_l4_ls__mcspi1,
- &am33xx_l3_main__tptc0,
- &am33xx_l3_main__tptc1,
- &am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
- &am33xx_l3_main__sha0,
- &am33xx_l3_main__aes0,
- &am43xx_l3_main__des,
- &am43xx_l4_ls__ocp2scp0,
- &am43xx_l4_ls__ocp2scp1,
- &am43xx_l3_s__usbotgss0,
- &am43xx_l3_s__usbotgss1,
- &am43xx_dss__l3_main,
- &am43xx_l4_ls__dss,
- &am43xx_l4_ls__dss_dispc,
- &am43xx_l4_ls__dss_rfbi,
- &am43xx_l4_ls__hdq1w,
- &am43xx_l3__vpfe0,
- &am43xx_l3__vpfe1,
- &am43xx_l4_ls__vpfe0,
- &am43xx_l4_ls__vpfe1,
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
- &am33xx_l4_wkup__rtc,
NULL,
};
@@ -884,8 +163,5 @@
omap_hwmod_init();
ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
- if (!ret && of_machine_is_compatible("ti,am4372"))
- ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
-
return ret;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 28ea296..37c5911 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -18,9 +18,6 @@
*/
#include <linux/io.h>
-#include <linux/power/smartreflex.h>
-
-#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
@@ -32,9 +29,6 @@
/* Base offset for all OMAP4 interrupts external to MPUSS */
#define OMAP44XX_IRQ_GIC_START 32
-/* Base offset for all OMAP4 dma requests */
-#define OMAP44XX_DMA_REQ_START 1
-
/*
* IP blocks
*/
@@ -130,21 +124,6 @@
.name = "l4",
};
-/* l4_abe */
-static struct omap_hwmod omap44xx_l4_abe_hwmod = {
- .name = "l4_abe",
- .class = &omap44xx_l4_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
- .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
/* l4_cfg */
static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
.name = "l4_cfg",
@@ -238,76 +217,6 @@
*/
/*
- * 'aess' class
- * audio engine sub system
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
- MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
- .name = "aess",
- .sysc = &omap44xx_aess_sysc,
- .enable_preprogram = omap_hwmod_aess_preprogram,
-};
-
-/* aess */
-static struct omap_hwmod omap44xx_aess_hwmod = {
- .name = "aess",
- .class = &omap44xx_aess_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "aess_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
- .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'counter' class
- * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0004,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
- .name = "counter",
- .sysc = &omap44xx_counter_sysc,
-};
-
-/* counter_32k */
-static struct omap_hwmod omap44xx_counter_32k_hwmod = {
- .name = "counter_32k",
- .class = &omap44xx_counter_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
* 'ctrl_module' class
* attila core control module + core pad control module + wkup pad control
* module + attila wkup control module
@@ -399,446 +308,6 @@
};
/*
- * 'dma' class
- * dma controller for data exchange between memory to memory (i.e. internal or
- * external memory) and gp peripherals to memory or memory to gp peripherals
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap44xx_dma_sysc,
-};
-
-/* dma dev_attr */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-/* dma_system */
-static struct omap_hwmod omap44xx_dma_system_hwmod = {
- .name = "dma_system",
- .class = &omap44xx_dma_hwmod_class,
- .clkdm_name = "l3_dma_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
- },
- },
- .dev_attr = &dma_dev_attr,
-};
-
-/*
- * 'dmic' class
- * digital microphone controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
- .name = "dmic",
- .sysc = &omap44xx_dmic_sysc,
-};
-
-/* dmic */
-static struct omap_hwmod omap44xx_dmic_hwmod = {
- .name = "dmic",
- .class = &omap44xx_dmic_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "func_dmic_abe_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'dsp' class
- * dsp sub-system
- */
-
-static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
- .name = "dsp",
-};
-
-/* dsp */
-static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
- { .name = "dsp", .rst_shift = 0 },
-};
-
-static struct omap_hwmod omap44xx_dsp_hwmod = {
- .name = "dsp",
- .class = &omap44xx_dsp_hwmod_class,
- .clkdm_name = "tesla_clkdm",
- .rst_lines = omap44xx_dsp_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
- .main_clk = "dpll_iva_m4x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
- .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'dss' class
- * display sub-system
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
- .rev_offs = 0x0000,
- .syss_offs = 0x0014,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
- .name = "dss",
- .sysc = &omap44xx_dss_sysc,
- .reset = omap_dss_reset,
-};
-
-/* dss */
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
- { .role = "tv_clk", .clk = "dss_tv_clk" },
- { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_hwmod = {
- .name = "dss_core",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .class = &omap44xx_dss_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-};
-
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap44xx_dispc_sysc,
-};
-
-/* dss_dispc */
-static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
- .manager_count = 3,
- .has_framedonetv_irq = 1
-};
-
-static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &omap44xx_dispc_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .dev_attr = &omap44xx_dss_dispc_dev_attr,
- .parent_hwmod = &omap44xx_dss_hwmod,
-};
-
-/*
- * 'dsi' class
- * display serial interface controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
- .name = "dsi",
- .sysc = &omap44xx_dsi_sysc,
-};
-
-/* dss_dsi1 */
-static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
- .name = "dss_dsi1",
- .class = &omap44xx_dsi_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .opt_clks = dss_dsi1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
- .parent_hwmod = &omap44xx_dss_hwmod,
-};
-
-/* dss_dsi2 */
-static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
- .name = "dss_dsi2",
- .class = &omap44xx_dsi_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .opt_clks = dss_dsi2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
- .parent_hwmod = &omap44xx_dss_hwmod,
-};
-
-/*
- * 'hdmi' class
- * hdmi controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
- .name = "hdmi",
- .sysc = &omap44xx_hdmi_sysc,
-};
-
-/* dss_hdmi */
-static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
- { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
- .name = "dss_hdmi",
- .class = &omap44xx_hdmi_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- /*
- * HDMI audio requires to use no-idle mode. Hence,
- * set idle mode by software.
- */
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
- .main_clk = "dss_48mhz_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .opt_clks = dss_hdmi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
- .parent_hwmod = &omap44xx_dss_hwmod,
-};
-
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
- .name = "rfbi",
- .sysc = &omap44xx_rfbi_sysc,
-};
-
-/* dss_rfbi */
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
- { .role = "ick", .clk = "l3_div_ck" },
-};
-
-static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap44xx_rfbi_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .opt_clks = dss_rfbi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
- .parent_hwmod = &omap44xx_dss_hwmod,
-};
-
-/*
- * 'venc' class
- * video encoder
- */
-
-static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
- .name = "venc",
-};
-
-/* dss_venc */
-static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
- { .role = "tv_clk", .clk = "dss_tv_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_venc_hwmod = {
- .name = "dss_venc",
- .class = &omap44xx_venc_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_tv_clk",
- .flags = HWMOD_OPT_CLKS_NEEDED,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .parent_hwmod = &omap44xx_dss_hwmod,
- .opt_clks = dss_venc_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
-};
-
-/* sha0 HIB2 (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
- .rev_offs = 0x100,
- .sysc_offs = 0x110,
- .syss_offs = 0x114,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
- .name = "sham",
- .sysc = &omap44xx_sha0_sysc,
-};
-
-struct omap_hwmod omap44xx_sha0_hwmod = {
- .name = "sham",
- .class = &omap44xx_sha0_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'elm' class
- * bch error location module
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
- .name = "elm",
- .sysc = &omap44xx_elm_sysc,
-};
-
-/* elm */
-static struct omap_hwmod omap44xx_elm_hwmod = {
- .name = "elm",
- .class = &omap44xx_elm_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
* 'emif' class
* external memory interface no1
*/
@@ -885,147 +354,6 @@
};
/*
- Crypto modules AES0/1 belong to:
- PD_L4_PER power domain
- CD_L4_SEC clock domain
- On the L3, the AES modules are mapped to
- L3_CLK2: Peripherals and multimedia sub clock domain
-*/
-static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
- .rev_offs = 0x80,
- .sysc_offs = 0x84,
- .syss_offs = 0x88,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
- .name = "aes",
- .sysc = &omap44xx_aes_sysc,
-};
-
-static struct omap_hwmod omap44xx_aes1_hwmod = {
- .name = "aes1",
- .class = &omap44xx_aes_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
- .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_aes1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod omap44xx_aes2_hwmod = {
- .name = "aes2",
- .class = &omap44xx_aes_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
- .clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_aes2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/*
- * 'des' class for DES3DES module
- */
-static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
- .rev_offs = 0x30,
- .sysc_offs = 0x34,
- .syss_offs = 0x38,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_des_hwmod_class = {
- .name = "des",
- .sysc = &omap44xx_des_sysc,
-};
-
-static struct omap_hwmod omap44xx_des_hwmod = {
- .name = "des",
- .class = &omap44xx_des_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
- .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_des_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/*
- * 'fdif' class
- * face detection hw accelerator module
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- /*
- * FDIF needs 100 OCP clk cycles delay after a softreset before
- * accessing sysconfig again.
- * The lowest frequency at the moment for L3 bus is 100 MHz, so
- * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
- *
- * TODO: Indicate errata when available.
- */
- .srst_udelay = 2,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
- .name = "fdif",
- .sysc = &omap44xx_fdif_sysc,
-};
-
-/* fdif */
-static struct omap_hwmod omap44xx_fdif_hwmod = {
- .name = "fdif",
- .class = &omap44xx_fdif_hwmod_class,
- .clkdm_name = "iss_clkdm",
- .main_clk = "fdif_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
* 'gpmc' class
* general purpose memory controller
*/
@@ -1062,112 +390,6 @@
};
/*
- * 'hdq1w' class
- * hdq / 1-wire serial interface controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0014,
- .syss_offs = 0x0018,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
- .name = "hdq1w",
- .sysc = &omap44xx_hdq1w_sysc,
-};
-
-/* hdq1w */
-static struct omap_hwmod omap44xx_hdq1w_hwmod = {
- .name = "hdq1w",
- .class = &omap44xx_hdq1w_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
- .main_clk = "func_12m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'hsi' class
- * mipi high-speed synchronous serial interface (multichannel and full-duplex
- * serial if)
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
- SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
- .name = "hsi",
- .sysc = &omap44xx_hsi_sysc,
-};
-
-/* hsi */
-static struct omap_hwmod omap44xx_hsi_hwmod = {
- .name = "hsi",
- .class = &omap44xx_hsi_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .main_clk = "hsi_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'ipu' class
- * imaging processor unit
- */
-
-static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
- .name = "ipu",
-};
-
-/* ipu */
-static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
- { .name = "cpu0", .rst_shift = 0 },
- { .name = "cpu1", .rst_shift = 1 },
-};
-
-static struct omap_hwmod omap44xx_ipu_hwmod = {
- .name = "ipu",
- .class = &omap44xx_ipu_hwmod_class,
- .clkdm_name = "ducati_clkdm",
- .rst_lines = omap44xx_ipu_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
- .main_clk = "ducati_clk_mux_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
- .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
* 'iss' class
* external images sensor pixel data processor
*/
@@ -1252,351 +474,6 @@
};
/*
- * 'kbd' class
- * keyboard controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
- .name = "kbd",
- .sysc = &omap44xx_kbd_sysc,
-};
-
-/* kbd */
-static struct omap_hwmod omap44xx_kbd_hwmod = {
- .name = "kbd",
- .class = &omap44xx_kbd_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors using a
- * queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &omap44xx_mailbox_sysc,
-};
-
-/* mailbox */
-static struct omap_hwmod omap44xx_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap44xx_mailbox_hwmod_class,
- .clkdm_name = "l4_cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'mcasp' class
- * multi-channel audio serial port controller
- */
-
-/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
- .rev_offs = 0,
- .sysc_offs = 0x0004,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type_mcasp,
-};
-
-static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
- .name = "mcasp",
- .sysc = &omap44xx_mcasp_sysc,
-};
-
-/* mcasp */
-static struct omap_hwmod omap44xx_mcasp_hwmod = {
- .name = "mcasp",
- .class = &omap44xx_mcasp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "func_mcasp_abe_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
- .rev_offs = -ENODEV,
- .sysc_offs = 0x008c,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
- .name = "mcbsp",
- .sysc = &omap44xx_mcbsp_sysc,
-};
-
-/* mcbsp1 */
-static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap44xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "func_mcbsp1_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
-};
-
-/* mcbsp2 */
-static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap44xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "func_mcbsp2_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
-};
-
-/* mcbsp3 */
-static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
- .name = "mcbsp3",
- .class = &omap44xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "func_mcbsp3_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
-};
-
-/* mcbsp4 */
-static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
- .name = "mcbsp4",
- .class = &omap44xx_mcbsp_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .main_clk = "per_mcbsp4_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp4_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
-};
-
-/*
- * 'mcpdm' class
- * multi channel pdm controller (proprietary interface with phoenix power
- * ic)
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
- .name = "mcpdm",
- .sysc = &omap44xx_mcpdm_sysc,
-};
-
-/* mcpdm */
-static struct omap_hwmod omap44xx_mcpdm_hwmod = {
- .name = "mcpdm",
- .class = &omap44xx_mcpdm_hwmod_class,
- .clkdm_name = "abe_clkdm",
- /*
- * It's suspected that the McPDM requires an off-chip main
- * functional clock, controlled via I2C. This IP block is
- * currently reset very early during boot, before I2C is
- * available, so it doesn't seem that we have any choice in
- * the kernel other than to avoid resetting it.
- *
- * Also, McPDM needs to be configured to NO_IDLE mode when it
- * is in used otherwise vital clocks will be gated which
- * results 'slow motion' audio playback.
- */
- .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
- .main_clk = "pad_clks_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mmu' class
- * The memory management unit performs virtual to physical address translation
- * for its requestors.
- */
-
-static struct omap_hwmod_class_sysconfig mmu_sysc = {
- .rev_offs = 0x000,
- .sysc_offs = 0x010,
- .syss_offs = 0x014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
- .name = "mmu",
- .sysc = &mmu_sysc,
-};
-
-/* mmu ipu */
-
-static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
-static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
- { .name = "mmu_cache", .rst_shift = 2 },
-};
-
-/* l3_main_2 -> mmu_ipu */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_mmu_ipu_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
- .name = "mmu_ipu",
- .class = &omap44xx_mmu_hwmod_class,
- .clkdm_name = "ducati_clkdm",
- .rst_lines = omap44xx_mmu_ipu_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
- .main_clk = "ducati_clk_mux_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
- .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* mmu dsp */
-
-static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
-static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
- { .name = "mmu_cache", .rst_shift = 1 },
-};
-
-/* l4_cfg -> dsp */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_mmu_dsp_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
- .name = "mmu_dsp",
- .class = &omap44xx_mmu_hwmod_class,
- .clkdm_name = "tesla_clkdm",
- .rst_lines = omap44xx_mmu_dsp_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
- .main_clk = "dpll_iva_m4x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
- .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
* 'mpu' class
* mpu sub-system
*/
@@ -1642,51 +519,6 @@
},
};
-/*
- * 'ocp2scp' class
- * bridge to transform ocp interface protocol to scp (serial control port)
- * protocol
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
- .name = "ocp2scp",
- .sysc = &omap44xx_ocp2scp_sysc,
-};
-
-/* ocp2scp_usb_phy */
-static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
- .name = "ocp2scp_usb_phy",
- .class = &omap44xx_ocp2scp_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- /*
- * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
- * block as an "optional clock," and normally should never be
- * specified as the main_clk for an OMAP IP block. However it
- * turns out that this clock is actually the main clock for
- * the ocp2scp_usb_phy IP block:
- * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
- * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
- * to be the best workaround.
- */
- .main_clk = "ocp2scp_usb_phy_phy_48m",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
/*
* 'prcm' class
@@ -1793,588 +625,6 @@
};
/*
- * 'slimbus' class
- * bidirectional, multi-drop, multi-channel two-line serial interface between
- * the device and external components
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
- .name = "slimbus",
- .sysc = &omap44xx_slimbus_sysc,
-};
-
-/* slimbus1 */
-static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
- { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
- { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
- { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
- { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
-};
-
-static struct omap_hwmod omap44xx_slimbus1_hwmod = {
- .name = "slimbus1",
- .class = &omap44xx_slimbus_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = slimbus1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
-};
-
-/* slimbus2 */
-static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
- { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
- { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
- { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
-};
-
-static struct omap_hwmod omap44xx_slimbus2_hwmod = {
- .name = "slimbus2",
- .class = &omap44xx_slimbus_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = slimbus2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
-};
-
-/*
- * 'smartreflex' class
- * smartreflex module (monitor silicon performance and outputs a measure of
- * performance error)
- */
-
-/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
- .rev_offs = -ENODEV,
- .sysc_offs = 0x0038,
- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap36xx_sr_sysc_fields,
-};
-
-static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
- .name = "smartreflex",
- .sysc = &omap44xx_smartreflex_sysc,
-};
-
-/* smartreflex_core */
-static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
- .sensor_voltdm_name = "core",
-};
-
-static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
- .name = "smartreflex_core",
- .class = &omap44xx_smartreflex_hwmod_class,
- .clkdm_name = "l4_ao_clkdm",
-
- .main_clk = "smartreflex_core_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .dev_attr = &smartreflex_core_dev_attr,
-};
-
-/* smartreflex_iva */
-static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
- .sensor_voltdm_name = "iva",
-};
-
-static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
- .name = "smartreflex_iva",
- .class = &omap44xx_smartreflex_hwmod_class,
- .clkdm_name = "l4_ao_clkdm",
- .main_clk = "smartreflex_iva_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .dev_attr = &smartreflex_iva_dev_attr,
-};
-
-/* smartreflex_mpu */
-static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
- .sensor_voltdm_name = "mpu",
-};
-
-static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
- .name = "smartreflex_mpu",
- .class = &omap44xx_smartreflex_hwmod_class,
- .clkdm_name = "l4_ao_clkdm",
- .main_clk = "smartreflex_mpu_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .dev_attr = &smartreflex_mpu_dev_attr,
-};
-
-/*
- * 'spinlock' class
- * spinlock provides hardware assistance for synchronizing the processes
- * running on multiple processors
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
- .name = "spinlock",
- .sysc = &omap44xx_spinlock_sysc,
-};
-
-/* spinlock */
-static struct omap_hwmod omap44xx_spinlock_hwmod = {
- .name = "spinlock",
- .class = &omap44xx_spinlock_hwmod_class,
- .clkdm_name = "l4_cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'timer' class
- * general purpose timer module with accurate 1ms tick
- * This class contains several variants: ['timer_1ms', 'timer']
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
- .name = "timer",
- .sysc = &omap44xx_timer_1ms_sysc,
-};
-
-static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &omap44xx_timer_sysc,
-};
-
-/* timer1 */
-static struct omap_hwmod omap44xx_timer1_hwmod = {
- .name = "timer1",
- .class = &omap44xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "dmt1_clk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer2 */
-static struct omap_hwmod omap44xx_timer2_hwmod = {
- .name = "timer2",
- .class = &omap44xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "cm2_dm2_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer3 */
-static struct omap_hwmod omap44xx_timer3_hwmod = {
- .name = "timer3",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm3_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer4 */
-static struct omap_hwmod omap44xx_timer4_hwmod = {
- .name = "timer4",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm4_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer5 */
-static struct omap_hwmod omap44xx_timer5_hwmod = {
- .name = "timer5",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer5_sync_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer6 */
-static struct omap_hwmod omap44xx_timer6_hwmod = {
- .name = "timer6",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer6_sync_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer7 */
-static struct omap_hwmod omap44xx_timer7_hwmod = {
- .name = "timer7",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer7_sync_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer8 */
-static struct omap_hwmod omap44xx_timer8_hwmod = {
- .name = "timer8",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer8_sync_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer9 */
-static struct omap_hwmod omap44xx_timer9_hwmod = {
- .name = "timer9",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm9_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer10 */
-static struct omap_hwmod omap44xx_timer10_hwmod = {
- .name = "timer10",
- .class = &omap44xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "cm2_dm10_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer11 */
-static struct omap_hwmod omap44xx_timer11_hwmod = {
- .name = "timer11",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm11_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'usb_host_fs' class
- * full-speed usb host controller
- */
-
-/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0210,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
-};
-
-static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
- .name = "usb_host_fs",
- .sysc = &omap44xx_usb_host_fs_sysc,
-};
-
-/* usb_host_fs */
-static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
- .name = "usb_host_fs",
- .class = &omap44xx_usb_host_fs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .main_clk = "usb_host_fs_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'usb_host_hs' class
- * high-speed multi-port usb host controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
- .name = "usb_host_hs",
- .sysc = &omap44xx_usb_host_hs_sysc,
-};
-
-/* usb_host_hs */
-static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
- .name = "usb_host_hs",
- .class = &omap44xx_usb_host_hs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .main_clk = "usb_host_hs_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-
- /*
- * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
- * id: i660
- *
- * Description:
- * In the following configuration :
- * - USBHOST module is set to smart-idle mode
- * - PRCM asserts idle_req to the USBHOST module ( This typically
- * happens when the system is going to a low power mode : all ports
- * have been suspended, the master part of the USBHOST module has
- * entered the standby state, and SW has cut the functional clocks)
- * - an USBHOST interrupt occurs before the module is able to answer
- * idle_ack, typically a remote wakeup IRQ.
- * Then the USB HOST module will enter a deadlock situation where it
- * is no more accessible nor functional.
- *
- * Workaround:
- * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
- */
-
- /*
- * Errata: USB host EHCI may stall when entering smart-standby mode
- * Id: i571
- *
- * Description:
- * When the USBHOST module is set to smart-standby mode, and when it is
- * ready to enter the standby state (i.e. all ports are suspended and
- * all attached devices are in suspend mode), then it can wrongly assert
- * the Mstandby signal too early while there are still some residual OCP
- * transactions ongoing. If this condition occurs, the internal state
- * machine may go to an undefined state and the USB link may be stuck
- * upon the next resume.
- *
- * Workaround:
- * Don't use smart standby; use only force standby,
- * hence HWMOD_SWSUP_MSTANDBY
- */
-
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
-};
-
-/*
- * 'usb_otg_hs' class
- * high-speed on-the-go universal serial bus (usb_otg_hs) controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
- .rev_offs = 0x0400,
- .sysc_offs = 0x0404,
- .syss_offs = 0x0408,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
- .name = "usb_otg_hs",
- .sysc = &omap44xx_usb_otg_hs_sysc,
-};
-
-/* usb_otg_hs */
-static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
- { .role = "xclk", .clk = "usb_otg_hs_xclk" },
-};
-
-static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
- .name = "usb_otg_hs",
- .class = &omap44xx_usb_otg_hs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "usb_otg_hs_ick",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
- .opt_clks = usb_otg_hs_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
-};
-
-/*
- * 'usb_tll_hs' class
- * usb_tll_hs module is the adapter on the usb_host_hs ports
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
- .name = "usb_tll_hs",
- .sysc = &omap44xx_usb_tll_hs_sysc,
-};
-
-static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
- .name = "usb_tll_hs",
- .class = &omap44xx_usb_tll_hs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .main_clk = "usb_tll_hs_ick",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
* interfaces
*/
@@ -2418,22 +668,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dsp -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
- .master = &omap44xx_dss_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_2 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -2466,38 +700,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dma_system -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
- .master = &omap44xx_dma_system_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* fdif -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
- .master = &omap44xx_fdif_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* hsi -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
- .master = &omap44xx_hsi_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* ipu -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
- .master = &omap44xx_ipu_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* iss -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
.master = &omap44xx_iss_hwmod,
@@ -2530,30 +732,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* usb_host_fs -> l3_main_2 */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
- .master = &omap44xx_usb_host_fs_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* usb_host_hs -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
- .master = &omap44xx_usb_host_hs_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* usb_otg_hs -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
- .master = &omap44xx_usb_otg_hs_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
.master = &omap44xx_l3_main_1_hwmod,
@@ -2578,38 +756,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* aess -> l4_abe */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
- .master = &omap44xx_aess_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dsp -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
.master = &omap44xx_l3_main_1_hwmod,
@@ -2650,30 +796,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_abe -> aess */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_aess_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> aess (dma) */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_aess_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_wkup -> counter_32k */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_counter_32k_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_cfg -> ctrl_module_core */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
.master = &omap44xx_l4_cfg_hwmod,
@@ -2714,182 +836,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_dma_system_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> dmic */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_dmic_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dsp -> iva */
-static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_iva_hwmod,
- .clk = "dpll_iva_m5x2_ck",
- .user = OCP_USER_DSP,
-};
-
-/* dsp -> sl2if */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_sl2if_hwmod,
- .clk = "dpll_iva_m5x2_ck",
- .user = OCP_USER_DSP,
-};
-
-/* l4_cfg -> dsp */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_dsp_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_dispc */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_dispc_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_dispc */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_dispc_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_dsi1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_dsi1_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_dsi2 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_dsi2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_dsi2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_dsi2_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_hdmi_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_hdmi_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_rfbi_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_rfbi_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_venc */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_venc_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_venc */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_venc_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> sham */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_sha0_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> elm */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_elm_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> fdif */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_fdif_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_2 -> gpmc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -2898,30 +844,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_per -> hdq1w */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_hdq1w_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> hsi */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_hsi_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> ipu */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_ipu_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_2 -> iss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -2946,78 +868,6 @@
.user = OCP_USER_MPU,
};
-/* l4_wkup -> kbd */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_kbd_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> mailbox */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_mailbox_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcasp */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcasp_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> mcasp (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcasp_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp1_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp2_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp3_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mcbsp4_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcpdm */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcpdm_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_2 -> ocmc_ram */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -3026,14 +876,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> ocp2scp_usb_phy */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* mpu_private -> prcm_mpu */
static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
.master = &omap44xx_mpu_private_hwmod,
@@ -3082,182 +924,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_abe -> slimbus1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_slimbus1_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> slimbus1 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_slimbus1_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> slimbus2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_slimbus2_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> smartreflex_core */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_smartreflex_core_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> smartreflex_iva */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_smartreflex_iva_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> smartreflex_mpu */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_smartreflex_mpu_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> spinlock */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_spinlock_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_timer1_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer2_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer3_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer4_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> timer5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer5_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> timer6 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer6_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> timer7 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer7_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> timer8 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer8_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer9 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer9_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer10 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer10_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer11 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer11_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_host_fs */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_host_fs_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_host_hs */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_host_hs_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_otg_hs */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_otg_hs_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_tll_hs */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_tll_hs_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* mpu -> emif1 */
static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
.master = &omap44xx_mpu_hwmod,
@@ -3280,118 +946,40 @@
&omap44xx_iva__l3_instr,
&omap44xx_l3_main_3__l3_instr,
&omap44xx_ocp_wp_noc__l3_instr,
- &omap44xx_dsp__l3_main_1,
- &omap44xx_dss__l3_main_1,
&omap44xx_l3_main_2__l3_main_1,
&omap44xx_l4_cfg__l3_main_1,
&omap44xx_mpu__l3_main_1,
&omap44xx_debugss__l3_main_2,
- &omap44xx_dma_system__l3_main_2,
- &omap44xx_fdif__l3_main_2,
- &omap44xx_hsi__l3_main_2,
- &omap44xx_ipu__l3_main_2,
&omap44xx_iss__l3_main_2,
&omap44xx_iva__l3_main_2,
&omap44xx_l3_main_1__l3_main_2,
&omap44xx_l4_cfg__l3_main_2,
- /* &omap44xx_usb_host_fs__l3_main_2, */
- &omap44xx_usb_host_hs__l3_main_2,
- &omap44xx_usb_otg_hs__l3_main_2,
&omap44xx_l3_main_1__l3_main_3,
&omap44xx_l3_main_2__l3_main_3,
&omap44xx_l4_cfg__l3_main_3,
- &omap44xx_aess__l4_abe,
- &omap44xx_dsp__l4_abe,
- &omap44xx_l3_main_1__l4_abe,
- &omap44xx_mpu__l4_abe,
&omap44xx_l3_main_1__l4_cfg,
&omap44xx_l3_main_2__l4_per,
&omap44xx_l4_cfg__l4_wkup,
&omap44xx_mpu__mpu_private,
&omap44xx_l4_cfg__ocp_wp_noc,
- &omap44xx_l4_abe__aess,
- &omap44xx_l4_abe__aess_dma,
- &omap44xx_l4_wkup__counter_32k,
&omap44xx_l4_cfg__ctrl_module_core,
&omap44xx_l4_cfg__ctrl_module_pad_core,
&omap44xx_l4_wkup__ctrl_module_wkup,
&omap44xx_l4_wkup__ctrl_module_pad_wkup,
&omap44xx_l3_instr__debugss,
- &omap44xx_l4_cfg__dma_system,
- &omap44xx_l4_abe__dmic,
- &omap44xx_dsp__iva,
- /* &omap44xx_dsp__sl2if, */
- &omap44xx_l4_cfg__dsp,
- &omap44xx_l3_main_2__dss,
- &omap44xx_l4_per__dss,
- &omap44xx_l3_main_2__dss_dispc,
- &omap44xx_l4_per__dss_dispc,
- &omap44xx_l3_main_2__dss_dsi1,
- &omap44xx_l4_per__dss_dsi1,
- &omap44xx_l3_main_2__dss_dsi2,
- &omap44xx_l4_per__dss_dsi2,
- &omap44xx_l3_main_2__dss_hdmi,
- &omap44xx_l4_per__dss_hdmi,
- &omap44xx_l3_main_2__dss_rfbi,
- &omap44xx_l4_per__dss_rfbi,
- &omap44xx_l3_main_2__dss_venc,
- &omap44xx_l4_per__dss_venc,
- &omap44xx_l4_per__elm,
- &omap44xx_l4_cfg__fdif,
&omap44xx_l3_main_2__gpmc,
- &omap44xx_l4_per__hdq1w,
- &omap44xx_l4_cfg__hsi,
- &omap44xx_l3_main_2__ipu,
&omap44xx_l3_main_2__iss,
/* &omap44xx_iva__sl2if, */
&omap44xx_l3_main_2__iva,
- &omap44xx_l4_wkup__kbd,
- &omap44xx_l4_cfg__mailbox,
- &omap44xx_l4_abe__mcasp,
- &omap44xx_l4_abe__mcasp_dma,
- &omap44xx_l4_abe__mcbsp1,
- &omap44xx_l4_abe__mcbsp2,
- &omap44xx_l4_abe__mcbsp3,
- &omap44xx_l4_per__mcbsp4,
- &omap44xx_l4_abe__mcpdm,
- &omap44xx_l3_main_2__mmu_ipu,
- &omap44xx_l4_cfg__mmu_dsp,
&omap44xx_l3_main_2__ocmc_ram,
- &omap44xx_l4_cfg__ocp2scp_usb_phy,
&omap44xx_mpu_private__prcm_mpu,
&omap44xx_l4_wkup__cm_core_aon,
&omap44xx_l4_cfg__cm_core,
&omap44xx_l4_wkup__prm,
&omap44xx_l4_wkup__scrm,
/* &omap44xx_l3_main_2__sl2if, */
- &omap44xx_l4_abe__slimbus1,
- &omap44xx_l4_abe__slimbus1_dma,
- &omap44xx_l4_per__slimbus2,
- &omap44xx_l4_cfg__smartreflex_core,
- &omap44xx_l4_cfg__smartreflex_iva,
- &omap44xx_l4_cfg__smartreflex_mpu,
- &omap44xx_l4_cfg__spinlock,
- &omap44xx_l4_wkup__timer1,
- &omap44xx_l4_per__timer2,
- &omap44xx_l4_per__timer3,
- &omap44xx_l4_per__timer4,
- &omap44xx_l4_abe__timer5,
- &omap44xx_l4_abe__timer6,
- &omap44xx_l4_abe__timer7,
- &omap44xx_l4_abe__timer8,
- &omap44xx_l4_per__timer9,
- &omap44xx_l4_per__timer10,
- &omap44xx_l4_per__timer11,
- /* &omap44xx_l4_cfg__usb_host_fs, */
- &omap44xx_l4_cfg__usb_host_hs,
- &omap44xx_l4_cfg__usb_otg_hs,
- &omap44xx_l4_cfg__usb_tll_hs,
&omap44xx_mpu__emif1,
&omap44xx_mpu__emif2,
- &omap44xx_l3_main_2__aes1,
- &omap44xx_l3_main_2__aes2,
- &omap44xx_l3_main_2__des,
- &omap44xx_l3_main_2__sha0,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 8006b43..85b9ab4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -2,7 +2,7 @@
/*
* Hardware modules present on the OMAP54xx chips
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley
* Benoit Cousson
@@ -17,22 +17,15 @@
#include <linux/io.h>
#include <linux/power/smartreflex.h>
-#include <linux/omap-dma.h>
-
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include "cm1_54xx.h"
#include "cm2_54xx.h"
#include "prm54xx.h"
-#include "wd_timer.h"
/* Base offset for all OMAP5 interrupts external to MPUSS */
#define OMAP54XX_IRQ_GIC_START 32
-/* Base offset for all OMAP5 dma requests */
-#define OMAP54XX_DMA_REQ_START 1
-
-
/*
* IP blocks
*/
@@ -128,19 +121,6 @@
.name = "l4",
};
-/* l4_abe */
-static struct omap_hwmod omap54xx_l4_abe_hwmod = {
- .name = "l4_abe",
- .class = &omap54xx_l4_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
/* l4_cfg */
static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
.name = "l4_cfg",
@@ -201,354 +181,6 @@
};
/*
- * 'counter' class
- * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
- .name = "counter",
- .sysc = &omap54xx_counter_sysc,
-};
-
-/* counter_32k */
-static struct omap_hwmod omap54xx_counter_32k_hwmod = {
- .name = "counter_32k",
- .class = &omap54xx_counter_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wkupaon_iclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'dma' class
- * dma controller for data exchange between memory to memory (i.e. internal or
- * external memory) and gp peripherals to memory or memory to gp peripherals
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap54xx_dma_sysc,
-};
-
-/* dma dev_attr */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-/* dma_system */
-static struct omap_hwmod omap54xx_dma_system_hwmod = {
- .name = "dma_system",
- .class = &omap54xx_dma_hwmod_class,
- .clkdm_name = "dma_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
- },
- },
- .dev_attr = &dma_dev_attr,
-};
-
-/*
- * 'dmic' class
- * digital microphone controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
- .name = "dmic",
- .sysc = &omap54xx_dmic_sysc,
-};
-
-/* dmic */
-static struct omap_hwmod omap54xx_dmic_hwmod = {
- .name = "dmic",
- .class = &omap54xx_dmic_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "dmic_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'dss' class
- * display sub-system
- */
-static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
- .rev_offs = 0x0000,
- .syss_offs = 0x0014,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
- .name = "dss",
- .sysc = &omap54xx_dss_sysc,
- .reset = omap_dss_reset,
-};
-
-/* dss */
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- { .role = "32khz_clk", .clk = "dss_32khz_clk" },
- { .role = "sys_clk", .clk = "dss_sys_clk" },
- { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
-};
-
-static struct omap_hwmod omap54xx_dss_hwmod = {
- .name = "dss_core",
- .class = &omap54xx_dss_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-};
-
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap54xx_dispc_sysc,
-};
-
-/* dss_dispc */
-static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-/* dss_dispc dev_attr */
-static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
- .has_framedonetv_irq = 1,
- .manager_count = 4,
-};
-
-static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &omap54xx_dispc_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_dispc_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
- .dev_attr = &dss_dispc_dev_attr,
- .parent_hwmod = &omap54xx_dss_hwmod,
-};
-
-/*
- * 'dsi1' class
- * display serial interface controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
- .name = "dsi1",
- .sysc = &omap54xx_dsi1_sysc,
-};
-
-/* dss_dsi1_a */
-static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
- .name = "dss_dsi1",
- .class = &omap54xx_dsi1_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_dsi1_a_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
- .parent_hwmod = &omap54xx_dss_hwmod,
-};
-
-/* dss_dsi1_c */
-static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
- .name = "dss_dsi2",
- .class = &omap54xx_dsi1_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_dsi1_c_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
- .parent_hwmod = &omap54xx_dss_hwmod,
-};
-
-/*
- * 'hdmi' class
- * hdmi controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
- .name = "hdmi",
- .sysc = &omap54xx_hdmi_sysc,
-};
-
-static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
- .name = "dss_hdmi",
- .class = &omap54xx_hdmi_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_48mhz_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_hdmi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
- .parent_hwmod = &omap54xx_dss_hwmod,
-};
-
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
- .name = "rfbi",
- .sysc = &omap54xx_rfbi_sysc,
-};
-
-/* dss_rfbi */
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
- { .role = "ick", .clk = "l3_iclk_div" },
-};
-
-static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap54xx_rfbi_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_rfbi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
- .parent_hwmod = &omap54xx_dss_hwmod,
-};
-
-/*
* 'emif' class
* external memory interface no1 (wrapper)
*/
@@ -594,352 +226,8 @@
},
};
-/*
- * 'kbd' class
- * keyboard controller
- */
-static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
- .name = "kbd",
- .sysc = &omap54xx_kbd_sysc,
-};
-
-/* kbd */
-static struct omap_hwmod omap54xx_kbd_hwmod = {
- .name = "kbd",
- .class = &omap54xx_kbd_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors using a
- * queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &omap54xx_mailbox_sysc,
-};
-
-/* mailbox */
-static struct omap_hwmod omap54xx_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap54xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
- .rev_offs = -ENODEV,
- .sysc_offs = 0x008c,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
- .name = "mcbsp",
- .sysc = &omap54xx_mcbsp_sysc,
-};
-
-/* mcbsp1 */
-static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap54xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "mcbsp1_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
-};
-
-/* mcbsp2 */
-static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap54xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "mcbsp2_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
-};
-
-/* mcbsp3 */
-static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
- .name = "mcbsp3",
- .class = &omap54xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "mcbsp3_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
-};
-
-/*
- * 'mcpdm' class
- * multi channel pdm controller (proprietary interface with phoenix power
- * ic)
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
- .name = "mcpdm",
- .sysc = &omap54xx_mcpdm_sysc,
-};
-
-/* mcpdm */
-static struct omap_hwmod omap54xx_mcpdm_hwmod = {
- .name = "mcpdm",
- .class = &omap54xx_mcpdm_hwmod_class,
- .clkdm_name = "abe_clkdm",
- /*
- * It's suspected that the McPDM requires an off-chip main
- * functional clock, controlled via I2C. This IP block is
- * currently reset very early during boot, before I2C is
- * available, so it doesn't seem that we have any choice in
- * the kernel other than to avoid resetting it. XXX This is
- * really a hardware issue workaround: every IP block should
- * be able to source its main functional clock from either
- * on-chip or off-chip sources. McPDM seems to be the only
- * current exception.
- */
-
- .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
- .main_clk = "pad_clks_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mcspi' class
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
- * bus
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
- .name = "mcspi",
- .sysc = &omap54xx_mcspi_sysc,
-};
-
-/* mcspi1 */
-static struct omap_hwmod omap54xx_mcspi1_hwmod = {
- .name = "mcspi1",
- .class = &omap54xx_mcspi_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* mcspi2 */
-static struct omap_hwmod omap54xx_mcspi2_hwmod = {
- .name = "mcspi2",
- .class = &omap54xx_mcspi_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* mcspi3 */
-static struct omap_hwmod omap54xx_mcspi3_hwmod = {
- .name = "mcspi3",
- .class = &omap54xx_mcspi_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* mcspi4 */
-static struct omap_hwmod omap54xx_mcspi4_hwmod = {
- .name = "mcspi4",
- .class = &omap54xx_mcspi_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mmu' class
- * The memory management unit performs virtual to physical address translation
- * for its requestors.
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
- .name = "mmu",
- .sysc = &omap54xx_mmu_sysc,
-};
-
-static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
- { .name = "mmu_cache", .rst_shift = 1 },
-};
-
-static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
- .name = "mmu_dsp",
- .class = &omap54xx_mmu_hwmod_class,
- .clkdm_name = "dsp_clkdm",
- .rst_lines = omap54xx_mmu_dsp_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
- .main_clk = "dpll_iva_h11x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* mmu ipu */
-static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
- { .name = "mmu_cache", .rst_shift = 2 },
-};
-
-static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
- .name = "mmu_ipu",
- .class = &omap54xx_mmu_hwmod_class,
- .clkdm_name = "ipu_clkdm",
- .rst_lines = omap54xx_mmu_ipu_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
- .main_clk = "dpll_core_h22x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
/*
* 'mpu' class
@@ -966,499 +254,6 @@
};
/*
- * 'spinlock' class
- * spinlock provides hardware assistance for synchronizing the processes
- * running on multiple processors
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
- .name = "spinlock",
- .sysc = &omap54xx_spinlock_sysc,
-};
-
-/* spinlock */
-static struct omap_hwmod omap54xx_spinlock_hwmod = {
- .name = "spinlock",
- .class = &omap54xx_spinlock_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'ocp2scp' class
- * bridge to transform ocp interface protocol to scp (serial control port)
- * protocol
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
- .name = "ocp2scp",
- .sysc = &omap54xx_ocp2scp_sysc,
-};
-
-/* ocp2scp1 */
-static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
- .name = "ocp2scp1",
- .class = &omap54xx_ocp2scp_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'timer' class
- * general purpose timer module with accurate 1ms tick
- * This class contains several variants: ['timer_1ms', 'timer']
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
- .name = "timer",
- .sysc = &omap54xx_timer_1ms_sysc,
-};
-
-static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &omap54xx_timer_sysc,
-};
-
-/* timer1 */
-static struct omap_hwmod omap54xx_timer1_hwmod = {
- .name = "timer1",
- .class = &omap54xx_timer_1ms_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "timer1_gfclk_mux",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer2 */
-static struct omap_hwmod omap54xx_timer2_hwmod = {
- .name = "timer2",
- .class = &omap54xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer2_gfclk_mux",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer3 */
-static struct omap_hwmod omap54xx_timer3_hwmod = {
- .name = "timer3",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer3_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer4 */
-static struct omap_hwmod omap54xx_timer4_hwmod = {
- .name = "timer4",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer4_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer5 */
-static struct omap_hwmod omap54xx_timer5_hwmod = {
- .name = "timer5",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer5_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer6 */
-static struct omap_hwmod omap54xx_timer6_hwmod = {
- .name = "timer6",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer6_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer7 */
-static struct omap_hwmod omap54xx_timer7_hwmod = {
- .name = "timer7",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer7_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer8 */
-static struct omap_hwmod omap54xx_timer8_hwmod = {
- .name = "timer8",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer8_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer9 */
-static struct omap_hwmod omap54xx_timer9_hwmod = {
- .name = "timer9",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer9_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer10 */
-static struct omap_hwmod omap54xx_timer10_hwmod = {
- .name = "timer10",
- .class = &omap54xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer10_gfclk_mux",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer11 */
-static struct omap_hwmod omap54xx_timer11_hwmod = {
- .name = "timer11",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer11_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'usb_host_hs' class
- * high-speed multi-port usb host controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
- .name = "usb_host_hs",
- .sysc = &omap54xx_usb_host_hs_sysc,
-};
-
-static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
- .name = "usb_host_hs",
- .class = &omap54xx_usb_host_hs_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- /*
- * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
- * id: i660
- *
- * Description:
- * In the following configuration :
- * - USBHOST module is set to smart-idle mode
- * - PRCM asserts idle_req to the USBHOST module ( This typically
- * happens when the system is going to a low power mode : all ports
- * have been suspended, the master part of the USBHOST module has
- * entered the standby state, and SW has cut the functional clocks)
- * - an USBHOST interrupt occurs before the module is able to answer
- * idle_ack, typically a remote wakeup IRQ.
- * Then the USB HOST module will enter a deadlock situation where it
- * is no more accessible nor functional.
- *
- * Workaround:
- * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
- */
-
- /*
- * Errata: USB host EHCI may stall when entering smart-standby mode
- * Id: i571
- *
- * Description:
- * When the USBHOST module is set to smart-standby mode, and when it is
- * ready to enter the standby state (i.e. all ports are suspended and
- * all attached devices are in suspend mode), then it can wrongly assert
- * the Mstandby signal too early while there are still some residual OCP
- * transactions ongoing. If this condition occurs, the internal state
- * machine may go to an undefined state and the USB link may be stuck
- * upon the next resume.
- *
- * Workaround:
- * Don't use smart standby; use only force standby,
- * hence HWMOD_SWSUP_MSTANDBY
- */
-
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "l3init_60m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'usb_tll_hs' class
- * usb_tll_hs module is the adapter on the usb_host_hs ports
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
- .name = "usb_tll_hs",
- .sysc = &omap54xx_usb_tll_hs_sysc,
-};
-
-static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
- .name = "usb_tll_hs",
- .class = &omap54xx_usb_tll_hs_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'usb_otg_ss' class
- * 2.0 super speed (usb_otg_ss) controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
- .name = "usb_otg_ss",
- .sysc = &omap54xx_usb_otg_ss_sysc,
-};
-
-/* usb_otg_ss */
-static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
- { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
-};
-
-static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
- .name = "usb_otg_ss",
- .class = &omap54xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "dpll_core_h13x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
- .opt_clks = usb_otg_ss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
-};
-
-/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &omap54xx_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable,
-};
-
-/* wd_timer2 */
-static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
- .name = "wd_timer2",
- .class = &omap54xx_wd_timer_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'ocp2scp' class
- * bridge to transform ocp interface protocol to scp (serial control port)
- * protocol
- */
-/* ocp2scp3 */
-static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
-/* l4_cfg -> ocp2scp3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_ocp2scp3_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
- .name = "ocp2scp3",
- .class = &omap54xx_ocp2scp_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
* 'sata' class
* sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
*/
@@ -1539,14 +334,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> mmu_dsp */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_mmu_dsp_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* mpu -> l3_main_1 */
static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
.master = &omap54xx_mpu_hwmod,
@@ -1571,14 +358,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l3_main_2 -> mmu_ipu */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_mmu_ipu_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
.master = &omap54xx_l3_main_1_hwmod,
@@ -1603,22 +382,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l3_main_1 -> l4_abe */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
- .master = &omap54xx_l3_main_1_hwmod,
- .slave = &omap54xx_l4_abe_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> l4_abe */
-static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
- .master = &omap54xx_mpu_hwmod,
- .slave = &omap54xx_l4_abe_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
.master = &omap54xx_l3_main_1_hwmod,
@@ -1651,78 +414,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> counter_32k */
-static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
- .master = &omap54xx_l4_wkup_hwmod,
- .slave = &omap54xx_counter_32k_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_dma_system_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> dmic */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_dmic_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss_dispc */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_dispc_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss_dsi1_a */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_dsi1_a_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss_dsi1_c */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_dsi1_c_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_hdmi_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_rfbi_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* mpu -> emif1 */
static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
.master = &omap54xx_mpu_hwmod,
@@ -1739,86 +430,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> kbd */
-static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
- .master = &omap54xx_l4_wkup_hwmod,
- .slave = &omap54xx_kbd_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> mailbox */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_mailbox_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_mcbsp1_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_mcbsp2_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_mcbsp3_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> mcpdm */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_mcpdm_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_per -> mcspi1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_mcspi1_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcspi2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_mcspi2_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcspi3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_mcspi3_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcspi4 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_mcspi4_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_cfg -> mpu */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
.master = &omap54xx_l4_cfg_hwmod,
@@ -1827,142 +438,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> spinlock */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_spinlock_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> ocp2scp1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_ocp2scp1_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
- .master = &omap54xx_l4_wkup_hwmod,
- .slave = &omap54xx_timer1_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer2_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer3_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer4 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer4_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> timer5 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_timer5_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> timer6 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_timer6_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> timer7 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_timer7_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> timer8 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_timer8_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_per -> timer9 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer9_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer10 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer10_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer11 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer11_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_host_hs */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_usb_host_hs_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_tll_hs */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_usb_tll_hs_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_otg_ss */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_usb_otg_ss_hwmod,
- .clk = "dpll_core_h13x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
- .master = &omap54xx_l4_wkup_hwmod,
- .slave = &omap54xx_wd_timer2_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l3_main_1__dmm,
&omap54xx_l3_main_3__l3_instr,
@@ -1974,54 +449,13 @@
&omap54xx_l3_main_1__l3_main_3,
&omap54xx_l3_main_2__l3_main_3,
&omap54xx_l4_cfg__l3_main_3,
- &omap54xx_l3_main_1__l4_abe,
- &omap54xx_mpu__l4_abe,
&omap54xx_l3_main_1__l4_cfg,
&omap54xx_l3_main_2__l4_per,
&omap54xx_l3_main_1__l4_wkup,
&omap54xx_mpu__mpu_private,
- &omap54xx_l4_wkup__counter_32k,
- &omap54xx_l4_cfg__dma_system,
- &omap54xx_l4_abe__dmic,
- &omap54xx_l4_cfg__mmu_dsp,
- &omap54xx_l3_main_2__dss,
- &omap54xx_l3_main_2__dss_dispc,
- &omap54xx_l3_main_2__dss_dsi1_a,
- &omap54xx_l3_main_2__dss_dsi1_c,
- &omap54xx_l3_main_2__dss_hdmi,
- &omap54xx_l3_main_2__dss_rfbi,
&omap54xx_mpu__emif1,
&omap54xx_mpu__emif2,
- &omap54xx_l3_main_2__mmu_ipu,
- &omap54xx_l4_wkup__kbd,
- &omap54xx_l4_cfg__mailbox,
- &omap54xx_l4_abe__mcbsp1,
- &omap54xx_l4_abe__mcbsp2,
- &omap54xx_l4_abe__mcbsp3,
- &omap54xx_l4_abe__mcpdm,
- &omap54xx_l4_per__mcspi1,
- &omap54xx_l4_per__mcspi2,
- &omap54xx_l4_per__mcspi3,
- &omap54xx_l4_per__mcspi4,
&omap54xx_l4_cfg__mpu,
- &omap54xx_l4_cfg__spinlock,
- &omap54xx_l4_cfg__ocp2scp1,
- &omap54xx_l4_wkup__timer1,
- &omap54xx_l4_per__timer2,
- &omap54xx_l4_per__timer3,
- &omap54xx_l4_per__timer4,
- &omap54xx_l4_abe__timer5,
- &omap54xx_l4_abe__timer6,
- &omap54xx_l4_abe__timer7,
- &omap54xx_l4_abe__timer8,
- &omap54xx_l4_per__timer9,
- &omap54xx_l4_per__timer10,
- &omap54xx_l4_per__timer11,
- &omap54xx_l4_cfg__usb_host_hs,
- &omap54xx_l4_cfg__usb_tll_hs,
- &omap54xx_l4_cfg__usb_otg_ss,
- &omap54xx_l4_wkup__wd_timer2,
- &omap54xx_l4_cfg__ocp2scp3,
&omap54xx_l4_cfg__sata,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index e5bd549..05e163c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -2,7 +2,7 @@
/*
* Hardware modules present on the DRA7xx chips
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley
* Benoit Cousson
@@ -15,25 +15,17 @@
*/
#include <linux/io.h>
-#include <linux/power/smartreflex.h>
-
-#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include "cm1_7xx.h"
#include "cm2_7xx.h"
#include "prm7xx.h"
-#include "wd_timer.h"
#include "soc.h"
/* Base offset for all DRA7XX interrupts external to MPUSS */
#define DRA7XX_IRQ_GIC_START 32
-/* Base offset for all DRA7XX dma requests */
-#define DRA7XX_DMA_REQ_START 1
-
-
/*
* IP blocks
*/
@@ -230,40 +222,6 @@
};
/*
- * 'counter' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
- .name = "counter",
- .sysc = &dra7xx_counter_sysc,
-};
-
-/* counter_32k */
-static struct omap_hwmod dra7xx_counter_32k_hwmod = {
- .name = "counter_32k",
- .class = &dra7xx_counter_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wkupaon_iclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
* 'ctrl_module' class
*
*/
@@ -285,456 +243,6 @@
};
/*
- * 'dcan' class
- *
- */
-
-static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
- .name = "dcan",
-};
-
-/* dcan1 */
-static struct omap_hwmod dra7xx_dcan1_hwmod = {
- .name = "dcan1",
- .class = &dra7xx_dcan_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "dcan1_sys_clk_mux",
- .flags = HWMOD_CLKDM_NOAUTO,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* dcan2 */
-static struct omap_hwmod dra7xx_dcan2_hwmod = {
- .name = "dcan2",
- .class = &dra7xx_dcan_hwmod_class,
- .clkdm_name = "l4per2_clkdm",
- .main_clk = "sys_clkin1",
- .flags = HWMOD_CLKDM_NOAUTO,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* pwmss */
-static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x4,
- .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_RESET_STATUS,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-/*
- * epwmss class
- */
-static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
- .name = "epwmss",
- .sysc = &dra7xx_epwmss_sysc,
-};
-
-/* epwmss0 */
-static struct omap_hwmod dra7xx_epwmss0_hwmod = {
- .name = "epwmss0",
- .class = &dra7xx_epwmss_hwmod_class,
- .clkdm_name = "l4per2_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
- },
- },
-};
-
-/* epwmss1 */
-static struct omap_hwmod dra7xx_epwmss1_hwmod = {
- .name = "epwmss1",
- .class = &dra7xx_epwmss_hwmod_class,
- .clkdm_name = "l4per2_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
- },
- },
-};
-
-/* epwmss2 */
-static struct omap_hwmod dra7xx_epwmss2_hwmod = {
- .name = "epwmss2",
- .class = &dra7xx_epwmss_hwmod_class,
- .clkdm_name = "l4per2_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'dma' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &dra7xx_dma_sysc,
-};
-
-/* dma dev_attr */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-/* dma_system */
-static struct omap_hwmod dra7xx_dma_system_hwmod = {
- .name = "dma_system",
- .class = &dra7xx_dma_hwmod_class,
- .clkdm_name = "dma_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
- },
- },
- .dev_attr = &dma_dev_attr,
-};
-
-/*
- * 'tpcc' class
- *
- */
-static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
- .name = "tpcc",
-};
-
-static struct omap_hwmod dra7xx_tpcc_hwmod = {
- .name = "tpcc",
- .class = &dra7xx_tpcc_hwmod_class,
- .clkdm_name = "l3main1_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'tptc' class
- *
- */
-static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
- .name = "tptc",
-};
-
-/* tptc0 */
-static struct omap_hwmod dra7xx_tptc0_hwmod = {
- .name = "tptc0",
- .class = &dra7xx_tptc_hwmod_class,
- .clkdm_name = "l3main1_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* tptc1 */
-static struct omap_hwmod dra7xx_tptc1_hwmod = {
- .name = "tptc1",
- .class = &dra7xx_tptc_hwmod_class,
- .clkdm_name = "l3main1_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'dss' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
- .rev_offs = 0x0000,
- .syss_offs = 0x0014,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
- .name = "dss",
- .sysc = &dra7xx_dss_sysc,
- .reset = omap_dss_reset,
-};
-
-/* dss */
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- { .role = "dss_clk", .clk = "dss_dss_clk" },
- { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
- { .role = "32khz_clk", .clk = "dss_32khz_clk" },
- { .role = "video2_clk", .clk = "dss_video2_clk" },
- { .role = "video1_clk", .clk = "dss_video1_clk" },
- { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
- { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
-};
-
-static struct omap_hwmod dra7xx_dss_hwmod = {
- .name = "dss_core",
- .class = &dra7xx_dss_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-};
-
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &dra7xx_dispc_sysc,
-};
-
-/* dss_dispc */
-/* dss_dispc dev_attr */
-static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
- .has_framedonetv_irq = 1,
- .manager_count = 4,
-};
-
-static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &dra7xx_dispc_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .dev_attr = &dss_dispc_dev_attr,
- .parent_hwmod = &dra7xx_dss_hwmod,
-};
-
-/*
- * 'hdmi' class
- * hdmi controller
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
- .name = "hdmi",
- .sysc = &dra7xx_hdmi_sysc,
-};
-
-/* dss_hdmi */
-
-static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_hdmi_clk" },
-};
-
-static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
- .name = "dss_hdmi",
- .class = &dra7xx_hdmi_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_48mhz_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_hdmi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
- .parent_hwmod = &dra7xx_dss_hwmod,
-};
-
-/* AES (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
- .rev_offs = 0x0080,
- .sysc_offs = 0x0084,
- .syss_offs = 0x0088,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
- .name = "aes",
- .sysc = &dra7xx_aes_sysc,
-};
-
-/* AES1 */
-static struct omap_hwmod dra7xx_aes1_hwmod = {
- .name = "aes1",
- .class = &dra7xx_aes_hwmod_class,
- .clkdm_name = "l4sec_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* AES2 */
-static struct omap_hwmod dra7xx_aes2_hwmod = {
- .name = "aes2",
- .class = &dra7xx_aes_hwmod_class,
- .clkdm_name = "l4sec_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* sha0 HIB2 (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
- .rev_offs = 0x100,
- .sysc_offs = 0x110,
- .syss_offs = 0x114,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
- .name = "sham",
- .sysc = &dra7xx_sha0_sysc,
-};
-
-struct omap_hwmod dra7xx_sha0_hwmod = {
- .name = "sham",
- .class = &dra7xx_sha0_hwmod_class,
- .clkdm_name = "l4sec_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'elm' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
- .name = "elm",
- .sysc = &dra7xx_elm_sysc,
-};
-
-/* elm */
-
-static struct omap_hwmod dra7xx_elm_hwmod = {
- .name = "elm",
- .class = &dra7xx_elm_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
* 'gpmc' class
*
*/
@@ -772,229 +280,7 @@
},
};
-/*
- * 'hdq1w' class
- *
- */
-static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0014,
- .syss_offs = 0x0018,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
- .name = "hdq1w",
- .sysc = &dra7xx_hdq1w_sysc,
-};
-
-/* hdq1w */
-
-static struct omap_hwmod dra7xx_hdq1w_hwmod = {
- .name = "hdq1w",
- .class = &dra7xx_hdq1w_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .flags = HWMOD_INIT_NO_RESET,
- .main_clk = "func_12m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mailbox' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &dra7xx_mailbox_sysc,
-};
-
-/* mailbox1 */
-static struct omap_hwmod dra7xx_mailbox1_hwmod = {
- .name = "mailbox1",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox2 */
-static struct omap_hwmod dra7xx_mailbox2_hwmod = {
- .name = "mailbox2",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox3 */
-static struct omap_hwmod dra7xx_mailbox3_hwmod = {
- .name = "mailbox3",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox4 */
-static struct omap_hwmod dra7xx_mailbox4_hwmod = {
- .name = "mailbox4",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox5 */
-static struct omap_hwmod dra7xx_mailbox5_hwmod = {
- .name = "mailbox5",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox6 */
-static struct omap_hwmod dra7xx_mailbox6_hwmod = {
- .name = "mailbox6",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox7 */
-static struct omap_hwmod dra7xx_mailbox7_hwmod = {
- .name = "mailbox7",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox8 */
-static struct omap_hwmod dra7xx_mailbox8_hwmod = {
- .name = "mailbox8",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox9 */
-static struct omap_hwmod dra7xx_mailbox9_hwmod = {
- .name = "mailbox9",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox10 */
-static struct omap_hwmod dra7xx_mailbox10_hwmod = {
- .name = "mailbox10",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox11 */
-static struct omap_hwmod dra7xx_mailbox11_hwmod = {
- .name = "mailbox11",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox12 */
-static struct omap_hwmod dra7xx_mailbox12_hwmod = {
- .name = "mailbox12",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox13 */
-static struct omap_hwmod dra7xx_mailbox13_hwmod = {
- .name = "mailbox13",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
- },
- },
-};
/*
* 'mpu' class
@@ -1020,55 +306,6 @@
},
};
-/*
- * 'ocp2scp' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
- .name = "ocp2scp",
- .sysc = &dra7xx_ocp2scp_sysc,
-};
-
-/* ocp2scp1 */
-static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
- .name = "ocp2scp1",
- .class = &dra7xx_ocp2scp_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* ocp2scp3 */
-static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
- .name = "ocp2scp3",
- .class = &dra7xx_ocp2scp_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
/*
* 'PCIE' class
@@ -1182,41 +419,6 @@
};
/*
- * 'rtcss' class
- *
- */
-static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
- .rev_offs = 0x0074,
- .sysc_offs = 0x0078,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
- .name = "rtcss",
- .sysc = &dra7xx_rtcss_sysc,
- .unlock = &omap_hwmod_rtc_unlock,
- .lock = &omap_hwmod_rtc_lock,
-};
-
-/* rtcss */
-static struct omap_hwmod dra7xx_rtcss_hwmod = {
- .name = "rtcss",
- .class = &dra7xx_rtcss_hwmod_class,
- .clkdm_name = "rtc_clkdm",
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
* 'sata' class
*
*/
@@ -1255,530 +457,6 @@
};
/*
- * 'smartreflex' class
- *
- */
-
-/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
- .rev_offs = -ENODEV,
- .sysc_offs = 0x0038,
- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap36xx_sr_sysc_fields,
-};
-
-static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
- .name = "smartreflex",
- .sysc = &dra7xx_smartreflex_sysc,
-};
-
-/* smartreflex_core */
-/* smartreflex_core dev_attr */
-static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
- .sensor_voltdm_name = "core",
-};
-
-static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
- .name = "smartreflex_core",
- .class = &dra7xx_smartreflex_hwmod_class,
- .clkdm_name = "coreaon_clkdm",
- .main_clk = "wkupaon_iclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .dev_attr = &smartreflex_core_dev_attr,
-};
-
-/* smartreflex_mpu */
-/* smartreflex_mpu dev_attr */
-static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
- .sensor_voltdm_name = "mpu",
-};
-
-static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
- .name = "smartreflex_mpu",
- .class = &dra7xx_smartreflex_hwmod_class,
- .clkdm_name = "coreaon_clkdm",
- .main_clk = "wkupaon_iclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .dev_attr = &smartreflex_mpu_dev_attr,
-};
-
-/*
- * 'spinlock' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
- .name = "spinlock",
- .sysc = &dra7xx_spinlock_sysc,
-};
-
-/* spinlock */
-static struct omap_hwmod dra7xx_spinlock_hwmod = {
- .name = "spinlock",
- .class = &dra7xx_spinlock_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'timer' class
- *
- * This class contains several variants: ['timer_1ms', 'timer_secure',
- * 'timer']
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
- .name = "timer",
- .sysc = &dra7xx_timer_1ms_sysc,
-};
-
-static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &dra7xx_timer_sysc,
-};
-
-/* timer1 */
-static struct omap_hwmod dra7xx_timer1_hwmod = {
- .name = "timer1",
- .class = &dra7xx_timer_1ms_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "timer1_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer2 */
-static struct omap_hwmod dra7xx_timer2_hwmod = {
- .name = "timer2",
- .class = &dra7xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer2_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer3 */
-static struct omap_hwmod dra7xx_timer3_hwmod = {
- .name = "timer3",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer3_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer4 */
-static struct omap_hwmod dra7xx_timer4_hwmod = {
- .name = "timer4",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer4_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer5 */
-static struct omap_hwmod dra7xx_timer5_hwmod = {
- .name = "timer5",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "ipu_clkdm",
- .main_clk = "timer5_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer6 */
-static struct omap_hwmod dra7xx_timer6_hwmod = {
- .name = "timer6",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "ipu_clkdm",
- .main_clk = "timer6_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer7 */
-static struct omap_hwmod dra7xx_timer7_hwmod = {
- .name = "timer7",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "ipu_clkdm",
- .main_clk = "timer7_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer8 */
-static struct omap_hwmod dra7xx_timer8_hwmod = {
- .name = "timer8",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "ipu_clkdm",
- .main_clk = "timer8_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer9 */
-static struct omap_hwmod dra7xx_timer9_hwmod = {
- .name = "timer9",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer9_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer10 */
-static struct omap_hwmod dra7xx_timer10_hwmod = {
- .name = "timer10",
- .class = &dra7xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer10_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer11 */
-static struct omap_hwmod dra7xx_timer11_hwmod = {
- .name = "timer11",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer11_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer12 */
-static struct omap_hwmod dra7xx_timer12_hwmod = {
- .name = "timer12",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "secure_32k_clk_src_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
- },
- },
-};
-
-/* timer13 */
-static struct omap_hwmod dra7xx_timer13_hwmod = {
- .name = "timer13",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per3_clkdm",
- .main_clk = "timer13_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer14 */
-static struct omap_hwmod dra7xx_timer14_hwmod = {
- .name = "timer14",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per3_clkdm",
- .main_clk = "timer14_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer15 */
-static struct omap_hwmod dra7xx_timer15_hwmod = {
- .name = "timer15",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per3_clkdm",
- .main_clk = "timer15_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer16 */
-static struct omap_hwmod dra7xx_timer16_hwmod = {
- .name = "timer16",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per3_clkdm",
- .main_clk = "timer16_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* DES (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
- .rev_offs = 0x0030,
- .sysc_offs = 0x0034,
- .syss_offs = 0x0038,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class dra7xx_des_hwmod_class = {
- .name = "des",
- .sysc = &dra7xx_des_sysc,
-};
-
-/* DES */
-static struct omap_hwmod dra7xx_des_hwmod = {
- .name = "des",
- .class = &dra7xx_des_hwmod_class,
- .clkdm_name = "l4sec_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* rng */
-static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
- .rev_offs = 0x1fe0,
- .sysc_offs = 0x1fe4,
- .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
- .idlemodes = SIDLE_FORCE | SIDLE_NO,
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
- .name = "rng",
- .sysc = &dra7xx_rng_sysc,
-};
-
-static struct omap_hwmod dra7xx_rng_hwmod = {
- .name = "rng",
- .class = &dra7xx_rng_hwmod_class,
- .flags = HWMOD_SWSUP_SIDLE,
- .clkdm_name = "l4sec_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'usb_otg_ss' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
- .name = "usb_otg_ss",
- .sysc = &dra7xx_usb_otg_ss_sysc,
-};
-
-/* usb_otg_ss1 */
-static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
- { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
-};
-
-static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
- .name = "usb_otg_ss1",
- .class = &dra7xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "dpll_core_h13x2_ck",
- .flags = HWMOD_CLKDM_NOAUTO,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
- .opt_clks = usb_otg_ss1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
-};
-
-/* usb_otg_ss2 */
-static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
- { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
-};
-
-static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
- .name = "usb_otg_ss2",
- .class = &dra7xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "dpll_core_h13x2_ck",
- .flags = HWMOD_CLKDM_NOAUTO,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
- .opt_clks = usb_otg_ss2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
-};
-
-/* usb_otg_ss3 */
-static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
- .name = "usb_otg_ss3",
- .class = &dra7xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "dpll_core_h13x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* usb_otg_ss4 */
-static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
- .name = "usb_otg_ss4",
- .class = &dra7xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "dpll_core_h13x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
* 'vcp' class
*
*/
@@ -1815,43 +493,6 @@
},
};
-/*
- * 'wd_timer' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &dra7xx_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable,
- .reset = &omap2_wd_timer_reset,
-};
-
-/* wd_timer2 */
-static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
- .name = "wd_timer2",
- .class = &dra7xx_wd_timer_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
/*
@@ -1962,14 +603,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> counter_32k */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_counter_32k_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_wkup -> ctrl_module_wkup */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
.master = &dra7xx_l4_wkup_hwmod,
@@ -1978,110 +611,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> dcan1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_dcan1_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> dcan2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_dcan2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_dma_system_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> tpcc */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_tpcc_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_1 -> tptc0 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_tptc0_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_1 -> tptc1 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_tptc1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_1 -> dss */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_dss_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> dispc */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_dss_dispc_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> dispc */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_dss_hdmi_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> aes1 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_aes1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> aes2 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_aes2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> sha0 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_sha0_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> elm */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_elm_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> gpmc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
.master = &dra7xx_l3_main_1_hwmod,
@@ -2090,118 +619,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_per1 -> hdq1w */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_hdq1w_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> mailbox1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_mailbox1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox3_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox4_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox5 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox5_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox6 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox6_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox7 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox7_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox8 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox8_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox9 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox9_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox10 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox10_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox11 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox11_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox12 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox12_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox13 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox13_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_cfg -> mpu */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2210,22 +627,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> ocp2scp1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_ocp2scp1_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> ocp2scp3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_ocp2scp3_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> pciess1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
.master = &dra7xx_l3_main_1_hwmod,
@@ -2266,14 +667,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_per3 -> rtcss */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_rtcss_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_cfg -> sata */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2282,205 +675,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> smartreflex_core */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_smartreflex_core_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> smartreflex_mpu */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_smartreflex_mpu_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> spinlock */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_spinlock_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_timer1_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer3_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer4_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer5 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer5_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer6 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer6_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer7 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer7_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer8 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer8_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer9 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer9_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer10 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer10_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer11 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer11_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> timer12 */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_timer12_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer13 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer13_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer14 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer14_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer15 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer15_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer16 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer16_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> des */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_des_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> rng */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_rng_hwmod,
- .user = OCP_USER_MPU,
-};
-
-/* l4_per3 -> usb_otg_ss1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_usb_otg_ss1_hwmod,
- .clk = "dpll_core_h13x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> usb_otg_ss2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_usb_otg_ss2_hwmod,
- .clk = "dpll_core_h13x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> usb_otg_ss3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_usb_otg_ss3_hwmod,
- .clk = "dpll_core_h13x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> usb_otg_ss4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_usb_otg_ss4_hwmod,
- .clk = "dpll_core_h13x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> vcp1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
.master = &dra7xx_l3_main_1_hwmod,
@@ -2513,38 +707,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_wd_timer2_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> epwmss0 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_epwmss0_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l4_per2 -> epwmss1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_epwmss1_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l4_per2 -> epwmss2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_epwmss2_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__dmm,
&dra7xx_l3_main_2__l3_instr,
@@ -2559,106 +721,28 @@
&dra7xx_l3_main_1__l4_wkup,
&dra7xx_l4_per2__atl,
&dra7xx_l3_main_1__bb2d,
- &dra7xx_l4_wkup__counter_32k,
&dra7xx_l4_wkup__ctrl_module_wkup,
- &dra7xx_l4_wkup__dcan1,
- &dra7xx_l4_per2__dcan2,
- &dra7xx_l4_cfg__dma_system,
- &dra7xx_l3_main_1__tpcc,
- &dra7xx_l3_main_1__tptc0,
- &dra7xx_l3_main_1__tptc1,
- &dra7xx_l3_main_1__dss,
- &dra7xx_l3_main_1__dispc,
- &dra7xx_l3_main_1__hdmi,
- &dra7xx_l3_main_1__aes1,
- &dra7xx_l3_main_1__aes2,
- &dra7xx_l3_main_1__sha0,
- &dra7xx_l4_per1__elm,
&dra7xx_l3_main_1__gpmc,
- &dra7xx_l4_per1__hdq1w,
- &dra7xx_l4_cfg__mailbox1,
- &dra7xx_l4_per3__mailbox2,
- &dra7xx_l4_per3__mailbox3,
- &dra7xx_l4_per3__mailbox4,
- &dra7xx_l4_per3__mailbox5,
- &dra7xx_l4_per3__mailbox6,
- &dra7xx_l4_per3__mailbox7,
- &dra7xx_l4_per3__mailbox8,
- &dra7xx_l4_per3__mailbox9,
- &dra7xx_l4_per3__mailbox10,
- &dra7xx_l4_per3__mailbox11,
- &dra7xx_l4_per3__mailbox12,
- &dra7xx_l4_per3__mailbox13,
&dra7xx_l4_cfg__mpu,
- &dra7xx_l4_cfg__ocp2scp1,
- &dra7xx_l4_cfg__ocp2scp3,
&dra7xx_l3_main_1__pciess1,
&dra7xx_l4_cfg__pciess1,
&dra7xx_l3_main_1__pciess2,
&dra7xx_l4_cfg__pciess2,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
- &dra7xx_l4_cfg__smartreflex_core,
- &dra7xx_l4_cfg__smartreflex_mpu,
- &dra7xx_l4_cfg__spinlock,
- &dra7xx_l4_wkup__timer1,
- &dra7xx_l4_per1__timer2,
- &dra7xx_l4_per1__timer3,
- &dra7xx_l4_per1__timer4,
- &dra7xx_l4_per3__timer5,
- &dra7xx_l4_per3__timer6,
- &dra7xx_l4_per3__timer7,
- &dra7xx_l4_per3__timer8,
- &dra7xx_l4_per1__timer9,
- &dra7xx_l4_per1__timer10,
- &dra7xx_l4_per1__timer11,
- &dra7xx_l4_per3__timer13,
- &dra7xx_l4_per3__timer14,
- &dra7xx_l4_per3__timer15,
- &dra7xx_l4_per3__timer16,
- &dra7xx_l4_per1__des,
- &dra7xx_l4_per3__usb_otg_ss1,
- &dra7xx_l4_per3__usb_otg_ss2,
- &dra7xx_l4_per3__usb_otg_ss3,
&dra7xx_l3_main_1__vcp1,
&dra7xx_l4_per2__vcp1,
&dra7xx_l3_main_1__vcp2,
&dra7xx_l4_per2__vcp2,
- &dra7xx_l4_wkup__wd_timer2,
- &dra7xx_l4_per2__epwmss0,
- &dra7xx_l4_per2__epwmss1,
- &dra7xx_l4_per2__epwmss2,
- NULL,
-};
-
-/* GP-only hwmod links */
-static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
- &dra7xx_l4_wkup__timer12,
- &dra7xx_l4_per1__rng,
NULL,
};
/* SoC variant specific hwmod links */
-static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
- &dra7xx_l4_per3__usb_otg_ss4,
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
- &dra7xx_l4_per3__usb_otg_ss4,
- NULL,
-};
-
static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
NULL,
};
static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
- &dra7xx_l4_per3__rtcss,
NULL,
};
@@ -2670,25 +754,15 @@
ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
if (!ret && soc_is_dra74x()) {
- ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
- if (!ret)
- ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
+ ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
} else if (!ret && soc_is_dra72x()) {
ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
if (!ret && !of_machine_is_compatible("ti,dra718"))
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
} else if (!ret && soc_is_dra76x()) {
- ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
-
- if (!ret && soc_is_dra76x_acd()) {
- ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
- } else if (!ret && soc_is_dra76x_abz()) {
+ if (!ret && soc_is_dra76x_abz())
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
- }
}
- if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
- ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
-
return ret;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index 83230d9..450ab99 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -1,7 +1,7 @@
/*
* DM81xx hwmod data.
*
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
*
* This program is free software; you can redistribute it and/or
@@ -129,13 +129,6 @@
.flags = HWMOD_NO_IDLEST,
};
-static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
- .name = "l3_fast",
- .clkdm_name = "alwon_l3_fast_clkdm",
- .class = &l3_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
/*
* L4 standard peripherals, see TRM table 1-12 for devices using this.
* See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
@@ -697,76 +690,6 @@
.sysc = &dm816x_timer_sysc,
};
-static struct omap_hwmod dm814x_timer1_hwmod = {
- .name = "timer1",
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "timer1_fck",
- .class = &dm816x_timer_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
-static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
- .master = &dm81xx_l4_ls_hwmod,
- .slave = &dm814x_timer1_hwmod,
- .clk = "sysclk6_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod dm816x_timer1_hwmod = {
- .name = "timer1",
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "timer1_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .class = &dm816x_timer_hwmod_class,
-};
-
-static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
- .master = &dm81xx_l4_ls_hwmod,
- .slave = &dm816x_timer1_hwmod,
- .clk = "sysclk6_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod dm814x_timer2_hwmod = {
- .name = "timer2",
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "timer2_fck",
- .class = &dm816x_timer_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
-static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
- .master = &dm81xx_l4_ls_hwmod,
- .slave = &dm814x_timer2_hwmod,
- .clk = "sysclk6_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod dm816x_timer2_hwmod = {
- .name = "timer2",
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "timer2_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .class = &dm816x_timer_hwmod_class,
-};
-
-static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
- .master = &dm81xx_l4_ls_hwmod,
- .slave = &dm816x_timer2_hwmod,
- .clk = "sysclk6_ck",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod dm816x_timer3_hwmod = {
.name = "timer3",
.clkdm_name = "alwon_l3s_clkdm",
@@ -867,62 +790,6 @@
.user = OCP_USER_MPU,
};
-/* CPSW on dm814x */
-static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x8,
- .syss_offs = 0x4,
- .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSS_HAS_RESET_STATUS,
- .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
- MSTANDBY_NO,
- .sysc_fields = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
- .name = "cpgmac0",
- .sysc = &dm814x_cpgmac_sysc,
-};
-
-static struct omap_hwmod dm814x_cpgmac0_hwmod = {
- .name = "cpgmac0",
- .class = &dm814x_cpgmac0_hwmod_class,
- .clkdm_name = "alwon_ethernet_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "cpsw_125mhz_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
- .name = "davinci_mdio",
-};
-
-static struct omap_hwmod dm814x_mdio_hwmod = {
- .name = "davinci_mdio",
- .class = &dm814x_mdio_hwmod_class,
- .clkdm_name = "alwon_ethernet_clkdm",
- .main_clk = "cpsw_125mhz_gclk",
-};
-
-static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
- .master = &dm81xx_l4_hs_hwmod,
- .slave = &dm814x_cpgmac0_hwmod,
- .clk = "cpsw_125mhz_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
- .master = &dm814x_cpgmac0_hwmod,
- .slave = &dm814x_mdio_hwmod,
- .user = OCP_USER_MPU,
- .flags = HWMOD_NO_IDLEST,
-};
-
/* EMAC Ethernet */
static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
.rev_offs = 0x0,
@@ -1321,154 +1188,6 @@
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
- .name = "tpcc",
-};
-
-static struct omap_hwmod dm81xx_tpcc_hwmod = {
- .name = "tpcc",
- .class = &dm81xx_tpcc_hwmod_class,
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "sysclk4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
- .master = &dm81xx_alwon_l3_fast_hwmod,
- .slave = &dm81xx_tpcc_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
- .name = "tptc0",
-};
-
-static struct omap_hwmod dm81xx_tptc0_hwmod = {
- .name = "tptc0",
- .class = &dm81xx_tptc0_hwmod_class,
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "sysclk4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
- .master = &dm81xx_alwon_l3_fast_hwmod,
- .slave = &dm81xx_tptc0_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
- .master = &dm81xx_tptc0_hwmod,
- .slave = &dm81xx_alwon_l3_fast_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
- .name = "tptc1",
-};
-
-static struct omap_hwmod dm81xx_tptc1_hwmod = {
- .name = "tptc1",
- .class = &dm81xx_tptc1_hwmod_class,
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "sysclk4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
- .master = &dm81xx_alwon_l3_fast_hwmod,
- .slave = &dm81xx_tptc1_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
- .master = &dm81xx_tptc1_hwmod,
- .slave = &dm81xx_alwon_l3_fast_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
- .name = "tptc2",
-};
-
-static struct omap_hwmod dm81xx_tptc2_hwmod = {
- .name = "tptc2",
- .class = &dm81xx_tptc2_hwmod_class,
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "sysclk4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
- .master = &dm81xx_alwon_l3_fast_hwmod,
- .slave = &dm81xx_tptc2_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
- .master = &dm81xx_tptc2_hwmod,
- .slave = &dm81xx_alwon_l3_fast_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
- .name = "tptc3",
-};
-
-static struct omap_hwmod dm81xx_tptc3_hwmod = {
- .name = "tptc3",
- .class = &dm81xx_tptc3_hwmod_class,
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "sysclk4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
- .master = &dm81xx_alwon_l3_fast_hwmod,
- .slave = &dm81xx_tptc3_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
- .master = &dm81xx_tptc3_hwmod,
- .slave = &dm81xx_alwon_l3_fast_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
/*
* REVISIT: Test and enable the following once clocks work:
* dm81xx_l4_ls__mailbox
@@ -1499,19 +1218,6 @@
&dm814x_l4_ls__mmc1,
&dm814x_l4_ls__mmc2,
&ti81xx_l4_ls__rtc,
- &dm81xx_alwon_l3_fast__tpcc,
- &dm81xx_alwon_l3_fast__tptc0,
- &dm81xx_alwon_l3_fast__tptc1,
- &dm81xx_alwon_l3_fast__tptc2,
- &dm81xx_alwon_l3_fast__tptc3,
- &dm81xx_tptc0__alwon_l3_fast,
- &dm81xx_tptc1__alwon_l3_fast,
- &dm81xx_tptc2__alwon_l3_fast,
- &dm81xx_tptc3__alwon_l3_fast,
- &dm814x_l4_ls__timer1,
- &dm814x_l4_ls__timer2,
- &dm814x_l4_hs__cpgmac0,
- &dm814x_cpgmac0__mdio,
&dm81xx_alwon_l3_slow__gpmc,
&dm814x_default_l3_slow__usbss,
&dm814x_alwon_l3_med__mmc3,
@@ -1540,8 +1246,6 @@
&dm81xx_l4_ls__elm,
&ti81xx_l4_ls__rtc,
&dm816x_l4_ls__mmc1,
- &dm816x_l4_ls__timer1,
- &dm816x_l4_ls__timer2,
&dm816x_l4_ls__timer3,
&dm816x_l4_ls__timer4,
&dm816x_l4_ls__timer5,
@@ -1554,15 +1258,6 @@
&dm81xx_emac0__mdio,
&dm816x_l4_hs__emac1,
&dm81xx_l4_hs__sata,
- &dm81xx_alwon_l3_fast__tpcc,
- &dm81xx_alwon_l3_fast__tptc0,
- &dm81xx_alwon_l3_fast__tptc1,
- &dm81xx_alwon_l3_fast__tptc2,
- &dm81xx_alwon_l3_fast__tptc3,
- &dm81xx_tptc0__alwon_l3_fast,
- &dm81xx_tptc1__alwon_l3_fast,
- &dm81xx_tptc2__alwon_l3_fast,
- &dm81xx_tptc3__alwon_l3_fast,
&dm81xx_alwon_l3_slow__gpmc,
&dm816x_default_l3_slow__usbss,
NULL,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index ca56563..0045e66 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -21,8 +21,6 @@
extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
extern struct omap_hwmod omap2xxx_mpu_hwmod;
extern struct omap_hwmod omap2xxx_iva_hwmod;
-extern struct omap_hwmod omap2xxx_timer1_hwmod;
-extern struct omap_hwmod omap2xxx_timer2_hwmod;
extern struct omap_hwmod omap2xxx_timer3_hwmod;
extern struct omap_hwmod omap2xxx_timer4_hwmod;
extern struct omap_hwmod omap2xxx_timer5_hwmod;
@@ -47,7 +45,6 @@
extern struct omap_hwmod omap2xxx_gpio4_hwmod;
extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
-extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
extern struct omap_hwmod omap2xxx_gpmc_hwmod;
extern struct omap_hwmod omap2xxx_rng_hwmod;
extern struct omap_hwmod omap2xxx_sham_hwmod;
@@ -98,7 +95,6 @@
extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
-extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mcspi_class;
diff --git a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c
index d5ddba0..143623b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_reset.c
+++ b/arch/arm/mach-omap2/omap_hwmod_reset.c
@@ -26,8 +26,6 @@
#include <linux/kernel.h>
#include <linux/errno.h>
-#include <sound/aess.h>
-
#include "omap_hwmod.h"
#include "common.h"
@@ -41,28 +39,6 @@
#define OMAP_RTC_MAX_READY_TIME 50
/**
- * omap_hwmod_aess_preprogram - enable AESS internal autogating
- * @oh: struct omap_hwmod *
- *
- * The AESS will not IdleAck to the PRCM until its internal autogating
- * is enabled. Since internal autogating is disabled by default after
- * AESS reset, we must enable autogating after the hwmod code resets
- * the AESS. Returns 0.
- */
-int omap_hwmod_aess_preprogram(struct omap_hwmod *oh)
-{
- void __iomem *va;
-
- va = omap_hwmod_get_mpu_rt_va(oh);
- if (!va)
- return -EINVAL;
-
- aess_enable_autogating(va);
-
- return 0;
-}
-
-/**
* omap_rtc_wait_not_busy - Wait for the RTC BUSY flag
* @oh: struct omap_hwmod *
*
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
index 336fdfc..533dd64 100644
--- a/arch/arm/mach-omap2/omap_opp_data.h
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -1,7 +1,7 @@
/*
* OMAP SoC specific OPP Data helpers
*
- * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Copyright (C) 2010 Nokia Corporation.
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d2925e8..6f6a6a6 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -3,7 +3,7 @@
* This file configures the internal USB PHY in OMAP4430. Used
* with TWL6030 transceiver and MUSB on OMAP4430.
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com
* Author: Hema HK <hemahk@ti.com>
*/
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 6787f1e..a642d3b 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -36,11 +36,6 @@
#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
#define OMAP4_VDD_CORE_SR_CMD_REG 0x62
-#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
-#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
-#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
-#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
-
static bool is_offset_valid;
static u8 smps_offset;
@@ -219,7 +214,8 @@
{
struct voltagedomain *voltdm;
- if (!cpu_is_omap44xx())
+ if (!cpu_is_omap44xx() ||
+ of_find_compatible_node(NULL, NULL, "motorola,cpcap"))
return -ENODEV;
voltdm = voltdm_lookup("mpu");
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index c2d459f..b610c5f 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -1,7 +1,7 @@
/*
* OMAP3 OPP table definitions.
*
- * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Copyright (C) 2010-2011 Nokia Corporation.
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index adea43e..d937c5e 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -1,7 +1,7 @@
/*
* OMAP4 OPP table definitions.
*
- * Copyright (C) 2010-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010-2012 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Thara Gopinath
@@ -32,20 +32,22 @@
#define OMAP4430_VDD_MPU_OPP50_UV 1025000
#define OMAP4430_VDD_MPU_OPP100_UV 1200000
-#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000
-#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
+#define OMAP4430_VDD_MPU_OPPTURBO_UV 1325000
+#define OMAP4430_VDD_MPU_OPPNITRO_UV 1388000
+#define OMAP4430_VDD_MPU_OPPNITROSB_UV 1398000
struct omap_volt_data omap443x_vdd_mpu_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
+ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITROSB_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB, 0xfa, 0x27),
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
-#define OMAP4430_VDD_IVA_OPP50_UV 1013000
-#define OMAP4430_VDD_IVA_OPP100_UV 1188000
-#define OMAP4430_VDD_IVA_OPPTURBO_UV 1300000
+#define OMAP4430_VDD_IVA_OPP50_UV 950000
+#define OMAP4430_VDD_IVA_OPP100_UV 1114000
+#define OMAP4430_VDD_IVA_OPPTURBO_UV 1291000
struct omap_volt_data omap443x_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
@@ -54,8 +56,8 @@
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
-#define OMAP4430_VDD_CORE_OPP50_UV 1025000
-#define OMAP4430_VDD_CORE_OPP100_UV 1200000
+#define OMAP4430_VDD_CORE_OPP50_UV 962000
+#define OMAP4430_VDD_CORE_OPP100_UV 1127000
struct omap_volt_data omap443x_vdd_core_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index ca07e31..2a4fe3e 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -10,7 +10,6 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
-#include <linux/ti_wilink_st.h>
#include <linux/wl12xx.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
@@ -24,6 +23,7 @@
#include <linux/platform_data/ti-sysc.h>
#include <linux/platform_data/wkup_m3.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/ti-prm.h>
#include "clockdomain.h"
#include "common.h"
@@ -32,7 +32,6 @@
#include "omap_device.h"
#include "omap-secure.h"
#include "soc.h"
-#include "hsmmc.h"
static struct omap_hsmmc_platform_data __maybe_unused mmc_pdata[2];
@@ -156,53 +155,6 @@
omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
}
-static struct ti_st_plat_data wilink_pdata = {
- .nshutdown_gpio = 137,
- .dev_name = "/dev/ttyO1",
- .flow_cntrl = 1,
- .baud_rate = 300000,
-};
-
-static struct platform_device wl18xx_device = {
- .name = "kim",
- .id = -1,
- .dev = {
- .platform_data = &wilink_pdata,
- }
-};
-
-static struct ti_st_plat_data wilink7_pdata = {
- .nshutdown_gpio = 162,
- .dev_name = "/dev/ttyO1",
- .flow_cntrl = 1,
- .baud_rate = 3000000,
-};
-
-static struct platform_device wl128x_device = {
- .name = "kim",
- .id = -1,
- .dev = {
- .platform_data = &wilink7_pdata,
- }
-};
-
-static struct platform_device btwilink_device = {
- .name = "btwilink",
- .id = -1,
-};
-
-static void __init omap3_igep0020_rev_f_legacy_init(void)
-{
- platform_device_register(&wl18xx_device);
- platform_device_register(&btwilink_device);
-}
-
-static void __init omap3_igep0030_rev_g_legacy_init(void)
-{
- platform_device_register(&wl18xx_device);
- platform_device_register(&btwilink_device);
-}
-
static void __init omap3_evm_legacy_init(void)
{
hsmmc2_internal_input_clk();
@@ -285,7 +237,7 @@
mmc_pdata[0].name = "external";
mmc_pdata[1].name = "internal";
- if (omap_type() == OMAP2_DEVICE_TYPE_SEC) {
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
if (IS_ENABLED(CONFIG_ARM_ERRATA_430973)) {
pr_info("RX-51: Enabling ARM errata 430973 workaround\n");
/* set IBE to 1 */
@@ -305,8 +257,6 @@
static void __init omap3_logicpd_torpedo_init(void)
{
omap3_gpio126_127_129();
- platform_device_register(&wl128x_device);
- platform_device_register(&btwilink_device);
}
/* omap3pandora legacy devices */
@@ -447,10 +397,16 @@
return omap_hwmod_shutdown(cookie->data);
}
+static bool ti_sysc_soc_type_gp(void)
+{
+ return omap_type() == OMAP2_DEVICE_TYPE_GP;
+}
+
static struct of_dev_auxdata omap_auxdata_lookup[];
static struct ti_sysc_platform_data ti_sysc_pdata = {
.auxdata = omap_auxdata_lookup,
+ .soc_type_gp = ti_sysc_soc_type_gp,
.init_clockdomain = ti_sysc_clkdm_init,
.clkdm_deny_idle = ti_sysc_clkdm_deny_idle,
.clkdm_allow_idle = ti_sysc_clkdm_allow_idle,
@@ -468,6 +424,12 @@
pcs_pdata.rearm = rearm;
}
+static struct ti_prm_platform_data ti_prm_pdata = {
+ .clkdm_deny_idle = clkdm_deny_idle,
+ .clkdm_allow_idle = clkdm_allow_idle,
+ .clkdm_lookup = clkdm_lookup,
+};
+
/*
* GPIOs for TWL are initialized by the I2C bus and need custom
* handing until DSS has device tree bindings.
@@ -572,6 +534,8 @@
/* Common auxdata */
OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata),
OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),
+ OF_DEV_AUXDATA("ti,omap-prm-inst", 0, NULL, &ti_prm_pdata),
+ OF_DEV_AUXDATA("ti,omap-sdma", 0, NULL, &dma_plat_info),
{ /* sentinel */ },
};
@@ -587,8 +551,6 @@
{ "nokia,omap3-n900", nokia_n900_legacy_init, },
{ "nokia,omap3-n9", hsmmc2_internal_input_clk, },
{ "nokia,omap3-n950", hsmmc2_internal_input_clk, },
- { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, },
- { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, },
{ "logicpd,dm3730-torpedo-devkit", omap3_logicpd_torpedo_init, },
{ "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
{ "ti,am3517-evm", am3517_evm_legacy_init, },
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index fceb1e5..919d35d 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -34,8 +34,6 @@
#include "prm2xxx_3xxx.h"
#include "pm.h"
-u32 enable_off_mode;
-
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 7ac9af5..da829a9 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -28,6 +28,8 @@
#include "clockdomain.h"
#include "pm.h"
+u32 enable_off_mode;
+
#ifdef CONFIG_SUSPEND
/*
* omap_pm_suspend: points to a function that does the SoC-specific
@@ -148,6 +150,7 @@
/* Init the voltage layer */
omap3_twl_init();
omap4_twl_init();
+ omap4_cpcap_init();
omap_voltage_late_init();
/* Smartreflex device init */
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 8a55b69..80e84ae 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -49,11 +49,7 @@
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
-#ifdef CONFIG_PM_DEBUG
extern u32 enable_off_mode;
-#else
-#define enable_off_mode 0
-#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
@@ -107,6 +103,11 @@
#define IS_PM44XX_ERRATUM(id) 0
#endif
+#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
+#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
+#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
+#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
+
#ifdef CONFIG_POWER_AVS_OMAP
extern int omap_devinit_smartreflex(void);
extern void omap_enable_smartreflex_on_init(void);
@@ -134,6 +135,15 @@
}
#endif
+#if IS_ENABLED(CONFIG_MFD_CPCAP)
+extern int omap4_cpcap_init(void);
+#else
+static inline int omap4_cpcap_init(void)
+{
+ return -EINVAL;
+}
+#endif
+
#ifdef CONFIG_PM
extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 1581b6a..6953c47 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -83,8 +83,6 @@
l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
- cpu_cluster_pm_enter();
-
/* One last check for pending IRQs to avoid extra latency due
* to sleeping unnecessarily. */
if (omap_irq_pending())
@@ -96,8 +94,6 @@
OMAP_SDRC_REGADDR(SDRC_POWER));
no_sleep:
- cpu_cluster_pm_exit();
-
clk_enable(osc_ck);
/* clear CORE wake-up events */
@@ -162,25 +158,27 @@
return 0;
if (__clk_is_enabled(osc_ck))
return 0;
- if (omap_dma_running())
- return 0;
return 1;
}
static void omap2_pm_idle(void)
{
- if (!omap2_can_sleep()) {
- if (omap_irq_pending())
- return;
- omap2_enter_mpu_retention();
- return;
- }
+ int error;
if (omap_irq_pending())
return;
+ error = cpu_cluster_pm_enter();
+ if (error || !omap2_can_sleep()) {
+ omap2_enter_mpu_retention();
+ goto out_cpu_cluster_pm;
+ }
+
omap2_enter_full_retention();
+
+out_cpu_cluster_pm:
+ cpu_cluster_pm_exit();
}
static void __init prcm_setup_regs(void)
diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c
index f11442e..bf0d25f 100644
--- a/arch/arm/mach-omap2/pm33xx-core.c
+++ b/arch/arm/mach-omap2/pm33xx-core.c
@@ -2,15 +2,19 @@
/*
* AM33XX Arch Power Management Routines
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach
*/
+#include <linux/cpuidle.h>
+#include <linux/platform_data/pm33xx.h>
+#include <linux/suspend.h>
+#include <asm/cpuidle.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>
#include <linux/errno.h>
-#include <linux/platform_data/pm33xx.h>
#include <linux/clk.h>
+#include <linux/cpu.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/wkup_m3_ipc.h>
@@ -22,17 +26,24 @@
#include "control.h"
#include "clockdomain.h"
#include "iomap.h"
-#include "omap_hwmod.h"
#include "pm.h"
#include "powerdomain.h"
#include "prm33xx.h"
#include "soc.h"
#include "sram.h"
+#include "omap-secure.h"
static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
static struct clockdomain *gfx_l4ls_clkdm;
static void __iomem *scu_base;
-static struct omap_hwmod *rtc_oh;
+
+static int (*idle_fn)(u32 wfi_flags);
+
+struct amx3_idle_state {
+ int wfi_flags;
+};
+
+static struct amx3_idle_state *idle_states;
static int am43xx_map_scu(void)
{
@@ -67,7 +78,7 @@
return 0;
}
-static int amx3_common_init(void)
+static int amx3_common_init(int (*idle)(u32 wfi_flags))
{
gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
per_pwrdm = pwrdm_lookup("per_pwrdm");
@@ -87,10 +98,12 @@
else
omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
+ idle_fn = idle;
+
return 0;
}
-static int am33xx_suspend_init(void)
+static int am33xx_suspend_init(int (*idle)(u32 wfi_flags))
{
int ret;
@@ -101,12 +114,12 @@
return -ENODEV;
}
- ret = amx3_common_init();
+ ret = amx3_common_init(idle);
return ret;
}
-static int am43xx_suspend_init(void)
+static int am43xx_suspend_init(int (*idle)(u32 wfi_flags))
{
int ret = 0;
@@ -116,11 +129,17 @@
return ret;
}
- ret = amx3_common_init();
+ ret = amx3_common_init(idle);
return ret;
}
+static int amx3_suspend_deinit(void)
+{
+ idle_fn = NULL;
+ return 0;
+}
+
static void amx3_pre_suspend_common(void)
{
omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF);
@@ -166,6 +185,16 @@
{
int ret = 0;
+ /* Suspend secure side on HS devices */
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+ if (optee_available)
+ omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0);
+ else
+ omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND,
+ FLAG_START_CRITICAL,
+ 0, 0, 0, 0, 0);
+ }
+
amx3_pre_suspend_common();
scu_power_mode(scu_base, SCU_PM_POWEROFF);
ret = cpu_suspend(args, fn);
@@ -174,9 +203,59 @@
if (!am43xx_check_off_mode_enable())
amx3_post_suspend_common();
+ /*
+ * Resume secure side on HS devices.
+ *
+ * Note that even on systems with OP-TEE available this resume call is
+ * issued to the ROM. This is because upon waking from suspend the ROM
+ * is restored as the secure monitor. On systems with OP-TEE ROM will
+ * restore OP-TEE during this call.
+ */
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+ omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME,
+ FLAG_START_CRITICAL,
+ 0, 0, 0, 0, 0);
+
return ret;
}
+static int am33xx_cpu_suspend(int (*fn)(unsigned long), unsigned long args)
+{
+ int ret = 0;
+
+ if (omap_irq_pending() || need_resched())
+ return ret;
+
+ ret = cpu_suspend(args, fn);
+
+ return ret;
+}
+
+static int am43xx_cpu_suspend(int (*fn)(unsigned long), unsigned long args)
+{
+ int ret = 0;
+
+ if (!scu_base)
+ return 0;
+
+ scu_power_mode(scu_base, SCU_PM_DORMANT);
+ ret = cpu_suspend(args, fn);
+ scu_power_mode(scu_base, SCU_PM_NORMAL);
+
+ return ret;
+}
+
+static void amx3_begin_suspend(void)
+{
+ cpu_idle_poll_ctrl(true);
+}
+
+static void amx3_finish_suspend(void)
+{
+ cpu_idle_poll_ctrl(false);
+}
+
+
static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void)
{
if (soc_is_am33xx())
@@ -187,13 +266,6 @@
return NULL;
}
-void __iomem *am43xx_get_rtc_base_addr(void)
-{
- rtc_oh = omap_hwmod_lookup("rtc");
-
- return omap_hwmod_get_mpu_rt_va(rtc_oh);
-}
-
static void am43xx_save_context(void)
{
}
@@ -217,38 +289,30 @@
writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14));
}
-static void am43xx_prepare_rtc_suspend(void)
-{
- omap_hwmod_enable(rtc_oh);
-}
-
-static void am43xx_prepare_rtc_resume(void)
-{
- omap_hwmod_idle(rtc_oh);
-}
-
static struct am33xx_pm_platform_data am33xx_ops = {
.init = am33xx_suspend_init,
+ .deinit = amx3_suspend_deinit,
.soc_suspend = am33xx_suspend,
+ .cpu_suspend = am33xx_cpu_suspend,
+ .begin_suspend = amx3_begin_suspend,
+ .finish_suspend = amx3_finish_suspend,
.get_sram_addrs = amx3_get_sram_addrs,
.save_context = am33xx_save_context,
.restore_context = am33xx_restore_context,
- .prepare_rtc_suspend = am43xx_prepare_rtc_suspend,
- .prepare_rtc_resume = am43xx_prepare_rtc_resume,
.check_off_mode_enable = am33xx_check_off_mode_enable,
- .get_rtc_base_addr = am43xx_get_rtc_base_addr,
};
static struct am33xx_pm_platform_data am43xx_ops = {
.init = am43xx_suspend_init,
+ .deinit = amx3_suspend_deinit,
.soc_suspend = am43xx_suspend,
+ .cpu_suspend = am43xx_cpu_suspend,
+ .begin_suspend = amx3_begin_suspend,
+ .finish_suspend = amx3_finish_suspend,
.get_sram_addrs = amx3_get_sram_addrs,
.save_context = am43xx_save_context,
.restore_context = am43xx_restore_context,
- .prepare_rtc_suspend = am43xx_prepare_rtc_suspend,
- .prepare_rtc_resume = am43xx_prepare_rtc_resume,
.check_off_mode_enable = am43xx_check_off_mode_enable,
- .get_rtc_base_addr = am43xx_get_rtc_base_addr,
};
static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void)
@@ -261,6 +325,44 @@
return NULL;
}
+#ifdef CONFIG_SUSPEND
+/*
+ * Block system suspend initially. Later on pm33xx sets up it's own
+ * platform_suspend_ops after probe. That depends also on loaded
+ * wkup_m3_ipc and booted am335x-pm-firmware.elf.
+ */
+static int amx3_suspend_block(suspend_state_t state)
+{
+ pr_warn("PM not initialized for pm33xx, wkup_m3_ipc, or am335x-pm-firmware.elf\n");
+
+ return -EINVAL;
+}
+
+static int amx3_pm_valid(suspend_state_t state)
+{
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+static const struct platform_suspend_ops amx3_blocked_pm_ops = {
+ .begin = amx3_suspend_block,
+ .valid = amx3_pm_valid,
+};
+
+static void __init amx3_block_suspend(void)
+{
+ suspend_set_ops(&amx3_blocked_pm_ops);
+}
+#else
+static inline void amx3_block_suspend(void)
+{
+}
+#endif /* CONFIG_SUSPEND */
+
int __init amx3_common_pm_init(void)
{
struct am33xx_pm_platform_data *pdata;
@@ -274,6 +376,68 @@
devinfo.size_data = sizeof(*pdata);
devinfo.id = -1;
platform_device_register_full(&devinfo);
+ amx3_block_suspend();
return 0;
}
+
+static int __init amx3_idle_init(struct device_node *cpu_node, int cpu)
+{
+ struct device_node *state_node;
+ struct amx3_idle_state states[CPUIDLE_STATE_MAX];
+ int i;
+ int state_count = 1;
+
+ for (i = 0; ; i++) {
+ state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+ if (!state_node)
+ break;
+
+ if (!of_device_is_available(state_node))
+ continue;
+
+ if (i == CPUIDLE_STATE_MAX) {
+ pr_warn("%s: cpuidle states reached max possible\n",
+ __func__);
+ break;
+ }
+
+ states[state_count].wfi_flags = 0;
+
+ if (of_property_read_bool(state_node, "ti,idle-wkup-m3"))
+ states[state_count].wfi_flags |= WFI_FLAG_WAKE_M3 |
+ WFI_FLAG_FLUSH_CACHE;
+
+ state_count++;
+ }
+
+ idle_states = kcalloc(state_count, sizeof(*idle_states), GFP_KERNEL);
+ if (!idle_states)
+ return -ENOMEM;
+
+ for (i = 1; i < state_count; i++)
+ idle_states[i].wfi_flags = states[i].wfi_flags;
+
+ return 0;
+}
+
+static int amx3_idle_enter(unsigned long index)
+{
+ struct amx3_idle_state *idle_state = &idle_states[index];
+
+ if (!idle_state)
+ return -EINVAL;
+
+ if (idle_fn)
+ idle_fn(idle_state->wfi_flags);
+
+ return 0;
+}
+
+static struct cpuidle_ops amx3_cpuidle_ops __initdata = {
+ .init = amx3_idle_init,
+ .suspend = amx3_idle_enter,
+};
+
+CPUIDLE_METHOD_OF_DECLARE(pm33xx_idle, "ti,am3352", &amx3_cpuidle_ops);
+CPUIDLE_METHOD_OF_DECLARE(pm43xx_idle, "ti,am4372", &amx3_cpuidle_ops);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fa66534..71c1d18 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -25,7 +25,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/slab.h>
-#include <linux/omap-dma.h>
+#include <linux/of.h>
#include <linux/omap-gpmc.h>
#include <trace/events/power.h>
@@ -85,7 +85,6 @@
omap3_gpmc_save_context();
/* Save the system control module context, padconf already save above*/
omap3_control_save_context();
- omap_dma_global_context_save();
}
static void omap3_core_restore_context(void)
@@ -96,7 +95,6 @@
omap3_gpmc_restore_context();
/* Restore the interrupt controller context */
omap_intc_restore_context();
- omap_dma_global_context_restore();
}
/*
@@ -301,11 +299,7 @@
if (omap_irq_pending())
return;
- trace_cpu_idle_rcuidle(1, smp_processor_id());
-
omap_sram_idle();
-
- trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
}
#ifdef CONFIG_SUSPEND
@@ -417,7 +411,12 @@
if (!pwrst)
return -ENOMEM;
pwrst->pwrdm = pwrdm;
- pwrst->next_state = PWRDM_POWER_RET;
+
+ if (enable_off_mode)
+ pwrst->next_state = PWRDM_POWER_OFF;
+ else
+ pwrst->next_state = PWRDM_POWER_RET;
+
list_add(&pwrst->node, &pwrst_list);
if (pwrdm_has_hdwr_sar(pwrdm))
@@ -451,6 +450,22 @@
}
}
+static void __init omap3_pm_check_pmic(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle");
+ if (!np)
+ np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off");
+
+ if (np) {
+ of_node_put(np);
+ enable_off_mode = 1;
+ } else {
+ enable_off_mode = 0;
+ }
+}
+
int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
@@ -484,6 +499,8 @@
goto err2;
}
+ omap3_pm_check_pmic();
+
ret = pwrdm_for_each(pwrdms_setup, NULL);
if (ret) {
pr_err("Failed to setup powerdomains\n");
@@ -551,9 +568,7 @@
local_irq_disable();
- omap_dma_global_context_save();
omap3_save_secure_ram_context();
- omap_dma_global_context_restore();
local_irq_enable();
}
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 485550a..5a7a949 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -128,18 +128,9 @@
return 0;
}
- /*
- * Bootloader or kexec boot may have LOGICRETSTATE cleared
- * for some domains. This is the case when kexec booting from
- * Android kernels that support off mode for example.
- * Make sure it's set at least for core and per, otherwise
- * we currently will see lost GPIO interrupts for wlcore and
- * smsc911x at least if per hits retention during idle.
- */
if (!strncmp(pwrdm->name, "core", 4) ||
- !strncmp(pwrdm->name, "l4per", 5) ||
- !strncmp(pwrdm->name, "wkup", 4))
- pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_RET);
+ !strncmp(pwrdm->name, "l4per", 5))
+ pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_OFF);
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
if (!pwrst)
diff --git a/arch/arm/mach-omap2/pmic-cpcap.c b/arch/arm/mach-omap2/pmic-cpcap.c
new file mode 100644
index 0000000..668dc84
--- /dev/null
+++ b/arch/arm/mach-omap2/pmic-cpcap.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * pmic-cpcap.c - CPCAP-specific functions for the OPP code
+ *
+ * Adapted from Motorola Mapphone Android Linux kernel
+ * Copyright (C) 2011 Motorola, Inc.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "soc.h"
+#include "pm.h"
+#include "voltage.h"
+
+#include <linux/init.h>
+#include "vc.h"
+
+/**
+ * omap_cpcap_vsel_to_vdc - convert CPCAP VSEL value to microvolts DC
+ * @vsel: CPCAP VSEL value to convert
+ *
+ * Returns the microvolts DC that the CPCAP PMIC should generate when
+ * programmed with @vsel.
+ */
+static unsigned long omap_cpcap_vsel_to_uv(unsigned char vsel)
+{
+ if (vsel > 0x44)
+ vsel = 0x44;
+ return (((vsel * 125) + 6000)) * 100;
+}
+
+/**
+ * omap_cpcap_uv_to_vsel - convert microvolts DC to CPCAP VSEL value
+ * @uv: microvolts DC to convert
+ *
+ * Returns the VSEL value necessary for the CPCAP PMIC to
+ * generate an output voltage equal to or greater than @uv microvolts DC.
+ */
+static unsigned char omap_cpcap_uv_to_vsel(unsigned long uv)
+{
+ if (uv < 600000)
+ uv = 600000;
+ else if (uv > 1450000)
+ uv = 1450000;
+ return DIV_ROUND_UP(uv - 600000, 12500);
+}
+
+static struct omap_voltdm_pmic omap_cpcap_core = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ .vddmin = 900000,
+ .vddmax = 1350000,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = 0x02,
+ .volt_reg_addr = 0x00,
+ .cmd_reg_addr = 0x01,
+ .i2c_high_speed = false,
+ .vsel_to_uv = omap_cpcap_vsel_to_uv,
+ .uv_to_vsel = omap_cpcap_uv_to_vsel,
+};
+
+static struct omap_voltdm_pmic omap_cpcap_iva = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ .vddmin = 900000,
+ .vddmax = 1375000,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = 0x44,
+ .volt_reg_addr = 0x0,
+ .cmd_reg_addr = 0x01,
+ .i2c_high_speed = false,
+ .vsel_to_uv = omap_cpcap_vsel_to_uv,
+ .uv_to_vsel = omap_cpcap_uv_to_vsel,
+};
+
+/**
+ * omap_max8952_vsel_to_vdc - convert MAX8952 VSEL value to microvolts DC
+ * @vsel: MAX8952 VSEL value to convert
+ *
+ * Returns the microvolts DC that the MAX8952 Regulator should generate when
+ * programmed with @vsel.
+ */
+static unsigned long omap_max8952_vsel_to_uv(unsigned char vsel)
+{
+ if (vsel > 0x3F)
+ vsel = 0x3F;
+ return (((vsel * 100) + 7700)) * 100;
+}
+
+/**
+ * omap_max8952_uv_to_vsel - convert microvolts DC to MAX8952 VSEL value
+ * @uv: microvolts DC to convert
+ *
+ * Returns the VSEL value necessary for the MAX8952 Regulator to
+ * generate an output voltage equal to or greater than @uv microvolts DC.
+ */
+static unsigned char omap_max8952_uv_to_vsel(unsigned long uv)
+{
+ if (uv < 770000)
+ uv = 770000;
+ else if (uv > 1400000)
+ uv = 1400000;
+ return DIV_ROUND_UP(uv - 770000, 10000);
+}
+
+static struct omap_voltdm_pmic omap443x_max8952_mpu = {
+ .slew_rate = 16000,
+ .step_size = 10000,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ .vddmin = 900000,
+ .vddmax = 1400000,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = 0x60,
+ .volt_reg_addr = 0x03,
+ .cmd_reg_addr = 0x03,
+ .i2c_high_speed = false,
+ .vsel_to_uv = omap_max8952_vsel_to_uv,
+ .uv_to_vsel = omap_max8952_uv_to_vsel,
+};
+
+/**
+ * omap_fan5355_vsel_to_vdc - convert FAN535503 VSEL value to microvolts DC
+ * @vsel: FAN535503 VSEL value to convert
+ *
+ * Returns the microvolts DC that the FAN535503 Regulator should generate when
+ * programmed with @vsel.
+ */
+static unsigned long omap_fan535503_vsel_to_uv(unsigned char vsel)
+{
+ /* Extract bits[5:0] */
+ vsel &= 0x3F;
+
+ return (((vsel * 125) + 7500)) * 100;
+}
+
+/**
+ * omap_fan535508_vsel_to_vdc - convert FAN535508 VSEL value to microvolts DC
+ * @vsel: FAN535508 VSEL value to convert
+ *
+ * Returns the microvolts DC that the FAN535508 Regulator should generate when
+ * programmed with @vsel.
+ */
+static unsigned long omap_fan535508_vsel_to_uv(unsigned char vsel)
+{
+ /* Extract bits[5:0] */
+ vsel &= 0x3F;
+
+ if (vsel > 0x37)
+ vsel = 0x37;
+ return (((vsel * 125) + 7500)) * 100;
+}
+
+
+/**
+ * omap_fan535503_uv_to_vsel - convert microvolts DC to FAN535503 VSEL value
+ * @uv: microvolts DC to convert
+ *
+ * Returns the VSEL value necessary for the MAX8952 Regulator to
+ * generate an output voltage equal to or greater than @uv microvolts DC.
+ */
+static unsigned char omap_fan535503_uv_to_vsel(unsigned long uv)
+{
+ unsigned char vsel;
+ if (uv < 750000)
+ uv = 750000;
+ else if (uv > 1537500)
+ uv = 1537500;
+
+ vsel = DIV_ROUND_UP(uv - 750000, 12500);
+ return vsel | 0xC0;
+}
+
+/**
+ * omap_fan535508_uv_to_vsel - convert microvolts DC to FAN535508 VSEL value
+ * @uv: microvolts DC to convert
+ *
+ * Returns the VSEL value necessary for the MAX8952 Regulator to
+ * generate an output voltage equal to or greater than @uv microvolts DC.
+ */
+static unsigned char omap_fan535508_uv_to_vsel(unsigned long uv)
+{
+ unsigned char vsel;
+ if (uv < 750000)
+ uv = 750000;
+ else if (uv > 1437500)
+ uv = 1437500;
+
+ vsel = DIV_ROUND_UP(uv - 750000, 12500);
+ return vsel | 0xC0;
+}
+
+/* fan5335-core */
+static struct omap_voltdm_pmic omap4_fan_core = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ .vddmin = 850000,
+ .vddmax = 1375000,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = 0x4A,
+ .i2c_high_speed = false,
+ .volt_reg_addr = 0x01,
+ .cmd_reg_addr = 0x01,
+ .vsel_to_uv = omap_fan535508_vsel_to_uv,
+ .uv_to_vsel = omap_fan535508_uv_to_vsel,
+};
+
+/* fan5335 iva */
+static struct omap_voltdm_pmic omap4_fan_iva = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ .vddmin = 850000,
+ .vddmax = 1375000,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = 0x48,
+ .volt_reg_addr = 0x01,
+ .cmd_reg_addr = 0x01,
+ .i2c_high_speed = false,
+ .vsel_to_uv = omap_fan535503_vsel_to_uv,
+ .uv_to_vsel = omap_fan535503_uv_to_vsel,
+};
+
+int __init omap4_cpcap_init(void)
+{
+ struct voltagedomain *voltdm;
+
+ if (!of_find_compatible_node(NULL, NULL, "motorola,cpcap"))
+ return -ENODEV;
+
+ voltdm = voltdm_lookup("mpu");
+ omap_voltage_register_pmic(voltdm, &omap443x_max8952_mpu);
+
+ if (of_machine_is_compatible("motorola,droid-bionic")) {
+ voltdm = voltdm_lookup("core");
+ omap_voltage_register_pmic(voltdm, &omap_cpcap_core);
+
+ voltdm = voltdm_lookup("iva");
+ omap_voltage_register_pmic(voltdm, &omap_cpcap_iva);
+ } else {
+ voltdm = voltdm_lookup("core");
+ omap_voltage_register_pmic(voltdm, &omap4_fan_core);
+
+ voltdm = voltdm_lookup("iva");
+ omap_voltage_register_pmic(voltdm, &omap4_fan_iva);
+ }
+
+ return 0;
+}
+
+static int __init cpcap_late_init(void)
+{
+ omap4_vc_set_pmic_signaling(PWRDM_POWER_RET);
+
+ return 0;
+}
+omap_late_initcall(cpcap_late_init);
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
index 869adb8..626055e 100644
--- a/arch/arm/mach-omap2/powerdomains33xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -1,7 +1,7 @@
/*
* AM33XX Power domain data
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index e2ad14e..899da0a 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -1,7 +1,7 @@
/*
* AM43x PRCM defines
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -68,6 +68,7 @@
#define AM43XX_CM_PER_ICSS_CDOFFS 0x0300
#define AM43XX_CM_PER_L4LS_CDOFFS 0x0400
#define AM43XX_CM_PER_EMIF_CDOFFS 0x0700
+#define AM43XX_CM_PER_LCDC_CDOFFS 0x0800
#define AM43XX_CM_PER_DSS_CDOFFS 0x0a00
#define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00
#define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00
diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h
index 6ef3882..bdbfa07 100644
--- a/arch/arm/mach-omap2/prcm_mpu54xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54xx PRCM MPU instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
diff --git a/arch/arm/mach-omap2/prcm_mpu7xx.h b/arch/arm/mach-omap2/prcm_mpu7xx.h
index 33d0013..2e30324 100644
--- a/arch/arm/mach-omap2/prcm_mpu7xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu7xx.h
@@ -2,7 +2,7 @@
/*
* DRA7xx PRCM MPU instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
index 84feece..7dfdff0 100644
--- a/arch/arm/mach-omap2/prm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -1,7 +1,7 @@
/*
* AM33XX PRM_XXX register bits
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index d514166..9144cc0 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -1,7 +1,7 @@
/*
* AM33XX PRM functions
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 66302c6..d0b7404 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -1,7 +1,7 @@
/*
* AM33XX PRM instance offset macros
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 1d9346f..25093c1 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -745,7 +745,7 @@
static int omap44xx_prm_late_init(void);
-void prm_save_context(void)
+static void prm_save_context(void)
{
omap_prm_context.irq_enable =
omap4_prm_read_inst_reg(AM43XX_PRM_OCP_SOCKET_INST,
@@ -756,7 +756,7 @@
omap4_prcm_irq_setup.pm_ctrl);
}
-void prm_restore_context(void)
+static void prm_restore_context(void)
{
omap4_prm_write_inst_reg(omap_prm_context.irq_enable,
OMAP4430_PRM_OCP_SOCKET_INST,
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index ee0f1cc..7329d6f 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54xx PRM instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index cf99307..e5aee04 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -2,7 +2,7 @@
/*
* DRA7xx PRM instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h
index 810d2b1..cb6f3e6 100644
--- a/arch/arm/mach-omap2/scrm54xx.h
+++ b/arch/arm/mach-omap2/scrm54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54XX SCRM registers and bitfields
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Benoit Cousson (b-cousson@ti.com)
*
diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
index dc22124..ac3d0b3 100644
--- a/arch/arm/mach-omap2/sleep33xx.S
+++ b/arch/arm/mach-omap2/sleep33xx.S
@@ -2,7 +2,7 @@
/*
* Low level suspend code for AM33XX SoCs
*
- * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012-2018 Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach, Vaibhav Bedia
*/
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index ac1324c..c4e97d3 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -72,7 +72,7 @@
stmfd sp!, {lr} @ save registers on stack
/* Setup so that we will disable and enable l2 */
mov r1, #0x1
- adrl r3, l2dis_3630_offset @ may be too distant for plain adr
+ adr r3, l2dis_3630_offset
ldr r2, [r3] @ value for offset
str r1, [r2, r3] @ write to l2dis_3630
ldmfd sp!, {pc} @ restore regs and return
diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S
index 90d2907..832c913 100644
--- a/arch/arm/mach-omap2/sleep43xx.S
+++ b/arch/arm/mach-omap2/sleep43xx.S
@@ -2,7 +2,7 @@
/*
* Low level suspend code for AM43XX SoCs
*
- * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2018 Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach, Vaibhav Bedia
*/
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 62df666..6059256 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -88,34 +88,26 @@
extern struct omap_sr_data omap_sr_pdata[];
-static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
+static int __init sr_init_by_name(const char *name, const char *voltdm)
{
struct omap_sr_data *sr_data = NULL;
struct omap_volt_data *volt_data;
- struct omap_smartreflex_dev_attr *sr_dev_attr;
static int i;
- if (!strncmp(oh->name, "smartreflex_mpu_iva", 20) ||
- !strncmp(oh->name, "smartreflex_mpu", 16))
+ if (!strncmp(name, "smartreflex_mpu_iva", 20) ||
+ !strncmp(name, "smartreflex_mpu", 16))
sr_data = &omap_sr_pdata[OMAP_SR_MPU];
- else if (!strncmp(oh->name, "smartreflex_core", 17))
+ else if (!strncmp(name, "smartreflex_core", 17))
sr_data = &omap_sr_pdata[OMAP_SR_CORE];
- else if (!strncmp(oh->name, "smartreflex_iva", 16))
+ else if (!strncmp(name, "smartreflex_iva", 16))
sr_data = &omap_sr_pdata[OMAP_SR_IVA];
if (!sr_data) {
- pr_err("%s: Unknown instance %s\n", __func__, oh->name);
+ pr_err("%s: Unknown instance %s\n", __func__, name);
return -EINVAL;
}
- sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
- if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
- pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
- __func__, oh->name);
- goto exit;
- }
-
- sr_data->name = oh->name;
+ sr_data->name = name;
if (cpu_is_omap343x())
sr_data->ip_type = 1;
else
@@ -136,10 +128,10 @@
}
}
- sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
+ sr_data->voltdm = voltdm_lookup(voltdm);
if (!sr_data->voltdm) {
pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
- __func__, sr_dev_attr->sensor_voltdm_name);
+ __func__, voltdm);
goto exit;
}
@@ -160,6 +152,20 @@
return 0;
}
+static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
+{
+ struct omap_smartreflex_dev_attr *sr_dev_attr;
+
+ sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
+ if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
+ pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
+ __func__, oh->name);
+ return 0;
+ }
+
+ return sr_init_by_name(oh->name, sr_dev_attr->sensor_voltdm_name);
+}
+
/*
* API to be called from board files to enable smartreflex
* autocompensation at init.
@@ -169,7 +175,42 @@
sr_enable_on_init = true;
}
+static const char * const omap4_sr_instances[] = {
+ "mpu",
+ "iva",
+ "core",
+};
+
+static const char * const dra7_sr_instances[] = {
+ "mpu",
+ "core",
+};
+
int __init omap_devinit_smartreflex(void)
{
+ const char * const *sr_inst = NULL;
+ int i, nr_sr = 0;
+
+ if (soc_is_omap44xx()) {
+ sr_inst = omap4_sr_instances;
+ nr_sr = ARRAY_SIZE(omap4_sr_instances);
+
+ } else if (soc_is_dra7xx()) {
+ sr_inst = dra7_sr_instances;
+ nr_sr = ARRAY_SIZE(dra7_sr_instances);
+ }
+
+ if (nr_sr) {
+ const char *name, *voltdm;
+
+ for (i = 0; i < nr_sr; i++) {
+ name = kasprintf(GFP_KERNEL, "smartreflex_%s", sr_inst[i]);
+ voltdm = sr_inst[i];
+ sr_init_by_name(name, voltdm);
+ }
+
+ return 0;
+ }
+
return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL);
}
diff --git a/arch/arm/mach-omap2/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h
index a1e6caf..192b0e7 100644
--- a/arch/arm/mach-omap2/ti81xx.h
+++ b/arch/arm/mach-omap2/ti81xx.h
@@ -1,7 +1,7 @@
/*
* This file contains the address data for various TI81XX modules.
*
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 1defb83..620ba69 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -26,35 +26,12 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/slab.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/dmtimer-omap.h>
-#include <linux/sched_clock.h>
-#include <linux/cpu.h>
-
-#include <asm/mach/time.h>
-
-#include "omap_hwmod.h"
-#include "omap_device.h"
-#include <plat/counter-32k.h>
-#include <clocksource/timer-ti-dm.h>
#include "soc.h"
#include "common.h"
#include "control.h"
-#include "powerdomain.h"
#include "omap-secure.h"
#define REALTIME_COUNTER_BASE 0x48243200
@@ -62,612 +39,12 @@
#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
-/* Clockevent code */
-
-/* Clockevent hwmod for am335x and am437x suspend */
-static struct omap_hwmod *clockevent_gpt_hwmod;
-
-/* Clockesource hwmod for am437x suspend */
-static struct omap_hwmod *clocksource_gpt_hwmod;
-
-struct dmtimer_clockevent {
- struct clock_event_device dev;
- struct omap_dm_timer timer;
-};
-
-static struct dmtimer_clockevent clockevent;
-
-static struct omap_dm_timer *to_dmtimer(struct clock_event_device *clockevent)
-{
- struct dmtimer_clockevent *clkevt =
- container_of(clockevent, struct dmtimer_clockevent, dev);
- struct omap_dm_timer *timer = &clkevt->timer;
-
- return timer;
-}
-
-#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
static unsigned long arch_timer_freq;
void set_cntfreq(void)
{
omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
}
-#endif
-
-static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
-{
- struct dmtimer_clockevent *clkevt = dev_id;
- struct clock_event_device *evt = &clkevt->dev;
- struct omap_dm_timer *timer = &clkevt->timer;
-
- __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW);
- evt->event_handler(evt);
- return IRQ_HANDLED;
-}
-
-static int omap2_gp_timer_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- struct omap_dm_timer *timer = to_dmtimer(evt);
-
- __omap_dm_timer_load_start(timer, OMAP_TIMER_CTRL_ST,
- 0xffffffff - cycles, OMAP_TIMER_POSTED);
-
- return 0;
-}
-
-static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
-{
- struct omap_dm_timer *timer = to_dmtimer(evt);
-
- __omap_dm_timer_stop(timer, OMAP_TIMER_POSTED, timer->rate);
-
- return 0;
-}
-
-static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
-{
- struct omap_dm_timer *timer = to_dmtimer(evt);
- u32 period;
-
- __omap_dm_timer_stop(timer, OMAP_TIMER_POSTED, timer->rate);
-
- period = timer->rate / HZ;
- period -= 1;
- /* Looks like we need to first set the load value separately */
- __omap_dm_timer_write(timer, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
- OMAP_TIMER_POSTED);
- __omap_dm_timer_load_start(timer,
- OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
- 0xffffffff - period, OMAP_TIMER_POSTED);
- return 0;
-}
-
-static void omap_clkevt_idle(struct clock_event_device *unused)
-{
- if (!clockevent_gpt_hwmod)
- return;
-
- omap_hwmod_idle(clockevent_gpt_hwmod);
-}
-
-static void omap_clkevt_unidle(struct clock_event_device *evt)
-{
- struct omap_dm_timer *timer = to_dmtimer(evt);
-
- if (!clockevent_gpt_hwmod)
- return;
-
- omap_hwmod_enable(clockevent_gpt_hwmod);
- __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
-}
-
-static const struct of_device_id omap_timer_match[] __initconst = {
- { .compatible = "ti,omap2420-timer", },
- { .compatible = "ti,omap3430-timer", },
- { .compatible = "ti,omap4430-timer", },
- { .compatible = "ti,omap5430-timer", },
- { .compatible = "ti,dm814-timer", },
- { .compatible = "ti,dm816-timer", },
- { .compatible = "ti,am335x-timer", },
- { .compatible = "ti,am335x-timer-1ms", },
- { }
-};
-
-static int omap_timer_add_disabled_property(struct device_node *np)
-{
- struct property *prop;
-
- prop = kzalloc(sizeof(*prop), GFP_KERNEL);
- if (!prop)
- return -ENOMEM;
-
- prop->name = "status";
- prop->value = "disabled";
- prop->length = strlen(prop->value);
-
- return of_add_property(np, prop);
-}
-
-static int omap_timer_update_dt(struct device_node *np)
-{
- int error = 0;
-
- if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
- error = omap_timer_add_disabled_property(np);
- if (error)
- return error;
- }
-
- /* No parent interconnect target module configured? */
- if (of_get_property(np, "ti,hwmods", NULL))
- return error;
-
- /* Tag parent interconnect target module disabled */
- error = omap_timer_add_disabled_property(np->parent);
- if (error)
- return error;
-
- return 0;
-}
-
-/**
- * omap_get_timer_dt - get a timer using device-tree
- * @match - device-tree match structure for matching a device type
- * @property - optional timer property to match
- *
- * Helper function to get a timer during early boot using device-tree for use
- * as kernel system timer. Optionally, the property argument can be used to
- * select a timer with a specific property. Once a timer is found then mark
- * the timer node in device-tree as disabled, to prevent the kernel from
- * registering this timer as a platform device and so no one else can use it.
- */
-static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
- const char *property)
-{
- struct device_node *np;
- int error;
-
- for_each_matching_node(np, match) {
- if (!of_device_is_available(np))
- continue;
-
- if (property && !of_get_property(np, property, NULL))
- continue;
-
- if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
- of_get_property(np, "ti,timer-dsp", NULL) ||
- of_get_property(np, "ti,timer-pwm", NULL) ||
- of_get_property(np, "ti,timer-secure", NULL)))
- continue;
-
- error = omap_timer_update_dt(np);
- WARN(error, "%s: Could not update dt: %i\n", __func__, error);
-
- return np;
- }
-
- return NULL;
-}
-
-/**
- * omap_dmtimer_init - initialisation function when device tree is used
- *
- * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
- * cannot be used by the kernel as they are reserved. Therefore, to prevent the
- * kernel registering these devices remove them dynamically from the device
- * tree on boot.
- */
-static void __init omap_dmtimer_init(void)
-{
- struct device_node *np;
-
- if (!cpu_is_omap34xx() && !soc_is_dra7xx())
- return;
-
- /* If we are a secure device, remove any secure timer nodes */
- if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
- np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
- of_node_put(np);
- }
-}
-
-/**
- * omap_dm_timer_get_errata - get errata flags for a timer
- *
- * Get the timer errata flags that are specific to the OMAP device being used.
- */
-static u32 __init omap_dm_timer_get_errata(void)
-{
- if (cpu_is_omap24xx())
- return 0;
-
- return OMAP_TIMER_ERRATA_I103_I767;
-}
-
-static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
- const char *fck_source,
- const char *property,
- const char **timer_name,
- int posted)
-{
- const char *oh_name = NULL;
- struct device_node *np;
- struct omap_hwmod *oh;
- struct clk *src;
- int r = 0;
-
- np = omap_get_timer_dt(omap_timer_match, property);
- if (!np)
- return -ENODEV;
-
- of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
- if (!oh_name) {
- of_property_read_string_index(np->parent, "ti,hwmods", 0,
- &oh_name);
- if (!oh_name)
- return -ENODEV;
- }
-
- timer->irq = irq_of_parse_and_map(np, 0);
- if (!timer->irq)
- return -ENXIO;
-
- timer->io_base = of_iomap(np, 0);
-
- timer->fclk = of_clk_get_by_name(np, "fck");
-
- of_node_put(np);
-
- oh = omap_hwmod_lookup(oh_name);
- if (!oh)
- return -ENODEV;
-
- *timer_name = oh->name;
-
- if (!timer->io_base)
- return -ENXIO;
-
- omap_hwmod_setup_one(oh_name);
-
- /* After the dmtimer is using hwmod these clocks won't be needed */
- if (IS_ERR_OR_NULL(timer->fclk))
- timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
- if (IS_ERR(timer->fclk))
- return PTR_ERR(timer->fclk);
-
- src = clk_get(NULL, fck_source);
- if (IS_ERR(src))
- return PTR_ERR(src);
-
- WARN(clk_set_parent(timer->fclk, src) < 0,
- "Cannot set timer parent clock, no PLL clock driver?");
-
- clk_put(src);
-
- omap_hwmod_enable(oh);
- __omap_dm_timer_init_regs(timer);
-
- if (posted)
- __omap_dm_timer_enable_posted(timer);
-
- /* Check that the intended posted configuration matches the actual */
- if (posted != timer->posted)
- return -EINVAL;
-
- timer->rate = clk_get_rate(timer->fclk);
- timer->reserved = 1;
-
- return r;
-}
-
-#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
-void tick_broadcast(const struct cpumask *mask)
-{
-}
-#endif
-
-static void __init dmtimer_clkevt_init_common(struct dmtimer_clockevent *clkevt,
- int gptimer_id,
- const char *fck_source,
- unsigned int features,
- const struct cpumask *cpumask,
- const char *property,
- int rating, const char *name)
-{
- struct omap_dm_timer *timer = &clkevt->timer;
- int res;
-
- timer->id = gptimer_id;
- timer->errata = omap_dm_timer_get_errata();
- clkevt->dev.features = features;
- clkevt->dev.rating = rating;
- clkevt->dev.set_next_event = omap2_gp_timer_set_next_event;
- clkevt->dev.set_state_shutdown = omap2_gp_timer_shutdown;
- clkevt->dev.set_state_periodic = omap2_gp_timer_set_periodic;
- clkevt->dev.set_state_oneshot = omap2_gp_timer_shutdown;
- clkevt->dev.tick_resume = omap2_gp_timer_shutdown;
-
- /*
- * For clock-event timers we never read the timer counter and
- * so we are not impacted by errata i103 and i767. Therefore,
- * we can safely ignore this errata for clock-event timers.
- */
- __omap_dm_timer_override_errata(timer, OMAP_TIMER_ERRATA_I103_I767);
-
- res = omap_dm_timer_init_one(timer, fck_source, property,
- &clkevt->dev.name, OMAP_TIMER_POSTED);
- BUG_ON(res);
-
- clkevt->dev.cpumask = cpumask;
- clkevt->dev.irq = omap_dm_timer_get_irq(timer);
-
- if (request_irq(clkevt->dev.irq, omap2_gp_timer_interrupt,
- IRQF_TIMER | IRQF_IRQPOLL, name, clkevt))
- pr_err("Failed to request irq %d (gp_timer)\n", clkevt->dev.irq);
-
- __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
-
- if (soc_is_am33xx() || soc_is_am43xx()) {
- clkevt->dev.suspend = omap_clkevt_idle;
- clkevt->dev.resume = omap_clkevt_unidle;
-
- clockevent_gpt_hwmod =
- omap_hwmod_lookup(clkevt->dev.name);
- }
-
- pr_info("OMAP clockevent source: %s at %lu Hz\n", clkevt->dev.name,
- timer->rate);
-}
-
-static DEFINE_PER_CPU(struct dmtimer_clockevent, dmtimer_percpu_timer);
-
-static int omap_gptimer_starting_cpu(unsigned int cpu)
-{
- struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
- struct clock_event_device *dev = &clkevt->dev;
- struct omap_dm_timer *timer = &clkevt->timer;
-
- clockevents_config_and_register(dev, timer->rate, 3, ULONG_MAX);
- irq_force_affinity(dev->irq, cpumask_of(cpu));
-
- return 0;
-}
-
-static int __init dmtimer_percpu_quirk_init(void)
-{
- struct dmtimer_clockevent *clkevt;
- struct clock_event_device *dev;
- struct device_node *arm_timer;
- struct omap_dm_timer *timer;
- int cpu = 0;
-
- arm_timer = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
- if (of_device_is_available(arm_timer)) {
- pr_warn_once("ARM architected timer wrap issue i940 detected\n");
- return 0;
- }
-
- for_each_possible_cpu(cpu) {
- clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
- dev = &clkevt->dev;
- timer = &clkevt->timer;
-
- dmtimer_clkevt_init_common(clkevt, 0, "timer_sys_ck",
- CLOCK_EVT_FEAT_ONESHOT,
- cpumask_of(cpu),
- "assigned-clock-parents",
- 500, "percpu timer");
- }
-
- cpuhp_setup_state(CPUHP_AP_OMAP_DM_TIMER_STARTING,
- "clockevents/omap/gptimer:starting",
- omap_gptimer_starting_cpu, NULL);
-
- return 0;
-}
-
-/* Clocksource code */
-static struct omap_dm_timer clksrc;
-static bool use_gptimer_clksrc __initdata;
-
-/*
- * clocksource
- */
-static u64 clocksource_read_cycles(struct clocksource *cs)
-{
- return (u64)__omap_dm_timer_read_counter(&clksrc,
- OMAP_TIMER_NONPOSTED);
-}
-
-static struct clocksource clocksource_gpt = {
- .rating = 300,
- .read = clocksource_read_cycles,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static u64 notrace dmtimer_read_sched_clock(void)
-{
- if (clksrc.reserved)
- return __omap_dm_timer_read_counter(&clksrc,
- OMAP_TIMER_NONPOSTED);
-
- return 0;
-}
-
-static const struct of_device_id omap_counter_match[] __initconst = {
- { .compatible = "ti,omap-counter32k", },
- { }
-};
-
-/* Setup free-running counter for clocksource */
-static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
-{
- int ret;
- struct device_node *np = NULL;
- struct omap_hwmod *oh;
- const char *oh_name = "counter_32k";
-
- /*
- * See if the 32kHz counter is supported.
- */
- np = omap_get_timer_dt(omap_counter_match, NULL);
- if (!np)
- return -ENODEV;
-
- of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name);
- if (!oh_name) {
- of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
- if (!oh_name)
- return -ENODEV;
- }
-
- /*
- * First check hwmod data is available for sync32k counter
- */
- oh = omap_hwmod_lookup(oh_name);
- if (!oh || oh->slaves_cnt == 0)
- return -ENODEV;
-
- omap_hwmod_setup_one(oh_name);
-
- ret = omap_hwmod_enable(oh);
- if (ret) {
- pr_warn("%s: failed to enable counter_32k module (%d)\n",
- __func__, ret);
- return ret;
- }
-
- return ret;
-}
-
-static unsigned int omap2_gptimer_clksrc_load;
-
-static void omap2_gptimer_clksrc_suspend(struct clocksource *unused)
-{
- omap2_gptimer_clksrc_load =
- __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
-
- omap_hwmod_idle(clocksource_gpt_hwmod);
-}
-
-static void omap2_gptimer_clksrc_resume(struct clocksource *unused)
-{
- omap_hwmod_enable(clocksource_gpt_hwmod);
-
- __omap_dm_timer_load_start(&clksrc,
- OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
- omap2_gptimer_clksrc_load,
- OMAP_TIMER_NONPOSTED);
-}
-
-static void __init omap2_gptimer_clocksource_init(int gptimer_id,
- const char *fck_source,
- const char *property)
-{
- int res;
-
- clksrc.id = gptimer_id;
- clksrc.errata = omap_dm_timer_get_errata();
-
- res = omap_dm_timer_init_one(&clksrc, fck_source, property,
- &clocksource_gpt.name,
- OMAP_TIMER_NONPOSTED);
-
- if (soc_is_am43xx()) {
- clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend;
- clocksource_gpt.resume = omap2_gptimer_clksrc_resume;
-
- clocksource_gpt_hwmod =
- omap_hwmod_lookup(clocksource_gpt.name);
- }
-
- BUG_ON(res);
-
- __omap_dm_timer_load_start(&clksrc,
- OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
- OMAP_TIMER_NONPOSTED);
- sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
-
- if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
- pr_err("Could not register clocksource %s\n",
- clocksource_gpt.name);
- else
- pr_info("OMAP clocksource: %s at %lu Hz\n",
- clocksource_gpt.name, clksrc.rate);
-}
-
-static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
- const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
- const char *clksrc_prop, bool gptimer)
-{
- omap_clk_init();
- omap_dmtimer_init();
- dmtimer_clkevt_init_common(&clockevent, clkev_nr, clkev_src,
- CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- cpu_possible_mask, clkev_prop, 300, "clockevent");
- clockevents_config_and_register(&clockevent.dev, clockevent.timer.rate,
- 3, /* Timer internal resynch latency */
- 0xffffffff);
-
- if (soc_is_dra7xx())
- dmtimer_percpu_quirk_init();
-
- /* Enable the use of clocksource="gp_timer" kernel parameter */
- if (use_gptimer_clksrc || gptimer)
- omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
- clksrc_prop);
- else
- omap2_sync32k_clocksource_init();
-}
-
-void __init omap_init_time(void)
-{
- __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
- 2, "timer_sys_ck", NULL, false);
-
- timer_probe();
-}
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
-void __init omap3_secure_sync32k_timer_init(void)
-{
- __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
- 2, "timer_sys_ck", NULL, false);
-
- timer_probe();
-}
-#endif /* CONFIG_ARCH_OMAP3 */
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
- defined(CONFIG_SOC_AM43XX) || defined(CONFIG_SOC_DRA7XX)
-void __init omap3_gptimer_timer_init(void)
-{
- __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
- 1, "timer_sys_ck", "ti,timer-alwon", true);
- if (of_have_populated_dt())
- timer_probe();
-}
-#endif
-
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
- defined(CONFIG_SOC_DRA7XX)
-static void __init omap4_sync32k_timer_init(void)
-{
- __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
- 2, "sys_clkin_ck", NULL, false);
-}
-
-void __init omap4_local_timer_init(void)
-{
- omap4_sync32k_timer_init();
- timer_probe();
-}
-#endif
-
-#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
/*
* The realtime counter also called master counter, is a free-running
@@ -680,7 +57,6 @@
*/
static void __init realtime_counter_init(void)
{
-#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
void __iomem *base;
static struct clk *sys_clk;
unsigned long rate;
@@ -779,39 +155,12 @@
set_cntfreq();
iounmap(base);
-#endif
}
void __init omap5_realtime_timer_init(void)
{
- omap4_sync32k_timer_init();
+ omap_clk_init();
realtime_counter_init();
timer_probe();
}
-#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
-
-/**
- * omap2_override_clocksource - clocksource override with user configuration
- *
- * Allows user to override default clocksource, using kernel parameter
- * clocksource="gp_timer" (For all OMAP2PLUS architectures)
- *
- * Note that, here we are using same standard kernel parameter "clocksource=",
- * and not introducing any OMAP specific interface.
- */
-static int __init omap2_override_clocksource(char *str)
-{
- if (!str)
- return 0;
- /*
- * For OMAP architecture, we only have two options
- * - sync_32k (default)
- * - gp_timer (sys_clk based)
- */
- if (!strcmp(str, "gp_timer"))
- use_gptimer_clksrc = true;
-
- return 0;
-}
-early_param("clocksource", omap2_override_clocksource);
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index d76b1e5..86f1ac4 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -26,6 +26,31 @@
#include "scrm44xx.h"
#include "control.h"
+#define OMAP4430_VDD_IVA_I2C_DISABLE BIT(14)
+#define OMAP4430_VDD_MPU_I2C_DISABLE BIT(13)
+#define OMAP4430_VDD_CORE_I2C_DISABLE BIT(12)
+#define OMAP4430_VDD_IVA_PRESENCE BIT(9)
+#define OMAP4430_VDD_MPU_PRESENCE BIT(8)
+#define OMAP4430_AUTO_CTRL_VDD_IVA(x) ((x) << 4)
+#define OMAP4430_AUTO_CTRL_VDD_MPU(x) ((x) << 2)
+#define OMAP4430_AUTO_CTRL_VDD_CORE(x) ((x) << 0)
+#define OMAP4430_AUTO_CTRL_VDD_RET 2
+
+#define OMAP4430_VDD_I2C_DISABLE_MASK \
+ (OMAP4430_VDD_IVA_I2C_DISABLE | \
+ OMAP4430_VDD_MPU_I2C_DISABLE | \
+ OMAP4430_VDD_CORE_I2C_DISABLE)
+
+#define OMAP4_VDD_DEFAULT_VAL \
+ (OMAP4430_VDD_I2C_DISABLE_MASK | \
+ OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \
+ OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \
+ OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \
+ OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET))
+
+#define OMAP4_VDD_RET_VAL \
+ (OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK)
+
/**
* struct omap_vc_channel_cfg - describe the cfg_channel bitfield
* @sa: bit for slave address
@@ -280,6 +305,26 @@
}
}
+void omap4_vc_set_pmic_signaling(int core_next_state)
+{
+ struct voltagedomain *vd = vc.vd;
+ u32 val;
+
+ if (!vd)
+ return;
+
+ switch (core_next_state) {
+ case PWRDM_POWER_RET:
+ val = OMAP4_VDD_RET_VAL;
+ break;
+ default:
+ val = OMAP4_VDD_DEFAULT_VAL;
+ break;
+ }
+
+ vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET);
+}
+
/*
* Configure signal polarity for sys_clkreq and sys_off_mode pins
* as the default values are wrong and can cause the system to hang
@@ -542,9 +587,19 @@
writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
}
+static void __init omap4_vc_init_pmic_signaling(struct voltagedomain *voltdm)
+{
+ if (vc.vd)
+ return;
+
+ vc.vd = voltdm;
+ voltdm->write(OMAP4_VDD_DEFAULT_VAL, OMAP4_PRM_VOLTCTRL_OFFSET);
+}
+
/* OMAP4 specific voltage init functions */
static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
{
+ omap4_vc_init_pmic_signaling(voltdm);
omap4_set_timings(voltdm, true);
omap4_set_timings(voltdm, false);
}
@@ -615,7 +670,7 @@
const struct i2c_init_data *i2c_data;
if (!voltdm->pmic->i2c_high_speed) {
- pr_warn("%s: only high speed supported!\n", __func__);
+ pr_info("%s: using bootloader low-speed timings\n", __func__);
return;
}
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
index 5bf0886..9e861db 100644
--- a/arch/arm/mach-omap2/vc.h
+++ b/arch/arm/mach-omap2/vc.h
@@ -117,7 +117,7 @@
extern struct omap_vc_param omap4_core_vc_data;
void omap3_vc_set_pmic_signaling(int core_next_state);
-
+void omap4_vc_set_pmic_signaling(int core_next_state);
void omap_vc_init_channel(struct voltagedomain *voltdm);
int omap_vc_pre_scale(struct voltagedomain *voltdm,
diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c
index aac274d..e60d76d 100644
--- a/arch/arm/mach-omap2/voltagedomains54xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c
@@ -4,7 +4,7 @@
*
* Based on voltagedomains44xx_data.c
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*/
#include <linux/kernel.h>
#include <linux/err.h>
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index cf9cb3d..e94a619 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -3,7 +3,6 @@
bool "Marvell Orion"
depends on MMU && ARCH_MULTI_V5
select CPU_FEROCEON
- select GENERIC_CLOCKEVENTS
select GPIOLIB
select MVEBU_MBUS
select FORCE_PCI
@@ -18,7 +17,6 @@
config ARCH_ORION5X_DT
bool "Marvell Orion5x Flattened Device Tree"
- select USE_OF
select ORION_CLK
select ORION_IRQCHIP
select ORION_TIMER
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index d13344b..87cb472 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -624,7 +624,7 @@
dns323ab_leds[0].active_low = 1;
gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
- /* Fall through */
+ fallthrough;
case DNS323_REV_B1:
i2c_register_board_info(0, dns323ab_i2c_devices,
ARRAY_SIZE(dns323ab_i2c_devices));
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index fda9b75..a39764f 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -398,7 +398,6 @@
static int ts78xx_fpga_unload_devices(void)
{
- int ret = 0;
if (ts78xx_fpga.supports.ts_rtc.present == 1)
ts78xx_ts_rtc_unload();
@@ -407,7 +406,7 @@
if (ts78xx_fpga.supports.ts_rng.present == 1)
ts78xx_ts_rng_unload();
- return ret;
+ return 0;
}
static int ts78xx_fpga_load(void)
diff --git a/arch/arm/mach-oxnas/platsmp.c b/arch/arm/mach-oxnas/platsmp.c
index ab35275..f0a50b9 100644
--- a/arch/arm/mach-oxnas/platsmp.c
+++ b/arch/arm/mach-oxnas/platsmp.c
@@ -27,7 +27,8 @@
#define GIC_CPU_CTRL 0x00
#define GIC_CPU_CTRL_ENABLE 1
-int __init ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __init ox820_boot_secondary(unsigned int cpu,
+ struct task_struct *idle)
{
/*
* Write the address of secondary startup into the
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 6f66785..ea077f6 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -30,7 +30,6 @@
select ARM_GIC
select ATLAS7_TIMER
select HAVE_ARM_SCU if SMP
- select HAVE_SMP
help
Support for CSR SiRFSoC ARM Cortex A7 Platform
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index f60bc29..f7520a6 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -123,23 +123,6 @@
bool "Enable support for CSB701 baseboard"
depends on MACH_CSB726
-config MACH_ARMCORE
- bool "CompuLab CM-X255/CM-X270 modules"
- select ARCH_HAS_DMA_SET_COHERENT_MASK if PCI
- select IWMMXT
- select HAVE_PCI
- select NEED_MACH_IO_H if PCI
- select PXA25x
- select PXA27x
-
-config MACH_EM_X270
- bool "CompuLab EM-x270 platform"
- select PXA27x
-
-config MACH_EXEDA
- bool "CompuLab eXeda platform"
- select PXA27x
-
config MACH_CM_X300
bool "CompuLab CM-X300 modules"
select CPU_PXA300
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index f707289..177abe5 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -40,11 +40,6 @@
obj-$(CONFIG_MACH_BALLOON3) += balloon3.o
obj-$(CONFIG_MACH_CSB726) += csb726.o
obj-$(CONFIG_CSB726_CSB701) += csb701.o
-obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o
-ifeq ($(CONFIG_PCI),y)
-obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o
-endif
-obj-$(CONFIG_MACH_EM_X270) += em-x270.o
obj-$(CONFIG_MACH_CM_X300) += cm-x300.o
obj-$(CONFIG_MACH_CAPC7117) += capc7117.o mxm8x10.o
obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o
diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c
deleted file mode 100644
index ea1e857..0000000
--- a/arch/arm/mach-pxa/cm-x255.c
+++ /dev/null
@@ -1,240 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/cm-x255.c
- *
- * Copyright (C) 2007, 2008 CompuLab, Ltd.
- * Mike Rapoport <mike@compulab.co.il>
- */
-
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/nand-gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/pxa2xx_spi.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-
-#include "pxa25x.h"
-
-#include "generic.h"
-
-#define GPIO_NAND_CS (5)
-#define GPIO_NAND_ALE (4)
-#define GPIO_NAND_CLE (3)
-#define GPIO_NAND_RB (10)
-
-static unsigned long cmx255_pin_config[] = {
- /* AC'97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- /* STUART */
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* SSP1 */
- GPIO23_SSP1_SCLK,
- GPIO24_SSP1_SFRM,
- GPIO25_SSP1_TXD,
- GPIO26_SSP1_RXD,
-
- /* SSP2 */
- GPIO81_SSP2_CLK_OUT,
- GPIO82_SSP2_FRM_OUT,
- GPIO83_SSP2_TXD,
- GPIO84_SSP2_RXD,
-
- /* PC Card */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO52_nPCE_1,
- GPIO53_nPCE_2,
- GPIO54_nPSKTSEL,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
-
- /* SDRAM and local bus */
- GPIO15_nCS_1,
- GPIO78_nCS_2,
- GPIO79_nCS_3,
- GPIO80_nCS_4,
- GPIO33_nCS_5,
- GPIO18_RDY,
-
- /* GPIO */
- GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,
- GPIO9_GPIO, /* PC card reset */
-
- /* NAND controls */
- GPIO5_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
- GPIO4_GPIO | MFP_LPM_DRIVE_LOW, /* NAND ALE */
- GPIO3_GPIO | MFP_LPM_DRIVE_LOW, /* NAND CLE */
- GPIO10_GPIO, /* NAND Ready/Busy */
-
- /* interrupts */
- GPIO22_GPIO, /* DM9000 interrupt */
-};
-
-#if defined(CONFIG_SPI_PXA2XX)
-static struct pxa2xx_spi_controller pxa_ssp_master_info = {
- .num_chipselect = 1,
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
- [0] = {
- .modalias = "rtc-max6902",
- .max_speed_hz = 1000000,
- .bus_num = 1,
- .chip_select = 0,
- },
-};
-
-static void __init cmx255_init_rtc(void)
-{
- pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
- spi_register_board_info(ARRAY_AND_SIZE(spi_board_info));
-}
-#else
-static inline void cmx255_init_rtc(void) {}
-#endif
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static struct mtd_partition cmx255_nor_partitions[] = {
- {
- .name = "ARMmon",
- .size = 0x00030000,
- .offset = 0,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- } , {
- .name = "ARMmon setup block",
- .size = 0x00010000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- } , {
- .name = "kernel",
- .size = 0x00160000,
- .offset = MTDPART_OFS_APPEND,
- } , {
- .name = "ramdisk",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND
- }
-};
-
-static struct physmap_flash_data cmx255_nor_flash_data[] = {
- {
- .width = 2, /* bankwidth in bytes */
- .parts = cmx255_nor_partitions,
- .nr_parts = ARRAY_SIZE(cmx255_nor_partitions)
- }
-};
-
-static struct resource cmx255_nor_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_8M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device cmx255_nor = {
- .name = "physmap-flash",
- .id = -1,
- .dev = {
- .platform_data = cmx255_nor_flash_data,
- },
- .resource = &cmx255_nor_resource,
- .num_resources = 1,
-};
-
-static void __init cmx255_init_nor(void)
-{
- platform_device_register(&cmx255_nor);
-}
-#else
-static inline void cmx255_init_nor(void) {}
-#endif
-
-#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
-
-static struct gpiod_lookup_table cmx255_nand_gpiod_table = {
- .dev_id = "gpio-nand",
- .table = {
- GPIO_LOOKUP("gpio-pxa", GPIO_NAND_CS, "nce", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO_NAND_CLE, "cle", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO_NAND_ALE, "ale", GPIO_ACTIVE_HIGH),
- GPIO_LOOKUP("gpio-pxa", GPIO_NAND_RB, "rdy", GPIO_ACTIVE_HIGH),
- },
-};
-
-static struct resource cmx255_nand_resource[] = {
- [0] = {
- .start = PXA_CS1_PHYS,
- .end = PXA_CS1_PHYS + 11,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_CS5_PHYS,
- .end = PXA_CS5_PHYS + 3,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct mtd_partition cmx255_nand_parts[] = {
- [0] = {
- .name = "cmx255-nand",
- .size = MTDPART_SIZ_FULL,
- .offset = 0,
- },
-};
-
-static struct gpio_nand_platdata cmx255_nand_platdata = {
- .parts = cmx255_nand_parts,
- .num_parts = ARRAY_SIZE(cmx255_nand_parts),
- .chip_delay = 25,
-};
-
-static struct platform_device cmx255_nand = {
- .name = "gpio-nand",
- .num_resources = ARRAY_SIZE(cmx255_nand_resource),
- .resource = cmx255_nand_resource,
- .id = -1,
- .dev = {
- .platform_data = &cmx255_nand_platdata,
- }
-};
-
-static void __init cmx255_init_nand(void)
-{
- gpiod_add_lookup_table(&cmx255_nand_gpiod_table);
- platform_device_register(&cmx255_nand);
-}
-#else
-static inline void cmx255_init_nand(void) {}
-#endif
-
-void __init cmx255_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config));
-
- cmx255_init_rtc();
- cmx255_init_nor();
- cmx255_init_nand();
-}
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
deleted file mode 100644
index 9baad11..0000000
--- a/arch/arm/mach-pxa/cm-x270.c
+++ /dev/null
@@ -1,419 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/cm-x270.c
- *
- * Copyright (C) 2007, 2008 CompuLab, Ltd.
- * Mike Rapoport <mike@compulab.co.il>
- */
-
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/delay.h>
-
-#include <linux/platform_data/rtc-v3020.h>
-#include <video/mbxfb.h>
-
-#include <linux/spi/spi.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/spi/libertas_spi.h>
-
-#include "pxa27x.h"
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/mmc-pxamci.h>
-
-#include "generic.h"
-
-/* physical address if local-bus attached devices */
-#define RTC_PHYS_BASE (PXA_CS1_PHYS + (5 << 22))
-
-/* GPIO IRQ usage */
-#define GPIO83_MMC_IRQ (83)
-
-#define CMX270_MMC_IRQ PXA_GPIO_TO_IRQ(GPIO83_MMC_IRQ)
-
-/* MMC power enable */
-#define GPIO105_MMC_POWER (105)
-
-/* WLAN GPIOS */
-#define GPIO19_WLAN_STRAP (19)
-#define GPIO102_WLAN_RST (102)
-
-static unsigned long cmx270_pin_config[] = {
- /* AC'97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO98_AC97_SYSCLK,
- GPIO113_AC97_nRESET,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- /* STUART */
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-
- /* MCI controller */
- GPIO32_MMC_CLK,
- GPIO112_MMC_CMD,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* SSP1 */
- GPIO23_SSP1_SCLK,
- GPIO24_SSP1_SFRM,
- GPIO25_SSP1_TXD,
- GPIO26_SSP1_RXD,
-
- /* SSP2 */
- GPIO19_GPIO, /* SSP2 clock is used as GPIO for Libertas pin-strap */
- GPIO14_GPIO,
- GPIO87_SSP2_TXD,
- GPIO88_SSP2_RXD,
-
- /* PC Card */
- GPIO48_nPOE,
- GPIO49_nPWE,
- GPIO50_nPIOR,
- GPIO51_nPIOW,
- GPIO85_nPCE_1,
- GPIO54_nPCE_2,
- GPIO55_nPREG,
- GPIO56_nPWAIT,
- GPIO57_nIOIS16,
-
- /* SDRAM and local bus */
- GPIO15_nCS_1,
- GPIO78_nCS_2,
- GPIO79_nCS_3,
- GPIO80_nCS_4,
- GPIO33_nCS_5,
- GPIO49_nPWE,
- GPIO18_RDY,
-
- /* GPIO */
- GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,
- GPIO105_GPIO | MFP_LPM_DRIVE_HIGH, /* MMC/SD power */
- GPIO53_GPIO, /* PC card reset */
- GPIO102_GPIO, /* WLAN reset */
-
- /* NAND controls */
- GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
- GPIO89_GPIO, /* NAND Ready/Busy */
-
- /* interrupts */
- GPIO10_GPIO, /* DM9000 interrupt */
- GPIO83_GPIO, /* MMC card detect */
- GPIO95_GPIO, /* WLAN interrupt */
-};
-
-/* V3020 RTC */
-#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
-static struct resource cmx270_v3020_resource[] = {
- [0] = {
- .start = RTC_PHYS_BASE,
- .end = RTC_PHYS_BASE + 4,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct v3020_platform_data cmx270_v3020_pdata = {
- .leftshift = 16,
-};
-
-static struct platform_device cmx270_rtc_device = {
- .name = "v3020",
- .num_resources = ARRAY_SIZE(cmx270_v3020_resource),
- .resource = cmx270_v3020_resource,
- .id = -1,
- .dev = {
- .platform_data = &cmx270_v3020_pdata,
- }
-};
-
-static void __init cmx270_init_rtc(void)
-{
- platform_device_register(&cmx270_rtc_device);
-}
-#else
-static inline void cmx270_init_rtc(void) {}
-#endif
-
-/* 2700G graphics */
-#if defined(CONFIG_FB_MBX) || defined(CONFIG_FB_MBX_MODULE)
-static u64 fb_dma_mask = ~(u64)0;
-
-static struct resource cmx270_2700G_resource[] = {
- /* frame buffer memory including ODFB and External SDRAM */
- [0] = {
- .start = PXA_CS2_PHYS,
- .end = PXA_CS2_PHYS + 0x01ffffff,
- .flags = IORESOURCE_MEM,
- },
- /* Marathon registers */
- [1] = {
- .start = PXA_CS2_PHYS + 0x03fe0000,
- .end = PXA_CS2_PHYS + 0x03ffffff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static unsigned long cmx270_marathon_on[] = {
- GPIO58_GPIO,
- GPIO59_GPIO,
- GPIO60_GPIO,
- GPIO61_GPIO,
- GPIO62_GPIO,
- GPIO63_GPIO,
- GPIO64_GPIO,
- GPIO65_GPIO,
- GPIO66_GPIO,
- GPIO67_GPIO,
- GPIO68_GPIO,
- GPIO69_GPIO,
- GPIO70_GPIO,
- GPIO71_GPIO,
- GPIO72_GPIO,
- GPIO73_GPIO,
- GPIO74_GPIO,
- GPIO75_GPIO,
- GPIO76_GPIO,
- GPIO77_GPIO,
-};
-
-static unsigned long cmx270_marathon_off[] = {
- GPIOxx_LCD_TFT_16BPP,
-};
-
-static int cmx270_marathon_probe(struct fb_info *fb)
-{
- int gpio, err;
-
- for (gpio = 58; gpio <= 77; gpio++) {
- err = gpio_request(gpio, "LCD");
- if (err)
- return err;
- gpio_direction_input(gpio);
- }
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_marathon_on));
- return 0;
-}
-
-static int cmx270_marathon_remove(struct fb_info *fb)
-{
- int gpio;
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_marathon_off));
-
- for (gpio = 58; gpio <= 77; gpio++)
- gpio_free(gpio);
-
- return 0;
-}
-
-static struct mbxfb_platform_data cmx270_2700G_data = {
- .xres = {
- .min = 240,
- .max = 1200,
- .defval = 640,
- },
- .yres = {
- .min = 240,
- .max = 1200,
- .defval = 480,
- },
- .bpp = {
- .min = 16,
- .max = 32,
- .defval = 16,
- },
- .memsize = 8*1024*1024,
- .probe = cmx270_marathon_probe,
- .remove = cmx270_marathon_remove,
-};
-
-static struct platform_device cmx270_2700G = {
- .name = "mbx-fb",
- .dev = {
- .platform_data = &cmx270_2700G_data,
- .dma_mask = &fb_dma_mask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(cmx270_2700G_resource),
- .resource = cmx270_2700G_resource,
- .id = -1,
-};
-
-static void __init cmx270_init_2700G(void)
-{
- platform_device_register(&cmx270_2700G);
-}
-#else
-static inline void cmx270_init_2700G(void) {}
-#endif
-
-/* PXA27x OHCI controller setup */
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static struct pxaohci_platform_data cmx270_ohci_platform_data = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
-};
-
-static void __init cmx270_init_ohci(void)
-{
- pxa_set_ohci_info(&cmx270_ohci_platform_data);
-}
-#else
-static inline void cmx270_init_ohci(void) {}
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
-static struct pxamci_platform_data cmx270_mci_platform_data = {
- .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
-};
-
-static struct gpiod_lookup_table cmx270_mci_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- /* Card detect on GPIO 83 */
- GPIO_LOOKUP("gpio-pxa", GPIO83_MMC_IRQ, "cd", GPIO_ACTIVE_LOW),
- /* Power on GPIO 105 */
- GPIO_LOOKUP("gpio-pxa", GPIO105_MMC_POWER,
- "power", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static void __init cmx270_init_mmc(void)
-{
- gpiod_add_lookup_table(&cmx270_mci_gpio_table);
- pxa_set_mci_info(&cmx270_mci_platform_data);
-}
-#else
-static inline void cmx270_init_mmc(void) {}
-#endif
-
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_controller cm_x270_spi_info = {
- .num_chipselect = 1,
- .enable_dma = 1,
-};
-
-static struct pxa2xx_spi_chip cm_x270_libertas_chip = {
- .rx_threshold = 1,
- .tx_threshold = 1,
- .timeout = 1000,
- .gpio_cs = 14,
-};
-
-static unsigned long cm_x270_libertas_pin_config[] = {
- /* SSP2 */
- GPIO19_SSP2_SCLK,
- GPIO14_GPIO,
- GPIO87_SSP2_TXD,
- GPIO88_SSP2_RXD,
-
-};
-
-static int cm_x270_libertas_setup(struct spi_device *spi)
-{
- int err = gpio_request(GPIO19_WLAN_STRAP, "WLAN STRAP");
- if (err)
- return err;
-
- err = gpio_request(GPIO102_WLAN_RST, "WLAN RST");
- if (err)
- goto err_free_strap;
-
- err = gpio_direction_output(GPIO102_WLAN_RST, 0);
- if (err)
- goto err_free_strap;
- msleep(100);
-
- err = gpio_direction_output(GPIO19_WLAN_STRAP, 1);
- if (err)
- goto err_free_strap;
- msleep(100);
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(cm_x270_libertas_pin_config));
-
- gpio_set_value(GPIO102_WLAN_RST, 1);
- msleep(100);
-
- spi->bits_per_word = 16;
- spi_setup(spi);
-
- return 0;
-
-err_free_strap:
- gpio_free(GPIO19_WLAN_STRAP);
-
- return err;
-}
-
-static int cm_x270_libertas_teardown(struct spi_device *spi)
-{
- gpio_set_value(GPIO102_WLAN_RST, 0);
- gpio_free(GPIO102_WLAN_RST);
- gpio_free(GPIO19_WLAN_STRAP);
-
- return 0;
-}
-
-struct libertas_spi_platform_data cm_x270_libertas_pdata = {
- .use_dummy_writes = 1,
- .setup = cm_x270_libertas_setup,
- .teardown = cm_x270_libertas_teardown,
-};
-
-static struct spi_board_info cm_x270_spi_devices[] __initdata = {
- {
- .modalias = "libertas_spi",
- .max_speed_hz = 13000000,
- .bus_num = 2,
- .irq = PXA_GPIO_TO_IRQ(95),
- .chip_select = 0,
- .controller_data = &cm_x270_libertas_chip,
- .platform_data = &cm_x270_libertas_pdata,
- },
-};
-
-static void __init cmx270_init_spi(void)
-{
- pxa2xx_set_spi_info(2, &cm_x270_spi_info);
- spi_register_board_info(ARRAY_AND_SIZE(cm_x270_spi_devices));
-}
-#else
-static inline void cmx270_init_spi(void) {}
-#endif
-
-void __init cmx270_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_pin_config));
-
-#ifdef CONFIG_PM
- pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP);
-#endif
-
- cmx270_init_rtc();
- cmx270_init_mmc();
- cmx270_init_ohci();
- cmx270_init_2700G();
- cmx270_init_spi();
-}
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
deleted file mode 100644
index f1c61c6..0000000
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ /dev/null
@@ -1,196 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/cm-x2xx-pci.c
- *
- * PCI bios-type initialisation for PCI machines
- *
- * Bits taken from various places.
- *
- * Copyright (C) 2007, 2008 Compulab, Ltd.
- * Mike Rapoport <mike@compulab.co.il>
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/pci.h>
-#include <asm/mach-types.h>
-
-#include <asm/hardware/it8152.h>
-
-void __iomem *it8152_base_address;
-static int cmx2xx_it8152_irq_gpio;
-
-static void cmx2xx_it8152_irq_demux(struct irq_desc *desc)
-{
- /* clear our parent irq */
- desc->irq_data.chip->irq_ack(&desc->irq_data);
-
- it8152_irq_demux(desc);
-}
-
-void __cmx2xx_pci_init_irq(int irq_gpio)
-{
- it8152_init_irq();
-
- cmx2xx_it8152_irq_gpio = irq_gpio;
-
- irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
-
- irq_set_chained_handler(gpio_to_irq(irq_gpio),
- cmx2xx_it8152_irq_demux);
-}
-
-#ifdef CONFIG_PM
-static unsigned long sleep_save_ite[10];
-
-void __cmx2xx_pci_suspend(void)
-{
- /* save ITE state */
- sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
- sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR);
- sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR);
-
- /* Clear ITE IRQ's */
- __raw_writel((0), IT8152_INTC_PDCNIRR);
- __raw_writel((0), IT8152_INTC_LPCNIRR);
-}
-
-void __cmx2xx_pci_resume(void)
-{
- /* restore IT8152 state */
- __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
- __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR);
- __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
-}
-#else
-void cmx2xx_pci_suspend(void) {}
-void cmx2xx_pci_resume(void) {}
-#endif
-
-/* PCI IRQ mapping*/
-static int __init cmx2xx_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq;
-
- dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __func__, slot, pin);
-
- irq = it8152_pci_map_irq(dev, slot, pin);
- if (irq)
- return irq;
-
- /*
- Here comes the ugly part. The routing is baseboard specific,
- but defining a platform for each possible base of CM-X2XX is
- unrealistic. Here we keep mapping for ATXBase and SB-X2XX.
- */
- /* ATXBASE PCI slot */
- if (slot == 7)
- return IT8152_PCI_INTA;
-
- /* ATXBase/SB-X2XX CardBus */
- if (slot == 8 || slot == 0)
- return IT8152_PCI_INTB;
-
- /* ATXBase Ethernet */
- if (slot == 9)
- return IT8152_PCI_INTA;
-
- /* CM-x255 Onboard Ethernet */
- if (slot == 15)
- return IT8152_PCI_INTC;
-
- /* SB-x2xx Ethernet */
- if (slot == 16)
- return IT8152_PCI_INTA;
-
- /* PC104+ interrupt routing */
- if ((slot == 17) || (slot == 19))
- return IT8152_PCI_INTA;
- if ((slot == 18) || (slot == 20))
- return IT8152_PCI_INTB;
-
- return(0);
-}
-
-static void cmx2xx_pci_preinit(void)
-{
- pr_info("Initializing CM-X2XX PCI subsystem\n");
-
- pcibios_min_io = 0;
- pcibios_min_mem = 0;
-
- __raw_writel(0x800, IT8152_PCI_CFG_ADDR);
- if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
- pr_info("PCI Bridge found.\n");
-
- /* set PCI I/O base at 0 */
- writel(0x848, IT8152_PCI_CFG_ADDR);
- writel(0, IT8152_PCI_CFG_DATA);
-
- /* set PCI memory base at 0 */
- writel(0x840, IT8152_PCI_CFG_ADDR);
- writel(0, IT8152_PCI_CFG_DATA);
-
- writel(0x20, IT8152_GPIO_GPDR);
-
- /* CardBus Controller on ATXbase baseboard */
- writel(0x4000, IT8152_PCI_CFG_ADDR);
- if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
- pr_info("CardBus Bridge found.\n");
-
- /* Configure socket 0 */
- writel(0x408C, IT8152_PCI_CFG_ADDR);
- writel(0x1022, IT8152_PCI_CFG_DATA);
-
- writel(0x4080, IT8152_PCI_CFG_ADDR);
- writel(0x3844d060, IT8152_PCI_CFG_DATA);
-
- writel(0x4090, IT8152_PCI_CFG_ADDR);
- writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
- 0x60440000),
- IT8152_PCI_CFG_DATA);
-
- writel(0x4018, IT8152_PCI_CFG_ADDR);
- writel(0xb0000000, IT8152_PCI_CFG_DATA);
-
- /* Configure socket 1 */
- writel(0x418C, IT8152_PCI_CFG_ADDR);
- writel(0x1022, IT8152_PCI_CFG_DATA);
-
- writel(0x4180, IT8152_PCI_CFG_ADDR);
- writel(0x3844d060, IT8152_PCI_CFG_DATA);
-
- writel(0x4190, IT8152_PCI_CFG_ADDR);
- writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
- 0x60440000),
- IT8152_PCI_CFG_DATA);
-
- writel(0x4118, IT8152_PCI_CFG_ADDR);
- writel(0xb0000000, IT8152_PCI_CFG_DATA);
- }
- }
-}
-
-static struct hw_pci cmx2xx_pci __initdata = {
- .map_irq = cmx2xx_pci_map_irq,
- .nr_controllers = 1,
- .ops = &it8152_ops,
- .setup = it8152_pci_setup,
- .preinit = cmx2xx_pci_preinit,
-};
-
-static int __init cmx2xx_init_pci(void)
-{
- if (machine_is_armcore())
- pci_common_init(&cmx2xx_pci);
-
- return 0;
-}
-
-subsys_initcall(cmx2xx_init_pci);
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.h b/arch/arm/mach-pxa/cm-x2xx-pci.h
deleted file mode 100644
index 93ffaae..0000000
--- a/arch/arm/mach-pxa/cm-x2xx-pci.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-extern void __cmx2xx_pci_init_irq(int irq_gpio);
-extern void __cmx2xx_pci_suspend(void);
-extern void __cmx2xx_pci_resume(void);
-
-#ifdef CONFIG_PCI
-#define cmx2xx_pci_init_irq(x) __cmx2xx_pci_init_irq(x)
-#define cmx2xx_pci_suspend(x) __cmx2xx_pci_suspend(x)
-#define cmx2xx_pci_resume(x) __cmx2xx_pci_resume(x)
-#else
-#define cmx2xx_pci_init_irq(x) do {} while (0)
-#define cmx2xx_pci_suspend(x) do {} while (0)
-#define cmx2xx_pci_resume(x) do {} while (0)
-#endif
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
deleted file mode 100644
index ff976d1..0000000
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ /dev/null
@@ -1,538 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-pxa/cm-x2xx.c
- *
- * Copyright (C) 2008 CompuLab, Ltd.
- * Mike Rapoport <mike@compulab.co.il>
- */
-
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/regulator/machine.h>
-
-#include <linux/dm9000.h>
-#include <linux/leds.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-
-#include "pxa25x.h"
-#undef GPIO24_SSP1_SFRM
-#undef GPIO86_GPIO
-#undef GPIO87_GPIO
-#undef GPIO88_GPIO
-#undef GPIO89_GPIO
-#include "pxa27x.h"
-#undef GPIO24_SSP1_SFRM
-#undef GPIO86_GPIO
-#undef GPIO87_GPIO
-#undef GPIO88_GPIO
-#undef GPIO89_GPIO
-#include <mach/audio.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <mach/smemc.h>
-
-#include <asm/hardware/it8152.h>
-
-#include "generic.h"
-#include "cm-x2xx-pci.h"
-
-extern void cmx255_init(void);
-extern void cmx270_init(void);
-
-/* reserve IRQs for IT8152 */
-#define CMX2XX_NR_IRQS (IRQ_BOARD_START + 40)
-
-/* virtual addresses for statically mapped regions */
-#define CMX2XX_VIRT_BASE (void __iomem *)(0xe8000000)
-#define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE)
-
-/* physical address if local-bus attached devices */
-#define CMX255_DM9000_PHYS_BASE (PXA_CS1_PHYS + (8 << 22))
-#define CMX270_DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22))
-
-/* leds */
-#define CMX255_GPIO_RED (27)
-#define CMX255_GPIO_GREEN (32)
-#define CMX270_GPIO_RED (93)
-#define CMX270_GPIO_GREEN (94)
-
-/* GPIO IRQ usage */
-#define GPIO22_ETHIRQ (22)
-#define GPIO10_ETHIRQ (10)
-#define CMX255_GPIO_IT8152_IRQ (0)
-#define CMX270_GPIO_IT8152_IRQ (22)
-
-#define CMX255_ETHIRQ PXA_GPIO_TO_IRQ(GPIO22_ETHIRQ)
-#define CMX270_ETHIRQ PXA_GPIO_TO_IRQ(GPIO10_ETHIRQ)
-
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
-static struct resource cmx255_dm9000_resource[] = {
- [0] = {
- .start = CMX255_DM9000_PHYS_BASE,
- .end = CMX255_DM9000_PHYS_BASE + 3,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CMX255_DM9000_PHYS_BASE + 4,
- .end = CMX255_DM9000_PHYS_BASE + 4 + 500,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = CMX255_ETHIRQ,
- .end = CMX255_ETHIRQ,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct resource cmx270_dm9000_resource[] = {
- [0] = {
- .start = CMX270_DM9000_PHYS_BASE,
- .end = CMX270_DM9000_PHYS_BASE + 3,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CMX270_DM9000_PHYS_BASE + 8,
- .end = CMX270_DM9000_PHYS_BASE + 8 + 500,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = CMX270_ETHIRQ,
- .end = CMX270_ETHIRQ,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct dm9000_plat_data cmx270_dm9000_platdata = {
- .flags = DM9000_PLATF_32BITONLY | DM9000_PLATF_NO_EEPROM,
-};
-
-static struct platform_device cmx2xx_dm9000_device = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(cmx270_dm9000_resource),
- .dev = {
- .platform_data = &cmx270_dm9000_platdata,
- }
-};
-
-static void __init cmx2xx_init_dm9000(void)
-{
- if (cpu_is_pxa25x())
- cmx2xx_dm9000_device.resource = cmx255_dm9000_resource;
- else
- cmx2xx_dm9000_device.resource = cmx270_dm9000_resource;
- platform_device_register(&cmx2xx_dm9000_device);
-}
-#else
-static inline void cmx2xx_init_dm9000(void) {}
-#endif
-
-/* UCB1400 touchscreen controller */
-#if defined(CONFIG_TOUCHSCREEN_UCB1400) || defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
-static struct platform_device cmx2xx_ts_device = {
- .name = "ucb1400_core",
- .id = -1,
-};
-
-static void __init cmx2xx_init_touchscreen(void)
-{
- platform_device_register(&cmx2xx_ts_device);
-}
-#else
-static inline void cmx2xx_init_touchscreen(void) {}
-#endif
-
-/* CM-X270 LEDs */
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-static struct gpio_led cmx2xx_leds[] = {
- [0] = {
- .name = "cm-x2xx:red",
- .default_trigger = "nand-disk",
- .active_low = 1,
- },
- [1] = {
- .name = "cm-x2xx:green",
- .default_trigger = "heartbeat",
- .active_low = 1,
- },
-};
-
-static struct gpio_led_platform_data cmx2xx_gpio_led_pdata = {
- .num_leds = ARRAY_SIZE(cmx2xx_leds),
- .leds = cmx2xx_leds,
-};
-
-static struct platform_device cmx2xx_led_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &cmx2xx_gpio_led_pdata,
- },
-};
-
-static void __init cmx2xx_init_leds(void)
-{
- if (cpu_is_pxa25x()) {
- cmx2xx_leds[0].gpio = CMX255_GPIO_RED;
- cmx2xx_leds[1].gpio = CMX255_GPIO_GREEN;
- } else {
- cmx2xx_leds[0].gpio = CMX270_GPIO_RED;
- cmx2xx_leds[1].gpio = CMX270_GPIO_GREEN;
- }
- platform_device_register(&cmx2xx_led_device);
-}
-#else
-static inline void cmx2xx_init_leds(void) {}
-#endif
-
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-/*
- Display definitions
- keep these for backwards compatibility, although symbolic names (as
- e.g. in lpd270.c) looks better
-*/
-#define MTYPE_STN320x240 0
-#define MTYPE_TFT640x480 1
-#define MTYPE_CRT640x480 2
-#define MTYPE_CRT800x600 3
-#define MTYPE_TFT320x240 6
-#define MTYPE_STN640x480 7
-
-static struct pxafb_mode_info generic_stn_320x240_mode = {
- .pixclock = 76923,
- .bpp = 8,
- .xres = 320,
- .yres = 240,
- .hsync_len = 3,
- .vsync_len = 2,
- .left_margin = 3,
- .upper_margin = 0,
- .right_margin = 3,
- .lower_margin = 0,
- .sync = (FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_VERT_HIGH_ACT),
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_stn_320x240 = {
- .modes = &generic_stn_320x240_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_STN_8BPP | LCD_PCLK_EDGE_FALL |\
- LCD_AC_BIAS_FREQ(0xff),
- .cmap_inverse = 0,
- .cmap_static = 0,
-};
-
-static struct pxafb_mode_info generic_tft_640x480_mode = {
- .pixclock = 38461,
- .bpp = 8,
- .xres = 640,
- .yres = 480,
- .hsync_len = 60,
- .vsync_len = 2,
- .left_margin = 70,
- .upper_margin = 10,
- .right_margin = 70,
- .lower_margin = 5,
- .sync = 0,
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_tft_640x480 = {
- .modes = &generic_tft_640x480_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_PCLK_EDGE_FALL |\
- LCD_AC_BIAS_FREQ(0xff),
- .cmap_inverse = 0,
- .cmap_static = 0,
-};
-
-static struct pxafb_mode_info generic_crt_640x480_mode = {
- .pixclock = 38461,
- .bpp = 8,
- .xres = 640,
- .yres = 480,
- .hsync_len = 63,
- .vsync_len = 2,
- .left_margin = 81,
- .upper_margin = 33,
- .right_margin = 16,
- .lower_margin = 10,
- .sync = (FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_VERT_HIGH_ACT),
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_crt_640x480 = {
- .modes = &generic_crt_640x480_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff),
- .cmap_inverse = 0,
- .cmap_static = 0,
-};
-
-static struct pxafb_mode_info generic_crt_800x600_mode = {
- .pixclock = 28846,
- .bpp = 8,
- .xres = 800,
- .yres = 600,
- .hsync_len = 63,
- .vsync_len = 2,
- .left_margin = 26,
- .upper_margin = 21,
- .right_margin = 26,
- .lower_margin = 11,
- .sync = (FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_VERT_HIGH_ACT),
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_crt_800x600 = {
- .modes = &generic_crt_800x600_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff),
- .cmap_inverse = 0,
- .cmap_static = 0,
-};
-
-static struct pxafb_mode_info generic_tft_320x240_mode = {
- .pixclock = 134615,
- .bpp = 16,
- .xres = 320,
- .yres = 240,
- .hsync_len = 63,
- .vsync_len = 7,
- .left_margin = 75,
- .upper_margin = 0,
- .right_margin = 15,
- .lower_margin = 15,
- .sync = 0,
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_tft_320x240 = {
- .modes = &generic_tft_320x240_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_AC_BIAS_FREQ(0xff),
- .cmap_inverse = 0,
- .cmap_static = 0,
-};
-
-static struct pxafb_mode_info generic_stn_640x480_mode = {
- .pixclock = 57692,
- .bpp = 8,
- .xres = 640,
- .yres = 480,
- .hsync_len = 4,
- .vsync_len = 2,
- .left_margin = 10,
- .upper_margin = 5,
- .right_margin = 10,
- .lower_margin = 5,
- .sync = (FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_VERT_HIGH_ACT),
- .cmap_greyscale = 0,
-};
-
-static struct pxafb_mach_info generic_stn_640x480 = {
- .modes = &generic_stn_640x480_mode,
- .num_modes = 1,
- .lcd_conn = LCD_COLOR_STN_8BPP | LCD_AC_BIAS_FREQ(0xff),
- .cmap_inverse = 0,
- .cmap_static = 0,
-};
-
-static struct pxafb_mach_info *cmx2xx_display = &generic_crt_640x480;
-
-static int __init cmx2xx_set_display(char *str)
-{
- int disp_type = simple_strtol(str, NULL, 0);
- switch (disp_type) {
- case MTYPE_STN320x240:
- cmx2xx_display = &generic_stn_320x240;
- break;
- case MTYPE_TFT640x480:
- cmx2xx_display = &generic_tft_640x480;
- break;
- case MTYPE_CRT640x480:
- cmx2xx_display = &generic_crt_640x480;
- break;
- case MTYPE_CRT800x600:
- cmx2xx_display = &generic_crt_800x600;
- break;
- case MTYPE_TFT320x240:
- cmx2xx_display = &generic_tft_320x240;
- break;
- case MTYPE_STN640x480:
- cmx2xx_display = &generic_stn_640x480;
- break;
- default: /* fallback to CRT 640x480 */
- cmx2xx_display = &generic_crt_640x480;
- break;
- }
- return 1;
-}
-
-/*
- This should be done really early to get proper configuration for
- frame buffer.
- Indeed, pxafb parameters can be used istead, but CM-X2XX bootloader
- has limitied line length for kernel command line, and also it will
- break compatibitlty with proprietary releases already in field.
-*/
-__setup("monitor=", cmx2xx_set_display);
-
-static void __init cmx2xx_init_display(void)
-{
- pxa_set_fb_info(NULL, cmx2xx_display);
-}
-#else
-static inline void cmx2xx_init_display(void) {}
-#endif
-
-#ifdef CONFIG_PM
-static unsigned long sleep_save_msc[10];
-
-static int cmx2xx_suspend(void)
-{
- cmx2xx_pci_suspend();
-
- /* save MSC registers */
- sleep_save_msc[0] = __raw_readl(MSC0);
- sleep_save_msc[1] = __raw_readl(MSC1);
- sleep_save_msc[2] = __raw_readl(MSC2);
-
- /* setup power saving mode registers */
- PCFR = 0x0;
- PSLR = 0xff400000;
- PMCR = 0x00000005;
- PWER = 0x80000000;
- PFER = 0x00000000;
- PRER = 0x00000000;
- PGSR0 = 0xC0018800;
- PGSR1 = 0x004F0002;
- PGSR2 = 0x6021C000;
- PGSR3 = 0x00020000;
-
- return 0;
-}
-
-static void cmx2xx_resume(void)
-{
- cmx2xx_pci_resume();
-
- /* restore MSC registers */
- __raw_writel(sleep_save_msc[0], MSC0);
- __raw_writel(sleep_save_msc[1], MSC1);
- __raw_writel(sleep_save_msc[2], MSC2);
-}
-
-static struct syscore_ops cmx2xx_pm_syscore_ops = {
- .resume = cmx2xx_resume,
- .suspend = cmx2xx_suspend,
-};
-
-static int __init cmx2xx_pm_init(void)
-{
- register_syscore_ops(&cmx2xx_pm_syscore_ops);
-
- return 0;
-}
-#else
-static int __init cmx2xx_pm_init(void) { return 0; }
-#endif
-
-#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
-static void __init cmx2xx_init_ac97(void)
-{
- pxa_set_ac97_info(NULL);
-}
-#else
-static inline void cmx2xx_init_ac97(void) {}
-#endif
-
-static void __init cmx2xx_init(void)
-{
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
- cmx2xx_pm_init();
-
- if (cpu_is_pxa25x())
- cmx255_init();
- else
- cmx270_init();
-
- cmx2xx_init_dm9000();
- cmx2xx_init_display();
- cmx2xx_init_ac97();
- cmx2xx_init_touchscreen();
- cmx2xx_init_leds();
-
- regulator_has_full_constraints();
-}
-
-static void __init cmx2xx_init_irq(void)
-{
- if (cpu_is_pxa25x()) {
- pxa25x_init_irq();
- cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ);
- } else {
- pxa27x_init_irq();
- cmx2xx_pci_init_irq(CMX270_GPIO_IT8152_IRQ);
- }
-}
-
-#ifdef CONFIG_PCI
-/* Map PCI companion statically */
-static struct map_desc cmx2xx_io_desc[] __initdata = {
- [0] = { /* PCI bridge */
- .virtual = (unsigned long)CMX2XX_IT8152_VIRT,
- .pfn = __phys_to_pfn(PXA_CS4_PHYS),
- .length = SZ_64M,
- .type = MT_DEVICE
- },
-};
-
-static void __init cmx2xx_map_io(void)
-{
- if (cpu_is_pxa25x())
- pxa25x_map_io();
-
- if (cpu_is_pxa27x())
- pxa27x_map_io();
-
- iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc));
-
- it8152_base_address = CMX2XX_IT8152_VIRT;
-}
-#else
-static void __init cmx2xx_map_io(void)
-{
- if (cpu_is_pxa25x())
- pxa25x_map_io();
-
- if (cpu_is_pxa27x())
- pxa27x_map_io();
-}
-#endif
-
-MACHINE_START(ARMCORE, "Compulab CM-X2XX")
- .atag_offset = 0x100,
- .map_io = cmx2xx_map_io,
- .nr_irqs = CMX2XX_NR_IRQS,
- .init_irq = cmx2xx_init_irq,
- /* NOTE: pxa25x_handle_irq() works on PXA27x w/o camera support */
- .handle_irq = pxa25x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = cmx2xx_init,
-#ifdef CONFIG_PCI
- .dma_zone_size = SZ_64M,
-#endif
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 425855f..2e35354 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -312,7 +312,6 @@
static struct platform_pwm_backlight_data cm_x300_backlight_data = {
.max_brightness = 100,
.dft_brightness = 100,
- .enable_gpio = -1,
};
static struct platform_device cm_x300_backlight_device = {
diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c
index dbad2f1..e5879e8 100644
--- a/arch/arm/mach-pxa/colibri-pxa270-income.c
+++ b/arch/arm/mach-pxa/colibri-pxa270-income.c
@@ -202,7 +202,6 @@
static struct platform_pwm_backlight_data income_backlight_data = {
.max_brightness = 0x3ff,
.dft_brightness = 0x1ff,
- .enable_gpio = -1,
};
static struct platform_device income_backlight = {
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index eba917d..35dd3ad 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -11,9 +11,9 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
+#include <linux/gpio/machine.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
-#include <linux/usb/gpio_vbus.h>
#include <asm/mach-types.h>
#include <linux/sizes.h>
@@ -144,17 +144,18 @@
#endif /* CONFIG_AX88796 */
#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
-static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = {
- .gpio_vbus = mfp_to_gpio(MFP_PIN_GPIO96),
- .gpio_pullup = -1,
+static struct gpiod_lookup_table gpio_vbus_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", MFP_PIN_GPIO96,
+ "vbus", GPIO_ACTIVE_HIGH),
+ { },
+ },
};
static struct platform_device colibri_pxa320_gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
- .dev = {
- .platform_data = &colibri_pxa320_gpio_vbus_info,
- },
};
static void colibri_pxa320_udc_command(int cmd)
@@ -173,6 +174,7 @@
static void __init colibri_pxa320_init_udc(void)
{
pxa_set_udc_info(&colibri_pxa320_udc_info);
+ gpiod_add_lookup_table(&gpio_vbus_gpiod_table);
platform_device_register(&colibri_pxa320_gpio_vbus);
}
#else
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index f2d7328..593c7f7 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -563,13 +563,20 @@
}
}
+static struct gpiod_lookup_table corgi_lcdcon_gpio_table = {
+ .dev_id = "spi1.1",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", CORGI_GPIO_BACKLIGHT_CONT,
+ "BL_CONT", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static struct corgi_lcd_platform_data corgi_lcdcon_info = {
.init_mode = CORGI_LCD_MODE_VGA,
.max_intensity = 0x2f,
.default_intensity = 0x1f,
.limit_mask = 0x0b,
- .gpio_backlight_cont = CORGI_GPIO_BACKLIGHT_CONT,
- .gpio_backlight_on = -1,
.kick_battery = corgi_bl_kick_battery,
};
@@ -609,6 +616,7 @@
static void __init corgi_init_spi(void)
{
pxa2xx_set_spi_info(1, &corgi_spi_info);
+ gpiod_add_lookup_table(&corgi_lcdcon_gpio_table);
spi_register_board_info(ARRAY_AND_SIZE(corgi_spi_devices));
}
#else
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
deleted file mode 100644
index d8681a3..0000000
--- a/arch/arm/mach-pxa/em-x270.c
+++ /dev/null
@@ -1,1286 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Support for CompuLab EM-X270 platform
- *
- * Copyright (C) 2007, 2008 CompuLab, Ltd.
- * Author: Mike Rapoport <mike@compulab.co.il>
- */
-
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-
-#include <linux/dm9000.h>
-#include <linux/platform_data/rtc-v3020.h>
-#include <linux/mtd/platnand.h>
-#include <linux/mtd/physmap.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/gpio/machine.h>
-#include <linux/mfd/da903x.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/tdo24m.h>
-#include <linux/spi/libertas_spi.h>
-#include <linux/spi/pxa2xx_spi.h>
-#include <linux/power_supply.h>
-#include <linux/apm-emulation.h>
-#include <linux/i2c.h>
-#include <linux/platform_data/pca953x.h>
-#include <linux/platform_data/i2c-pxa.h>
-#include <linux/regulator/userspace-consumer.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include "pxa27x.h"
-#include "pxa27x-udc.h"
-#include <mach/audio.h>
-#include <linux/platform_data/video-pxafb.h>
-#include <linux/platform_data/usb-ohci-pxa27x.h>
-#include <linux/platform_data/mmc-pxamci.h>
-#include <linux/platform_data/keypad-pxa27x.h>
-#include <linux/platform_data/media/camera-pxa.h>
-
-#include "generic.h"
-#include "devices.h"
-
-/* EM-X270 specific GPIOs */
-#define GPIO13_MMC_CD (13)
-#define GPIO95_MMC_WP (95)
-#define GPIO56_NAND_RB (56)
-#define GPIO93_CAM_RESET (93)
-#define GPIO16_USB_HUB_RESET (16)
-
-/* eXeda specific GPIOs */
-#define GPIO114_MMC_CD (114)
-#define GPIO20_NAND_RB (20)
-#define GPIO38_SD_PWEN (38)
-#define GPIO37_WLAN_RST (37)
-#define GPIO95_TOUCHPAD_INT (95)
-#define GPIO130_CAM_RESET (130)
-#define GPIO10_USB_HUB_RESET (10)
-
-/* common GPIOs */
-#define GPIO11_NAND_CS (11)
-#define GPIO41_ETHIRQ (41)
-#define EM_X270_ETHIRQ PXA_GPIO_TO_IRQ(GPIO41_ETHIRQ)
-#define GPIO115_WLAN_PWEN (115)
-#define GPIO19_WLAN_STRAP (19)
-#define GPIO9_USB_VBUS_EN (9)
-
-static int mmc_cd;
-static int nand_rb;
-static int dm9000_flags;
-static int cam_reset;
-static int usb_hub_reset;
-
-static unsigned long common_pin_config[] = {
- /* AC'97 */
- GPIO28_AC97_BITCLK,
- GPIO29_AC97_SDATA_IN_0,
- GPIO30_AC97_SDATA_OUT,
- GPIO31_AC97_SYNC,
- GPIO98_AC97_SYSCLK,
- GPIO113_AC97_nRESET,
-
- /* BTUART */
- GPIO42_BTUART_RXD,
- GPIO43_BTUART_TXD,
- GPIO44_BTUART_CTS,
- GPIO45_BTUART_RTS,
-
- /* STUART */
- GPIO46_STUART_RXD,
- GPIO47_STUART_TXD,
-
- /* MCI controller */
- GPIO32_MMC_CLK,
- GPIO112_MMC_CMD,
- GPIO92_MMC_DAT_0,
- GPIO109_MMC_DAT_1,
- GPIO110_MMC_DAT_2,
- GPIO111_MMC_DAT_3,
-
- /* LCD */
- GPIOxx_LCD_TFT_16BPP,
-
- /* QCI */
- GPIO84_CIF_FV,
- GPIO25_CIF_LV,
- GPIO53_CIF_MCLK,
- GPIO54_CIF_PCLK,
- GPIO81_CIF_DD_0,
- GPIO55_CIF_DD_1,
- GPIO51_CIF_DD_2,
- GPIO50_CIF_DD_3,
- GPIO52_CIF_DD_4,
- GPIO48_CIF_DD_5,
- GPIO17_CIF_DD_6,
- GPIO12_CIF_DD_7,
-
- /* I2C */
- GPIO117_I2C_SCL,
- GPIO118_I2C_SDA,
-
- /* Keypad */
- GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
- GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
- GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
- GPIO34_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
- GPIO39_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
- GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
- GPIO91_KP_MKIN_6 | WAKEUP_ON_LEVEL_HIGH,
- GPIO36_KP_MKIN_7 | WAKEUP_ON_LEVEL_HIGH,
- GPIO103_KP_MKOUT_0,
- GPIO104_KP_MKOUT_1,
- GPIO105_KP_MKOUT_2,
- GPIO106_KP_MKOUT_3,
- GPIO107_KP_MKOUT_4,
- GPIO108_KP_MKOUT_5,
- GPIO96_KP_MKOUT_6,
- GPIO22_KP_MKOUT_7,
-
- /* SSP1 */
- GPIO26_SSP1_RXD,
- GPIO23_SSP1_SCLK,
- GPIO24_SSP1_SFRM,
- GPIO57_SSP1_TXD,
-
- /* SSP2 */
- GPIO19_GPIO, /* SSP2 clock is used as GPIO for Libertas pin-strap */
- GPIO14_GPIO,
- GPIO89_SSP2_TXD,
- GPIO88_SSP2_RXD,
-
- /* SDRAM and local bus */
- GPIO15_nCS_1,
- GPIO78_nCS_2,
- GPIO79_nCS_3,
- GPIO80_nCS_4,
- GPIO49_nPWE,
- GPIO18_RDY,
-
- /* GPIO */
- GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* sleep/resume button */
-
- /* power controls */
- GPIO20_GPIO | MFP_LPM_DRIVE_LOW, /* GPRS_PWEN */
- GPIO115_GPIO | MFP_LPM_DRIVE_LOW, /* WLAN_PWEN */
-
- /* NAND controls */
- GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
-
- /* interrupts */
- GPIO41_GPIO, /* DM9000 interrupt */
-};
-
-static unsigned long em_x270_pin_config[] = {
- GPIO13_GPIO, /* MMC card detect */
- GPIO16_GPIO, /* USB hub reset */
- GPIO56_GPIO, /* NAND Ready/Busy */
- GPIO93_GPIO | MFP_LPM_DRIVE_LOW, /* Camera reset */
- GPIO95_GPIO, /* MMC Write protect */
-};
-
-static unsigned long exeda_pin_config[] = {
- GPIO10_GPIO, /* USB hub reset */
- GPIO20_GPIO, /* NAND Ready/Busy */
- GPIO38_GPIO | MFP_LPM_DRIVE_LOW, /* SD slot power */
- GPIO95_GPIO, /* touchpad IRQ */
- GPIO114_GPIO, /* MMC card detect */
-};
-
-#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
-static struct resource em_x270_dm9000_resource[] = {
- [0] = {
- .start = PXA_CS2_PHYS,
- .end = PXA_CS2_PHYS + 3,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = PXA_CS2_PHYS + 8,
- .end = PXA_CS2_PHYS + 8 + 0x3f,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = EM_X270_ETHIRQ,
- .end = EM_X270_ETHIRQ,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- }
-};
-
-static struct dm9000_plat_data em_x270_dm9000_platdata = {
- .flags = DM9000_PLATF_NO_EEPROM,
-};
-
-static struct platform_device em_x270_dm9000 = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(em_x270_dm9000_resource),
- .resource = em_x270_dm9000_resource,
- .dev = {
- .platform_data = &em_x270_dm9000_platdata,
- }
-};
-
-static void __init em_x270_init_dm9000(void)
-{
- em_x270_dm9000_platdata.flags |= dm9000_flags;
- platform_device_register(&em_x270_dm9000);
-}
-#else
-static inline void em_x270_init_dm9000(void) {}
-#endif
-
-/* V3020 RTC */
-#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
-static struct resource em_x270_v3020_resource[] = {
- [0] = {
- .start = PXA_CS4_PHYS,
- .end = PXA_CS4_PHYS + 3,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct v3020_platform_data em_x270_v3020_platdata = {
- .leftshift = 0,
-};
-
-static struct platform_device em_x270_rtc = {
- .name = "v3020",
- .num_resources = ARRAY_SIZE(em_x270_v3020_resource),
- .resource = em_x270_v3020_resource,
- .id = -1,
- .dev = {
- .platform_data = &em_x270_v3020_platdata,
- }
-};
-
-static void __init em_x270_init_rtc(void)
-{
- platform_device_register(&em_x270_rtc);
-}
-#else
-static inline void em_x270_init_rtc(void) {}
-#endif
-
-/* NAND flash */
-#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
-static inline void nand_cs_on(void)
-{
- gpio_set_value(GPIO11_NAND_CS, 0);
-}
-
-static void nand_cs_off(void)
-{
- dsb();
-
- gpio_set_value(GPIO11_NAND_CS, 1);
-}
-
-/* hardware specific access to control-lines */
-static void em_x270_nand_cmd_ctl(struct nand_chip *this, int dat,
- unsigned int ctrl)
-{
- unsigned long nandaddr = (unsigned long)this->legacy.IO_ADDR_W;
-
- dsb();
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if (ctrl & NAND_ALE)
- nandaddr |= (1 << 3);
- else
- nandaddr &= ~(1 << 3);
- if (ctrl & NAND_CLE)
- nandaddr |= (1 << 2);
- else
- nandaddr &= ~(1 << 2);
- if (ctrl & NAND_NCE)
- nand_cs_on();
- else
- nand_cs_off();
- }
-
- dsb();
- this->legacy.IO_ADDR_W = (void __iomem *)nandaddr;
- if (dat != NAND_CMD_NONE)
- writel(dat, this->legacy.IO_ADDR_W);
-
- dsb();
-}
-
-/* read device ready pin */
-static int em_x270_nand_device_ready(struct nand_chip *this)
-{
- dsb();
-
- return gpio_get_value(nand_rb);
-}
-
-static struct mtd_partition em_x270_partition_info[] = {
- [0] = {
- .name = "em_x270-0",
- .offset = 0,
- .size = SZ_4M,
- },
- [1] = {
- .name = "em_x270-1",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL
- },
-};
-
-struct platform_nand_data em_x270_nand_platdata = {
- .chip = {
- .nr_chips = 1,
- .chip_offset = 0,
- .nr_partitions = ARRAY_SIZE(em_x270_partition_info),
- .partitions = em_x270_partition_info,
- .chip_delay = 20,
- },
- .ctrl = {
- .dev_ready = em_x270_nand_device_ready,
- .select_chip = 0,
- .cmd_ctrl = em_x270_nand_cmd_ctl,
- },
-};
-
-static struct resource em_x270_nand_resource[] = {
- [0] = {
- .start = PXA_CS1_PHYS,
- .end = PXA_CS1_PHYS + 12,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device em_x270_nand = {
- .name = "gen_nand",
- .num_resources = ARRAY_SIZE(em_x270_nand_resource),
- .resource = em_x270_nand_resource,
- .id = -1,
- .dev = {
- .platform_data = &em_x270_nand_platdata,
- }
-};
-
-static void __init em_x270_init_nand(void)
-{
- int err;
-
- err = gpio_request(GPIO11_NAND_CS, "NAND CS");
- if (err) {
- pr_warn("EM-X270: failed to request NAND CS gpio\n");
- return;
- }
-
- gpio_direction_output(GPIO11_NAND_CS, 1);
-
- err = gpio_request(nand_rb, "NAND R/B");
- if (err) {
- pr_warn("EM-X270: failed to request NAND R/B gpio\n");
- gpio_free(GPIO11_NAND_CS);
- return;
- }
-
- gpio_direction_input(nand_rb);
-
- platform_device_register(&em_x270_nand);
-}
-#else
-static inline void em_x270_init_nand(void) {}
-#endif
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static struct mtd_partition em_x270_nor_parts[] = {
- {
- .name = "Bootloader",
- .offset = 0x00000000,
- .size = 0x00050000,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- }, {
- .name = "Environment",
- .offset = 0x00050000,
- .size = 0x00010000,
- }, {
- .name = "Reserved",
- .offset = 0x00060000,
- .size = 0x00050000,
- .mask_flags = MTD_WRITEABLE /* force read-only */
- }, {
- .name = "Splashscreen",
- .offset = 0x000b0000,
- .size = 0x00050000,
- }
-};
-
-static struct physmap_flash_data em_x270_nor_data[] = {
- [0] = {
- .width = 2,
- .parts = em_x270_nor_parts,
- .nr_parts = ARRAY_SIZE(em_x270_nor_parts),
- },
-};
-
-static struct resource em_x270_nor_flash_resource = {
- .start = PXA_CS0_PHYS,
- .end = PXA_CS0_PHYS + SZ_1M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device em_x270_physmap_flash = {
- .name = "physmap-flash",
- .id = 0,
- .num_resources = 1,
- .resource = &em_x270_nor_flash_resource,
- .dev = {
- .platform_data = &em_x270_nor_data,
- },
-};
-
-static void __init em_x270_init_nor(void)
-{
- platform_device_register(&em_x270_physmap_flash);
-}
-#else
-static inline void em_x270_init_nor(void) {}
-#endif
-
-/* PXA27x OHCI controller setup */
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static struct regulator *em_x270_usb_ldo;
-
-static int em_x270_usb_hub_init(void)
-{
- int err;
-
- em_x270_usb_ldo = regulator_get(NULL, "vcc usb");
- if (IS_ERR(em_x270_usb_ldo))
- return PTR_ERR(em_x270_usb_ldo);
-
- err = gpio_request(GPIO9_USB_VBUS_EN, "vbus en");
- if (err)
- goto err_free_usb_ldo;
-
- err = gpio_request(usb_hub_reset, "hub rst");
- if (err)
- goto err_free_vbus_gpio;
-
- /* USB Hub power-on and reset */
- gpio_direction_output(usb_hub_reset, 1);
- gpio_direction_output(GPIO9_USB_VBUS_EN, 0);
- err = regulator_enable(em_x270_usb_ldo);
- if (err)
- goto err_free_rst_gpio;
-
- gpio_set_value(usb_hub_reset, 0);
- gpio_set_value(usb_hub_reset, 1);
- regulator_disable(em_x270_usb_ldo);
- err = regulator_enable(em_x270_usb_ldo);
- if (err)
- goto err_free_rst_gpio;
-
- gpio_set_value(usb_hub_reset, 0);
- gpio_set_value(GPIO9_USB_VBUS_EN, 1);
-
- return 0;
-
-err_free_rst_gpio:
- gpio_free(usb_hub_reset);
-err_free_vbus_gpio:
- gpio_free(GPIO9_USB_VBUS_EN);
-err_free_usb_ldo:
- regulator_put(em_x270_usb_ldo);
-
- return err;
-}
-
-static int em_x270_ohci_init(struct device *dev)
-{
- int err;
-
- /* we don't want to entirely disable USB if the HUB init failed */
- err = em_x270_usb_hub_init();
- if (err)
- pr_err("USB Hub initialization failed: %d\n", err);
-
- /* enable port 2 transiever */
- UP2OCR = UP2OCR_HXS | UP2OCR_HXOE;
-
- return 0;
-}
-
-static void em_x270_ohci_exit(struct device *dev)
-{
- gpio_free(usb_hub_reset);
- gpio_free(GPIO9_USB_VBUS_EN);
-
- if (!IS_ERR(em_x270_usb_ldo)) {
- if (regulator_is_enabled(em_x270_usb_ldo))
- regulator_disable(em_x270_usb_ldo);
-
- regulator_put(em_x270_usb_ldo);
- }
-}
-
-static struct pxaohci_platform_data em_x270_ohci_platform_data = {
- .port_mode = PMM_PERPORT_MODE,
- .flags = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW,
- .init = em_x270_ohci_init,
- .exit = em_x270_ohci_exit,
-};
-
-static void __init em_x270_init_ohci(void)
-{
- pxa_set_ohci_info(&em_x270_ohci_platform_data);
-}
-#else
-static inline void em_x270_init_ohci(void) {}
-#endif
-
-/* MCI controller setup */
-#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
-static struct regulator *em_x270_sdio_ldo;
-
-static struct gpiod_lookup_table em_x270_mci_wp_gpio_table = {
- .dev_id = "pxa2xx-mci.0",
- .table = {
- /* Write protect on GPIO 95 */
- GPIO_LOOKUP("gpio-pxa", GPIO95_MMC_WP, "wp", GPIO_ACTIVE_LOW),
- { },
- },
-};
-
-static int em_x270_mci_init(struct device *dev,
- irq_handler_t em_x270_detect_int,
- void *data)
-{
- int err;
-
- em_x270_sdio_ldo = regulator_get(dev, "vcc sdio");
- if (IS_ERR(em_x270_sdio_ldo)) {
- dev_err(dev, "can't request SDIO power supply: %ld\n",
- PTR_ERR(em_x270_sdio_ldo));
- return PTR_ERR(em_x270_sdio_ldo);
- }
-
- err = request_irq(gpio_to_irq(mmc_cd), em_x270_detect_int,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "MMC card detect", data);
- if (err) {
- dev_err(dev, "can't request MMC card detect IRQ: %d\n", err);
- goto err_irq;
- }
-
- if (!machine_is_em_x270()) {
- err = gpio_request(GPIO38_SD_PWEN, "sdio power");
- if (err) {
- dev_err(dev, "can't request MMC power control : %d\n",
- err);
- goto err_gpio_wp;
- }
- gpio_direction_output(GPIO38_SD_PWEN, 1);
- }
-
- return 0;
-
-err_gpio_wp:
- free_irq(gpio_to_irq(mmc_cd), data);
-err_irq:
- regulator_put(em_x270_sdio_ldo);
-
- return err;
-}
-
-static int em_x270_mci_setpower(struct device *dev, unsigned int vdd)
-{
- struct pxamci_platform_data* p_d = dev->platform_data;
-
- if ((1 << vdd) & p_d->ocr_mask) {
- int vdd_uV = (2000 + (vdd - __ffs(MMC_VDD_20_21)) * 100) * 1000;
-
- regulator_set_voltage(em_x270_sdio_ldo, vdd_uV, vdd_uV);
- return regulator_enable(em_x270_sdio_ldo);
- } else {
- regulator_disable(em_x270_sdio_ldo);
- }
- return 0;
-}
-
-static void em_x270_mci_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(mmc_cd), data);
- regulator_put(em_x270_sdio_ldo);
-
- if (!machine_is_em_x270())
- gpio_free(GPIO38_SD_PWEN);
-}
-
-static struct pxamci_platform_data em_x270_mci_platform_data = {
- .detect_delay_ms = 250,
- .ocr_mask = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23|
- MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27|
- MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
- MMC_VDD_30_31|MMC_VDD_31_32,
- .init = em_x270_mci_init,
- .setpower = em_x270_mci_setpower,
- .exit = em_x270_mci_exit,
-};
-
-static void __init em_x270_init_mmc(void)
-{
- if (machine_is_em_x270())
- gpiod_add_lookup_table(&em_x270_mci_wp_gpio_table);
-
- pxa_set_mci_info(&em_x270_mci_platform_data);
-}
-#else
-static inline void em_x270_init_mmc(void) {}
-#endif
-
-/* LCD */
-#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
-static struct pxafb_mode_info em_x270_lcd_modes[] = {
- [0] = {
- .pixclock = 38250,
- .bpp = 16,
- .xres = 480,
- .yres = 640,
- .hsync_len = 8,
- .vsync_len = 2,
- .left_margin = 8,
- .upper_margin = 2,
- .right_margin = 24,
- .lower_margin = 4,
- .sync = 0,
- },
- [1] = {
- .pixclock = 153800,
- .bpp = 16,
- .xres = 240,
- .yres = 320,
- .hsync_len = 8,
- .vsync_len = 2,
- .left_margin = 8,
- .upper_margin = 2,
- .right_margin = 88,
- .lower_margin = 2,
- .sync = 0,
- },
-};
-
-static struct pxafb_mach_info em_x270_lcd = {
- .modes = em_x270_lcd_modes,
- .num_modes = 2,
- .lcd_conn = LCD_COLOR_TFT_16BPP,
-};
-
-static void __init em_x270_init_lcd(void)
-{
- pxa_set_fb_info(NULL, &em_x270_lcd);
-}
-#else
-static inline void em_x270_init_lcd(void) {}
-#endif
-
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_controller em_x270_spi_info = {
- .num_chipselect = 1,
-};
-
-static struct pxa2xx_spi_chip em_x270_tdo24m_chip = {
- .rx_threshold = 1,
- .tx_threshold = 1,
- .gpio_cs = -1,
-};
-
-static struct tdo24m_platform_data em_x270_tdo24m_pdata = {
- .model = TDO35S,
-};
-
-static struct pxa2xx_spi_controller em_x270_spi_2_info = {
- .num_chipselect = 1,
- .enable_dma = 1,
-};
-
-static struct pxa2xx_spi_chip em_x270_libertas_chip = {
- .rx_threshold = 1,
- .tx_threshold = 1,
- .timeout = 1000,
- .gpio_cs = 14,
-};
-
-static unsigned long em_x270_libertas_pin_config[] = {
- /* SSP2 */
- GPIO19_SSP2_SCLK,
- GPIO14_GPIO,
- GPIO89_SSP2_TXD,
- GPIO88_SSP2_RXD,
-};
-
-static int em_x270_libertas_setup(struct spi_device *spi)
-{
- int err = gpio_request(GPIO115_WLAN_PWEN, "WLAN PWEN");
- if (err)
- return err;
-
- err = gpio_request(GPIO19_WLAN_STRAP, "WLAN STRAP");
- if (err)
- goto err_free_pwen;
-
- if (machine_is_exeda()) {
- err = gpio_request(GPIO37_WLAN_RST, "WLAN RST");
- if (err)
- goto err_free_strap;
-
- gpio_direction_output(GPIO37_WLAN_RST, 1);
- msleep(100);
- }
-
- gpio_direction_output(GPIO19_WLAN_STRAP, 1);
- msleep(100);
-
- pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_libertas_pin_config));
-
- gpio_direction_output(GPIO115_WLAN_PWEN, 0);
- msleep(100);
- gpio_set_value(GPIO115_WLAN_PWEN, 1);
- msleep(100);
-
- spi->bits_per_word = 16;
- spi_setup(spi);
-
- return 0;
-
-err_free_strap:
- gpio_free(GPIO19_WLAN_STRAP);
-err_free_pwen:
- gpio_free(GPIO115_WLAN_PWEN);
-
- return err;
-}
-
-static int em_x270_libertas_teardown(struct spi_device *spi)
-{
- gpio_set_value(GPIO115_WLAN_PWEN, 0);
- gpio_free(GPIO115_WLAN_PWEN);
- gpio_free(GPIO19_WLAN_STRAP);
-
- if (machine_is_exeda()) {
- gpio_set_value(GPIO37_WLAN_RST, 0);
- gpio_free(GPIO37_WLAN_RST);
- }
-
- return 0;
-}
-
-struct libertas_spi_platform_data em_x270_libertas_pdata = {
- .use_dummy_writes = 1,
- .setup = em_x270_libertas_setup,
- .teardown = em_x270_libertas_teardown,
-};
-
-static struct spi_board_info em_x270_spi_devices[] __initdata = {
- {
- .modalias = "tdo24m",
- .max_speed_hz = 1000000,
- .bus_num = 1,
- .chip_select = 0,
- .controller_data = &em_x270_tdo24m_chip,
- .platform_data = &em_x270_tdo24m_pdata,
- },
- {
- .modalias = "libertas_spi",
- .max_speed_hz = 13000000,
- .bus_num = 2,
- .irq = PXA_GPIO_TO_IRQ(116),
- .chip_select = 0,
- .controller_data = &em_x270_libertas_chip,
- .platform_data = &em_x270_libertas_pdata,
- },
-};
-
-static void __init em_x270_init_spi(void)
-{
- pxa2xx_set_spi_info(1, &em_x270_spi_info);
- pxa2xx_set_spi_info(2, &em_x270_spi_2_info);
- spi_register_board_info(ARRAY_AND_SIZE(em_x270_spi_devices));
-}
-#else
-static inline void em_x270_init_spi(void) {}
-#endif
-
-#if defined(CONFIG_SND_PXA2XX_LIB_AC97)
-static pxa2xx_audio_ops_t em_x270_ac97_info = {
- .reset_gpio = 113,
-};
-
-static void __init em_x270_init_ac97(void)
-{
- pxa_set_ac97_info(&em_x270_ac97_info);
-}
-#else
-static inline void em_x270_init_ac97(void) {}
-#endif
-
-#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static const unsigned int em_x270_module_matrix_keys[] = {
- KEY(0, 0, KEY_A), KEY(1, 0, KEY_UP), KEY(2, 1, KEY_B),
- KEY(0, 2, KEY_LEFT), KEY(1, 1, KEY_ENTER), KEY(2, 0, KEY_RIGHT),
- KEY(0, 1, KEY_C), KEY(1, 2, KEY_DOWN), KEY(2, 2, KEY_D),
-};
-
-static struct matrix_keymap_data em_x270_matrix_keymap_data = {
- .keymap = em_x270_module_matrix_keys,
- .keymap_size = ARRAY_SIZE(em_x270_module_matrix_keys),
-};
-
-struct pxa27x_keypad_platform_data em_x270_module_keypad_info = {
- /* code map for the matrix keys */
- .matrix_key_rows = 3,
- .matrix_key_cols = 3,
- .matrix_keymap_data = &em_x270_matrix_keymap_data,
-};
-
-static const unsigned int em_x270_exeda_matrix_keys[] = {
- KEY(0, 0, KEY_RIGHTSHIFT), KEY(0, 1, KEY_RIGHTCTRL),
- KEY(0, 2, KEY_RIGHTALT), KEY(0, 3, KEY_SPACE),
- KEY(0, 4, KEY_LEFTALT), KEY(0, 5, KEY_LEFTCTRL),
- KEY(0, 6, KEY_ENTER), KEY(0, 7, KEY_SLASH),
-
- KEY(1, 0, KEY_DOT), KEY(1, 1, KEY_M),
- KEY(1, 2, KEY_N), KEY(1, 3, KEY_B),
- KEY(1, 4, KEY_V), KEY(1, 5, KEY_C),
- KEY(1, 6, KEY_X), KEY(1, 7, KEY_Z),
-
- KEY(2, 0, KEY_LEFTSHIFT), KEY(2, 1, KEY_SEMICOLON),
- KEY(2, 2, KEY_L), KEY(2, 3, KEY_K),
- KEY(2, 4, KEY_J), KEY(2, 5, KEY_H),
- KEY(2, 6, KEY_G), KEY(2, 7, KEY_F),
-
- KEY(3, 0, KEY_D), KEY(3, 1, KEY_S),
- KEY(3, 2, KEY_A), KEY(3, 3, KEY_TAB),
- KEY(3, 4, KEY_BACKSPACE), KEY(3, 5, KEY_P),
- KEY(3, 6, KEY_O), KEY(3, 7, KEY_I),
-
- KEY(4, 0, KEY_U), KEY(4, 1, KEY_Y),
- KEY(4, 2, KEY_T), KEY(4, 3, KEY_R),
- KEY(4, 4, KEY_E), KEY(4, 5, KEY_W),
- KEY(4, 6, KEY_Q), KEY(4, 7, KEY_MINUS),
-
- KEY(5, 0, KEY_0), KEY(5, 1, KEY_9),
- KEY(5, 2, KEY_8), KEY(5, 3, KEY_7),
- KEY(5, 4, KEY_6), KEY(5, 5, KEY_5),
- KEY(5, 6, KEY_4), KEY(5, 7, KEY_3),
-
- KEY(6, 0, KEY_2), KEY(6, 1, KEY_1),
- KEY(6, 2, KEY_ENTER), KEY(6, 3, KEY_END),
- KEY(6, 4, KEY_DOWN), KEY(6, 5, KEY_UP),
- KEY(6, 6, KEY_MENU), KEY(6, 7, KEY_F1),
-
- KEY(7, 0, KEY_LEFT), KEY(7, 1, KEY_RIGHT),
- KEY(7, 2, KEY_BACK), KEY(7, 3, KEY_HOME),
- KEY(7, 4, 0), KEY(7, 5, 0),
- KEY(7, 6, 0), KEY(7, 7, 0),
-};
-
-static struct matrix_keymap_data em_x270_exeda_matrix_keymap_data = {
- .keymap = em_x270_exeda_matrix_keys,
- .keymap_size = ARRAY_SIZE(em_x270_exeda_matrix_keys),
-};
-
-struct pxa27x_keypad_platform_data em_x270_exeda_keypad_info = {
- /* code map for the matrix keys */
- .matrix_key_rows = 8,
- .matrix_key_cols = 8,
- .matrix_keymap_data = &em_x270_exeda_matrix_keymap_data,
-};
-
-static void __init em_x270_init_keypad(void)
-{
- if (machine_is_em_x270())
- pxa_set_keypad_info(&em_x270_module_keypad_info);
- else
- pxa_set_keypad_info(&em_x270_exeda_keypad_info);
-}
-#else
-static inline void em_x270_init_keypad(void) {}
-#endif
-
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button gpio_keys_button[] = {
- [0] = {
- .desc = "sleep/wakeup",
- .code = KEY_SUSPEND,
- .type = EV_PWR,
- .gpio = 1,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data em_x270_gpio_keys_data = {
- .buttons = gpio_keys_button,
- .nbuttons = 1,
-};
-
-static struct platform_device em_x270_gpio_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &em_x270_gpio_keys_data,
- },
-};
-
-static void __init em_x270_init_gpio_keys(void)
-{
- platform_device_register(&em_x270_gpio_keys);
-}
-#else
-static inline void em_x270_init_gpio_keys(void) {}
-#endif
-
-/* Quick Capture Interface and sensor setup */
-#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
-static int em_x270_sensor_init(void)
-{
- int ret;
-
- ret = gpio_request(cam_reset, "camera reset");
- if (ret)
- return ret;
-
- gpio_direction_output(cam_reset, 0);
- gpio_set_value(cam_reset, 1);
-
- return 0;
-}
-
-static struct regulator_consumer_supply camera_dummy_supplies[] = {
- REGULATOR_SUPPLY("vdd", "0-005d"),
-};
-
-static struct regulator_init_data camera_dummy_initdata = {
- .consumer_supplies = camera_dummy_supplies,
- .num_consumer_supplies = ARRAY_SIZE(camera_dummy_supplies),
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct fixed_voltage_config camera_dummy_config = {
- .supply_name = "camera_vdd",
- .input_supply = "vcc cam",
- .microvolts = 2800000,
- .init_data = &camera_dummy_initdata,
-};
-
-static struct platform_device camera_supply_dummy_device = {
- .name = "reg-fixed-voltage",
- .id = 1,
- .dev = {
- .platform_data = &camera_dummy_config,
- },
-};
-
-struct pxacamera_platform_data em_x270_camera_platform_data = {
- .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
- PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
- .mclk_10khz = 2600,
- .sensor_i2c_adapter_id = 0,
- .sensor_i2c_address = 0x5d,
-};
-
-static void __init em_x270_init_camera(void)
-{
- if (em_x270_sensor_init() == 0)
- pxa_set_camera_info(&em_x270_camera_platform_data);
- platform_device_register(&camera_supply_dummy_device);
-}
-#else
-static inline void em_x270_init_camera(void) {}
-#endif
-
-static struct regulator_bulk_data em_x270_gps_consumer_supply = {
- .supply = "vcc gps",
-};
-
-static struct regulator_userspace_consumer_data em_x270_gps_consumer_data = {
- .name = "vcc gps",
- .num_supplies = 1,
- .supplies = &em_x270_gps_consumer_supply,
-};
-
-static struct platform_device em_x270_gps_userspace_consumer = {
- .name = "reg-userspace-consumer",
- .id = 0,
- .dev = {
- .platform_data = &em_x270_gps_consumer_data,
- },
-};
-
-static struct regulator_bulk_data em_x270_gprs_consumer_supply = {
- .supply = "vcc gprs",
-};
-
-static struct regulator_userspace_consumer_data em_x270_gprs_consumer_data = {
- .name = "vcc gprs",
- .num_supplies = 1,
- .supplies = &em_x270_gprs_consumer_supply
-};
-
-static struct platform_device em_x270_gprs_userspace_consumer = {
- .name = "reg-userspace-consumer",
- .id = 1,
- .dev = {
- .platform_data = &em_x270_gprs_consumer_data,
- }
-};
-
-static struct platform_device *em_x270_userspace_consumers[] = {
- &em_x270_gps_userspace_consumer,
- &em_x270_gprs_userspace_consumer,
-};
-
-static void __init em_x270_userspace_consumers_init(void)
-{
- platform_add_devices(ARRAY_AND_SIZE(em_x270_userspace_consumers));
-}
-
-/* DA9030 related initializations */
-#define REGULATOR_CONSUMER(_name, _dev_name, _supply) \
- static struct regulator_consumer_supply _name##_consumers[] = { \
- REGULATOR_SUPPLY(_supply, _dev_name), \
- }
-
-REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer.0", "vcc gps");
-REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
-REGULATOR_CONSUMER(ldo10, "pxa2xx-mci", "vcc sdio");
-REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
-REGULATOR_CONSUMER(ldo19, "reg-userspace-consumer.1", "vcc gprs");
-REGULATOR_CONSUMER(buck2, NULL, "vcc_core");
-
-#define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \
- static struct regulator_init_data _ldo##_data = { \
- .constraints = { \
- .min_uV = _min_uV, \
- .max_uV = _max_uV, \
- .state_mem = { \
- .enabled = 0, \
- }, \
- .valid_ops_mask = _ops_mask, \
- .apply_uV = 1, \
- }, \
- .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \
- .consumer_supplies = _ldo##_consumers, \
- };
-
-REGULATOR_INIT(ldo3, 3200000, 3200000, REGULATOR_CHANGE_STATUS);
-REGULATOR_INIT(ldo5, 3000000, 3000000, REGULATOR_CHANGE_STATUS);
-REGULATOR_INIT(ldo10, 2000000, 3200000,
- REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE);
-REGULATOR_INIT(ldo12, 3000000, 3000000, REGULATOR_CHANGE_STATUS);
-REGULATOR_INIT(ldo19, 3200000, 3200000, REGULATOR_CHANGE_STATUS);
-REGULATOR_INIT(buck2, 1000000, 1650000, REGULATOR_CHANGE_VOLTAGE);
-
-struct led_info em_x270_led_info = {
- .name = "em-x270:orange",
- .default_trigger = "battery-charging-or-full",
-};
-
-struct power_supply_info em_x270_psy_info = {
- .name = "battery",
- .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
- .voltage_max_design = 4200000,
- .voltage_min_design = 3000000,
- .use_for_apm = 1,
-};
-
-static void em_x270_battery_low(void)
-{
-#if defined(CONFIG_APM_EMULATION)
- apm_queue_event(APM_LOW_BATTERY);
-#endif
-}
-
-static void em_x270_battery_critical(void)
-{
-#if defined(CONFIG_APM_EMULATION)
- apm_queue_event(APM_CRITICAL_SUSPEND);
-#endif
-}
-
-struct da9030_battery_info em_x270_batterty_info = {
- .battery_info = &em_x270_psy_info,
-
- .charge_milliamp = 1000,
- .charge_millivolt = 4200,
-
- .vbat_low = 3600,
- .vbat_crit = 3400,
- .vbat_charge_start = 4100,
- .vbat_charge_stop = 4200,
- .vbat_charge_restart = 4000,
-
- .vcharge_min = 3200,
- .vcharge_max = 5500,
-
- .tbat_low = 197,
- .tbat_high = 78,
- .tbat_restart = 100,
-
- .batmon_interval = 0,
-
- .battery_low = em_x270_battery_low,
- .battery_critical = em_x270_battery_critical,
-};
-
-#define DA9030_SUBDEV(_name, _id, _pdata) \
- { \
- .name = "da903x-" #_name, \
- .id = DA9030_ID_##_id, \
- .platform_data = _pdata, \
- }
-
-#define DA9030_LDO(num) DA9030_SUBDEV(regulator, LDO##num, &ldo##num##_data)
-
-struct da903x_subdev_info em_x270_da9030_subdevs[] = {
- DA9030_LDO(3),
- DA9030_LDO(5),
- DA9030_LDO(10),
- DA9030_LDO(12),
- DA9030_LDO(19),
-
- DA9030_SUBDEV(regulator, BUCK2, &buck2_data),
-
- DA9030_SUBDEV(led, LED_PC, &em_x270_led_info),
- DA9030_SUBDEV(backlight, WLED, &em_x270_led_info),
- DA9030_SUBDEV(battery, BAT, &em_x270_batterty_info),
-};
-
-static struct da903x_platform_data em_x270_da9030_info = {
- .num_subdevs = ARRAY_SIZE(em_x270_da9030_subdevs),
- .subdevs = em_x270_da9030_subdevs,
-};
-
-static struct i2c_board_info em_x270_i2c_pmic_info = {
- I2C_BOARD_INFO("da9030", 0x49),
- .irq = PXA_GPIO_TO_IRQ(0),
- .platform_data = &em_x270_da9030_info,
-};
-
-static struct i2c_pxa_platform_data em_x270_pwr_i2c_info = {
- .use_pio = 1,
-};
-
-static void __init em_x270_init_da9030(void)
-{
- pxa27x_set_i2c_power_info(&em_x270_pwr_i2c_info);
- i2c_register_board_info(1, &em_x270_i2c_pmic_info, 1);
-}
-
-static struct pca953x_platform_data exeda_gpio_ext_pdata = {
- .gpio_base = 128,
-};
-
-static struct i2c_board_info exeda_i2c_info[] = {
- {
- I2C_BOARD_INFO("pca9555", 0x21),
- .platform_data = &exeda_gpio_ext_pdata,
- },
-};
-
-static struct i2c_pxa_platform_data em_x270_i2c_info = {
- .fast_mode = 1,
-};
-
-static void __init em_x270_init_i2c(void)
-{
- pxa_set_i2c_info(&em_x270_i2c_info);
-
- if (machine_is_exeda())
- i2c_register_board_info(0, ARRAY_AND_SIZE(exeda_i2c_info));
-}
-
-static void __init em_x270_module_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_pin_config));
-
- mmc_cd = GPIO13_MMC_CD;
- nand_rb = GPIO56_NAND_RB;
- dm9000_flags = DM9000_PLATF_32BITONLY;
- cam_reset = GPIO93_CAM_RESET;
- usb_hub_reset = GPIO16_USB_HUB_RESET;
-}
-
-static void __init em_x270_exeda_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(exeda_pin_config));
-
- mmc_cd = GPIO114_MMC_CD;
- nand_rb = GPIO20_NAND_RB;
- dm9000_flags = DM9000_PLATF_16BITONLY;
- cam_reset = GPIO130_CAM_RESET;
- usb_hub_reset = GPIO10_USB_HUB_RESET;
-}
-
-static void __init em_x270_init(void)
-{
- pxa2xx_mfp_config(ARRAY_AND_SIZE(common_pin_config));
-
- pxa_set_ffuart_info(NULL);
- pxa_set_btuart_info(NULL);
- pxa_set_stuart_info(NULL);
-
-#ifdef CONFIG_PM
- pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP);
-#endif
-
- if (machine_is_em_x270())
- em_x270_module_init();
- else if (machine_is_exeda())
- em_x270_exeda_init();
- else
- panic("Unsupported machine: %d\n", machine_arch_type);
-
- em_x270_init_da9030();
- em_x270_init_dm9000();
- em_x270_init_rtc();
- em_x270_init_nand();
- em_x270_init_nor();
- em_x270_init_lcd();
- em_x270_init_mmc();
- em_x270_init_ohci();
- em_x270_init_keypad();
- em_x270_init_gpio_keys();
- em_x270_init_ac97();
- em_x270_init_spi();
- em_x270_init_i2c();
- em_x270_init_camera();
- em_x270_userspace_consumers_init();
-
- regulator_has_full_constraints();
-}
-
-MACHINE_START(EM_X270, "Compulab EM-X270")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = em_x270_init,
- .restart = pxa_restart,
-MACHINE_END
-
-MACHINE_START(EXEDA, "Compulab eXeda")
- .atag_offset = 0x100,
- .map_io = pxa27x_map_io,
- .nr_irqs = PXA_NR_IRQS,
- .init_irq = pxa27x_init_irq,
- .handle_irq = pxa27x_handle_irq,
- .init_time = pxa_timer_init,
- .init_machine = em_x270_init,
- .restart = pxa_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 91f7c3e..f37c44b 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk-provider.h>
+#include <linux/gpio/machine.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
@@ -22,7 +23,6 @@
#include <linux/mfd/t7l66xb.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
-#include <linux/usb/gpio_vbus.h>
#include <linux/memblock.h>
#include <video/w100fb.h>
@@ -51,18 +51,20 @@
memblock_add(0xa0000000, SZ_64M);
}
-struct gpio_vbus_mach_info e7xx_udc_info = {
- .gpio_vbus = GPIO_E7XX_USB_DISC,
- .gpio_pullup = GPIO_E7XX_USB_PULLUP,
- .gpio_pullup_inverted = 1
+static struct gpiod_lookup_table e7xx_gpio_vbus_gpiod_table __maybe_unused = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", GPIO_E7XX_USB_DISC,
+ "vbus", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio-pxa", GPIO_E7XX_USB_PULLUP,
+ "pullup", GPIO_ACTIVE_LOW),
+ { },
+ },
};
static struct platform_device e7xx_gpio_vbus __maybe_unused = {
.name = "gpio-vbus",
.id = -1,
- .dev = {
- .platform_data = &e7xx_udc_info,
- },
};
struct pxaficp_platform_data e7xx_ficp_platform_data = {
@@ -165,6 +167,7 @@
pxa_set_stuart_info(NULL);
eseries_register_clks();
eseries_get_tmio_gpios();
+ gpiod_add_lookup_table(&e7xx_gpio_vbus_gpiod_table);
platform_add_devices(ARRAY_AND_SIZE(e330_devices));
}
@@ -216,6 +219,7 @@
pxa_set_stuart_info(NULL);
eseries_register_clks();
eseries_get_tmio_gpios();
+ gpiod_add_lookup_table(&e7xx_gpio_vbus_gpiod_table);
platform_add_devices(ARRAY_AND_SIZE(e350_devices));
}
@@ -340,6 +344,7 @@
eseries_register_clks();
eseries_get_tmio_gpios();
pxa_set_fb_info(NULL, &e400_pxafb_mach_info);
+ gpiod_add_lookup_table(&e7xx_gpio_vbus_gpiod_table);
platform_add_devices(ARRAY_AND_SIZE(e400_devices));
}
@@ -534,6 +539,7 @@
clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name,
"UDCCLK", &pxa25x_device_udc.dev),
eseries_get_tmio_gpios();
+ gpiod_add_lookup_table(&e7xx_gpio_vbus_gpiod_table);
platform_add_devices(ARRAY_AND_SIZE(e740_devices));
pxa_set_ac97_info(NULL);
pxa_set_ficp_info(&e7xx_ficp_platform_data);
@@ -733,6 +739,7 @@
clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name,
"GPIO11_CLK", NULL),
eseries_get_tmio_gpios();
+ gpiod_add_lookup_table(&e7xx_gpio_vbus_gpiod_table);
platform_add_devices(ARRAY_AND_SIZE(e750_devices));
pxa_set_ac97_info(NULL);
pxa_set_ficp_info(&e7xx_ficp_platform_data);
@@ -888,18 +895,20 @@
/* --------------------------- UDC definitions --------------------------- */
-static struct gpio_vbus_mach_info e800_udc_info = {
- .gpio_vbus = GPIO_E800_USB_DISC,
- .gpio_pullup = GPIO_E800_USB_PULLUP,
- .gpio_pullup_inverted = 1
+static struct gpiod_lookup_table e800_gpio_vbus_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", GPIO_E800_USB_DISC,
+ "vbus", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio-pxa", GPIO_E800_USB_PULLUP,
+ "pullup", GPIO_ACTIVE_LOW),
+ { },
+ },
};
static struct platform_device e800_gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
- .dev = {
- .platform_data = &e800_udc_info,
- },
};
@@ -949,6 +958,7 @@
clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name,
"GPIO11_CLK", NULL),
eseries_get_tmio_gpios();
+ gpiod_add_lookup_table(&e800_gpio_vbus_gpiod_table);
platform_add_devices(ARRAY_AND_SIZE(e800_devices));
pxa_set_ac97_info(NULL);
}
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index ec10851..eb85950 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -55,7 +55,6 @@
static struct platform_pwm_backlight_data ezx_backlight_data = {
.max_brightness = 1023,
.dft_brightness = 1023,
- .enable_gpio = -1,
};
static struct platform_device ezx_backlight_device = {
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 4b4589c..49dd618 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -20,10 +20,10 @@
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <linux/gpio/machine.h>
#include <linux/gpio.h>
#include <linux/err.h>
#include <linux/clk.h>
-#include <linux/usb/gpio_vbus.h>
#include <asm/setup.h>
#include <asm/memory.h>
@@ -101,21 +101,25 @@
#endif
#ifdef CONFIG_USB_PXA25X
-static struct gpio_vbus_mach_info gumstix_udc_info = {
- .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn,
- .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx,
+static struct gpiod_lookup_table gumstix_gpio_vbus_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", GPIO_GUMSTIX_USB_GPIOn,
+ "vbus", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio-pxa", GPIO_GUMSTIX_USB_GPIOx,
+ "pullup", GPIO_ACTIVE_HIGH),
+ { },
+ },
};
static struct platform_device gumstix_gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
- .dev = {
- .platform_data = &gumstix_udc_info,
- },
};
static void __init gumstix_udc_init(void)
{
+ gpiod_add_lookup_table(&gumstix_gpio_vbus_gpiod_table);
platform_device_register(&gumstix_gpio_vbus);
}
#else
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 311268d..1d4c5db 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -34,7 +34,6 @@
#include <linux/spi/ads7846.h>
#include <linux/spi/spi.h>
#include <linux/spi/pxa2xx_spi.h>
-#include <linux/usb/gpio_vbus.h>
#include <linux/platform_data/i2c-pxa.h>
#include <mach/hardware.h>
@@ -557,7 +556,6 @@
static struct platform_pwm_backlight_data backlight_data = {
.max_brightness = 200,
.dft_brightness = 100,
- .enable_gpio = -1,
};
static struct platform_device backlight = {
@@ -578,18 +576,24 @@
* USB "Transceiver"
*/
-static struct gpio_vbus_mach_info gpio_vbus_info = {
- .gpio_pullup = GPIO76_HX4700_USBC_PUEN,
- .gpio_vbus = GPIOD14_nUSBC_DETECT,
- .gpio_vbus_inverted = 1,
+static struct gpiod_lookup_table gpio_vbus_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ /* This GPIO is on ASIC3 */
+ GPIO_LOOKUP("asic3",
+ /* Convert to a local offset on the ASIC3 */
+ GPIOD14_nUSBC_DETECT - HX4700_ASIC3_GPIO_BASE,
+ "vbus", GPIO_ACTIVE_LOW),
+ /* This one is on the primary SOC GPIO */
+ GPIO_LOOKUP("gpio-pxa", GPIO76_HX4700_USBC_PUEN,
+ "pullup", GPIO_ACTIVE_HIGH),
+ { },
+ },
};
static struct platform_device gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
- .dev = {
- .platform_data = &gpio_vbus_info,
- },
};
static struct pxa2xx_udc_mach_info hx4700_udc_info;
@@ -883,6 +887,7 @@
pxa_set_stuart_info(NULL);
gpiod_add_lookup_table(&bq24022_gpiod_table);
+ gpiod_add_lookup_table(&gpio_vbus_gpiod_table);
platform_add_devices(devices, ARRAY_SIZE(devices));
pwm_add_table(hx4700_pwm_lookup, ARRAY_SIZE(hx4700_pwm_lookup));
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index 865b103..151e26e 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -12,6 +12,7 @@
#include <linux/irq.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
@@ -22,7 +23,6 @@
#include <linux/spi/spi.h>
#include <linux/spi/pxa2xx_spi.h>
-#include <linux/can/platform/mcp251x.h>
#include <linux/regulator/machine.h>
#include "generic.h"
@@ -69,8 +69,9 @@
.gpio_cs = ICONTROL_MCP251x_nCS4
};
-static struct mcp251x_platform_data mcp251x_info = {
- .oscillator_frequency = 16E6,
+static const struct property_entry mcp251x_properties[] = {
+ PROPERTY_ENTRY_U32("clock-frequency", 16000000),
+ {}
};
static struct spi_board_info mcp251x_board_info[] = {
@@ -79,7 +80,7 @@
.max_speed_hz = 6500000,
.bus_num = 3,
.chip_select = 0,
- .platform_data = &mcp251x_info,
+ .properties = mcp251x_properties,
.controller_data = &mcp251x_chip_info1,
.irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ1)
},
@@ -88,7 +89,7 @@
.max_speed_hz = 6500000,
.bus_num = 3,
.chip_select = 1,
- .platform_data = &mcp251x_info,
+ .properties = mcp251x_properties,
.controller_data = &mcp251x_chip_info2,
.irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ2)
},
@@ -97,7 +98,7 @@
.max_speed_hz = 6500000,
.bus_num = 4,
.chip_select = 0,
- .platform_data = &mcp251x_info,
+ .properties = mcp251x_properties,
.controller_data = &mcp251x_chip_info3,
.irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ3)
},
@@ -106,7 +107,7 @@
.max_speed_hz = 6500000,
.bus_num = 4,
.chip_select = 1,
- .platform_data = &mcp251x_info,
+ .properties = mcp251x_properties,
.controller_data = &mcp251x_chip_info4,
.irq = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ4)
}
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
deleted file mode 100644
index d54031c..0000000
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-pxa/include/mach/io.h
- *
- * Copied from asm/arch/sa1100/io.h
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a) __typesafe_io(a)
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index a499ed1..8bfaca3 100644
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
@@ -73,18 +73,6 @@
#define TOSA_GPIO_BAT1_TH_ON (TOSA_TC6393XB_GPIO_BASE + 15)
/*
- * Timing Generator
- */
-#define TG_PNLCTL 0x00
-#define TG_TPOSCTL 0x01
-#define TG_DUTYCTL 0x02
-#define TG_GPOSR 0x03
-#define TG_GPODR1 0x04
-#define TG_GPODR2 0x05
-#define TG_PINICTL 0x06
-#define TG_HPOSCTL 0x07
-
-/*
* PXA GPIOs
*/
#define TOSA_GPIO_POWERON (0)
@@ -192,7 +180,4 @@
#define TOSA_KEY_MAIL KEY_MAIL
#endif
-struct spi_device;
-extern int tosa_bl_enable(struct spi_device *spi, int enable);
-
#endif /* _ASM_ARCH_TOSA_H_ */
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 20e00e9..6fc40bc 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -277,7 +277,6 @@
static struct platform_pwm_backlight_data lpd270_backlight_data = {
.max_brightness = 1,
.dft_brightness = 1,
- .enable_gpio = -1,
};
static struct platform_device lpd270_backlight_device = {
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index e1a394a..cd9fa46 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -27,7 +27,6 @@
#include <linux/regulator/fixed.h>
#include <linux/regulator/gpio-regulator.h>
#include <linux/regulator/machine.h>
-#include <linux/usb/gpio_vbus.h>
#include <linux/platform_data/i2c-pxa.h>
#include <mach/hardware.h>
@@ -402,7 +401,6 @@
static struct platform_pwm_backlight_data backlight_data = {
.max_brightness = 272,
.dft_brightness = 100,
- .enable_gpio = -1,
.init = magician_backlight_init,
.notify = magician_backlight_notify,
.exit = magician_backlight_exit,
@@ -506,9 +504,20 @@
.end = IRQ_MAGICIAN_VBUS,
};
-static struct gpio_vbus_mach_info gpio_vbus_info = {
- .gpio_pullup = GPIO27_MAGICIAN_USBC_PUEN,
- .gpio_vbus = EGPIO_MAGICIAN_CABLE_VBUS,
+static struct gpiod_lookup_table gpio_vbus_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ /*
+ * EGPIO on register 4 index 1, the second EGPIO chip
+ * starts at register 4 so this will be at index 1 on that
+ * chip.
+ */
+ GPIO_LOOKUP("htc-egpio-1", 1,
+ "vbus", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio-pxa", GPIO27_MAGICIAN_USBC_PUEN,
+ "pullup", GPIO_ACTIVE_HIGH),
+ { },
+ },
};
static struct platform_device gpio_vbus = {
@@ -516,9 +525,6 @@
.id = -1,
.num_resources = 1,
.resource = &gpio_vbus_resource,
- .dev = {
- .platform_data = &gpio_vbus_info,
- },
};
/*
@@ -1008,7 +1014,7 @@
pxa_set_udc_info(&magician_udc_info);
/* Check LCD type we have */
- cpld = ioremap_nocache(PXA_CS3_PHYS, 0x1000);
+ cpld = ioremap(PXA_CS3_PHYS, 0x1000);
if (cpld) {
u8 board_id = __raw_readb(cpld + 0x14);
@@ -1032,6 +1038,7 @@
ARRAY_SIZE(pwm_backlight_supply), 5000000);
gpiod_add_lookup_table(&bq24022_gpiod_table);
+ gpiod_add_lookup_table(&gpio_vbus_gpiod_table);
platform_add_devices(ARRAY_AND_SIZE(devices));
}
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 1b78829..d1010ec 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -256,7 +256,6 @@
static struct platform_pwm_backlight_data mainstone_backlight_data = {
.max_brightness = 1023,
.dft_brightness = 1023,
- .enable_gpio = -1,
};
static struct platform_device mainstone_backlight_device = {
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index c360023..d3af803 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -24,7 +24,6 @@
#include <linux/power_supply.h>
#include <linux/wm97xx.h>
#include <linux/mtd/physmap.h>
-#include <linux/usb/gpio_vbus.h>
#include <linux/reboot.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/max1586.h>
@@ -177,7 +176,6 @@
static struct platform_pwm_backlight_data mioa701_backlight_data = {
.max_brightness = 100,
.dft_brightness = 50,
- .enable_gpio = -1,
};
/*
@@ -368,10 +366,13 @@
.gpio_pullup = GPIO22_USB_ENABLE,
};
-struct gpio_vbus_mach_info gpio_vbus_data = {
- .gpio_vbus = GPIO13_nUSB_DETECT,
- .gpio_vbus_inverted = 1,
- .gpio_pullup = -1,
+static struct gpiod_lookup_table gpio_vbus_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", GPIO13_nUSB_DETECT,
+ "vbus", GPIO_ACTIVE_LOW),
+ { },
+ },
};
/*
@@ -677,7 +678,7 @@
MIO_SIMPLE_DEV(pxa2xx_pcm, "pxa2xx-pcm", NULL)
MIO_SIMPLE_DEV(mioa701_sound, "mioa701-wm9713", NULL)
MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL)
-MIO_SIMPLE_DEV(gpio_vbus, "gpio-vbus", &gpio_vbus_data);
+MIO_SIMPLE_DEV(gpio_vbus, "gpio-vbus", NULL);
static struct platform_device *devices[] __initdata = {
&mioa701_gpio_keys,
@@ -750,6 +751,7 @@
pxa_set_ac97_info(&mioa701_ac97_info);
pm_power_off = mioa701_poweroff;
pwm_add_table(mioa701_pwm_lookup, ARRAY_SIZE(mioa701_pwm_lookup));
+ gpiod_add_lookup_table(&gpio_vbus_gpiod_table);
platform_add_devices(devices, ARRAY_SIZE(devices));
gsm_init();
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
index 3ad0b39..0d246a1 100644
--- a/arch/arm/mach-pxa/palm27x.c
+++ b/arch/arm/mach-pxa/palm27x.c
@@ -13,10 +13,10 @@
#include <linux/pda_power.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
+#include <linux/gpio/machine.h>
#include <linux/gpio.h>
#include <linux/wm97xx.h>
#include <linux/power_supply.h>
-#include <linux/usb/gpio_vbus.h>
#include <linux/regulator/max1586.h>
#include <linux/platform_data/i2c-pxa.h>
@@ -159,32 +159,32 @@
******************************************************************************/
#if defined(CONFIG_USB_PXA27X) || \
defined(CONFIG_USB_PXA27X_MODULE)
-static struct gpio_vbus_mach_info palm27x_udc_info = {
- .gpio_vbus_inverted = 1,
+
+/* The actual GPIO offsets get filled in in the palm27x_udc_init() call */
+static struct gpiod_lookup_table palm27x_udc_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", 0,
+ "vbus", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("gpio-pxa", 0,
+ "pullup", GPIO_ACTIVE_HIGH),
+ { },
+ },
};
static struct platform_device palm27x_gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
- .dev = {
- .platform_data = &palm27x_udc_info,
- },
};
void __init palm27x_udc_init(int vbus, int pullup, int vbus_inverted)
{
- palm27x_udc_info.gpio_vbus = vbus;
- palm27x_udc_info.gpio_pullup = pullup;
+ palm27x_udc_gpiod_table.table[0].chip_hwnum = vbus;
+ palm27x_udc_gpiod_table.table[1].chip_hwnum = pullup;
+ if (vbus_inverted)
+ palm27x_udc_gpiod_table.table[0].flags = GPIO_ACTIVE_LOW;
- palm27x_udc_info.gpio_vbus_inverted = vbus_inverted;
-
- if (!gpio_request(pullup, "USB Pullup")) {
- gpio_direction_output(pullup,
- palm27x_udc_info.gpio_vbus_inverted);
- gpio_free(pullup);
- } else
- return;
-
+ gpiod_add_lookup_table(&palm27x_udc_gpiod_table);
platform_device_register(&palm27x_gpio_vbus);
}
#endif
@@ -318,7 +318,6 @@
static struct platform_pwm_backlight_data palm27x_backlight_data = {
.max_brightness = 0xfe,
.dft_brightness = 0x7e,
- .enable_gpio = -1,
.init = palm27x_backlight_init,
.notify = palm27x_backlight_notify,
.exit = palm27x_backlight_exit,
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 9024033..7c7cbb4 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -23,7 +23,6 @@
#include <linux/gpio.h>
#include <linux/wm97xx.h>
#include <linux/power_supply.h>
-#include <linux/usb/gpio_vbus.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index f52bd15..455cb8c 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -23,7 +23,6 @@
#include <linux/power_supply.h>
#include <linux/gpio_keys.h>
#include <linux/mtd/physmap.h>
-#include <linux/usb/gpio_vbus.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -175,6 +174,15 @@
* Backlight
******************************************************************************/
#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
+
+static struct gpiod_lookup_table palmtc_pwm_bl_gpio_table = {
+ .dev_id = "pwm-backlight.0",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTC_BL_POWER,
+ "enable", GPIO_ACTIVE_HIGH),
+ },
+};
+
static struct pwm_lookup palmtc_pwm_lookup[] = {
PWM_LOOKUP("pxa25x-pwm.1", 0, "pwm-backlight.0", NULL, PALMTC_PERIOD_NS,
PWM_POLARITY_NORMAL),
@@ -183,7 +191,6 @@
static struct platform_pwm_backlight_data palmtc_backlight_data = {
.max_brightness = PALMTC_MAX_INTENSITY,
.dft_brightness = PALMTC_MAX_INTENSITY,
- .enable_gpio = GPIO_NR_PALMTC_BL_POWER,
};
static struct platform_device palmtc_backlight = {
@@ -196,6 +203,7 @@
static void __init palmtc_pwm_init(void)
{
+ gpiod_add_lookup_table(&palmtc_pwm_bl_gpio_table);
pwm_add_table(palmtc_pwm_lookup, ARRAY_SIZE(palmtc_pwm_lookup));
platform_device_register(&palmtc_backlight);
}
@@ -319,22 +327,25 @@
* UDC
******************************************************************************/
#if defined(CONFIG_USB_PXA25X)||defined(CONFIG_USB_PXA25X_MODULE)
-static struct gpio_vbus_mach_info palmtc_udc_info = {
- .gpio_vbus = GPIO_NR_PALMTC_USB_DETECT_N,
- .gpio_vbus_inverted = 1,
- .gpio_pullup = GPIO_NR_PALMTC_USB_POWER,
+static struct gpiod_lookup_table palmtc_udc_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTC_USB_DETECT_N,
+ "vbus", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTC_USB_POWER,
+ "pullup", GPIO_ACTIVE_HIGH),
+ { },
+ },
};
static struct platform_device palmtc_gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
- .dev = {
- .platform_data = &palmtc_udc_info,
- },
};
static void __init palmtc_udc_init(void)
{
+ gpiod_add_lookup_table(&palmtc_udc_gpiod_table);
platform_device_register(&palmtc_gpio_vbus);
};
#else
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index a92b966..e3bcf58 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -23,7 +23,6 @@
#include <linux/gpio.h>
#include <linux/wm97xx.h>
#include <linux/power_supply.h>
-#include <linux/usb/gpio_vbus.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -176,7 +175,6 @@
static struct platform_pwm_backlight_data palmte2_backlight_data = {
.max_brightness = PALMTE2_MAX_INTENSITY,
.dft_brightness = PALMTE2_MAX_INTENSITY,
- .enable_gpio = -1,
.init = palmte2_backlight_init,
.notify = palmte2_backlight_notify,
.exit = palmte2_backlight_exit,
@@ -201,18 +199,20 @@
/******************************************************************************
* UDC
******************************************************************************/
-static struct gpio_vbus_mach_info palmte2_udc_info = {
- .gpio_vbus = GPIO_NR_PALMTE2_USB_DETECT_N,
- .gpio_vbus_inverted = 1,
- .gpio_pullup = GPIO_NR_PALMTE2_USB_PULLUP,
+static struct gpiod_lookup_table palmte2_udc_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTE2_USB_DETECT_N,
+ "vbus", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio-pxa", GPIO_NR_PALMTE2_USB_PULLUP,
+ "pullup", GPIO_ACTIVE_HIGH),
+ { },
+ },
};
static struct platform_device palmte2_gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
- .dev = {
- .platform_data = &palmte2_udc_info,
- },
};
/******************************************************************************
@@ -368,6 +368,7 @@
pxa_set_ficp_info(&palmte2_ficp_platform_data);
pwm_add_table(palmte2_pwm_lookup, ARRAY_SIZE(palmte2_pwm_lookup));
+ gpiod_add_lookup_table(&palmte2_udc_gpiod_table);
platform_add_devices(devices, ARRAY_SIZE(devices));
}
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 926593e..07332c9 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -23,7 +23,6 @@
#include <linux/gpio.h>
#include <linux/wm97xx.h>
#include <linux/power_supply.h>
-#include <linux/usb/gpio_vbus.h>
#include <linux/mtd/platnand.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/physmap.h>
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 77fe2e3..b4a5fe0 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -25,7 +25,6 @@
#include <linux/gpio.h>
#include <linux/wm97xx.h>
#include <linux/power_supply.h>
-#include <linux/usb/gpio_vbus.h>
#include <linux/platform_data/i2c-gpio.h>
#include <linux/gpio/machine.h>
@@ -48,8 +47,6 @@
#include "pm.h"
#include <linux/platform_data/media/camera-pxa.h>
-#include <media/soc_camera.h>
-
#include "generic.h"
#include "devices.h"
@@ -273,115 +270,6 @@
device_initcall(palmz72_pm_init);
#endif
-/******************************************************************************
- * SoC Camera
- ******************************************************************************/
-#if defined(CONFIG_SOC_CAMERA_OV9640) || \
- defined(CONFIG_SOC_CAMERA_OV9640_MODULE)
-static struct pxacamera_platform_data palmz72_pxacamera_platform_data = {
- .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 |
- PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN,
- .mclk_10khz = 2600,
-};
-
-/* Board I2C devices. */
-static struct i2c_board_info palmz72_i2c_device[] = {
- {
- I2C_BOARD_INFO("ov9640", 0x30),
- }
-};
-
-static int palmz72_camera_power(struct device *dev, int power)
-{
- gpio_set_value(GPIO_NR_PALMZ72_CAM_PWDN, !power);
- mdelay(50);
- return 0;
-}
-
-static int palmz72_camera_reset(struct device *dev)
-{
- gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 1);
- mdelay(50);
- gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 0);
- mdelay(50);
- return 0;
-}
-
-static struct soc_camera_link palmz72_iclink = {
- .bus_id = 0, /* Match id in pxa27x_device_camera in device.c */
- .board_info = &palmz72_i2c_device[0],
- .i2c_adapter_id = 0,
- .module_name = "ov96xx",
- .power = &palmz72_camera_power,
- .reset = &palmz72_camera_reset,
- .flags = SOCAM_DATAWIDTH_8,
-};
-
-static struct gpiod_lookup_table palmz72_i2c_gpiod_table = {
- .dev_id = "i2c-gpio.0",
- .table = {
- GPIO_LOOKUP_IDX("gpio-pxa", 118, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("gpio-pxa", 117, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data palmz72_i2c_bus_data = {
- .udelay = 10,
- .timeout = 100,
-};
-
-static struct platform_device palmz72_i2c_bus_device = {
- .name = "i2c-gpio",
- .id = 0, /* we use this as a replacement for i2c-pxa */
- .dev = {
- .platform_data = &palmz72_i2c_bus_data,
- }
-};
-
-static struct platform_device palmz72_camera = {
- .name = "soc-camera-pdrv",
- .id = -1,
- .dev = {
- .platform_data = &palmz72_iclink,
- },
-};
-
-/* Here we request the camera GPIOs and configure them. We power up the camera
- * module, deassert the reset pin, but put it into powerdown (low to no power
- * consumption) mode. This allows us to later bring the module up fast. */
-static struct gpio palmz72_camera_gpios[] = {
- { GPIO_NR_PALMZ72_CAM_POWER, GPIOF_INIT_HIGH,"Camera DVDD" },
- { GPIO_NR_PALMZ72_CAM_RESET, GPIOF_INIT_LOW, "Camera RESET" },
- { GPIO_NR_PALMZ72_CAM_PWDN, GPIOF_INIT_LOW, "Camera PWDN" },
-};
-
-static inline void __init palmz72_cam_gpio_init(void)
-{
- int ret;
-
- ret = gpio_request_array(ARRAY_AND_SIZE(palmz72_camera_gpios));
- if (!ret)
- gpio_free_array(ARRAY_AND_SIZE(palmz72_camera_gpios));
- else
- printk(KERN_ERR "Camera GPIO init failed!\n");
-
- return;
-}
-
-static void __init palmz72_camera_init(void)
-{
- palmz72_cam_gpio_init();
- pxa_set_camera_info(&palmz72_pxacamera_platform_data);
- gpiod_add_lookup_table(&palmz72_i2c_gpiod_table);
- platform_device_register(&palmz72_i2c_bus_device);
- platform_device_register(&palmz72_camera);
-}
-#else
-static inline void palmz72_camera_init(void) {}
-#endif
-
static struct gpiod_lookup_table palmz72_mci_gpio_table = {
.dev_id = "pxa2xx-mci.0",
.table = {
@@ -417,7 +305,6 @@
palm27x_pmic_init();
palmz72_kpc_init();
palmz72_leds_init();
- palmz72_camera_init();
}
MACHINE_START(PALMZ72, "Palm Zire72")
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index cb1c567..8dfcc36 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -24,10 +24,6 @@
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
-#include <media/i2c/mt9v022.h>
-#include <media/soc_camera.h>
-
-#include <linux/platform_data/media/camera-pxa.h>
#include <asm/mach/map.h>
#include "pxa27x.h"
#include <mach/audio.h>
@@ -154,7 +150,6 @@
static struct platform_pwm_backlight_data pcm990_backlight_data = {
.max_brightness = 1023,
.dft_brightness = 1023,
- .enable_gpio = -1,
};
static struct platform_device pcm990_backlight_device = {
@@ -376,149 +371,6 @@
};
/*
- * PXA27x Camera specific stuff
- */
-#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
-static unsigned long pcm990_camera_pin_config[] = {
- /* CIF */
- GPIO98_CIF_DD_0,
- GPIO105_CIF_DD_1,
- GPIO104_CIF_DD_2,
- GPIO103_CIF_DD_3,
- GPIO95_CIF_DD_4,
- GPIO94_CIF_DD_5,
- GPIO93_CIF_DD_6,
- GPIO108_CIF_DD_7,
- GPIO107_CIF_DD_8,
- GPIO106_CIF_DD_9,
- GPIO42_CIF_MCLK,
- GPIO45_CIF_PCLK,
- GPIO43_CIF_FV,
- GPIO44_CIF_LV,
-};
-
-/*
- * CICR4: PCLK_EN: Pixel clock is supplied by the sensor
- * MCLK_EN: Master clock is generated by PXA
- * PCP: Data sampled on the falling edge of pixel clock
- */
-struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
- .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_DATAWIDTH_10 |
- PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN/* | PXA_CAMERA_PCP*/,
- .mclk_10khz = 1000,
-};
-
-#include <linux/platform_data/pca953x.h>
-
-static struct pca953x_platform_data pca9536_data = {
- .gpio_base = PXA_NR_BUILTIN_GPIO,
-};
-
-static int gpio_bus_switch = -EINVAL;
-
-static int pcm990_camera_set_bus_param(struct soc_camera_link *link,
- unsigned long flags)
-{
- if (gpio_bus_switch < 0) {
- if (flags == SOCAM_DATAWIDTH_10)
- return 0;
- else
- return -EINVAL;
- }
-
- if (flags & SOCAM_DATAWIDTH_8)
- gpio_set_value_cansleep(gpio_bus_switch, 1);
- else
- gpio_set_value_cansleep(gpio_bus_switch, 0);
-
- return 0;
-}
-
-static unsigned long pcm990_camera_query_bus_param(struct soc_camera_link *link)
-{
- int ret;
-
- if (gpio_bus_switch < 0) {
- ret = gpio_request(PXA_NR_BUILTIN_GPIO, "camera");
- if (!ret) {
- gpio_bus_switch = PXA_NR_BUILTIN_GPIO;
- gpio_direction_output(gpio_bus_switch, 0);
- }
- }
-
- if (gpio_bus_switch >= 0)
- return SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_10;
- else
- return SOCAM_DATAWIDTH_10;
-}
-
-static void pcm990_camera_free_bus(struct soc_camera_link *link)
-{
- if (gpio_bus_switch < 0)
- return;
-
- gpio_free(gpio_bus_switch);
- gpio_bus_switch = -EINVAL;
-}
-
-/* Board I2C devices. */
-static struct i2c_board_info __initdata pcm990_i2c_devices[] = {
- {
- /* Must initialize before the camera(s) */
- I2C_BOARD_INFO("pca9536", 0x41),
- .platform_data = &pca9536_data,
- },
-};
-
-static struct mt9v022_platform_data mt9v022_pdata = {
- .y_skip_top = 1,
-};
-
-static struct i2c_board_info pcm990_camera_i2c[] = {
- {
- I2C_BOARD_INFO("mt9v022", 0x48),
- }, {
- I2C_BOARD_INFO("mt9m001", 0x5d),
- },
-};
-
-static struct soc_camera_link iclink[] = {
- {
- .bus_id = 0, /* Must match with the camera ID */
- .board_info = &pcm990_camera_i2c[0],
- .priv = &mt9v022_pdata,
- .i2c_adapter_id = 0,
- .query_bus_param = pcm990_camera_query_bus_param,
- .set_bus_param = pcm990_camera_set_bus_param,
- .free_bus = pcm990_camera_free_bus,
- }, {
- .bus_id = 0, /* Must match with the camera ID */
- .board_info = &pcm990_camera_i2c[1],
- .i2c_adapter_id = 0,
- .query_bus_param = pcm990_camera_query_bus_param,
- .set_bus_param = pcm990_camera_set_bus_param,
- .free_bus = pcm990_camera_free_bus,
- },
-};
-
-static struct platform_device pcm990_camera[] = {
- {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &iclink[0],
- },
- }, {
- .name = "soc-camera-pdrv",
- .id = 1,
- .dev = {
- .platform_data = &iclink[1],
- },
- },
-};
-#endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */
-
-/*
* system init for baseboard usage. Will be called by pcm027 init.
*
* Add platform devices present on this baseboard and init
@@ -552,15 +404,5 @@
pxa_set_i2c_info(NULL);
pxa_set_ac97_info(NULL);
-#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
- pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_camera_pin_config));
- pxa_set_camera_info(&pcm990_pxacamera_platform_data);
-
- i2c_register_board_info(0, ARRAY_AND_SIZE(pcm990_i2c_devices));
-
- platform_device_register(&pcm990_camera[0]);
- platform_device_register(&pcm990_camera[1]);
-#endif
-
printk(KERN_INFO "PCM-990 Evaluation baseboard initialized\n");
}
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index a4fdc39..371008e 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -525,13 +525,33 @@
}
}
+static struct gpiod_lookup_table spitz_lcdcon_gpio_table = {
+ .dev_id = "spi2.1",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", SPITZ_GPIO_BACKLIGHT_CONT,
+ "BL_CONT", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio-pxa", SPITZ_GPIO_BACKLIGHT_ON,
+ "BL_ON", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table akita_lcdcon_gpio_table = {
+ .dev_id = "spi2.1",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", AKITA_GPIO_BACKLIGHT_CONT,
+ "BL_CONT", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio-pxa", AKITA_GPIO_BACKLIGHT_ON,
+ "BL_ON", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static struct corgi_lcd_platform_data spitz_lcdcon_info = {
.init_mode = CORGI_LCD_MODE_VGA,
.max_intensity = 0x2f,
.default_intensity = 0x1f,
.limit_mask = 0x0b,
- .gpio_backlight_cont = SPITZ_GPIO_BACKLIGHT_CONT,
- .gpio_backlight_on = SPITZ_GPIO_BACKLIGHT_ON,
.kick_battery = spitz_bl_kick_battery,
};
@@ -574,12 +594,10 @@
static void __init spitz_spi_init(void)
{
- struct corgi_lcd_platform_data *lcd_data = &spitz_lcdcon_info;
-
- if (machine_is_akita()) {
- lcd_data->gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
- lcd_data->gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
- }
+ if (machine_is_akita())
+ gpiod_add_lookup_table(&akita_lcdcon_gpio_table);
+ else
+ gpiod_add_lookup_table(&spitz_lcdcon_gpio_table);
pxa2xx_set_spi_info(2, &spitz_spi_info);
spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 93466fa..a15eb3b 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -178,13 +178,11 @@
/* primary backlight */
.max_brightness = 100,
.dft_brightness = 100,
- .enable_gpio = -1,
},
[1] = {
/* secondary backlight */
.max_brightness = 100,
.dft_brightness = 100,
- .enable_gpio = -1,
},
};
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index f537ff1..4317097 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -33,7 +33,6 @@
#include <linux/spi/pxa2xx_spi.h>
#include <linux/input/matrix_keypad.h>
#include <linux/platform_data/i2c-pxa.h>
-#include <linux/usb/gpio_vbus.h>
#include <linux/reboot.h>
#include <linux/memblock.h>
@@ -240,18 +239,20 @@
/*
* USB Device Controller
*/
-static struct gpio_vbus_mach_info tosa_udc_info = {
- .gpio_pullup = TOSA_GPIO_USB_PULLUP,
- .gpio_vbus = TOSA_GPIO_USB_IN,
- .gpio_vbus_inverted = 1,
+static struct gpiod_lookup_table tosa_udc_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_USB_IN,
+ "vbus", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_USB_PULLUP,
+ "pullup", GPIO_ACTIVE_HIGH),
+ { },
+ },
};
static struct platform_device tosa_gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
- .dev = {
- .platform_data = &tosa_udc_info,
- },
};
/*
@@ -368,6 +369,15 @@
/*
* Tosa AC IN
*/
+static struct gpiod_lookup_table tosa_power_gpiod_table = {
+ .dev_id = "gpio-charger",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_AC_IN,
+ NULL, GPIO_ACTIVE_LOW),
+ { },
+ },
+};
+
static char *tosa_ac_supplied_to[] = {
"main-battery",
"backup-battery",
@@ -377,8 +387,6 @@
static struct gpio_charger_platform_data tosa_power_data = {
.name = "charger",
.type = POWER_SUPPLY_TYPE_MAINS,
- .gpio = TOSA_GPIO_AC_IN,
- .gpio_active_low = 1,
.supplied_to = tosa_ac_supplied_to,
.num_supplicants = ARRAY_SIZE(tosa_ac_supplied_to),
};
@@ -813,6 +821,26 @@
.num_chipselect = 1,
};
+static struct gpiod_lookup_table tosa_lcd_gpio_table = {
+ .dev_id = "spi2.0",
+ .table = {
+ GPIO_LOOKUP("tc6393xb",
+ TOSA_GPIO_TG_ON - TOSA_TC6393XB_GPIO_BASE,
+ "tg #pwr", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table tosa_lcd_bl_gpio_table = {
+ .dev_id = "i2c-tosa-bl",
+ .table = {
+ GPIO_LOOKUP("tc6393xb",
+ TOSA_GPIO_BL_C20MA - TOSA_TC6393XB_GPIO_BASE,
+ "backlight", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static struct spi_board_info spi_board_info[] __initdata = {
{
.modalias = "tosa-lcd",
@@ -923,10 +951,14 @@
platform_scoop_config = &tosa_pcmcia_config;
pxa2xx_set_spi_info(2, &pxa_ssp_master_info);
+ gpiod_add_lookup_table(&tosa_lcd_gpio_table);
+ gpiod_add_lookup_table(&tosa_lcd_bl_gpio_table);
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
clk_add_alias("CLK_CK3P6MI", tc6393xb_device.name, "GPIO11_CLK", NULL);
+ gpiod_add_lookup_table(&tosa_udc_gpiod_table);
+ gpiod_add_lookup_table(&tosa_power_gpiod_table);
platform_add_devices(devices, ARRAY_SIZE(devices));
}
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index c06031d..3aa34e9 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -404,7 +404,6 @@
static struct platform_pwm_backlight_data viper_backlight_data = {
.max_brightness = 100,
.dft_brightness = 100,
- .enable_gpio = -1,
.init = viper_backlight_init,
.notify = viper_backlight_notify,
.exit = viper_backlight_exit,
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index 26a5ebc..14505e8 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -14,7 +14,6 @@
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
-#include <linux/usb/gpio_vbus.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
@@ -352,17 +351,18 @@
* USB Gadget
******************************************************************************/
#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
-static struct gpio_vbus_mach_info vpac270_gpio_vbus_info = {
- .gpio_vbus = GPIO41_VPAC270_UDC_DETECT,
- .gpio_pullup = -1,
+static struct gpiod_lookup_table vpac270_gpio_vbus_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("gpio-pxa", GPIO41_VPAC270_UDC_DETECT,
+ "vbus", GPIO_ACTIVE_HIGH),
+ { },
+ },
};
static struct platform_device vpac270_gpio_vbus = {
.name = "gpio-vbus",
.id = -1,
- .dev = {
- .platform_data = &vpac270_gpio_vbus_info,
- },
};
static void vpac270_udc_command(int cmd)
@@ -381,6 +381,7 @@
static void __init vpac270_udc_init(void)
{
pxa_set_udc_info(&vpac270_udc_info);
+ gpiod_add_lookup_table(&vpac270_gpio_vbus_gpiod_table);
platform_device_register(&vpac270_gpio_vbus);
}
#else
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 900cefc..21fd76b 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -210,13 +210,11 @@
/* Keypad Backlight */
.max_brightness = 1023,
.dft_brightness = 0,
- .enable_gpio = -1,
},
[1] = {
/* LCD Backlight */
.max_brightness = 1023,
.dft_brightness = 512,
- .enable_gpio = -1,
},
};
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index da113c8..b27fc7a 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -13,6 +13,7 @@
#include <linux/leds.h>
#include <linux/irq.h>
#include <linux/pm.h>
+#include <linux/property.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/serial_8250.h>
@@ -27,7 +28,6 @@
#include <linux/platform_data/i2c-pxa.h>
#include <linux/platform_data/pca953x.h>
#include <linux/apm-emulation.h>
-#include <linux/can/platform/mcp251x.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
@@ -428,14 +428,15 @@
},
};
-static struct mcp251x_platform_data zeus_mcp2515_pdata = {
- .oscillator_frequency = 16*1000*1000,
+static const struct property_entry mcp251x_properties[] = {
+ PROPERTY_ENTRY_U32("clock-frequency", 16000000),
+ {}
};
static struct spi_board_info zeus_spi_board_info[] = {
[0] = {
.modalias = "mcp2515",
- .platform_data = &zeus_mcp2515_pdata,
+ .properties = mcp251x_properties,
.irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
.max_speed_hz = 1*1000*1000,
.bus_num = 3,
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index bf2ab5b..79f0025 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -117,7 +117,6 @@
static struct platform_pwm_backlight_data zylonite_backlight_data = {
.max_brightness = 100,
.dft_brightness = 100,
- .enable_gpio = -1,
};
static struct platform_device zylonite_backlight_device = {
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
index ecbf3c4..1772ecc 100644
--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
@@ -12,6 +12,11 @@
if ARCH_QCOM
+config ARCH_IPQ40XX
+ bool "Enable support for IPQ40XX"
+ select CLKSRC_QCOM
+ select HAVE_ARM_ARCH_TIMER
+
config ARCH_MSM8X60
bool "Enable support for MSM8X60"
select CLKSRC_QCOM
diff --git a/arch/arm/mach-realtek/Kconfig b/arch/arm/mach-realtek/Kconfig
new file mode 100644
index 0000000..19fdcf0
--- /dev/null
+++ b/arch/arm/mach-realtek/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+menuconfig ARCH_REALTEK
+ bool "Realtek SoCs"
+ depends on ARCH_MULTI_V7
+ select ARM_GIC
+ select ARM_GLOBAL_TIMER
+ select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+ select GENERIC_IRQ_CHIP
+ select RESET_CONTROLLER
+ help
+ This enables support for the Realtek RTD1195 SoC family.
diff --git a/arch/arm/mach-realtek/Makefile b/arch/arm/mach-realtek/Makefile
new file mode 100644
index 0000000..5382d5b
--- /dev/null
+++ b/arch/arm/mach-realtek/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+obj-y += rtd1195.o
diff --git a/arch/arm/mach-realtek/rtd1195.c b/arch/arm/mach-realtek/rtd1195.c
new file mode 100644
index 0000000..0381a44
--- /dev/null
+++ b/arch/arm/mach-realtek/rtd1195.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek RTD1195
+ *
+ * Copyright (c) 2017-2019 Andreas Färber
+ */
+
+#include <linux/memblock.h>
+#include <asm/mach/arch.h>
+
+static void __init rtd1195_memblock_remove(phys_addr_t base, phys_addr_t size)
+{
+ int ret;
+
+ ret = memblock_remove(base, size);
+ if (ret)
+ pr_err("Failed to remove memblock %pa (%d)\n", &base, ret);
+}
+
+static void __init rtd1195_reserve(void)
+{
+ /* Exclude boot ROM from RAM */
+ rtd1195_memblock_remove(0x00000000, 0x0000a800);
+
+ /* Exclude peripheral register spaces from RAM */
+ rtd1195_memblock_remove(0x18000000, 0x00070000);
+ rtd1195_memblock_remove(0x18100000, 0x01000000);
+}
+
+static const char *const rtd1195_dt_compat[] __initconst = {
+ "realtek,rtd1195",
+ NULL
+};
+
+DT_MACHINE_START(rtd1195, "Realtek RTD1195")
+ .dt_compat = rtd1195_dt_compat,
+ .reserve = rtd1195_reserve,
+ .l2c_aux_val = 0x0,
+ .l2c_aux_mask = ~0x0,
+MACHINE_END
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 44ebbf9..5c6031b 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -6,7 +6,6 @@
select ARM_GIC
select ARM_TIMER_SP804
select CLK_SP810
- select COMMON_CLK_VERSATILE
select GPIO_PL061 if GPIOLIB
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
@@ -16,12 +15,10 @@
select MACH_REALVIEW_EB if ARCH_MULTI_V5
select MFD_SYSCON
select PLAT_VERSATILE
- select PLAT_VERSATILE_SCHED_CLOCK
select POWER_RESET
select POWER_RESET_VERSATILE
select POWER_SUPPLY
select SOC_REALVIEW
- select USE_OF
help
This enables support for ARM Ltd RealView boards.
@@ -56,8 +53,6 @@
config REALVIEW_EB_A9MP
bool "Support Multicore Cortex-A9 Tile"
depends on MACH_REALVIEW_EB && ARCH_MULTI_V7
- select HAVE_SMP
- select MIGHT_HAVE_CACHE_L2X0
help
Enable support for the Cortex-A9MPCore tile fitted to the
Realview(R) Emulation Baseboard platform.
@@ -66,7 +61,6 @@
bool "Support ARM11MPCore Tile"
depends on MACH_REALVIEW_EB && ARCH_MULTI_V6
select HAVE_SMP
- select MIGHT_HAVE_CACHE_L2X0
help
Enable support for the ARM11MPCore tile fitted to the Realview(R)
Emulation Baseboard platform.
@@ -75,7 +69,6 @@
bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
depends on ARCH_MULTI_V6
select HAVE_SMP
- select MIGHT_HAVE_CACHE_L2X0
help
Include support for the ARM(R) RealView(R) Platform Baseboard for
the ARM11MPCore. This platform has an on-board ARM11MPCore and has
@@ -87,7 +80,6 @@
depends on ARCH_MULTI_V6
select CPU_V6
select HAVE_TCM
- select MIGHT_HAVE_CACHE_L2X0
help
Include support for the ARM(R) RealView(R) Platform Baseboard for
ARM1176JZF-S.
@@ -103,8 +95,6 @@
config MACH_REALVIEW_PBX
bool "Support RealView(R) Platform Baseboard Explore for Cortex-A9"
depends on ARCH_MULTI_V7
- select HAVE_SMP
- select MIGHT_HAVE_CACHE_L2X0
select ZONE_DMA
help
Include support for the ARM(R) RealView(R) Platform Baseboard
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 649e0a5..d608568 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -180,7 +180,7 @@
rsize = resource_size(&res);
if (rsize < trampoline_sz) {
- pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
+ pr_err("%s: reserved block with size 0x%x is too small for trampoline size 0x%x\n",
__func__, rsize, trampoline_sz);
return -EINVAL;
}
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index f9797a2..beea456 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -9,9 +9,9 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/of_clk.h>
#include <linux/of_platform.h>
#include <linux/irqchip.h>
-#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c
index 75cfad2..827b50f 100644
--- a/arch/arm/mach-rpc/ecard.c
+++ b/arch/arm/mach-rpc/ecard.c
@@ -63,7 +63,7 @@
struct completion *complete;
};
-struct expcard_blacklist {
+struct expcard_quirklist {
unsigned short manufacturer;
unsigned short product;
const char *type;
@@ -79,7 +79,7 @@
/* List of descriptions of cards which don't have an extended
* identification, or chunk directories containing a description.
*/
-static struct expcard_blacklist __initdata blacklist[] = {
+static struct expcard_quirklist quirklist[] __initdata = {
{ MANU_ACORN, PROD_ACORN_ETHER1, "Acorn Ether1" },
{ MANU_ATOMWIDE, PROD_ATOMWIDE_3PSERIAL, NULL, atomwide_3p_quirk },
};
@@ -935,13 +935,13 @@
ec->fiqmask = 4;
}
- for (i = 0; i < ARRAY_SIZE(blacklist); i++)
- if (blacklist[i].manufacturer == ec->cid.manufacturer &&
- blacklist[i].product == ec->cid.product) {
- if (blacklist[i].type)
- ec->card_desc = blacklist[i].type;
- if (blacklist[i].init)
- blacklist[i].init(ec);
+ for (i = 0; i < ARRAY_SIZE(quirklist); i++)
+ if (quirklist[i].manufacturer == ec->cid.manufacturer &&
+ quirklist[i].product == ec->cid.product) {
+ if (quirklist[i].type)
+ ec->card_desc = quirklist[i].type;
+ if (quirklist[i].init)
+ quirklist[i].init(ec);
break;
}
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index ea2c842..d23970b 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -46,7 +46,7 @@
switch (tag->u.acorn.vram_pages) {
case 512:
vram_size += PAGE_SIZE * 256;
- /* Fall through - ??? */
+ fallthrough; /* ??? */
case 256:
vram_size += PAGE_SIZE * 256;
default:
diff --git a/arch/arm/mach-rpc/time.c b/arch/arm/mach-rpc/time.c
index 1d75015..da85cac 100644
--- a/arch/arm/mach-rpc/time.c
+++ b/arch/arm/mach-rpc/time.c
@@ -85,11 +85,6 @@
return IRQ_HANDLED;
}
-static struct irqaction ioc_timer_irq = {
- .name = "timer",
- .handler = ioc_timer_interrupt
-};
-
/*
* Set up timer interrupt.
*/
@@ -97,5 +92,6 @@
{
WARN_ON(clocksource_register_hz(&ioctime_clocksource, RPC_CLOCK_FREQ));
ioctime_init();
- setup_irq(IRQ_TIMER0, &ioc_timer_irq);
+ if (request_irq(IRQ_TIMER0, ioc_timer_interrupt, 0, "timer", NULL))
+ pr_err("Failed to request irq %d (timer)\n", IRQ_TIMER0);
}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/mach-s3c/Kconfig
similarity index 69%
rename from arch/arm/plat-samsung/Kconfig
rename to arch/arm/mach-s3c/Kconfig
index 790c87e..25606e6 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/mach-s3c/Kconfig
@@ -2,12 +2,16 @@
#
# Copyright 2009 Simtec Electronics
+source "arch/arm/mach-s3c/Kconfig.s3c24xx"
+source "arch/arm/mach-s3c/Kconfig.s3c64xx"
+
config PLAT_SAMSUNG
bool
- depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_EXYNOS || ARCH_S5PV210
+ depends on PLAT_S3C24XX || ARCH_S3C64XX
default y
select GENERIC_IRQ_CHIP
select NO_IOPORT_MAP
+ select SOC_SAMSUNG
help
Base platform code for all Samsung SoC based systems
@@ -154,7 +158,7 @@
bool
default y if ARCH_S3C24XX
help
- Complie in platform device definition for Watchdog Timer
+ Compile in platform device definition for Watchdog Timer
config S3C_DEV_NAND
bool
@@ -169,7 +173,7 @@
config S3C_DEV_RTC
bool
help
- Complie in platform device definition for RTC
+ Compile in platform device definition for RTC
config SAMSUNG_DEV_ADC
bool
@@ -234,55 +238,6 @@
pinctrl-samsung driver.
endif
-comment "Power management"
-
-config SAMSUNG_PM_DEBUG
- bool "Samsung PM Suspend debug"
- depends on PM && DEBUG_KERNEL
- depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
- depends on DEBUG_EXYNOS_UART || DEBUG_S3C24XX_UART || DEBUG_S3C2410_UART
- depends on DEBUG_LL && MMU
- help
- Say Y here if you want verbose debugging from the PM Suspend and
- Resume code. See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
- for more information.
-
-config S3C_PM_DEBUG_LED_SMDK
- bool "SMDK LED suspend/resume debugging"
- depends on PM && (MACH_SMDK6410)
- help
- Say Y here to enable the use of the SMDK LEDs on the baseboard
- for debugging of the state of the suspend and resume process.
-
- Note, this currently only works for S3C64XX based SMDK boards.
-
-config SAMSUNG_PM_CHECK
- bool "S3C2410 PM Suspend Memory CRC"
- depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210)
- select CRC32
- help
- Enable the PM code's memory area checksum over sleep. This option
- will generate CRCs of all blocks of memory, and store them before
- going to sleep. The blocks are then checked on resume for any
- errors.
-
- Note, this can take several seconds depending on memory size
- and CPU speed.
-
- See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
-
-config SAMSUNG_PM_CHECK_CHUNKSIZE
- int "S3C2410 PM Suspend CRC Chunksize (KiB)"
- depends on PM && SAMSUNG_PM_CHECK
- default 64
- help
- Set the chunksize in Kilobytes of the CRC for checking memory
- corruption over suspend and resume. A smaller value will mean that
- the CRC data block will take more memory, but will identify any
- faults with better precision.
-
- See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
-
config SAMSUNG_WAKEMASK
bool
depends on PM
@@ -291,19 +246,5 @@
and above. This code allows a set of interrupt to wakeup-mask
mappings. See <plat/wakeup-mask.h>
-config SAMSUNG_WDT_RESET
- bool
- help
- Compile support for system restart by triggering watchdog reset.
- Used on SoCs that do not provide dedicated reset control.
-
-config DEBUG_S3C_UART
- depends on PLAT_SAMSUNG
- int
- default "0" if DEBUG_S3C_UART0
- default "1" if DEBUG_S3C_UART1
- default "2" if DEBUG_S3C_UART2
- default "3" if DEBUG_S3C_UART3
-
endmenu
endif
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c/Kconfig.s3c24xx
similarity index 94%
rename from arch/arm/mach-s3c24xx/Kconfig
rename to arch/arm/mach-s3c/Kconfig.s3c24xx
index 686f0bb..000e3e2 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c/Kconfig.s3c24xx
@@ -19,12 +19,12 @@
-menu "SAMSUNG S3C24XX SoCs Support"
+menu "Samsung S3C24XX SoCs Support"
comment "S3C24XX SoCs"
config CPU_S3C2410
- bool "SAMSUNG S3C2410"
+ bool "Samsung S3C2410"
default y
select CPU_ARM920T
select S3C2410_COMMON_CLK
@@ -35,7 +35,7 @@
of Samsung Mobile CPUs.
config CPU_S3C2412
- bool "SAMSUNG S3C2412"
+ bool "Samsung S3C2412"
select CPU_ARM926T
select S3C2412_COMMON_CLK
select S3C2412_PM if PM_SLEEP
@@ -43,7 +43,7 @@
Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
config CPU_S3C2416
- bool "SAMSUNG S3C2416/S3C2450"
+ bool "Samsung S3C2416/S3C2450"
select CPU_ARM926T
select S3C2416_PM if PM_SLEEP
select S3C2443_COMMON_CLK
@@ -51,7 +51,7 @@
Support for the S3C2416 SoC from the S3C24XX line
config CPU_S3C2440
- bool "SAMSUNG S3C2440"
+ bool "Samsung S3C2440"
select CPU_ARM920T
select S3C2410_COMMON_CLK
select S3C2410_PM if PM_SLEEP
@@ -59,7 +59,7 @@
Support for S3C2440 Samsung Mobile CPU based systems.
config CPU_S3C2442
- bool "SAMSUNG S3C2442"
+ bool "Samsung S3C2442"
select CPU_ARM920T
select S3C2410_COMMON_CLK
select S3C2410_PM if PM_SLEEP
@@ -71,7 +71,7 @@
depends on CPU_S3C2440 || CPU_S3C2442
config CPU_S3C2443
- bool "SAMSUNG S3C2443"
+ bool "Samsung S3C2443"
select CPU_ARM920T
select S3C2443_COMMON_CLK
help
@@ -123,11 +123,6 @@
This also means that the PLL tables for the selected CPU(s) will
be built which may increase the size of the kernel image.
-config S3C_SETUP_CAMIF
- bool
- help
- Compile in common setup code for S3C CAMIF devices
-
# cpu frequency items common between s3c2410 and s3c2440/s3c2442
config S3C2410_IOTIMING
@@ -137,13 +132,6 @@
Internal node to select io timing code that is common to the s3c2410
and s3c2440/s3c2442 cpu frequency support.
-config S3C2410_CPUFREQ_UTILS
- bool
- depends on ARM_S3C24XX_CPUFREQ
- help
- Internal node to select timing code that is common to the s3c2410
- and s3c2440/s3c244 cpu frequency support.
-
# cpu frequency support common to s3c2412, s3c2413 and s3c2442
config S3C2412_IOTIMING
@@ -267,7 +255,7 @@
select S3C_DEV_USB_HOST
help
Say Y here if you are using the TinCanTools Hammer Board
- <http://www.tincantools.com>
+ <https://www.tincantools.com>
config MACH_VR1000
bool "Thorcom VR1000"
@@ -468,7 +456,6 @@
select NEW_LEDS
select S3C_DEV_NAND
select S3C_DEV_USB_HOST
- select S3C_SETUP_CAMIF
help
Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
available via various sources. It can come with a 3.5" or 7" touch LCD.
@@ -591,6 +578,6 @@
help
Internal node for H1940 and related PM
-endmenu # SAMSUNG S3C24XX SoCs Support
+endmenu # Samsung S3C24XX SoCs Support
endif # ARCH_S3C24XX
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c/Kconfig.s3c64xx
similarity index 97%
rename from arch/arm/mach-s3c64xx/Kconfig
rename to arch/arm/mach-s3c/Kconfig.s3c64xx
index 5700822..f3fcb57 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c/Kconfig.s3c64xx
@@ -13,15 +13,15 @@
select GPIO_SAMSUNG if ATAGS
select GPIOLIB
select HAVE_S3C2410_I2C if I2C
- select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_TCM
select PLAT_SAMSUNG
select PM_GENERIC_DOMAINS if PM
select S3C_DEV_NAND if ATAGS
select S3C_GPIO_TRACK if ATAGS
+ select S3C2410_WATCHDOG
select SAMSUNG_ATAGS if ATAGS
select SAMSUNG_WAKEMASK if PM
- select SAMSUNG_WDT_RESET
+ select WATCHDOG
help
Samsung S3C64XX series based systems
@@ -165,7 +165,6 @@
bool "SMDK6410"
depends on ATAGS
select CPU_S3C6410
- select HAVE_S3C2410_WATCHDOG if WATCHDOG
select S3C64XX_SETUP_FB_24BPP
select S3C64XX_SETUP_I2C1
select S3C64XX_SETUP_IDE
@@ -336,7 +335,6 @@
config MACH_S3C64XX_DT
bool "Samsung S3C6400/S3C6410 machine using Device Tree"
- select TIMER_OF
select CPU_S3C6400
select CPU_S3C6410
select PINCTRL
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/mach-s3c/Makefile
similarity index 62%
rename from arch/arm/plat-samsung/Makefile
rename to arch/arm/mach-s3c/Makefile
index 3db9d2c..54188d1 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/mach-s3c/Makefile
@@ -2,9 +2,16 @@
#
# Copyright 2009 Simtec Electronics
-ccflags-$(CONFIG_ARCH_S3C64XX) := -I$(srctree)/arch/arm/mach-s3c64xx/include
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include
+ifdef CONFIG_ARCH_S3C24XX
+include $(src)/Makefile.s3c24xx
+endif
+
+ifdef CONFIG_ARCH_S3C64XX
+include $(src)/Makefile.s3c64xx
+endif
+
# Objects we always build independent of SoC choice
obj-y += init.o cpu.o
@@ -24,12 +31,7 @@
# PM support
-obj-$(CONFIG_PM_SLEEP) += pm-common.o
-obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm-common.o
-obj-$(CONFIG_SAMSUNG_PM) += pm.o
+obj-$(CONFIG_SAMSUNG_PM) += pm.o pm-common.o
obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o
-obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o
-obj-$(CONFIG_SAMSUNG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o
-obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o
diff --git a/arch/arm/mach-s3c24xx/Makefile.boot b/arch/arm/mach-s3c/Makefile.boot
similarity index 100%
rename from arch/arm/mach-s3c24xx/Makefile.boot
rename to arch/arm/mach-s3c/Makefile.boot
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c/Makefile.s3c24xx
similarity index 80%
rename from arch/arm/mach-s3c24xx/Makefile
rename to arch/arm/mach-s3c/Makefile.s3c24xx
index 6692f2d..3483ab3 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c/Makefile.s3c24xx
@@ -7,7 +7,10 @@
# core
-obj-y += common.o
+obj-y += s3c24xx.o
+obj-y += irq-s3c24xx.o
+obj-$(CONFIG_SPI_S3C24XX_FIQ) += irq-s3c24xx-fiq.o
+obj-$(CONFIG_SPI_S3C24XX_FIQ) += irq-s3c24xx-fiq-exports.o
obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
@@ -30,12 +33,12 @@
# PM
-obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_PM_SLEEP) += irq-pm.o sleep.o
+obj-$(CONFIG_PM) += pm-s3c24xx.o
+obj-$(CONFIG_PM_SLEEP) += irq-pm-s3c24xx.o sleep-s3c24xx.o
# common code
-obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
+obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += cpufreq-utils-s3c24xx.o
obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
@@ -80,7 +83,7 @@
# common bits of machine support
-obj-$(CONFIG_S3C24XX_SMDK) += common-smdk.o
+obj-$(CONFIG_S3C24XX_SMDK) += common-smdk-s3c24xx.o
obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO) += simtec-audio.o
obj-$(CONFIG_S3C24XX_SIMTEC_NOR) += simtec-nor.o
obj-$(CONFIG_S3C24XX_SIMTEC_PM) += simtec-pm.o
@@ -93,8 +96,7 @@
# device setup
-obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
-obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi.o
-obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o
-obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o
-obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o
+obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio-s3c24xx.o
+obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi-s3c24xx.o
+obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c-s3c24xx.o
+obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts-s3c24xx.o
diff --git a/arch/arm/mach-s3c/Makefile.s3c64xx b/arch/arm/mach-s3c/Makefile.s3c64xx
new file mode 100644
index 0000000..0c18e31
--- /dev/null
+++ b/arch/arm/mach-s3c/Makefile.s3c64xx
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright 2008 Openmoko, Inc.
+# Copyright 2008 Simtec Electronics
+
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
+# PM
+
+obj-$(CONFIG_PM) += pm-s3c64xx.o
+obj-$(CONFIG_PM_SLEEP) += sleep-s3c64xx.o
+obj-$(CONFIG_CPU_IDLE) += cpuidle-s3c64xx.o
+
+ifdef CONFIG_SAMSUNG_ATAGS
+
+obj-$(CONFIG_PM_SLEEP) += irq-pm-s3c64xx.o
+
+# Core
+
+obj-y += s3c64xx.o
+obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
+obj-$(CONFIG_CPU_S3C6410) += s3c6410.o
+
+# DMA support
+
+obj-$(CONFIG_S3C64XX_PL080) += pl080.o
+
+# Device support
+
+obj-y += dev-uart-s3c64xx.o
+obj-y += dev-audio-s3c64xx.o
+
+# Device setup
+
+obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp-s3c64xx.o
+obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0-s3c64xx.o
+obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1-s3c64xx.o
+obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide-s3c64xx.o
+obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad-s3c64xx.o
+obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio-s3c64xx.o
+obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi-s3c64xx.o
+obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy-s3c64xx.o
+
+obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight-s3c64xx.o
+
+# Machine support
+
+obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
+obj-$(CONFIG_MACH_HMT) += mach-hmt.o
+obj-$(CONFIG_MACH_MINI6410) += mach-mini6410.o
+obj-$(CONFIG_MACH_NCP) += mach-ncp.o
+obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o
+obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
+obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o
+obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
+obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
+obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
+obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
+endif
+
+obj-$(CONFIG_MACH_S3C64XX_DT) += mach-s3c64xx-dt.o
diff --git a/arch/arm/plat-samsung/include/plat/adc-core.h b/arch/arm/mach-s3c/adc-core.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/adc-core.h
rename to arch/arm/mach-s3c/adc-core.h
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/mach-s3c/adc.c
similarity index 97%
rename from arch/arm/plat-samsung/adc.c
rename to arch/arm/mach-s3c/adc.c
index ee3d5c9..0232520 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/mach-s3c/adc.c
@@ -19,8 +19,8 @@
#include <linux/io.h>
#include <linux/regulator/consumer.h>
-#include <plat/regs-adc.h>
-#include <plat/adc.h>
+#include "regs-adc.h"
+#include <linux/soc/samsung/s3c-adc.h>
/* This driver is designed to control the usage of the ADC block between
* the touchscreen and any other drivers that may need to use it, such as
@@ -40,7 +40,7 @@
TYPE_ADCV11, /* S3C2443 */
TYPE_ADCV12, /* S3C2416, S3C2450 */
TYPE_ADCV2, /* S3C64XX */
- TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
+ TYPE_ADCV3, /* S5PV210, S5PC110, Exynos4210 */
};
struct s3c_adc_client {
@@ -333,7 +333,6 @@
{
struct device *dev = &pdev->dev;
struct adc_device *adc;
- struct resource *regs;
enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
int ret;
unsigned tmp;
@@ -354,10 +353,8 @@
}
adc->irq = platform_get_irq(pdev, 1);
- if (adc->irq <= 0) {
- dev_err(dev, "failed to get adc irq\n");
+ if (adc->irq <= 0)
return -ENOENT;
- }
ret = devm_request_irq(dev, adc->irq, s3c_adc_irq, 0, dev_name(dev),
adc);
@@ -372,8 +369,7 @@
return PTR_ERR(adc->clk);
}
- regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- adc->regs = devm_ioremap_resource(dev, regs);
+ adc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(adc->regs))
return PTR_ERR(adc->regs);
diff --git a/arch/arm/mach-s3c24xx/anubis.h b/arch/arm/mach-s3c/anubis.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/anubis.h
rename to arch/arm/mach-s3c/anubis.h
diff --git a/arch/arm/mach-s3c64xx/ata-core.h b/arch/arm/mach-s3c/ata-core-s3c64xx.h
similarity index 77%
rename from arch/arm/mach-s3c64xx/ata-core.h
rename to arch/arm/mach-s3c/ata-core-s3c64xx.h
index 6d9a81f..4863ad9 100644
--- a/arch/arm/mach-s3c64xx/ata-core.h
+++ b/arch/arm/mach-s3c/ata-core-s3c64xx.h
@@ -6,8 +6,8 @@
* Samsung CF-ATA Controller core functions
*/
-#ifndef __ASM_PLAT_ATA_CORE_H
-#define __ASM_PLAT_ATA_CORE_H __FILE__
+#ifndef __ASM_PLAT_ATA_CORE_S3C64XX_H
+#define __ASM_PLAT_ATA_CORE_S3C64XX_H __FILE__
/* These functions are only for use with the core support code, such as
* the cpu specific initialisation code
@@ -21,4 +21,4 @@
#endif
}
-#endif /* __ASM_PLAT_ATA_CORE_H */
+#endif /* __ASM_PLAT_ATA_CORE_S3C64XX_H */
diff --git a/arch/arm/mach-s3c64xx/backlight.h b/arch/arm/mach-s3c/backlight-s3c64xx.h
similarity index 77%
rename from arch/arm/mach-s3c64xx/backlight.h
rename to arch/arm/mach-s3c/backlight-s3c64xx.h
index 028663f..2a2b358 100644
--- a/arch/arm/mach-s3c64xx/backlight.h
+++ b/arch/arm/mach-s3c/backlight-s3c64xx.h
@@ -4,8 +4,8 @@
* http://www.samsung.com
*/
-#ifndef __ASM_PLAT_BACKLIGHT_H
-#define __ASM_PLAT_BACKLIGHT_H __FILE__
+#ifndef __ASM_PLAT_BACKLIGHT_S3C64XX_H
+#define __ASM_PLAT_BACKLIGHT_S3C64XX_H __FILE__
/* samsung_bl_gpio_info - GPIO info for PWM Backlight control
* @no: GPIO number for PWM timer out
@@ -19,4 +19,4 @@
extern void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
struct platform_pwm_backlight_data *bl_data);
-#endif /* __ASM_PLAT_BACKLIGHT_H */
+#endif /* __ASM_PLAT_BACKLIGHT_S3C64XX_H */
diff --git a/arch/arm/mach-s3c24xx/bast-ide.c b/arch/arm/mach-s3c/bast-ide.c
similarity index 97%
rename from arch/arm/mach-s3c24xx/bast-ide.c
rename to arch/arm/mach-s3c/bast-ide.c
index 0679443..da64db1 100644
--- a/arch/arm/mach-s3c24xx/bast-ide.c
+++ b/arch/arm/mach-s3c/bast-ide.c
@@ -19,7 +19,8 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/map.h>
+#include "map.h"
+#include <mach/irqs.h>
#include "bast.h"
diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c/bast-irq.c
similarity index 94%
rename from arch/arm/mach-s3c24xx/bast-irq.c
rename to arch/arm/mach-s3c/bast-irq.c
index 0372805..d299f12 100644
--- a/arch/arm/mach-s3c24xx/bast-irq.c
+++ b/arch/arm/mach-s3c/bast-irq.c
@@ -15,8 +15,8 @@
#include <asm/mach-types.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/regs-irq.h>
+#include "regs-irq.h"
+#include <mach/irqs.h>
#include "bast.h"
@@ -62,7 +62,7 @@
static void
bast_pc104_maskack(struct irq_data *data)
{
- struct irq_desc *desc = irq_desc + BAST_IRQ_ISA;
+ struct irq_desc *desc = irq_to_desc(BAST_IRQ_ISA);
bast_pc104_mask(data);
desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -94,8 +94,6 @@
if (unlikely(stat == 0)) {
/* ack if we get an irq with nothing (ie, startup) */
-
- desc = irq_desc + BAST_IRQ_ISA;
desc->irq_data.chip->irq_ack(&desc->irq_data);
} else {
/* handle the IRQ */
diff --git a/arch/arm/mach-s3c24xx/bast.h b/arch/arm/mach-s3c/bast.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/bast.h
rename to arch/arm/mach-s3c/bast.h
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c/common-smdk-s3c24xx.c
similarity index 70%
rename from arch/arm/mach-s3c24xx/common-smdk.c
rename to arch/arm/mach-s3c/common-smdk-s3c24xx.c
index 58e30ca..f860d8b 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c/common-smdk-s3c24xx.c
@@ -14,6 +14,7 @@
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
+#include <linux/gpio/machine.h>
#include <linux/device.h>
#include <linux/platform_device.h>
@@ -28,45 +29,68 @@
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
#include <linux/platform_data/leds-s3c24xx.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-#include <plat/pm.h>
+#include "gpio-cfg.h"
+#include "devs.h"
+#include "pm.h"
-#include "common-smdk.h"
+#include "common-smdk-s3c24xx.h"
/* LED devices */
+static struct gpiod_lookup_table smdk_led4_gpio_table = {
+ .dev_id = "s3c24xx_led.0",
+ .table = {
+ GPIO_LOOKUP("GPF", 4, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table smdk_led5_gpio_table = {
+ .dev_id = "s3c24xx_led.1",
+ .table = {
+ GPIO_LOOKUP("GPF", 5, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table smdk_led6_gpio_table = {
+ .dev_id = "s3c24xx_led.2",
+ .table = {
+ GPIO_LOOKUP("GPF", 6, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table smdk_led7_gpio_table = {
+ .dev_id = "s3c24xx_led.3",
+ .table = {
+ GPIO_LOOKUP("GPF", 7, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
+ { },
+ },
+};
+
static struct s3c24xx_led_platdata smdk_pdata_led4 = {
- .gpio = S3C2410_GPF(4),
- .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.name = "led4",
.def_trigger = "timer",
};
static struct s3c24xx_led_platdata smdk_pdata_led5 = {
- .gpio = S3C2410_GPF(5),
- .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.name = "led5",
.def_trigger = "nand-disk",
};
static struct s3c24xx_led_platdata smdk_pdata_led6 = {
- .gpio = S3C2410_GPF(6),
- .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.name = "led6",
};
static struct s3c24xx_led_platdata smdk_pdata_led7 = {
- .gpio = S3C2410_GPF(7),
- .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.name = "led7",
};
@@ -166,7 +190,7 @@
.twrph1 = 20,
.nr_sets = ARRAY_SIZE(smdk_nand_sets),
.sets = smdk_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
/* devices we initialise */
@@ -179,27 +203,25 @@
&smdk_led7,
};
-static const struct gpio smdk_led_gpios[] = {
- { S3C2410_GPF(4), GPIOF_OUT_INIT_HIGH, NULL },
- { S3C2410_GPF(5), GPIOF_OUT_INIT_HIGH, NULL },
- { S3C2410_GPF(6), GPIOF_OUT_INIT_HIGH, NULL },
- { S3C2410_GPF(7), GPIOF_OUT_INIT_HIGH, NULL },
-};
-
void __init smdk_machine_init(void)
{
- /* Configure the LEDs (even if we have no LED support)*/
-
- int ret = gpio_request_array(smdk_led_gpios,
- ARRAY_SIZE(smdk_led_gpios));
- if (!WARN_ON(ret < 0))
- gpio_free_array(smdk_led_gpios, ARRAY_SIZE(smdk_led_gpios));
-
if (machine_is_smdk2443())
smdk_nand_info.twrph0 = 50;
s3c_nand_set_platdata(&smdk_nand_info);
+ /* Disable pull-up on the LED lines */
+ s3c_gpio_setpull(S3C2410_GPF(4), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPF(5), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPF(6), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPF(7), S3C_GPIO_PULL_NONE);
+
+ /* Add lookups for the lines */
+ gpiod_add_lookup_table(&smdk_led4_gpio_table);
+ gpiod_add_lookup_table(&smdk_led5_gpio_table);
+ gpiod_add_lookup_table(&smdk_led6_gpio_table);
+ gpiod_add_lookup_table(&smdk_led7_gpio_table);
+
platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
s3c_pm_init();
diff --git a/arch/arm/mach-s3c24xx/common-smdk.h b/arch/arm/mach-s3c/common-smdk-s3c24xx.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/common-smdk.h
rename to arch/arm/mach-s3c/common-smdk-s3c24xx.h
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/mach-s3c/cpu.c
similarity index 62%
rename from arch/arm/plat-samsung/cpu.c
rename to arch/arm/mach-s3c/cpu.c
index e1ba88b..6e97725 100644
--- a/arch/arm/plat-samsung/cpu.c
+++ b/arch/arm/mach-s3c/cpu.c
@@ -10,17 +10,10 @@
#include <linux/init.h>
#include <linux/io.h>
-#include <plat/map-base.h>
-#include <plat/cpu.h>
+#include <mach/map-base.h>
+#include "cpu.h"
unsigned long samsung_cpu_id;
-static unsigned int samsung_cpu_rev;
-
-unsigned int samsung_rev(void)
-{
- return samsung_cpu_rev;
-}
-EXPORT_SYMBOL(samsung_rev);
void __init s3c64xx_init_cpu(void)
{
@@ -34,15 +27,5 @@
samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C);
}
- samsung_cpu_rev = 0;
-
- pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);
-}
-
-void __init s5p_init_cpu(const void __iomem *cpuid_addr)
-{
- samsung_cpu_id = readl_relaxed(cpuid_addr);
- samsung_cpu_rev = samsung_cpu_id & 0xFF;
-
pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);
}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/mach-s3c/cpu.h
similarity index 89%
rename from arch/arm/plat-samsung/include/plat/cpu.h
rename to arch/arm/mach-s3c/cpu.h
index fadcddb..20ff98d 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/mach-s3c/cpu.h
@@ -109,9 +109,6 @@
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
extern void s3c64xx_init_cpu(void);
-extern void s5p_init_cpu(const void __iomem *cpuid_addr);
-
-extern unsigned int samsung_rev(void);
extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
@@ -126,15 +123,6 @@
extern struct syscore_ops s3c2416_pm_syscore_ops;
extern struct syscore_ops s3c244x_pm_syscore_ops;
-/* system device subsystems */
-
-extern struct bus_type s3c2410_subsys;
-extern struct bus_type s3c2410a_subsys;
-extern struct bus_type s3c2412_subsys;
-extern struct bus_type s3c2416_subsys;
-extern struct bus_type s3c2440_subsys;
-extern struct bus_type s3c2442_subsys;
-extern struct bus_type s3c2443_subsys;
extern struct bus_type s3c6410_subsys;
#endif
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c
similarity index 68%
rename from arch/arm/mach-s3c24xx/cpufreq-utils.c
rename to arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c
index 1a7f38d..c1784d8 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c
@@ -12,12 +12,12 @@
#include <linux/io.h>
#include <linux/clk.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
+#include "map.h"
+#include "regs-clock.h"
-#include <plat/cpu-freq-core.h>
+#include <linux/soc/samsung/s3c-cpufreq-core.h>
-#include "regs-mem.h"
+#include "regs-mem-s3c24xx.h"
/**
* s3c2410_cpufreq_setrefresh - set SDRAM refresh value
@@ -60,3 +60,35 @@
if (!IS_ERR(cfg->mpll))
clk_set_rate(cfg->mpll, cfg->pll.frequency);
}
+
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
+u32 s3c2440_read_camdivn(void)
+{
+ return __raw_readl(S3C2440_CAMDIVN);
+}
+
+void s3c2440_write_camdivn(u32 camdiv)
+{
+ __raw_writel(camdiv, S3C2440_CAMDIVN);
+}
+#endif
+
+u32 s3c24xx_read_clkdivn(void)
+{
+ return __raw_readl(S3C2410_CLKDIVN);
+}
+
+void s3c24xx_write_clkdivn(u32 clkdiv)
+{
+ __raw_writel(clkdiv, S3C2410_CLKDIVN);
+}
+
+u32 s3c24xx_read_mpllcon(void)
+{
+ return __raw_readl(S3C2410_MPLLCON);
+}
+
+void s3c24xx_write_locktime(u32 locktime)
+{
+ return __raw_writel(locktime, S3C2410_LOCKTIME);
+}
diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c/cpuidle-s3c64xx.c
similarity index 91%
rename from arch/arm/mach-s3c64xx/cpuidle.c
rename to arch/arm/mach-s3c/cpuidle-s3c64xx.c
index 0bac6f6..b1c5f43 100644
--- a/arch/arm/mach-s3c64xx/cpuidle.c
+++ b/arch/arm/mach-s3c/cpuidle-s3c64xx.c
@@ -13,11 +13,11 @@
#include <asm/cpuidle.h>
-#include <plat/cpu.h>
-#include <mach/map.h>
+#include "cpu.h"
+#include "map.h"
-#include "regs-sys.h"
-#include "regs-syscon-power.h"
+#include "regs-sys-s3c64xx.h"
+#include "regs-syscon-power-s3c64xx.h"
static int s3c64xx_enter_idle(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
diff --git a/arch/arm/mach-s3c64xx/crag6410.h b/arch/arm/mach-s3c/crag6410.h
similarity index 94%
rename from arch/arm/mach-s3c64xx/crag6410.h
rename to arch/arm/mach-s3c/crag6410.h
index 00d9aa1..f39ea2c 100644
--- a/arch/arm/mach-s3c64xx/crag6410.h
+++ b/arch/arm/mach-s3c/crag6410.h
@@ -8,7 +8,7 @@
#ifndef MACH_CRAG6410_H
#define MACH_CRAG6410_H
-#include <mach/gpio-samsung.h>
+#include "gpio-samsung.h"
#define GLENFARCLAS_PMIC_IRQ_BASE IRQ_BOARD_START
#define BANFF_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c/dev-audio-s3c64xx.c
similarity index 96%
rename from arch/arm/mach-s3c64xx/dev-audio.c
rename to arch/arm/mach-s3c/dev-audio-s3c64xx.c
index e3c49b5..fc2f077 100644
--- a/arch/arm/mach-s3c64xx/dev-audio.c
+++ b/arch/arm/mach-s3c/dev-audio-s3c64xx.c
@@ -11,13 +11,12 @@
#include <linux/export.h>
#include <mach/irqs.h>
-#include <mach/map.h>
-#include <mach/dma.h>
+#include "map.h"
-#include <plat/devs.h>
+#include "devs.h"
#include <linux/platform_data/asoc-s3c.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
+#include "gpio-cfg.h"
+#include "gpio-samsung.h"
static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
{
diff --git a/arch/arm/mach-s3c64xx/dev-backlight.c b/arch/arm/mach-s3c/dev-backlight-s3c64xx.c
similarity index 94%
rename from arch/arm/mach-s3c64xx/dev-backlight.c
rename to arch/arm/mach-s3c/dev-backlight-s3c64xx.c
index 799cfdf..65488b6 100644
--- a/arch/arm/mach-s3c64xx/dev-backlight.c
+++ b/arch/arm/mach-s3c/dev-backlight-s3c64xx.c
@@ -11,10 +11,10 @@
#include <linux/io.h>
#include <linux/pwm_backlight.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
+#include "devs.h"
+#include "gpio-cfg.h"
-#include "backlight.h"
+#include "backlight-s3c64xx.h"
struct samsung_bl_drvdata {
struct platform_pwm_backlight_data plat_data;
@@ -65,7 +65,6 @@
.plat_data = {
.max_brightness = 255,
.dft_brightness = 255,
- .enable_gpio = -1,
.init = samsung_bl_init,
.exit = samsung_bl_exit,
},
@@ -111,8 +110,6 @@
samsung_bl_data->dft_brightness = bl_data->dft_brightness;
if (bl_data->lth_brightness)
samsung_bl_data->lth_brightness = bl_data->lth_brightness;
- if (bl_data->enable_gpio >= 0)
- samsung_bl_data->enable_gpio = bl_data->enable_gpio;
if (bl_data->init)
samsung_bl_data->init = bl_data->init;
if (bl_data->notify)
diff --git a/arch/arm/mach-s3c64xx/dev-uart.c b/arch/arm/mach-s3c/dev-uart-s3c64xx.c
similarity index 94%
rename from arch/arm/mach-s3c64xx/dev-uart.c
rename to arch/arm/mach-s3c/dev-uart-s3c64xx.c
index 5fb59ad..8288e8d 100644
--- a/arch/arm/mach-s3c64xx/dev-uart.c
+++ b/arch/arm/mach-s3c/dev-uart-s3c64xx.c
@@ -15,11 +15,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
+#include "map.h"
#include <mach/irqs.h>
-#include <plat/devs.h>
+#include "devs.h"
/* Serial port registrations */
diff --git a/arch/arm/plat-samsung/dev-uart.c b/arch/arm/mach-s3c/dev-uart.c
similarity index 96%
rename from arch/arm/plat-samsung/dev-uart.c
rename to arch/arm/mach-s3c/dev-uart.c
index 7476a5d..3d1f7f2 100644
--- a/arch/arm/plat-samsung/dev-uart.c
+++ b/arch/arm/mach-s3c/dev-uart.c
@@ -10,7 +10,7 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
-#include <plat/devs.h>
+#include "devs.h"
/* uart devices */
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/mach-s3c/devs.c
similarity index 95%
rename from arch/arm/plat-samsung/devs.c
rename to arch/arm/mach-s3c/devs.c
index 1d1fa06..06dec64 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/mach-s3c/devs.c
@@ -3,8 +3,9 @@
// Copyright (c) 2011 Samsung Electronics Co., Ltd.
// http://www.samsung.com
//
-// Base SAMSUNG platform device definitions
+// Base Samsung platform device definitions
+#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
@@ -37,28 +38,32 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/dma.h>
#include <mach/irqs.h>
-#include <mach/map.h>
+#include "map.h"
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/adc.h>
+#ifdef CONFIG_PLAT_S3C24XX
+#include "regs-s3c2443-clock.h"
+#endif /* CONFIG_PLAT_S3C24XX */
+
+#include "cpu.h"
+#include "devs.h"
+#include <linux/soc/samsung/s3c-adc.h>
#include <linux/platform_data/ata-samsung_cf.h>
-#include <plat/fb.h>
-#include <plat/fb-s3c2410.h>
+#include "fb.h"
+#include <linux/platform_data/fb-s3c2410.h>
#include <linux/platform_data/hwmon-s3c.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/keypad.h>
+#include "keypad.h"
#include <linux/platform_data/mmc-s3cmci.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/pwm-core.h>
-#include <plat/sdhci.h>
+#include "pwm-core.h"
+#include "sdhci.h"
#include <linux/platform_data/touchscreen-s3c2410.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <linux/platform_data/usb-ohci-s3c2410.h>
-#include <plat/usb-phy.h>
-#include <plat/regs-spi.h>
+#include "usb-phy.h"
#include <linux/platform_data/asoc-s3c.h>
#include <linux/platform_data/spi-s3c64xx.h>
@@ -833,16 +838,42 @@
/* SDI */
#ifdef CONFIG_PLAT_S3C24XX
+void s3c24xx_mci_def_set_power(unsigned char power_mode, unsigned short vdd)
+{
+ switch (power_mode) {
+ case MMC_POWER_ON:
+ case MMC_POWER_UP:
+ /* Configure GPE5...GPE10 pins in SD mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
+ break;
+
+ case MMC_POWER_OFF:
+ default:
+ gpio_direction_output(S3C2410_GPE(5), 0);
+ break;
+ }
+}
+
static struct resource s3c_sdi_resource[] = {
[0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
[1] = DEFINE_RES_IRQ(IRQ_SDI),
};
+static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
+ /* This is currently here to avoid a number of if (host->pdata)
+ * checks. Any zero fields to ensure reasonable defaults are picked. */
+ .no_wprotect = 1,
+ .no_detect = 1,
+ .set_power = s3c24xx_mci_def_set_power,
+};
+
struct platform_device s3c_device_sdi = {
.name = "s3c2410-sdi",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_sdi_resource),
.resource = s3c_sdi_resource,
+ .dev.platform_data = &s3cmci_def_pdata,
};
void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
@@ -1010,9 +1041,9 @@
npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_usb_hsotg);
if (!npd->phy_init)
- npd->phy_init = s5p_usb_phy_init;
+ npd->phy_init = s3c_usb_phy_init;
if (!npd->phy_exit)
- npd->phy_exit = s5p_usb_phy_exit;
+ npd->phy_exit = s3c_usb_phy_exit;
}
#endif /* CONFIG_S3C_DEV_USB_HSOTG */
@@ -1038,6 +1069,8 @@
void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
{
s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
+ pd->phy_init = s3c_hsudc_init_phy;
+ pd->phy_uninit = s3c_hsudc_uninit_phy;
}
#endif /* CONFIG_PLAT_S3C24XX */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/mach-s3c/devs.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/devs.h
rename to arch/arm/mach-s3c/devs.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c/dma-s3c24xx.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/include/mach/dma.h
rename to arch/arm/mach-s3c/dma-s3c24xx.h
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c/dma-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/include/mach/dma.h
rename to arch/arm/mach-s3c/dma-s3c64xx.h
diff --git a/arch/arm/mach-s3c/dma.h b/arch/arm/mach-s3c/dma.h
new file mode 100644
index 0000000..59a4578
--- /dev/null
+++ b/arch/arm/mach-s3c/dma.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_ARCH_S3C24XX
+#include "dma-s3c24xx.h"
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+#include "dma-s3c64xx.h"
+#endif
diff --git a/arch/arm/mach-s3c24xx/fb-core.h b/arch/arm/mach-s3c/fb-core-s3c24xx.h
similarity index 78%
rename from arch/arm/mach-s3c24xx/fb-core.h
rename to arch/arm/mach-s3c/fb-core-s3c24xx.h
index 1821e82..0e07f3b 100644
--- a/arch/arm/mach-s3c24xx/fb-core.h
+++ b/arch/arm/mach-s3c/fb-core-s3c24xx.h
@@ -5,8 +5,8 @@
*
* Samsung framebuffer driver core functions
*/
-#ifndef __ASM_PLAT_FB_CORE_H
-#define __ASM_PLAT_FB_CORE_H __FILE__
+#ifndef __ASM_PLAT_FB_CORE_S3C24XX_H
+#define __ASM_PLAT_FB_CORE_S3C24XX_H __FILE__
/*
* These functions are only for use with the core support code, such as
@@ -21,4 +21,4 @@
#endif
}
-#endif /* __ASM_PLAT_FB_CORE_H */
+#endif /* __ASM_PLAT_FB_CORE_S3C24XX_H */
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/mach-s3c/fb.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/fb.h
rename to arch/arm/mach-s3c/fb.h
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/mach-s3c/gpio-cfg-helpers.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
rename to arch/arm/mach-s3c/gpio-cfg-helpers.h
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/mach-s3c/gpio-cfg.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/gpio-cfg.h
rename to arch/arm/mach-s3c/gpio-cfg.h
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/mach-s3c/gpio-core.h
similarity index 98%
rename from arch/arm/plat-samsung/include/plat/gpio-core.h
rename to arch/arm/mach-s3c/gpio-core.h
index c0bfceb..b361c8c 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/mach-s3c/gpio-core.h
@@ -11,7 +11,7 @@
#define __PLAT_SAMSUNG_GPIO_CORE_H
/* Bring in machine-local definitions, especially S3C_GPIO_END */
-#include <mach/gpio-samsung.h>
+#include "gpio-samsung.h"
#include <linux/gpio/driver.h>
#define GPIOCON_OFF (0x00)
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h b/arch/arm/mach-s3c/gpio-samsung-s3c24xx.h
similarity index 98%
rename from arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h
rename to arch/arm/mach-s3c/gpio-samsung-s3c24xx.h
index 2ad22b2..c29fdc9 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h
+++ b/arch/arm/mach-s3c/gpio-samsung-s3c24xx.h
@@ -14,6 +14,8 @@
#ifndef GPIO_SAMSUNG_S3C24XX_H
#define GPIO_SAMSUNG_S3C24XX_H
+#include "map.h"
+
/*
* GPIO sizes for various SoCs:
*
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-samsung.h b/arch/arm/mach-s3c/gpio-samsung-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/include/mach/gpio-samsung.h
rename to arch/arm/mach-s3c/gpio-samsung-s3c64xx.h
diff --git a/arch/arm/plat-samsung/gpio-samsung.c b/arch/arm/mach-s3c/gpio-samsung.c
similarity index 98%
rename from arch/arm/plat-samsung/gpio-samsung.c
rename to arch/arm/mach-s3c/gpio-samsung.c
index f66c820..76ef415 100644
--- a/arch/arm/plat-samsung/gpio-samsung.c
+++ b/arch/arm/mach-s3c/gpio-samsung.c
@@ -8,7 +8,7 @@
// Ben Dooks <ben@simtec.co.uk>
// http://armlinux.simtec.co.uk/
//
-// SAMSUNG - GPIOlib support
+// Samsung - GPIOlib support
#include <linux/kernel.h>
#include <linux/irq.h>
@@ -27,15 +27,15 @@
#include <asm/irq.h>
#include <mach/irqs.h>
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "map.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include <plat/cpu.h>
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-#include <plat/pm.h>
+#include "cpu.h"
+#include "gpio-core.h"
+#include "gpio-cfg.h"
+#include "gpio-cfg-helpers.h"
+#include "pm.h"
int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
unsigned int off, samsung_gpio_pull_t pull)
diff --git a/arch/arm/mach-s3c/gpio-samsung.h b/arch/arm/mach-s3c/gpio-samsung.h
new file mode 100644
index 0000000..02f6f4a
--- /dev/null
+++ b/arch/arm/mach-s3c/gpio-samsung.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_ARCH_S3C24XX
+#include "gpio-samsung-s3c24xx.h"
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+#include "gpio-samsung-s3c64xx.h"
+#endif
diff --git a/arch/arm/mach-s3c24xx/gta02.h b/arch/arm/mach-s3c/gta02.h
similarity index 94%
rename from arch/arm/mach-s3c24xx/gta02.h
rename to arch/arm/mach-s3c/gta02.h
index d5610ba..043ae38 100644
--- a/arch/arm/mach-s3c24xx/gta02.h
+++ b/arch/arm/mach-s3c/gta02.h
@@ -6,7 +6,7 @@
#ifndef __MACH_S3C24XX_GTA02_H
#define __MACH_S3C24XX_GTA02_H __FILE__
-#include <mach/regs-gpio.h>
+#include "regs-gpio.h"
#define GTA02_GPIO_AUX_LED S3C2410_GPB(2)
#define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9)
diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c/h1940-bluetooth.c
similarity index 96%
rename from arch/arm/mach-s3c24xx/h1940-bluetooth.c
rename to arch/arm/mach-s3c/h1940-bluetooth.c
index 186b532..59edcf8 100644
--- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c/h1940-bluetooth.c
@@ -13,10 +13,9 @@
#include <linux/gpio.h>
#include <linux/rfkill.h>
-#include <plat/gpio-cfg.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "gpio-cfg.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
#include "h1940.h"
diff --git a/arch/arm/mach-s3c24xx/h1940.h b/arch/arm/mach-s3c/h1940.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/h1940.h
rename to arch/arm/mach-s3c/h1940.h
diff --git a/arch/arm/mach-s3c/hardware-s3c24xx.h b/arch/arm/mach-s3c/hardware-s3c24xx.h
new file mode 100644
index 0000000..33b3746
--- /dev/null
+++ b/arch/arm/mach-s3c/hardware-s3c24xx.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2003 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - hardware
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_S3C24XX_H
+#define __ASM_ARCH_HARDWARE_S3C24XX_H
+
+extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
+
+#endif /* __ASM_ARCH_HARDWARE_S3C24XX_H */
diff --git a/arch/arm/plat-samsung/include/plat/iic-core.h b/arch/arm/mach-s3c/iic-core.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/iic-core.h
rename to arch/arm/mach-s3c/iic-core.h
diff --git a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h b/arch/arm/mach-s3c/include/mach/io-s3c24xx.h
new file mode 100644
index 0000000..738b775
--- /dev/null
+++ b/arch/arm/mach-s3c/include/mach/io-s3c24xx.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * arch/arm/mach-s3c2410/include/mach/io.h
+ * from arch/arm/mach-rpc/include/mach/io.h
+ *
+ * Copyright (C) 1997 Russell King
+ * (C) 2003 Simtec Electronics
+*/
+
+#ifndef __ASM_ARM_ARCH_IO_S3C24XX_H
+#define __ASM_ARM_ARCH_IO_S3C24XX_H
+
+#include <mach/map-base.h>
+
+/*
+ * ISA style IO, for each machine to sort out mappings for,
+ * if it implements it. We reserve two 16M regions for ISA,
+ * so the PC/104 can use separate addresses for 8-bit and
+ * 16-bit port I/O.
+ */
+#define PCIO_BASE S3C_ADDR(0x02000000)
+#define IO_SPACE_LIMIT 0x00ffffff
+#define S3C24XX_VA_ISA_WORD (PCIO_BASE)
+#define S3C24XX_VA_ISA_BYTE (PCIO_BASE + 0x01000000)
+
+#ifdef CONFIG_ISA
+
+#define inb(p) readb(S3C24XX_VA_ISA_BYTE + (p))
+#define inw(p) readw(S3C24XX_VA_ISA_WORD + (p))
+#define inl(p) readl(S3C24XX_VA_ISA_WORD + (p))
+
+#define outb(v,p) writeb((v), S3C24XX_VA_ISA_BYTE + (p))
+#define outw(v,p) writew((v), S3C24XX_VA_ISA_WORD + (p))
+#define outl(v,p) writel((v), S3C24XX_VA_ISA_WORD + (p))
+
+#define insb(p,d,l) readsb(S3C24XX_VA_ISA_BYTE + (p),d,l)
+#define insw(p,d,l) readsw(S3C24XX_VA_ISA_WORD + (p),d,l)
+#define insl(p,d,l) readsl(S3C24XX_VA_ISA_WORD + (p),d,l)
+
+#define outsb(p,d,l) writesb(S3C24XX_VA_ISA_BYTE + (p),d,l)
+#define outsw(p,d,l) writesw(S3C24XX_VA_ISA_WORD + (p),d,l)
+#define outsl(p,d,l) writesl(S3C24XX_VA_ISA_WORD + (p),d,l)
+
+#else
+
+#define __io(x) (PCIO_BASE + (x))
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-s3c/include/mach/io.h b/arch/arm/mach-s3c/include/mach/io.h
new file mode 100644
index 0000000..30a0135
--- /dev/null
+++ b/arch/arm/mach-s3c/include/mach/io.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 Krzysztof Kozlowski <krzk@kernel.org>
+ */
+
+#ifdef CONFIG_ARCH_S3C24XX
+#include "io-s3c24xx.h"
+#endif
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/include/mach/irqs.h
rename to arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/include/mach/irqs.h
rename to arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h
diff --git a/arch/arm/mach-s3c/include/mach/irqs.h b/arch/arm/mach-s3c/include/mach/irqs.h
new file mode 100644
index 0000000..0bff1c1
--- /dev/null
+++ b/arch/arm/mach-s3c/include/mach/irqs.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_ARCH_S3C24XX
+#include "irqs-s3c24xx.h"
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+#include "irqs-s3c64xx.h"
+#endif
diff --git a/arch/arm/plat-samsung/include/plat/map-base.h b/arch/arm/mach-s3c/include/mach/map-base.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/map-base.h
rename to arch/arm/mach-s3c/include/mach/map-base.h
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/mach-s3c/init.c
similarity index 98%
rename from arch/arm/plat-samsung/init.c
rename to arch/arm/mach-s3c/init.c
index e9acf02..9d92f03 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/mach-s3c/init.c
@@ -23,8 +23,8 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
+#include "cpu.h"
+#include "devs.h"
static struct cpu_table *cpu;
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c b/arch/arm/mach-s3c/iotiming-s3c2410.c
similarity index 97%
rename from arch/arm/mach-s3c24xx/iotiming-s3c2410.c
rename to arch/arm/mach-s3c/iotiming-s3c2410.c
index 9f90aaf..28d9f47 100644
--- a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
+++ b/arch/arm/mach-s3c/iotiming-s3c2410.c
@@ -14,12 +14,12 @@
#include <linux/io.h>
#include <linux/slab.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
+#include "map.h"
+#include "regs-clock.h"
-#include <plat/cpu-freq-core.h>
+#include <linux/soc/samsung/s3c-cpufreq-core.h>
-#include "regs-mem.h"
+#include "regs-mem-s3c24xx.h"
#define print_ns(x) ((x) / 10), ((x) % 10)
@@ -129,7 +129,7 @@
return 0;
}
-int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
+static int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
{
/* Currently no support for Tacp calculations. */
return 0;
@@ -288,8 +288,8 @@
* Given the BANKCON setting in @bt and the current frequency settings
* in @cfg, update the cycle timing information.
*/
-void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
- struct s3c2410_iobank_timing *bt)
+static void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
+ struct s3c2410_iobank_timing *bt)
{
unsigned long bankcon = bt->bankcon;
unsigned long hclk = cfg->freq.hclk_tns;
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c/iotiming-s3c2412.c
similarity index 98%
rename from arch/arm/mach-s3c24xx/iotiming-s3c2412.c
rename to arch/arm/mach-s3c/iotiming-s3c2412.c
index 59356d1..003f89c 100644
--- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
+++ b/arch/arm/mach-s3c/iotiming-s3c2412.c
@@ -23,10 +23,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <plat/cpu.h>
-#include <plat/cpu-freq-core.h>
+#include "cpu.h"
+#include <linux/soc/samsung/s3c-cpufreq-core.h>
-#include <mach/s3c2412.h>
+#include "s3c2412.h"
#define print_ns(x) ((x) / 10), ((x) % 10)
diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c/irq-pm-s3c24xx.c
similarity index 92%
rename from arch/arm/mach-s3c24xx/irq-pm.c
rename to arch/arm/mach-s3c/irq-pm-s3c24xx.c
index e0131b1..4d5e283 100644
--- a/arch/arm/mach-s3c24xx/irq-pm.c
+++ b/arch/arm/mach-s3c/irq-pm-s3c24xx.c
@@ -13,14 +13,14 @@
#include <linux/syscore_ops.h>
#include <linux/io.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/map-base.h>
-#include <plat/map-s3c.h>
+#include "cpu.h"
+#include "pm.h"
+#include <mach/map-base.h>
+#include "map-s3c.h"
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-#include <mach/pm-core.h>
+#include "regs-irq.h"
+#include "regs-gpio.h"
+#include "pm-core.h"
#include <asm/irq.h>
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c/irq-pm-s3c64xx.c
similarity index 96%
rename from arch/arm/mach-s3c64xx/irq-pm.c
rename to arch/arm/mach-s3c/irq-pm-s3c64xx.c
index 31b2211..4a1e935 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c/irq-pm-s3c64xx.c
@@ -20,11 +20,11 @@
#include <linux/io.h>
#include <linux/of.h>
-#include <mach/map.h>
+#include "map.h"
-#include <mach/regs-gpio.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
+#include "regs-gpio.h"
+#include "cpu.h"
+#include "pm.h"
/* We handled all the IRQ types in this code, to save having to make several
* small files to handle each different type separately. Having the EINT_GRP
diff --git a/arch/arm/mach-s3c/irq-s3c24xx-fiq-exports.c b/arch/arm/mach-s3c/irq-s3c24xx-fiq-exports.c
new file mode 100644
index 0000000..84cf863
--- /dev/null
+++ b/arch/arm/mach-s3c/irq-s3c24xx-fiq-exports.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/stddef.h>
+#include <linux/export.h>
+#include <linux/spi/s3c24xx-fiq.h>
+
+EXPORT_SYMBOL(s3c24xx_spi_fiq_rx);
+EXPORT_SYMBOL(s3c24xx_spi_fiq_txrx);
+EXPORT_SYMBOL(s3c24xx_spi_fiq_tx);
diff --git a/arch/arm/mach-s3c/irq-s3c24xx-fiq.S b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S
new file mode 100644
index 0000000..5d238d9
--- /dev/null
+++ b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* linux/drivers/spi/spi_s3c24xx_fiq.S
+ *
+ * Copyright 2009 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX SPI - FIQ pseudo-DMA transfer code
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#include "map.h"
+#include "regs-irq.h"
+
+#include <linux/spi/s3c24xx-fiq.h>
+
+#define S3C2410_SPTDAT (0x10)
+#define S3C2410_SPRDAT (0x14)
+
+ .text
+
+ @ entry to these routines is as follows, with the register names
+ @ defined in fiq.h so that they can be shared with the C files which
+ @ setup the calling registers.
+ @
+ @ fiq_rirq The base of the IRQ registers to find S3C2410_SRCPND
+ @ fiq_rtmp Temporary register to hold tx/rx data
+ @ fiq_rspi The base of the SPI register block
+ @ fiq_rtx The tx buffer pointer
+ @ fiq_rrx The rx buffer pointer
+ @ fiq_rcount The number of bytes to move
+
+ @ each entry starts with a word entry of how long it is
+ @ and an offset to the irq acknowledgment word
+
+ENTRY(s3c24xx_spi_fiq_rx)
+ .word fiq_rx_end - fiq_rx_start
+ .word fiq_rx_irq_ack - fiq_rx_start
+fiq_rx_start:
+ ldr fiq_rtmp, fiq_rx_irq_ack
+ str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
+
+ ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
+ strb fiq_rtmp, [ fiq_rrx ], #1
+
+ mov fiq_rtmp, #0xff
+ strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
+
+ subs fiq_rcount, fiq_rcount, #1
+ subsne pc, lr, #4 @@ return, still have work to do
+
+ @@ set IRQ controller so that next op will trigger IRQ
+ mov fiq_rtmp, #0
+ str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
+ subs pc, lr, #4
+
+fiq_rx_irq_ack:
+ .word 0
+fiq_rx_end:
+
+ENTRY(s3c24xx_spi_fiq_txrx)
+ .word fiq_txrx_end - fiq_txrx_start
+ .word fiq_txrx_irq_ack - fiq_txrx_start
+fiq_txrx_start:
+
+ ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
+ strb fiq_rtmp, [ fiq_rrx ], #1
+
+ ldr fiq_rtmp, fiq_txrx_irq_ack
+ str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
+
+ ldrb fiq_rtmp, [ fiq_rtx ], #1
+ strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
+
+ subs fiq_rcount, fiq_rcount, #1
+ subsne pc, lr, #4 @@ return, still have work to do
+
+ mov fiq_rtmp, #0
+ str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
+ subs pc, lr, #4
+
+fiq_txrx_irq_ack:
+ .word 0
+
+fiq_txrx_end:
+
+ENTRY(s3c24xx_spi_fiq_tx)
+ .word fiq_tx_end - fiq_tx_start
+ .word fiq_tx_irq_ack - fiq_tx_start
+fiq_tx_start:
+ ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
+
+ ldr fiq_rtmp, fiq_tx_irq_ack
+ str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
+
+ ldrb fiq_rtmp, [ fiq_rtx ], #1
+ strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
+
+ subs fiq_rcount, fiq_rcount, #1
+ subsne pc, lr, #4 @@ return, still have work to do
+
+ mov fiq_rtmp, #0
+ str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
+ subs pc, lr, #4
+
+fiq_tx_irq_ack:
+ .word 0
+
+fiq_tx_end:
+
+ .end
diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c
new file mode 100644
index 0000000..19fb9bd
--- /dev/null
+++ b/arch/arm/mach-s3c/irq-s3c24xx.c
@@ -0,0 +1,1351 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * S3C24XX IRQ handling
+ *
+ * Copyright (c) 2003-2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
+*/
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
+
+#include <mach/irqs.h>
+#include "regs-irq.h"
+#include "regs-gpio.h"
+
+#include "cpu.h"
+#include "regs-irqtype.h"
+#include "pm.h"
+
+#define S3C_IRQTYPE_NONE 0
+#define S3C_IRQTYPE_EINT 1
+#define S3C_IRQTYPE_EDGE 2
+#define S3C_IRQTYPE_LEVEL 3
+
+struct s3c_irq_data {
+ unsigned int type;
+ unsigned long offset;
+ unsigned long parent_irq;
+
+ /* data gets filled during init */
+ struct s3c_irq_intc *intc;
+ unsigned long sub_bits;
+ struct s3c_irq_intc *sub_intc;
+};
+
+/*
+ * Structure holding the controller data
+ * @reg_pending register holding pending irqs
+ * @reg_intpnd special register intpnd in main intc
+ * @reg_mask mask register
+ * @domain irq_domain of the controller
+ * @parent parent controller for ext and sub irqs
+ * @irqs irq-data, always s3c_irq_data[32]
+ */
+struct s3c_irq_intc {
+ void __iomem *reg_pending;
+ void __iomem *reg_intpnd;
+ void __iomem *reg_mask;
+ struct irq_domain *domain;
+ struct s3c_irq_intc *parent;
+ struct s3c_irq_data *irqs;
+};
+
+/*
+ * Array holding pointers to the global controller structs
+ * [0] ... main_intc
+ * [1] ... sub_intc
+ * [2] ... main_intc2 on s3c2416
+ */
+static struct s3c_irq_intc *s3c_intc[3];
+
+static void s3c_irq_mask(struct irq_data *data)
+{
+ struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
+ struct s3c_irq_intc *intc = irq_data->intc;
+ struct s3c_irq_intc *parent_intc = intc->parent;
+ struct s3c_irq_data *parent_data;
+ unsigned long mask;
+ unsigned int irqno;
+
+ mask = readl_relaxed(intc->reg_mask);
+ mask |= (1UL << irq_data->offset);
+ writel_relaxed(mask, intc->reg_mask);
+
+ if (parent_intc) {
+ parent_data = &parent_intc->irqs[irq_data->parent_irq];
+
+ /* check to see if we need to mask the parent IRQ
+ * The parent_irq is always in main_intc, so the hwirq
+ * for find_mapping does not need an offset in any case.
+ */
+ if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
+ irqno = irq_find_mapping(parent_intc->domain,
+ irq_data->parent_irq);
+ s3c_irq_mask(irq_get_irq_data(irqno));
+ }
+ }
+}
+
+static void s3c_irq_unmask(struct irq_data *data)
+{
+ struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
+ struct s3c_irq_intc *intc = irq_data->intc;
+ struct s3c_irq_intc *parent_intc = intc->parent;
+ unsigned long mask;
+ unsigned int irqno;
+
+ mask = readl_relaxed(intc->reg_mask);
+ mask &= ~(1UL << irq_data->offset);
+ writel_relaxed(mask, intc->reg_mask);
+
+ if (parent_intc) {
+ irqno = irq_find_mapping(parent_intc->domain,
+ irq_data->parent_irq);
+ s3c_irq_unmask(irq_get_irq_data(irqno));
+ }
+}
+
+static inline void s3c_irq_ack(struct irq_data *data)
+{
+ struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
+ struct s3c_irq_intc *intc = irq_data->intc;
+ unsigned long bitval = 1UL << irq_data->offset;
+
+ writel_relaxed(bitval, intc->reg_pending);
+ if (intc->reg_intpnd)
+ writel_relaxed(bitval, intc->reg_intpnd);
+}
+
+static int s3c_irq_type(struct irq_data *data, unsigned int type)
+{
+ switch (type) {
+ case IRQ_TYPE_NONE:
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ case IRQ_TYPE_EDGE_FALLING:
+ case IRQ_TYPE_EDGE_BOTH:
+ irq_set_handler(data->irq, handle_edge_irq);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ case IRQ_TYPE_LEVEL_HIGH:
+ irq_set_handler(data->irq, handle_level_irq);
+ break;
+ default:
+ pr_err("No such irq type %d\n", type);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int s3c_irqext_type_set(void __iomem *gpcon_reg,
+ void __iomem *extint_reg,
+ unsigned long gpcon_offset,
+ unsigned long extint_offset,
+ unsigned int type)
+{
+ unsigned long newvalue = 0, value;
+
+ /* Set the GPIO to external interrupt mode */
+ value = readl_relaxed(gpcon_reg);
+ value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
+ writel_relaxed(value, gpcon_reg);
+
+ /* Set the external interrupt to pointed trigger type */
+ switch (type)
+ {
+ case IRQ_TYPE_NONE:
+ pr_warn("No edge setting!\n");
+ break;
+
+ case IRQ_TYPE_EDGE_RISING:
+ newvalue = S3C2410_EXTINT_RISEEDGE;
+ break;
+
+ case IRQ_TYPE_EDGE_FALLING:
+ newvalue = S3C2410_EXTINT_FALLEDGE;
+ break;
+
+ case IRQ_TYPE_EDGE_BOTH:
+ newvalue = S3C2410_EXTINT_BOTHEDGE;
+ break;
+
+ case IRQ_TYPE_LEVEL_LOW:
+ newvalue = S3C2410_EXTINT_LOWLEV;
+ break;
+
+ case IRQ_TYPE_LEVEL_HIGH:
+ newvalue = S3C2410_EXTINT_HILEV;
+ break;
+
+ default:
+ pr_err("No such irq type %d\n", type);
+ return -EINVAL;
+ }
+
+ value = readl_relaxed(extint_reg);
+ value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
+ writel_relaxed(value, extint_reg);
+
+ return 0;
+}
+
+static int s3c_irqext_type(struct irq_data *data, unsigned int type)
+{
+ void __iomem *extint_reg;
+ void __iomem *gpcon_reg;
+ unsigned long gpcon_offset, extint_offset;
+
+ if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
+ gpcon_reg = S3C2410_GPFCON;
+ extint_reg = S3C24XX_EXTINT0;
+ gpcon_offset = (data->hwirq) * 2;
+ extint_offset = (data->hwirq) * 4;
+ } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
+ gpcon_reg = S3C2410_GPGCON;
+ extint_reg = S3C24XX_EXTINT1;
+ gpcon_offset = (data->hwirq - 8) * 2;
+ extint_offset = (data->hwirq - 8) * 4;
+ } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
+ gpcon_reg = S3C2410_GPGCON;
+ extint_reg = S3C24XX_EXTINT2;
+ gpcon_offset = (data->hwirq - 8) * 2;
+ extint_offset = (data->hwirq - 16) * 4;
+ } else {
+ return -EINVAL;
+ }
+
+ return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
+ extint_offset, type);
+}
+
+static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
+{
+ void __iomem *extint_reg;
+ void __iomem *gpcon_reg;
+ unsigned long gpcon_offset, extint_offset;
+
+ if (data->hwirq <= 3) {
+ gpcon_reg = S3C2410_GPFCON;
+ extint_reg = S3C24XX_EXTINT0;
+ gpcon_offset = (data->hwirq) * 2;
+ extint_offset = (data->hwirq) * 4;
+ } else {
+ return -EINVAL;
+ }
+
+ return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
+ extint_offset, type);
+}
+
+static struct irq_chip s3c_irq_chip = {
+ .name = "s3c",
+ .irq_ack = s3c_irq_ack,
+ .irq_mask = s3c_irq_mask,
+ .irq_unmask = s3c_irq_unmask,
+ .irq_set_type = s3c_irq_type,
+ .irq_set_wake = s3c_irq_wake
+};
+
+static struct irq_chip s3c_irq_level_chip = {
+ .name = "s3c-level",
+ .irq_mask = s3c_irq_mask,
+ .irq_unmask = s3c_irq_unmask,
+ .irq_ack = s3c_irq_ack,
+ .irq_set_type = s3c_irq_type,
+};
+
+static struct irq_chip s3c_irqext_chip = {
+ .name = "s3c-ext",
+ .irq_mask = s3c_irq_mask,
+ .irq_unmask = s3c_irq_unmask,
+ .irq_ack = s3c_irq_ack,
+ .irq_set_type = s3c_irqext_type,
+ .irq_set_wake = s3c_irqext_wake
+};
+
+static struct irq_chip s3c_irq_eint0t4 = {
+ .name = "s3c-ext0",
+ .irq_ack = s3c_irq_ack,
+ .irq_mask = s3c_irq_mask,
+ .irq_unmask = s3c_irq_unmask,
+ .irq_set_wake = s3c_irq_wake,
+ .irq_set_type = s3c_irqext0_type,
+};
+
+static void s3c_irq_demux(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
+ struct s3c_irq_intc *intc = irq_data->intc;
+ struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
+ unsigned int n, offset, irq;
+ unsigned long src, msk;
+
+ /* we're using individual domains for the non-dt case
+ * and one big domain for the dt case where the subintc
+ * starts at hwirq number 32.
+ */
+ offset = irq_domain_get_of_node(intc->domain) ? 32 : 0;
+
+ chained_irq_enter(chip, desc);
+
+ src = readl_relaxed(sub_intc->reg_pending);
+ msk = readl_relaxed(sub_intc->reg_mask);
+
+ src &= ~msk;
+ src &= irq_data->sub_bits;
+
+ while (src) {
+ n = __ffs(src);
+ src &= ~(1 << n);
+ irq = irq_find_mapping(sub_intc->domain, offset + n);
+ generic_handle_irq(irq);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
+ struct pt_regs *regs, int intc_offset)
+{
+ int pnd;
+ int offset;
+
+ pnd = readl_relaxed(intc->reg_intpnd);
+ if (!pnd)
+ return false;
+
+ /* non-dt machines use individual domains */
+ if (!irq_domain_get_of_node(intc->domain))
+ intc_offset = 0;
+
+ /* We have a problem that the INTOFFSET register does not always
+ * show one interrupt. Occasionally we get two interrupts through
+ * the prioritiser, and this causes the INTOFFSET register to show
+ * what looks like the logical-or of the two interrupt numbers.
+ *
+ * Thanks to Klaus, Shannon, et al for helping to debug this problem
+ */
+ offset = readl_relaxed(intc->reg_intpnd + 4);
+
+ /* Find the bit manually, when the offset is wrong.
+ * The pending register only ever contains the one bit of the next
+ * interrupt to handle.
+ */
+ if (!(pnd & (1 << offset)))
+ offset = __ffs(pnd);
+
+ handle_domain_irq(intc->domain, intc_offset + offset, regs);
+ return true;
+}
+
+asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
+{
+ do {
+ /*
+ * For platform based machines, neither ERR nor NULL can happen here.
+ * The s3c24xx_handle_irq() will be set as IRQ handler iff this succeeds:
+ *
+ * s3c_intc[0] = s3c24xx_init_intc()
+ *
+ * If this fails, the next calls to s3c24xx_init_intc() won't be executed.
+ *
+ * For DT machine, s3c_init_intc_of() could set the IRQ handler without
+ * setting s3c_intc[0] only if it was called with num_ctrl=0. There is no
+ * such code path, so again the s3c_intc[0] will have a valid pointer if
+ * set_handle_irq() is called.
+ *
+ * Therefore in s3c24xx_handle_irq(), the s3c_intc[0] is always something.
+ */
+ if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
+ continue;
+
+ if (!IS_ERR_OR_NULL(s3c_intc[2]))
+ if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
+ continue;
+
+ break;
+ } while (1);
+}
+
+#ifdef CONFIG_FIQ
+/**
+ * s3c24xx_set_fiq - set the FIQ routing
+ * @irq: IRQ number to route to FIQ on processor.
+ * @ack_ptr: pointer to a location for storing the bit mask
+ * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
+ *
+ * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
+ * @on is true, the @irq is checked to see if it can be routed and the
+ * interrupt controller updated to route the IRQ. If @on is false, the FIQ
+ * routing is cleared, regardless of which @irq is specified.
+ *
+ * returns the mask value for the register.
+ */
+int s3c24xx_set_fiq(unsigned int irq, u32 *ack_ptr, bool on)
+{
+ u32 intmod;
+ unsigned offs;
+
+ if (on) {
+ offs = irq - FIQ_START;
+ if (offs > 31)
+ return 0;
+
+ intmod = 1 << offs;
+ } else {
+ intmod = 0;
+ }
+
+ if (ack_ptr)
+ *ack_ptr = intmod;
+ writel_relaxed(intmod, S3C2410_INTMOD);
+
+ return intmod;
+}
+
+EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
+#endif
+
+static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ struct s3c_irq_intc *intc = h->host_data;
+ struct s3c_irq_data *irq_data = &intc->irqs[hw];
+ struct s3c_irq_intc *parent_intc;
+ struct s3c_irq_data *parent_irq_data;
+ unsigned int irqno;
+
+ /* attach controller pointer to irq_data */
+ irq_data->intc = intc;
+ irq_data->offset = hw;
+
+ parent_intc = intc->parent;
+
+ /* set handler and flags */
+ switch (irq_data->type) {
+ case S3C_IRQTYPE_NONE:
+ return 0;
+ case S3C_IRQTYPE_EINT:
+ /* On the S3C2412, the EINT0to3 have a parent irq
+ * but need the s3c_irq_eint0t4 chip
+ */
+ if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
+ irq_set_chip_and_handler(virq, &s3c_irqext_chip,
+ handle_edge_irq);
+ else
+ irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
+ handle_edge_irq);
+ break;
+ case S3C_IRQTYPE_EDGE:
+ if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
+ irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+ handle_edge_irq);
+ else
+ irq_set_chip_and_handler(virq, &s3c_irq_chip,
+ handle_edge_irq);
+ break;
+ case S3C_IRQTYPE_LEVEL:
+ if (parent_intc)
+ irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+ handle_level_irq);
+ else
+ irq_set_chip_and_handler(virq, &s3c_irq_chip,
+ handle_level_irq);
+ break;
+ default:
+ pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
+ return -EINVAL;
+ }
+
+ irq_set_chip_data(virq, irq_data);
+
+ if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
+ if (irq_data->parent_irq > 31) {
+ pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
+ irq_data->parent_irq);
+ return -EINVAL;
+ }
+
+ parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
+ parent_irq_data->sub_intc = intc;
+ parent_irq_data->sub_bits |= (1UL << hw);
+
+ /* attach the demuxer to the parent irq */
+ irqno = irq_find_mapping(parent_intc->domain,
+ irq_data->parent_irq);
+ if (!irqno) {
+ pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
+ irq_data->parent_irq);
+ return -EINVAL;
+ }
+ irq_set_chained_handler(irqno, s3c_irq_demux);
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops s3c24xx_irq_ops = {
+ .map = s3c24xx_irq_map,
+ .xlate = irq_domain_xlate_twocell,
+};
+
+static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
+{
+ void __iomem *reg_source;
+ unsigned long pend;
+ unsigned long last;
+ int i;
+
+ /* if intpnd is set, read the next pending irq from there */
+ reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
+
+ last = 0;
+ for (i = 0; i < 4; i++) {
+ pend = readl_relaxed(reg_source);
+
+ if (pend == 0 || pend == last)
+ break;
+
+ writel_relaxed(pend, intc->reg_pending);
+ if (intc->reg_intpnd)
+ writel_relaxed(pend, intc->reg_intpnd);
+
+ pr_info("irq: clearing pending status %08x\n", (int)pend);
+ last = pend;
+ }
+}
+
+static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
+ struct s3c_irq_data *irq_data,
+ struct s3c_irq_intc *parent,
+ unsigned long address)
+{
+ struct s3c_irq_intc *intc;
+ void __iomem *base = (void *)0xf6000000; /* static mapping */
+ int irq_num;
+ int irq_start;
+ int ret;
+
+ intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
+ if (!intc)
+ return ERR_PTR(-ENOMEM);
+
+ intc->irqs = irq_data;
+
+ if (parent)
+ intc->parent = parent;
+
+ /* select the correct data for the controller.
+ * Need to hard code the irq num start and offset
+ * to preserve the static mapping for now
+ */
+ switch (address) {
+ case 0x4a000000:
+ pr_debug("irq: found main intc\n");
+ intc->reg_pending = base;
+ intc->reg_mask = base + 0x08;
+ intc->reg_intpnd = base + 0x10;
+ irq_num = 32;
+ irq_start = S3C2410_IRQ(0);
+ break;
+ case 0x4a000018:
+ pr_debug("irq: found subintc\n");
+ intc->reg_pending = base + 0x18;
+ intc->reg_mask = base + 0x1c;
+ irq_num = 29;
+ irq_start = S3C2410_IRQSUB(0);
+ break;
+ case 0x4a000040:
+ pr_debug("irq: found intc2\n");
+ intc->reg_pending = base + 0x40;
+ intc->reg_mask = base + 0x48;
+ intc->reg_intpnd = base + 0x50;
+ irq_num = 8;
+ irq_start = S3C2416_IRQ(0);
+ break;
+ case 0x560000a4:
+ pr_debug("irq: found eintc\n");
+ base = (void *)0xfd000000;
+
+ intc->reg_mask = base + 0xa4;
+ intc->reg_pending = base + 0xa8;
+ irq_num = 24;
+ irq_start = S3C2410_IRQ(32);
+ break;
+ default:
+ pr_err("irq: unsupported controller address\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* now that all the data is complete, init the irq-domain */
+ s3c24xx_clear_intc(intc);
+ intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
+ 0, &s3c24xx_irq_ops,
+ intc);
+ if (!intc->domain) {
+ pr_err("irq: could not create irq-domain\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ set_handle_irq(s3c24xx_handle_irq);
+
+ return intc;
+
+err:
+ kfree(intc);
+ return ERR_PTR(ret);
+}
+
+static struct s3c_irq_data __maybe_unused init_eint[32] = {
+ { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+ { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+ { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+ { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
+};
+
+#ifdef CONFIG_CPU_S3C2410
+static struct s3c_irq_data init_s3c2410base[32] = {
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+ { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+ { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+ { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+static struct s3c_irq_data init_s3c2410subint[32] = {
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+};
+
+void __init s3c2410_init_irq(void)
+{
+#ifdef CONFIG_FIQ
+ init_FIQ(FIQ_START);
+#endif
+
+ s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
+ 0x4a000000);
+ if (IS_ERR(s3c_intc[0])) {
+ pr_err("irq: could not create main interrupt controller\n");
+ return;
+ }
+
+ s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
+ s3c_intc[0], 0x4a000018);
+ s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+}
+#endif
+
+#ifdef CONFIG_CPU_S3C2412
+static struct s3c_irq_data init_s3c2412base[32] = {
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+ { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+ { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+ { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+static struct s3c_irq_data init_s3c2412eint[32] = {
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
+ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
+};
+
+static struct s3c_irq_data init_s3c2412subint[32] = {
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+ { .type = S3C_IRQTYPE_NONE, },
+ { .type = S3C_IRQTYPE_NONE, },
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
+};
+
+void __init s3c2412_init_irq(void)
+{
+ pr_info("S3C2412: IRQ Support\n");
+
+#ifdef CONFIG_FIQ
+ init_FIQ(FIQ_START);
+#endif
+
+ s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
+ 0x4a000000);
+ if (IS_ERR(s3c_intc[0])) {
+ pr_err("irq: could not create main interrupt controller\n");
+ return;
+ }
+
+ s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
+ s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
+ s3c_intc[0], 0x4a000018);
+}
+#endif
+
+#ifdef CONFIG_CPU_S3C2416
+static struct s3c_irq_data init_s3c2416base[32] = {
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+ { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
+ { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+ { .type = S3C_IRQTYPE_NONE, },
+ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+static struct s3c_irq_data init_s3c2416subint[32] = {
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+ { .type = S3C_IRQTYPE_NONE }, /* reserved */
+ { .type = S3C_IRQTYPE_NONE }, /* reserved */
+ { .type = S3C_IRQTYPE_NONE }, /* reserved */
+ { .type = S3C_IRQTYPE_NONE }, /* reserved */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
+};
+
+static struct s3c_irq_data init_s3c2416_second[32] = {
+ { .type = S3C_IRQTYPE_EDGE }, /* 2D */
+ { .type = S3C_IRQTYPE_NONE }, /* reserved */
+ { .type = S3C_IRQTYPE_NONE }, /* reserved */
+ { .type = S3C_IRQTYPE_NONE }, /* reserved */
+ { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
+ { .type = S3C_IRQTYPE_NONE }, /* reserved */
+ { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
+};
+
+void __init s3c2416_init_irq(void)
+{
+ pr_info("S3C2416: IRQ Support\n");
+
+#ifdef CONFIG_FIQ
+ init_FIQ(FIQ_START);
+#endif
+
+ s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
+ 0x4a000000);
+ if (IS_ERR(s3c_intc[0])) {
+ pr_err("irq: could not create main interrupt controller\n");
+ return;
+ }
+
+ s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+ s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
+ s3c_intc[0], 0x4a000018);
+
+ s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
+ NULL, 0x4a000040);
+}
+
+#endif
+
+#ifdef CONFIG_CPU_S3C2440
+static struct s3c_irq_data init_s3c2440base[32] = {
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
+ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+static struct s3c_irq_data init_s3c2440subint[32] = {
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
+};
+
+void __init s3c2440_init_irq(void)
+{
+ pr_info("S3C2440: IRQ Support\n");
+
+#ifdef CONFIG_FIQ
+ init_FIQ(FIQ_START);
+#endif
+
+ s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
+ 0x4a000000);
+ if (IS_ERR(s3c_intc[0])) {
+ pr_err("irq: could not create main interrupt controller\n");
+ return;
+ }
+
+ s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+ s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
+ s3c_intc[0], 0x4a000018);
+}
+#endif
+
+#ifdef CONFIG_CPU_S3C2442
+static struct s3c_irq_data init_s3c2442base[32] = {
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
+ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+ { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+static struct s3c_irq_data init_s3c2442subint[32] = {
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
+};
+
+void __init s3c2442_init_irq(void)
+{
+ pr_info("S3C2442: IRQ Support\n");
+
+#ifdef CONFIG_FIQ
+ init_FIQ(FIQ_START);
+#endif
+
+ s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
+ 0x4a000000);
+ if (IS_ERR(s3c_intc[0])) {
+ pr_err("irq: could not create main interrupt controller\n");
+ return;
+ }
+
+ s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+ s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
+ s3c_intc[0], 0x4a000018);
+}
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
+static struct s3c_irq_data init_s3c2443base[32] = {
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+ { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
+ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+
+static struct s3c_irq_data init_s3c2443subint[32] = {
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
+ { .type = S3C_IRQTYPE_NONE }, /* reserved */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
+ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
+};
+
+void __init s3c2443_init_irq(void)
+{
+ pr_info("S3C2443: IRQ Support\n");
+
+#ifdef CONFIG_FIQ
+ init_FIQ(FIQ_START);
+#endif
+
+ s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
+ 0x4a000000);
+ if (IS_ERR(s3c_intc[0])) {
+ pr_err("irq: could not create main interrupt controller\n");
+ return;
+ }
+
+ s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+ s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
+ s3c_intc[0], 0x4a000018);
+}
+#endif
+
+#ifdef CONFIG_OF
+static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ unsigned int ctrl_num = hw / 32;
+ unsigned int intc_hw = hw % 32;
+ struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
+ struct s3c_irq_intc *parent_intc = intc->parent;
+ struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
+
+ /* attach controller pointer to irq_data */
+ irq_data->intc = intc;
+ irq_data->offset = intc_hw;
+
+ if (!parent_intc)
+ irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
+ else
+ irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+ handle_edge_irq);
+
+ irq_set_chip_data(virq, irq_data);
+
+ return 0;
+}
+
+/* Translate our of irq notation
+ * format: <ctrl_num ctrl_irq parent_irq type>
+ */
+static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
+ const u32 *intspec, unsigned int intsize,
+ irq_hw_number_t *out_hwirq, unsigned int *out_type)
+{
+ struct s3c_irq_intc *intc;
+ struct s3c_irq_intc *parent_intc;
+ struct s3c_irq_data *irq_data;
+ struct s3c_irq_data *parent_irq_data;
+ int irqno;
+
+ if (WARN_ON(intsize < 4))
+ return -EINVAL;
+
+ if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
+ pr_err("controller number %d invalid\n", intspec[0]);
+ return -EINVAL;
+ }
+ intc = s3c_intc[intspec[0]];
+
+ *out_hwirq = intspec[0] * 32 + intspec[2];
+ *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
+
+ parent_intc = intc->parent;
+ if (parent_intc) {
+ irq_data = &intc->irqs[intspec[2]];
+ irq_data->parent_irq = intspec[1];
+ parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
+ parent_irq_data->sub_intc = intc;
+ parent_irq_data->sub_bits |= (1UL << intspec[2]);
+
+ /* parent_intc is always s3c_intc[0], so no offset */
+ irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
+ if (irqno < 0) {
+ pr_err("irq: could not map parent interrupt\n");
+ return irqno;
+ }
+
+ irq_set_chained_handler(irqno, s3c_irq_demux);
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops s3c24xx_irq_ops_of = {
+ .map = s3c24xx_irq_map_of,
+ .xlate = s3c24xx_irq_xlate_of,
+};
+
+struct s3c24xx_irq_of_ctrl {
+ char *name;
+ unsigned long offset;
+ struct s3c_irq_intc **handle;
+ struct s3c_irq_intc **parent;
+ struct irq_domain_ops *ops;
+};
+
+static int __init s3c_init_intc_of(struct device_node *np,
+ struct device_node *interrupt_parent,
+ struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
+{
+ struct s3c_irq_intc *intc;
+ struct s3c24xx_irq_of_ctrl *ctrl;
+ struct irq_domain *domain;
+ void __iomem *reg_base;
+ int i;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("irq-s3c24xx: could not map irq registers\n");
+ return -EINVAL;
+ }
+
+ domain = irq_domain_add_linear(np, num_ctrl * 32,
+ &s3c24xx_irq_ops_of, NULL);
+ if (!domain) {
+ pr_err("irq: could not create irq-domain\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_ctrl; i++) {
+ ctrl = &s3c_ctrl[i];
+
+ pr_debug("irq: found controller %s\n", ctrl->name);
+
+ intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
+ if (!intc)
+ return -ENOMEM;
+
+ intc->domain = domain;
+ intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data),
+ GFP_KERNEL);
+ if (!intc->irqs) {
+ kfree(intc);
+ return -ENOMEM;
+ }
+
+ if (ctrl->parent) {
+ intc->reg_pending = reg_base + ctrl->offset;
+ intc->reg_mask = reg_base + ctrl->offset + 0x4;
+
+ if (*(ctrl->parent)) {
+ intc->parent = *(ctrl->parent);
+ } else {
+ pr_warn("irq: parent of %s missing\n",
+ ctrl->name);
+ kfree(intc->irqs);
+ kfree(intc);
+ continue;
+ }
+ } else {
+ intc->reg_pending = reg_base + ctrl->offset;
+ intc->reg_mask = reg_base + ctrl->offset + 0x08;
+ intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
+ }
+
+ s3c24xx_clear_intc(intc);
+ s3c_intc[i] = intc;
+ }
+
+ set_handle_irq(s3c24xx_handle_irq);
+
+ return 0;
+}
+
+static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
+ {
+ .name = "intc",
+ .offset = 0,
+ }, {
+ .name = "subintc",
+ .offset = 0x18,
+ .parent = &s3c_intc[0],
+ }
+};
+
+int __init s3c2410_init_intc_of(struct device_node *np,
+ struct device_node *interrupt_parent)
+{
+ return s3c_init_intc_of(np, interrupt_parent,
+ s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
+}
+IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
+
+static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
+ {
+ .name = "intc",
+ .offset = 0,
+ }, {
+ .name = "subintc",
+ .offset = 0x18,
+ .parent = &s3c_intc[0],
+ }, {
+ .name = "intc2",
+ .offset = 0x40,
+ }
+};
+
+int __init s3c2416_init_intc_of(struct device_node *np,
+ struct device_node *interrupt_parent)
+{
+ return s3c_init_intc_of(np, interrupt_parent,
+ s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
+}
+IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
+#endif
diff --git a/arch/arm/mach-s3c64xx/irq-uart.h b/arch/arm/mach-s3c/irq-uart-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/irq-uart.h
rename to arch/arm/mach-s3c/irq-uart-s3c64xx.h
diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/mach-s3c/keypad.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/keypad.h
rename to arch/arm/mach-s3c/keypad.h
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c/mach-amlm5900.c
similarity index 83%
rename from arch/arm/mach-s3c24xx/mach-amlm5900.c
rename to arch/arm/mach-s3c/mach-amlm5900.c
index 9a9daf5..94c4512 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c/mach-amlm5900.c
@@ -13,6 +13,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
+#include <linux/gpio/machine.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/platform_device.h>
@@ -26,28 +27,24 @@
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/fb.h>
+#include <linux/platform_data/fb-s3c2410.h>
-#include <mach/regs-lcd.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/gpio-cfg.h>
+#include "devs.h"
+#include "cpu.h"
+#include "gpio-cfg.h"
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/map.h>
#include <linux/mtd/physmap.h>
-#include <plat/samsung-time.h>
-
-#include "common.h"
+#include "s3c24xx.h"
static struct resource amlm5900_nor_resource =
DEFINE_RES_MEM(0x00000000, SZ_16M);
@@ -124,6 +121,19 @@
}
};
+static struct gpiod_lookup_table amlm5900_mmc_gpio_table = {
+ .dev_id = "s3c2410-sdi",
+ .table = {
+ /* bus pins */
+ GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
static struct platform_device *amlm5900_devices[] __initdata = {
#ifdef CONFIG_FB_S3C2410
@@ -143,13 +153,13 @@
{
s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init amlm5900_init_time(void)
{
s3c2410_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
#ifdef CONFIG_FB_S3C2410
@@ -180,13 +190,17 @@
.gpccon = 0xaaaaaaaa,
.gpccon_mask = 0xffffffff,
+ .gpccon_reg = S3C2410_GPCCON,
.gpcup = 0x0000ffff,
.gpcup_mask = 0xffffffff,
+ .gpcup_reg = S3C2410_GPCUP,
.gpdcon = 0xaaaaaaaa,
.gpdcon_mask = 0xffffffff,
+ .gpdcon_reg = S3C2410_GPDCON,
.gpdup = 0x0000ffff,
.gpdup_mask = 0xffffffff,
+ .gpdup_reg = S3C2410_GPDUP,
};
#endif
@@ -219,6 +233,7 @@
s3c24xx_fb_set_platdata(&amlm5900_fb_info);
#endif
s3c_i2c0_set_platdata(NULL);
+ gpiod_add_lookup_table(&amlm5900_mmc_gpio_table);
platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
}
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c
similarity index 96%
rename from arch/arm/mach-s3c24xx/mach-anubis.c
rename to arch/arm/mach-s3c/mach-anubis.c
index 072966d..90e3fd9 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c/mach-anubis.c
@@ -24,13 +24,11 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
@@ -41,13 +39,12 @@
#include <net/ax88796.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
+#include "devs.h"
+#include "cpu.h"
#include <linux/platform_data/asoc-s3c24xx_simtec.h>
-#include <plat/samsung-time.h>
#include "anubis.h"
-#include "common.h"
+#include "s3c24xx.h"
#include "simtec.h"
#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
@@ -218,7 +215,7 @@
.nr_sets = ARRAY_SIZE(anubis_nand_sets),
.sets = anubis_nand_sets,
.select_chip = anubis_nand_select,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
/* IDE channels */
@@ -384,7 +381,7 @@
{
s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
/* check for the newer revision boards with large page nand */
@@ -403,7 +400,7 @@
static void __init anubis_init_time(void)
{
s3c2440_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init anubis_init(void)
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c/mach-anw6410.c
similarity index 93%
rename from arch/arm/mach-s3c64xx/mach-anw6410.c
rename to arch/arm/mach-s3c/mach-anw6410.c
index 0d3d5be..825714e 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c/mach-anw6410.c
@@ -30,24 +30,22 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
+#include "map.h"
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/fb.h>
+#include "fb.h"
-#include <plat/devs.h>
-#include <plat/cpu.h>
+#include "devs.h"
+#include "cpu.h"
#include <mach/irqs.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
-#include <plat/samsung-time.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include "common.h"
-#include "regs-modem.h"
+#include "s3c64xx.h"
+#include "regs-modem-s3c64xx.h"
/* DM9000 */
#define ANW6410_PA_DM9000 (0x18000000)
@@ -204,7 +202,7 @@
s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
anw6410_lcd_mode_set();
}
@@ -228,6 +226,5 @@
.init_irq = s3c6410_init_irq,
.map_io = anw6410_map_io,
.init_machine = anw6410_machine_init,
- .init_time = samsung_timer_init,
- .restart = s3c64xx_restart,
+ .init_time = s3c64xx_timer_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c/mach-at2440evb.c
similarity index 87%
rename from arch/arm/mach-s3c24xx/mach-at2440evb.c
rename to arch/arm/mach-s3c/mach-at2440evb.c
index 2d370f7..5fa49d4 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c/mach-at2440evb.c
@@ -24,14 +24,12 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/fb.h>
+#include <linux/platform_data/fb-s3c2410.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
@@ -40,12 +38,11 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
+#include "devs.h"
+#include "cpu.h"
#include <linux/platform_data/mmc-s3cmci.h>
-#include <plat/samsung-time.h>
-#include "common.h"
+#include "s3c24xx.h"
static struct map_desc at2440evb_iodesc[] __initdata = {
/* Nothing here */
@@ -109,7 +106,7 @@
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
.sets = at2440evb_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
/* DM9000AEP 10/100 ethernet controller */
@@ -136,7 +133,7 @@
};
static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = {
- /* Intentionally left blank */
+ .set_power = s3c24xx_mci_def_set_power,
};
static struct gpiod_lookup_table at2440evb_mci_gpio_table = {
@@ -144,10 +141,18 @@
.table = {
/* Card detect S3C2410_GPG(10) */
GPIO_LOOKUP("GPIOG", 10, "cd", GPIO_ACTIVE_LOW),
+ /* bus pins */
+ GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
{ },
},
};
+
/* 7" LCD panel */
static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
@@ -197,13 +202,13 @@
{
s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init at2440evb_init_time(void)
{
s3c2440_init_clocks(16934400);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init at2440evb_init(void)
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c
similarity index 96%
rename from arch/arm/mach-s3c24xx/mach-bast.c
rename to arch/arm/mach-s3c/mach-bast.c
index a7c3955..328f5d9 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c/mach-bast.c
@@ -40,20 +40,17 @@
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
-#include <mach/fb.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
-#include <mach/gpio-samsung.h>
+#include <linux/platform_data/fb-s3c2410.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include <plat/cpu.h>
-#include <plat/cpu-freq.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
-#include <plat/samsung-time.h>
+#include "cpu.h"
+#include <linux/soc/samsung/s3c-cpu-freq.h>
+#include "devs.h"
+#include "gpio-cfg.h"
#include "bast.h"
-#include "common.h"
+#include "s3c24xx.h"
#include "simtec.h"
#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
@@ -294,7 +291,7 @@
.nr_sets = ARRAY_SIZE(bast_nand_sets),
.sets = bast_nand_sets,
.select_chip = bast_nand_select,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
/* DM9000 */
@@ -550,13 +547,13 @@
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init bast_init_time(void)
{
s3c2410_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init bast_init(void)
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c/mach-crag6410-module.c
similarity index 97%
rename from arch/arm/mach-s3c64xx/mach-crag6410-module.c
rename to arch/arm/mach-s3c/mach-crag6410-module.c
index 937d0a8..407ad49 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c/mach-crag6410-module.c
@@ -27,7 +27,7 @@
#include <linux/platform_data/spi-s3c64xx.h>
-#include <plat/cpu.h>
+#include "cpu.h"
#include <mach/irqs.h>
#include "crag6410.h"
@@ -378,8 +378,7 @@
.i2c_devs = wm2200_i2c, .num_i2c_devs = ARRAY_SIZE(wm2200_i2c) },
};
-static int wlf_gf_module_probe(struct i2c_client *i2c,
- const struct i2c_device_id *i2c_id)
+static int wlf_gf_module_probe(struct i2c_client *i2c)
{
int ret, i, j, id, rev;
@@ -405,10 +404,9 @@
gf_mods[i].name, rev + 1);
for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
- if (!i2c_new_device(i2c->adapter,
- &(gf_mods[i].i2c_devs[j])))
- dev_err(&i2c->dev,
- "Failed to register dev: %d\n", ret);
+ if (IS_ERR(i2c_new_client_device(i2c->adapter,
+ &(gf_mods[i].i2c_devs[j]))))
+ dev_err(&i2c->dev, "Failed to register\n");
}
spi_register_board_info(gf_mods[i].spi_devs,
@@ -433,7 +431,7 @@
.driver = {
.name = "wlf-gf-module"
},
- .probe = wlf_gf_module_probe,
+ .probe_new = wlf_gf_module_probe,
.id_table = wlf_gf_module_id,
};
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c/mach-crag6410.c
similarity index 97%
rename from arch/arm/mach-s3c64xx/mach-crag6410.c
rename to arch/arm/mach-s3c/mach-crag6410.c
index 8ec6a4f..4a12c75 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c/mach-crag6410.c
@@ -44,30 +44,28 @@
#include <asm/mach-types.h>
#include <video/samsung_fimd.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "map.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
#include <mach/irqs.h>
-#include <plat/fb.h>
-#include <plat/sdhci.h>
-#include <plat/gpio-cfg.h>
+#include "fb.h"
+#include "sdhci.h"
+#include "gpio-cfg.h"
#include <linux/platform_data/spi-s3c64xx.h>
-#include <plat/keypad.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/adc.h>
+#include "keypad.h"
+#include "devs.h"
+#include "cpu.h"
+#include <linux/soc/samsung/s3c-adc.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/pm.h>
-#include <plat/samsung-time.h>
+#include "pm.h"
-#include "common.h"
+#include "s3c64xx.h"
#include "crag6410.h"
-#include "regs-gpio-memport.h"
-#include "regs-modem.h"
-#include "regs-sys.h"
+#include "regs-gpio-memport-s3c64xx.h"
+#include "regs-modem-s3c64xx.h"
+#include "regs-sys-s3c64xx.h"
/* serial port setup */
@@ -114,7 +112,6 @@
static struct platform_pwm_backlight_data crag6410_backlight_data = {
.max_brightness = 1000,
.dft_brightness = 600,
- .enable_gpio = -1,
};
static struct platform_device crag6410_backlight_device = {
@@ -751,7 +748,7 @@
s3c64xx_init_io(NULL, 0);
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
/* LCD type and Bypass set by bootloader */
}
@@ -878,6 +875,5 @@
.init_irq = s3c6410_init_irq,
.map_io = crag6410_map_io,
.init_machine = crag6410_machine_init,
- .init_time = samsung_timer_init,
- .restart = s3c64xx_restart,
+ .init_time = s3c64xx_timer_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c/mach-gta02.c
similarity index 89%
rename from arch/arm/mach-s3c24xx/mach-gta02.c
rename to arch/arm/mach-s3c/mach-gta02.c
index 594901f..3c75c7d 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c/mach-gta02.c
@@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/init.h>
+#include <linux/gpio/machine.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/workqueue.h>
@@ -56,20 +57,18 @@
#include <linux/platform_data/touchscreen-s3c2410.h>
#include <linux/platform_data/usb-ohci-s3c2410.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <linux/platform_data/fb-s3c2410.h>
-#include <mach/fb.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-irq.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "regs-irq.h"
+#include "gpio-samsung.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
-#include <plat/pm.h>
-#include <plat/samsung-time.h>
+#include "cpu.h"
+#include "devs.h"
+#include "gpio-cfg.h"
+#include "pm.h"
-#include "common.h"
+#include "s3c24xx.h"
#include "gta02.h"
static struct pcf50633 *gta02_pcf;
@@ -416,7 +415,7 @@
.twrph1 = 15,
.nr_sets = ARRAY_SIZE(gta02_nand_sets),
.sets = gta02_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
@@ -474,11 +473,39 @@
},
};
+static struct gpiod_lookup_table gta02_audio_gpio_table = {
+ .dev_id = "neo1973-audio",
+ .table = {
+ GPIO_LOOKUP("GPIOJ", 2, "amp-shut", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOJ", 1, "hp", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct platform_device gta02_audio = {
+ .name = "neo1973-audio",
+ .id = -1,
+};
+
+static struct gpiod_lookup_table gta02_mmc_gpio_table = {
+ .dev_id = "s3c2410-sdi",
+ .table = {
+ /* bus pins */
+ GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static void __init gta02_map_io(void)
{
s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
@@ -498,6 +525,7 @@
>a02_buttons_device,
&s3c_device_adc,
&s3c_device_ts,
+ >a02_audio,
};
static void gta02_poweroff(void)
@@ -524,6 +552,12 @@
i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs));
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
+
+ gpiod_add_lookup_table(>a02_audio_gpio_table);
+ gpiod_add_lookup_table(>a02_mmc_gpio_table);
platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices));
pm_power_off = gta02_poweroff;
@@ -533,7 +567,7 @@
static void __init gta02_init_time(void)
{
s3c2442_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
MACHINE_START(NEO1973_GTA02, "GTA02")
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c/mach-h1940.c
similarity index 92%
rename from arch/arm/mach-s3c24xx/mach-h1940.c
rename to arch/arm/mach-s3c/mach-h1940.c
index 8d9d8e7..53d51aa 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c/mach-h1940.c
@@ -3,7 +3,7 @@
// Copyright (c) 2003-2005 Simtec Electronics
// Ben Dooks <ben@simtec.co.uk>
//
-// http://www.handhelds.org/projects/h1940.html
+// https://www.handhelds.org/projects/h1940.html
#include <linux/kernel.h>
#include <linux/types.h>
@@ -47,20 +47,19 @@
#include <sound/uda1380.h>
-#include <mach/fb.h>
-#include <mach/hardware.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
-#include <mach/gpio-samsung.h>
+#include <linux/platform_data/fb-s3c2410.h>
+#include "map.h"
+#include "hardware-s3c24xx.h"
+#include "regs-clock.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
-#include <plat/pm.h>
-#include <plat/samsung-time.h>
+#include "cpu.h"
+#include "devs.h"
+#include "gpio-cfg.h"
+#include "pm.h"
-#include "common.h"
+#include "s3c24xx.h"
#include "h1940.h"
#define H1940_LATCH ((void __force __iomem *)0xF8000000)
@@ -180,9 +179,9 @@
.cfg_gpio = s3c24xx_ts_cfg_gpio,
};
-/**
+/*
* Set lcd on or off
- **/
+ */
static struct s3c2410fb_display h1940_lcd __initdata = {
.lcdcon5= S3C2410_LCDCON5_FRM565 | \
S3C2410_LCDCON5_INVVLINE | \
@@ -211,12 +210,16 @@
.lpcsel = 0x02,
.gpccon = 0xaa940659,
.gpccon_mask = 0xffffc0f0,
+ .gpccon_reg = S3C2410_GPCCON,
.gpcup = 0x0000ffff,
.gpcup_mask = 0xffffffff,
+ .gpcup_reg = S3C2410_GPCUP,
.gpdcon = 0xaa84aaa0,
.gpdcon_mask = 0xffffffff,
+ .gpdcon_reg = S3C2410_GPDCON,
.gpdup = 0x0000faff,
.gpdup_mask = 0xffffffff,
+ .gpdup_reg = S3C2410_GPDUP,
};
static int power_supply_init(struct device *dev)
@@ -446,6 +449,8 @@
static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd)
{
+ s3c24xx_mci_def_set_power(power_mode, vdd);
+
switch (power_mode) {
case MMC_POWER_OFF:
gpio_set_value(H1940_LATCH_SD_POWER, 0);
@@ -471,10 +476,33 @@
GPIO_LOOKUP("GPIOF", 5, "cd", GPIO_ACTIVE_LOW),
/* Write protect S3C2410_GPH(8) */
GPIO_LOOKUP("GPIOH", 8, "wp", GPIO_ACTIVE_LOW),
+ /* bus pins */
+ GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
{ },
},
};
+static struct gpiod_lookup_table h1940_audio_gpio_table = {
+ .dev_id = "h1940-audio",
+ .table = {
+ GPIO_LOOKUP("H1940_LATCH",
+ H1940_LATCH_AUDIO_POWER - H1940_LATCH_GPIO(0),
+ "speaker-power", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOG", 4, "hp", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct platform_device h1940_audio = {
+ .name = "h1940-audio",
+ .id = -1,
+};
+
static struct pwm_lookup h1940_pwm_lookup[] = {
PWM_LOOKUP("samsung-pwm", 0, "pwm-backlight", NULL, 36296,
PWM_POLARITY_NORMAL),
@@ -516,7 +544,6 @@
static struct platform_pwm_backlight_data backlight_data = {
.max_brightness = 100,
.dft_brightness = 50,
- .enable_gpio = -1,
.init = h1940_backlight_init,
.notify = h1940_backlight_notify,
.exit = h1940_backlight_exit,
@@ -652,13 +679,14 @@
&s3c_device_ts,
&power_supply,
&h1940_battery,
+ &h1940_audio,
};
static void __init h1940_map_io(void)
{
s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
/* setup PM */
@@ -675,7 +703,7 @@
static void __init h1940_init_time(void)
{
s3c2410_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
/* H1940 and RX3715 need to reserve this for suspend */
@@ -691,6 +719,10 @@
s3c24xx_fb_set_platdata(&h1940_fb_info);
gpiod_add_lookup_table(&h1940_mmc_gpio_table);
+ gpiod_add_lookup_table(&h1940_audio_gpio_table);
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
s3c24xx_mci_set_platdata(&h1940_mmc_cfg);
s3c24xx_udc_set_platdata(&h1940_udc_cfg);
s3c24xx_ts_set_platdata(&h1940_ts_cfg);
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c/mach-hmt.c
similarity index 94%
rename from arch/arm/mach-s3c64xx/mach-hmt.c
rename to arch/arm/mach-s3c/mach-hmt.c
index bfe9881..b287e99 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c/mach-hmt.c
@@ -25,23 +25,21 @@
#include <asm/mach/irq.h>
#include <video/samsung_fimd.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
+#include "map.h"
#include <mach/irqs.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/gpio-samsung.h>
-#include <plat/fb.h>
+#include "gpio-samsung.h"
+#include "fb.h"
#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/samsung-time.h>
+#include "devs.h"
+#include "cpu.h"
-#include "common.h"
+#include "s3c64xx.h"
#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
@@ -115,7 +113,6 @@
static struct platform_pwm_backlight_data hmt_backlight_data = {
.max_brightness = 100 * 256,
.dft_brightness = 40 * 256,
- .enable_gpio = -1,
.init = hmt_bl_init,
.notify = hmt_bl_notify,
.exit = hmt_bl_exit,
@@ -200,7 +197,7 @@
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(hmt_nand_sets),
.sets = hmt_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
static struct gpio_led hmt_leds[] = {
@@ -252,7 +249,7 @@
s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
}
static void __init hmt_machine_init(void)
@@ -281,6 +278,5 @@
.init_irq = s3c6410_init_irq,
.map_io = hmt_map_io,
.init_machine = hmt_machine_init,
- .init_time = samsung_timer_init,
- .restart = s3c64xx_restart,
+ .init_time = s3c64xx_timer_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c/mach-jive.c
similarity index 97%
rename from arch/arm/mach-s3c24xx/mach-jive.c
rename to arch/arm/mach-s3c/mach-jive.c
index 885e8f1..2a29c3e 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c/mach-jive.c
@@ -31,10 +31,10 @@
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
-#include <mach/fb.h>
-#include <mach/gpio-samsung.h>
+#include "hardware-s3c24xx.h"
+#include "regs-gpio.h"
+#include <linux/platform_data/fb-s3c2410.h>
+#include "gpio-samsung.h"
#include <asm/mach-types.h>
@@ -43,14 +43,13 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
+#include "gpio-cfg.h"
+#include "devs.h"
+#include "cpu.h"
+#include "pm.h"
#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <plat/samsung-time.h>
-#include "common.h"
+#include "s3c24xx.h"
#include "s3c2412-power.h"
static struct map_desc jive_iodesc[] __initdata = {
@@ -228,7 +227,7 @@
.twrph1 = 40,
.sets = jive_nand_sets,
.nr_sets = ARRAY_SIZE(jive_nand_sets),
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
static int __init jive_mtdset(char *options)
@@ -321,6 +320,7 @@
* data. */
.gpcup = (0xf << 1) | (0x3f << 10),
+ .gpcup_reg = S3C2410_GPCUP,
.gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
@@ -334,8 +334,12 @@
S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
+ .gpccon_reg = S3C2410_GPCCON,
+
.gpdup = (0x3f << 2) | (0x3f << 10),
+ .gpdup_reg = S3C2410_GPDUP,
+
.gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
@@ -349,6 +353,8 @@
S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
+
+ .gpdcon_reg = S3C2410_GPDCON,
};
/* ILI9320 support. */
@@ -523,13 +529,13 @@
{
s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init jive_init_time(void)
{
s3c2412_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void jive_power_off(void)
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c/mach-mini2440.c
similarity index 86%
rename from arch/arm/mach-s3c24xx/mach-mini2440.c
rename to arch/arm/mach-s3c/mach-mini2440.c
index 3a5b112..dc22ab8 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c/mach-mini2440.c
@@ -6,7 +6,7 @@
// Weibing <http://weibing.blogbus.com> and
// Michel Pollet <buserror@gmail.com>
//
-// For product information, visit http://code.google.com/p/mini2440/
+// For product information, visit https://code.google.com/p/mini2440/
#include <linux/kernel.h>
#include <linux/types.h>
@@ -30,15 +30,13 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/fb.h>
+#include <linux/platform_data/fb-s3c2410.h>
#include <asm/mach-types.h>
-#include <mach/regs-gpio.h>
+#include "regs-gpio.h"
#include <linux/platform_data/leds-s3c24xx.h>
-#include <mach/regs-lcd.h>
#include <mach/irqs.h>
-#include <mach/gpio-samsung.h>
+#include "gpio-samsung.h"
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/mmc-s3cmci.h>
@@ -49,14 +47,13 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/samsung-time.h>
+#include "gpio-cfg.h"
+#include "devs.h"
+#include "cpu.h"
#include <sound/s3c24xx_uda134x.h>
-#include "common.h"
+#include "s3c24xx.h"
#define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300)
@@ -215,6 +212,9 @@
S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
+ .gpccon_reg = S3C2410_GPCCON,
+ .gpcup_reg = S3C2410_GPCUP,
+
.gpdup = (0x3f << 2) | (0x3f << 10),
.gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
@@ -230,13 +230,16 @@
S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
+
+ .gpdcon_reg = S3C2410_GPDCON,
+ .gpdup_reg = S3C2410_GPDUP,
};
/* MMC/SD */
static struct s3c24xx_mci_pdata mini2440_mmc_cfg __initdata = {
.wprotect_invert = 1,
- .set_power = NULL,
+ .set_power = s3c24xx_mci_def_set_power,
.ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34,
};
@@ -247,6 +250,13 @@
GPIO_LOOKUP("GPIOG", 8, "cd", GPIO_ACTIVE_LOW),
/* Write protect S3C2410_GPH(8) */
GPIO_LOOKUP("GPIOH", 8, "wp", GPIO_ACTIVE_HIGH),
+ /* bus pins */
+ GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
{ },
},
};
@@ -296,7 +306,7 @@
.nr_sets = ARRAY_SIZE(mini2440_nand_sets),
.sets = mini2440_nand_sets,
.ignore_unset_ecc = 1,
- .ecc_mode = NAND_ECC_HW,
+ .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST,
};
/* DM9000AEP 10/100 ethernet controller */
@@ -402,37 +412,68 @@
/* LEDS */
+static struct gpiod_lookup_table mini2440_led1_gpio_table = {
+ .dev_id = "s3c24xx_led.1",
+ .table = {
+ GPIO_LOOKUP("GPB", 5, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table mini2440_led2_gpio_table = {
+ .dev_id = "s3c24xx_led.2",
+ .table = {
+ GPIO_LOOKUP("GPB", 6, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table mini2440_led3_gpio_table = {
+ .dev_id = "s3c24xx_led.3",
+ .table = {
+ GPIO_LOOKUP("GPB", 7, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table mini2440_led4_gpio_table = {
+ .dev_id = "s3c24xx_led.4",
+ .table = {
+ GPIO_LOOKUP("GPB", 8, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table mini2440_backlight_gpio_table = {
+ .dev_id = "s3c24xx_led.5",
+ .table = {
+ GPIO_LOOKUP("GPG", 4, NULL, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static struct s3c24xx_led_platdata mini2440_led1_pdata = {
.name = "led1",
- .gpio = S3C2410_GPB(5),
- .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.def_trigger = "heartbeat",
};
static struct s3c24xx_led_platdata mini2440_led2_pdata = {
.name = "led2",
- .gpio = S3C2410_GPB(6),
- .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.def_trigger = "nand-disk",
};
static struct s3c24xx_led_platdata mini2440_led3_pdata = {
.name = "led3",
- .gpio = S3C2410_GPB(7),
- .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.def_trigger = "mmc0",
};
static struct s3c24xx_led_platdata mini2440_led4_pdata = {
.name = "led4",
- .gpio = S3C2410_GPB(8),
- .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.def_trigger = "",
};
static struct s3c24xx_led_platdata mini2440_led_backlight_pdata = {
.name = "backlight",
- .gpio = S3C2410_GPG(4),
.def_trigger = "backlight",
};
@@ -556,13 +597,13 @@
{
s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init mini2440_init_time(void)
{
s3c2440_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
/*
@@ -685,6 +726,11 @@
s3c_gpio_setpull(mini2440_buttons[i].gpio, S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(mini2440_buttons[i].gpio, S3C2410_GPIO_INPUT);
}
+
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
+
if (features.lcd_index != -1) {
int li;
@@ -714,6 +760,20 @@
i2c_register_board_info(0, mini2440_i2c_devs,
ARRAY_SIZE(mini2440_i2c_devs));
+ /* Disable pull-up on the LED lines */
+ s3c_gpio_setpull(S3C2410_GPB(5), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPB(6), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPB(7), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPB(8), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPG(4), S3C_GPIO_PULL_NONE);
+
+ /* Add lookups for the lines */
+ gpiod_add_lookup_table(&mini2440_led1_gpio_table);
+ gpiod_add_lookup_table(&mini2440_led2_gpio_table);
+ gpiod_add_lookup_table(&mini2440_led3_gpio_table);
+ gpiod_add_lookup_table(&mini2440_led4_gpio_table);
+ gpiod_add_lookup_table(&mini2440_backlight_gpio_table);
+
platform_add_devices(mini2440_devices, ARRAY_SIZE(mini2440_devices));
if (features.count) /* the optional features */
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c/mach-mini6410.c
similarity index 94%
rename from arch/arm/mach-s3c64xx/mach-mini6410.c
rename to arch/arm/mach-s3c/mach-mini6410.c
index 0dd36ae..741fa1f 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c/mach-mini6410.c
@@ -23,27 +23,26 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "map.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include <plat/adc.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
+#include <linux/soc/samsung/s3c-adc.h>
+#include "cpu.h"
+#include "devs.h"
+#include "fb.h"
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/mmc-sdhci-s3c.h>
-#include <plat/sdhci.h>
+#include "sdhci.h"
#include <linux/platform_data/touchscreen-s3c2410.h>
#include <mach/irqs.h>
#include <video/platform_lcd.h>
#include <video/samsung_fimd.h>
-#include <plat/samsung-time.h>
-#include "common.h"
-#include "regs-modem.h"
-#include "regs-srom.h"
+#include "s3c64xx.h"
+#include "regs-modem-s3c64xx.h"
+#include "regs-srom-s3c64xx.h"
#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
@@ -136,7 +135,7 @@
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(mini6410_nand_sets),
.sets = mini6410_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
@@ -238,7 +237,7 @@
s3c64xx_init_io(NULL, 0);
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
/* set the LCD type */
tmp = __raw_readl(S3C64XX_SPCON);
@@ -362,6 +361,5 @@
.init_irq = s3c6410_init_irq,
.map_io = mini6410_map_io,
.init_machine = mini6410_machine_init,
- .init_time = samsung_timer_init,
- .restart = s3c64xx_restart,
+ .init_time = s3c64xx_timer_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c/mach-n30.c
similarity index 87%
rename from arch/arm/mach-s3c24xx/mach-n30.c
rename to arch/arm/mach-s3c/mach-n30.c
index ffa20f5..e40c1fc 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c/mach-n30.c
@@ -9,7 +9,7 @@
// Copyright (c) 2005-2008 Christer Weinigel <christer@weinigel.se>
//
// There is a wiki with more information about the n30 port at
-// http://handhelds.org/moin/moin.cgi/AcerN30Documentation .
+// https://handhelds.org/moin/moin.cgi/AcerN30Documentation .
#include <linux/kernel.h>
#include <linux/types.h>
@@ -27,15 +27,15 @@
#include <linux/io.h>
#include <linux/mmc/host.h>
-#include <mach/hardware.h>
+#include "hardware-s3c24xx.h"
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/fb.h>
+#include <linux/platform_data/fb-s3c2410.h>
#include <linux/platform_data/leds-s3c24xx.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
@@ -43,13 +43,12 @@
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
+#include "cpu.h"
+#include "devs.h"
#include <linux/platform_data/mmc-s3cmci.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
-#include <plat/samsung-time.h>
-#include "common.h"
+#include "s3c24xx.h"
static struct map_desc n30_iodesc[] __initdata = {
/* nothing here yet */
@@ -246,17 +245,33 @@
};
/* This is the bluetooth LED on the device. */
+
+static struct gpiod_lookup_table n30_blue_led_gpio_table = {
+ .dev_id = "s3c24xx_led.1",
+ .table = {
+ GPIO_LOOKUP("GPG", 6, NULL, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static struct s3c24xx_led_platdata n30_blue_led_pdata = {
.name = "blue_led",
- .gpio = S3C2410_GPG(6),
.def_trigger = "",
};
/* This is the blue LED on the device. Originally used to indicate GPS activity
* by flashing. */
+
+static struct gpiod_lookup_table n35_blue_led_gpio_table = {
+ .dev_id = "s3c24xx_led.1",
+ .table = {
+ GPIO_LOOKUP("GPD", 8, NULL, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static struct s3c24xx_led_platdata n35_blue_led_pdata = {
.name = "blue_led",
- .gpio = S3C2410_GPD(8),
.def_trigger = "",
};
@@ -264,17 +279,30 @@
* red, blinking green or solid green when the battery is low,
* charging or full respectively. By driving GPD9 low, it's possible
* to force the LED to blink red, so call that warning LED. */
+
+static struct gpiod_lookup_table n30_warning_led_gpio_table = {
+ .dev_id = "s3c24xx_led.2",
+ .table = {
+ GPIO_LOOKUP("GPD", 9, NULL, GPIO_ACTIVE_LOW),
+ { },
+ },
+};
+
static struct s3c24xx_led_platdata n30_warning_led_pdata = {
.name = "warning_led",
- .flags = S3C24XX_LEDF_ACTLOW,
- .gpio = S3C2410_GPD(9),
.def_trigger = "",
};
+static struct gpiod_lookup_table n35_warning_led_gpio_table = {
+ .dev_id = "s3c24xx_led.2",
+ .table = {
+ GPIO_LOOKUP("GPD", 9, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
+ { },
+ },
+};
+
static struct s3c24xx_led_platdata n35_warning_led_pdata = {
.name = "warning_led",
- .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
- .gpio = S3C2410_GPD(9),
.def_trigger = "",
};
@@ -338,6 +366,8 @@
static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd)
{
+ s3c24xx_mci_def_set_power(power_mode, vdd);
+
switch (power_mode) {
case MMC_POWER_ON:
case MMC_POWER_UP:
@@ -363,6 +393,13 @@
/* Write protect S3C2410_GPG(10) */
GPIO_LOOKUP("GPIOG", 10, "wp", GPIO_ACTIVE_LOW),
{ },
+ /* bus pins */
+ GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
},
};
@@ -542,13 +579,13 @@
s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc));
n30_hwinit();
s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init n30_init_time(void)
{
s3c2410_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
/* GPB3 is the line that controls the pull-up for the USB D+ line */
@@ -570,6 +607,10 @@
S3C2410_MISCCR_USBSUSPND0 |
S3C2410_MISCCR_USBSUSPND1, 0x0);
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
+
if (machine_is_n30()) {
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
@@ -577,6 +618,12 @@
S3C2410_MISCCR_USBSUSPND0 |
S3C2410_MISCCR_USBSUSPND1, 0x0);
+ /* Disable pull-up and add GPIO tables */
+ s3c_gpio_setpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
+ gpiod_add_lookup_table(&n30_blue_led_gpio_table);
+ gpiod_add_lookup_table(&n30_warning_led_gpio_table);
+
platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices));
}
@@ -594,6 +641,12 @@
S3C2410_MISCCR_USBSUSPND1,
S3C2410_MISCCR_USBSUSPND0);
+ /* Disable pull-up and add GPIO tables */
+ s3c_gpio_setpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
+ gpiod_add_lookup_table(&n35_blue_led_gpio_table);
+ gpiod_add_lookup_table(&n35_warning_led_gpio_table);
+
platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
}
}
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c/mach-ncp.c
similarity index 87%
rename from arch/arm/mach-s3c64xx/mach-ncp.c
rename to arch/arm/mach-s3c/mach-ncp.c
index 13fea5c..1a45bed 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c/mach-ncp.c
@@ -25,20 +25,18 @@
#include <asm/mach/irq.h>
#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
+#include "map.h"
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/fb.h>
+#include "fb.h"
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/samsung-time.h>
+#include "devs.h"
+#include "cpu.h"
-#include "common.h"
+#include "s3c64xx.h"
#define UCON S3C2410_UCON_DEFAULT
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
@@ -81,7 +79,7 @@
s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
}
static void __init ncp_machine_init(void)
@@ -98,6 +96,5 @@
.init_irq = s3c6410_init_irq,
.map_io = ncp_map_io,
.init_machine = ncp_machine_init,
- .init_time = samsung_timer_init,
- .restart = s3c64xx_restart,
+ .init_time = s3c64xx_timer_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c/mach-nexcoder.c
similarity index 90%
rename from arch/arm/mach-s3c24xx/mach-nexcoder.c
rename to arch/arm/mach-s3c/mach-nexcoder.c
index c2f3475..2a454c9 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c/mach-nexcoder.c
@@ -28,21 +28,19 @@
#include <asm/mach/irq.h>
#include <asm/setup.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
//#include <asm/debug-ll.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/samsung-time.h>
+#include "gpio-cfg.h"
+#include "devs.h"
+#include "cpu.h"
-#include "common.h"
+#include "s3c24xx.h"
static struct map_desc nexcoder_iodesc[] __initdata = {
/* nothing here yet */
@@ -131,7 +129,7 @@
{
s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
nexcoder_sensorboard_init();
}
@@ -139,12 +137,17 @@
static void __init nexcoder_init_time(void)
{
s3c2440_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init nexcoder_init(void)
{
s3c_i2c0_set_platdata(NULL);
+
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
+
platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
};
diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c b/arch/arm/mach-s3c/mach-osiris-dvs.c
similarity index 97%
rename from arch/arm/mach-s3c24xx/mach-osiris-dvs.c
rename to arch/arm/mach-s3c/mach-osiris-dvs.c
index 5d819b6..2e283ae 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
+++ b/arch/arm/mach-s3c/mach-osiris-dvs.c
@@ -14,8 +14,8 @@
#include <linux/mfd/tps65010.h>
-#include <plat/cpu-freq.h>
-#include <mach/gpio-samsung.h>
+#include <linux/soc/samsung/s3c-cpu-freq.h>
+#include "gpio-samsung.h"
#define OSIRIS_GPIO_DVS S3C2410_GPB(5)
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c/mach-osiris.c
similarity index 95%
rename from arch/arm/mach-s3c24xx/mach-osiris.c
rename to arch/arm/mach-s3c/mach-osiris.c
index ee3630c..81744ca 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c/mach-osiris.c
@@ -36,20 +36,17 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
-#include <plat/cpu.h>
-#include <plat/cpu-freq.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
-#include <plat/samsung-time.h>
+#include "cpu.h"
+#include <linux/soc/samsung/s3c-cpu-freq.h>
+#include "devs.h"
+#include "gpio-cfg.h"
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include "common.h"
+#include "s3c24xx.h"
#include "osiris.h"
-#include "regs-mem.h"
+#include "regs-mem-s3c24xx.h"
/* onboard perihperal map */
@@ -234,7 +231,7 @@
.nr_sets = ARRAY_SIZE(osiris_nand_sets),
.sets = osiris_nand_sets,
.select_chip = osiris_nand_select,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
/* PCMCIA control and configuration */
@@ -359,7 +356,7 @@
s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
/* check for the newer revision boards with large page nand */
@@ -384,7 +381,7 @@
static void __init osiris_init_time(void)
{
s3c2440_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init osiris_init(void)
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c/mach-otom.c
similarity index 88%
rename from arch/arm/mach-s3c24xx/mach-otom.c
rename to arch/arm/mach-s3c/mach-otom.c
index 4e24d89..460ee97 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c/mach-otom.c
@@ -22,14 +22,13 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/samsung-time.h>
+#include "cpu.h"
+#include "devs.h"
-#include "common.h"
+#include "s3c24xx.h"
#include "otom.h"
static struct map_desc otom11_iodesc[] __initdata = {
@@ -95,18 +94,22 @@
{
s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init otom11_init_time(void)
{
s3c2410_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init otom11_init(void)
{
s3c_i2c0_set_platdata(NULL);
+
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
}
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c/mach-qt2410.c
similarity index 84%
rename from arch/arm/mach-s3c24xx/mach-qt2410.c
rename to arch/arm/mach-s3c/mach-qt2410.c
index 5d48e5b..151e8e3 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c/mach-qt2410.c
@@ -28,26 +28,23 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <linux/platform_data/leds-s3c24xx.h>
-#include <mach/regs-lcd.h>
-#include <mach/fb.h>
+#include <linux/platform_data/fb-s3c2410.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/gpio-samsung.h>
+#include "gpio-samsung.h"
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/samsung-time.h>
+#include "gpio-cfg.h"
+#include "devs.h"
+#include "cpu.h"
+#include "pm.h"
-#include "common.h"
-#include "common-smdk.h"
+#include "s3c24xx.h"
+#include "common-smdk-s3c24xx.h"
static struct map_desc qt2410_iodesc[] __initdata = {
{ 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
@@ -177,9 +174,15 @@
/* LED */
+static struct gpiod_lookup_table qt2410_led_gpio_table = {
+ .dev_id = "s3c24xx_led.0",
+ .table = {
+ GPIO_LOOKUP("GPB", 0, NULL, GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN),
+ { },
+ },
+};
+
static struct s3c24xx_led_platdata qt2410_pdata_led = {
- .gpio = S3C2410_GPB(0),
- .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.name = "led",
.def_trigger = "timer",
};
@@ -219,6 +222,20 @@
},
};
+static struct gpiod_lookup_table qt2410_mmc_gpiod_table = {
+ .dev_id = "s3c2410-sdi",
+ .table = {
+ /* bus pins */
+ GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
/* Board devices */
static struct platform_device *qt2410_devices[] __initdata = {
@@ -281,7 +298,7 @@
.twrph1 = 20,
.nr_sets = ARRAY_SIZE(qt2410_nand_sets),
.sets = qt2410_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
/* UDC */
@@ -303,13 +320,13 @@
{
s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init qt2410_init_time(void)
{
s3c2410_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init qt2410_machine_init(void)
@@ -337,7 +354,13 @@
s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
s3c_i2c0_set_platdata(NULL);
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
gpiod_add_lookup_table(&qt2410_spi_gpiod_table);
+ s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
+ gpiod_add_lookup_table(&qt2410_led_gpio_table);
+ gpiod_add_lookup_table(&qt2410_mmc_gpiod_table);
platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
s3c_pm_init();
}
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c/mach-real6410.c
similarity index 94%
rename from arch/arm/mach-s3c64xx/mach-real6410.c
rename to arch/arm/mach-s3c/mach-real6410.c
index 0ff88b6..9d218a5 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c/mach-real6410.c
@@ -24,25 +24,24 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "map.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
#include <mach/irqs.h>
-#include <plat/adc.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
+#include <linux/soc/samsung/s3c-adc.h>
+#include "cpu.h"
+#include "devs.h"
+#include "fb.h"
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/touchscreen-s3c2410.h>
#include <video/platform_lcd.h>
#include <video/samsung_fimd.h>
-#include <plat/samsung-time.h>
-#include "common.h"
-#include "regs-modem.h"
-#include "regs-srom.h"
+#include "s3c64xx.h"
+#include "regs-modem-s3c64xx.h"
+#include "regs-srom-s3c64xx.h"
#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
@@ -188,7 +187,7 @@
.twrph1 = 40,
.nr_sets = ARRAY_SIZE(real6410_nand_sets),
.sets = real6410_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
static struct platform_device *real6410_devices[] __initdata = {
@@ -208,7 +207,7 @@
s3c64xx_init_io(NULL, 0);
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
/* set the LCD type */
tmp = __raw_readl(S3C64XX_SPCON);
@@ -330,6 +329,5 @@
.init_irq = s3c6410_init_irq,
.map_io = real6410_map_io,
.init_machine = real6410_machine_init,
- .init_time = samsung_timer_init,
- .restart = s3c64xx_restart,
+ .init_time = s3c64xx_timer_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c/mach-rx1950.c
similarity index 90%
rename from arch/arm/mach-s3c24xx/mach-rx1950.c
rename to arch/arm/mach-s3c/mach-rx1950.c
index 534e9c1..b9758f0 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c/mach-rx1950.c
@@ -42,21 +42,20 @@
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/touchscreen-s3c2410.h>
#include <linux/platform_data/usb-s3c2410_udc.h>
+#include <linux/platform_data/fb-s3c2410.h>
#include <sound/uda1380.h>
-#include <mach/fb.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
-#include <mach/gpio-samsung.h>
+#include "hardware-s3c24xx.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/pm.h>
-#include <plat/samsung-time.h>
-#include <plat/gpio-cfg.h>
+#include "cpu.h"
+#include "devs.h"
+#include "pm.h"
+#include "gpio-cfg.h"
-#include "common.h"
+#include "s3c24xx.h"
#include "h1940.h"
#define LCD_PWM_PERIOD 192960
@@ -361,14 +360,17 @@
.lpcsel = 0x02,
.gpccon = 0xaa9556a9,
.gpccon_mask = 0xffc003fc,
+ .gpccon_reg = S3C2410_GPCCON,
.gpcup = 0x0000ffff,
.gpcup_mask = 0xffffffff,
+ .gpcup_reg = S3C2410_GPCUP,
.gpdcon = 0xaa90aaa1,
.gpdcon_mask = 0xffc0fff0,
+ .gpdcon_reg = S3C2410_GPDCON,
.gpdup = 0x0000fcfd,
.gpdup_mask = 0xffffffff,
-
+ .gpdup_reg = S3C2410_GPDUP,
};
static struct pwm_lookup rx1950_pwm_lookup[] = {
@@ -377,6 +379,7 @@
};
static struct pwm_device *lcd_pwm;
+static struct pwm_state lcd_pwm_state;
static void rx1950_lcd_power(int enable)
{
@@ -429,15 +432,16 @@
/* GPB1->OUTPUT, GPB1->0 */
gpio_direction_output(S3C2410_GPB(1), 0);
- pwm_config(lcd_pwm, 0, LCD_PWM_PERIOD);
- pwm_disable(lcd_pwm);
+
+ lcd_pwm_state.enabled = false;
+ pwm_apply_state(lcd_pwm, &lcd_pwm_state);
/* GPC0->0, GPC10->0 */
gpio_direction_output(S3C2410_GPC(0), 0);
gpio_direction_output(S3C2410_GPC(10), 0);
} else {
- pwm_config(lcd_pwm, LCD_PWM_DUTY, LCD_PWM_PERIOD);
- pwm_enable(lcd_pwm);
+ lcd_pwm_state.enabled = true;
+ pwm_apply_state(lcd_pwm, &lcd_pwm_state);
gpio_direction_output(S3C2410_GPC(0), 1);
gpio_direction_output(S3C2410_GPC(5), 1);
@@ -493,10 +497,13 @@
}
/*
- * FIXME: pwm_apply_args() should be removed when switching to
- * the atomic PWM API.
+ * This is only required to initialize .polarity; all other values are
+ * fixed in this driver.
*/
- pwm_apply_args(lcd_pwm);
+ pwm_init_state(lcd_pwm, &lcd_pwm_state);
+
+ lcd_pwm_state.period = LCD_PWM_PERIOD;
+ lcd_pwm_state.duty_cycle = LCD_PWM_DUTY;
rx1950_lcd_power(1);
rx1950_bl_power(1);
@@ -529,7 +536,6 @@
static struct platform_pwm_backlight_data rx1950_backlight_data = {
.max_brightness = 24,
.dft_brightness = 4,
- .enable_gpio = -1,
.init = rx1950_backlight_init,
.notify = rx1950_backlight_notify,
.exit = rx1950_backlight_exit,
@@ -545,6 +551,8 @@
static void rx1950_set_mmc_power(unsigned char power_mode, unsigned short vdd)
{
+ s3c24xx_mci_def_set_power(power_mode, vdd);
+
switch (power_mode) {
case MMC_POWER_OFF:
gpio_direction_output(S3C2410_GPJ(1), 0);
@@ -570,6 +578,13 @@
GPIO_LOOKUP("GPIOF", 5, "cd", GPIO_ACTIVE_LOW),
/* Write protect S3C2410_GPH(8) */
GPIO_LOOKUP("GPIOH", 8, "wp", GPIO_ACTIVE_LOW),
+ /* bus pins */
+ GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
{ },
},
};
@@ -616,7 +631,7 @@
.twrph1 = 15,
.nr_sets = ARRAY_SIZE(rx1950_nand_sets),
.sets = rx1950_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {
@@ -724,6 +739,20 @@
},
};
+static struct gpiod_lookup_table rx1950_audio_gpio_table = {
+ .dev_id = "rx1950-audio",
+ .table = {
+ GPIO_LOOKUP("GPIOG", 12, "hp-gpio", GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP("GPIOA", 1, "speaker-power", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct platform_device rx1950_audio = {
+ .name = "rx1950-audio",
+ .id = -1,
+};
+
static struct platform_device *rx1950_devices[] __initdata = {
&s3c2410_device_dclk,
&s3c_device_lcd,
@@ -742,13 +771,14 @@
&power_supply,
&rx1950_battery,
&rx1950_leds,
+ &rx1950_audio,
};
static void __init rx1950_map_io(void)
{
s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
/* setup PM */
@@ -762,7 +792,7 @@
static void __init rx1950_init_time(void)
{
s3c2442_init_clocks(16934000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init rx1950_init_machine(void)
@@ -809,6 +839,10 @@
gpio_direction_output(S3C2410_GPJ(6), 0);
pwm_add_table(rx1950_pwm_lookup, ARRAY_SIZE(rx1950_pwm_lookup));
+ gpiod_add_lookup_table(&rx1950_audio_gpio_table);
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
i2c_register_board_info(0, rx1950_i2c_devices,
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c/mach-rx3715.c
similarity index 87%
rename from arch/arm/mach-s3c24xx/mach-rx3715.c
rename to arch/arm/mach-s3c/mach-rx3715.c
index 529c6fa..a03662a 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c/mach-rx3715.c
@@ -3,7 +3,7 @@
// Copyright (c) 2003-2004 Simtec Electronics
// Ben Dooks <ben@simtec.co.uk>
//
-// http://www.handhelds.org/projects/rx3715.html
+// https://www.handhelds.org/projects/rx3715.html
#include <linux/kernel.h>
#include <linux/types.h>
@@ -30,22 +30,20 @@
#include <asm/mach/map.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
+#include <linux/platform_data/fb-s3c2410.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/fb.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/pm.h>
-#include <plat/samsung-time.h>
+#include "cpu.h"
+#include "devs.h"
+#include "pm.h"
-#include "common.h"
+#include "s3c24xx.h"
#include "h1940.h"
static struct map_desc rx3715_iodesc[] __initdata = {
@@ -125,13 +123,17 @@
.gpccon = 0xaa955699,
.gpccon_mask = 0xffc003cc,
+ .gpccon_reg = S3C2410_GPCCON,
.gpcup = 0x0000ffff,
.gpcup_mask = 0xffffffff,
+ .gpcup_reg = S3C2410_GPCUP,
.gpdcon = 0xaa95aaa1,
.gpdcon_mask = 0xffc0fff0,
+ .gpdcon_reg = S3C2410_GPDCON,
.gpdup = 0x0000faff,
.gpdup_mask = 0xffffffff,
+ .gpdup_reg = S3C2410_GPDUP,
};
static struct mtd_partition __initdata rx3715_nand_part[] = {
@@ -158,7 +160,7 @@
.twrph1 = 15,
.nr_sets = ARRAY_SIZE(rx3715_nand_sets),
.sets = rx3715_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
static struct platform_device *rx3715_devices[] __initdata = {
@@ -174,13 +176,13 @@
{
s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init rx3715_init_time(void)
{
s3c2440_init_clocks(16934000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
/* H1940 and RX3715 need to reserve this for suspend */
@@ -199,6 +201,9 @@
s3c_nand_set_platdata(&rx3715_nand_info);
s3c24xx_fb_set_platdata(&rx3715_fb_info);
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
}
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c/mach-s3c2416-dt.c
similarity index 91%
rename from arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
rename to arch/arm/mach-s3c/mach-s3c2416-dt.c
index aa71027..418544d 100644
--- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
+++ b/arch/arm/mach-s3c/mach-s3c2416-dt.c
@@ -16,12 +16,12 @@
#include <linux/serial_s3c.h>
#include <asm/mach/arch.h>
-#include <mach/map.h>
+#include "map.h"
-#include <plat/cpu.h>
-#include <plat/pm.h>
+#include "cpu.h"
+#include "pm.h"
-#include "common.h"
+#include "s3c24xx.h"
static void __init s3c2416_dt_map_io(void)
{
diff --git a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c b/arch/arm/mach-s3c/mach-s3c64xx-dt.c
similarity index 70%
rename from arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
rename to arch/arm/mach-s3c/mach-s3c64xx-dt.c
index 1724f5e..00169c1 100644
--- a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
+++ b/arch/arm/mach-s3c/mach-s3c64xx-dt.c
@@ -8,11 +8,10 @@
#include <asm/mach/map.h>
#include <asm/system_misc.h>
-#include <plat/cpu.h>
-#include <mach/map.h>
+#include "cpu.h"
+#include "map.h"
-#include "common.h"
-#include "watchdog-reset.h"
+#include "s3c64xx.h"
/*
* IO mapping for shared system controller IP.
@@ -39,20 +38,6 @@
panic("SoC is not S3C64xx!");
}
-static void __init s3c64xx_dt_init_machine(void)
-{
- samsung_wdt_reset_of_init();
-}
-
-static void s3c64xx_dt_restart(enum reboot_mode mode, const char *cmd)
-{
- if (mode != REBOOT_SOFT)
- samsung_wdt_reset();
-
- /* if all else fails, or mode was for soft, jump to 0 */
- soft_restart(0);
-}
-
static const char *const s3c64xx_dt_compat[] __initconst = {
"samsung,s3c6400",
"samsung,s3c6410",
@@ -63,6 +48,4 @@
/* Maintainer: Tomasz Figa <tomasz.figa@gmail.com> */
.dt_compat = s3c64xx_dt_compat,
.map_io = s3c64xx_dt_map_io,
- .init_machine = s3c64xx_dt_init_machine,
- .restart = s3c64xx_dt_restart,
MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c/mach-smartq.c
similarity index 94%
rename from arch/arm/mach-s3c64xx/mach-smartq.c
rename to arch/arm/mach-s3c/mach-smartq.c
index 951208f..5b6e7c2 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c/mach-smartq.c
@@ -13,31 +13,29 @@
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/spi/spi_gpio.h>
-#include <linux/usb/gpio_vbus.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "map.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
+#include "cpu.h"
+#include "devs.h"
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
+#include "gpio-cfg.h"
#include <linux/platform_data/hwmon-s3c.h>
#include <linux/platform_data/usb-ohci-s3c2410.h>
-#include <plat/sdhci.h>
+#include "sdhci.h"
#include <linux/platform_data/touchscreen-s3c2410.h>
#include <video/platform_lcd.h>
-#include <plat/samsung-time.h>
-#include "common.h"
+#include "s3c64xx.h"
#include "mach-smartq.h"
-#include "regs-modem.h"
+#include "regs-modem-s3c64xx.h"
#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
@@ -124,15 +122,16 @@
.enable_oc = smartq_usb_host_enableoc,
};
-static struct gpio_vbus_mach_info smartq_usb_otg_vbus_pdata = {
- .gpio_vbus = S3C64XX_GPL(9),
- .gpio_pullup = -1,
- .gpio_vbus_inverted = true,
+static struct gpiod_lookup_table smartq_usb_otg_vbus_gpiod_table = {
+ .dev_id = "gpio-vbus",
+ .table = {
+ GPIO_LOOKUP("GPL", 9, "vbus", GPIO_ACTIVE_LOW),
+ { },
+ },
};
static struct platform_device smartq_usb_otg_vbus_dev = {
.name = "gpio-vbus",
- .dev.platform_data = &smartq_usb_otg_vbus_pdata,
};
static struct pwm_lookup smartq_pwm_lookup[] = {
@@ -150,7 +149,6 @@
static struct platform_pwm_backlight_data smartq_backlight_data = {
.max_brightness = 1000,
.dft_brightness = 600,
- .enable_gpio = -1,
.init = smartq_bl_init,
};
@@ -385,7 +383,7 @@
s3c64xx_set_xtal_freq(12000000);
s3c64xx_set_xusbxti_freq(12000000);
s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
smartq_lcd_mode_set();
}
@@ -418,6 +416,7 @@
pwm_add_table(smartq_pwm_lookup, ARRAY_SIZE(smartq_pwm_lookup));
gpiod_add_lookup_table(&smartq_lcd_control_gpiod_table);
+ gpiod_add_lookup_table(&smartq_usb_otg_vbus_gpiod_table);
platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices));
gpiod_add_lookup_table(&smartq_audio_gpios);
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.h b/arch/arm/mach-s3c/mach-smartq.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/mach-smartq.h
rename to arch/arm/mach-s3c/mach-smartq.h
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c/mach-smartq5.c
similarity index 91%
rename from arch/arm/mach-s3c64xx/mach-smartq5.c
rename to arch/arm/mach-s3c/mach-smartq5.c
index 44e9edb..8c94022 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c/mach-smartq5.c
@@ -15,17 +15,16 @@
#include <video/samsung_fimd.h>
#include <mach/irqs.h>
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "map.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/gpio-cfg.h>
-#include <plat/samsung-time.h>
+#include "cpu.h"
+#include "devs.h"
+#include "fb.h"
+#include "gpio-cfg.h"
-#include "common.h"
+#include "s3c64xx.h"
#include "mach-smartq.h"
static struct gpio_led smartq5_leds[] = {
@@ -151,6 +150,5 @@
.init_irq = s3c6410_init_irq,
.map_io = smartq_map_io,
.init_machine = smartq5_machine_init,
- .init_time = samsung_timer_init,
- .restart = s3c64xx_restart,
+ .init_time = s3c64xx_timer_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c/mach-smartq7.c
similarity index 92%
rename from arch/arm/mach-s3c64xx/mach-smartq7.c
rename to arch/arm/mach-s3c/mach-smartq7.c
index 815ee7d..ab24396 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c/mach-smartq7.c
@@ -15,17 +15,16 @@
#include <video/samsung_fimd.h>
#include <mach/irqs.h>
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "map.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/gpio-cfg.h>
-#include <plat/samsung-time.h>
+#include "cpu.h"
+#include "devs.h"
+#include "fb.h"
+#include "gpio-cfg.h"
-#include "common.h"
+#include "s3c64xx.h"
#include "mach-smartq.h"
static struct gpio_led smartq7_leds[] = {
@@ -167,6 +166,5 @@
.init_irq = s3c6410_init_irq,
.map_io = smartq_map_io,
.init_machine = smartq7_machine_init,
- .init_time = samsung_timer_init,
- .restart = s3c64xx_restart,
+ .init_time = s3c64xx_timer_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c/mach-smdk2410.c
similarity index 86%
rename from arch/arm/mach-s3c24xx/mach-smdk2410.c
rename to arch/arm/mach-s3c/mach-smdk2410.c
index 18dfef5..ca83d5a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c/mach-smdk2410.c
@@ -19,23 +19,23 @@
#include <linux/serial_s3c.h>
#include <linux/platform_device.h>
#include <linux/io.h>
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/samsung-time.h>
+#include "devs.h"
+#include "cpu.h"
-#include "common.h"
-#include "common-smdk.h"
+#include "s3c24xx.h"
+#include "common-smdk-s3c24xx.h"
static struct map_desc smdk2410_iodesc[] __initdata = {
/* nothing here yet */
@@ -81,19 +81,22 @@
{
s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init smdk2410_init_time(void)
{
s3c2410_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init smdk2410_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices));
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
smdk_machine_init();
}
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c/mach-smdk2413.c
similarity index 86%
rename from arch/arm/mach-s3c24xx/mach-smdk2413.c
rename to arch/arm/mach-s3c/mach-smdk2413.c
index ca80167..c43095b 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c/mach-smdk2413.c
@@ -23,27 +23,26 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
#include <asm/hardware/iomd.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
//#include <asm/debug-ll.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
+#include "hardware-s3c24xx.h"
+#include "regs-gpio.h"
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/gpio-samsung.h>
-#include <mach/fb.h>
+#include <linux/platform_data/fb-s3c2410.h>
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/samsung-time.h>
+#include "devs.h"
+#include "cpu.h"
-#include "common.h"
-#include "common-smdk.h"
+#include "s3c24xx.h"
+#include "common-smdk-s3c24xx.h"
static struct map_desc smdk2413_iodesc[] __initdata = {
};
@@ -99,13 +98,13 @@
{
s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init smdk2413_init_time(void)
{
s3c2412_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init smdk2413_machine_init(void)
@@ -119,6 +118,9 @@
s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
s3c_i2c0_set_platdata(NULL);
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
smdk_machine_init();
@@ -132,7 +134,7 @@
.init_irq = s3c2412_init_irq,
.map_io = smdk2413_map_io,
.init_machine = smdk2413_machine_init,
- .init_time = samsung_timer_init,
+ .init_time = s3c24xx_timer_init,
MACHINE_END
MACHINE_START(SMDK2412, "SMDK2412")
@@ -143,7 +145,7 @@
.init_irq = s3c2412_init_irq,
.map_io = smdk2413_map_io,
.init_machine = smdk2413_machine_init,
- .init_time = samsung_timer_init,
+ .init_time = s3c24xx_timer_init,
MACHINE_END
MACHINE_START(SMDK2413, "SMDK2413")
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c/mach-smdk2416.c
similarity index 93%
rename from arch/arm/mach-s3c24xx/mach-smdk2416.c
rename to arch/arm/mach-s3c/mach-smdk2416.c
index 61c3e45..4d883a7 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c/mach-smdk2416.c
@@ -25,31 +25,29 @@
#include <asm/mach/irq.h>
#include <video/samsung_fimd.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
-#include <mach/regs-s3c2443-clock.h>
-#include <mach/gpio-samsung.h>
+#include "hardware-s3c24xx.h"
+#include "regs-gpio.h"
+#include "regs-s3c2443-clock.h"
+#include "gpio-samsung.h"
#include <linux/platform_data/leds-s3c24xx.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
+#include "gpio-cfg.h"
+#include "devs.h"
+#include "cpu.h"
#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/sdhci.h>
+#include "sdhci.h"
#include <linux/platform_data/usb-s3c2410_udc.h>
#include <linux/platform_data/s3c-hsudc.h>
-#include <plat/samsung-time.h>
-#include <plat/fb.h>
+#include "fb.h"
-#include "common.h"
-#include "common-smdk.h"
+#include "s3c24xx.h"
+#include "common-smdk-s3c24xx.h"
static struct map_desc smdk2416_iodesc[] __initdata = {
/* ISA IO Space map (memory space selected by A24) */
@@ -215,14 +213,14 @@
static void __init smdk2416_init_time(void)
{
s3c2416_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init smdk2416_map_io(void)
{
s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init smdk2416_machine_init(void)
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c/mach-smdk2440.c
similarity index 87%
rename from arch/arm/mach-s3c24xx/mach-smdk2440.c
rename to arch/arm/mach-s3c/mach-smdk2440.c
index 7bafcd8..7f6fe0d 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c/mach-smdk2440.c
@@ -23,22 +23,21 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
-#include <mach/fb.h>
+#include <linux/platform_data/fb-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/samsung-time.h>
+#include "devs.h"
+#include "cpu.h"
-#include "common.h"
-#include "common-smdk.h"
+#include "s3c24xx.h"
+#include "common-smdk-s3c24xx.h"
static struct map_desc smdk2440_iodesc[] __initdata = {
/* ISA IO Space map (memory space selected by A24) */
@@ -137,6 +136,11 @@
.gpdcon_mask = 0xffffffff,
.gpdup = 0x0000faff,
.gpdup_mask = 0xffffffff,
+
+ .gpccon_reg = S3C2410_GPCCON,
+ .gpcup_reg = S3C2410_GPCUP,
+ .gpdcon_reg = S3C2410_GPDCON,
+ .gpdup_reg = S3C2410_GPDUP,
#endif
.lpcsel = ((0xCE6) & ~7) | 1<<4,
@@ -154,20 +158,22 @@
{
s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init smdk2440_init_time(void)
{
s3c2440_init_clocks(16934400);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init smdk2440_machine_init(void)
{
s3c24xx_fb_set_platdata(&smdk2440_fb_info);
s3c_i2c0_set_platdata(NULL);
-
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices));
smdk_machine_init();
}
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c/mach-smdk2443.c
similarity index 90%
rename from arch/arm/mach-s3c24xx/mach-smdk2443.c
rename to arch/arm/mach-s3c/mach-smdk2443.c
index 2358ed5..fc54c91 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c/mach-smdk2443.c
@@ -22,22 +22,19 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
+#include "regs-gpio.h"
-#include <mach/fb.h>
+#include <linux/platform_data/fb-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/samsung-time.h>
+#include "devs.h"
+#include "cpu.h"
-#include "common.h"
-#include "common-smdk.h"
+#include "s3c24xx.h"
+#include "common-smdk-s3c24xx.h"
static struct map_desc smdk2443_iodesc[] __initdata = {
/* ISA IO Space map (memory space selected by A24) */
@@ -112,13 +109,13 @@
{
s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init smdk2443_init_time(void)
{
s3c2443_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init smdk2443_machine_init(void)
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c/mach-smdk6400.c
similarity index 87%
rename from arch/arm/mach-s3c64xx/mach-smdk6400.c
rename to arch/arm/mach-s3c/mach-smdk6400.c
index cbd1684..8272213 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c/mach-smdk6400.c
@@ -23,16 +23,14 @@
#include <asm/mach/irq.h>
#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
+#include "map.h"
-#include <plat/devs.h>
-#include <plat/cpu.h>
+#include "devs.h"
+#include "cpu.h"
#include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/gpio-samsung.h>
-#include <plat/samsung-time.h>
+#include "gpio-samsung.h"
-#include "common.h"
+#include "s3c64xx.h"
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
@@ -62,7 +60,7 @@
s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
}
static struct platform_device *smdk6400_devices[] __initdata = {
@@ -88,6 +86,5 @@
.init_irq = s3c6400_init_irq,
.map_io = smdk6400_map_io,
.init_machine = smdk6400_machine_init,
- .init_time = samsung_timer_init,
- .restart = s3c64xx_restart,
+ .init_time = s3c64xx_timer_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c/mach-smdk6410.c
similarity index 96%
rename from arch/arm/mach-s3c64xx/mach-smdk6410.c
rename to arch/arm/mach-s3c/mach-smdk6410.c
index 908e5aa..ae18c13 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c/mach-smdk6410.c
@@ -45,32 +45,30 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
#include <mach/irqs.h>
-#include <mach/map.h>
+#include "map.h"
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
#include <linux/platform_data/ata-samsung_cf.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/fb.h>
-#include <plat/gpio-cfg.h>
+#include "fb.h"
+#include "gpio-cfg.h"
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/adc.h>
+#include "devs.h"
+#include "cpu.h"
+#include <linux/soc/samsung/s3c-adc.h>
#include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/keypad.h>
-#include <plat/samsung-time.h>
+#include "keypad.h"
-#include "backlight.h"
-#include "common.h"
-#include "regs-modem.h"
-#include "regs-srom.h"
-#include "regs-sys.h"
+#include "backlight-s3c64xx.h"
+#include "s3c64xx.h"
+#include "regs-modem-s3c64xx.h"
+#include "regs-srom-s3c64xx.h"
+#include "regs-sys-s3c64xx.h"
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
@@ -623,7 +621,7 @@
};
static struct platform_pwm_backlight_data smdk6410_bl_data = {
- .enable_gpio = -1,
+ /* Intentionally blank */
};
static struct dwc2_hsotg_plat smdk6410_hsotg_pdata;
@@ -635,7 +633,7 @@
s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
/* set the LCD type */
@@ -704,6 +702,5 @@
.init_irq = s3c6410_init_irq,
.map_io = smdk6410_map_io,
.init_machine = smdk6410_machine_init,
- .init_time = samsung_timer_init,
- .restart = s3c64xx_restart,
+ .init_time = s3c64xx_timer_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c/mach-tct_hammer.c
similarity index 81%
rename from arch/arm/mach-s3c24xx/mach-tct_hammer.c
rename to arch/arm/mach-s3c/mach-tct_hammer.c
index 8d8ddd6..2a61df3 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c/mach-tct_hammer.c
@@ -7,6 +7,7 @@
// derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by
// Ben Dooks <ben@simtec.co.uk>
+#include <linux/gpio/machine.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
@@ -24,21 +25,19 @@
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
+#include "devs.h"
+#include "cpu.h"
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/map.h>
#include <linux/mtd/physmap.h>
-#include <plat/samsung-time.h>
-#include "common.h"
+#include "s3c24xx.h"
static struct resource tct_hammer_nor_resource =
DEFINE_RES_MEM(0x00000000, SZ_16M);
@@ -103,6 +102,19 @@
}
};
+static struct gpiod_lookup_table tct_hammer_mmc_gpio_table = {
+ .dev_id = "s3c2410-sdi",
+ .table = {
+ /* bus pins */
+ GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH),
+ GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
static struct platform_device *tct_hammer_devices[] __initdata = {
&s3c_device_adc,
@@ -119,18 +131,19 @@
{
s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init tct_hammer_init_time(void)
{
s3c2410_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init tct_hammer_init(void)
{
s3c_i2c0_set_platdata(NULL);
+ gpiod_add_lookup_table(&tct_hammer_mmc_gpio_table);
platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
}
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c/mach-vr1000.c
similarity index 87%
rename from arch/arm/mach-s3c24xx/mach-vr1000.c
rename to arch/arm/mach-s3c/mach-vr1000.c
index 853e74f..5c3d07c 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c/mach-vr1000.c
@@ -13,6 +13,7 @@
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
+#include <linux/gpio/machine.h>
#include <linux/dm9000.h>
#include <linux/i2c.h>
@@ -34,16 +35,15 @@
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/asoc-s3c24xx_simtec.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/samsung-time.h>
+#include "cpu.h"
+#include "devs.h"
#include "bast.h"
-#include "common.h"
+#include "s3c24xx.h"
#include "simtec.h"
#include "vr1000.h"
@@ -223,21 +223,42 @@
/* LEDS */
+static struct gpiod_lookup_table vr1000_led1_gpio_table = {
+ .dev_id = "s3c24xx_led.1",
+ .table = {
+ GPIO_LOOKUP("GPB", 0, NULL, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table vr1000_led2_gpio_table = {
+ .dev_id = "s3c24xx_led.2",
+ .table = {
+ GPIO_LOOKUP("GPB", 1, NULL, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
+static struct gpiod_lookup_table vr1000_led3_gpio_table = {
+ .dev_id = "s3c24xx_led.3",
+ .table = {
+ GPIO_LOOKUP("GPB", 2, NULL, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static struct s3c24xx_led_platdata vr1000_led1_pdata = {
.name = "led1",
- .gpio = S3C2410_GPB(0),
.def_trigger = "",
};
static struct s3c24xx_led_platdata vr1000_led2_pdata = {
.name = "led2",
- .gpio = S3C2410_GPB(1),
.def_trigger = "",
};
static struct s3c24xx_led_platdata vr1000_led3_pdata = {
.name = "led3",
- .gpio = S3C2410_GPB(2),
.def_trigger = "",
};
@@ -305,18 +326,27 @@
s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init vr1000_init_time(void)
{
s3c2410_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init vr1000_init(void)
{
s3c_i2c0_set_platdata(NULL);
+
+ /* Disable pull-up on LED lines and register GPIO lookups */
+ s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_NONE);
+ s3c_gpio_setpull(S3C2410_GPB(2), S3C_GPIO_PULL_NONE);
+ gpiod_add_lookup_table(&vr1000_led1_gpio_table);
+ gpiod_add_lookup_table(&vr1000_led2_gpio_table);
+ gpiod_add_lookup_table(&vr1000_led3_gpio_table);
+
platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
i2c_register_board_info(0, vr1000_i2c_devs,
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c/mach-vstms.c
similarity index 87%
rename from arch/arm/mach-s3c24xx/mach-vstms.c
rename to arch/arm/mach-s3c/mach-vstms.c
index d76b28b..05f19f5 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c/mach-vstms.c
@@ -24,24 +24,23 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-lcd.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
-#include <mach/fb.h>
+#include <linux/platform_data/fb-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/samsung-time.h>
+#include "devs.h"
+#include "cpu.h"
-#include "common.h"
+#include "s3c24xx.h"
static struct map_desc vstms_iodesc[] __initdata = {
};
@@ -112,7 +111,7 @@
.twrph1 = 20,
.nr_sets = ARRAY_SIZE(vstms_nand_sets),
.sets = vstms_nand_sets,
- .ecc_mode = NAND_ECC_SOFT,
+ .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
};
static struct platform_device *vstms_devices[] __initdata = {
@@ -136,20 +135,22 @@
{
s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
+ s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
}
static void __init vstms_init_time(void)
{
s3c2412_init_clocks(12000000);
- samsung_timer_init();
+ s3c24xx_timer_init();
}
static void __init vstms_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_nand_set_platdata(&vstms_nand_info);
-
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
}
diff --git a/arch/arm/plat-samsung/include/plat/map-s3c.h b/arch/arm/mach-s3c/map-s3c.h
similarity index 87%
rename from arch/arm/plat-samsung/include/plat/map-s3c.h
rename to arch/arm/mach-s3c/map-s3c.h
index 4244acb..a18fdd3 100644
--- a/arch/arm/plat-samsung/include/plat/map-s3c.h
+++ b/arch/arm/mach-s3c/map-s3c.h
@@ -9,6 +9,8 @@
#ifndef __ASM_PLAT_MAP_S3C_H
#define __ASM_PLAT_MAP_S3C_H __FILE__
+#include "map.h"
+
#define S3C24XX_VA_IRQ S3C_VA_IRQ
#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
#define S3C24XX_VA_UART S3C_VA_UART
@@ -45,16 +47,8 @@
#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
-/*
- * ISA style IO, for each machine to sort out mappings for,
- * if it implements it. We reserve two 16M regions for ISA.
- */
-
#define S3C2410_ADDR(x) S3C_ADDR(x)
-#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
-#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
-
/* deal with the registers that move under the 2412/2413 */
#if defined(CONFIG_CPU_S3C2412)
@@ -71,6 +65,6 @@
#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
#endif
-#include <plat/map-s5p.h>
+#include "map-s5p.h"
#endif /* __ASM_PLAT_MAP_S3C_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c/map-s3c24xx.h
similarity index 96%
rename from arch/arm/mach-s3c24xx/include/mach/map.h
rename to arch/arm/mach-s3c/map-s3c24xx.h
index bca9311..b5dba78 100644
--- a/arch/arm/mach-s3c24xx/include/mach/map.h
+++ b/arch/arm/mach-s3c/map-s3c24xx.h
@@ -9,8 +9,8 @@
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H
-#include <plat/map-base.h>
-#include <plat/map-s3c.h>
+#include <mach/map-base.h>
+#include "map-s3c.h"
/*
* interrupt controller is the first thing we put in, to make
@@ -86,6 +86,8 @@
#define S3C2410_PA_SPI (0x59000000)
#define S3C2443_PA_SPI0 (0x52000000)
#define S3C2443_PA_SPI1 S3C2410_PA_SPI
+#define S3C2410_SPI1 (0x20)
+#define S3C2412_SPI1 (0x100)
/* SDI */
#define S3C2410_PA_SDI (0x5A000000)
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c/map-s3c64xx.h
similarity index 97%
rename from arch/arm/mach-s3c64xx/include/mach/map.h
rename to arch/arm/mach-s3c/map-s3c64xx.h
index 9372a53..d7740d2 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c/map-s3c64xx.h
@@ -11,8 +11,8 @@
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
-#include <plat/map-base.h>
-#include <plat/map-s3c.h>
+#include <mach/map-base.h>
+#include "map-s3c.h"
/*
* Post-mux Chip Select Regions Xm0CSn_
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/mach-s3c/map-s5p.h
similarity index 85%
rename from arch/arm/plat-samsung/include/plat/map-s5p.h
rename to arch/arm/mach-s3c/map-s5p.h
index d69a0ca..cd23792 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/mach-s3c/map-s5p.h
@@ -9,14 +9,12 @@
#ifndef __ASM_PLAT_MAP_S5P_H
#define __ASM_PLAT_MAP_S5P_H __FILE__
-#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
-
#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
#define VA_VIC0 VA_VIC(0)
#define VA_VIC1 VA_VIC(1)
#define VA_VIC2 VA_VIC(2)
#define VA_VIC3 VA_VIC(3)
-#include <plat/map-s3c.h>
+#include "map-s3c.h"
#endif /* __ASM_PLAT_MAP_S5P_H */
diff --git a/arch/arm/mach-s3c/map.h b/arch/arm/mach-s3c/map.h
new file mode 100644
index 0000000..7cfb517
--- /dev/null
+++ b/arch/arm/mach-s3c/map.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_ARCH_S3C24XX
+#include "map-s3c24xx.h"
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+#include "map-s3c64xx.h"
+#endif
diff --git a/arch/arm/mach-s3c24xx/nand-core.h b/arch/arm/mach-s3c/nand-core-s3c24xx.h
similarity index 77%
rename from arch/arm/mach-s3c24xx/nand-core.h
rename to arch/arm/mach-s3c/nand-core-s3c24xx.h
index 8de633d..a143167 100644
--- a/arch/arm/mach-s3c24xx/nand-core.h
+++ b/arch/arm/mach-s3c/nand-core-s3c24xx.h
@@ -6,8 +6,8 @@
* S3C - Nand Controller core functions
*/
-#ifndef __ASM_ARCH_NAND_CORE_H
-#define __ASM_ARCH_NAND_CORE_H __FILE__
+#ifndef __ASM_ARCH_NAND_CORE_S3C24XX_H
+#define __ASM_ARCH_NAND_CORE_S3C24XX_H __FILE__
/* These functions are only for use with the core support code, such as
* the cpu specific initialisation code
@@ -21,4 +21,4 @@
#endif
}
-#endif /* __ASM_ARCH_NAND_CORE_H */
+#endif /* __ASM_ARCH_NAND_CORE_S3C24XX_H */
diff --git a/arch/arm/mach-s3c64xx/onenand-core.h b/arch/arm/mach-s3c/onenand-core-s3c64xx.h
similarity index 82%
rename from arch/arm/mach-s3c64xx/onenand-core.h
rename to arch/arm/mach-s3c/onenand-core-s3c64xx.h
index 0cf6b5e..e2dfdd1 100644
--- a/arch/arm/mach-s3c64xx/onenand-core.h
+++ b/arch/arm/mach-s3c/onenand-core-s3c64xx.h
@@ -7,8 +7,8 @@
* Samsung OneNAD Controller core functions
*/
-#ifndef __ASM_ARCH_ONENAND_CORE_H
-#define __ASM_ARCH_ONENAND_CORE_H __FILE__
+#ifndef __ASM_ARCH_ONENAND_CORE_S3C64XX_H
+#define __ASM_ARCH_ONENAND_CORE_S3C64XX_H __FILE__
/* These functions are only for use with the core support code, such as
* the cpu specific initialisation code
@@ -29,4 +29,4 @@
#endif
}
-#endif /* __ASM_ARCH_ONENAND_CORE_H */
+#endif /* __ASM_ARCH_ONENAND_CORE_S3C64XX_H */
diff --git a/arch/arm/mach-s3c24xx/osiris.h b/arch/arm/mach-s3c/osiris.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/osiris.h
rename to arch/arm/mach-s3c/osiris.h
diff --git a/arch/arm/mach-s3c24xx/otom.h b/arch/arm/mach-s3c/otom.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/otom.h
rename to arch/arm/mach-s3c/otom.h
diff --git a/arch/arm/mach-s3c64xx/pl080.c b/arch/arm/mach-s3c/pl080.c
similarity index 98%
rename from arch/arm/mach-s3c64xx/pl080.c
rename to arch/arm/mach-s3c/pl080.c
index 152edbe..4730f08 100644
--- a/arch/arm/mach-s3c64xx/pl080.c
+++ b/arch/arm/mach-s3c/pl080.c
@@ -10,11 +10,11 @@
#include <linux/amba/pl08x.h>
#include <linux/of.h>
-#include <plat/cpu.h>
+#include "cpu.h"
#include <mach/irqs.h>
-#include <mach/map.h>
+#include "map.h"
-#include "regs-sys.h"
+#include "regs-sys-s3c64xx.h"
static int pl08x_get_xfer_signal(const struct pl08x_channel_data *cd)
{
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/mach-s3c/platformdata.c
similarity index 95%
rename from arch/arm/plat-samsung/platformdata.c
rename to arch/arm/mach-s3c/platformdata.c
index cbc3b4b..e643c81 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/mach-s3c/platformdata.c
@@ -9,8 +9,8 @@
#include <linux/string.h>
#include <linux/platform_device.h>
-#include <plat/devs.h>
-#include <plat/sdhci.h>
+#include "devs.h"
+#include "sdhci.h"
void __init *s3c_set_platdata(void *pd, size_t pdsize,
struct platform_device *pdev)
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c/pll-s3c2410.c
similarity index 97%
rename from arch/arm/mach-s3c24xx/pll-s3c2410.c
rename to arch/arm/mach-s3c/pll-s3c2410.c
index 0561f79..3fbc99e 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2410.c
+++ b/arch/arm/mach-s3c/pll-s3c2410.c
@@ -15,8 +15,8 @@
#include <linux/clk.h>
#include <linux/err.h>
-#include <plat/cpu.h>
-#include <plat/cpu-freq-core.h>
+#include <linux/soc/samsung/s3c-cpufreq-core.h>
+#include <linux/soc/samsung/s3c-pm.h>
/* This array should be sorted in ascending order of the frequencies */
static struct cpufreq_frequency_table pll_vals_12MHz[] = {
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c/pll-s3c2440-12000000.c
similarity index 97%
rename from arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
rename to arch/arm/mach-s3c/pll-s3c2440-12000000.c
index 2ec3a2f..fdb8e8c 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
+++ b/arch/arm/mach-s3c/pll-s3c2440-12000000.c
@@ -13,8 +13,8 @@
#include <linux/clk.h>
#include <linux/err.h>
-#include <plat/cpu.h>
-#include <plat/cpu-freq-core.h>
+#include <linux/soc/samsung/s3c-cpufreq-core.h>
+#include <linux/soc/samsung/s3c-pm.h>
/* This array should be sorted in ascending order of the frequencies */
static struct cpufreq_frequency_table s3c2440_plls_12[] = {
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c/pll-s3c2440-16934400.c
similarity index 98%
rename from arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
rename to arch/arm/mach-s3c/pll-s3c2440-16934400.c
index 4b3d9e3..438b6fc 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
+++ b/arch/arm/mach-s3c/pll-s3c2440-16934400.c
@@ -13,8 +13,8 @@
#include <linux/clk.h>
#include <linux/err.h>
-#include <plat/cpu.h>
-#include <plat/cpu-freq-core.h>
+#include <linux/soc/samsung/s3c-cpufreq-core.h>
+#include <linux/soc/samsung/s3c-pm.h>
/* This array should be sorted in ascending order of the frequencies */
static struct cpufreq_frequency_table s3c2440_plls_169344[] = {
diff --git a/arch/arm/plat-samsung/pm-common.c b/arch/arm/mach-s3c/pm-common.c
similarity index 94%
rename from arch/arm/plat-samsung/pm-common.c
rename to arch/arm/mach-s3c/pm-common.c
index 59a10c6..618bd44 100644
--- a/arch/arm/plat-samsung/pm-common.c
+++ b/arch/arm/mach-s3c/pm-common.c
@@ -12,7 +12,7 @@
#include <linux/io.h>
#include <linux/kernel.h>
-#include <plat/pm-common.h>
+#include "pm-common.h"
/* helper functions to save and restore register state */
@@ -55,6 +55,8 @@
/**
* s3c_pm_do_restore_core() - early restore register values from save list.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
*
* This is similar to s3c_pm_do_restore() except we try and minimise the
* side effects of the function in case registers that hardware might need
diff --git a/arch/arm/mach-s3c/pm-common.h b/arch/arm/mach-s3c/pm-common.h
new file mode 100644
index 0000000..18b9607
--- /dev/null
+++ b/arch/arm/mach-s3c/pm-common.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Tomasz Figa <t.figa@samsung.com>
+ * Copyright (c) 2004 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Written by Ben Dooks, <ben@simtec.co.uk>
+ */
+
+#ifndef __PLAT_SAMSUNG_PM_COMMON_H
+#define __PLAT_SAMSUNG_PM_COMMON_H __FILE__
+
+#include <linux/irq.h>
+#include <linux/soc/samsung/s3c-pm.h>
+
+/* sleep save info */
+
+/**
+ * struct sleep_save - save information for shared peripherals.
+ * @reg: Pointer to the register to save.
+ * @val: Holder for the value saved from reg.
+ *
+ * This describes a list of registers which is used by the pm core and
+ * other subsystem to save and restore register values over suspend.
+ */
+struct sleep_save {
+ void __iomem *reg;
+ unsigned long val;
+};
+
+#define SAVE_ITEM(x) \
+ { .reg = (x) }
+
+/* helper functions to save/restore lists of registers. */
+
+extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count);
+
+#endif
diff --git a/arch/arm/mach-s3c24xx/include/mach/pm-core.h b/arch/arm/mach-s3c/pm-core-s3c24xx.h
similarity index 94%
rename from arch/arm/mach-s3c24xx/include/mach/pm-core.h
rename to arch/arm/mach-s3c/pm-core-s3c24xx.h
index 5e4ce89..bcb7978 100644
--- a/arch/arm/mach-s3c24xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c/pm-core-s3c24xx.h
@@ -11,10 +11,12 @@
#include <linux/io.h>
#include "regs-clock.h"
-#include "regs-irq.h"
+#include "regs-irq-s3c24xx.h"
+#include <mach/irqs.h>
static inline void s3c_pm_debug_init_uart(void)
{
+#ifdef CONFIG_SAMSUNG_PM_DEBUG
unsigned long tmp = __raw_readl(S3C2410_CLKCON);
/* re-start uart clocks */
@@ -24,6 +26,7 @@
__raw_writel(tmp, S3C2410_CLKCON);
udelay(10);
+#endif
}
static inline void s3c_pm_arch_prepare_irqs(void)
@@ -75,11 +78,6 @@
s3c_irqwake_eintmask);
}
-static inline void s3c_pm_arch_update_uart(void __iomem *regs,
- struct pm_uart_save *save)
-{
-}
-
static inline void s3c_pm_restored_gpios(void) { }
static inline void samsung_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s3c/pm-core-s3c64xx.h b/arch/arm/mach-s3c/pm-core-s3c64xx.h
new file mode 100644
index 0000000..06f564e
--- /dev/null
+++ b/arch/arm/mach-s3c/pm-core-s3c64xx.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
+ */
+
+#ifndef __MACH_S3C64XX_PM_CORE_H
+#define __MACH_S3C64XX_PM_CORE_H __FILE__
+
+#include <linux/serial_s3c.h>
+#include <linux/delay.h>
+
+#include "regs-gpio.h"
+#include "regs-clock.h"
+#include "map.h"
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+#ifdef CONFIG_SAMSUNG_PM_DEBUG
+ u32 tmp = __raw_readl(S3C_PCLK_GATE);
+
+ /* As a note, since the S3C64XX UARTs generally have multiple
+ * clock sources, we simply enable PCLK at the moment and hope
+ * that the resume settings for the UART are suitable for the
+ * use with PCLK.
+ */
+
+ tmp |= S3C_CLKCON_PCLK_UART0;
+ tmp |= S3C_CLKCON_PCLK_UART1;
+ tmp |= S3C_CLKCON_PCLK_UART2;
+ tmp |= S3C_CLKCON_PCLK_UART3;
+
+ __raw_writel(tmp, S3C_PCLK_GATE);
+ udelay(10);
+#endif
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+ /* VIC should have already been taken care of */
+
+ /* clear any pending EINT0 interrupts */
+ __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+}
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+}
+
+/* make these defines, we currently do not have any need to change
+ * the IRQ wake controls depending on the CPU we are running on */
+#ifdef CONFIG_PM_SLEEP
+#define s3c_irqwake_eintallow ((1 << 28) - 1)
+#define s3c_irqwake_intallow (~0)
+#else
+#define s3c_irqwake_eintallow 0
+#define s3c_irqwake_intallow 0
+#endif
+
+static inline void s3c_pm_restored_gpios(void)
+{
+ /* ensure sleep mode has been cleared from the system */
+
+ __raw_writel(0, S3C64XX_SLPEN);
+}
+
+static inline void samsung_pm_saved_gpios(void)
+{
+ /* turn on the sleep mode and keep it there, as it seems that during
+ * suspend the xCON registers get re-set and thus you can end up with
+ * problems between going to sleep and resuming.
+ */
+
+ __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
+}
+#endif /* __MACH_S3C64XX_PM_CORE_H */
diff --git a/arch/arm/mach-s3c/pm-core.h b/arch/arm/mach-s3c/pm-core.h
new file mode 100644
index 0000000..b0e1d27
--- /dev/null
+++ b/arch/arm/mach-s3c/pm-core.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_ARCH_S3C24XX
+#include "pm-core-s3c24xx.h"
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+#include "pm-core-s3c64xx.h"
+#endif
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/mach-s3c/pm-gpio.c
similarity index 98%
rename from arch/arm/plat-samsung/pm-gpio.c
rename to arch/arm/mach-s3c/pm-gpio.c
index cb2e3bc..cfdbc23 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/mach-s3c/pm-gpio.c
@@ -13,10 +13,10 @@
#include <linux/io.h>
#include <linux/gpio.h>
-#include <mach/gpio-samsung.h>
+#include "gpio-samsung.h"
-#include <plat/gpio-core.h>
-#include <plat/pm.h>
+#include "gpio-core.h"
+#include "pm.h"
/* PM GPIO helpers */
diff --git a/arch/arm/mach-s3c24xx/pm-h1940.S b/arch/arm/mach-s3c/pm-h1940.S
similarity index 80%
rename from arch/arm/mach-s3c24xx/pm-h1940.S
rename to arch/arm/mach-s3c/pm-h1940.S
index a7bbe33..3bf6685 100644
--- a/arch/arm/mach-s3c24xx/pm-h1940.S
+++ b/arch/arm/mach-s3c/pm-h1940.S
@@ -7,10 +7,9 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
+#include "map.h"
-#include <mach/regs-gpio.h>
+#include "regs-gpio.h"
.text
.global h1940_pm_return
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c/pm-s3c2410.c
similarity index 95%
rename from arch/arm/mach-s3c24xx/pm-s3c2410.c
rename to arch/arm/mach-s3c/pm-s3c2410.c
index 2d8ea70..a664198 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2410.c
+++ b/arch/arm/mach-s3c/pm-s3c2410.c
@@ -16,13 +16,12 @@
#include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include <plat/gpio-cfg.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
+#include "gpio-cfg.h"
+#include "cpu.h"
+#include "pm.h"
#include "h1940.h"
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c/pm-s3c2412.c
similarity index 94%
rename from arch/arm/mach-s3c24xx/pm-s3c2412.c
rename to arch/arm/mach-s3c/pm-s3c2412.c
index 2dfdaab..6a96044 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c/pm-s3c2412.c
@@ -19,14 +19,14 @@
#include <asm/cacheflush.h>
#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
+#include <mach/irqs.h>
+#include "regs-gpio.h"
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/wakeup-mask.h>
+#include "cpu.h"
+#include "pm.h"
+#include "wakeup-mask.h"
-#include "regs-dsc.h"
+#include "regs-dsc-s3c24xx.h"
#include "s3c2412-power.h"
extern void s3c2412_sleep_enter(void);
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c/pm-s3c2416.c
similarity index 95%
rename from arch/arm/mach-s3c24xx/pm-s3c2416.c
rename to arch/arm/mach-s3c/pm-s3c2416.c
index 9a2f05e..f69ad84 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2416.c
+++ b/arch/arm/mach-s3c/pm-s3c2416.c
@@ -11,10 +11,10 @@
#include <asm/cacheflush.h>
-#include <mach/regs-s3c2443-clock.h>
+#include "regs-s3c2443-clock.h"
-#include <plat/cpu.h>
-#include <plat/pm.h>
+#include "cpu.h"
+#include "pm.h"
#include "s3c2412-power.h"
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c/pm-s3c24xx.c
similarity index 92%
rename from arch/arm/mach-s3c24xx/pm.c
rename to arch/arm/mach-s3c/pm-s3c24xx.c
index c64988c..3a8f5c3 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c/pm-s3c24xx.c
@@ -21,17 +21,17 @@
#include <linux/serial_s3c.h>
#include <linux/io.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-irq.h>
-#include <mach/gpio-samsung.h>
+#include "regs-clock.h"
+#include "regs-gpio.h"
+#include "regs-irq.h"
+#include "gpio-samsung.h"
#include <asm/mach/time.h>
-#include <plat/gpio-cfg.h>
-#include <plat/pm.h>
+#include "gpio-cfg.h"
+#include "pm.h"
-#include "regs-mem.h"
+#include "regs-mem-s3c24xx.h"
#define PFX "s3c24xx-pm: "
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c/pm-s3c64xx.c
similarity index 81%
rename from arch/arm/mach-s3c64xx/pm.c
rename to arch/arm/mach-s3c/pm-s3c64xx.c
index fd6dbb2..4f17781 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c/pm-s3c64xx.c
@@ -14,22 +14,22 @@
#include <linux/gpio.h>
#include <linux/pm_domain.h>
-#include <mach/map.h>
+#include "map.h"
#include <mach/irqs.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/pm.h>
-#include <plat/wakeup-mask.h>
+#include "cpu.h"
+#include "devs.h"
+#include "pm.h"
+#include "wakeup-mask.h"
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "regs-clock.h"
+#include "gpio-samsung.h"
-#include "regs-gpio-memport.h"
-#include "regs-modem.h"
-#include "regs-sys.h"
-#include "regs-syscon-power.h"
+#include "regs-gpio-memport-s3c64xx.h"
+#include "regs-modem-s3c64xx.h"
+#include "regs-sys-s3c64xx.h"
+#include "regs-syscon-power-s3c64xx.h"
struct s3c64xx_pm_domain {
char *const name;
@@ -305,6 +305,56 @@
__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
}
+#ifdef CONFIG_SAMSUNG_PM_DEBUG
+void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save)
+{
+ u32 ucon;
+ u32 ucon_clk
+ u32 save_clk;
+ u32 new_ucon;
+ u32 delta;
+
+ if (!soc_is_s3c64xx())
+ return;
+
+ ucon = __raw_readl(regs + S3C2410_UCON);
+ ucon_clk = ucon & S3C6400_UCON_CLKMASK;
+ sav_clk = save->ucon & S3C6400_UCON_CLKMASK;
+
+ /* S3C64XX UART blocks only support level interrupts, so ensure that
+ * when we restore unused UART blocks we force the level interrupt
+ * settigs. */
+ save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
+
+ /* We have a constraint on changing the clock type of the UART
+ * between UCLKx and PCLK, so ensure that when we restore UCON
+ * that the CLK field is correctly modified if the bootloader
+ * has changed anything.
+ */
+ if (ucon_clk != save_clk) {
+ new_ucon = save->ucon;
+ delta = ucon_clk ^ save_clk;
+
+ /* change from UCLKx => wrong PCLK,
+ * either UCLK can be tested for by a bit-test
+ * with UCLK0 */
+ if (ucon_clk & S3C6400_UCON_UCLK0 &&
+ !(save_clk & S3C6400_UCON_UCLK0) &&
+ delta & S3C6400_UCON_PCLK2) {
+ new_ucon &= ~S3C6400_UCON_UCLK0;
+ } else if (delta == S3C6400_UCON_PCLK2) {
+ /* as an precaution, don't change from
+ * PCLK2 => PCLK or vice-versa */
+ new_ucon ^= S3C6400_UCON_PCLK2;
+ }
+
+ S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
+ ucon, new_ucon, save->ucon);
+ save->ucon = new_ucon;
+ }
+}
+#endif
+
int __init s3c64xx_pm_init(void)
{
int i;
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/mach-s3c/pm.c
similarity index 93%
rename from arch/arm/plat-samsung/pm.c
rename to arch/arm/mach-s3c/pm.c
index d6bfd66..c563bb9 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/mach-s3c/pm.c
@@ -18,15 +18,16 @@
#include <asm/cacheflush.h>
#include <asm/suspend.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-irq.h>
+#include "map.h"
+#include "regs-clock.h"
+#include "regs-irq.h"
#include <mach/irqs.h>
#include <asm/irq.h>
-#include <plat/pm.h>
-#include <mach/pm-core.h>
+#include "cpu.h"
+#include "pm.h"
+#include "pm-core.h"
/* for external use */
@@ -70,8 +71,7 @@
{
int ret;
/* ensure the debug is initialised (if enabled) */
-
- s3c_pm_debug_init();
+ s3c_pm_debug_init_uart();
S3C_PMDBG("%s(%d)\n", __func__, state);
@@ -100,7 +100,7 @@
samsung_pm_saved_gpios();
}
- s3c_pm_save_uarts();
+ s3c_pm_save_uarts(soc_is_s3c2410());
s3c_pm_save_core();
/* set the irq configuration for wake */
@@ -137,14 +137,14 @@
/* restore the system state */
s3c_pm_restore_core();
- s3c_pm_restore_uarts();
+ s3c_pm_restore_uarts(soc_is_s3c2410());
if (!of_have_populated_dt()) {
samsung_pm_restore_gpios();
s3c_pm_restored_gpios();
}
- s3c_pm_debug_init();
+ s3c_pm_debug_init_uart();
/* check what irq (if any) restored the system */
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/mach-s3c/pm.h
similarity index 98%
rename from arch/arm/plat-samsung/include/plat/pm.h
rename to arch/arm/mach-s3c/pm.h
index 2746137..eed61e5 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/mach-s3c/pm.h
@@ -11,7 +11,7 @@
* management
*/
-#include <plat/pm-common.h>
+#include "pm-common.h"
struct device;
diff --git a/arch/arm/plat-samsung/include/plat/pwm-core.h b/arch/arm/mach-s3c/pwm-core.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/pwm-core.h
rename to arch/arm/mach-s3c/pwm-core.h
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/mach-s3c/regs-adc.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/regs-adc.h
rename to arch/arm/mach-s3c/regs-adc.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h b/arch/arm/mach-s3c/regs-clock-s3c24xx.h
similarity index 98%
rename from arch/arm/mach-s3c24xx/include/mach/regs-clock.h
rename to arch/arm/mach-s3c/regs-clock-s3c24xx.h
index 7ca3dd4..933ddb5 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c/regs-clock-s3c24xx.h
@@ -9,6 +9,8 @@
#ifndef __ASM_ARM_REGS_CLOCK
#define __ASM_ARM_REGS_CLOCK
+#include "map.h"
+
#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c/regs-clock-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/include/mach/regs-clock.h
rename to arch/arm/mach-s3c/regs-clock-s3c64xx.h
diff --git a/arch/arm/mach-s3c/regs-clock.h b/arch/arm/mach-s3c/regs-clock.h
new file mode 100644
index 0000000..7df31f2
--- /dev/null
+++ b/arch/arm/mach-s3c/regs-clock.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_ARCH_S3C24XX
+#include "regs-clock-s3c24xx.h"
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+#include "regs-clock-s3c64xx.h"
+#endif
diff --git a/arch/arm/mach-s3c24xx/regs-dsc.h b/arch/arm/mach-s3c/regs-dsc-s3c24xx.h
similarity index 76%
rename from arch/arm/mach-s3c24xx/regs-dsc.h
rename to arch/arm/mach-s3c/regs-dsc-s3c24xx.h
index b500636..8b8b572 100644
--- a/arch/arm/mach-s3c24xx/regs-dsc.h
+++ b/arch/arm/mach-s3c/regs-dsc-s3c24xx.h
@@ -7,8 +7,8 @@
*/
-#ifndef __ASM_ARCH_REGS_DSC_H
-#define __ASM_ARCH_REGS_DSC_H __FILE__
+#ifndef __ASM_ARCH_REGS_DSC_S3C24XX_H
+#define __ASM_ARCH_REGS_DSC_S3C24XX_H __FILE__
/* S3C2412 */
#define S3C2412_DSC0 S3C2410_GPIOREG(0xdc)
@@ -18,5 +18,5 @@
#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8)
-#endif /* __ASM_ARCH_REGS_DSC_H */
+#endif /* __ASM_ARCH_REGS_DSC_S3C24XX_H */
diff --git a/arch/arm/mach-s3c64xx/regs-gpio-memport.h b/arch/arm/mach-s3c/regs-gpio-memport-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/regs-gpio-memport.h
rename to arch/arm/mach-s3c/regs-gpio-memport-s3c64xx.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c/regs-gpio-s3c24xx.h
similarity index 99%
rename from arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
rename to arch/arm/mach-s3c/regs-gpio-s3c24xx.h
index 594e967..9a7e262 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c/regs-gpio-s3c24xx.h
@@ -10,6 +10,8 @@
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H
+#include "map-s3c.h"
+
#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
/* general configuration options */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c/regs-gpio-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/include/mach/regs-gpio.h
rename to arch/arm/mach-s3c/regs-gpio-s3c64xx.h
diff --git a/arch/arm/mach-s3c/regs-gpio.h b/arch/arm/mach-s3c/regs-gpio.h
new file mode 100644
index 0000000..0d41cb7
--- /dev/null
+++ b/arch/arm/mach-s3c/regs-gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_ARCH_S3C24XX
+#include "regs-gpio-s3c24xx.h"
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+#include "regs-gpio-s3c64xx.h"
+#endif
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-irq.h b/arch/arm/mach-s3c/regs-irq-s3c24xx.h
similarity index 97%
rename from arch/arm/mach-s3c24xx/include/mach/regs-irq.h
rename to arch/arm/mach-s3c/regs-irq-s3c24xx.h
index 8d8e669..c0b97b2 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-irq.h
+++ b/arch/arm/mach-s3c/regs-irq-s3c24xx.h
@@ -8,6 +8,8 @@
#ifndef ___ASM_ARCH_REGS_IRQ_H
#define ___ASM_ARCH_REGS_IRQ_H
+#include "map-s3c.h"
+
/* interrupt controller */
#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h b/arch/arm/mach-s3c/regs-irq-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/include/mach/regs-irq.h
rename to arch/arm/mach-s3c/regs-irq-s3c64xx.h
diff --git a/arch/arm/mach-s3c/regs-irq.h b/arch/arm/mach-s3c/regs-irq.h
new file mode 100644
index 0000000..57f0dda
--- /dev/null
+++ b/arch/arm/mach-s3c/regs-irq.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifdef CONFIG_ARCH_S3C24XX
+#include "regs-irq-s3c24xx.h"
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+#include "regs-irq-s3c64xx.h"
+#endif
diff --git a/arch/arm/plat-samsung/include/plat/regs-irqtype.h b/arch/arm/mach-s3c/regs-irqtype.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/regs-irqtype.h
rename to arch/arm/mach-s3c/regs-irqtype.h
diff --git a/arch/arm/mach-s3c24xx/regs-mem.h b/arch/arm/mach-s3c/regs-mem-s3c24xx.h
similarity index 97%
rename from arch/arm/mach-s3c24xx/regs-mem.h
rename to arch/arm/mach-s3c/regs-mem-s3c24xx.h
index 2f3bc48..8fed34a 100644
--- a/arch/arm/mach-s3c24xx/regs-mem.h
+++ b/arch/arm/mach-s3c/regs-mem-s3c24xx.h
@@ -9,6 +9,8 @@
#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__
+#include "map-s3c.h"
+
#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#define S3C2410_BWSCON S3C2410_MEMREG(0x00)
diff --git a/arch/arm/mach-s3c64xx/regs-modem.h b/arch/arm/mach-s3c/regs-modem-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/regs-modem.h
rename to arch/arm/mach-s3c/regs-modem-s3c64xx.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c/regs-s3c2443-clock.h
similarity index 81%
rename from arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
rename to arch/arm/mach-s3c/regs-s3c2443-clock.h
index 6bf9246..b3b670d 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c/regs-s3c2443-clock.h
@@ -10,6 +10,9 @@
#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
#define __ASM_ARM_REGS_S3C2443_CLOCK
+#include <linux/delay.h>
+#include "map-s3c.h"
+
#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
#define S3C2443_PLLCON_MDIVSHIFT 16
@@ -184,5 +187,52 @@
return (unsigned int)fvco;
}
+static inline void s3c_hsudc_init_phy(void)
+{
+ u32 cfg;
+
+ cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
+ writel(cfg, S3C2443_PWRCFG);
+
+ cfg = readl(S3C2443_URSTCON);
+ cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
+ writel(cfg, S3C2443_URSTCON);
+ mdelay(1);
+
+ cfg = readl(S3C2443_URSTCON);
+ cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
+ writel(cfg, S3C2443_URSTCON);
+
+ cfg = readl(S3C2443_PHYCTRL);
+ cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
+ cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
+ writel(cfg, S3C2443_PHYCTRL);
+
+ cfg = readl(S3C2443_PHYPWR);
+ cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
+ S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
+ S3C2443_PHYPWR_ANALOG_PD);
+ cfg |= S3C2443_PHYPWR_COMMON_ON;
+ writel(cfg, S3C2443_PHYPWR);
+
+ cfg = readl(S3C2443_UCLKCON);
+ cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
+ S3C2443_UCLKCON_TCLKEN);
+ writel(cfg, S3C2443_UCLKCON);
+}
+
+static inline void s3c_hsudc_uninit_phy(void)
+{
+ u32 cfg;
+
+ cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
+ writel(cfg, S3C2443_PWRCFG);
+
+ writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
+
+ cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
+ writel(cfg, S3C2443_UCLKCON);
+}
+
#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
diff --git a/arch/arm/mach-s3c64xx/regs-srom.h b/arch/arm/mach-s3c/regs-srom-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/regs-srom.h
rename to arch/arm/mach-s3c/regs-srom-s3c64xx.h
diff --git a/arch/arm/mach-s3c64xx/regs-sys.h b/arch/arm/mach-s3c/regs-sys-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/regs-sys.h
rename to arch/arm/mach-s3c/regs-sys-s3c64xx.h
diff --git a/arch/arm/mach-s3c64xx/regs-syscon-power.h b/arch/arm/mach-s3c/regs-syscon-power-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/regs-syscon-power.h
rename to arch/arm/mach-s3c/regs-syscon-power-s3c64xx.h
diff --git a/arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h b/arch/arm/mach-s3c/regs-usb-hsotg-phy-s3c64xx.h
similarity index 100%
rename from arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h
rename to arch/arm/mach-s3c/regs-usb-hsotg-phy-s3c64xx.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/rtc-core.h b/arch/arm/mach-s3c/rtc-core-s3c24xx.h
similarity index 80%
rename from arch/arm/mach-s3c24xx/include/mach/rtc-core.h
rename to arch/arm/mach-s3c/rtc-core-s3c24xx.h
index 8851033..e7258b2 100644
--- a/arch/arm/mach-s3c24xx/include/mach/rtc-core.h
+++ b/arch/arm/mach-s3c/rtc-core-s3c24xx.h
@@ -5,8 +5,8 @@
* Samsung RTC Controller core functions
*/
-#ifndef __RTC_CORE_H
-#define __RTC_CORE_H __FILE__
+#ifndef __RTC_CORE_S3C24XX_H
+#define __RTC_CORE_S3C24XX_H __FILE__
/* These functions are only for use with the core support code, such as
* the cpu specific initialisation code
@@ -20,4 +20,4 @@
s3c_device_rtc.name = name;
}
-#endif /* __RTC_CORE_H */
+#endif /* __RTC_CORE_S3C24XX_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c/s3c2410.c
similarity index 88%
rename from arch/arm/mach-s3c24xx/s3c2410.c
rename to arch/arm/mach-s3c/s3c2410.c
index 21fd540..4d39d99 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c/s3c2410.c
@@ -25,28 +25,27 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/gpio-samsung.h>
+#include "map.h"
+#include "gpio-samsung.h"
#include <asm/irq.h>
#include <asm/system_misc.h>
-#include <plat/cpu-freq.h>
-#include <mach/regs-clock.h>
+#include "regs-clock.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/pm.h>
+#include "cpu.h"
+#include "devs.h"
+#include "pm.h"
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
+#include "gpio-core.h"
+#include "gpio-cfg.h"
+#include "gpio-cfg-helpers.h"
-#include "common.h"
+#include "s3c24xx.h"
/* Initial IO mappings */
-static struct map_desc s3c2410_iodesc[] __initdata = {
+static struct map_desc s3c2410_iodesc[] __initdata __maybe_unused = {
IODESC_ENT(CLKPWR),
IODESC_ENT(TIMER),
IODESC_ENT(WATCHDOG),
diff --git a/arch/arm/mach-s3c24xx/s3c2412-power.h b/arch/arm/mach-s3c/s3c2412-power.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/s3c2412-power.h
rename to arch/arm/mach-s3c/s3c2412-power.h
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c/s3c2412.c
similarity index 91%
rename from arch/arm/mach-s3c24xx/s3c2412.c
rename to arch/arm/mach-s3c/s3c2412.c
index 8fe4d46..0b1ca78 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c/s3c2412.c
@@ -29,19 +29,17 @@
#include <asm/irq.h>
#include <asm/system_misc.h>
-#include <mach/hardware.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
+#include "map.h"
+#include "regs-clock.h"
+#include "regs-gpio.h"
-#include <plat/cpu.h>
-#include <plat/cpu-freq.h>
-#include <plat/devs.h>
-#include <plat/pm.h>
-#include <plat/regs-spi.h>
+#include "cpu.h"
+#include "devs.h"
+#include "pm.h"
-#include "common.h"
-#include "nand-core.h"
-#include "regs-dsc.h"
+#include "s3c24xx.h"
+#include "nand-core-s3c24xx.h"
+#include "regs-dsc-s3c24xx.h"
#include "s3c2412-power.h"
#ifndef CONFIG_CPU_S3C2412_ONLY
@@ -57,7 +55,7 @@
/* Initial IO mappings */
-static struct map_desc s3c2412_iodesc[] __initdata = {
+static struct map_desc s3c2412_iodesc[] __initdata __maybe_unused = {
IODESC_ENT(CLKPWR),
IODESC_ENT(TIMER),
IODESC_ENT(WATCHDOG),
diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c2412.h b/arch/arm/mach-s3c/s3c2412.h
similarity index 96%
rename from arch/arm/mach-s3c24xx/include/mach/s3c2412.h
rename to arch/arm/mach-s3c/s3c2412.h
index 4ff83f9..ed09a0e 100644
--- a/arch/arm/mach-s3c24xx/include/mach/s3c2412.h
+++ b/arch/arm/mach-s3c/s3c2412.h
@@ -8,6 +8,8 @@
#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H
#define __ARCH_ARM_MACH_S3C24XX_S3C2412_H __FILE__
+#include "map-s3c.h"
+
#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c/s3c2416.c
similarity index 83%
rename from arch/arm/mach-s3c24xx/s3c2416.c
rename to arch/arm/mach-s3c/s3c2416.c
index 1cdb7bd..126e6ed 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c/s3c2416.c
@@ -26,32 +26,32 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/gpio-samsung.h>
+#include "map.h"
+#include "gpio-samsung.h"
#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/system_misc.h>
-#include <mach/regs-s3c2443-clock.h>
-#include <mach/rtc-core.h>
+#include "regs-s3c2443-clock.h"
+#include "rtc-core-s3c24xx.h"
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/sdhci.h>
-#include <plat/pm.h>
+#include "gpio-core.h"
+#include "gpio-cfg.h"
+#include "gpio-cfg-helpers.h"
+#include "devs.h"
+#include "cpu.h"
+#include "sdhci.h"
+#include "pm.h"
-#include <plat/iic-core.h>
-#include <plat/adc-core.h>
+#include "iic-core.h"
+#include "adc-core.h"
-#include "common.h"
-#include "fb-core.h"
-#include "nand-core.h"
-#include "spi-core.h"
+#include "s3c24xx.h"
+#include "fb-core-s3c24xx.h"
+#include "nand-core-s3c24xx.h"
+#include "spi-core-s3c24xx.h"
-static struct map_desc s3c2416_iodesc[] __initdata = {
+static struct map_desc s3c2416_iodesc[] __initdata __maybe_unused = {
IODESC_ENT(WATCHDOG),
IODESC_ENT(CLKPWR),
IODESC_ENT(TIMER),
@@ -113,7 +113,7 @@
/* initialize device information early */
s3c2416_default_sdhci0();
s3c2416_default_sdhci1();
- s3c64xx_spi_setname("s3c2443-spi");
+ s3c24xx_spi_setname("s3c2443-spi");
iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
}
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c/s3c2440.c
similarity index 85%
rename from arch/arm/mach-s3c24xx/s3c2440.c
rename to arch/arm/mach-s3c/s3c2440.c
index 451d985..c6cdee4 100644
--- a/arch/arm/mach-s3c24xx/s3c2440.c
+++ b/arch/arm/mach-s3c/s3c2440.c
@@ -23,19 +23,18 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/gpio-samsung.h>
#include <asm/irq.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
+#include "devs.h"
+#include "cpu.h"
+#include "pm.h"
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
+#include "gpio-core.h"
+#include "gpio-cfg.h"
+#include "gpio-cfg-helpers.h"
+#include "gpio-samsung.h"
-#include "common.h"
+#include "s3c24xx.h"
static struct device s3c2440_dev = {
.bus = &s3c2440_subsys,
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c/s3c2442.c
similarity index 82%
rename from arch/arm/mach-s3c24xx/s3c2442.c
rename to arch/arm/mach-s3c/s3c2442.c
index 432d683..0c0e30b 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c/s3c2442.c
@@ -21,21 +21,20 @@
#include <linux/clk.h>
#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/gpio-samsung.h>
#include <linux/atomic.h>
#include <asm/irq.h>
-#include <mach/regs-clock.h>
+#include "regs-clock.h"
-#include <plat/cpu.h>
-#include <plat/pm.h>
+#include "cpu.h"
+#include "pm.h"
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
+#include "gpio-core.h"
+#include "gpio-cfg.h"
+#include "gpio-cfg-helpers.h"
+#include "gpio-samsung.h"
-#include "common.h"
+#include "s3c24xx.h"
static struct device s3c2442_dev = {
.bus = &s3c2442_subsys,
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c/s3c2443.c
similarity index 82%
rename from arch/arm/mach-s3c24xx/s3c2443.c
rename to arch/arm/mach-s3c/s3c2443.c
index 313e369..08f9101 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c/s3c2443.c
@@ -23,26 +23,28 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/gpio-samsung.h>
+#include "map.h"
+#include "gpio-samsung.h"
+#include <mach/irqs.h>
#include <asm/irq.h>
#include <asm/system_misc.h>
-#include <mach/regs-s3c2443-clock.h>
-#include <mach/rtc-core.h>
+#include "regs-s3c2443-clock.h"
+#include "rtc-core-s3c24xx.h"
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/adc-core.h>
+#include "gpio-core.h"
+#include "gpio-cfg.h"
+#include "gpio-cfg-helpers.h"
+#include "devs.h"
+#include "cpu.h"
+#include "adc-core.h"
-#include "fb-core.h"
-#include "nand-core.h"
-#include "spi-core.h"
+#include "s3c24xx.h"
+#include "fb-core-s3c24xx.h"
+#include "nand-core-s3c24xx.h"
+#include "spi-core-s3c24xx.h"
-static struct map_desc s3c2443_iodesc[] __initdata = {
+static struct map_desc s3c2443_iodesc[] __initdata __maybe_unused = {
IODESC_ENT(WATCHDOG),
IODESC_ENT(CLKPWR),
IODESC_ENT(TIMER),
@@ -91,7 +93,7 @@
s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull;
/* initialize device information early */
- s3c64xx_spi_setname("s3c2443-spi");
+ s3c24xx_spi_setname("s3c2443-spi");
iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
}
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c/s3c244x.c
similarity index 89%
rename from arch/arm/mach-s3c24xx/s3c244x.c
rename to arch/arm/mach-s3c/s3c244x.c
index a75f588..95df349 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c/s3c244x.c
@@ -25,23 +25,21 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
+#include "map.h"
#include <asm/irq.h>
-#include <plat/cpu-freq.h>
+#include "regs-clock.h"
+#include "regs-gpio.h"
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
+#include "devs.h"
+#include "cpu.h"
+#include "pm.h"
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
+#include "s3c24xx.h"
+#include "nand-core-s3c24xx.h"
+#include "regs-dsc-s3c24xx.h"
-#include "common.h"
-#include "nand-core.h"
-#include "regs-dsc.h"
-
-static struct map_desc s3c244x_iodesc[] __initdata = {
+static struct map_desc s3c244x_iodesc[] __initdata __maybe_unused = {
IODESC_ENT(CLKPWR),
IODESC_ENT(TIMER),
IODESC_ENT(WATCHDOG),
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c/s3c24xx.c
similarity index 96%
rename from arch/arm/mach-s3c24xx/common.c
rename to arch/arm/mach-s3c/s3c24xx.c
index 3dc029c..ccfed48 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c/s3c24xx.c
@@ -17,11 +17,14 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/platform_data/clk-s3c2410.h>
#include <linux/platform_data/dma-s3c24xx.h>
#include <linux/dmaengine.h>
+#include <linux/clk/samsung.h>
-#include <mach/hardware.h>
-#include <mach/regs-clock.h>
+#include "hardware-s3c24xx.h"
+#include "map.h"
+#include "regs-clock.h"
#include <asm/irq.h>
#include <asm/cacheflush.h>
#include <asm/system_info.h>
@@ -30,15 +33,14 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/regs-gpio.h>
-#include <mach/dma.h>
+#include "regs-gpio.h"
+#include "dma-s3c24xx.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/cpu-freq.h>
-#include <plat/pwm-core.h>
+#include "cpu.h"
+#include "devs.h"
+#include "pwm-core.h"
-#include "common.h"
+#include "s3c24xx.h"
/* table of supported CPUs */
@@ -137,7 +139,7 @@
/* minimal IO mapping */
-static struct map_desc s3c_iodesc[] __initdata = {
+static struct map_desc s3c_iodesc[] __initdata __maybe_unused = {
IODESC_ENT(GPIO),
IODESC_ENT(IRQ),
IODESC_ENT(MEMCTRL),
@@ -220,13 +222,13 @@
samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
}
-void __init samsung_set_timer_source(unsigned int event, unsigned int source)
+void __init s3c24xx_set_timer_source(unsigned int event, unsigned int source)
{
s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
}
-void __init samsung_timer_init(void)
+void __init s3c24xx_timer_init(void)
{
unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
@@ -662,10 +664,17 @@
[0] = DEFINE_RES_MEM(0x56000084, 0x4),
};
+static struct s3c2410_clk_platform_data s3c_clk_platform_data = {
+ .modify_misccr = s3c2410_modify_misccr,
+};
+
struct platform_device s3c2410_device_dclk = {
.name = "s3c2410-dclk",
.id = 0,
.num_resources = ARRAY_SIZE(s3c2410_dclk_resource),
.resource = s3c2410_dclk_resource,
+ .dev = {
+ .platform_data = &s3c_clk_platform_data,
+ },
};
#endif
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c/s3c24xx.h
similarity index 84%
rename from arch/arm/mach-s3c24xx/common.h
rename to arch/arm/mach-s3c/s3c24xx.h
index d087b20..5848bef 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c/s3c24xx.h
@@ -10,6 +10,7 @@
#define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
#include <linux/reboot.h>
+#include <mach/irqs.h>
struct s3c2410_uartcfg;
@@ -108,19 +109,16 @@
extern struct platform_device s3c2410_device_dclk;
-#ifdef CONFIG_S3C2410_COMMON_CLK
-void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
- int current_soc,
- void __iomem *reg_base);
-#endif
-#ifdef CONFIG_S3C2412_COMMON_CLK
-void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
- unsigned long ext_f, void __iomem *reg_base);
-#endif
-#ifdef CONFIG_S3C2443_COMMON_CLK
-void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
- int current_soc,
- void __iomem *reg_base);
-#endif
+enum s3c24xx_timer_mode {
+ S3C24XX_PWM0,
+ S3C24XX_PWM1,
+ S3C24XX_PWM2,
+ S3C24XX_PWM3,
+ S3C24XX_PWM4,
+};
+
+extern void __init s3c24xx_set_timer_source(enum s3c24xx_timer_mode event,
+ enum s3c24xx_timer_mode source);
+extern void __init s3c24xx_timer_init(void);
#endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c/s3c6400.c
similarity index 88%
rename from arch/arm/mach-s3c64xx/s3c6400.c
rename to arch/arm/mach-s3c/s3c6400.c
index 545eea7..802f4fb 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c/s3c6400.c
@@ -26,19 +26,17 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
-#include <plat/cpu-freq.h>
-#include <mach/regs-clock.h>
+#include "regs-clock.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/sdhci.h>
-#include <plat/iic-core.h>
+#include "cpu.h"
+#include "devs.h"
+#include "sdhci.h"
+#include "iic-core.h"
-#include "common.h"
-#include "onenand-core.h"
+#include "s3c64xx.h"
+#include "onenand-core-s3c64xx.h"
void __init s3c6400_map_io(void)
{
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c/s3c6410.c
similarity index 86%
rename from arch/arm/mach-s3c64xx/s3c6410.c
rename to arch/arm/mach-s3c/s3c6410.c
index 47e04e0..dae17d5 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c/s3c6410.c
@@ -27,21 +27,20 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
-#include <plat/cpu-freq.h>
-#include <mach/regs-clock.h>
+#include <linux/soc/samsung/s3c-pm.h>
+#include "regs-clock.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/sdhci.h>
-#include <plat/adc-core.h>
-#include <plat/iic-core.h>
+#include "cpu.h"
+#include "devs.h"
+#include "sdhci.h"
+#include "adc-core.h"
+#include "iic-core.h"
-#include "ata-core.h"
-#include "common.h"
-#include "onenand-core.h"
+#include "ata-core-s3c64xx.h"
+#include "s3c64xx.h"
+#include "onenand-core-s3c64xx.h"
void __init s3c6410_map_io(void)
{
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c/s3c64xx.c
similarity index 90%
rename from arch/arm/mach-s3c64xx/common.c
rename to arch/arm/mach-s3c/s3c64xx.c
index 13e9107..4dfb648 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c/s3c64xx.c
@@ -24,6 +24,7 @@
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/io.h>
+#include <linux/clk/samsung.h>
#include <linux/dma-mapping.h>
#include <linux/irq.h>
#include <linux/gpio.h>
@@ -34,22 +35,19 @@
#include <asm/mach/map.h>
#include <asm/system_misc.h>
-#include <mach/map.h>
+#include "map.h"
#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/pm.h>
-#include <plat/gpio-cfg.h>
-#include <plat/pwm-core.h>
-#include <plat/regs-irqtype.h>
-
-#include "common.h"
-#include "irq-uart.h"
-#include "watchdog-reset.h"
+#include "cpu.h"
+#include "devs.h"
+#include "pm.h"
+#include "gpio-cfg.h"
+#include "pwm-core.h"
+#include "regs-irqtype.h"
+#include "s3c64xx.h"
+#include "irq-uart-s3c64xx.h"
/* External clock frequency */
static unsigned long xtal_f __ro_after_init = 12000000;
@@ -97,7 +95,12 @@
/* minimal IO mapping */
-/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
+/*
+ * note, for the boot process to work we have to keep the UART
+ * virtual address aligned to an 1MiB boundary for the L1
+ * mapping the head code makes. We keep the UART virtual address
+ * aligned and add in the offset when we load the value here.
+ */
#define UART_OFFS (S3C_PA_UART & 0xfffff)
static struct map_desc s3c_iodesc[] __initdata = {
@@ -170,13 +173,13 @@
.tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
};
-void __init samsung_set_timer_source(unsigned int event, unsigned int source)
+void __init s3c64xx_set_timer_source(unsigned int event, unsigned int source)
{
s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
}
-void __init samsung_timer_init(void)
+void __init s3c64xx_timer_init(void)
{
unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
@@ -228,13 +231,7 @@
void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
- /*
- * FIXME: there is no better place to put this at the moment
- * (s3c64xx_clk_init needs ioremap and must happen before init_time
- * samsung_wdt_reset_init needs clocks)
- */
s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
- samsung_wdt_reset_init(S3C_VA_WATCHDOG);
printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
@@ -428,12 +425,3 @@
return 0;
}
arch_initcall(s3c64xx_init_irq_eint);
-
-void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
-{
- if (mode != REBOOT_SOFT)
- samsung_wdt_reset();
-
- /* if all else fails, or mode was for soft, jump to 0 */
- soft_restart(0);
-}
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c/s3c64xx.h
similarity index 79%
rename from arch/arm/mach-s3c64xx/common.h
rename to arch/arm/mach-s3c/s3c64xx.h
index 0367088..92258e4 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c/s3c64xx.h
@@ -19,11 +19,7 @@
void s3c64xx_init_irq(u32 vic0, u32 vic1);
void s3c64xx_init_io(struct map_desc *mach_desc, int size);
-void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
-
struct device_node;
-void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
- unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
void s3c64xx_set_xtal_freq(unsigned long freq);
void s3c64xx_set_xusbxti_freq(unsigned long freq);
@@ -54,4 +50,17 @@
extern struct pl08x_platform_data s3c64xx_dma1_plat_data;
#endif
+/* Samsung HR-Timer Clock mode */
+enum s3c64xx_timer_mode {
+ S3C64XX_PWM0,
+ S3C64XX_PWM1,
+ S3C64XX_PWM2,
+ S3C64XX_PWM3,
+ S3C64XX_PWM4,
+};
+
+extern void __init s3c64xx_set_timer_source(enum s3c64xx_timer_mode event,
+ enum s3c64xx_timer_mode source);
+extern void __init s3c64xx_timer_init(void);
+
#endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/mach-s3c/sdhci.h
similarity index 99%
rename from arch/arm/plat-samsung/include/plat/sdhci.h
rename to arch/arm/mach-s3c/sdhci.h
index 5731e42..9f9d419 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/mach-s3c/sdhci.h
@@ -15,7 +15,7 @@
#define __PLAT_S3C_SDHCI_H __FILE__
#include <linux/platform_data/mmc-sdhci-s3c.h>
-#include <plat/devs.h>
+#include "devs.h"
/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data
* @pd: The default platform data for this device.
diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c/setup-fb-24bpp-s3c64xx.c
similarity index 85%
rename from arch/arm/mach-s3c64xx/setup-fb-24bpp.c
rename to arch/arm/mach-s3c/setup-fb-24bpp-s3c64xx.c
index 2c7178b..cfa34b5 100644
--- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
+++ b/arch/arm/mach-s3c/setup-fb-24bpp-s3c64xx.c
@@ -12,9 +12,9 @@
#include <linux/fb.h>
#include <linux/gpio.h>
-#include <plat/fb.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
+#include "fb.h"
+#include "gpio-cfg.h"
+#include "gpio-samsung.h"
void s3c64xx_fb_gpio_setup_24bpp(void)
{
diff --git a/arch/arm/mach-s3c24xx/setup-i2c.c b/arch/arm/mach-s3c/setup-i2c-s3c24xx.c
similarity index 79%
rename from arch/arm/mach-s3c24xx/setup-i2c.c
rename to arch/arm/mach-s3c/setup-i2c-s3c24xx.c
index 1a01d44..0d88366 100644
--- a/arch/arm/mach-s3c24xx/setup-i2c.c
+++ b/arch/arm/mach-s3c/setup-i2c-s3c24xx.c
@@ -10,11 +10,11 @@
struct platform_device;
-#include <plat/gpio-cfg.h>
#include <linux/platform_data/i2c-s3c2410.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
+
+#include "gpio-cfg.h"
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
diff --git a/arch/arm/mach-s3c64xx/setup-i2c0.c b/arch/arm/mach-s3c/setup-i2c0-s3c64xx.c
similarity index 89%
rename from arch/arm/mach-s3c64xx/setup-i2c0.c
rename to arch/arm/mach-s3c/setup-i2c0-s3c64xx.c
index 552eb50..a6ef8d2 100644
--- a/arch/arm/mach-s3c64xx/setup-i2c0.c
+++ b/arch/arm/mach-s3c/setup-i2c0-s3c64xx.c
@@ -14,8 +14,8 @@
struct platform_device; /* don't need the contents */
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
+#include "gpio-cfg.h"
+#include "gpio-samsung.h"
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
diff --git a/arch/arm/mach-s3c64xx/setup-i2c1.c b/arch/arm/mach-s3c/setup-i2c1-s3c64xx.c
similarity index 89%
rename from arch/arm/mach-s3c64xx/setup-i2c1.c
rename to arch/arm/mach-s3c/setup-i2c1-s3c64xx.c
index d231f0f..0fe3736 100644
--- a/arch/arm/mach-s3c64xx/setup-i2c1.c
+++ b/arch/arm/mach-s3c/setup-i2c1-s3c64xx.c
@@ -14,8 +14,8 @@
struct platform_device; /* don't need the contents */
#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
+#include "gpio-cfg.h"
+#include "gpio-samsung.h"
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c/setup-ide-s3c64xx.c
similarity index 89%
rename from arch/arm/mach-s3c64xx/setup-ide.c
rename to arch/arm/mach-s3c/setup-ide-s3c64xx.c
index 810139a..f11f2b0 100644
--- a/arch/arm/mach-s3c64xx/setup-ide.c
+++ b/arch/arm/mach-s3c/setup-ide-s3c64xx.c
@@ -9,12 +9,13 @@
#include <linux/gpio.h>
#include <linux/io.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
#include <linux/platform_data/ata-samsung_cf.h>
+#include "map.h"
+#include "regs-clock.h"
+#include "gpio-cfg.h"
+#include "gpio-samsung.h"
+
void s3c64xx_ide_setup_gpio(void)
{
u32 reg;
diff --git a/arch/arm/mach-s3c64xx/setup-keypad.c b/arch/arm/mach-s3c/setup-keypad-s3c64xx.c
similarity index 86%
rename from arch/arm/mach-s3c64xx/setup-keypad.c
rename to arch/arm/mach-s3c/setup-keypad-s3c64xx.c
index 3519610..8463ad3 100644
--- a/arch/arm/mach-s3c64xx/setup-keypad.c
+++ b/arch/arm/mach-s3c/setup-keypad-s3c64xx.c
@@ -6,9 +6,9 @@
// GPIO configuration for S3C64XX KeyPad device
#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <plat/keypad.h>
-#include <mach/gpio-samsung.h>
+#include "gpio-cfg.h"
+#include "keypad.h"
+#include "gpio-samsung.h"
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
{
diff --git a/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c/setup-sdhci-gpio-s3c24xx.c
similarity index 88%
rename from arch/arm/mach-s3c24xx/setup-sdhci-gpio.c
rename to arch/arm/mach-s3c/setup-sdhci-gpio-s3c24xx.c
index 218346a..02131b3 100644
--- a/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s3c/setup-sdhci-gpio-s3c24xx.c
@@ -14,9 +14,10 @@
#include <linux/io.h>
#include <linux/gpio.h>
-#include <mach/regs-gpio.h>
-#include <mach/gpio-samsung.h>
-#include <plat/gpio-cfg.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
+#include "sdhci.h"
void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c/setup-sdhci-gpio-s3c64xx.c
similarity index 94%
rename from arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
rename to arch/arm/mach-s3c/setup-sdhci-gpio-s3c64xx.c
index 138455a..646ff94 100644
--- a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s3c/setup-sdhci-gpio-s3c64xx.c
@@ -13,9 +13,9 @@
#include <linux/io.h>
#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <plat/sdhci.h>
-#include <mach/gpio-samsung.h>
+#include "gpio-cfg.h"
+#include "sdhci.h"
+#include "gpio-samsung.h"
void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c/setup-spi-s3c24xx.c
similarity index 84%
rename from arch/arm/mach-s3c24xx/setup-spi.c
rename to arch/arm/mach-s3c/setup-spi-s3c24xx.c
index 6c2b96a..93fa1bb 100644
--- a/arch/arm/mach-s3c24xx/setup-spi.c
+++ b/arch/arm/mach-s3c/setup-spi-s3c24xx.c
@@ -8,10 +8,10 @@
#include <linux/gpio.h>
#include <linux/platform_device.h>
-#include <plat/gpio-cfg.h>
+#include "gpio-cfg.h"
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
+#include "hardware-s3c24xx.h"
+#include "regs-gpio.h"
#ifdef CONFIG_S3C64XX_DEV_SPI0
int s3c64xx_spi0_cfg_gpio(void)
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c/setup-spi-s3c64xx.c
similarity index 83%
rename from arch/arm/mach-s3c64xx/setup-spi.c
rename to arch/arm/mach-s3c/setup-spi-s3c64xx.c
index 39dfae1..efcf78d 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c/setup-spi-s3c64xx.c
@@ -4,8 +4,9 @@
// http://www.samsung.com/
#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
+#include <linux/platform_data/spi-s3c64xx.h>
+#include "gpio-cfg.h"
+#include "gpio-samsung.h"
#ifdef CONFIG_S3C64XX_DEV_SPI0
int s3c64xx_spi0_cfg_gpio(void)
diff --git a/arch/arm/mach-s3c24xx/setup-ts.c b/arch/arm/mach-s3c/setup-ts-s3c24xx.c
similarity index 80%
rename from arch/arm/mach-s3c24xx/setup-ts.c
rename to arch/arm/mach-s3c/setup-ts-s3c24xx.c
index 53a14d4..57363ea 100644
--- a/arch/arm/mach-s3c24xx/setup-ts.c
+++ b/arch/arm/mach-s3c/setup-ts-s3c24xx.c
@@ -10,12 +10,14 @@
struct platform_device; /* don't need the contents */
-#include <plat/gpio-cfg.h>
-#include <mach/hardware.h>
-#include <mach/gpio-samsung.h>
+#include <linux/platform_data/touchscreen-s3c2410.h>
+
+#include "gpio-cfg.h"
+#include "gpio-samsung.h"
/**
* s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems
+ * @dev: Device to configure GPIO for (ignored)
*
* Configure the GPIO for the S3C2410 system, where we have external FETs
* connected to the device (later systems such as the S3C2440 integrate
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c
similarity index 85%
rename from arch/arm/mach-s3c64xx/setup-usb-phy.c
rename to arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c
index 6aaaa1d..500d105 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c
@@ -8,12 +8,12 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
-#include <mach/map.h>
-#include <plat/cpu.h>
-#include <plat/usb-phy.h>
+#include "map.h"
+#include "cpu.h"
+#include "usb-phy.h"
-#include "regs-sys.h"
-#include "regs-usb-hsotg-phy.h"
+#include "regs-sys-s3c64xx.h"
+#include "regs-usb-hsotg-phy-s3c64xx.h"
enum samsung_usb_phy_type {
USB_PHY_TYPE_DEVICE,
@@ -31,7 +31,7 @@
phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
xusbxti = clk_get(&pdev->dev, "xusbxti");
- if (xusbxti && !IS_ERR(xusbxti)) {
+ if (!IS_ERR(xusbxti)) {
switch (clk_get_rate(xusbxti)) {
case 12 * MHZ:
phyclk |= S3C_PHYCLK_CLKSEL_12M;
@@ -73,7 +73,7 @@
return 0;
}
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
+int s3c_usb_phy_init(struct platform_device *pdev, int type)
{
if (type == USB_PHY_TYPE_DEVICE)
return s3c_usb_otgphy_init(pdev);
@@ -81,7 +81,7 @@
return -EINVAL;
}
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+int s3c_usb_phy_exit(struct platform_device *pdev, int type)
{
if (type == USB_PHY_TYPE_DEVICE)
return s3c_usb_otgphy_exit(pdev);
diff --git a/arch/arm/mach-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c/simtec-audio.c
similarity index 86%
rename from arch/arm/mach-s3c24xx/simtec-audio.c
rename to arch/arm/mach-s3c/simtec-audio.c
index 12e17f8..487485b 100644
--- a/arch/arm/mach-s3c24xx/simtec-audio.c
+++ b/arch/arm/mach-s3c/simtec-audio.c
@@ -12,11 +12,12 @@
#include <linux/device.h>
#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/regs-gpio.h>
+#include "regs-gpio.h"
+#include "gpio-samsung.h"
+#include "gpio-cfg.h"
#include <linux/platform_data/asoc-s3c24xx_simtec.h>
-#include <plat/devs.h>
+#include "devs.h"
#include "bast.h"
#include "simtec.h"
@@ -65,6 +66,10 @@
if (has_lr_routing)
simtec_audio_platdata.startup = simtec_audio_startup_lrroute;
+ /* Configure the I2S pins (GPE0...GPE4) in correct mode */
+ s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
+ S3C_GPIO_PULL_NONE);
+
platform_device_register(&s3c_device_iis);
platform_device_register(&simtec_audio_dev);
return 0;
diff --git a/arch/arm/mach-s3c24xx/simtec-nor.c b/arch/arm/mach-s3c/simtec-nor.c
similarity index 98%
rename from arch/arm/mach-s3c24xx/simtec-nor.c
rename to arch/arm/mach-s3c/simtec-nor.c
index 26b1849..a6fba05 100644
--- a/arch/arm/mach-s3c24xx/simtec-nor.c
+++ b/arch/arm/mach-s3c/simtec-nor.c
@@ -21,7 +21,7 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/map.h>
+#include "map.h"
#include "bast.h"
#include "simtec.h"
diff --git a/arch/arm/mach-s3c24xx/simtec-pm.c b/arch/arm/mach-s3c/simtec-pm.c
similarity index 90%
rename from arch/arm/mach-s3c24xx/simtec-pm.c
rename to arch/arm/mach-s3c/simtec-pm.c
index c19074d..490256a 100644
--- a/arch/arm/mach-s3c24xx/simtec-pm.c
+++ b/arch/arm/mach-s3c/simtec-pm.c
@@ -19,16 +19,14 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/hardware.h>
-
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
+#include "map.h"
+#include "regs-gpio.h"
#include <asm/mach-types.h>
-#include <plat/pm.h>
+#include "pm.h"
-#include "regs-mem.h"
+#include "regs-mem-s3c24xx.h"
#define COPYRIGHT ", Copyright 2005 Simtec Electronics"
diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c/simtec-usb.c
similarity index 96%
rename from arch/arm/mach-s3c24xx/simtec-usb.c
rename to arch/arm/mach-s3c/simtec-usb.c
index dc1016f..18fe064 100644
--- a/arch/arm/mach-s3c24xx/simtec-usb.c
+++ b/arch/arm/mach-s3c/simtec-usb.c
@@ -23,12 +23,12 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/gpio-samsung.h>
+#include "gpio-samsung.h"
+#include <mach/irqs.h>
#include <asm/irq.h>
#include <linux/platform_data/usb-ohci-s3c2410.h>
-#include <plat/devs.h>
+#include "devs.h"
#include "bast.h"
#include "simtec.h"
diff --git a/arch/arm/mach-s3c24xx/simtec.h b/arch/arm/mach-s3c/simtec.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/simtec.h
rename to arch/arm/mach-s3c/simtec.h
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c/sleep-s3c2410.S
similarity index 90%
rename from arch/arm/mach-s3c24xx/sleep-s3c2410.S
rename to arch/arm/mach-s3c/sleep-s3c2410.S
index 659f9ef..04aded9 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S
+++ b/arch/arm/mach-s3c/sleep-s3c2410.S
@@ -13,13 +13,12 @@
#include <linux/linkage.h>
#include <linux/serial_s3c.h>
#include <asm/assembler.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
+#include "map.h"
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
+#include "regs-gpio.h"
+#include "regs-clock.h"
-#include "regs-mem.h"
+#include "regs-mem-s3c24xx.h"
/* s3c2410_cpu_suspend
*
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2412.S b/arch/arm/mach-s3c/sleep-s3c2412.S
similarity index 93%
rename from arch/arm/mach-s3c24xx/sleep-s3c2412.S
rename to arch/arm/mach-s3c/sleep-s3c2412.S
index c373f1c..b4b6173 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2412.S
+++ b/arch/arm/mach-s3c/sleep-s3c2412.S
@@ -8,10 +8,9 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
+#include "map.h"
-#include <mach/regs-irq.h>
+#include "regs-irq.h"
.text
diff --git a/arch/arm/mach-s3c24xx/sleep.S b/arch/arm/mach-s3c/sleep-s3c24xx.S
similarity index 92%
rename from arch/arm/mach-s3c24xx/sleep.S
rename to arch/arm/mach-s3c/sleep-s3c24xx.S
index f0f11ad..4b2af91 100644
--- a/arch/arm/mach-s3c24xx/sleep.S
+++ b/arch/arm/mach-s3c/sleep-s3c24xx.S
@@ -13,11 +13,10 @@
#include <linux/linkage.h>
#include <linux/serial_s3c.h>
#include <asm/assembler.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
+#include "map.h"
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
+#include "regs-gpio.h"
+#include "regs-clock.h"
/*
* S3C24XX_DEBUG_RESUME is dangerous if your bootloader does not
diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c/sleep-s3c64xx.S
similarity index 96%
rename from arch/arm/mach-s3c64xx/sleep.S
rename to arch/arm/mach-s3c/sleep-s3c64xx.S
index 39e16a0..739e53f 100644
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ b/arch/arm/mach-s3c/sleep-s3c64xx.S
@@ -11,12 +11,12 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include <mach/map.h>
+#include "map.h"
#undef S3C64XX_VA_GPIO
#define S3C64XX_VA_GPIO (0x0)
-#include <mach/regs-gpio.h>
+#include "regs-gpio.h"
#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
diff --git a/arch/arm/mach-s3c24xx/spi-core.h b/arch/arm/mach-s3c/spi-core-s3c24xx.h
similarity index 73%
rename from arch/arm/mach-s3c24xx/spi-core.h
rename to arch/arm/mach-s3c/spi-core-s3c24xx.h
index bb555cc..0576674 100644
--- a/arch/arm/mach-s3c24xx/spi-core.h
+++ b/arch/arm/mach-s3c/spi-core-s3c24xx.h
@@ -3,15 +3,15 @@
* Copyright (C) 2012 Heiko Stuebner <heiko@sntech.de>
*/
-#ifndef __PLAT_S3C_SPI_CORE_H
-#define __PLAT_S3C_SPI_CORE_H
+#ifndef __PLAT_S3C_SPI_CORE_S3C24XX_H
+#define __PLAT_S3C_SPI_CORE_S3C24XX_H
/* These functions are only for use with the core support code, such as
* the cpu specific initialisation code
*/
/* re-define device name depending on support. */
-static inline void s3c64xx_spi_setname(char *name)
+static inline void s3c24xx_spi_setname(char *name)
{
#ifdef CONFIG_S3C64XX_DEV_SPI0
s3c64xx_device_spi0.name = name;
@@ -24,4 +24,4 @@
#endif
}
-#endif /* __PLAT_S3C_SPI_CORE_H */
+#endif /* __PLAT_S3C_SPI_CORE_S3C24XX_H */
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/mach-s3c/usb-phy.h
similarity index 68%
rename from arch/arm/plat-samsung/include/plat/usb-phy.h
rename to arch/arm/mach-s3c/usb-phy.h
index 94da89e..759d66a 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/mach-s3c/usb-phy.h
@@ -7,7 +7,7 @@
#ifndef __PLAT_SAMSUNG_USB_PHY_H
#define __PLAT_SAMSUNG_USB_PHY_H __FILE__
-extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
-extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
+extern int s3c_usb_phy_init(struct platform_device *pdev, int type);
+extern int s3c_usb_phy_exit(struct platform_device *pdev, int type);
#endif /* __PLAT_SAMSUNG_USB_PHY_H */
diff --git a/arch/arm/mach-s3c24xx/vr1000.h b/arch/arm/mach-s3c/vr1000.h
similarity index 100%
rename from arch/arm/mach-s3c24xx/vr1000.h
rename to arch/arm/mach-s3c/vr1000.h
diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/mach-s3c/wakeup-mask.c
similarity index 94%
rename from arch/arm/plat-samsung/wakeup-mask.c
rename to arch/arm/mach-s3c/wakeup-mask.c
index 24f96fb..b490e75 100644
--- a/arch/arm/plat-samsung/wakeup-mask.c
+++ b/arch/arm/mach-s3c/wakeup-mask.c
@@ -11,8 +11,8 @@
#include <linux/irq.h>
#include <linux/io.h>
-#include <plat/wakeup-mask.h>
-#include <plat/pm.h>
+#include "wakeup-mask.h"
+#include "pm.h"
void samsung_sync_wakemask(void __iomem *reg,
const struct samsung_wakeup_mask *mask, int nr_mask)
diff --git a/arch/arm/plat-samsung/include/plat/wakeup-mask.h b/arch/arm/mach-s3c/wakeup-mask.h
similarity index 100%
rename from arch/arm/plat-samsung/include/plat/wakeup-mask.h
rename to arch/arm/mach-s3c/wakeup-mask.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/fb.h b/arch/arm/mach-s3c24xx/include/mach/fb.h
deleted file mode 100644
index 4e539cb..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/fb.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <plat/fb-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h
deleted file mode 100644
index f28ac6c..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/hardware.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2003 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - hardware
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#ifndef __ASSEMBLY__
-
-extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
-
-#endif /* __ASSEMBLY__ */
-
-#include <linux/sizes.h>
-#include <mach/map.h>
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/io.h b/arch/arm/mach-s3c24xx/include/mach/io.h
deleted file mode 100644
index f960e6d..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/io.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/arm/mach-s3c2410/include/mach/io.h
- * from arch/arm/mach-rpc/include/mach/io.h
- *
- * Copyright (C) 1997 Russell King
- * (C) 2003 Simtec Electronics
-*/
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <mach/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We use two different types of addressing - PC style addresses, and ARM
- * addresses. PC style accesses the PC hardware with the normal PC IO
- * addresses, eg 0x3f8 for serial#1. ARM addresses are above A28
- * and are translated to the start of IO. Note that all addresses are
- * not shifted left!
- */
-
-#define __PORT_PCIO(x) ((x) < (1<<28))
-
-#define PCIO_BASE (S3C24XX_VA_ISA_WORD)
-#define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE)
-#define PCIO_BASE_w (S3C24XX_VA_ISA_WORD)
-#define PCIO_BASE_l (S3C24XX_VA_ISA_WORD)
-/*
- * Dynamic IO functions - let the compiler
- * optimize the expressions
- */
-
-#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
-static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
-{ \
- unsigned long temp; \
- __asm__ __volatile__( \
- "cmp %2, #(1<<28)\n\t" \
- "mov %0, %2\n\t" \
- "addcc %0, %0, %3\n\t" \
- "str" instr " %1, [%0, #0 ] @ out" #fnsuffix \
- : "=&r" (temp) \
- : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
- : "cc"); \
-}
-
-
-#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
-static inline unsigned sz __in##fnsuffix (unsigned int port) \
-{ \
- unsigned long temp, value; \
- __asm__ __volatile__( \
- "cmp %2, #(1<<28)\n\t" \
- "mov %0, %2\n\t" \
- "addcc %0, %0, %3\n\t" \
- "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \
- : "=&r" (temp), "=r" (value) \
- : "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
- : "cc"); \
- return (unsigned sz)value; \
-}
-
-static inline void __iomem *__ioaddr (unsigned long port)
-{
- return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port;
-}
-
-#define DECLARE_IO(sz,fnsuffix,instr) \
- DECLARE_DYN_IN(sz,fnsuffix,instr) \
- DECLARE_DYN_OUT(sz,fnsuffix,instr)
-
-DECLARE_IO(char,b,"b")
-DECLARE_IO(short,w,"h")
-DECLARE_IO(int,l,"")
-
-#undef DECLARE_IO
-#undef DECLARE_DYN_IN
-
-/*
- * Constant address IO functions
- *
- * These have to be macros for the 'J' constraint to work -
- * +/-4096 immediate operand.
- */
-#define __outbc(value,port) \
-({ \
- if (__PORT_PCIO((port))) \
- __asm__ __volatile__( \
- "strb %0, [%1, %2] @ outbc" \
- : : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \
- else \
- __asm__ __volatile__( \
- "strb %0, [%1, #0] @ outbc" \
- : : "r" (value), "r" ((port))); \
-})
-
-#define __inbc(port) \
-({ \
- unsigned char result; \
- if (__PORT_PCIO((port))) \
- __asm__ __volatile__( \
- "ldrb %0, [%1, %2] @ inbc" \
- : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
- else \
- __asm__ __volatile__( \
- "ldrb %0, [%1, #0] @ inbc" \
- : "=r" (result) : "r" ((port))); \
- result; \
-})
-
-#define __outwc(value,port) \
-({ \
- unsigned long v = value; \
- if (__PORT_PCIO((port))) { \
- if ((port) < 256 && (port) > -256) \
- __asm__ __volatile__( \
- "strh %0, [%1, %2] @ outwc" \
- : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
- else if ((port) > 0) \
- __asm__ __volatile__( \
- "strh %0, [%1, %2] @ outwc" \
- : : "r" (v), \
- "r" (PCIO_BASE + ((port) & ~0xff)), \
- "Jr" (((port) & 0xff))); \
- else \
- __asm__ __volatile__( \
- "strh %0, [%1, #0] @ outwc" \
- : : "r" (v), \
- "r" (PCIO_BASE + (port))); \
- } else \
- __asm__ __volatile__( \
- "strh %0, [%1, #0] @ outwc" \
- : : "r" (v), "r" ((port))); \
-})
-
-#define __inwc(port) \
-({ \
- unsigned short result; \
- if (__PORT_PCIO((port))) { \
- if ((port) < 256 && (port) > -256 ) \
- __asm__ __volatile__( \
- "ldrh %0, [%1, %2] @ inwc" \
- : "=r" (result) \
- : "r" (PCIO_BASE), \
- "Jr" ((port))); \
- else if ((port) > 0) \
- __asm__ __volatile__( \
- "ldrh %0, [%1, %2] @ inwc" \
- : "=r" (result) \
- : "r" (PCIO_BASE + ((port) & ~0xff)), \
- "Jr" (((port) & 0xff))); \
- else \
- __asm__ __volatile__( \
- "ldrh %0, [%1, #0] @ inwc" \
- : "=r" (result) \
- : "r" (PCIO_BASE + ((port)))); \
- } else \
- __asm__ __volatile__( \
- "ldrh %0, [%1, #0] @ inwc" \
- : "=r" (result) : "r" ((port))); \
- result; \
-})
-
-#define __outlc(value,port) \
-({ \
- unsigned long v = value; \
- if (__PORT_PCIO((port))) \
- __asm__ __volatile__( \
- "str %0, [%1, %2] @ outlc" \
- : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
- else \
- __asm__ __volatile__( \
- "str %0, [%1, #0] @ outlc" \
- : : "r" (v), "r" ((port))); \
-})
-
-#define __inlc(port) \
-({ \
- unsigned long result; \
- if (__PORT_PCIO((port))) \
- __asm__ __volatile__( \
- "ldr %0, [%1, %2] @ inlc" \
- : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
- else \
- __asm__ __volatile__( \
- "ldr %0, [%1, #0] @ inlc" \
- : "=r" (result) : "r" ((port))); \
- result; \
-})
-
-#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)0 + (port)))
-
-#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
-#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
-#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
-#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
-#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
-#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
-#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
-
-#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
-#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
-#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l)
-
-#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
-#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
-#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l)
-
-#endif
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h b/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h
deleted file mode 100644
index 4c3434f..0000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- */
-
-#ifndef ___ASM_ARCH_REGS_LCD_H
-#define ___ASM_ARCH_REGS_LCD_H
-
-#define S3C2410_LCDREG(x) (x)
-
-/* LCD control registers */
-#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00)
-#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04)
-#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08)
-#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C)
-#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10)
-
-#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8)
-#define S3C2410_LCDCON1_MMODE (1<<7)
-#define S3C2410_LCDCON1_DSCAN4 (0<<5)
-#define S3C2410_LCDCON1_STN4 (1<<5)
-#define S3C2410_LCDCON1_STN8 (2<<5)
-#define S3C2410_LCDCON1_TFT (3<<5)
-
-#define S3C2410_LCDCON1_STN1BPP (0<<1)
-#define S3C2410_LCDCON1_STN2GREY (1<<1)
-#define S3C2410_LCDCON1_STN4GREY (2<<1)
-#define S3C2410_LCDCON1_STN8BPP (3<<1)
-#define S3C2410_LCDCON1_STN12BPP (4<<1)
-
-#define S3C2410_LCDCON1_TFT1BPP (8<<1)
-#define S3C2410_LCDCON1_TFT2BPP (9<<1)
-#define S3C2410_LCDCON1_TFT4BPP (10<<1)
-#define S3C2410_LCDCON1_TFT8BPP (11<<1)
-#define S3C2410_LCDCON1_TFT16BPP (12<<1)
-#define S3C2410_LCDCON1_TFT24BPP (13<<1)
-
-#define S3C2410_LCDCON1_ENVID (1)
-
-#define S3C2410_LCDCON1_MODEMASK 0x1E
-
-#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
-#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
-#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
-#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
-
-#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
-#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
-#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
-
-#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
-#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
-#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
-#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
-#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
-
-#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
-#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
-
-/* LDCCON4 changes for STN mode on the S3C2412 */
-
-#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
-#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
-#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
-
-#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
-
-#define S3C2410_LCDCON5_BPP24BL (1<<12)
-#define S3C2410_LCDCON5_FRM565 (1<<11)
-#define S3C2410_LCDCON5_INVVCLK (1<<10)
-#define S3C2410_LCDCON5_INVVLINE (1<<9)
-#define S3C2410_LCDCON5_INVVFRAME (1<<8)
-#define S3C2410_LCDCON5_INVVD (1<<7)
-#define S3C2410_LCDCON5_INVVDEN (1<<6)
-#define S3C2410_LCDCON5_INVPWREN (1<<5)
-#define S3C2410_LCDCON5_INVLEND (1<<4)
-#define S3C2410_LCDCON5_PWREN (1<<3)
-#define S3C2410_LCDCON5_ENLEND (1<<2)
-#define S3C2410_LCDCON5_BSWP (1<<1)
-#define S3C2410_LCDCON5_HWSWP (1<<0)
-
-/* framebuffer start addressed */
-#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14)
-#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18)
-#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C)
-
-#define S3C2410_LCDBANK(x) ((x) << 21)
-#define S3C2410_LCDBASEU(x) (x)
-
-#define S3C2410_OFFSIZE(x) ((x) << 11)
-#define S3C2410_PAGEWIDTH(x) (x)
-
-/* colour lookup and miscellaneous controls */
-
-#define S3C2410_REDLUT S3C2410_LCDREG(0x20)
-#define S3C2410_GREENLUT S3C2410_LCDREG(0x24)
-#define S3C2410_BLUELUT S3C2410_LCDREG(0x28)
-
-#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
-#define S3C2410_TPAL S3C2410_LCDREG(0x50)
-
-#define S3C2410_TPAL_EN (1<<24)
-
-/* interrupt info */
-#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
-#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
-#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
-#define S3C2410_LCDINT_FIWSEL (1<<2)
-#define S3C2410_LCDINT_FRSYNC (1<<1)
-#define S3C2410_LCDINT_FICNT (1<<0)
-
-/* s3c2442 extra stn registers */
-
-#define S3C2442_REDLUT S3C2410_LCDREG(0x20)
-#define S3C2442_GREENLUT S3C2410_LCDREG(0x24)
-#define S3C2442_BLUELUT S3C2410_LCDREG(0x28)
-#define S3C2442_DITHMODE S3C2410_LCDREG(0x20)
-
-#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
-
-#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
-
-/* S3C2412 registers */
-
-#define S3C2412_TPAL S3C2410_LCDREG(0x20)
-
-#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24)
-#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28)
-#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C)
-
-#define S3C2412_TCONSEL S3C2410_LCDREG(0x30)
-
-#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34)
-#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38)
-#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C)
-#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40)
-
-#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4))
-#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
-#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4))
-
-#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
-
-/* general registers */
-
-/* base of the LCD registers, where INTPND, INTSRC and then INTMSK
- * are available. */
-
-#define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54)
-#define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24)
-
-#define S3C24XX_LCDINTPND (0x00)
-#define S3C24XX_LCDSRCPND (0x04)
-#define S3C24XX_LCDINTMSK (0x08)
-
-#endif /* ___ASM_ARCH_REGS_LCD_H */
diff --git a/arch/arm/mach-s3c24xx/setup-camif.c b/arch/arm/mach-s3c24xx/setup-camif.c
deleted file mode 100644
index 2b262fa..0000000
--- a/arch/arm/mach-s3c24xx/setup-camif.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
-//
-// Helper functions for S3C24XX/S3C64XX SoC series CAMIF driver
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <mach/gpio-samsung.h>
-
-/* Number of camera port pins, without FIELD */
-#define S3C_CAMIF_NUM_GPIOS 13
-
-/* Default camera port configuration helpers. */
-
-static void camif_get_gpios(int *gpio_start, int *gpio_reset)
-{
-#ifdef CONFIG_ARCH_S3C24XX
- *gpio_start = S3C2410_GPJ(0);
- *gpio_reset = S3C2410_GPJ(12);
-#else
- /* s3c64xx */
- *gpio_start = S3C64XX_GPF(0);
- *gpio_reset = S3C64XX_GPF(3);
-#endif
-}
-
-int s3c_camif_gpio_get(void)
-{
- int gpio_start, gpio_reset;
- int ret, i;
-
- camif_get_gpios(&gpio_start, &gpio_reset);
-
- for (i = 0; i < S3C_CAMIF_NUM_GPIOS; i++) {
- int gpio = gpio_start + i;
-
- if (gpio == gpio_reset)
- continue;
-
- ret = gpio_request(gpio, "camif");
- if (!ret)
- ret = s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
- if (ret) {
- pr_err("failed to configure GPIO %d\n", gpio);
- for (--i; i >= 0; i--)
- gpio_free(gpio--);
- return ret;
- }
- s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
- }
-
- return 0;
-}
-
-void s3c_camif_gpio_put(void)
-{
- int i, gpio_start, gpio_reset;
-
- camif_get_gpios(&gpio_start, &gpio_reset);
-
- for (i = 0; i < S3C_CAMIF_NUM_GPIOS; i++) {
- int gpio = gpio_start + i;
- if (gpio != gpio_reset)
- gpio_free(gpio);
- }
-}
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
deleted file mode 100644
index 8caeb4a..0000000
--- a/arch/arm/mach-s3c64xx/Makefile
+++ /dev/null
@@ -1,62 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Copyright 2008 Openmoko, Inc.
-# Copyright 2008 Simtec Electronics
-
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
-asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
-
-# PM
-
-obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_PM_SLEEP) += sleep.o
-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
-
-ifdef CONFIG_SAMSUNG_ATAGS
-
-obj-$(CONFIG_PM_SLEEP) += irq-pm.o
-
-# Core
-
-obj-y += common.o
-obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
-obj-$(CONFIG_CPU_S3C6410) += s3c6410.o
-
-# DMA support
-
-obj-$(CONFIG_S3C64XX_PL080) += pl080.o
-
-# Device support
-
-obj-y += dev-uart.o
-obj-y += dev-audio.o
-
-# Device setup
-
-obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
-obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
-obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
-obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
-obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
-obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
-obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o
-obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy.o
-
-obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
-
-# Machine support
-
-obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o
-obj-$(CONFIG_MACH_HMT) += mach-hmt.o
-obj-$(CONFIG_MACH_MINI6410) += mach-mini6410.o
-obj-$(CONFIG_MACH_NCP) += mach-ncp.o
-obj-$(CONFIG_MACH_REAL6410) += mach-real6410.o
-obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
-obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o
-obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
-obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
-obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
-obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
-endif
-
-obj-$(CONFIG_MACH_S3C64XX_DT) += mach-s3c64xx-dt.o
diff --git a/arch/arm/mach-s3c64xx/include/mach/hardware.h b/arch/arm/mach-s3c64xx/include/mach/hardware.h
deleted file mode 100644
index c4ed359..0000000
--- a/arch/arm/mach-s3c64xx/include/mach/hardware.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C6400 - Hardware support
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H __FILE__
-
-/* currently nothing here, placeholder */
-
-#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
deleted file mode 100644
index bbf79ed..0000000
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
- */
-
-#ifndef __MACH_S3C64XX_PM_CORE_H
-#define __MACH_S3C64XX_PM_CORE_H __FILE__
-
-#include <linux/serial_s3c.h>
-#include <linux/delay.h>
-
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
-#include <mach/map.h>
-
-static inline void s3c_pm_debug_init_uart(void)
-{
- u32 tmp = __raw_readl(S3C_PCLK_GATE);
-
- /* As a note, since the S3C64XX UARTs generally have multiple
- * clock sources, we simply enable PCLK at the moment and hope
- * that the resume settings for the UART are suitable for the
- * use with PCLK.
- */
-
- tmp |= S3C_CLKCON_PCLK_UART0;
- tmp |= S3C_CLKCON_PCLK_UART1;
- tmp |= S3C_CLKCON_PCLK_UART2;
- tmp |= S3C_CLKCON_PCLK_UART3;
-
- __raw_writel(tmp, S3C_PCLK_GATE);
- udelay(10);
-}
-
-static inline void s3c_pm_arch_prepare_irqs(void)
-{
- /* VIC should have already been taken care of */
-
- /* clear any pending EINT0 interrupts */
- __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
-}
-
-static inline void s3c_pm_arch_stop_clocks(void)
-{
-}
-
-static inline void s3c_pm_arch_show_resume_irqs(void)
-{
-}
-
-/* make these defines, we currently do not have any need to change
- * the IRQ wake controls depending on the CPU we are running on */
-#ifdef CONFIG_PM_SLEEP
-#define s3c_irqwake_eintallow ((1 << 28) - 1)
-#define s3c_irqwake_intallow (~0)
-#else
-#define s3c_irqwake_eintallow 0
-#define s3c_irqwake_intallow 0
-#endif
-
-static inline void s3c_pm_arch_update_uart(void __iomem *regs,
- struct pm_uart_save *save)
-{
- u32 ucon = __raw_readl(regs + S3C2410_UCON);
- u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
- u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
- u32 new_ucon;
- u32 delta;
-
- /* S3C64XX UART blocks only support level interrupts, so ensure that
- * when we restore unused UART blocks we force the level interrupt
- * settigs. */
- save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
-
- /* We have a constraint on changing the clock type of the UART
- * between UCLKx and PCLK, so ensure that when we restore UCON
- * that the CLK field is correctly modified if the bootloader
- * has changed anything.
- */
- if (ucon_clk != save_clk) {
- new_ucon = save->ucon;
- delta = ucon_clk ^ save_clk;
-
- /* change from UCLKx => wrong PCLK,
- * either UCLK can be tested for by a bit-test
- * with UCLK0 */
- if (ucon_clk & S3C6400_UCON_UCLK0 &&
- !(save_clk & S3C6400_UCON_UCLK0) &&
- delta & S3C6400_UCON_PCLK2) {
- new_ucon &= ~S3C6400_UCON_UCLK0;
- } else if (delta == S3C6400_UCON_PCLK2) {
- /* as an precaution, don't change from
- * PCLK2 => PCLK or vice-versa */
- new_ucon ^= S3C6400_UCON_PCLK2;
- }
-
- S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
- ucon, new_ucon, save->ucon);
- save->ucon = new_ucon;
- }
-}
-
-static inline void s3c_pm_restored_gpios(void)
-{
- /* ensure sleep mode has been cleared from the system */
-
- __raw_writel(0, S3C64XX_SLPEN);
-}
-
-static inline void samsung_pm_saved_gpios(void)
-{
- /* turn on the sleep mode and keep it there, as it seems that during
- * suspend the xCON registers get re-set and thus you can end up with
- * problems between going to sleep and resuming.
- */
-
- __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
-}
-#endif /* __MACH_S3C64XX_PM_CORE_H */
diff --git a/arch/arm/mach-s3c64xx/watchdog-reset.h b/arch/arm/mach-s3c64xx/watchdog-reset.h
deleted file mode 100644
index 1042d6c..0000000
--- a/arch/arm/mach-s3c64xx/watchdog-reset.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - System define for arch_reset() function
- */
-
-#ifndef __PLAT_SAMSUNG_WATCHDOG_RESET_H
-#define __PLAT_SAMSUNG_WATCHDOG_RESET_H
-
-extern void samsung_wdt_reset(void);
-extern void samsung_wdt_reset_of_init(void);
-extern void samsung_wdt_reset_init(void __iomem *base);
-
-#endif /* __PLAT_SAMSUNG_WATCHDOG_RESET_H */
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 03984a7..95d4e82 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -14,10 +14,10 @@
select COMMON_CLK_SAMSUNG
select GPIOLIB
select HAVE_S3C2410_I2C if I2C
- select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select PINCTRL
select PINCTRL_EXYNOS
+ select SOC_SAMSUNG
help
Samsung S5PV210/S5PC110 series based systems
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index e7b551e..aa0a1f0 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -3,12 +3,5 @@
# Copyright (c) 2010 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/arch/arm/plat-samsung/include
-
-# Core
-
obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
-
-# machine support
-
obj-y += s5pv210.o
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index b336df0..d59c094 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -13,15 +13,56 @@
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
+#include <linux/soc/samsung/s3c-pm.h>
#include <asm/cacheflush.h>
#include <asm/suspend.h>
-#include <plat/pm-common.h>
-
#include "common.h"
#include "regs-clock.h"
+/* helper functions to save and restore register state */
+struct sleep_save {
+ void __iomem *reg;
+ unsigned long val;
+};
+
+#define SAVE_ITEM(x) \
+ { .reg = (x) }
+
+/**
+ * s3c_pm_do_save() - save a set of registers for restoration on resume.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Run through the list of registers given, saving their contents in the
+ * array for later restoration when we wakeup.
+ */
+static void s3c_pm_do_save(struct sleep_save *ptr, int count)
+{
+ for (; count > 0; count--, ptr++) {
+ ptr->val = readl_relaxed(ptr->reg);
+ S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
+ }
+}
+
+/**
+ * s3c_pm_do_restore() - restore register values from the save list.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Restore the register values saved from s3c_pm_do_save().
+ *
+ * WARNING: Do not put any debug in here that may effect memory or use
+ * peripherals, as things may be changing!
+*/
+
+static void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
+{
+ for (; count > 0; count--, ptr++)
+ writel_relaxed(ptr->val, ptr->reg);
+}
+
static struct sleep_save s5pv210_core_save[] = {
/* Clock ETC */
SAVE_ITEM(S5P_MDNIE_SEL),
@@ -99,8 +140,6 @@
u32 eint_wakeup_mask = s5pv210_read_eint_wakeup_mask();
int ret;
- s3c_pm_debug_init();
-
S3C_PMDBG("%s: suspending the system...\n", __func__);
S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
@@ -113,7 +152,7 @@
return -EINVAL;
}
- s3c_pm_save_uarts();
+ s3c_pm_save_uarts(false);
s5pv210_pm_prepare();
flush_cache_all();
s3c_pm_check_store();
@@ -122,7 +161,7 @@
if (ret)
return ret;
- s3c_pm_restore_uarts();
+ s3c_pm_restore_uarts(false);
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
__raw_readl(S5P_WAKEUP_STAT));
diff --git a/arch/arm/mach-s5pv210/regs-clock.h b/arch/arm/mach-s5pv210/regs-clock.h
index 2a35c83..9cad230 100644
--- a/arch/arm/mach-s5pv210/regs-clock.h
+++ b/arch/arm/mach-s5pv210/regs-clock.h
@@ -9,7 +9,9 @@
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
-#include <plat/map-base.h>
+#define S3C_ADDR_BASE 0xF6000000
+#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
+#define S3C_VA_SYS S3C_ADDR(0x00100000)
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
diff --git a/arch/arm/mach-s5pv210/s5pv210.c b/arch/arm/mach-s5pv210/s5pv210.c
index 868f9c2..a21ed3b 100644
--- a/arch/arm/mach-s5pv210/s5pv210.c
+++ b/arch/arm/mach-s5pv210/s5pv210.c
@@ -13,8 +13,6 @@
#include <asm/mach/map.h>
#include <asm/system_misc.h>
-#include <plat/map-base.h>
-
#include "common.h"
#include "regs-clock.h"
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index d96a101..2012fa8 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -34,7 +34,6 @@
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/tlbflush.h>
#include <asm/mach/arch.h>
@@ -633,7 +632,7 @@
int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
pmd_t *pmd;
- pmd = pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
+ pmd = pmd_off_k(virt);
*pmd = __pmd(phys | prot);
flush_pmd_entry(pmd);
}
@@ -653,7 +652,7 @@
*/
static void __init get_assabet_scr(void)
{
- unsigned long uninitialized_var(scr), i;
+ unsigned long scr, i;
GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */
GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 3cc2b71..bd3a52f 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -30,6 +30,7 @@
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
+#include <linux/gpio/machine.h>
#include <linux/power/gpio-charger.h>
#include <video/sa1100fb.h>
@@ -131,16 +132,23 @@
/*
* Collie AC IN
*/
+static struct gpiod_lookup_table collie_power_gpiod_table = {
+ .dev_id = "gpio-charger",
+ .table = {
+ GPIO_LOOKUP("gpio", COLLIE_GPIO_AC_IN,
+ NULL, GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static char *collie_ac_supplied_to[] = {
"main-battery",
"backup-battery",
};
-
static struct gpio_charger_platform_data collie_power_data = {
.name = "charger",
.type = POWER_SUPPLY_TYPE_MAINS,
- .gpio = COLLIE_GPIO_AC_IN,
.supplied_to = collie_ac_supplied_to,
.num_supplicants = ARRAY_SIZE(collie_ac_supplied_to),
};
@@ -386,6 +394,8 @@
platform_scoop_config = &collie_pcmcia_config;
+ gpiod_add_lookup_table(&collie_power_gpiod_table);
+
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
if (ret) {
printk(KERN_WARNING "collie: Unable to register LoCoMo device\n");
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index 6d37d26..3085f1c 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -22,11 +22,11 @@
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
+#include <linux/pgtable.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <asm/page.h>
-#include <asm/pgtable.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 5bc82e2..351f891 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -104,6 +104,14 @@
.enabled_at_boot = 1,
};
+static struct gpiod_lookup_table shannon_display_gpio_table = {
+ .dev_id = "sa11x0-fb",
+ .table = {
+ GPIO_LOOKUP("gpio", 22, "shannon-lcden", GPIO_ACTIVE_HIGH),
+ { },
+ },
+};
+
static void __init shannon_init(void)
{
sa11x0_register_fixed_regulator(0, &shannon_cf_vcc_pdata,
@@ -113,6 +121,7 @@
sa11x0_register_pcmcia(0, &shannon_pcmcia0_gpio_table);
sa11x0_register_pcmcia(1, &shannon_pcmcia1_gpio_table);
sa11x0_ppc_configure_mcp();
+ gpiod_add_lookup_table(&shannon_display_gpio_table);
sa11x0_register_lcd(&shannon_lcd_info);
sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
sa11x0_register_mcp(&shannon_mcp_data);
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 96330ef..e771ce7 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -189,7 +189,7 @@
if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
return;
- apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
+ apmu_cpus[cpu].iomem = ioremap(res->start, resource_size(res));
apmu_cpus[cpu].bit = bit;
pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index e84599d..6720814 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -103,7 +103,7 @@
iounmap(p);
/* setup reset vectors */
- p = ioremap_nocache(RST, 0x63);
+ p = ioremap(RST, 0x63);
bar = phys_to_sbar(res.start);
if (has_a15) {
writel_relaxed(bar, p + CA15BAR);
diff --git a/arch/arm/mach-shmobile/rcar-gen2.h b/arch/arm/mach-shmobile/rcar-gen2.h
index 4777fff..af9dbd6 100644
--- a/arch/arm/mach-shmobile/rcar-gen2.h
+++ b/arch/arm/mach-shmobile/rcar-gen2.h
@@ -2,8 +2,6 @@
#ifndef __ASM_RCAR_GEN2_H__
#define __ASM_RCAR_GEN2_H__
-void rcar_gen2_timer_init(void);
-void rcar_gen2_reserve(void);
void rcar_gen2_pm_init(void);
#endif /* __ASM_RCAR_GEN2_H__ */
diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
index ee94925..09ef73b 100644
--- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
@@ -154,8 +154,10 @@
return -ENODEV;
for_each_matching_node_and_match(np, rcar_gen2_quirk_match, &id) {
- if (!of_device_is_available(np))
+ if (!of_device_is_available(np)) {
+ of_node_put(np);
break;
+ }
ret = of_property_read_u32(np, "reg", &addr);
if (ret) /* Skip invalid entry and continue */
@@ -164,6 +166,7 @@
quirk = kzalloc(sizeof(*quirk), GFP_KERNEL);
if (!quirk) {
ret = -ENOMEM;
+ of_node_put(np);
goto err_mem;
}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 787d039..f760c27 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -28,7 +28,7 @@
{
void __iomem *reg;
- reg = ioremap_nocache(MEBUFCNTR, 4);
+ reg = ioremap(MEBUFCNTR, 4);
if (reg) {
iowrite32(0x01600164, reg);
iounmap(reg);
@@ -37,9 +37,9 @@
static void __init r8a7740_init_irq_of(void)
{
- void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
- void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
- void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
+ void __iomem *intc_prio_base = ioremap(0xe6900010, 0x10);
+ void __iomem *intc_msk_base = ioremap(0xe6900040, 0x10);
+ void __iomem *pfc_inta_ctrl = ioremap(0xe605807c, 0x4);
irqchip_init();
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index ce51794..2bc93f3 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -22,7 +22,7 @@
static void __init r8a7778_init_irq_dt(void)
{
- void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
+ void __iomem *base = ioremap(0xfe700000, 0x00100000);
BUG_ON(!base);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index b13ec90..86406e3 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -72,7 +72,6 @@
DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
.smp = smp_ops(r8a7779_smp_ops),
.map_io = r8a7779_map_io,
- .init_early = shmobile_init_delay,
.init_irq = r8a7779_init_irq_dt,
.init_late = shmobile_init_late,
.dt_compat = r8a7779_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 9e4bc18..d42d934 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -7,14 +7,14 @@
* Copyright (C) 2014 Ulrich Hecht
*/
-#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/device.h>
-#include <linux/dma-contiguous.h>
+#include <linux/dma-map-ops.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/memblock.h>
#include <linux/of.h>
+#include <linux/of_clk.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/psci.h>
@@ -24,7 +24,7 @@
#include "rcar-gen2.h"
static const struct of_device_id cpg_matches[] __initconst = {
- { .compatible = "renesas,rcar-gen2-cpg-clocks", },
+ { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
{ .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
@@ -59,7 +59,7 @@
#define CNTCR 0
#define CNTFID0 0x20
-void __init rcar_gen2_timer_init(void)
+static void __init rcar_gen2_timer_init(void)
{
bool need_update = true;
void __iomem *base;
@@ -174,7 +174,7 @@
return 0;
}
-void __init rcar_gen2_reserve(void)
+static void __init rcar_gen2_reserve(void)
{
struct memory_reserve_config mrc;
@@ -210,6 +210,7 @@
MACHINE_END
static const char * const rz_g1_boards_compat_dt[] __initconst = {
+ "renesas,r8a7742",
"renesas,r8a7743",
"renesas,r8a7744",
"renesas,r8a7745",
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index cc08aa7..eb4a62f 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -56,7 +56,6 @@
DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
.smp = smp_ops(sh73a0_smp_ops),
.map_io = sh73a0_map_io,
- .init_early = shmobile_init_delay,
.init_machine = sh73a0_generic_init,
.init_late = shmobile_init_late,
.dt_compat = sh73a0_boards_compat_dt,
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 22af5e3..b62ae4d 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -2,6 +2,7 @@
menuconfig ARCH_SOCFPGA
bool "Altera SOCFPGA family"
depends on ARCH_MULTI_V7
+ select ARCH_HAS_RESET_CONTROLLER
select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select ARM_GIC
@@ -11,7 +12,6 @@
select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
select MFD_SYSCON
- select PCI_DOMAINS_GENERIC if PCI
select ARM_ERRATA_754322
select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420
@@ -19,6 +19,7 @@
select PL310_ERRATA_727915
select PL310_ERRATA_753970 if PL310
select PL310_ERRATA_769419
+ select RESET_CONTROLLER
if ARCH_SOCFPGA
config SOCFPGA_SUSPEND
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index fc2608b..18f0119 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -33,7 +33,7 @@
u32 socfpga_sdram_self_refresh(u32 sdr_base);
extern unsigned int socfpga_sdram_self_refresh_sz;
-extern char secondary_trampoline, secondary_trampoline_end;
+extern char secondary_trampoline[], secondary_trampoline_end[];
extern unsigned long socfpga_cpu1start_addr;
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index fbb80b8..201191c 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -20,14 +20,14 @@
static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
- int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+ int trampoline_size = secondary_trampoline_end - secondary_trampoline;
if (socfpga_cpu1start_addr) {
/* This will put CPU #1 into reset. */
writel(RSTMGR_MPUMODRST_CPU1,
rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
- memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+ memcpy(phys_to_virt(0), secondary_trampoline, trampoline_size);
writel(__pa_symbol(secondary_startup),
sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
@@ -45,12 +45,12 @@
static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
- int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+ int trampoline_size = secondary_trampoline_end - secondary_trampoline;
if (socfpga_cpu1start_addr) {
writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr +
SOCFPGA_A10_RSTMGR_MODMPURST);
- memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+ memcpy(phys_to_virt(0), secondary_trampoline, trampoline_size);
writel(__pa_symbol(secondary_startup),
sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 47ebcc8..9e4cb2f 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -73,10 +73,10 @@
temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
- if (mode == REBOOT_HARD)
- temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
- else
+ if (mode == REBOOT_WARM)
temp |= RSTMGR_CTRL_SWWARMRSTREQ;
+ else
+ temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
}
@@ -86,10 +86,10 @@
temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
- if (mode == REBOOT_HARD)
- temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
- else
+ if (mode == REBOOT_WARM)
temp |= RSTMGR_CTRL_SWWARMRSTREQ;
+ else
+ temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
}
diff --git a/arch/arm/mach-spear/time.c b/arch/arm/mach-spear/time.c
index 289e036..d1fdb60 100644
--- a/arch/arm/mach-spear/time.c
+++ b/arch/arm/mach-spear/time.c
@@ -181,12 +181,6 @@
return IRQ_HANDLED;
}
-static struct irqaction spear_timer_irq = {
- .name = "timer",
- .flags = IRQF_TIMER,
- .handler = spear_timer_interrupt
-};
-
static void __init spear_clockevent_init(int irq)
{
u32 tick_rate;
@@ -201,7 +195,8 @@
clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
- setup_irq(irq, &spear_timer_irq);
+ if (request_irq(irq, spear_timer_interrupt, IRQF_TIMER, "timer", NULL))
+ pr_err("Failed to request irq %d (timer)\n", irq);
}
static const struct of_device_id timer_of_match[] __initconst = {
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index dcb9893..ffecbf2 100644
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -20,14 +20,6 @@
NULL
};
-static void sti_l2_write_sec(unsigned long val, unsigned reg)
-{
- /*
- * We can't write to secure registers as we are in non-secure
- * mode, until we have some SMI service available.
- */
-}
-
DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree")
.dt_compat = stih41x_dt_match,
.l2c_aux_val = L2C_AUX_CTRL_SHARED_OVERRIDE |
@@ -36,5 +28,4 @@
L2C_AUX_CTRL_WAY_SIZE(4),
.l2c_aux_mask = 0xc0000fff,
.smp = smp_ops(sti_smp_ops),
- .l2c_write_sec = sti_l2_write_sec,
MACHINE_END
diff --git a/arch/arm/mach-stm32/Makefile.boot b/arch/arm/mach-stm32/Makefile.boot
index cec195d..5dde732 100644
--- a/arch/arm/mach-stm32/Makefile.boot
+++ b/arch/arm/mach-stm32/Makefile.boot
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
# Empty file waiting for deletion once Makefile.boot isn't needed any more.
# Patch waits for application at
-# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .
+# https://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 .
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index a0ca5e7..1963572 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -10,9 +10,9 @@
* warranty of any kind, whether express or implied.
*/
-#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/init.h>
+#include <linux/of_clk.h>
#include <linux/platform_device.h>
#include <linux/reset/sunxi.h>
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 6c1dff2..07572b5 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -8,29 +8,14 @@
obj-y += reset-handler.o
obj-y += sleep.o
obj-y += tegra.o
-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
+obj-y += sleep-tegra20.o
+obj-y += sleep-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o
-ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
-endif
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
-ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
-endif
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o
-ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
-endif
-obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o
-ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o
-endif
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
deleted file mode 100644
index 5118f77..0000000
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ /dev/null
@@ -1,89 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
- */
-
-#include <asm/firmware.h>
-#include <linux/tick.h>
-#include <linux/cpuidle.h>
-#include <linux/cpu_pm.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <linux/firmware/trusted_foundations.h>
-
-#include <asm/cpuidle.h>
-#include <asm/smp_plat.h>
-#include <asm/suspend.h>
-#include <asm/psci.h>
-
-#include "cpuidle.h"
-#include "pm.h"
-#include "sleep.h"
-
-#ifdef CONFIG_PM_SLEEP
-#define TEGRA114_MAX_STATES 2
-#else
-#define TEGRA114_MAX_STATES 1
-#endif
-
-#ifdef CONFIG_PM_SLEEP
-static int tegra114_idle_power_down(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- local_fiq_disable();
-
- tegra_set_cpu_in_lp2();
- cpu_pm_enter();
-
- call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);
-
- /* Do suspend by ourselves if the firmware does not implement it */
- if (call_firmware_op(do_idle, 0) == -ENOSYS)
- cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
-
- cpu_pm_exit();
- tegra_clear_cpu_in_lp2();
-
- local_fiq_enable();
-
- return index;
-}
-
-static void tegra114_idle_enter_s2idle(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- tegra114_idle_power_down(dev, drv, index);
-}
-#endif
-
-static struct cpuidle_driver tegra_idle_driver = {
- .name = "tegra_idle",
- .owner = THIS_MODULE,
- .state_count = TEGRA114_MAX_STATES,
- .states = {
- [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
-#ifdef CONFIG_PM_SLEEP
- [1] = {
- .enter = tegra114_idle_power_down,
- .enter_s2idle = tegra114_idle_enter_s2idle,
- .exit_latency = 500,
- .target_residency = 1000,
- .flags = CPUIDLE_FLAG_TIMER_STOP,
- .power_usage = 0,
- .name = "powered-down",
- .desc = "CPU power gated",
- },
-#endif
- },
-};
-
-int __init tegra114_cpuidle_init(void)
-{
- if (!psci_smp_available())
- return cpuidle_register(&tegra_idle_driver, NULL);
-
- return 0;
-}
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
deleted file mode 100644
index 2447427..0000000
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ /dev/null
@@ -1,212 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * CPU idle driver for Tegra CPUs
- *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
- * Copyright (c) 2011 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- * Gary King <gking@nvidia.com>
- *
- * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
- */
-
-#include <linux/clk/tegra.h>
-#include <linux/tick.h>
-#include <linux/cpuidle.h>
-#include <linux/cpu_pm.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <soc/tegra/flowctrl.h>
-
-#include <asm/cpuidle.h>
-#include <asm/smp_plat.h>
-#include <asm/suspend.h>
-
-#include "cpuidle.h"
-#include "iomap.h"
-#include "irq.h"
-#include "pm.h"
-#include "reset.h"
-#include "sleep.h"
-
-#ifdef CONFIG_PM_SLEEP
-static bool abort_flag;
-static atomic_t abort_barrier;
-static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index);
-#define TEGRA20_MAX_STATES 2
-#else
-#define TEGRA20_MAX_STATES 1
-#endif
-
-static struct cpuidle_driver tegra_idle_driver = {
- .name = "tegra_idle",
- .owner = THIS_MODULE,
- .states = {
- ARM_CPUIDLE_WFI_STATE_PWR(600),
-#ifdef CONFIG_PM_SLEEP
- {
- .enter = tegra20_idle_lp2_coupled,
- .exit_latency = 5000,
- .target_residency = 10000,
- .power_usage = 0,
- .flags = CPUIDLE_FLAG_COUPLED |
- CPUIDLE_FLAG_TIMER_STOP,
- .name = "powered-down",
- .desc = "CPU power gated",
- },
-#endif
- },
- .state_count = TEGRA20_MAX_STATES,
- .safe_state_index = 0,
-};
-
-#ifdef CONFIG_PM_SLEEP
-#ifdef CONFIG_SMP
-static int tegra20_reset_sleeping_cpu_1(void)
-{
- int ret = 0;
-
- tegra_pen_lock();
-
- if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE)
- tegra20_cpu_shutdown(1);
- else
- ret = -EINVAL;
-
- tegra_pen_unlock();
-
- return ret;
-}
-
-static void tegra20_wake_cpu1_from_reset(void)
-{
- tegra_pen_lock();
-
- tegra20_cpu_clear_resettable();
-
- /* enable cpu clock on cpu */
- tegra_enable_cpu_clock(1);
-
- /* take the CPU out of reset */
- tegra_cpu_out_of_reset(1);
-
- /* unhalt the cpu */
- flowctrl_write_cpu_halt(1, 0);
-
- tegra_pen_unlock();
-}
-
-static int tegra20_reset_cpu_1(void)
-{
- if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
- return 0;
-
- tegra20_wake_cpu1_from_reset();
- return -EBUSY;
-}
-#else
-static inline void tegra20_wake_cpu1_from_reset(void)
-{
-}
-
-static inline int tegra20_reset_cpu_1(void)
-{
- return 0;
-}
-#endif
-
-static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- while (tegra20_cpu_is_resettable_soon())
- cpu_relax();
-
- if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
- return false;
-
- tegra_idle_lp2_last();
-
- if (cpu_online(1))
- tegra20_wake_cpu1_from_reset();
-
- return true;
-}
-
-#ifdef CONFIG_SMP
-static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
-
- tegra20_cpu_clear_resettable();
-
- return true;
-}
-#else
-static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- return true;
-}
-#endif
-
-static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- bool entered_lp2 = false;
-
- if (tegra_pending_sgi())
- WRITE_ONCE(abort_flag, true);
-
- cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
-
- if (abort_flag) {
- cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
- abort_flag = false; /* clean flag for next coming */
- return -EINTR;
- }
-
- local_fiq_disable();
-
- tegra_set_cpu_in_lp2();
- cpu_pm_enter();
-
- if (dev->cpu == 0)
- entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
- else
- entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
-
- cpu_pm_exit();
- tegra_clear_cpu_in_lp2();
-
- local_fiq_enable();
-
- smp_rmb();
-
- return entered_lp2 ? index : 0;
-}
-#endif
-
-/*
- * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
- * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
- * this, simply disable LP2 if the PCI driver and DT node are both enabled.
- */
-void tegra20_cpuidle_pcie_irqs_in_use(void)
-{
- pr_info_once(
- "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
- tegra_idle_driver.states[1].disabled = true;
-}
-
-int __init tegra20_cpuidle_init(void)
-{
- return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
-}
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
deleted file mode 100644
index c612852..0000000
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ /dev/null
@@ -1,132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * CPU idle driver for Tegra CPUs
- *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
- * Copyright (c) 2011 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- * Gary King <gking@nvidia.com>
- *
- * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
- */
-
-#include <linux/clk/tegra.h>
-#include <linux/tick.h>
-#include <linux/cpuidle.h>
-#include <linux/cpu_pm.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/cpuidle.h>
-#include <asm/smp_plat.h>
-#include <asm/suspend.h>
-
-#include "cpuidle.h"
-#include "pm.h"
-#include "sleep.h"
-
-#ifdef CONFIG_PM_SLEEP
-static int tegra30_idle_lp2(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index);
-#endif
-
-static struct cpuidle_driver tegra_idle_driver = {
- .name = "tegra_idle",
- .owner = THIS_MODULE,
-#ifdef CONFIG_PM_SLEEP
- .state_count = 2,
-#else
- .state_count = 1,
-#endif
- .states = {
- [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
-#ifdef CONFIG_PM_SLEEP
- [1] = {
- .enter = tegra30_idle_lp2,
- .exit_latency = 2000,
- .target_residency = 2200,
- .power_usage = 0,
- .flags = CPUIDLE_FLAG_TIMER_STOP,
- .name = "powered-down",
- .desc = "CPU power gated",
- },
-#endif
- },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- /* All CPUs entering LP2 is not working.
- * Don't let CPU0 enter LP2 when any secondary CPU is online.
- */
- if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
- cpu_do_idle();
- return false;
- }
-
- tegra_idle_lp2_last();
-
- return true;
-}
-
-#ifdef CONFIG_SMP
-static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- smp_wmb();
-
- cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
-
- return true;
-}
-#else
-static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- return true;
-}
-#endif
-
-static int tegra30_idle_lp2(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- bool entered_lp2 = false;
- bool last_cpu;
-
- local_fiq_disable();
-
- last_cpu = tegra_set_cpu_in_lp2();
- cpu_pm_enter();
-
- if (dev->cpu == 0) {
- if (last_cpu)
- entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
- index);
- else
- cpu_do_idle();
- } else {
- entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
- }
-
- cpu_pm_exit();
- tegra_clear_cpu_in_lp2();
-
- local_fiq_enable();
-
- smp_rmb();
-
- return (entered_lp2) ? index : 0;
-}
-#endif
-
-int __init tegra30_cpuidle_init(void)
-{
- return cpuidle_register(&tegra_idle_driver, NULL);
-}
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
deleted file mode 100644
index d565c44..0000000
--- a/arch/arm/mach-tegra/cpuidle.c
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-tegra/cpuidle.c
- *
- * CPU idle driver for Tegra CPUs
- *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
- * Copyright (c) 2011 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- * Gary King <gking@nvidia.com>
- *
- * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <soc/tegra/fuse.h>
-
-#include "cpuidle.h"
-
-void __init tegra_cpuidle_init(void)
-{
- switch (tegra_get_chip_id()) {
- case TEGRA20:
- if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
- tegra20_cpuidle_init();
- break;
- case TEGRA30:
- if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
- tegra30_cpuidle_init();
- break;
- case TEGRA114:
- case TEGRA124:
- if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
- IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
- tegra114_cpuidle_init();
- break;
- }
-}
-
-void tegra_cpuidle_pcie_irqs_in_use(void)
-{
- switch (tegra_get_chip_id()) {
- case TEGRA20:
- if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
- tegra20_cpuidle_pcie_irqs_in_use();
- break;
- }
-}
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
deleted file mode 100644
index 4e1f459..0000000
--- a/arch/arm/mach-tegra/cpuidle.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
- */
-
-#ifndef __MACH_TEGRA_CPUIDLE_H
-#define __MACH_TEGRA_CPUIDLE_H
-
-#ifdef CONFIG_CPU_IDLE
-int tegra20_cpuidle_init(void);
-void tegra20_cpuidle_pcie_irqs_in_use(void);
-int tegra30_cpuidle_init(void);
-int tegra114_cpuidle_init(void);
-void tegra_cpuidle_init(void);
-void tegra_cpuidle_pcie_irqs_in_use(void);
-#else
-static inline void tegra_cpuidle_init(void) {}
-static inline void tegra_cpuidle_pcie_irqs_in_use(void) {}
-#endif
-
-#endif
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 160cb18..4cb7e5f 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -10,7 +10,7 @@
#ifndef __MACH_TEGRA_IOMAP_H
#define __MACH_TEGRA_IOMAP_H
-#include <asm/pgtable.h>
+#include <linux/pgtable.h>
#include <linux/sizes.h>
#define TEGRA_IRAM_BASE 0x40000000
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index ace7a39..4e1ee70 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -18,9 +18,10 @@
#include <linux/of.h>
#include <linux/syscore_ops.h>
+#include <soc/tegra/irq.h>
+
#include "board.h"
#include "iomap.h"
-#include "irq.h"
#define SGI_MASK 0xFFFF
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h
deleted file mode 100644
index 7a94cf1..0000000
--- a/arch/arm/mach-tegra/irq.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
- */
-
-#ifndef __TEGRA_IRQ_H
-#define __TEGRA_IRQ_H
-
-bool tegra_pending_sgi(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 3cab81b..6452ebf 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -110,7 +110,7 @@
flowctrl_cpu_suspend_enter(cpu);
}
-void tegra_clear_cpu_in_lp2(void)
+void tegra_pm_clear_cpu_in_lp2(void)
{
int phy_cpu_id = cpu_logical_map(smp_processor_id());
u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
@@ -123,11 +123,9 @@
spin_unlock(&tegra_lp2_lock);
}
-bool tegra_set_cpu_in_lp2(void)
+void tegra_pm_set_cpu_in_lp2(void)
{
int phy_cpu_id = cpu_logical_map(smp_processor_id());
- bool last_cpu = false;
- cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
spin_lock(&tegra_lp2_lock);
@@ -135,22 +133,15 @@
BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
*cpu_in_lp2 |= BIT(phy_cpu_id);
- if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
- last_cpu = true;
- else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1)
- tegra20_cpu_set_resettable_soon();
-
spin_unlock(&tegra_lp2_lock);
- return last_cpu;
-}
-
-int tegra_cpu_do_idle(void)
-{
- return cpu_do_idle();
}
static int tegra_sleep_cpu(unsigned long v2p)
{
+ if (tegra_cpu_car_ops->rail_off_ready &&
+ WARN_ON(!tegra_cpu_rail_off_ready()))
+ return -EBUSY;
+
/*
* L2 cache disabling using kernel API only allowed when all
* secondary CPU's are offline. Cache have to be disabled with
@@ -159,9 +150,10 @@
* if any of secondary CPU's is online and this is the LP2-idle
* code-path only for Tegra20/30.
*/
- if (trusted_foundations_registered())
- outer_disable();
-
+#ifdef CONFIG_OUTER_CACHE
+ if (trusted_foundations_registered() && outer_cache.disable)
+ outer_cache.disable();
+#endif
/*
* Note that besides of setting up CPU reset vector this firmware
* call may also do the following, depending on the FW version:
@@ -202,14 +194,16 @@
tegra_pmc_enter_suspend_mode(mode);
}
-void tegra_idle_lp2_last(void)
+int tegra_pm_enter_lp2(void)
{
+ int err;
+
tegra_pm_set(TEGRA_SUSPEND_LP2);
cpu_cluster_pm_enter();
suspend_cpu_complex();
- cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+ err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
/*
* Resume L2 cache if it wasn't re-enabled early during resume,
@@ -221,6 +215,10 @@
restore_cpu_complex();
cpu_cluster_pm_exit();
+
+ call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
+
+ return err;
}
enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
@@ -365,7 +363,7 @@
tegra_suspend_enter_lp1();
break;
case TEGRA_SUSPEND_LP2:
- tegra_set_cpu_in_lp2();
+ tegra_pm_set_cpu_in_lp2();
break;
default:
break;
@@ -386,7 +384,7 @@
tegra_suspend_exit_lp1();
break;
case TEGRA_SUSPEND_LP2:
- tegra_clear_cpu_in_lp2();
+ tegra_pm_clear_cpu_in_lp2();
break;
default:
break;
@@ -395,6 +393,8 @@
local_fiq_enable();
+ call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
+
return 0;
}
@@ -436,4 +436,18 @@
suspend_set_ops(&tegra_suspend_ops);
}
+
+int tegra_pm_park_secondary_cpu(unsigned long cpu)
+{
+ if (cpu > 0) {
+ tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS);
+
+ if (tegra_get_chip_id() == TEGRA20)
+ tegra20_hotplug_shutdown();
+ else
+ tegra30_hotplug_shutdown();
+ }
+
+ return -EINVAL;
+}
#endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 569151b..81525f5 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -23,10 +23,6 @@
void tegra30_lp1_iram_hook(void);
void tegra30_sleep_core_init(void);
-void tegra_clear_cpu_in_lp2(void);
-bool tegra_set_cpu_in_lp2(void);
-int tegra_cpu_do_idle(void);
-void tegra_idle_lp2_last(void);
extern void (*tegra_tear_down_cpu)(void);
#ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index e3f3481..06ca44b 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -98,7 +98,12 @@
reteq lr
.arch_extension sec
- /* First call after suspend wakes firmware. No arguments required. */
+ /*
+ * First call after suspend wakes firmware. No arguments required
+ * for some firmware versions. Downstream kernel of ASUS TF300T uses
+ * r0=3 for the wake-up notification.
+ */
+ mov r0, #3
smc #0
b cpu_resume
@@ -183,17 +188,6 @@
bleq __die @ CPU not present (to OS)
#endif
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- /* Are we on Tegra20? */
- cmp r6, #TEGRA20
- bne 1f
- /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
- mov r0, #CPU_NOT_RESETTABLE
- cmp r10, #0
- strbne r0, [r12, #RESET_DATA(RESETTABLE_STATUS)]
-1:
-#endif
-
/* Waking up from LP1? */
ldr r8, [r12, #RESET_DATA(MASK_LP1)]
tst r8, r11 @ if in_lp1
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 76a65df..d5c805a 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -70,7 +70,7 @@
switch (err) {
case -ENOSYS:
tegra_cpu_reset_handler_set(reset_address);
- /* fall through */
+ fallthrough;
case 0:
is_enabled = true;
break;
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index a4cfc08..5126559 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -16,9 +16,8 @@
#define TEGRA_RESET_STARTUP_SECONDARY 3
#define TEGRA_RESET_STARTUP_LP2 4
#define TEGRA_RESET_STARTUP_LP1 5
-#define TEGRA_RESET_RESETTABLE_STATUS 6
-#define TEGRA_RESET_TF_PRESENT 7
-#define TEGRA_RESET_DATA_SIZE 8
+#define TEGRA_RESET_TF_PRESENT 6
+#define TEGRA_RESET_DATA_SIZE 7
#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
@@ -42,10 +41,6 @@
(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
(u32)__tegra_cpu_reset_handler_start)))
-#define tegra20_cpu1_resettable_status \
- (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
- ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \
- (u32)__tegra_cpu_reset_handler_start)))
#endif
#define tegra_cpu_reset_handler_offset \
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 9a89f30..0e00ba8 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -43,9 +43,6 @@
#define APB_MISC_XM2CFGCPADCTRL2 0x8e4
#define APB_MISC_XM2CFGDPADCTRL2 0x8e8
-#define __tegra20_cpu1_resettable_status_offset \
- (__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS))
-
.macro pll_enable, rd, r_car_base, pll_base
ldr \rd, [\r_car_base, #\pll_base]
tst \rd, #(1 << 30)
@@ -90,10 +87,6 @@
ENTRY(tegra20_cpu_shutdown)
cmp r0, #0
reteq lr @ must not be called for CPU 0
- mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
- mov r12, #CPU_RESETTABLE
- strb r12, [r1, r2]
cpu_to_halt_reg r1, r0
ldr r3, =TEGRA_FLOW_CTRL_VIRT
@@ -117,107 +110,6 @@
#ifdef CONFIG_PM_SLEEP
/*
- * tegra_pen_lock
- *
- * spinlock implementation with no atomic test-and-set and no coherence
- * using Peterson's algorithm on strongly-ordered registers
- * used to synchronize a cpu waking up from wfi with entering lp2 on idle
- *
- * The reference link of Peterson's algorithm:
- * http://en.wikipedia.org/wiki/Peterson's_algorithm
- *
- * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
- * on cpu 0:
- * r2 = flag[0] (in SCRATCH38)
- * r3 = flag[1] (in SCRATCH39)
- * on cpu1:
- * r2 = flag[1] (in SCRATCH39)
- * r3 = flag[0] (in SCRATCH38)
- *
- * must be called with MMU on
- * corrupts r0-r3, r12
- */
-ENTRY(tegra_pen_lock)
- mov32 r3, TEGRA_PMC_VIRT
- cpu_id r0
- add r1, r3, #PMC_SCRATCH37
- cmp r0, #0
- addeq r2, r3, #PMC_SCRATCH38
- addeq r3, r3, #PMC_SCRATCH39
- addne r2, r3, #PMC_SCRATCH39
- addne r3, r3, #PMC_SCRATCH38
-
- mov r12, #1
- str r12, [r2] @ flag[cpu] = 1
- dsb
- str r12, [r1] @ !turn = cpu
-1: dsb
- ldr r12, [r3]
- cmp r12, #1 @ flag[!cpu] == 1?
- ldreq r12, [r1]
- cmpeq r12, r0 @ !turn == cpu?
- beq 1b @ while !turn == cpu && flag[!cpu] == 1
-
- ret lr @ locked
-ENDPROC(tegra_pen_lock)
-
-ENTRY(tegra_pen_unlock)
- dsb
- mov32 r3, TEGRA_PMC_VIRT
- cpu_id r0
- cmp r0, #0
- addeq r2, r3, #PMC_SCRATCH38
- addne r2, r3, #PMC_SCRATCH39
- mov r12, #0
- str r12, [r2]
- ret lr
-ENDPROC(tegra_pen_unlock)
-
-/*
- * tegra20_cpu_clear_resettable(void)
- *
- * Called to clear the "resettable soon" flag in IRAM variable when
- * it is expected that the secondary CPU will be idle soon.
- */
-ENTRY(tegra20_cpu_clear_resettable)
- mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
- mov r12, #CPU_NOT_RESETTABLE
- strb r12, [r1, r2]
- ret lr
-ENDPROC(tegra20_cpu_clear_resettable)
-
-/*
- * tegra20_cpu_set_resettable_soon(void)
- *
- * Called to set the "resettable soon" flag in IRAM variable when
- * it is expected that the secondary CPU will be idle soon.
- */
-ENTRY(tegra20_cpu_set_resettable_soon)
- mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
- mov r12, #CPU_RESETTABLE_SOON
- strb r12, [r1, r2]
- ret lr
-ENDPROC(tegra20_cpu_set_resettable_soon)
-
-/*
- * tegra20_cpu_is_resettable_soon(void)
- *
- * Returns true if the "resettable soon" flag in IRAM variable has been
- * set because it is expected that the secondary CPU will be idle soon.
- */
-ENTRY(tegra20_cpu_is_resettable_soon)
- mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
- ldrb r12, [r1, r2]
- cmp r12, #CPU_RESETTABLE_SOON
- moveq r0, #1
- movne r0, #0
- ret lr
-ENDPROC(tegra20_cpu_is_resettable_soon)
-
-/*
* tegra20_sleep_core_finish(unsigned long v2p)
*
* Enters suspend in LP0 or LP1 by turning off the mmu and jumping to
@@ -243,68 +135,6 @@
ENDPROC(tegra20_sleep_core_finish)
/*
- * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
- *
- * Enters WFI on secondary CPU by exiting coherency.
- */
-ENTRY(tegra20_sleep_cpu_secondary_finish)
- stmfd sp!, {r4-r11, lr}
-
- mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency
-
- /* Flush and disable the L1 data cache */
- mov r0, #TEGRA_FLUSH_CACHE_LOUIS
- bl tegra_disable_clean_inv_dcache
-
- mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r4, =__tegra20_cpu1_resettable_status_offset
- mov r3, #CPU_RESETTABLE
- strb r3, [r0, r4]
-
- bl tegra_cpu_do_idle
-
- /*
- * cpu may be reset while in wfi, which will return through
- * tegra_resume to cpu_resume
- * or interrupt may wake wfi, which will return here
- * cpu state is unchanged - MMU is on, cache is on, coherency
- * is off, and the data cache is off
- *
- * r11 contains the original actlr
- */
-
- bl tegra_pen_lock
-
- mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r4, =__tegra20_cpu1_resettable_status_offset
- mov r3, #CPU_NOT_RESETTABLE
- strb r3, [r0, r4]
-
- bl tegra_pen_unlock
-
- /* Re-enable the data cache */
- mrc p15, 0, r10, c1, c0, 0
- orr r10, r10, #CR_C
- mcr p15, 0, r10, c1, c0, 0
- isb
-
- mcr p15, 0, r11, c1, c0, 1 @ reenable coherency
-
- /* Invalidate the TLBs & BTAC */
- mov r1, #0
- mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
- mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
- dsb
- isb
-
- /* the cpu was running with coherency disabled,
- * caches may be out of date */
- bl v7_flush_kern_cache_louis
-
- ldmfd sp!, {r4 - r11, pc}
-ENDPROC(tegra20_sleep_cpu_secondary_finish)
-
-/*
* tegra20_tear_down_cpu
*
* Switches the CPU cluster to PLL-P and enters sleep.
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 6922dd8..2667bcd 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -59,6 +59,9 @@
#define CLK_RESET_PLLX_MISC3_IDDQ 3
#define CLK_RESET_PLLM_MISC_IDDQ 5
#define CLK_RESET_PLLC_MISC_IDDQ 26
+#define CLK_RESET_PLLP_RESHIFT 0x528
+#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
+#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3
#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
@@ -262,11 +265,11 @@
ENDPROC(tegra30_sleep_core_finish)
/*
- * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
+ * tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg)
*
* Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
*/
-ENTRY(tegra30_sleep_cpu_secondary_finish)
+ENTRY(tegra30_pm_secondary_cpu_suspend)
mov r7, lr
/* Flush and disable the L1 data cache */
@@ -278,7 +281,7 @@
bl tegra30_cpu_shutdown
mov r0, #1 @ never return here
ret r7
-ENDPROC(tegra30_sleep_cpu_secondary_finish)
+ENDPROC(tegra30_pm_secondary_cpu_suspend)
/*
* tegra30_tear_down_cpu
@@ -358,7 +361,6 @@
pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
- pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
_pll_m_c_x_done:
pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
@@ -368,14 +370,24 @@
pll_locked r1, r0, CLK_RESET_PLLP_BASE
pll_locked r1, r0, CLK_RESET_PLLA_BASE
pll_locked r1, r0, CLK_RESET_PLLC_BASE
- pll_locked r1, r0, CLK_RESET_PLLX_BASE
+ /*
+ * CPUFreq driver could select other PLL for CPU. PLLX will be
+ * enabled by the Tegra30 CLK driver on an as-needed basis, see
+ * tegra30_cpu_clock_resume().
+ */
tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
cmp r1, #TEGRA30
beq 1f
+
+ pll_locked r1, r0, CLK_RESET_PLLX_BASE
+
ldr r1, [r0, #CLK_RESET_PLLP_BASE]
bic r1, r1, #(1<<31) @ disable PllP bypass
str r1, [r0, #CLK_RESET_PLLP_BASE]
+
+ mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
+ str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
1:
mov32 r7, TEGRA_TMRUS_BASE
@@ -391,11 +403,8 @@
ldr r4, [r5, #0x1C] @ restore SCLK_BURST
str r4, [r0, #CLK_RESET_SCLK_BURST]
- cmp r10, #TEGRA30
- movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
- movteq r4, #:upper16:((1 << 28) | (0x8))
- movwne r4, #:lower16:((1 << 28) | (0xe))
- movtne r4, #:upper16:((1 << 28) | (0xe))
+ movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP
+ movt r4, #:upper16:((1 << 28) | (0x4))
str r4, [r0, #CLK_RESET_CCLK_BURST]
/* Restore pad power state to normal */
@@ -644,6 +653,10 @@
orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLP_BASE]
+ beq 1f
+ mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
+ str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
+1:
ldr r0, [r5, #CLK_RESET_PLLA_BASE]
bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLA_BASE]
@@ -659,8 +672,12 @@
pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
_no_pll_in_iddq:
- /* switch to CLKS */
- mov r0, #0 /* brust policy = 32KHz */
+ /*
+ * Switch to clk_s (32KHz); bits 28:31=0
+ * Enable burst on CPU IRQ; bit 24=1
+ * Set IRQ burst clock source to clk_m; bits 10:8=0
+ */
+ mov r0, #(1 << 24)
str r0, [r5, #CLK_RESET_SCLK_BURST]
ret lr
@@ -693,10 +710,12 @@
dsb
ldr r0, [r6, r2] /* memory barrier */
+ cmp r10, #TEGRA30
halted:
isb
dsb
- wfi /* CPU should be power gated here */
+ wfine /* CPU should be power gated here */
+ wfeeq
/* !!!FIXME!!! Implement halt failure handler */
b halted
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 78ef32a..4718a3c 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -114,29 +114,14 @@
.endm
#else
-void tegra_pen_lock(void);
-void tegra_pen_unlock(void);
void tegra_resume(void);
int tegra_sleep_cpu_finish(unsigned long);
void tegra_disable_clean_inv_dcache(u32 flag);
-#ifdef CONFIG_HOTPLUG_CPU
void tegra20_hotplug_shutdown(void);
void tegra30_hotplug_shutdown(void);
-#endif
-void tegra20_cpu_shutdown(int cpu);
-int tegra20_cpu_is_resettable_soon(void);
-void tegra20_cpu_clear_resettable(void);
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void tegra20_cpu_set_resettable_soon(void);
-#else
-static inline void tegra20_cpu_set_resettable_soon(void) {}
-#endif
-
-int tegra20_sleep_cpu_secondary_finish(unsigned long);
void tegra20_tear_down_cpu(void);
-int tegra30_sleep_cpu_secondary_finish(unsigned long);
void tegra30_tear_down_cpu(void);
#endif
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 5ea3421..c011359 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -36,13 +36,12 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
+#include <asm/psci.h>
#include <asm/setup.h>
#include "board.h"
#include "common.h"
-#include "cpuidle.h"
#include "iomap.h"
-#include "irq.h"
#include "pm.h"
#include "reset.h"
#include "sleep.h"
@@ -86,7 +85,6 @@
static void __init tegra_dt_init_late(void)
{
tegra_init_suspend();
- tegra_cpuidle_init();
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
of_machine_is_compatible("compal,paz00"))
@@ -95,6 +93,13 @@
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
of_machine_is_compatible("nvidia,tegra20"))
platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
+
+ if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())
+ platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
+
+ if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) &&
+ of_machine_is_compatible("nvidia,tegra30"))
+ platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
}
static const char * const tegra_dt_board_compat[] = {
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a79fa3b..a1694d9 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -201,7 +201,7 @@
};
/* Pin control settings */
-static struct pinctrl_map __initdata u300_pinmux_map[] = {
+static const struct pinctrl_map u300_pinmux_map[] = {
/* anonymous maps for chip power and EMIFs */
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 3875027..e929aaa 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -84,6 +84,7 @@
struct resource r;
irqchip_init();
+ prcmu_early_init();
np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
of_address_to_resource(np, 0, &r);
of_node_put(np);
@@ -91,7 +92,6 @@
pr_err("could not find PRCMU base resource\n");
return;
}
- prcmu_early_init(r.start, r.end-r.start);
ux500_pm_init(r.start, r.end-r.start);
/* Unlock before init */
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index f5c2754..d88e772 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -6,7 +6,6 @@
select ARM_TIMER_SP804
select ARM_VIC
select CLKSRC_VERSATILE
- select COMMON_CLK_VERSATILE
select CPU_ARM926T
select ICST
select MFD_SYSCON
diff --git a/arch/arm/mach-versatile/versatile_dt.c b/arch/arm/mach-versatile/versatile_dt.c
index c00ea4f..02ba68a 100644
--- a/arch/arm/mach-versatile/versatile_dt.c
+++ b/arch/arm/mach-versatile/versatile_dt.c
@@ -39,8 +39,6 @@
#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
-#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */
-#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000)
/*
* System controller bit assignment
@@ -54,7 +52,6 @@
#define VERSATILE_TIMER4_EnSel 21
static void __iomem *versatile_sys_base;
-static void __iomem *versatile_ib2_ctrl;
unsigned int mmc_status(struct device *dev)
{
@@ -169,8 +166,6 @@
versatile_sys_base = of_iomap(np, 0);
WARN_ON(!versatile_sys_base);
- versatile_ib2_ctrl = ioremap(VERSATILE_IB2_CTL_BASE, SZ_4K);
-
versatile_dt_pci_init();
of_platform_default_populate(NULL, versatile_auxdata_lookup, NULL);
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 726a680..065e129 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -7,7 +7,6 @@
select ARM_GIC
select ARM_GLOBAL_TIMER
select ARM_TIMER_SP804
- select COMMON_CLK_VERSATILE
select GPIOLIB
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
@@ -21,8 +20,6 @@
select REGULATOR if MMC_ARMMMCI
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select VEXPRESS_CONFIG
- select VEXPRESS_SYSCFG
- select MFD_VEXPRESS_SYSREG
help
This option enables support for systems using Cortex processor based
ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f4a7519..bda7867 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,3 +1,4 @@
bool vexpress_smp_init_ops(void);
+void vexpress_flags_set(u32 data);
extern const struct smp_operations vexpress_smp_dt_ops;
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 46a903c..a0554d7 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -20,6 +20,7 @@
#include <asm/cputype.h>
#include <asm/cp15.h>
+#include "core.h"
#define RST_HOLD0 0x0
#define RST_HOLD1 0x4
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 95886b3..ffe7c7a 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -1,8 +1,31 @@
// SPDX-License-Identifier: GPL-2.0
+#include <linux/of.h>
+#include <linux/of_address.h>
#include <asm/mach/arch.h>
#include "core.h"
+#define SYS_FLAGSSET 0x030
+#define SYS_FLAGSCLR 0x034
+
+void vexpress_flags_set(u32 data)
+{
+ static void __iomem *base;
+
+ if (!base) {
+ struct device_node *node = of_find_compatible_node(NULL, NULL,
+ "arm,vexpress-sysreg");
+
+ base = of_iomap(node, 0);
+ }
+
+ if (WARN_ON(!base))
+ return;
+
+ writel(~0, base + SYS_FLAGSCLR);
+ writel(data, base + SYS_FLAGSSET);
+}
+
static const char * const v2m_dt_match[] __initconst = {
"arm,vexpress",
NULL,
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 8841199..d01cdd9 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -2,7 +2,6 @@
config ARCH_VT8500
bool
select GPIOLIB
- select CLKDEV_LOOKUP
select VT8500_TIMER
select PINCTRL
help
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 1ca633e..43fb941 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -10,7 +10,6 @@
select CADENCE_TTC_TIMER
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
- select ICST
select MFD_SYSCON
select PINCTRL
select PINCTRL_ZYNQ
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 3a4248f..e1ca6a5 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -12,10 +12,10 @@
#include <linux/cpumask.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
-#include <linux/clk-provider.h>
#include <linux/clk/zynq.h>
#include <linux/clocksource.h>
#include <linux/of_address.h>
+#include <linux/of_clk.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/of.h>
@@ -24,13 +24,13 @@
#include <linux/irqchip/arm-gic.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
+#include <linux/pgtable.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
#include <asm/page.h>
-#include <asm/pgtable.h>
#include <asm/smp_scu.h>
#include <asm/system_info.h>
#include <asm/hardware/cache-l2x0.h>
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index a10085b..68ec303 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
@@ -30,6 +31,7 @@
{
u32 trampoline_code_size = &zynq_secondary_trampoline_end -
&zynq_secondary_trampoline;
+ u32 phy_cpuid = cpu_logical_map(cpu);
/* MS: Expectation that SLCR are directly map and accessible */
/* Not possible to jump to non aligned address */
@@ -39,7 +41,7 @@
u32 trampoline_size = &zynq_secondary_trampoline_jump -
&zynq_secondary_trampoline;
- zynq_slcr_cpu_stop(cpu);
+ zynq_slcr_cpu_stop(phy_cpuid);
if (address) {
if (__pa(PAGE_OFFSET)) {
zero = ioremap(0, trampoline_code_size);
@@ -68,7 +70,7 @@
if (__pa(PAGE_OFFSET))
iounmap(zero);
}
- zynq_slcr_cpu_start(cpu);
+ zynq_slcr_cpu_start(phy_cpuid);
return 0;
}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 0ab3a86..c6bf34a 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -743,6 +743,7 @@
config CPU_BIG_ENDIAN
bool "Build big-endian kernel"
depends on ARCH_SUPPORTS_BIG_ENDIAN
+ depends on !LD_IS_LLD
help
Say Y if you plan on running a kernel in big-endian mode.
Note that your board must be properly built and your board
@@ -752,7 +753,7 @@
config CPU_ENDIAN_BE8
bool
depends on CPU_BIG_ENDIAN
- default CPU_V6 || CPU_V6K || CPU_V7
+ default CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
help
Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
@@ -832,6 +833,7 @@
config CPU_SPECTRE
bool
+ select GENERIC_CPU_VULNERABILITIES
config HARDEN_BRANCH_PREDICTOR
bool "Harden the branch predictor against aliasing attacks" if EXPERT
@@ -852,6 +854,16 @@
If unsure, say Y.
+config HARDEN_BRANCH_HISTORY
+ bool "Harden Spectre style attacks against branch history" if EXPERT
+ depends on CPU_SPECTRE
+ default y
+ help
+ Speculation attacks against some high-performance processors can
+ make use of branch history to influence future speculation. When
+ taking an exception, a sequence of branches overwrites the branch
+ history, or branch history is invalidated.
+
config TLS_REG_EMUL
bool
select NEED_KUSER_HELPERS
@@ -896,7 +908,10 @@
bool "Enable VDSO for acceleration of some system calls"
depends on AEABI && MMU && CPU_V7
default y if ARM_ARCH_TIMER
+ select HAVE_GENERIC_VDSO
select GENERIC_TIME_VSYSCALL
+ select GENERIC_VDSO_32
+ select GENERIC_GETTIMEOFDAY
help
Place in the process address space an ELF shared object
providing fast implementations of gettimeofday and
@@ -1041,7 +1056,7 @@
config CACHE_TAUROS2
bool "Enable the Tauros2 L2 cache controller"
- depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
+ depends on (CPU_MOHAWK || CPU_PJ4)
default y
select OUTER_CACHE
help
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 788c5cf..ea81e89 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -162,12 +162,12 @@
return count;
}
-static const struct file_operations alignment_proc_fops = {
- .open = alignment_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
- .write = alignment_proc_write,
+static const struct proc_ops alignment_proc_ops = {
+ .proc_open = alignment_proc_open,
+ .proc_read = seq_read,
+ .proc_lseek = seq_lseek,
+ .proc_release = single_release,
+ .proc_write = alignment_proc_write,
};
#endif /* CONFIG_PROC_FS */
@@ -694,7 +694,7 @@
return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
(tinstr & 255); /* register_list */
}
- /* Else, fall through - for illegal instruction case */
+ fallthrough; /* for illegal instruction case */
default:
return BAD_INSTR;
@@ -750,7 +750,7 @@
case 0xe8e0:
case 0xe9e0:
poffset->un = (tinst2 & 0xff) << 2;
- /* Fall through */
+ fallthrough;
case 0xe940:
case 0xe9c0:
@@ -774,7 +774,7 @@
if (user_mode(regs))
fault = get_user(instr, ip);
else
- fault = probe_kernel_address(ip, instr);
+ fault = get_kernel_nofault(instr, ip);
*inst = __mem_to_opcode_arm(instr);
@@ -789,7 +789,7 @@
if (user_mode(regs))
fault = get_user(instr, ip);
else
- fault = probe_kernel_address(ip, instr);
+ fault = get_kernel_nofault(instr, ip);
*inst = __mem_to_opcode_thumb16(instr);
@@ -799,7 +799,7 @@
static int
do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
- union offset_union uninitialized_var(offset);
+ union offset_union offset;
unsigned long instrptr;
int (*handler)(unsigned long addr, u32 instr, struct pt_regs *regs);
unsigned int type;
@@ -1016,7 +1016,7 @@
struct proc_dir_entry *res;
res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
- &alignment_proc_fops);
+ &alignment_proc_ops);
if (!res)
return -ENOMEM;
#endif
diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c
index 3471fc6..bdc0703 100644
--- a/arch/arm/mm/cache-b15-rac.c
+++ b/arch/arm/mm/cache-b15-rac.c
@@ -358,8 +358,7 @@
set_bit(RAC_ENABLED, &b15_rac_flags);
spin_unlock(&rac_lock);
- pr_info("Broadcom Brahma-B15 readahead cache at: 0x%p\n",
- b15_rac_base + RAC_CONFIG0_REG);
+ pr_info("%pOF: Broadcom Brahma-B15 readahead cache\n", dn);
goto out;
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 0ee8fc4..dc8f152 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -135,13 +135,13 @@
and r1, r1, #7 @ mask of the bits for current cache only
cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache
-#ifdef CONFIG_PREEMPT
+#ifdef CONFIG_PREEMPTION
save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
#endif
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr
mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
-#ifdef CONFIG_PREEMPT
+#ifdef CONFIG_PREEMPTION
restore_irqs_notrace r9
#endif
and r2, r1, #7 @ extract the length of the cache lines
diff --git a/arch/arm/mm/cache-v7m.S b/arch/arm/mm/cache-v7m.S
index a0035c4..1bc3a0a 100644
--- a/arch/arm/mm/cache-v7m.S
+++ b/arch/arm/mm/cache-v7m.S
@@ -183,13 +183,13 @@
and r1, r1, #7 @ mask of the bits for current cache only
cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache
-#ifdef CONFIG_PREEMPT
+#ifdef CONFIG_PREEMPTION
save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
#endif
write_csselr r10, r1 @ set current cache level
isb @ isb to sych the new cssr&csidr
read_ccsidr r1 @ read the new csidr
-#ifdef CONFIG_PREEMPT
+#ifdef CONFIG_PREEMPTION
restore_irqs_notrace r9
#endif
and r2, r1, #7 @ extract the length of the cache lines
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index a94bd08..44f7292 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -14,7 +14,6 @@
#include <linux/mm.h>
#include <linux/highmem.h>
-#include <asm/pgtable.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index a6488bb..6a769a6 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -9,7 +9,6 @@
#include <linux/mm.h>
#include <linux/highmem.h>
-#include <asm/pgtable.h>
#include <asm/shmparam.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 382e1c2..eb5d338 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -14,7 +14,6 @@
#include <linux/mm.h>
#include <linux/highmem.h>
-#include <asm/pgtable.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c
index 287ef89..6bfd2b8 100644
--- a/arch/arm/mm/dma-mapping-nommu.c
+++ b/arch/arm/mm/dma-mapping-nommu.c
@@ -8,6 +8,7 @@
#include <linux/export.h>
#include <linux/mm.h>
#include <linux/dma-direct.h>
+#include <linux/dma-map-ops.h>
#include <linux/scatterlist.h>
#include <asm/cachetype.h>
@@ -176,6 +177,8 @@
const struct dma_map_ops arm_nommu_dma_ops = {
.alloc = arm_nommu_dma_alloc,
.free = arm_nommu_dma_free,
+ .alloc_pages = dma_direct_alloc_pages,
+ .free_pages = dma_direct_free_pages,
.mmap = arm_nommu_dma_mmap,
.map_page = arm_nommu_dma_map_page,
.unmap_page = arm_nommu_dma_unmap_page,
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 27576c7..c4b8df2 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -15,9 +15,7 @@
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-direct.h>
-#include <linux/dma-mapping.h>
-#include <linux/dma-noncoherent.h>
-#include <linux/dma-contiguous.h>
+#include <linux/dma-map-ops.h>
#include <linux/highmem.h>
#include <linux/memblock.h>
#include <linux/slab.h>
@@ -35,7 +33,6 @@
#include <asm/dma-iommu.h>
#include <asm/mach/map.h>
#include <asm/system_info.h>
-#include <asm/dma-contiguous.h>
#include <xen/swiotlb-xen.h>
#include "dma.h"
@@ -179,9 +176,28 @@
__dma_page_cpu_to_dev(page, offset, size, dir);
}
+/*
+ * Return whether the given device DMA address mask can be supported
+ * properly. For example, if your device can only drive the low 24-bits
+ * during bus mastering, then you would pass 0x00ffffff as the mask
+ * to this function.
+ */
+static int arm_dma_supported(struct device *dev, u64 mask)
+{
+ unsigned long max_dma_pfn = min(max_pfn - 1, arm_dma_pfn_limit);
+
+ /*
+ * Translate the device's DMA mask to a PFN limit. This
+ * PFN number includes the page which we can DMA to.
+ */
+ return dma_to_pfn(dev, mask) >= max_dma_pfn;
+}
+
const struct dma_map_ops arm_dma_ops = {
.alloc = arm_dma_alloc,
.free = arm_dma_free,
+ .alloc_pages = dma_direct_alloc_pages,
+ .free_pages = dma_direct_free_pages,
.mmap = arm_dma_mmap,
.get_sgtable = arm_dma_get_sgtable,
.map_page = arm_dma_map_page,
@@ -209,6 +225,8 @@
const struct dma_map_ops arm_coherent_dma_ops = {
.alloc = arm_coherent_dma_alloc,
.free = arm_coherent_dma_free,
+ .alloc_pages = dma_direct_alloc_pages,
+ .free_pages = dma_direct_free_pages,
.mmap = arm_coherent_dma_mmap,
.get_sgtable = arm_dma_get_sgtable,
.map_page = arm_coherent_dma_map_page,
@@ -219,49 +237,6 @@
};
EXPORT_SYMBOL(arm_coherent_dma_ops);
-static int __dma_supported(struct device *dev, u64 mask, bool warn)
-{
- unsigned long max_dma_pfn = min(max_pfn - 1, arm_dma_pfn_limit);
-
- /*
- * Translate the device's DMA mask to a PFN limit. This
- * PFN number includes the page which we can DMA to.
- */
- if (dma_to_pfn(dev, mask) < max_dma_pfn) {
- if (warn)
- dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
- mask,
- dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
- max_dma_pfn + 1);
- return 0;
- }
-
- return 1;
-}
-
-static u64 get_coherent_dma_mask(struct device *dev)
-{
- u64 mask = (u64)DMA_BIT_MASK(32);
-
- if (dev) {
- mask = dev->coherent_dma_mask;
-
- /*
- * Sanity check the DMA mask - it must be non-zero, and
- * must be able to be satisfied by a DMA allocation.
- */
- if (mask == 0) {
- dev_warn(dev, "coherent DMA mask is unset\n");
- return 0;
- }
-
- if (!__dma_supported(dev, mask, true))
- return 0;
- }
-
- return mask;
-}
-
static void __dma_clear_buffer(struct page *page, size_t size, int coherent_flag)
{
/*
@@ -529,7 +504,7 @@
static bool __in_atomic_pool(void *start, size_t size)
{
- return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
+ return gen_pool_has_addr(atomic_pool, (unsigned long)start, size);
}
static int __free_from_pool(void *start, size_t size)
@@ -688,7 +663,7 @@
gfp_t gfp, pgprot_t prot, bool is_coherent,
unsigned long attrs, const void *caller)
{
- u64 mask = get_coherent_dma_mask(dev);
+ u64 mask = min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
struct page *page = NULL;
void *addr;
bool allowblock, cma;
@@ -712,9 +687,6 @@
}
#endif
- if (!mask)
- return NULL;
-
buf = kzalloc(sizeof(*buf),
gfp & ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM));
if (!buf)
@@ -1087,17 +1059,6 @@
dir);
}
-/*
- * Return whether the given device DMA address mask can be supported
- * properly. For example, if your device can only drive the low 24-bits
- * during bus mastering, then you would pass 0x00ffffff as the mask
- * to this function.
- */
-int arm_dma_supported(struct device *dev, u64 mask)
-{
- return __dma_supported(dev, mask, false);
-}
-
static const struct dma_map_ops *arm_get_dma_map_ops(bool coherent)
{
/*
@@ -1559,7 +1520,7 @@
* free a page as defined by the above mapping.
* Must not be called with IRQs disabled.
*/
-void __arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
+static void __arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
dma_addr_t handle, unsigned long attrs, int coherent_flag)
{
struct page **pages;
@@ -1583,13 +1544,14 @@
__iommu_free_buffer(dev, pages, size, attrs);
}
-void arm_iommu_free_attrs(struct device *dev, size_t size,
- void *cpu_addr, dma_addr_t handle, unsigned long attrs)
+static void arm_iommu_free_attrs(struct device *dev, size_t size,
+ void *cpu_addr, dma_addr_t handle,
+ unsigned long attrs)
{
__arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, NORMAL);
}
-void arm_coherent_iommu_free_attrs(struct device *dev, size_t size,
+static void arm_coherent_iommu_free_attrs(struct device *dev, size_t size,
void *cpu_addr, dma_addr_t handle, unsigned long attrs)
{
__arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, COHERENT);
@@ -1713,7 +1675,7 @@
* possible) and tagged with the appropriate dma address and length. They are
* obtained via sg_dma_{address,length}.
*/
-int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
+static int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction dir, unsigned long attrs)
{
return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
@@ -1731,7 +1693,7 @@
* tagged with the appropriate dma address and length. They are obtained via
* sg_dma_{address,length}.
*/
-int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
+static int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction dir, unsigned long attrs)
{
return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
@@ -1764,8 +1726,8 @@
* Unmap a set of streaming mode DMA translations. Again, CPU access
* rules concerning calls here are the same as for dma_unmap_single().
*/
-void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
- int nents, enum dma_data_direction dir,
+static void arm_coherent_iommu_unmap_sg(struct device *dev,
+ struct scatterlist *sg, int nents, enum dma_data_direction dir,
unsigned long attrs)
{
__iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
@@ -1781,9 +1743,10 @@
* Unmap a set of streaming mode DMA translations. Again, CPU access
* rules concerning calls here are the same as for dma_unmap_single().
*/
-void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
- enum dma_data_direction dir,
- unsigned long attrs)
+static void arm_iommu_unmap_sg(struct device *dev,
+ struct scatterlist *sg, int nents,
+ enum dma_data_direction dir,
+ unsigned long attrs)
{
__iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
}
@@ -1795,7 +1758,8 @@
* @nents: number of buffers to map (returned from dma_map_sg)
* @dir: DMA transfer direction (same as was passed to dma_map_sg)
*/
-void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+static void arm_iommu_sync_sg_for_cpu(struct device *dev,
+ struct scatterlist *sg,
int nents, enum dma_data_direction dir)
{
struct scatterlist *s;
@@ -1813,7 +1777,8 @@
* @nents: number of buffers to map (returned from dma_map_sg)
* @dir: DMA transfer direction (same as was passed to dma_map_sg)
*/
-void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+static void arm_iommu_sync_sg_for_device(struct device *dev,
+ struct scatterlist *sg,
int nents, enum dma_data_direction dir)
{
struct scatterlist *s;
@@ -2015,7 +1980,7 @@
__dma_page_cpu_to_dev(page, offset, size, dir);
}
-const struct dma_map_ops iommu_ops = {
+static const struct dma_map_ops iommu_ops = {
.alloc = arm_iommu_alloc_attrs,
.free = arm_iommu_free_attrs,
.mmap = arm_iommu_mmap_attrs,
@@ -2037,7 +2002,7 @@
.dma_supported = arm_dma_supported,
};
-const struct dma_map_ops iommu_coherent_ops = {
+static const struct dma_map_ops iommu_coherent_ops = {
.alloc = arm_coherent_iommu_alloc_attrs,
.free = arm_coherent_iommu_free_attrs,
.mmap = arm_coherent_iommu_mmap_attrs,
@@ -2332,26 +2297,20 @@
}
#ifdef CONFIG_SWIOTLB
-void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
- size_t size, enum dma_data_direction dir)
+void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
+ enum dma_data_direction dir)
{
__dma_page_cpu_to_dev(phys_to_page(paddr), paddr & (PAGE_SIZE - 1),
size, dir);
}
-void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
- size_t size, enum dma_data_direction dir)
+void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
+ enum dma_data_direction dir)
{
__dma_page_dev_to_cpu(phys_to_page(paddr), paddr & (PAGE_SIZE - 1),
size, dir);
}
-long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr,
- dma_addr_t dma_addr)
-{
- return dma_to_pfn(dev, dma_addr);
-}
-
void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
gfp_t gfp, unsigned long attrs)
{
diff --git a/arch/arm/mm/dump.c b/arch/arm/mm/dump.c
index 7d6291f..c18d23a 100644
--- a/arch/arm/mm/dump.c
+++ b/arch/arm/mm/dump.c
@@ -16,7 +16,6 @@
#include <asm/domain.h>
#include <asm/fixmap.h>
#include <asm/memory.h>
-#include <asm/pgtable.h>
#include <asm/ptdump.h>
static struct addr_marker address_markers[] = {
@@ -207,6 +206,7 @@
static struct pg_level pg_level[] = {
{
}, { /* pgd */
+ }, { /* p4d */
}, { /* pud */
}, { /* pmd */
.bits = section_bits,
@@ -308,7 +308,7 @@
for (i = 0; i < PTRS_PER_PTE; i++, pte++) {
addr = start + i * PAGE_SIZE;
- note_page(st, addr, 4, pte_val(*pte), domain);
+ note_page(st, addr, 5, pte_val(*pte), domain);
}
}
@@ -350,14 +350,14 @@
addr += SECTION_SIZE;
pmd++;
domain = get_domain_name(pmd);
- note_page(st, addr, 3, pmd_val(*pmd), domain);
+ note_page(st, addr, 4, pmd_val(*pmd), domain);
}
}
}
-static void walk_pud(struct pg_state *st, pgd_t *pgd, unsigned long start)
+static void walk_pud(struct pg_state *st, p4d_t *p4d, unsigned long start)
{
- pud_t *pud = pud_offset(pgd, 0);
+ pud_t *pud = pud_offset(p4d, 0);
unsigned long addr;
unsigned i;
@@ -366,7 +366,23 @@
if (!pud_none(*pud)) {
walk_pmd(st, pud, addr);
} else {
- note_page(st, addr, 2, pud_val(*pud), NULL);
+ note_page(st, addr, 3, pud_val(*pud), NULL);
+ }
+ }
+}
+
+static void walk_p4d(struct pg_state *st, pgd_t *pgd, unsigned long start)
+{
+ p4d_t *p4d = p4d_offset(pgd, 0);
+ unsigned long addr;
+ unsigned i;
+
+ for (i = 0; i < PTRS_PER_P4D; i++, p4d++) {
+ addr = start + i * P4D_SIZE;
+ if (!p4d_none(*p4d)) {
+ walk_pud(st, p4d, addr);
+ } else {
+ note_page(st, addr, 2, p4d_val(*p4d), NULL);
}
}
}
@@ -381,7 +397,7 @@
for (i = 0; i < PTRS_PER_PGD; i++, pgd++) {
addr = start + i * PGDIR_SIZE;
if (!pgd_none(*pgd)) {
- walk_pud(st, pgd, addr);
+ walk_p4d(st, pgd, addr);
} else {
note_page(st, addr, 1, pgd_val(*pgd), NULL);
}
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index ae857f4..0e49154 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -17,7 +17,6 @@
#include <asm/bugs.h>
#include <asm/cacheflush.h>
#include <asm/cachetype.h>
-#include <asm/pgtable.h>
#include <asm/tlbflush.h>
#include "mm.h"
@@ -91,6 +90,7 @@
{
spinlock_t *ptl;
pgd_t *pgd;
+ p4d_t *p4d;
pud_t *pud;
pmd_t *pmd;
pte_t *pte;
@@ -100,7 +100,11 @@
if (pgd_none_or_clear_bad(pgd))
return 0;
- pud = pud_offset(pgd, address);
+ p4d = p4d_offset(pgd, address);
+ if (p4d_none_or_clear_bad(p4d))
+ return 0;
+
+ pud = pud_offset(p4d, address);
if (pud_none_or_clear_bad(pud))
return 0;
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index bd0f482..efa4020 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -18,7 +18,6 @@
#include <linux/highmem.h>
#include <linux/perf_event.h>
-#include <asm/pgtable.h>
#include <asm/system_misc.h>
#include <asm/system_info.h>
#include <asm/tlbflush.h>
@@ -43,19 +42,21 @@
printk("%s[%08lx] *pgd=%08llx", lvl, addr, (long long)pgd_val(*pgd));
do {
+ p4d_t *p4d;
pud_t *pud;
pmd_t *pmd;
pte_t *pte;
- if (pgd_none(*pgd))
+ p4d = p4d_offset(pgd, addr);
+ if (p4d_none(*p4d))
break;
- if (pgd_bad(*pgd)) {
+ if (p4d_bad(*p4d)) {
pr_cont("(bad)");
break;
}
- pud = pud_offset(pgd, addr);
+ pud = pud_offset(p4d, addr);
if (PTRS_PER_PUD != 1)
pr_cont(", *pud=%08llx", (long long)pud_val(*pud));
@@ -189,7 +190,7 @@
*/
static inline bool access_error(unsigned int fsr, struct vm_area_struct *vma)
{
- unsigned int mask = VM_READ | VM_WRITE | VM_EXEC;
+ unsigned int mask = VM_ACCESS_FLAGS;
if ((fsr & FSR_WRITE) && !(fsr & FSR_CM))
mask = VM_WRITE;
@@ -201,7 +202,8 @@
static vm_fault_t __kprobes
__do_page_fault(struct mm_struct *mm, unsigned long addr, unsigned int fsr,
- unsigned int flags, struct task_struct *tsk)
+ unsigned int flags, struct task_struct *tsk,
+ struct pt_regs *regs)
{
struct vm_area_struct *vma;
vm_fault_t fault;
@@ -223,7 +225,7 @@
goto out;
}
- return handle_mm_fault(vma, addr & PAGE_MASK, flags);
+ return handle_mm_fault(vma, addr & PAGE_MASK, flags, regs);
check_stack:
/* Don't allow expansion below FIRST_USER_ADDRESS */
@@ -241,7 +243,7 @@
struct mm_struct *mm;
int sig, code;
vm_fault_t fault;
- unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
+ unsigned int flags = FAULT_FLAG_DEFAULT;
if (kprobe_page_fault(regs, fsr))
return 0;
@@ -265,16 +267,18 @@
if ((fsr & FSR_WRITE) && !(fsr & FSR_CM))
flags |= FAULT_FLAG_WRITE;
+ perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
+
/*
* As per x86, we may deadlock here. However, since the kernel only
* validly references user space from well defined areas of the code,
* we can bug out early if this is from code which shouldn't.
*/
- if (!down_read_trylock(&mm->mmap_sem)) {
+ if (!mmap_read_trylock(mm)) {
if (!user_mode(regs) && !search_exception_tables(regs->ARM_pc))
goto no_context;
retry:
- down_read(&mm->mmap_sem);
+ mmap_read_lock(mm);
} else {
/*
* The above down_read_trylock() might have succeeded in
@@ -289,45 +293,26 @@
#endif
}
- fault = __do_page_fault(mm, addr, fsr, flags, tsk);
+ fault = __do_page_fault(mm, addr, fsr, flags, tsk, regs);
/* If we need to retry but a fatal signal is pending, handle the
- * signal first. We do not need to release the mmap_sem because
+ * signal first. We do not need to release the mmap_lock because
* it would already be released in __lock_page_or_retry in
* mm/filemap.c. */
- if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) {
+ if (fault_signal_pending(fault, regs)) {
if (!user_mode(regs))
goto no_context;
return 0;
}
- /*
- * Major/minor page fault accounting is only done on the
- * initial attempt. If we go through a retry, it is extremely
- * likely that the page will be found in page cache at that point.
- */
-
- perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
if (!(fault & VM_FAULT_ERROR) && flags & FAULT_FLAG_ALLOW_RETRY) {
- if (fault & VM_FAULT_MAJOR) {
- tsk->maj_flt++;
- perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
- regs, addr);
- } else {
- tsk->min_flt++;
- perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
- regs, addr);
- }
if (fault & VM_FAULT_RETRY) {
- /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk
- * of starvation. */
- flags &= ~FAULT_FLAG_ALLOW_RETRY;
flags |= FAULT_FLAG_TRIED;
goto retry;
}
}
- up_read(&mm->mmap_sem);
+ mmap_read_unlock(mm);
/*
* Handle the "normal" case first - VM_FAULT_MAJOR
@@ -408,6 +393,7 @@
{
unsigned int index;
pgd_t *pgd, *pgd_k;
+ p4d_t *p4d, *p4d_k;
pud_t *pud, *pud_k;
pmd_t *pmd, *pmd_k;
@@ -422,13 +408,16 @@
pgd = cpu_get_pgd() + index;
pgd_k = init_mm.pgd + index;
- if (pgd_none(*pgd_k))
- goto bad_area;
- if (!pgd_present(*pgd))
- set_pgd(pgd, *pgd_k);
+ p4d = p4d_offset(pgd, addr);
+ p4d_k = p4d_offset(pgd_k, addr);
- pud = pud_offset(pgd, addr);
- pud_k = pud_offset(pgd_k, addr);
+ if (p4d_none(*p4d_k))
+ goto bad_area;
+ if (!p4d_present(*p4d))
+ set_p4d(p4d, *p4d_k);
+
+ pud = pud_offset(p4d, addr);
+ pud_k = pud_offset(p4d_k, addr);
if (pud_none(*pud_k))
goto bad_area;
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index a76f8ac..187fab2 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -18,7 +18,7 @@
static inline void set_fixmap_pte(int idx, pte_t pte)
{
unsigned long vaddr = __fix_to_virt(idx);
- pte_t *ptep = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
+ pte_t *ptep = virt_to_kpte(vaddr);
set_pte_ext(ptep, pte, 0);
local_flush_tlb_kernel_page(vaddr);
@@ -26,41 +26,18 @@
static inline pte_t get_fixmap_pte(unsigned long vaddr)
{
- pte_t *ptep = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
+ pte_t *ptep = virt_to_kpte(vaddr);
return *ptep;
}
-void *kmap(struct page *page)
-{
- might_sleep();
- if (!PageHighMem(page))
- return page_address(page);
- return kmap_high(page);
-}
-EXPORT_SYMBOL(kmap);
-
-void kunmap(struct page *page)
-{
- BUG_ON(in_interrupt());
- if (!PageHighMem(page))
- return;
- kunmap_high(page);
-}
-EXPORT_SYMBOL(kunmap);
-
-void *kmap_atomic(struct page *page)
+void *kmap_atomic_high_prot(struct page *page, pgprot_t prot)
{
unsigned int idx;
unsigned long vaddr;
void *kmap;
int type;
- preempt_disable();
- pagefault_disable();
- if (!PageHighMem(page))
- return page_address(page);
-
#ifdef CONFIG_DEBUG_HIGHMEM
/*
* There is no cache coherency issue when non VIVT, so force the
@@ -90,13 +67,13 @@
* in place, so the contained TLB flush ensures the TLB is updated
* with the new mapping.
*/
- set_fixmap_pte(idx, mk_pte(page, kmap_prot));
+ set_fixmap_pte(idx, mk_pte(page, prot));
return (void *)vaddr;
}
-EXPORT_SYMBOL(kmap_atomic);
+EXPORT_SYMBOL(kmap_atomic_high_prot);
-void __kunmap_atomic(void *kvaddr)
+void kunmap_atomic_high(void *kvaddr)
{
unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
int idx, type;
@@ -118,10 +95,8 @@
/* this address was obtained through kmap_high_get() */
kunmap_high(pte_page(pkmap_page_table[PKMAP_NR(vaddr)]));
}
- pagefault_enable();
- preempt_enable();
}
-EXPORT_SYMBOL(__kunmap_atomic);
+EXPORT_SYMBOL(kunmap_atomic_high);
void *kmap_atomic_pfn(unsigned long pfn)
{
diff --git a/arch/arm/mm/hugetlbpage.c b/arch/arm/mm/hugetlbpage.c
index a1e5aac..dd7a027 100644
--- a/arch/arm/mm/hugetlbpage.c
+++ b/arch/arm/mm/hugetlbpage.c
@@ -17,7 +17,6 @@
#include <asm/mman.h>
#include <asm/tlb.h>
#include <asm/tlbflush.h>
-#include <asm/pgalloc.h>
/*
* On ARM, huge pages are backed by pmd's rather than pte's, so we do a lot
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index a033f61..448e57c 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -3,12 +3,12 @@
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/mm_types.h>
+#include <linux/pgtable.h>
#include <asm/cputype.h>
#include <asm/idmap.h>
#include <asm/hwcap.h>
#include <asm/pgalloc.h>
-#include <asm/pgtable.h>
#include <asm/sections.h>
#include <asm/system_info.h>
@@ -68,7 +68,8 @@
static void idmap_add_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
unsigned long prot)
{
- pud_t *pud = pud_offset(pgd, addr);
+ p4d_t *p4d = p4d_offset(pgd, addr);
+ pud_t *pud = pud_offset(p4d, addr);
unsigned long next;
do {
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 0804a6a..15af4dd 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -18,7 +18,7 @@
#include <linux/highmem.h>
#include <linux/gfp.h>
#include <linux/memblock.h>
-#include <linux/dma-contiguous.h>
+#include <linux/dma-map-ops.h>
#include <linux/sizes.h>
#include <linux/stop_machine.h>
#include <linux/swiotlb.h>
@@ -30,6 +30,7 @@
#include <asm/prom.h>
#include <asm/sections.h>
#include <asm/setup.h>
+#include <asm/set_memory.h>
#include <asm/system_info.h>
#include <asm/tlb.h>
#include <asm/fixmap.h>
@@ -91,18 +92,6 @@
*/
phys_addr_t arm_dma_limit;
unsigned long arm_dma_pfn_limit;
-
-static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole,
- unsigned long dma_size)
-{
- if (size[0] <= dma_size)
- return;
-
- size[ZONE_NORMAL] = size[0] - dma_size;
- size[ZONE_DMA] = dma_size;
- hole[ZONE_NORMAL] = hole[0];
- hole[ZONE_DMA] = 0;
-}
#endif
void __init setup_dma_zone(const struct machine_desc *mdesc)
@@ -120,67 +109,38 @@
static void __init zone_sizes_init(unsigned long min, unsigned long max_low,
unsigned long max_high)
{
- unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
- struct memblock_region *reg;
-
- /*
- * initialise the zones.
- */
- memset(zone_size, 0, sizeof(zone_size));
-
- /*
- * The memory size has already been determined. If we need
- * to do anything fancy with the allocation of this memory
- * to the zones, now is the time to do it.
- */
- zone_size[0] = max_low - min;
-#ifdef CONFIG_HIGHMEM
- zone_size[ZONE_HIGHMEM] = max_high - max_low;
-#endif
-
- /*
- * Calculate the size of the holes.
- * holes = node_size - sum(bank_sizes)
- */
- memcpy(zhole_size, zone_size, sizeof(zhole_size));
- for_each_memblock(memory, reg) {
- unsigned long start = memblock_region_memory_base_pfn(reg);
- unsigned long end = memblock_region_memory_end_pfn(reg);
-
- if (start < max_low) {
- unsigned long low_end = min(end, max_low);
- zhole_size[0] -= low_end - start;
- }
-#ifdef CONFIG_HIGHMEM
- if (end > max_low) {
- unsigned long high_start = max(start, max_low);
- zhole_size[ZONE_HIGHMEM] -= end - high_start;
- }
-#endif
- }
+ unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 };
#ifdef CONFIG_ZONE_DMA
- /*
- * Adjust the sizes according to any special requirements for
- * this machine type.
- */
- if (arm_dma_zone_size)
- arm_adjust_dma_zone(zone_size, zhole_size,
- arm_dma_zone_size >> PAGE_SHIFT);
+ max_zone_pfn[ZONE_DMA] = min(arm_dma_pfn_limit, max_low);
#endif
-
- free_area_init_node(0, zone_size, min, zhole_size);
+ max_zone_pfn[ZONE_NORMAL] = max_low;
+#ifdef CONFIG_HIGHMEM
+ max_zone_pfn[ZONE_HIGHMEM] = max_high;
+#endif
+ free_area_init(max_zone_pfn);
}
#ifdef CONFIG_HAVE_ARCH_PFN_VALID
int pfn_valid(unsigned long pfn)
{
phys_addr_t addr = __pfn_to_phys(pfn);
+ unsigned long pageblock_size = PAGE_SIZE * pageblock_nr_pages;
if (__phys_to_pfn(addr) != pfn)
return 0;
- return memblock_is_map_memory(__pfn_to_phys(pfn));
+ /*
+ * If address less than pageblock_size bytes away from a present
+ * memory chunk there still will be a memory map entry for it
+ * because we round freed memory map to the pageblock boundaries.
+ */
+ if (memblock_overlaps_region(&memblock.memory,
+ ALIGN_DOWN(addr, pageblock_size),
+ pageblock_size))
+ return 1;
+
+ return 0;
}
EXPORT_SYMBOL(pfn_valid);
#endif
@@ -293,18 +253,13 @@
(phys_addr_t)max_low_pfn << PAGE_SHIFT);
/*
- * Sparsemem tries to allocate bootmem in memory_present(),
- * so must be done after the fixed reservations
- */
- memblocks_present();
-
- /*
- * sparse_init() needs the bootmem allocator up and running.
+ * sparse_init() tries to allocate memory from memblock, so must be
+ * done after the fixed reservations
*/
sparse_init();
/*
- * Now free the memory - free_area_init_node needs
+ * Now free the memory - free_area_init needs
* the sparse mem_map arrays initialized by sparse_init()
* for memmap_init_zone(), otherwise all PFNs are invalid.
*/
@@ -354,16 +309,14 @@
*/
static void __init free_unused_memmap(void)
{
- unsigned long start, prev_end = 0;
- struct memblock_region *reg;
+ unsigned long start, end, prev_end = 0;
+ int i;
/*
* This relies on each bank being in address order.
* The banks are sorted previously in bootmem_init().
*/
- for_each_memblock(memory, reg) {
- start = memblock_region_memory_base_pfn(reg);
-
+ for_each_mem_pfn_range(i, MAX_NUMNODES, &start, &end, NULL) {
#ifdef CONFIG_SPARSEMEM
/*
* Take care not to free memmap entries that don't exist
@@ -371,15 +324,15 @@
*/
start = min(start,
ALIGN(prev_end, PAGES_PER_SECTION));
-#else
- /*
- * Align down here since the VM subsystem insists that the
- * memmap entries are valid from the bank start aligned to
- * MAX_ORDER_NR_PAGES.
- */
- start = round_down(start, MAX_ORDER_NR_PAGES);
#endif
/*
+ * Align down here since many operations in VM subsystem
+ * presume that there are no holes in the memory map inside
+ * a pageblock
+ */
+ start = round_down(start, pageblock_nr_pages);
+
+ /*
* If we had a previous bank, and there is a space
* between the current bank and the previous, free it.
*/
@@ -387,76 +340,45 @@
free_memmap(prev_end, start);
/*
- * Align up here since the VM subsystem insists that the
- * memmap entries are valid from the bank end aligned to
- * MAX_ORDER_NR_PAGES.
+ * Align up here since many operations in VM subsystem
+ * presume that there are no holes in the memory map inside
+ * a pageblock
*/
- prev_end = ALIGN(memblock_region_memory_end_pfn(reg),
- MAX_ORDER_NR_PAGES);
+ prev_end = ALIGN(end, pageblock_nr_pages);
}
#ifdef CONFIG_SPARSEMEM
- if (!IS_ALIGNED(prev_end, PAGES_PER_SECTION))
+ if (!IS_ALIGNED(prev_end, PAGES_PER_SECTION)) {
+ prev_end = ALIGN(end, pageblock_nr_pages);
free_memmap(prev_end,
ALIGN(prev_end, PAGES_PER_SECTION));
+ }
#endif
}
-#ifdef CONFIG_HIGHMEM
-static inline void free_area_high(unsigned long pfn, unsigned long end)
-{
- for (; pfn < end; pfn++)
- free_highmem_page(pfn_to_page(pfn));
-}
-#endif
-
static void __init free_highpages(void)
{
#ifdef CONFIG_HIGHMEM
unsigned long max_low = max_low_pfn;
- struct memblock_region *mem, *res;
+ phys_addr_t range_start, range_end;
+ u64 i;
/* set highmem page free */
- for_each_memblock(memory, mem) {
- unsigned long start = memblock_region_memory_base_pfn(mem);
- unsigned long end = memblock_region_memory_end_pfn(mem);
+ for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE,
+ &range_start, &range_end, NULL) {
+ unsigned long start = PFN_UP(range_start);
+ unsigned long end = PFN_DOWN(range_end);
/* Ignore complete lowmem entries */
if (end <= max_low)
continue;
- if (memblock_is_nomap(mem))
- continue;
-
/* Truncate partial highmem entries */
if (start < max_low)
start = max_low;
- /* Find and exclude any reserved regions */
- for_each_memblock(reserved, res) {
- unsigned long res_start, res_end;
-
- res_start = memblock_region_reserved_base_pfn(res);
- res_end = memblock_region_reserved_end_pfn(res);
-
- if (res_end < start)
- continue;
- if (res_start < start)
- res_start = start;
- if (res_start > end)
- res_start = end;
- if (res_end > end)
- res_end = end;
- if (res_start != start)
- free_area_high(start, res_start);
- start = res_end;
- if (start == end)
- break;
- }
-
- /* And now free anything which remains */
- if (start < end)
- free_area_high(start, end);
+ for (; start < end; start++)
+ free_highmem_page(pfn_to_page(start));
}
#endif
}
@@ -469,7 +391,11 @@
void __init mem_init(void)
{
#ifdef CONFIG_ARM_LPAE
- swiotlb_init(1);
+ if (swiotlb_force == SWIOTLB_FORCE ||
+ max_pfn > arm_dma_pfn_limit)
+ swiotlb_init(1);
+ else
+ swiotlb_force = SWIOTLB_NO_FORCE;
#endif
set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
@@ -569,7 +495,7 @@
{
pmd_t *pmd;
- pmd = pmd_offset(pud_offset(pgd_offset(mm, addr), addr), addr);
+ pmd = pmd_offset(pud_offset(p4d_offset(pgd_offset(mm, addr), addr), addr), addr);
#ifdef CONFIG_ARM_LPAE
pmd[0] = __pmd((pmd_val(pmd[0]) & mask) | prot);
@@ -592,8 +518,8 @@
return !!(get_cr() & CR_XP);
}
-void set_section_perms(struct section_perm *perms, int n, bool set,
- struct mm_struct *mm)
+static void set_section_perms(struct section_perm *perms, int n, bool set,
+ struct mm_struct *mm)
{
size_t i;
unsigned long addr;
diff --git a/arch/arm/mm/iomap.c b/arch/arm/mm/iomap.c
index 091ddc5..415d0a4 100644
--- a/arch/arm/mm/iomap.c
+++ b/arch/arm/mm/iomap.c
@@ -10,6 +10,8 @@
#include <linux/ioport.h>
#include <linux/io.h>
+#include <asm/vga.h>
+
unsigned long vga_base;
EXPORT_SYMBOL(vga_base);
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index d42b933..80fb5a4 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -27,6 +27,7 @@
#include <linux/vmalloc.h>
#include <linux/io.h>
#include <linux/sizes.h>
+#include <linux/memblock.h>
#include <asm/cp15.h>
#include <asm/cputype.h>
@@ -141,14 +142,8 @@
static void unmap_area_sections(unsigned long virt, unsigned long size)
{
unsigned long addr = virt, end = virt + (size & ~(SZ_1M - 1));
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmdp;
+ pmd_t *pmdp = pmd_off_k(addr);
- flush_cache_vunmap(addr, end);
- pgd = pgd_offset_k(addr);
- pud = pud_offset(pgd, addr);
- pmdp = pmd_offset(pud, addr);
do {
pmd_t pmd = *pmdp;
@@ -189,9 +184,7 @@
size_t size, const struct mem_type *type)
{
unsigned long addr = virt, end = virt + size;
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
+ pmd_t *pmd = pmd_off_k(addr);
/*
* Remove and free any PTE-based mapping, and
@@ -199,9 +192,6 @@
*/
unmap_area_sections(virt, size);
- pgd = pgd_offset_k(addr);
- pud = pud_offset(pgd, addr);
- pmd = pmd_offset(pud, addr);
do {
pmd[0] = __pmd(__pfn_to_phys(pfn) | type->prot_sect);
pfn += SZ_1M >> PAGE_SHIFT;
@@ -221,19 +211,13 @@
size_t size, const struct mem_type *type)
{
unsigned long addr = virt, end = virt + size;
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
+ pmd_t *pmd = pmd_off_k(addr);
/*
* Remove and free any PTE-based mapping, and
* sync the current kernel mapping.
*/
unmap_area_sections(virt, size);
-
- pgd = pgd_offset_k(virt);
- pud = pud_offset(pgd, addr);
- pmd = pmd_offset(pud, addr);
do {
unsigned long super_pmd_val, i;
@@ -301,7 +285,8 @@
* Don't allow RAM to be mapped with mismatched attributes - this
* causes problems with ARMv6+
*/
- if (WARN_ON(pfn_valid(pfn) && mtype != MT_MEMORY_RW))
+ if (WARN_ON(memblock_is_map_memory(PFN_PHYS(pfn)) &&
+ mtype != MT_MEMORY_RW))
return NULL;
area = get_vm_area_caller(size, VM_IOREMAP, caller);
@@ -382,15 +367,11 @@
EXPORT_SYMBOL(ioremap);
void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
- __alias(ioremap_cached);
-
-void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size)
{
return arch_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
__builtin_return_address(0));
}
EXPORT_SYMBOL(ioremap_cache);
-EXPORT_SYMBOL(ioremap_cached);
void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
{
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 88c121a..9ff6836 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -2,8 +2,7 @@
#ifdef CONFIG_MMU
#include <linux/list.h>
#include <linux/vmalloc.h>
-
-#include <asm/pgtable.h>
+#include <linux/pgtable.h>
/* the upper-most page table pointer */
extern pmd_t *top_pmd;
@@ -36,11 +35,6 @@
return *ptep;
}
-static inline pmd_t *pmd_off_k(unsigned long virt)
-{
- return pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
-}
-
struct mem_type {
pteval_t prot_pte;
pteval_t prot_pte_s2;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index ee943ac..3e30019 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -17,7 +17,6 @@
#include <asm/cp15.h>
#include <asm/cputype.h>
-#include <asm/sections.h>
#include <asm/cachetype.h>
#include <asm/fixmap.h>
#include <asm/sections.h>
@@ -29,6 +28,7 @@
#include <asm/traps.h>
#include <asm/procinfo.h>
#include <asm/memory.h>
+#include <asm/pgalloc.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -65,9 +65,6 @@
static unsigned int ecc_mask __initdata = 0;
pgprot_t pgprot_user;
pgprot_t pgprot_kernel;
-pgprot_t pgprot_hyp_device;
-pgprot_t pgprot_s2;
-pgprot_t pgprot_s2_device;
EXPORT_SYMBOL(pgprot_user);
EXPORT_SYMBOL(pgprot_kernel);
@@ -77,48 +74,34 @@
unsigned int cr_mask;
pmdval_t pmd;
pteval_t pte;
- pteval_t pte_s2;
};
-#ifdef CONFIG_ARM_LPAE
-#define s2_policy(policy) policy
-#else
-#define s2_policy(policy) 0
-#endif
-
-unsigned long kimage_voffset __ro_after_init;
-
static struct cachepolicy cache_policies[] __initdata = {
{
.policy = "uncached",
.cr_mask = CR_W|CR_C,
.pmd = PMD_SECT_UNCACHED,
.pte = L_PTE_MT_UNCACHED,
- .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
}, {
.policy = "buffered",
.cr_mask = CR_C,
.pmd = PMD_SECT_BUFFERED,
.pte = L_PTE_MT_BUFFERABLE,
- .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
}, {
.policy = "writethrough",
.cr_mask = 0,
.pmd = PMD_SECT_WT,
.pte = L_PTE_MT_WRITETHROUGH,
- .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
}, {
.policy = "writeback",
.cr_mask = 0,
.pmd = PMD_SECT_WB,
.pte = L_PTE_MT_WRITEBACK,
- .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
}, {
.policy = "writealloc",
.cr_mask = 0,
.pmd = PMD_SECT_WBWA,
.pte = L_PTE_MT_WRITEALLOC,
- .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
}
};
@@ -229,12 +212,14 @@
static int __init early_cachepolicy(char *p)
{
pr_warn("cachepolicy kernel parameter not supported without cp15\n");
+ return 0;
}
early_param("cachepolicy", early_cachepolicy);
static int __init noalign_setup(char *__unused)
{
pr_warn("noalign kernel parameter not supported without cp15\n");
+ return 1;
}
__setup("noalign", noalign_setup);
@@ -248,9 +233,6 @@
[MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
L_PTE_SHARED,
- .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
- s2_policy(L_PTE_S2_MT_DEV_SHARED) |
- L_PTE_SHARED,
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
.domain = DOMAIN_IO,
@@ -261,7 +243,7 @@
.prot_sect = PROT_SECT_DEVICE,
.domain = DOMAIN_IO,
},
- [MT_DEVICE_CACHED] = { /* ioremap_cached */
+ [MT_DEVICE_CACHED] = { /* ioremap_cache */
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
@@ -376,11 +358,7 @@
static inline pmd_t * __init fixmap_pmd(unsigned long addr)
{
- pgd_t *pgd = pgd_offset_k(addr);
- pud_t *pud = pud_offset(pgd, addr);
- pmd_t *pmd = pmd_offset(pud, addr);
-
- return pmd;
+ return pmd_off_k(addr);
}
void __init early_fixmap_init(void)
@@ -415,9 +393,9 @@
FIXADDR_END);
BUG_ON(idx >= __end_of_fixed_addresses);
- /* we only support device mappings until pgprot_kernel has been set */
+ /* We support only device mappings before pgprot_kernel is set. */
if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
- pgprot_val(pgprot_kernel) == 0))
+ pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
return;
if (pgprot_val(prot))
@@ -436,7 +414,6 @@
struct cachepolicy *cp;
unsigned int cr = get_cr();
pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
- pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
int cpu_arch = cpu_architecture();
int i;
@@ -560,9 +537,6 @@
*/
cp = &cache_policies[cachepolicy];
vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
- s2_pgprot = cp->pte_s2;
- hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
- s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
#ifndef CONFIG_ARM_LPAE
/*
@@ -606,7 +580,6 @@
user_pgprot |= L_PTE_SHARED;
kern_pgprot |= L_PTE_SHARED;
vecs_pgprot |= L_PTE_SHARED;
- s2_pgprot |= L_PTE_SHARED;
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
@@ -668,9 +641,6 @@
pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
L_PTE_DIRTY | kern_pgprot);
- pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
- pgprot_s2_device = __pgprot(s2_device_pgprot);
- pgprot_hyp_device = __pgprot(hyp_device_pgprot);
mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
@@ -829,12 +799,12 @@
} while (pmd++, addr = next, addr != end);
}
-static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
+static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr,
unsigned long end, phys_addr_t phys,
const struct mem_type *type,
void *(*alloc)(unsigned long sz), bool ng)
{
- pud_t *pud = pud_offset(pgd, addr);
+ pud_t *pud = pud_offset(p4d, addr);
unsigned long next;
do {
@@ -844,6 +814,21 @@
} while (pud++, addr = next, addr != end);
}
+static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr,
+ unsigned long end, phys_addr_t phys,
+ const struct mem_type *type,
+ void *(*alloc)(unsigned long sz), bool ng)
+{
+ p4d_t *p4d = p4d_offset(pgd, addr);
+ unsigned long next;
+
+ do {
+ next = p4d_addr_end(addr, end);
+ alloc_init_pud(p4d, addr, next, phys, type, alloc, ng);
+ phys += next - addr;
+ } while (p4d++, addr = next, addr != end);
+}
+
#ifndef CONFIG_ARM_LPAE
static void __init create_36bit_mapping(struct mm_struct *mm,
struct map_desc *md,
@@ -891,7 +876,8 @@
pgd = pgd_offset(mm, addr);
end = addr + length;
do {
- pud_t *pud = pud_offset(pgd, addr);
+ p4d_t *p4d = p4d_offset(pgd, addr);
+ pud_t *pud = pud_offset(p4d, addr);
pmd_t *pmd = pmd_offset(pud, addr);
int i;
@@ -942,7 +928,7 @@
do {
unsigned long next = pgd_addr_end(addr, end);
- alloc_init_pud(pgd, addr, next, phys, type, alloc, ng);
+ alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng);
phys += next - addr;
addr = next;
@@ -978,7 +964,13 @@
bool ng)
{
#ifdef CONFIG_ARM_LPAE
- pud_t *pud = pud_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
+ p4d_t *p4d;
+ pud_t *pud;
+
+ p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
+ if (WARN_ON(!p4d))
+ return;
+ pud = pud_alloc(mm, p4d, md->virtual);
if (WARN_ON(!pud))
return;
pmd_alloc(mm, pud, 0);
@@ -1165,9 +1157,8 @@
void __init adjust_lowmem_bounds(void)
{
- phys_addr_t memblock_limit = 0;
- u64 vmalloc_limit;
- struct memblock_region *reg;
+ phys_addr_t block_start, block_end, memblock_limit = 0;
+ u64 vmalloc_limit, i;
phys_addr_t lowmem_limit = 0;
/*
@@ -1183,26 +1174,18 @@
* The first usable region must be PMD aligned. Mark its start
* as MEMBLOCK_NOMAP if it isn't
*/
- for_each_memblock(memory, reg) {
- if (!memblock_is_nomap(reg)) {
- if (!IS_ALIGNED(reg->base, PMD_SIZE)) {
- phys_addr_t len;
+ for_each_mem_range(i, &block_start, &block_end) {
+ if (!IS_ALIGNED(block_start, PMD_SIZE)) {
+ phys_addr_t len;
- len = round_up(reg->base, PMD_SIZE) - reg->base;
- memblock_mark_nomap(reg->base, len);
- }
- break;
+ len = round_up(block_start, PMD_SIZE) - block_start;
+ memblock_mark_nomap(block_start, len);
}
+ break;
}
- for_each_memblock(memory, reg) {
- phys_addr_t block_start = reg->base;
- phys_addr_t block_end = reg->base + reg->size;
-
- if (memblock_is_nomap(reg))
- continue;
-
- if (reg->base < vmalloc_limit) {
+ for_each_mem_range(i, &block_start, &block_end) {
+ if (block_start < vmalloc_limit) {
if (block_end > lowmem_limit)
/*
* Compare as u64 to ensure vmalloc_limit does
@@ -1460,19 +1443,15 @@
static void __init map_lowmem(void)
{
- struct memblock_region *reg;
phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE);
phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
+ phys_addr_t start, end;
+ u64 i;
/* Map all the lowmem memory banks. */
- for_each_memblock(memory, reg) {
- phys_addr_t start = reg->base;
- phys_addr_t end = start + reg->size;
+ for_each_mem_range(i, &start, &end) {
struct map_desc map;
- if (memblock_is_nomap(reg))
- continue;
-
if (end > arm_lowmem_limit)
end = arm_lowmem_limit;
if (start >= end)
@@ -1670,9 +1649,6 @@
empty_zero_page = virt_to_page(zero_page);
__flush_dcache_page(NULL, empty_zero_page);
-
- /* Compute the virt/idmap offset, mostly for the sake of KVM */
- kimage_voffset = (unsigned long)&kimage_voffset - virt_to_idmap(&kimage_voffset);
}
void __init early_mm_init(const struct machine_desc *mdesc)
@@ -1680,3 +1656,17 @@
build_mem_type_table();
early_paging_init(mdesc);
}
+
+void set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pteval)
+{
+ unsigned long ext = 0;
+
+ if (addr < TASK_SIZE && pte_valid_user(pteval)) {
+ if (!pte_special(pteval))
+ __sync_icache_dcache(pteval);
+ ext |= PTE_EXT_NG;
+ }
+
+ set_pte_ext(ptep, pteval, ext);
+}
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 24ecf8d..8b3d719 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -206,15 +206,11 @@
EXPORT_SYMBOL(ioremap);
void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
- __alias(ioremap_cached);
-
-void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size)
{
return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
__builtin_return_address(0));
}
EXPORT_SYMBOL(ioremap_cache);
-EXPORT_SYMBOL(ioremap_cached);
void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
{
diff --git a/arch/arm/mm/pageattr.c b/arch/arm/mm/pageattr.c
index d546efa..9790ae3 100644
--- a/arch/arm/mm/pageattr.c
+++ b/arch/arm/mm/pageattr.c
@@ -5,7 +5,6 @@
#include <linux/mm.h>
#include <linux/module.h>
-#include <asm/pgtable.h>
#include <asm/tlbflush.h>
#include <asm/set_memory.h>
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
index 478bd2c..c5e1b27 100644
--- a/arch/arm/mm/pgd.c
+++ b/arch/arm/mm/pgd.c
@@ -30,6 +30,7 @@
pgd_t *pgd_alloc(struct mm_struct *mm)
{
pgd_t *new_pgd, *init_pgd;
+ p4d_t *new_p4d, *init_p4d;
pud_t *new_pud, *init_pud;
pmd_t *new_pmd, *init_pmd;
pte_t *new_pte, *init_pte;
@@ -53,8 +54,12 @@
/*
* Allocate PMD table for modules and pkmap mappings.
*/
- new_pud = pud_alloc(mm, new_pgd + pgd_index(MODULES_VADDR),
+ new_p4d = p4d_alloc(mm, new_pgd + pgd_index(MODULES_VADDR),
MODULES_VADDR);
+ if (!new_p4d)
+ goto no_p4d;
+
+ new_pud = pud_alloc(mm, new_p4d, MODULES_VADDR);
if (!new_pud)
goto no_pud;
@@ -69,7 +74,11 @@
* contains the machine vectors. The vectors are always high
* with LPAE.
*/
- new_pud = pud_alloc(mm, new_pgd, 0);
+ new_p4d = p4d_alloc(mm, new_pgd, 0);
+ if (!new_p4d)
+ goto no_p4d;
+
+ new_pud = pud_alloc(mm, new_p4d, 0);
if (!new_pud)
goto no_pud;
@@ -91,7 +100,8 @@
pmd_val(*new_pmd) |= PMD_DOMAIN(DOMAIN_VECTORS);
#endif
- init_pud = pud_offset(init_pgd, 0);
+ init_p4d = p4d_offset(init_pgd, 0);
+ init_pud = pud_offset(init_p4d, 0);
init_pmd = pmd_offset(init_pud, 0);
init_pte = pte_offset_map(init_pmd, 0);
set_pte_ext(new_pte + 0, init_pte[0], 0);
@@ -108,6 +118,8 @@
no_pmd:
pud_free(mm, new_pud);
no_pud:
+ p4d_free(mm, new_p4d);
+no_p4d:
__pgd_free(new_pgd);
no_pgd:
return NULL;
@@ -116,6 +128,7 @@
void pgd_free(struct mm_struct *mm, pgd_t *pgd_base)
{
pgd_t *pgd;
+ p4d_t *p4d;
pud_t *pud;
pmd_t *pmd;
pgtable_t pte;
@@ -127,7 +140,11 @@
if (pgd_none_or_clear_bad(pgd))
goto no_pgd;
- pud = pud_offset(pgd, 0);
+ p4d = p4d_offset(pgd, 0);
+ if (p4d_none_or_clear_bad(p4d))
+ goto no_p4d;
+
+ pud = pud_offset(p4d, 0);
if (pud_none_or_clear_bad(pud))
goto no_pud;
@@ -144,8 +161,11 @@
pmd_free(mm, pmd);
mm_dec_nr_pmds(mm);
no_pud:
- pgd_clear(pgd);
+ p4d_clear(p4d);
pud_free(mm, pud);
+no_p4d:
+ pgd_clear(pgd);
+ p4d_free(mm, p4d);
no_pgd:
#ifdef CONFIG_ARM_LPAE
/*
@@ -156,15 +176,21 @@
continue;
if (pgd_val(*pgd) & L_PGD_SWAPPER)
continue;
- pud = pud_offset(pgd, 0);
+ p4d = p4d_offset(pgd, 0);
+ if (p4d_none_or_clear_bad(p4d))
+ continue;
+ pud = pud_offset(p4d, 0);
if (pud_none_or_clear_bad(pud))
continue;
pmd = pmd_offset(pud, 0);
pud_clear(pud);
pmd_free(mm, pmd);
mm_dec_nr_pmds(mm);
- pgd_clear(pgd);
+ p4d_clear(p4d);
pud_free(mm, pud);
+ mm_dec_nr_puds(mm);
+ pgd_clear(pgd);
+ p4d_free(mm, p4d);
}
#endif
__pgd_free(pgd_base);
diff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c
index 699fa2e..59d916c 100644
--- a/arch/arm/mm/pmsa-v7.c
+++ b/arch/arm/mm/pmsa-v7.c
@@ -231,12 +231,13 @@
void __init pmsav7_adjust_lowmem_bounds(void)
{
phys_addr_t specified_mem_size = 0, total_mem_size = 0;
- struct memblock_region *reg;
- bool first = true;
phys_addr_t mem_start;
phys_addr_t mem_end;
+ phys_addr_t reg_start, reg_end;
unsigned int mem_max_regions;
- int num, i;
+ bool first = true;
+ int num;
+ u64 i;
/* Free-up PMSAv7_PROBE_REGION */
mpu_min_region_order = __mpu_min_region_order();
@@ -262,19 +263,19 @@
mem_max_regions -= num;
#endif
- for_each_memblock(memory, reg) {
+ for_each_mem_range(i, ®_start, ®_end) {
if (first) {
phys_addr_t phys_offset = PHYS_OFFSET;
/*
* Initially only use memory continuous from
* PHYS_OFFSET */
- if (reg->base != phys_offset)
+ if (reg_start != phys_offset)
panic("First memory bank must be contiguous from PHYS_OFFSET");
- mem_start = reg->base;
- mem_end = reg->base + reg->size;
- specified_mem_size = reg->size;
+ mem_start = reg_start;
+ mem_end = reg_end;
+ specified_mem_size = mem_end - mem_start;
first = false;
} else {
/*
@@ -283,8 +284,8 @@
* blocks separately while iterating)
*/
pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
- &mem_end, ®->base);
- memblock_remove(reg->base, 0 - reg->base);
+ &mem_end, ®_start);
+ memblock_remove(reg_start, 0 - reg_start);
break;
}
}
diff --git a/arch/arm/mm/pmsa-v8.c b/arch/arm/mm/pmsa-v8.c
index 0d7d5fb..8359748 100644
--- a/arch/arm/mm/pmsa-v8.c
+++ b/arch/arm/mm/pmsa-v8.c
@@ -94,19 +94,20 @@
void __init pmsav8_adjust_lowmem_bounds(void)
{
phys_addr_t mem_end;
- struct memblock_region *reg;
+ phys_addr_t reg_start, reg_end;
bool first = true;
+ u64 i;
- for_each_memblock(memory, reg) {
+ for_each_mem_range(i, ®_start, ®_end) {
if (first) {
phys_addr_t phys_offset = PHYS_OFFSET;
/*
* Initially only use memory continuous from
* PHYS_OFFSET */
- if (reg->base != phys_offset)
+ if (reg_start != phys_offset)
panic("First memory bank must be contiguous from PHYS_OFFSET");
- mem_end = reg->base + reg->size;
+ mem_end = reg_end;
first = false;
} else {
/*
@@ -115,8 +116,8 @@
* blocks separately while iterating)
*/
pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
- &mem_end, ®->base);
- memblock_remove(reg->base, 0 - reg->base);
+ &mem_end, ®_start);
+ memblock_remove(reg_start, 0 - reg_start);
break;
}
}
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 4fa5371..6837cf7 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -11,11 +11,11 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -491,7 +491,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __arm1020_proc_info,#object
__arm1020_proc_info:
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 5d8a833..df49b10 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -11,11 +11,11 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -449,7 +449,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __arm1020e_proc_info,#object
__arm1020e_proc_info:
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index b3dd95c..e89ce46 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -11,11 +11,11 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -443,7 +443,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __arm1022_proc_info,#object
__arm1022_proc_info:
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index ac5afde..7fdd1a2 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -11,11 +11,11 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -138,7 +138,7 @@
mov ip, #0
__flush_whole_cache:
#ifndef CONFIG_CPU_DCACHE_DISABLE
-1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
+1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
bne 1b
#endif
tst r2, #VM_EXEC
@@ -363,7 +363,7 @@
#ifdef CONFIG_MMU
mov r1, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
-1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
+1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
bne 1b
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
@@ -437,7 +437,7 @@
string cpu_arm1026_name, "ARM1026EJ-S"
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __arm1026_proc_info,#object
__arm1026_proc_info:
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index c99d243..3b687e6 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -20,11 +20,11 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -172,7 +172,7 @@
* See <asm/procinfo.h> for a definition of this structure.
*/
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
.type __\name\()_proc_info,#object
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 1b4a383..f2ec3bc 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -6,11 +6,11 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -128,7 +128,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __arm740_proc_info,#object
__arm740_proc_info:
.long 0x41807400
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 17a4687..01bbe75 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -6,11 +6,11 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -72,7 +72,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.macro arm7tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
extra_hwcaps=0
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 298c76b..a234cd8 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -13,10 +13,10 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -434,7 +434,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __arm920_proc_info,#object
__arm920_proc_info:
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 824be3a..53c029d 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -14,10 +14,10 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -412,7 +412,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __arm922_proc_info,#object
__arm922_proc_info:
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index d40cff8..0bfad62 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -37,10 +37,10 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -477,7 +477,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
.type __\name\()_proc_info,#object
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index f3cd08f..0487a2c 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -13,10 +13,10 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -131,7 +131,7 @@
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
+1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
bne 1b
#endif
tst r2, #VM_EXEC
@@ -358,7 +358,7 @@
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
+1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
bne 1b
#endif
mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
@@ -460,7 +460,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __arm926_proc_info,#object
__arm926_proc_info:
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 1c26d99..cf9bfcc 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -6,10 +6,10 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -340,7 +340,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __arm940_proc_info,#object
__arm940_proc_info:
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 2dc1c75..6fb3898 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -8,10 +8,10 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -395,7 +395,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __arm946_proc_info,#object
__arm946_proc_info:
.long 0x41009460
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 913c06e..a054c0e 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -6,11 +6,11 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -66,7 +66,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.macro arm9tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
.type __\name\()_proc_info, #object
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 8120b6f..2c73e0d 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -11,10 +11,10 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
@@ -185,7 +185,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __fa526_proc_info,#object
__fa526_proc_info:
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index bb6dc34..61ce82a 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -8,10 +8,10 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -571,7 +571,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req
.type __\name\()_proc_info,#object
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 60ac7c5..d9f7dfe 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -5,7 +5,6 @@
* VMA_VM_FLAGS
* VM_EXEC
*/
-#include <linux/const.h>
#include <asm/asm-offsets.h>
#include <asm/thread_info.h>
@@ -31,8 +30,7 @@
* act_mm - get current->active_mm
*/
.macro act_mm, rd
- bic \rd, sp, #(THREAD_SIZE - 1) & ~63
- bic \rd, \rd, #63
+ get_thread_info \rd
ldr \rd, [\rd, #TI_TASK]
.if (TSK_ACTIVE_MM > IMM12_MASK)
add \rd, \rd, #TSK_ACTIVE_MM & ~IMM12_MASK
@@ -342,6 +340,7 @@
.macro define_tlb_functions name:req, flags_up:req, flags_smp
.type \name\()_tlb_fns, #object
+ .align 2
ENTRY(\name\()_tlb_fns)
.long \name\()_flush_user_tlb_range
.long \name\()_flush_kern_tlb_range
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index f083085..1645cca 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -9,10 +9,10 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -416,7 +416,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __88sv331x_proc_info,#object
__88sv331x_proc_info:
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index d5bc5d7..4071f7a 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -12,12 +12,12 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <mach/hardware.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"
@@ -196,7 +196,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.type __sa110_proc_info,#object
__sa110_proc_info:
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index be7b611..e723bd4 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -17,12 +17,12 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <mach/hardware.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include "proc-macros.S"
@@ -239,7 +239,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
.type __\name\()_proc_info,#object
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index c1c85eb..a0618f3 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -9,11 +9,11 @@
*/
#include <linux/init.h>
#include <linux/linkage.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include "proc-macros.S"
@@ -261,7 +261,7 @@
string cpu_elf_name, "v6"
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
/*
* Match any ARMv6 processor core.
diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c
index a6554fd..06dbfb9 100644
--- a/arch/arm/mm/proc-v7-bugs.c
+++ b/arch/arm/mm/proc-v7-bugs.c
@@ -1,14 +1,40 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/arm-smccc.h>
#include <linux/kernel.h>
-#include <linux/psci.h>
#include <linux/smp.h>
#include <asm/cp15.h>
#include <asm/cputype.h>
#include <asm/proc-fns.h>
+#include <asm/spectre.h>
#include <asm/system_misc.h>
+#ifdef CONFIG_ARM_PSCI
+static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
+ ARM_SMCCC_ARCH_WORKAROUND_1, &res);
+
+ switch ((int)res.a0) {
+ case SMCCC_RET_SUCCESS:
+ return SPECTRE_MITIGATED;
+
+ case SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED:
+ return SPECTRE_UNAFFECTED;
+
+ default:
+ return SPECTRE_VULNERABLE;
+ }
+}
+#else
+static int __maybe_unused spectre_v2_get_cpu_fw_mitigation_state(void)
+{
+ return SPECTRE_VULNERABLE;
+}
+#endif
+
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn);
@@ -37,13 +63,61 @@
arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
}
-static void cpu_v7_spectre_init(void)
+static unsigned int spectre_v2_install_workaround(unsigned int method)
{
const char *spectre_v2_method = NULL;
int cpu = smp_processor_id();
if (per_cpu(harden_branch_predictor_fn, cpu))
- return;
+ return SPECTRE_MITIGATED;
+
+ switch (method) {
+ case SPECTRE_V2_METHOD_BPIALL:
+ per_cpu(harden_branch_predictor_fn, cpu) =
+ harden_branch_predictor_bpiall;
+ spectre_v2_method = "BPIALL";
+ break;
+
+ case SPECTRE_V2_METHOD_ICIALLU:
+ per_cpu(harden_branch_predictor_fn, cpu) =
+ harden_branch_predictor_iciallu;
+ spectre_v2_method = "ICIALLU";
+ break;
+
+ case SPECTRE_V2_METHOD_HVC:
+ per_cpu(harden_branch_predictor_fn, cpu) =
+ call_hvc_arch_workaround_1;
+ cpu_do_switch_mm = cpu_v7_hvc_switch_mm;
+ spectre_v2_method = "hypervisor";
+ break;
+
+ case SPECTRE_V2_METHOD_SMC:
+ per_cpu(harden_branch_predictor_fn, cpu) =
+ call_smc_arch_workaround_1;
+ cpu_do_switch_mm = cpu_v7_smc_switch_mm;
+ spectre_v2_method = "firmware";
+ break;
+ }
+
+ if (spectre_v2_method)
+ pr_info("CPU%u: Spectre v2: using %s workaround\n",
+ smp_processor_id(), spectre_v2_method);
+
+ return SPECTRE_MITIGATED;
+}
+#else
+static unsigned int spectre_v2_install_workaround(unsigned int method)
+{
+ pr_info("CPU%u: Spectre V2: workarounds disabled by configuration\n",
+ smp_processor_id());
+
+ return SPECTRE_VULNERABLE;
+}
+#endif
+
+static void cpu_v7_spectre_v2_init(void)
+{
+ unsigned int state, method = 0;
switch (read_cpuid_part()) {
case ARM_CPU_PART_CORTEX_A8:
@@ -52,75 +126,133 @@
case ARM_CPU_PART_CORTEX_A17:
case ARM_CPU_PART_CORTEX_A73:
case ARM_CPU_PART_CORTEX_A75:
- per_cpu(harden_branch_predictor_fn, cpu) =
- harden_branch_predictor_bpiall;
- spectre_v2_method = "BPIALL";
+ state = SPECTRE_MITIGATED;
+ method = SPECTRE_V2_METHOD_BPIALL;
break;
case ARM_CPU_PART_CORTEX_A15:
case ARM_CPU_PART_BRAHMA_B15:
- per_cpu(harden_branch_predictor_fn, cpu) =
- harden_branch_predictor_iciallu;
- spectre_v2_method = "ICIALLU";
+ state = SPECTRE_MITIGATED;
+ method = SPECTRE_V2_METHOD_ICIALLU;
break;
-#ifdef CONFIG_ARM_PSCI
case ARM_CPU_PART_BRAHMA_B53:
/* Requires no workaround */
+ state = SPECTRE_UNAFFECTED;
break;
+
default:
/* Other ARM CPUs require no workaround */
- if (read_cpuid_implementor() == ARM_CPU_IMP_ARM)
+ if (read_cpuid_implementor() == ARM_CPU_IMP_ARM) {
+ state = SPECTRE_UNAFFECTED;
break;
- /* fallthrough */
- /* Cortex A57/A72 require firmware workaround */
+ }
+
+ fallthrough;
+
+ /* Cortex A57/A72 require firmware workaround */
case ARM_CPU_PART_CORTEX_A57:
- case ARM_CPU_PART_CORTEX_A72: {
- struct arm_smccc_res res;
-
- if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
+ case ARM_CPU_PART_CORTEX_A72:
+ state = spectre_v2_get_cpu_fw_mitigation_state();
+ if (state != SPECTRE_MITIGATED)
break;
- switch (psci_ops.conduit) {
- case PSCI_CONDUIT_HVC:
- arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
- ARM_SMCCC_ARCH_WORKAROUND_1, &res);
- if ((int)res.a0 != 0)
- break;
- per_cpu(harden_branch_predictor_fn, cpu) =
- call_hvc_arch_workaround_1;
- cpu_do_switch_mm = cpu_v7_hvc_switch_mm;
- spectre_v2_method = "hypervisor";
+ switch (arm_smccc_1_1_get_conduit()) {
+ case SMCCC_CONDUIT_HVC:
+ method = SPECTRE_V2_METHOD_HVC;
break;
- case PSCI_CONDUIT_SMC:
- arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
- ARM_SMCCC_ARCH_WORKAROUND_1, &res);
- if ((int)res.a0 != 0)
- break;
- per_cpu(harden_branch_predictor_fn, cpu) =
- call_smc_arch_workaround_1;
- cpu_do_switch_mm = cpu_v7_smc_switch_mm;
- spectre_v2_method = "firmware";
+ case SMCCC_CONDUIT_SMC:
+ method = SPECTRE_V2_METHOD_SMC;
break;
default:
+ state = SPECTRE_VULNERABLE;
break;
}
}
-#endif
+
+ if (state == SPECTRE_MITIGATED)
+ state = spectre_v2_install_workaround(method);
+
+ spectre_v2_update_state(state, method);
+}
+
+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
+static int spectre_bhb_method;
+
+static const char *spectre_bhb_method_name(int method)
+{
+ switch (method) {
+ case SPECTRE_V2_METHOD_LOOP8:
+ return "loop";
+
+ case SPECTRE_V2_METHOD_BPIALL:
+ return "BPIALL";
+
+ default:
+ return "unknown";
+ }
+}
+
+static int spectre_bhb_install_workaround(int method)
+{
+ if (spectre_bhb_method != method) {
+ if (spectre_bhb_method) {
+ pr_err("CPU%u: Spectre BHB: method disagreement, system vulnerable\n",
+ smp_processor_id());
+
+ return SPECTRE_VULNERABLE;
+ }
+
+ if (spectre_bhb_update_vectors(method) == SPECTRE_VULNERABLE)
+ return SPECTRE_VULNERABLE;
+
+ spectre_bhb_method = method;
}
- if (spectre_v2_method)
- pr_info("CPU%u: Spectre v2: using %s workaround\n",
- smp_processor_id(), spectre_v2_method);
+ pr_info("CPU%u: Spectre BHB: using %s workaround\n",
+ smp_processor_id(), spectre_bhb_method_name(method));
+
+ return SPECTRE_MITIGATED;
}
#else
-static void cpu_v7_spectre_init(void)
+static int spectre_bhb_install_workaround(int method)
{
+ return SPECTRE_VULNERABLE;
}
#endif
+static void cpu_v7_spectre_bhb_init(void)
+{
+ unsigned int state, method = 0;
+
+ switch (read_cpuid_part()) {
+ case ARM_CPU_PART_CORTEX_A15:
+ case ARM_CPU_PART_BRAHMA_B15:
+ case ARM_CPU_PART_CORTEX_A57:
+ case ARM_CPU_PART_CORTEX_A72:
+ state = SPECTRE_MITIGATED;
+ method = SPECTRE_V2_METHOD_LOOP8;
+ break;
+
+ case ARM_CPU_PART_CORTEX_A73:
+ case ARM_CPU_PART_CORTEX_A75:
+ state = SPECTRE_MITIGATED;
+ method = SPECTRE_V2_METHOD_BPIALL;
+ break;
+
+ default:
+ state = SPECTRE_UNAFFECTED;
+ break;
+ }
+
+ if (state == SPECTRE_MITIGATED)
+ state = spectre_bhb_install_workaround(method);
+
+ spectre_v2_update_state(state, method);
+}
+
static __maybe_unused bool cpu_v7_check_auxcr_set(bool *warned,
u32 mask, const char *msg)
{
@@ -149,16 +281,17 @@
void cpu_v7_ca8_ibe(void)
{
if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6)))
- cpu_v7_spectre_init();
+ cpu_v7_spectre_v2_init();
}
void cpu_v7_ca15_ibe(void)
{
if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0)))
- cpu_v7_spectre_init();
+ cpu_v7_spectre_v2_init();
}
void cpu_v7_bugs_init(void)
{
- cpu_v7_spectre_init();
+ cpu_v7_spectre_v2_init();
+ cpu_v7_spectre_bhb_init();
}
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index c4e8006..28c9d32 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -9,11 +9,11 @@
#include <linux/arm-smccc.h>
#include <linux/init.h>
#include <linux/linkage.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
#include <asm/memory.h>
#include "proc-macros.S"
@@ -644,7 +644,7 @@
string cpu_elf_name, "v7"
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
/*
* Standard v7 proc info content
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 1a49d50..84459c1 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -93,7 +93,7 @@
ret lr
ENDPROC(cpu_cm7_proc_fin)
- .section ".init.text", #alloc, #execinstr
+ .section ".init.text", "ax"
__v7m_cm7_setup:
mov r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP)
@@ -177,7 +177,7 @@
string cpu_elf_name "v7m"
string cpu_v7m_name "ARMv7-M"
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0, proc_fns = v7m_processor_functions
.long 0 /* proc_info_list.__cpu_mm_mmu_flags */
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 1ac0fbb..a17afe7 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -23,9 +23,9 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
-#include <asm/pgtable.h>
#include <asm/pgtable-hwdef.h>
#include <asm/page.h>
#include <asm/ptrace.h>
@@ -496,7 +496,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req
.type __\name\()_proc_info,#object
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index bdb2b77..d82590a 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -19,9 +19,9 @@
#include <linux/linkage.h>
#include <linux/init.h>
+#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
-#include <asm/pgtable.h>
#include <asm/pgtable-hwdef.h>
#include <asm/page.h>
#include <asm/ptrace.h>
@@ -610,7 +610,7 @@
.align
- .section ".proc.info.init", #alloc
+ .section ".proc.info.init", "a"
.macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
.type __\name\()_proc_info,#object
diff --git a/arch/arm/mm/pv-fixup-asm.S b/arch/arm/mm/pv-fixup-asm.S
index 6d081d1..5c5e195 100644
--- a/arch/arm/mm/pv-fixup-asm.S
+++ b/arch/arm/mm/pv-fixup-asm.S
@@ -6,10 +6,10 @@
* for Keystone 2
*/
#include <linux/linkage.h>
+#include <linux/pgtable.h>
#include <asm/asm-offsets.h>
#include <asm/cp15.h>
#include <asm/memory.h>
-#include <asm/pgtable.h>
.section ".idmap.text", "ax"
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index b51a8c7..1214e39 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -36,6 +36,10 @@
* +-----+
* |RSVD | JIT scratchpad
* current ARM_SP => +-----+ <= (BPF_FP - STACK_SIZE + SCRATCH_SIZE)
+ * | ... | caller-saved registers
+ * +-----+
+ * | ... | arguments passed on stack
+ * ARM_SP during call => +-----|
* | |
* | ... | Function call stack
* | |
@@ -63,6 +67,12 @@
*
* When popping registers off the stack at the end of a BPF function, we
* reference them via the current ARM_FP register.
+ *
+ * Some eBPF operations are implemented via a call to a helper function.
+ * Such calls are "invisible" in the eBPF code, so it is up to the calling
+ * program to preserve any caller-saved ARM registers during the call. The
+ * JIT emits code to push and pop those registers onto the stack, immediately
+ * above the callee stack frame.
*/
#define CALLEE_MASK (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \
1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R9 | \
@@ -70,6 +80,8 @@
#define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR)
#define CALLEE_POP_MASK (CALLEE_MASK | 1 << ARM_PC)
+#define CALLER_MASK (1 << ARM_R0 | 1 << ARM_R1 | 1 << ARM_R2 | 1 << ARM_R3)
+
enum {
/* Stack layout - these are offsets from (top of stack - 4) */
BPF_R2_HI,
@@ -464,6 +476,7 @@
static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
{
+ const int exclude_mask = BIT(ARM_R0) | BIT(ARM_R1);
const s8 *tmp = bpf2a32[TMP_REG_1];
#if __LINUX_ARM_ARCH__ == 7
@@ -495,11 +508,17 @@
emit(ARM_MOV_R(ARM_R0, rm), ctx);
}
+ /* Push caller-saved registers on stack */
+ emit(ARM_PUSH(CALLER_MASK & ~exclude_mask), ctx);
+
/* Call appropriate function */
emit_mov_i(ARM_IP, op == BPF_DIV ?
(u32)jit_udiv32 : (u32)jit_mod32, ctx);
emit_blx_r(ARM_IP, ctx);
+ /* Restore caller-saved registers from stack */
+ emit(ARM_POP(CALLER_MASK & ~exclude_mask), ctx);
+
/* Save return value */
if (rd != ARM_R0)
emit(ARM_MOV_R(rd, ARM_R0), ctx);
@@ -795,6 +814,9 @@
case BPF_RSH:
emit(ARM_LSR_I(rd, rd, val), ctx);
break;
+ case BPF_ARSH:
+ emit(ARM_ASR_I(rd, rd, val), ctx);
+ break;
case BPF_NEG:
emit(ARM_RSB_I(rd, rd, val), ctx);
break;
@@ -860,8 +882,8 @@
emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx);
emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx);
- _emit(ARM_COND_MI, ARM_B(0), ctx);
- emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASR, tmp2[0]), ctx);
+ _emit(ARM_COND_PL,
+ ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASR, tmp2[0]), ctx);
emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_ASR, rt), ctx);
arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
@@ -1276,12 +1298,9 @@
static void build_prologue(struct jit_ctx *ctx)
{
- const s8 r0 = bpf2a32[BPF_REG_0][1];
- const s8 r2 = bpf2a32[BPF_REG_1][1];
- const s8 r3 = bpf2a32[BPF_REG_1][0];
- const s8 r4 = bpf2a32[BPF_REG_6][1];
- const s8 fplo = bpf2a32[BPF_REG_FP][1];
- const s8 fphi = bpf2a32[BPF_REG_FP][0];
+ const s8 arm_r0 = bpf2a32[BPF_REG_0][1];
+ const s8 *bpf_r1 = bpf2a32[BPF_REG_1];
+ const s8 *bpf_fp = bpf2a32[BPF_REG_FP];
const s8 *tcc = bpf2a32[TCALL_CNT];
/* Save callee saved registers. */
@@ -1294,8 +1313,10 @@
emit(ARM_PUSH(CALLEE_PUSH_MASK), ctx);
emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx);
#endif
- /* Save frame pointer for later */
- emit(ARM_SUB_I(ARM_IP, ARM_SP, SCRATCH_SIZE), ctx);
+ /* mov r3, #0 */
+ /* sub r2, sp, #SCRATCH_SIZE */
+ emit(ARM_MOV_I(bpf_r1[0], 0), ctx);
+ emit(ARM_SUB_I(bpf_r1[1], ARM_SP, SCRATCH_SIZE), ctx);
ctx->stack_size = imm8m(STACK_SIZE);
@@ -1303,18 +1324,15 @@
emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx);
/* Set up BPF prog stack base register */
- emit_a32_mov_r(fplo, ARM_IP, ctx);
- emit_a32_mov_i(fphi, 0, ctx);
+ emit_a32_mov_r64(true, bpf_fp, bpf_r1, ctx);
- /* mov r4, 0 */
- emit(ARM_MOV_I(r4, 0), ctx);
+ /* Initialize Tail Count */
+ emit(ARM_MOV_I(bpf_r1[1], 0), ctx);
+ emit_a32_mov_r64(true, tcc, bpf_r1, ctx);
/* Move BPF_CTX to BPF_R1 */
- emit(ARM_MOV_R(r3, r4), ctx);
- emit(ARM_MOV_R(r2, r0), ctx);
- /* Initialize Tail Count */
- emit(ARM_STR_I(r4, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(tcc[0])), ctx);
- emit(ARM_STR_I(r4, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(tcc[1])), ctx);
+ emit(ARM_MOV_R(bpf_r1[1], arm_r0), ctx);
+
/* end of prologue */
}
@@ -1412,7 +1430,6 @@
case BPF_ALU | BPF_MUL | BPF_X:
case BPF_ALU | BPF_LSH | BPF_X:
case BPF_ALU | BPF_RSH | BPF_X:
- case BPF_ALU | BPF_ARSH | BPF_K:
case BPF_ALU | BPF_ARSH | BPF_X:
case BPF_ALU64 | BPF_ADD | BPF_K:
case BPF_ALU64 | BPF_ADD | BPF_X:
@@ -1469,10 +1486,12 @@
case BPF_ALU64 | BPF_MOD | BPF_K:
case BPF_ALU64 | BPF_MOD | BPF_X:
goto notyet;
- /* dst = dst >> imm */
/* dst = dst << imm */
- case BPF_ALU | BPF_RSH | BPF_K:
+ /* dst = dst >> imm */
+ /* dst = dst >> imm (signed) */
case BPF_ALU | BPF_LSH | BPF_K:
+ case BPF_ALU | BPF_RSH | BPF_K:
+ case BPF_ALU | BPF_ARSH | BPF_K:
if (unlikely(imm > 31))
return -EINVAL;
if (imm)
diff --git a/arch/arm/net/bpf_jit_32.h b/arch/arm/net/bpf_jit_32.h
index fb67cbc..e0b593a 100644
--- a/arch/arm/net/bpf_jit_32.h
+++ b/arch/arm/net/bpf_jit_32.h
@@ -94,6 +94,9 @@
#define ARM_INST_LSR_I 0x01a00020
#define ARM_INST_LSR_R 0x01a00030
+#define ARM_INST_ASR_I 0x01a00040
+#define ARM_INST_ASR_R 0x01a00050
+
#define ARM_INST_MOV_R 0x01a00000
#define ARM_INST_MOVS_R 0x01b00000
#define ARM_INST_MOV_I 0x03a00000
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 93fd7fc..272670e 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -23,7 +23,7 @@
config POWER_AVS_OMAP
bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"
- depends on POWER_AVS && (ARCH_OMAP3 || ARCH_OMAP4) && PM
+ depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
select POWER_SUPPLY
help
Say Y to enable AVS(Adaptive Voltage Scaling)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 08c9941..1eb5900 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -16,7 +16,7 @@
*
* Support functions for the OMAP internal DMA channels.
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Converted DMA library into DMA platform driver.
* - G, Manjunath Kondaiah <manjugk@ti.com>
*/
@@ -65,18 +65,9 @@
static struct omap_system_dma_plat_info *p;
static struct omap_dma_dev_attr *d;
static void omap_clear_dma(int lch);
-static int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
- unsigned char write_prio);
static int enable_1510_mode;
static u32 errata;
-static struct omap_dma_global_context_registers {
- u32 dma_irqenable_l0;
- u32 dma_irqenable_l1;
- u32 dma_ocp_sysconfig;
- u32 dma_gcr;
-} omap_dma_global_context;
-
struct dma_link_info {
int *linked_dmach_q;
int no_of_lchs_linked;
@@ -90,42 +81,6 @@
};
-static struct dma_link_info *dma_linked_lch;
-
-#ifndef CONFIG_ARCH_OMAP1
-
-/* Chain handling macros */
-#define OMAP_DMA_CHAIN_QINIT(chain_id) \
- do { \
- dma_linked_lch[chain_id].q_head = \
- dma_linked_lch[chain_id].q_tail = \
- dma_linked_lch[chain_id].q_count = 0; \
- } while (0)
-#define OMAP_DMA_CHAIN_QFULL(chain_id) \
- (dma_linked_lch[chain_id].no_of_lchs_linked == \
- dma_linked_lch[chain_id].q_count)
-#define OMAP_DMA_CHAIN_QLAST(chain_id) \
- do { \
- ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
- dma_linked_lch[chain_id].q_count) \
- } while (0)
-#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
- (0 == dma_linked_lch[chain_id].q_count)
-#define __OMAP_DMA_CHAIN_INCQ(end) \
- ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
-#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
- do { \
- __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
- dma_linked_lch[chain_id].q_count--; \
- } while (0)
-
-#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
- do { \
- __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
- dma_linked_lch[chain_id].q_count++; \
- } while (0)
-#endif
-
static int dma_lch_count;
static int dma_chan_count;
static int omap_dma_reserve_channels;
@@ -137,9 +92,6 @@
static void omap_disable_channel_irq(int lch);
static inline void omap_enable_channel_irq(int lch);
-#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
- __func__);
-
#ifdef CONFIG_ARCH_OMAP15XX
/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
static int omap_dma_in_1510_mode(void)
@@ -278,19 +230,6 @@
}
EXPORT_SYMBOL(omap_set_dma_transfer_params);
-void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
-{
- if (dma_omap2plus()) {
- u32 csdp;
-
- csdp = p->dma_read(CSDP, lch);
- csdp &= ~(0x3 << 16);
- csdp |= (mode << 16);
- p->dma_write(csdp, CSDP, lch);
- }
-}
-EXPORT_SYMBOL(omap_set_dma_write_mode);
-
void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
{
if (dma_omap1() && !dma_omap15xx()) {
@@ -332,25 +271,6 @@
}
EXPORT_SYMBOL(omap_set_dma_src_params);
-void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
-{
- omap_set_dma_transfer_params(lch, params->data_type,
- params->elem_count, params->frame_count,
- params->sync_mode, params->trigger,
- params->src_or_dst_synch);
- omap_set_dma_src_params(lch, params->src_port,
- params->src_amode, params->src_start,
- params->src_ei, params->src_fi);
-
- omap_set_dma_dest_params(lch, params->dst_port,
- params->dst_amode, params->dst_start,
- params->dst_ei, params->dst_fi);
- if (params->read_prio || params->write_prio)
- omap_dma_set_prio_lch(lch, params->read_prio,
- params->write_prio);
-}
-EXPORT_SYMBOL(omap_set_dma_params);
-
void omap_set_dma_src_data_pack(int lch, int enable)
{
u32 l;
@@ -389,14 +309,14 @@
* not supported by current hardware on OMAP1
* w |= (0x03 << 7);
*/
- /* fall through */
+ fallthrough;
case OMAP_DMA_DATA_BURST_16:
if (dma_omap2plus()) {
burst = 0x3;
break;
}
/* OMAP1 don't support burst 16 */
- /* fall through */
+ fallthrough;
default:
BUG();
}
@@ -473,7 +393,7 @@
break;
}
/* OMAP1 don't support burst 16 */
- /* fall through */
+ fallthrough;
default:
printk(KERN_ERR "Invalid DMA burst mode\n");
BUG();
@@ -507,12 +427,6 @@
p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
}
-void omap_enable_dma_irq(int lch, u16 bits)
-{
- dma_chan[lch].enabled_irqs |= bits;
-}
-EXPORT_SYMBOL(omap_enable_dma_irq);
-
void omap_disable_dma_irq(int lch, u16 bits)
{
dma_chan[lch].enabled_irqs &= ~bits;
@@ -532,12 +446,6 @@
if (dma_chan[lch].next_lch != -1)
l = dma_chan[lch].next_lch | (1 << 15);
-#ifndef CONFIG_ARCH_OMAP1
- if (dma_omap2plus())
- if (dma_chan[lch].next_linked_ch != -1)
- l = dma_chan[lch].next_linked_ch | (1 << 15);
-#endif
-
p->dma_write(l, CLNK_CTRL, lch);
}
@@ -564,42 +472,6 @@
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
}
-static inline void omap2_enable_irq_lch(int lch)
-{
- u32 val;
- unsigned long flags;
-
- if (dma_omap1())
- return;
-
- spin_lock_irqsave(&dma_chan_lock, flags);
- /* clear IRQ STATUS */
- p->dma_write(1 << lch, IRQSTATUS_L0, lch);
- /* Enable interrupt */
- val = p->dma_read(IRQENABLE_L0, lch);
- val |= 1 << lch;
- p->dma_write(val, IRQENABLE_L0, lch);
- spin_unlock_irqrestore(&dma_chan_lock, flags);
-}
-
-static inline void omap2_disable_irq_lch(int lch)
-{
- u32 val;
- unsigned long flags;
-
- if (dma_omap1())
- return;
-
- spin_lock_irqsave(&dma_chan_lock, flags);
- /* Disable interrupt */
- val = p->dma_read(IRQENABLE_L0, lch);
- val &= ~(1 << lch);
- p->dma_write(val, IRQENABLE_L0, lch);
- /* clear IRQ STATUS */
- p->dma_write(1 << lch, IRQSTATUS_L0, lch);
- spin_unlock_irqrestore(&dma_chan_lock, flags);
-}
-
int omap_request_dma(int dev_id, const char *dev_name,
void (*callback)(int lch, u16 ch_status, void *data),
void *data, int *dma_ch_out)
@@ -628,9 +500,6 @@
if (p->clear_lch_regs)
p->clear_lch_regs(free_ch);
- if (dma_omap2plus())
- omap_clear_dma(free_ch);
-
spin_unlock_irqrestore(&dma_chan_lock, flags);
chan->dev_name = dev_name;
@@ -638,20 +507,10 @@
chan->data = data;
chan->flags = 0;
-#ifndef CONFIG_ARCH_OMAP1
- if (dma_omap2plus()) {
- chan->chain_id = -1;
- chan->next_linked_ch = -1;
- }
-#endif
-
chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
if (dma_omap1())
chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
- else if (dma_omap2plus())
- chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
- OMAP2_DMA_TRANS_ERR_IRQ;
if (dma_omap16xx()) {
/* If the sync device is set, configure it dynamically. */
@@ -668,11 +527,6 @@
p->dma_write(dev_id, CCR, free_ch);
}
- if (dma_omap2plus()) {
- omap_enable_channel_irq(free_ch);
- omap2_enable_irq_lch(free_ch);
- }
-
*dma_ch_out = free_ch;
return 0;
@@ -689,20 +543,12 @@
return;
}
- /* Disable interrupt for logical channel */
- if (dma_omap2plus())
- omap2_disable_irq_lch(lch);
-
/* Disable all DMA interrupts for the channel. */
omap_disable_channel_irq(lch);
/* Make sure the DMA transfer is stopped. */
p->dma_write(0, CCR, lch);
- /* Clear registers */
- if (dma_omap2plus())
- omap_clear_dma(lch);
-
spin_lock_irqsave(&dma_chan_lock, flags);
dma_chan[lch].dev_id = -1;
dma_chan[lch].next_lch = -1;
@@ -711,71 +557,6 @@
}
EXPORT_SYMBOL(omap_free_dma);
-/**
- * @brief omap_dma_set_global_params : Set global priority settings for dma
- *
- * @param arb_rate
- * @param max_fifo_depth
- * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
- * DMA_THREAD_RESERVE_ONET
- * DMA_THREAD_RESERVE_TWOT
- * DMA_THREAD_RESERVE_THREET
- */
-void
-omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
-{
- u32 reg;
-
- if (dma_omap1()) {
- printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
- return;
- }
-
- if (max_fifo_depth == 0)
- max_fifo_depth = 1;
- if (arb_rate == 0)
- arb_rate = 1;
-
- reg = 0xff & max_fifo_depth;
- reg |= (0x3 & tparams) << 12;
- reg |= (arb_rate & 0xff) << 16;
-
- p->dma_write(reg, GCR, 0);
-}
-EXPORT_SYMBOL(omap_dma_set_global_params);
-
-/**
- * @brief omap_dma_set_prio_lch : Set channel wise priority settings
- *
- * @param lch
- * @param read_prio - Read priority
- * @param write_prio - Write priority
- * Both of the above can be set with one of the following values :
- * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
- */
-static int
-omap_dma_set_prio_lch(int lch, unsigned char read_prio,
- unsigned char write_prio)
-{
- u32 l;
-
- if (unlikely((lch < 0 || lch >= dma_lch_count))) {
- printk(KERN_ERR "Invalid channel id\n");
- return -EINVAL;
- }
- l = p->dma_read(CCR, lch);
- l &= ~((1 << 6) | (1 << 26));
- if (d->dev_caps & IS_RW_PRIORITY)
- l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
- else
- l |= ((read_prio & 0x1) << 6);
-
- p->dma_write(l, CCR, lch);
-
- return 0;
-}
-
-
/*
* Clears any DMA state so the DMA engine is ready to restart with new buffers
* through omap_start_dma(). Any buffers in flight are discarded.
@@ -926,29 +707,6 @@
* Allows changing the DMA callback function or data. This may be needed if
* the driver shares a single DMA channel for multiple dma triggers.
*/
-int omap_set_dma_callback(int lch,
- void (*callback)(int lch, u16 ch_status, void *data),
- void *data)
-{
- unsigned long flags;
-
- if (lch < 0)
- return -ENODEV;
-
- spin_lock_irqsave(&dma_chan_lock, flags);
- if (dma_chan[lch].dev_id == -1) {
- printk(KERN_ERR "DMA callback for not set for free channel\n");
- spin_unlock_irqrestore(&dma_chan_lock, flags);
- return -EINVAL;
- }
- dma_chan[lch].callback = callback;
- dma_chan[lch].data = data;
- spin_unlock_irqrestore(&dma_chan_lock, flags);
-
- return 0;
-}
-EXPORT_SYMBOL(omap_set_dma_callback);
-
/*
* Returns current physical source address for the given DMA channel.
* If the channel is running the caller must disable interrupts prior calling
@@ -1048,34 +806,6 @@
return 0;
}
-/*
- * lch_queue DMA will start right after lch_head one is finished.
- * For this DMA link to start, you still need to start (see omap_start_dma)
- * the first one. That will fire up the entire queue.
- */
-void omap_dma_link_lch(int lch_head, int lch_queue)
-{
- if (omap_dma_in_1510_mode()) {
- if (lch_head == lch_queue) {
- p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
- CCR, lch_head);
- return;
- }
- printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
- BUG();
- return;
- }
-
- if ((dma_chan[lch_head].dev_id == -1) ||
- (dma_chan[lch_queue].dev_id == -1)) {
- pr_err("omap_dma: trying to link non requested channels\n");
- dump_stack();
- }
-
- dma_chan[lch_head].next_lch = lch_queue;
-}
-EXPORT_SYMBOL(omap_dma_link_lch);
-
/*----------------------------------------------------------------------------*/
#ifdef CONFIG_ARCH_OMAP1
@@ -1136,145 +866,6 @@
#define omap1_dma_irq_handler NULL
#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
-
-static int omap2_dma_handle_ch(int ch)
-{
- u32 status = p->dma_read(CSR, ch);
-
- if (!status) {
- if (printk_ratelimit())
- pr_warn("Spurious DMA IRQ for lch %d\n", ch);
- p->dma_write(1 << ch, IRQSTATUS_L0, ch);
- return 0;
- }
- if (unlikely(dma_chan[ch].dev_id == -1)) {
- if (printk_ratelimit())
- pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
- status, ch);
- return 0;
- }
- if (unlikely(status & OMAP_DMA_DROP_IRQ))
- pr_info("DMA synchronization event drop occurred with device %d\n",
- dma_chan[ch].dev_id);
- if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
- printk(KERN_INFO "DMA transaction error with device %d\n",
- dma_chan[ch].dev_id);
- if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
- u32 ccr;
-
- ccr = p->dma_read(CCR, ch);
- ccr &= ~OMAP_DMA_CCR_EN;
- p->dma_write(ccr, CCR, ch);
- dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
- }
- }
- if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
- printk(KERN_INFO "DMA secure error with device %d\n",
- dma_chan[ch].dev_id);
- if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
- printk(KERN_INFO "DMA misaligned error with device %d\n",
- dma_chan[ch].dev_id);
-
- p->dma_write(status, CSR, ch);
- p->dma_write(1 << ch, IRQSTATUS_L0, ch);
- /* read back the register to flush the write */
- p->dma_read(IRQSTATUS_L0, ch);
-
- /* If the ch is not chained then chain_id will be -1 */
- if (dma_chan[ch].chain_id != -1) {
- int chain_id = dma_chan[ch].chain_id;
- dma_chan[ch].state = DMA_CH_NOTSTARTED;
- if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
- dma_chan[dma_chan[ch].next_linked_ch].state =
- DMA_CH_STARTED;
- if (dma_linked_lch[chain_id].chain_mode ==
- OMAP_DMA_DYNAMIC_CHAIN)
- disable_lnk(ch);
-
- if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
- OMAP_DMA_CHAIN_INCQHEAD(chain_id);
-
- status = p->dma_read(CSR, ch);
- p->dma_write(status, CSR, ch);
- }
-
- if (likely(dma_chan[ch].callback != NULL))
- dma_chan[ch].callback(ch, status, dma_chan[ch].data);
-
- return 0;
-}
-
-/* STATUS register count is from 1-32 while our is 0-31 */
-static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
-{
- u32 val, enable_reg;
- int i;
-
- val = p->dma_read(IRQSTATUS_L0, 0);
- if (val == 0) {
- if (printk_ratelimit())
- printk(KERN_WARNING "Spurious DMA IRQ\n");
- return IRQ_HANDLED;
- }
- enable_reg = p->dma_read(IRQENABLE_L0, 0);
- val &= enable_reg; /* Dispatch only relevant interrupts */
- for (i = 0; i < dma_lch_count && val != 0; i++) {
- if (val & 1)
- omap2_dma_handle_ch(i);
- val >>= 1;
- }
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction omap24xx_dma_irq = {
- .name = "DMA",
- .handler = omap2_dma_irq_handler,
-};
-
-#else
-static struct irqaction omap24xx_dma_irq;
-#endif
-
-/*----------------------------------------------------------------------------*/
-
-/*
- * Note that we are currently using only IRQENABLE_L0 and L1.
- * As the DSP may be using IRQENABLE_L2 and L3, let's not
- * touch those for now.
- */
-void omap_dma_global_context_save(void)
-{
- omap_dma_global_context.dma_irqenable_l0 =
- p->dma_read(IRQENABLE_L0, 0);
- omap_dma_global_context.dma_irqenable_l1 =
- p->dma_read(IRQENABLE_L1, 0);
- omap_dma_global_context.dma_ocp_sysconfig =
- p->dma_read(OCP_SYSCONFIG, 0);
- omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
-}
-
-void omap_dma_global_context_restore(void)
-{
- int ch;
-
- p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
- p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
- OCP_SYSCONFIG, 0);
- p->dma_write(omap_dma_global_context.dma_irqenable_l0,
- IRQENABLE_L0, 0);
- p->dma_write(omap_dma_global_context.dma_irqenable_l1,
- IRQENABLE_L1, 0);
-
- if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
- p->dma_write(0x3 , IRQSTATUS_L0, 0);
-
- for (ch = 0; ch < dma_chan_count; ch++)
- if (dma_chan[ch].dev_id != -1)
- omap_clear_dma(ch);
-}
-
struct omap_system_dma_plat_info *omap_get_plat_info(void)
{
return p;
@@ -1286,7 +877,6 @@
int ch, ret = 0;
int dma_irq;
char irq_name[4];
- int irq_rel;
p = pdev->dev.platform_data;
if (!p) {
@@ -1312,21 +902,9 @@
if (!dma_chan)
return -ENOMEM;
- if (dma_omap2plus()) {
- dma_linked_lch = kcalloc(dma_lch_count,
- sizeof(*dma_linked_lch),
- GFP_KERNEL);
- if (!dma_linked_lch) {
- ret = -ENOMEM;
- goto exit_dma_lch_fail;
- }
- }
-
spin_lock_init(&dma_chan_lock);
for (ch = 0; ch < dma_chan_count; ch++) {
omap_clear_dma(ch);
- if (dma_omap2plus())
- omap2_disable_irq_lch(ch);
dma_chan[ch].dev_id = -1;
dma_chan[ch].next_lch = -1;
@@ -1359,26 +937,6 @@
}
}
- if (d->dev_caps & IS_RW_PRIORITY)
- omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
- DMA_DEFAULT_FIFO_DEPTH, 0);
-
- if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
- strcpy(irq_name, "0");
- dma_irq = platform_get_irq_byname(pdev, irq_name);
- if (dma_irq < 0) {
- dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
- ret = dma_irq;
- goto exit_dma_lch_fail;
- }
- ret = setup_irq(dma_irq, &omap24xx_dma_irq);
- if (ret) {
- dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
- dma_irq, ret);
- goto exit_dma_lch_fail;
- }
- }
-
/* reserve dma channels 0 and 1 in high security devices on 34xx */
if (d->dev_caps & HS_CHANNELS_RESERVED) {
pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
@@ -1389,34 +947,21 @@
return 0;
exit_dma_irq_fail:
- dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
- dma_irq, ret);
- for (irq_rel = 0; irq_rel < ch; irq_rel++) {
- dma_irq = platform_get_irq(pdev, irq_rel);
- free_irq(dma_irq, (void *)(irq_rel + 1));
- }
-
-exit_dma_lch_fail:
return ret;
}
static int omap_system_dma_remove(struct platform_device *pdev)
{
- int dma_irq;
+ int dma_irq, irq_rel = 0;
- if (dma_omap2plus()) {
- char irq_name[4];
- strcpy(irq_name, "0");
- dma_irq = platform_get_irq_byname(pdev, irq_name);
- if (dma_irq >= 0)
- remove_irq(dma_irq, &omap24xx_dma_irq);
- } else {
- int irq_rel = 0;
- for ( ; irq_rel < dma_chan_count; irq_rel++) {
- dma_irq = platform_get_irq(pdev, irq_rel);
- free_irq(dma_irq, (void *)(irq_rel + 1));
- }
+ if (dma_omap2plus())
+ return 0;
+
+ for ( ; irq_rel < dma_chan_count; irq_rel++) {
+ dma_irq = platform_get_irq(pdev, irq_rel);
+ free_irq(dma_irq, (void *)(irq_rel + 1));
}
+
return 0;
}
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 26a531e..734f0be 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -442,6 +442,7 @@
struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
+ const char *label;
int i;
out = readl_relaxed(GPIO_OUT(ochip));
@@ -453,15 +454,10 @@
edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip));
lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip));
- for (i = 0; i < chip->ngpio; i++) {
- const char *label;
+ for_each_requested_gpio(chip, i, label) {
u32 msk;
bool is_out;
- label = gpiochip_is_requested(chip, i);
- if (!label)
- continue;
-
msk = 1 << i;
is_out = !(io_conf & msk);
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index ffb93db..509d482 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -177,12 +177,6 @@
return IRQ_HANDLED;
}
-static struct irqaction orion_timer_irq = {
- .name = "orion_tick",
- .flags = IRQF_TIMER,
- .handler = orion_timer_interrupt
-};
-
void __init
orion_time_set_base(void __iomem *_timer_base)
{
@@ -236,7 +230,9 @@
/*
* Setup clockevent timer (interrupt-driven).
*/
- setup_irq(irq, &orion_timer_irq);
+ if (request_irq(irq, orion_timer_interrupt, IRQF_TIMER, "orion_tick",
+ NULL))
+ pr_err("Failed to request irq %u (orion_tick)\n", irq);
orion_clkevt.cpumask = cpumask_of(0);
clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
}
diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c
index 9a6e492..5634403 100644
--- a/arch/arm/plat-pxa/ssp.c
+++ b/arch/arm/plat-pxa/ssp.c
@@ -89,7 +89,7 @@
ssp->use_count--;
ssp->label = NULL;
} else
- dev_err(&ssp->pdev->dev, "device already free\n");
+ dev_err(ssp->dev, "device already free\n");
mutex_unlock(&ssp_lock);
}
EXPORT_SYMBOL(pxa_ssp_free);
@@ -118,7 +118,7 @@
if (ssp == NULL)
return -ENOMEM;
- ssp->pdev = pdev;
+ ssp->dev = dev;
ssp->clk = devm_clk_get(dev, NULL);
if (IS_ERR(ssp->clk))
diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h
deleted file mode 100644
index 74d1a46..0000000
--- a/arch/arm/plat-samsung/include/plat/adc.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2008 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C ADC driver information
- */
-
-#ifndef __ASM_PLAT_ADC_H
-#define __ASM_PLAT_ADC_H __FILE__
-
-struct s3c_adc_client;
-struct platform_device;
-
-extern int s3c_adc_start(struct s3c_adc_client *client,
- unsigned int channel, unsigned int nr_samples);
-
-extern int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch);
-
-extern struct s3c_adc_client *
- s3c_adc_register(struct platform_device *pdev,
- void (*select)(struct s3c_adc_client *client,
- unsigned selected),
- void (*conv)(struct s3c_adc_client *client,
- unsigned d0, unsigned d1,
- unsigned *samples_left),
- unsigned int is_ts);
-
-extern void s3c_adc_release(struct s3c_adc_client *client);
-
-#endif /* __ASM_PLAT_ADC_H */
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
deleted file mode 100644
index 2c7cf26..0000000
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2006-2009 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C CPU frequency scaling support - core support
- */
-
-#include <plat/cpu-freq.h>
-
-struct seq_file;
-
-#define MAX_BANKS (8)
-#define S3C2412_MAX_IO (8)
-
-/**
- * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
- * @bankcon: The cached version of settings in this structure.
- * @tacp:
- * @tacs: Time from address valid to nCS asserted.
- * @tcos: Time from nCS asserted to nOE or nWE asserted.
- * @tacc: Time that nOE or nWE is asserted.
- * @tcoh: Time nCS is held after nOE or nWE are released.
- * @tcah: Time address is held for after
- * @nwait_en: Whether nWAIT is enabled for this bank.
- *
- * This structure represents the IO timings for a S3C2410 style IO bank
- * used by the CPU frequency support if it needs to change the settings
- * of the IO.
- */
-struct s3c2410_iobank_timing {
- unsigned long bankcon;
- unsigned int tacp;
- unsigned int tacs;
- unsigned int tcos;
- unsigned int tacc;
- unsigned int tcoh; /* nCS hold after nOE/nWE */
- unsigned int tcah; /* Address hold after nCS */
- unsigned char nwait_en; /* nWait enabled for bank. */
-};
-
-/**
- * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
- * @idcy: The idle cycle time between transactions.
- * @wstrd: nCS release to end of read cycle.
- * @wstwr: nCS release to end of write cycle.
- * @wstoen: nCS assertion to nOE assertion time.
- * @wstwen: nCS assertion to nWE assertion time.
- * @wstbrd: Burst ready delay.
- * @smbidcyr: Register cache for smbidcyr value.
- * @smbwstrd: Register cache for smbwstrd value.
- * @smbwstwr: Register cache for smbwstwr value.
- * @smbwstoen: Register cache for smbwstoen value.
- * @smbwstwen: Register cache for smbwstwen value.
- * @smbwstbrd: Register cache for smbwstbrd value.
- *
- * Timing information for a IO bank on an S3C2412 or similar system which
- * uses a PL093 block.
- */
-struct s3c2412_iobank_timing {
- unsigned int idcy;
- unsigned int wstrd;
- unsigned int wstwr;
- unsigned int wstoen;
- unsigned int wstwen;
- unsigned int wstbrd;
-
- /* register cache */
- unsigned char smbidcyr;
- unsigned char smbwstrd;
- unsigned char smbwstwr;
- unsigned char smbwstoen;
- unsigned char smbwstwen;
- unsigned char smbwstbrd;
-};
-
-union s3c_iobank {
- struct s3c2410_iobank_timing *io_2410;
- struct s3c2412_iobank_timing *io_2412;
-};
-
-/**
- * struct s3c_iotimings - Chip IO timings holder
- * @bank: The timings for each IO bank.
- */
-struct s3c_iotimings {
- union s3c_iobank bank[MAX_BANKS];
-};
-
-/**
- * struct s3c_plltab - PLL table information.
- * @vals: List of PLL values.
- * @size: Size of the PLL table @vals.
- */
-struct s3c_plltab {
- struct s3c_pllval *vals;
- int size;
-};
-
-/**
- * struct s3c_cpufreq_config - current cpu frequency configuration
- * @freq: The current settings for the core clocks.
- * @max: Maxium settings, derived from core, board and user settings.
- * @pll: The PLL table entry for the current PLL settings.
- * @divs: The divisor settings for the core clocks.
- * @info: The current core driver information.
- * @board: The information for the board we are running on.
- * @lock_pll: Set if the PLL settings cannot be changed.
- *
- * This is for the core drivers that need to know information about
- * the current settings and values. It should not be needed by any
- * device drivers.
-*/
-struct s3c_cpufreq_config {
- struct s3c_freq freq;
- struct s3c_freq max;
- struct clk *mpll;
- struct cpufreq_frequency_table pll;
- struct s3c_clkdivs divs;
- struct s3c_cpufreq_info *info; /* for core, not drivers */
- struct s3c_cpufreq_board *board;
-
- unsigned int lock_pll:1;
-};
-
-/**
- * struct s3c_cpufreq_info - Information for the CPU frequency driver.
- * @name: The name of this implementation.
- * @max: The maximum frequencies for the system.
- * @latency: Transition latency to give to cpufreq.
- * @locktime_m: The lock-time in uS for the MPLL.
- * @locktime_u: The lock-time in uS for the UPLL.
- * @locttime_bits: The number of bits each LOCKTIME field.
- * @need_pll: Set if this driver needs to change the PLL values to achieve
- * any frequency changes. This is really only need by devices like the
- * S3C2410 where there is no or limited divider between the PLL and the
- * ARMCLK.
- * @get_iotiming: Get the current IO timing data, mainly for use at start.
- * @set_iotiming: Update the IO timings from the cached copies calculated
- * from the @calc_iotiming entry when changing the frequency.
- * @calc_iotiming: Calculate and update the cached copies of the IO timings
- * from the newly calculated frequencies.
- * @calc_freqtable: Calculate (fill in) the given frequency table from the
- * current frequency configuration. If the table passed in is NULL,
- * then the return is the number of elements to be filled for allocation
- * of the table.
- * @set_refresh: Set the memory refresh configuration.
- * @set_fvco: Set the PLL frequencies.
- * @set_divs: Update the clock divisors.
- * @calc_divs: Calculate the clock divisors.
- */
-struct s3c_cpufreq_info {
- const char *name;
- struct s3c_freq max;
-
- unsigned int latency;
-
- unsigned int locktime_m;
- unsigned int locktime_u;
- unsigned char locktime_bits;
-
- unsigned int need_pll:1;
-
- /* driver routines */
-
- int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *timings);
-
- void (*set_iotiming)(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *timings);
-
- int (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *timings);
-
- int (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
- struct cpufreq_frequency_table *t,
- size_t table_size);
-
- void (*debug_io_show)(struct seq_file *seq,
- struct s3c_cpufreq_config *cfg,
- union s3c_iobank *iob);
-
- void (*set_refresh)(struct s3c_cpufreq_config *cfg);
- void (*set_fvco)(struct s3c_cpufreq_config *cfg);
- void (*set_divs)(struct s3c_cpufreq_config *cfg);
- int (*calc_divs)(struct s3c_cpufreq_config *cfg);
-};
-
-extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
-
-extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
- unsigned int plls_no);
-
-/* exports and utilities for debugfs */
-extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
-extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
-
-#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
-#define s3c_cpufreq_debugfs_call(x) x
-#else
-#define s3c_cpufreq_debugfs_call(x) NULL
-#endif
-
-/* Useful utility functions. */
-
-extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
-
-/* S3C2410 and compatible exported functions */
-
-extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
-extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
-
-#ifdef CONFIG_S3C2410_IOTIMING
-extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
- struct s3c_cpufreq_config *cfg,
- union s3c_iobank *iob);
-
-extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *iot);
-
-extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *timings);
-
-extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *iot);
-#else
-#define s3c2410_iotiming_debugfs NULL
-#define s3c2410_iotiming_calc NULL
-#define s3c2410_iotiming_get NULL
-#define s3c2410_iotiming_set NULL
-#endif /* CONFIG_S3C2410_IOTIMING */
-
-/* S3C2412 compatible routines */
-
-#ifdef CONFIG_S3C2412_IOTIMING
-extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
- struct s3c_cpufreq_config *cfg,
- union s3c_iobank *iob);
-
-extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *timings);
-
-extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *iot);
-
-extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
- struct s3c_iotimings *iot);
-#else
-#define s3c2412_iotiming_debugfs NULL
-#define s3c2412_iotiming_calc NULL
-#define s3c2412_iotiming_get NULL
-#define s3c2412_iotiming_set NULL
-#endif /* CONFIG_S3C2412_IOTIMING */
-
-#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG
-#define s3c_freq_dbg(x...) printk(KERN_INFO x)
-#else
-#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
-#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */
-
-#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG
-#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
-#else
-#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
-#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */
-
-static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
- int index, size_t table_size,
- unsigned int freq)
-{
- if (index < 0)
- return index;
-
- if (table) {
- if (index >= table_size)
- return -ENOMEM;
-
- s3c_freq_dbg("%s: { %d = %u kHz }\n",
- __func__, index, freq);
-
- table[index].driver_data = index;
- table[index].frequency = freq;
- }
-
- return index + 1;
-}
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h
deleted file mode 100644
index 558892b..0000000
--- a/arch/arm/plat-samsung/include/plat/cpu-freq.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2006-2007 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C CPU frequency scaling support - driver and board
- */
-
-#include <linux/cpufreq.h>
-
-struct s3c_cpufreq_info;
-struct s3c_cpufreq_board;
-struct s3c_iotimings;
-
-/**
- * struct s3c_freq - frequency information (mainly for core drivers)
- * @fclk: The FCLK frequency in Hz.
- * @armclk: The ARMCLK frequency in Hz.
- * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
- * @hclk: The HCLK frequency in Hz.
- * @pclk: The PCLK frequency in Hz.
- *
- * This contains the frequency information about the current configuration
- * mainly for the core drivers to ensure we do not end up passing about
- * a large number of parameters.
- *
- * The @hclk_tns field is a useful cache for the parts of the drivers that
- * need to calculate IO timings and suchlike.
- */
-struct s3c_freq {
- unsigned long fclk;
- unsigned long armclk;
- unsigned long hclk_tns; /* in 10ths of ns */
- unsigned long hclk;
- unsigned long pclk;
-};
-
-/**
- * struct s3c_cpufreq_freqs - s3c cpufreq notification information.
- * @freqs: The cpufreq setting information.
- * @old: The old clock settings.
- * @new: The new clock settings.
- * @pll_changing: Set if the PLL is changing.
- *
- * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the
- * notification can use this information that is not provided by just
- * having the core frequency alone.
- *
- * The pll_changing flag is used to indicate if the PLL itself is
- * being set during this change. This is important as the clocks
- * will temporarily be set to the XTAL clock during this time, so
- * drivers may want to close down their output during this time.
- *
- * Note, this is not being used by any current drivers and therefore
- * may be removed in the future.
- */
-struct s3c_cpufreq_freqs {
- struct cpufreq_freqs freqs;
- struct s3c_freq old;
- struct s3c_freq new;
-
- unsigned int pll_changing:1;
-};
-
-#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
-
-/**
- * struct s3c_clkdivs - clock divisor information
- * @p_divisor: Divisor from FCLK to PCLK.
- * @h_divisor: Divisor from FCLK to HCLK.
- * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
- * @dvs: Non-zero if using DVS mode for ARMCLK.
- *
- * Divisor settings for the core clocks.
- */
-struct s3c_clkdivs {
- int p_divisor;
- int h_divisor;
- int arm_divisor;
- unsigned char dvs;
-};
-
-#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
-
-/**
- * struct s3c_pllval - PLL value entry.
- * @freq: The frequency for this entry in Hz.
- * @pll_reg: The PLL register setting for this PLL value.
- */
-struct s3c_pllval {
- unsigned long freq;
- unsigned long pll_reg;
-};
-
-/**
- * struct s3c_cpufreq_board - per-board cpu frequency informatin
- * @refresh: The SDRAM refresh period in nanoseconds.
- * @auto_io: Set if the IO timing settings should be generated from the
- * initialisation time hardware registers.
- * @need_io: Set if the board has external IO on any of the chipselect
- * lines that will require the hardware timing registers to be
- * updated on a clock change.
- * @max: The maxium frequency limits for the system. Any field that
- * is left at zero will use the CPU's settings.
- *
- * This contains the board specific settings that affect how the CPU
- * drivers chose settings. These include the memory refresh and IO
- * timing information.
- *
- * Registration depends on the driver being used, the ARMCLK only
- * implementation does not currently need this but the older style
- * driver requires this to be available.
- */
-struct s3c_cpufreq_board {
- unsigned int refresh;
- unsigned int auto_io:1; /* automatically init io timings. */
- unsigned int need_io:1; /* set if needs io timing support. */
-
- /* any non-zero field in here is taken as an upper limit. */
- struct s3c_freq max; /* frequency limits */
-};
-
-/* Things depending on frequency scaling. */
-#ifdef CONFIG_ARM_S3C_CPUFREQ
-#define __init_or_cpufreq
-#else
-#define __init_or_cpufreq __init
-#endif
-
-/* Board functions */
-
-#ifdef CONFIG_ARM_S3C_CPUFREQ
-extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
-#else
-
-static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
-{
- return 0;
-}
-#endif /* CONFIG_ARM_S3C_CPUFREQ */
diff --git a/arch/arm/plat-samsung/include/plat/fb-s3c2410.h b/arch/arm/plat-samsung/include/plat/fb-s3c2410.h
deleted file mode 100644
index 614240d..0000000
--- a/arch/arm/plat-samsung/include/plat/fb-s3c2410.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- * Inspired by pxafb.h
-*/
-
-#ifndef __ASM_PLAT_FB_S3C2410_H
-#define __ASM_PLAT_FB_S3C2410_H __FILE__
-
-struct s3c2410fb_hw {
- unsigned long lcdcon1;
- unsigned long lcdcon2;
- unsigned long lcdcon3;
- unsigned long lcdcon4;
- unsigned long lcdcon5;
-};
-
-/* LCD description */
-struct s3c2410fb_display {
- /* LCD type */
- unsigned type;
-
- /* Screen size */
- unsigned short width;
- unsigned short height;
-
- /* Screen info */
- unsigned short xres;
- unsigned short yres;
- unsigned short bpp;
-
- unsigned pixclock; /* pixclock in picoseconds */
- unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */
- unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
- unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */
- unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */
- unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */
- unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */
-
- /* lcd configuration registers */
- unsigned long lcdcon5;
-};
-
-struct s3c2410fb_mach_info {
-
- struct s3c2410fb_display *displays; /* attached displays info */
- unsigned num_displays; /* number of defined displays */
- unsigned default_display;
-
- /* GPIOs */
-
- unsigned long gpcup;
- unsigned long gpcup_mask;
- unsigned long gpccon;
- unsigned long gpccon_mask;
- unsigned long gpdup;
- unsigned long gpdup_mask;
- unsigned long gpdcon;
- unsigned long gpdcon_mask;
-
- /* lpc3600 control register */
- unsigned long lpcsel;
-};
-
-extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
-
-#endif /* __ASM_PLAT_FB_S3C2410_H */
diff --git a/arch/arm/plat-samsung/include/plat/pm-common.h b/arch/arm/plat-samsung/include/plat/pm-common.h
deleted file mode 100644
index 1268bae..0000000
--- a/arch/arm/plat-samsung/include/plat/pm-common.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2013 Samsung Electronics Co., Ltd.
- * Tomasz Figa <t.figa@samsung.com>
- * Copyright (c) 2004 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Written by Ben Dooks, <ben@simtec.co.uk>
- */
-
-#ifndef __PLAT_SAMSUNG_PM_COMMON_H
-#define __PLAT_SAMSUNG_PM_COMMON_H __FILE__
-
-#include <linux/irq.h>
-
-/* sleep save info */
-
-/**
- * struct sleep_save - save information for shared peripherals.
- * @reg: Pointer to the register to save.
- * @val: Holder for the value saved from reg.
- *
- * This describes a list of registers which is used by the pm core and
- * other subsystem to save and restore register values over suspend.
- */
-struct sleep_save {
- void __iomem *reg;
- unsigned long val;
-};
-
-#define SAVE_ITEM(x) \
- { .reg = (x) }
-
-/* helper functions to save/restore lists of registers. */
-
-extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
-extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count);
-extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count);
-
-/* PM debug functions */
-
-/**
- * struct pm_uart_save - save block for core UART
- * @ulcon: Save value for S3C2410_ULCON
- * @ucon: Save value for S3C2410_UCON
- * @ufcon: Save value for S3C2410_UFCON
- * @umcon: Save value for S3C2410_UMCON
- * @ubrdiv: Save value for S3C2410_UBRDIV
- *
- * Save block for UART registers to be held over sleep and restored if they
- * are needed (say by debug).
-*/
-struct pm_uart_save {
- u32 ulcon;
- u32 ucon;
- u32 ufcon;
- u32 umcon;
- u32 ubrdiv;
- u32 udivslot;
-};
-
-#ifdef CONFIG_SAMSUNG_PM_DEBUG
-/**
- * s3c_pm_dbg() - low level debug function for use in suspend/resume.
- * @msg: The message to print.
- *
- * This function is used mainly to debug the resume process before the system
- * can rely on printk/console output. It uses the low-level debugging output
- * routine printascii() to do its work.
- */
-extern void s3c_pm_dbg(const char *msg, ...);
-
-/**
- * s3c_pm_debug_init() - suspend/resume low level debug initialization.
- * @base: Virtual base of UART to use for suspend/resume debugging.
- *
- * This function needs to be called before S3C_PMDBG() can be used, to set up
- * UART port base address and configuration.
- */
-extern void s3c_pm_debug_init(void);
-
-#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
-
-extern void s3c_pm_save_uarts(void);
-extern void s3c_pm_restore_uarts(void);
-#else
-#define S3C_PMDBG(fmt...) pr_debug(fmt)
-#define s3c_pm_debug_init() do { } while (0)
-
-static inline void s3c_pm_save_uarts(void) { }
-static inline void s3c_pm_restore_uarts(void) { }
-#endif
-
-/* suspend memory checking */
-
-#ifdef CONFIG_SAMSUNG_PM_CHECK
-extern void s3c_pm_check_prepare(void);
-extern void s3c_pm_check_restore(void);
-extern void s3c_pm_check_cleanup(void);
-extern void s3c_pm_check_store(void);
-#else
-#define s3c_pm_check_prepare() do { } while (0)
-#define s3c_pm_check_restore() do { } while (0)
-#define s3c_pm_check_cleanup() do { } while (0)
-#define s3c_pm_check_store() do { } while (0)
-#endif
-
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/regs-spi.h b/arch/arm/plat-samsung/include/plat/regs-spi.h
deleted file mode 100644
index 6078443..0000000
--- a/arch/arm/plat-samsung/include/plat/regs-spi.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2004 Fetron GmbH
- *
- * S3C2410 SPI register definition
- */
-
-#ifndef __ASM_ARCH_REGS_SPI_H
-#define __ASM_ARCH_REGS_SPI_H
-
-#define S3C2410_SPI1 (0x20)
-#define S3C2412_SPI1 (0x100)
-
-#define S3C2410_SPCON (0x00)
-
-#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */
-#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */
-#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */
-#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */
-#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */
-#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */
-#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */
-
-#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */
-#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */
-
-#define S3C2410_SPSTA (0x04)
-
-#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */
-#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */
-#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */
-#define S3C2412_SPSTA_READY_ORG (1 << 3)
-
-#define S3C2410_SPPIN (0x08)
-
-#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */
-#define S3C2410_SPPIN_RESERVED (1 << 1)
-#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */
-
-#define S3C2410_SPPRE (0x0C)
-#define S3C2410_SPTDAT (0x10)
-#define S3C2410_SPRDAT (0x14)
-
-#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-udc.h b/arch/arm/plat-samsung/include/plat/regs-udc.h
deleted file mode 100644
index d8d2eea..0000000
--- a/arch/arm/plat-samsung/include/plat/regs-udc.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
- */
-
-#ifndef __ASM_ARCH_REGS_UDC_H
-#define __ASM_ARCH_REGS_UDC_H
-
-#define S3C2410_USBDREG(x) (x)
-
-#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
-#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
-#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
-
-#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
-#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
-
-#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
-
-#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
-#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
-
-#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
-#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
-#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
-#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
-#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
-
-#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
-#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
-#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
-#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
-#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
-#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
-
-#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
-#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
-#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
-#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
-#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
-#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
-
-#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
-#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
-#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
-#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
-#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
-#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
-
-#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
-#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
-#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
-#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
-#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
-#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
-
-#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
-
-/* indexed registers */
-
-#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
-
-#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
-
-#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
-#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
-
-#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
-#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
-#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
-#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
-
-#define S3C2410_UDC_FUNCADDR_UPDATE (1 << 7)
-
-#define S3C2410_UDC_PWR_ISOUP (1 << 7) /* R/W */
-#define S3C2410_UDC_PWR_RESET (1 << 3) /* R */
-#define S3C2410_UDC_PWR_RESUME (1 << 2) /* R/W */
-#define S3C2410_UDC_PWR_SUSPEND (1 << 1) /* R */
-#define S3C2410_UDC_PWR_ENSUSPEND (1 << 0) /* R/W */
-
-#define S3C2410_UDC_PWR_DEFAULT (0x00)
-
-#define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */
-#define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */
-#define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */
-#define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */
-#define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */
-
-#define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */
-#define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */
-#define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */
-
-#define S3C2410_UDC_INTE_EP4 (1 << 4) /* R/W */
-#define S3C2410_UDC_INTE_EP3 (1 << 3) /* R/W */
-#define S3C2410_UDC_INTE_EP2 (1 << 2) /* R/W */
-#define S3C2410_UDC_INTE_EP1 (1 << 1) /* R/W */
-#define S3C2410_UDC_INTE_EP0 (1 << 0) /* R/W */
-
-#define S3C2410_UDC_USBINTE_RESET (1 << 2) /* R/W */
-#define S3C2410_UDC_USBINTE_SUSPEND (1 << 0) /* R/W */
-
-#define S3C2410_UDC_INDEX_EP0 (0x00)
-#define S3C2410_UDC_INDEX_EP1 (0x01)
-#define S3C2410_UDC_INDEX_EP2 (0x02)
-#define S3C2410_UDC_INDEX_EP3 (0x03)
-#define S3C2410_UDC_INDEX_EP4 (0x04)
-
-#define S3C2410_UDC_ICSR1_CLRDT (1 << 6) /* R/W */
-#define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */
-#define S3C2410_UDC_ICSR1_SENDSTL (1 << 4) /* R/W */
-#define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */
-#define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */
-#define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */
-
-#define S3C2410_UDC_ICSR2_AUTOSET (1 << 7) /* R/W */
-#define S3C2410_UDC_ICSR2_ISO (1 << 6) /* R/W */
-#define S3C2410_UDC_ICSR2_MODEIN (1 << 5) /* R/W */
-#define S3C2410_UDC_ICSR2_DMAIEN (1 << 4) /* R/W */
-
-#define S3C2410_UDC_OCSR1_CLRDT (1 << 7) /* R/W */
-#define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */
-#define S3C2410_UDC_OCSR1_SENDSTL (1 << 5) /* R/W */
-#define S3C2410_UDC_OCSR1_FFLUSH (1 << 4) /* R/W */
-#define S3C2410_UDC_OCSR1_DERROR (1 << 3) /* R */
-#define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */
-#define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */
-
-#define S3C2410_UDC_OCSR2_AUTOCLR (1 << 7) /* R/W */
-#define S3C2410_UDC_OCSR2_ISO (1 << 6) /* R/W */
-#define S3C2410_UDC_OCSR2_DMAIEN (1 << 5) /* R/W */
-
-#define S3C2410_UDC_EP0_CSR_OPKRDY (1 << 0)
-#define S3C2410_UDC_EP0_CSR_IPKRDY (1 << 1)
-#define S3C2410_UDC_EP0_CSR_SENTSTL (1 << 2)
-#define S3C2410_UDC_EP0_CSR_DE (1 << 3)
-#define S3C2410_UDC_EP0_CSR_SE (1 << 4)
-#define S3C2410_UDC_EP0_CSR_SENDSTL (1 << 5)
-#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1 << 6)
-#define S3C2410_UDC_EP0_CSR_SSE (1 << 7)
-
-#define S3C2410_UDC_MAXP_8 (1 << 0)
-#define S3C2410_UDC_MAXP_16 (1 << 1)
-#define S3C2410_UDC_MAXP_32 (1 << 2)
-#define S3C2410_UDC_MAXP_64 (1 << 3)
-
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h
deleted file mode 100644
index d16eefe..0000000
--- a/arch/arm/plat-samsung/include/plat/samsung-time.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright 2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * Header file for samsung s3c and s5p time support
- */
-
-#ifndef __ASM_PLAT_SAMSUNG_TIME_H
-#define __ASM_PLAT_SAMSUNG_TIME_H __FILE__
-
-/* SAMSUNG HR-Timer Clock mode */
-enum samsung_timer_mode {
- SAMSUNG_PWM0,
- SAMSUNG_PWM1,
- SAMSUNG_PWM2,
- SAMSUNG_PWM3,
- SAMSUNG_PWM4,
-};
-
-extern void __init samsung_set_timer_source(enum samsung_timer_mode event,
- enum samsung_timer_mode source);
-
-extern void __init samsung_timer_init(void);
-
-#endif /* __ASM_PLAT_SAMSUNG_TIME_H */
diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c
deleted file mode 100644
index cd2c02c..0000000
--- a/arch/arm/plat-samsung/pm-check.c
+++ /dev/null
@@ -1,233 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// originally in linux/arch/arm/plat-s3c24xx/pm.c
-//
-// Copyright (c) 2004-2008 Simtec Electronics
-// http://armlinux.simtec.co.uk
-// Ben Dooks <ben@simtec.co.uk>
-//
-// S3C Power Mangament - suspend/resume memory corruption check.
-
-#include <linux/kernel.h>
-#include <linux/suspend.h>
-#include <linux/init.h>
-#include <linux/crc32.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-
-#include <plat/pm-common.h>
-
-#if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1
-#error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value
-#endif
-
-/* suspend checking code...
- *
- * this next area does a set of crc checks over all the installed
- * memory, so the system can verify if the resume was ok.
- *
- * CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
- * increasing it will mean that the area corrupted will be less easy to spot,
- * and reducing the size will cause the CRC save area to grow
-*/
-
-#define CHECK_CHUNKSIZE (CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE * 1024)
-
-static u32 crc_size; /* size needed for the crc block */
-static u32 *crcs; /* allocated over suspend/resume */
-
-typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
-
-/* s3c_pm_run_res
- *
- * go through the given resource list, and look for system ram
-*/
-
-static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
-{
- while (ptr != NULL) {
- if (ptr->child != NULL)
- s3c_pm_run_res(ptr->child, fn, arg);
-
- if ((ptr->flags & IORESOURCE_SYSTEM_RAM)
- == IORESOURCE_SYSTEM_RAM) {
- S3C_PMDBG("Found system RAM at %08lx..%08lx\n",
- (unsigned long)ptr->start,
- (unsigned long)ptr->end);
- arg = (fn)(ptr, arg);
- }
-
- ptr = ptr->sibling;
- }
-}
-
-static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg)
-{
- s3c_pm_run_res(&iomem_resource, fn, arg);
-}
-
-static u32 *s3c_pm_countram(struct resource *res, u32 *val)
-{
- u32 size = (u32)resource_size(res);
-
- size += CHECK_CHUNKSIZE-1;
- size /= CHECK_CHUNKSIZE;
-
- S3C_PMDBG("Area %08lx..%08lx, %d blocks\n",
- (unsigned long)res->start, (unsigned long)res->end, size);
-
- *val += size * sizeof(u32);
- return val;
-}
-
-/* s3c_pm_prepare_check
- *
- * prepare the necessary information for creating the CRCs. This
- * must be done before the final save, as it will require memory
- * allocating, and thus touching bits of the kernel we do not
- * know about.
-*/
-
-void s3c_pm_check_prepare(void)
-{
- crc_size = 0;
-
- s3c_pm_run_sysram(s3c_pm_countram, &crc_size);
-
- S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size);
-
- crcs = kmalloc(crc_size+4, GFP_KERNEL);
- if (crcs == NULL)
- printk(KERN_ERR "Cannot allocated CRC save area\n");
-}
-
-static u32 *s3c_pm_makecheck(struct resource *res, u32 *val)
-{
- unsigned long addr, left;
-
- for (addr = res->start; addr < res->end;
- addr += CHECK_CHUNKSIZE) {
- left = res->end - addr;
-
- if (left > CHECK_CHUNKSIZE)
- left = CHECK_CHUNKSIZE;
-
- *val = crc32_le(~0, phys_to_virt(addr), left);
- val++;
- }
-
- return val;
-}
-
-/* s3c_pm_check_store
- *
- * compute the CRC values for the memory blocks before the final
- * sleep.
-*/
-
-void s3c_pm_check_store(void)
-{
- if (crcs != NULL)
- s3c_pm_run_sysram(s3c_pm_makecheck, crcs);
-}
-
-/* in_region
- *
- * return TRUE if the area defined by ptr..ptr+size contains the
- * what..what+whatsz
-*/
-
-static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
-{
- if ((what+whatsz) < ptr)
- return 0;
-
- if (what > (ptr+size))
- return 0;
-
- return 1;
-}
-
-/**
- * s3c_pm_runcheck() - helper to check a resource on restore.
- * @res: The resource to check
- * @vak: Pointer to list of CRC32 values to check.
- *
- * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this
- * function runs the given memory resource checking it against the stored
- * CRC to ensure that memory is restored. The function tries to skip as
- * many of the areas used during the suspend process.
- */
-static u32 *s3c_pm_runcheck(struct resource *res, u32 *val)
-{
- unsigned long addr;
- unsigned long left;
- void *stkpage;
- void *ptr;
- u32 calc;
-
- stkpage = (void *)((u32)&calc & ~PAGE_MASK);
-
- for (addr = res->start; addr < res->end;
- addr += CHECK_CHUNKSIZE) {
- left = res->end - addr;
-
- if (left > CHECK_CHUNKSIZE)
- left = CHECK_CHUNKSIZE;
-
- ptr = phys_to_virt(addr);
-
- if (in_region(ptr, left, stkpage, 4096)) {
- S3C_PMDBG("skipping %08lx, has stack in\n", addr);
- goto skip_check;
- }
-
- if (in_region(ptr, left, crcs, crc_size)) {
- S3C_PMDBG("skipping %08lx, has crc block in\n", addr);
- goto skip_check;
- }
-
- /* calculate and check the checksum */
-
- calc = crc32_le(~0, ptr, left);
- if (calc != *val) {
- printk(KERN_ERR "Restore CRC error at "
- "%08lx (%08x vs %08x)\n", addr, calc, *val);
-
- S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n",
- addr, calc, *val);
- }
-
- skip_check:
- val++;
- }
-
- return val;
-}
-
-/**
- * s3c_pm_check_restore() - memory check called on resume
- *
- * check the CRCs after the restore event and free the memory used
- * to hold them
-*/
-void s3c_pm_check_restore(void)
-{
- if (crcs != NULL)
- s3c_pm_run_sysram(s3c_pm_runcheck, crcs);
-}
-
-/**
- * s3c_pm_check_cleanup() - free memory resources
- *
- * Free the resources that where allocated by the suspend
- * memory check code. We do this separately from the
- * s3c_pm_check_restore() function as we cannot call any
- * functions that might sleep during that resume.
- */
-void s3c_pm_check_cleanup(void)
-{
- kfree(crcs);
- crcs = NULL;
-}
-
diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c
deleted file mode 100644
index b76b1e9..0000000
--- a/arch/arm/plat-samsung/pm-debug.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (C) 2013 Samsung Electronics Co., Ltd.
-// Tomasz Figa <t.figa@samsung.com>
-// Copyright (C) 2008 Openmoko, Inc.
-// Copyright (C) 2004-2008 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-// http://armlinux.simtec.co.uk/
-//
-// Samsung common power management (suspend to RAM) debug support
-
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/io.h>
-
-#include <asm/mach/map.h>
-
-#include <plat/cpu.h>
-#include <plat/pm-common.h>
-
-#ifdef CONFIG_SAMSUNG_ATAGS
-#include <plat/pm.h>
-#include <mach/pm-core.h>
-#else
-static inline void s3c_pm_debug_init_uart(void) {}
-static inline void s3c_pm_arch_update_uart(void __iomem *regs,
- struct pm_uart_save *save) {}
-#endif
-
-static struct pm_uart_save uart_save;
-
-extern void printascii(const char *);
-
-void s3c_pm_dbg(const char *fmt, ...)
-{
- va_list va;
- char buff[256];
-
- va_start(va, fmt);
- vsnprintf(buff, sizeof(buff), fmt, va);
- va_end(va);
-
- printascii(buff);
-}
-
-void s3c_pm_debug_init(void)
-{
- /* restart uart clocks so we can use them to output */
- s3c_pm_debug_init_uart();
-}
-
-static inline void __iomem *s3c_pm_uart_base(void)
-{
- unsigned long paddr;
- unsigned long vaddr;
-
- debug_ll_addr(&paddr, &vaddr);
-
- return (void __iomem *)vaddr;
-}
-
-void s3c_pm_save_uarts(void)
-{
- void __iomem *regs = s3c_pm_uart_base();
- struct pm_uart_save *save = &uart_save;
-
- save->ulcon = __raw_readl(regs + S3C2410_ULCON);
- save->ucon = __raw_readl(regs + S3C2410_UCON);
- save->ufcon = __raw_readl(regs + S3C2410_UFCON);
- save->umcon = __raw_readl(regs + S3C2410_UMCON);
- save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
-
- if (!soc_is_s3c2410())
- save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
-
- S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
- regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
-}
-
-void s3c_pm_restore_uarts(void)
-{
- void __iomem *regs = s3c_pm_uart_base();
- struct pm_uart_save *save = &uart_save;
-
- s3c_pm_arch_update_uart(regs, save);
-
- __raw_writel(save->ulcon, regs + S3C2410_ULCON);
- __raw_writel(save->ucon, regs + S3C2410_UCON);
- __raw_writel(save->ufcon, regs + S3C2410_UFCON);
- __raw_writel(save->umcon, regs + S3C2410_UMCON);
- __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
-
- if (!soc_is_s3c2410())
- __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
-}
diff --git a/arch/arm/plat-samsung/watchdog-reset.c b/arch/arm/plat-samsung/watchdog-reset.c
deleted file mode 100644
index 71d85ff..0000000
--- a/arch/arm/plat-samsung/watchdog-reset.c
+++ /dev/null
@@ -1,93 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright (c) 2008 Simtec Electronics
-// Ben Dooks <ben@simtec.co.uk>
-//
-// Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
-//
-// Watchdog reset support for Samsung SoCs.
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#define S3C2410_WTCON 0x00
-#define S3C2410_WTDAT 0x04
-#define S3C2410_WTCNT 0x08
-
-#define S3C2410_WTCON_ENABLE (1 << 5)
-#define S3C2410_WTCON_DIV16 (0 << 3)
-#define S3C2410_WTCON_RSTEN (1 << 0)
-#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
-
-static void __iomem *wdt_base;
-static struct clk *wdt_clock;
-
-void samsung_wdt_reset(void)
-{
- if (!wdt_base) {
- pr_err("%s: wdt reset not initialized\n", __func__);
- /* delay to allow the serial port to show the message */
- mdelay(50);
- return;
- }
-
- if (!IS_ERR(wdt_clock))
- clk_prepare_enable(wdt_clock);
-
- /* disable watchdog, to be safe */
- __raw_writel(0, wdt_base + S3C2410_WTCON);
-
- /* put initial values into count and data */
- __raw_writel(0x80, wdt_base + S3C2410_WTCNT);
- __raw_writel(0x80, wdt_base + S3C2410_WTDAT);
-
- /* set the watchdog to go and reset... */
- __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
- S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
- wdt_base + S3C2410_WTCON);
-
- /* wait for reset to assert... */
- mdelay(500);
-
- pr_err("Watchdog reset failed to assert reset\n");
-
- /* delay to allow the serial port to show the message */
- mdelay(50);
-}
-
-#ifdef CONFIG_OF
-static const struct of_device_id s3c2410_wdt_match[] = {
- { .compatible = "samsung,s3c2410-wdt" },
- { .compatible = "samsung,s3c6410-wdt" },
- {},
-};
-
-void __init samsung_wdt_reset_of_init(void)
-{
- struct device_node *np;
-
- np = of_find_matching_node(NULL, s3c2410_wdt_match);
- if (!np) {
- pr_err("%s: failed to find watchdog node\n", __func__);
- return;
- }
-
- wdt_base = of_iomap(np, 0);
- if (!wdt_base) {
- pr_err("%s: failed to map watchdog registers\n", __func__);
- return;
- }
-
- wdt_clock = of_clk_get(np, 0);
-}
-#endif
-
-void __init samsung_wdt_reset_init(void __iomem *base)
-{
- wdt_base = base;
- wdt_clock = clk_get(NULL, "watchdog");
-}
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
deleted file mode 100644
index 748238f..0000000
--- a/arch/arm/plat-versatile/Kconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-if PLAT_VERSATILE
-
-config PLAT_VERSATILE_SCHED_CLOCK
- bool
-
-endif
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index e856f0a..5de44a5 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,6 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
-obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/plat-versatile/include/plat/sched_clock.h b/arch/arm/plat-versatile/include/plat/sched_clock.h
deleted file mode 100644
index 83fdaef..0000000
--- a/arch/arm/plat-versatile/include/plat/sched_clock.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef ARM_PLAT_SCHED_CLOCK_H
-#define ARM_PLAT_SCHED_CLOCK_H
-
-void versatile_sched_clock_init(void __iomem *, unsigned long);
-
-#endif
diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatile/sched-clock.c
deleted file mode 100644
index ecb7913..0000000
--- a/arch/arm/plat-versatile/sched-clock.c
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * linux/arch/arm/plat-versatile/sched-clock.c
- *
- * Copyright (C) 1999 - 2003 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- */
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/sched_clock.h>
-
-#include <plat/sched_clock.h>
-
-static void __iomem *ctr;
-
-static u64 notrace versatile_read_sched_clock(void)
-{
- if (ctr)
- return readl(ctr);
-
- return 0;
-}
-
-void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate)
-{
- ctr = reg;
- sched_clock_register(versatile_read_sched_clock, 32, rate);
-}
diff --git a/arch/arm/probes/decode.c b/arch/arm/probes/decode.c
index fe81a9c..c84053a 100644
--- a/arch/arm/probes/decode.c
+++ b/arch/arm/probes/decode.c
@@ -307,7 +307,7 @@
case REG_TYPE_NOPCWB:
if (!is_writeback(insn))
break; /* No writeback, so any register is OK */
- /* fall through... */
+ fallthrough;
case REG_TYPE_NOPC:
case REG_TYPE_NOPCX:
/* Reject PC (R15) */
diff --git a/arch/arm/probes/kprobes/core.c b/arch/arm/probes/kprobes/core.c
index 90b5bc7..e513d8a 100644
--- a/arch/arm/probes/kprobes/core.c
+++ b/arch/arm/probes/kprobes/core.c
@@ -280,7 +280,7 @@
/* A nested probe was hit in FIQ, it is a BUG */
pr_warn("Unrecoverable kprobe detected.\n");
dump_kprobe(p);
- /* fall through */
+ fallthrough;
default:
/* impossible cases */
BUG();
@@ -413,87 +413,15 @@
/* Called from kretprobe_trampoline */
static __used __kprobes void *trampoline_handler(struct pt_regs *regs)
{
- struct kretprobe_instance *ri = NULL;
- struct hlist_head *head, empty_rp;
- struct hlist_node *tmp;
- unsigned long flags, orig_ret_address = 0;
- unsigned long trampoline_address = (unsigned long)&kretprobe_trampoline;
- kprobe_opcode_t *correct_ret_addr = NULL;
-
- INIT_HLIST_HEAD(&empty_rp);
- kretprobe_hash_lock(current, &head, &flags);
-
- /*
- * It is possible to have multiple instances associated with a given
- * task either because multiple functions in the call path have
- * a return probe installed on them, and/or more than one return
- * probe was registered for a target function.
- *
- * We can handle this because:
- * - instances are always inserted at the head of the list
- * - when multiple return probes are registered for the same
- * function, the first instance's ret_addr will point to the
- * real return address, and all the rest will point to
- * kretprobe_trampoline
- */
- hlist_for_each_entry_safe(ri, tmp, head, hlist) {
- if (ri->task != current)
- /* another task is sharing our hash bucket */
- continue;
-
- orig_ret_address = (unsigned long)ri->ret_addr;
-
- if (orig_ret_address != trampoline_address)
- /*
- * This is the real return address. Any other
- * instances associated with this task are for
- * other calls deeper on the call stack
- */
- break;
- }
-
- kretprobe_assert(ri, orig_ret_address, trampoline_address);
-
- correct_ret_addr = ri->ret_addr;
- hlist_for_each_entry_safe(ri, tmp, head, hlist) {
- if (ri->task != current)
- /* another task is sharing our hash bucket */
- continue;
-
- orig_ret_address = (unsigned long)ri->ret_addr;
- if (ri->rp && ri->rp->handler) {
- __this_cpu_write(current_kprobe, &ri->rp->kp);
- get_kprobe_ctlblk()->kprobe_status = KPROBE_HIT_ACTIVE;
- ri->ret_addr = correct_ret_addr;
- ri->rp->handler(ri, regs);
- __this_cpu_write(current_kprobe, NULL);
- }
-
- recycle_rp_inst(ri, &empty_rp);
-
- if (orig_ret_address != trampoline_address)
- /*
- * This is the real return address. Any other
- * instances associated with this task are for
- * other calls deeper on the call stack
- */
- break;
- }
-
- kretprobe_hash_unlock(current, &flags);
-
- hlist_for_each_entry_safe(ri, tmp, &empty_rp, hlist) {
- hlist_del(&ri->hlist);
- kfree(ri);
- }
-
- return (void *)orig_ret_address;
+ return (void *)kretprobe_trampoline_handler(regs, &kretprobe_trampoline,
+ (void *)regs->ARM_fp);
}
void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
struct pt_regs *regs)
{
ri->ret_addr = (kprobe_opcode_t *)regs->ARM_lr;
+ ri->fp = (void *)regs->ARM_fp;
/* Replace the return addr with trampoline addr. */
regs->ARM_lr = (unsigned long)&kretprobe_trampoline;
@@ -534,7 +462,7 @@
#endif /* !CONFIG_THUMB2_KERNEL */
-int __init arch_init_kprobes()
+int __init arch_init_kprobes(void)
{
arm_probes_decode_init();
#ifdef CONFIG_THUMB2_KERNEL
diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl
index 6da7dc4..d056a54 100644
--- a/arch/arm/tools/syscall.tbl
+++ b/arch/arm/tools/syscall.tbl
@@ -162,7 +162,7 @@
146 common writev sys_writev
147 common getsid sys_getsid
148 common fdatasync sys_fdatasync
-149 common _sysctl sys_sysctl
+149 common _sysctl sys_ni_syscall
150 common mlock sys_mlock
151 common munlock sys_munlock
152 common mlockall sys_mlockall
@@ -449,3 +449,8 @@
433 common fspick sys_fspick
434 common pidfd_open sys_pidfd_open
435 common clone3 sys_clone3
+436 common close_range sys_close_range
+437 common openat2 sys_openat2
+438 common pidfd_getfd sys_pidfd_getfd
+439 common faccessat2 sys_faccessat2
+440 common process_madvise sys_process_madvise
diff --git a/arch/arm/vdso/.gitignore b/arch/arm/vdso/.gitignore
index 6b47f6e..dfa06f5 100644
--- a/arch/arm/vdso/.gitignore
+++ b/arch/arm/vdso/.gitignore
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
vdso.lds
vdso.so.raw
vdsomunge
diff --git a/arch/arm/vdso/Makefile b/arch/arm/vdso/Makefile
index 87b7769..150ce6e 100644
--- a/arch/arm/vdso/Makefile
+++ b/arch/arm/vdso/Makefile
@@ -1,19 +1,25 @@
# SPDX-License-Identifier: GPL-2.0
-hostprogs-y := vdsomunge
-obj-vdso := vgettimeofday.o datapage.o
+# Absolute relocation type $(ARCH_REL_TYPE_ABS) needs to be defined before
+# the inclusion of generic Makefile.
+ARCH_REL_TYPE_ABS := R_ARM_JUMP_SLOT|R_ARM_GLOB_DAT|R_ARM_ABS32
+include $(srctree)/lib/vdso/Makefile
+
+hostprogs := vdsomunge
+
+obj-vdso := vgettimeofday.o datapage.o note.o
# Build rules
targets := $(obj-vdso) vdso.so vdso.so.dbg vdso.so.raw vdso.lds
obj-vdso := $(addprefix $(obj)/, $(obj-vdso))
ccflags-y := -fPIC -fno-common -fno-builtin -fno-stack-protector
-ccflags-y += -DDISABLE_BRANCH_PROFILING
+ccflags-y += -DDISABLE_BRANCH_PROFILING -DBUILD_VDSO32
ldflags-$(CONFIG_CPU_ENDIAN_BE8) := --be8
ldflags-y := -Bsymbolic --no-undefined -soname=linux-vdso.so.1 \
-z max-page-size=4096 -nostdlib -shared $(ldflags-y) \
- --hash-style=sysv --build-id \
+ --hash-style=sysv --build-id=sha1 \
-T
obj-$(CONFIG_VDSO) += vdso.o
@@ -23,8 +29,12 @@
CFLAGS_REMOVE_vdso.o = -pg
# Force -O2 to avoid libgcc dependencies
-CFLAGS_REMOVE_vgettimeofday.o = -pg -Os
+CFLAGS_REMOVE_vgettimeofday.o = -pg -Os $(GCC_PLUGINS_CFLAGS)
+ifeq ($(c-gettimeofday-y),)
CFLAGS_vgettimeofday.o = -O2
+else
+CFLAGS_vgettimeofday.o = -O2 -include $(c-gettimeofday-y)
+endif
# Disable gcov profiling for VDSO code
GCOV_PROFILE := n
@@ -37,7 +47,7 @@
# Link rule for the .so file
$(obj)/vdso.so.raw: $(obj)/vdso.lds $(obj-vdso) FORCE
- $(call if_changed,ld)
+ $(call if_changed,vdsold_and_vdso_check)
$(obj)/vdso.so.dbg: $(obj)/vdso.so.raw $(obj)/vdsomunge FORCE
$(call if_changed,vdsomunge)
@@ -47,6 +57,10 @@
$(obj)/%.so: $(obj)/%.so.dbg FORCE
$(call if_changed,objcopy)
+# Actual build commands
+quiet_cmd_vdsold_and_vdso_check = LD $@
+ cmd_vdsold_and_vdso_check = $(cmd_ld); $(cmd_vdso_check)
+
quiet_cmd_vdsomunge = MUNGE $@
cmd_vdsomunge = $(objtree)/$(obj)/vdsomunge $< $@
diff --git a/arch/arm/vdso/note.c b/arch/arm/vdso/note.c
new file mode 100644
index 0000000..eff5bf9
--- /dev/null
+++ b/arch/arm/vdso/note.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2012-2018 ARM Limited
+ *
+ * This supplies .note.* sections to go into the PT_NOTE inside the vDSO text.
+ * Here we can supply some information useful to userland.
+ */
+
+#include <linux/uts.h>
+#include <linux/version.h>
+#include <linux/elfnote.h>
+#include <linux/build-salt.h>
+
+ELFNOTE32("Linux", 0, LINUX_VERSION_CODE);
+BUILD_SALT;
diff --git a/arch/arm/vdso/vdso.lds.S b/arch/arm/vdso/vdso.lds.S
index 73cf205..165d1d2 100644
--- a/arch/arm/vdso/vdso.lds.S
+++ b/arch/arm/vdso/vdso.lds.S
@@ -71,6 +71,8 @@
global:
__vdso_clock_gettime;
__vdso_gettimeofday;
+ __vdso_clock_getres;
+ __vdso_clock_gettime64;
local: *;
};
}
diff --git a/arch/arm/vdso/vgettimeofday.c b/arch/arm/vdso/vgettimeofday.c
index d1fdbb1..1976c6f 100644
--- a/arch/arm/vdso/vgettimeofday.c
+++ b/arch/arm/vdso/vgettimeofday.c
@@ -1,259 +1,34 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
+ * ARM userspace implementations of gettimeofday() and similar.
+ *
* Copyright 2015 Mentor Graphics Corporation.
*/
-
-#include <linux/compiler.h>
-#include <linux/hrtimer.h>
#include <linux/time.h>
-#include <asm/barrier.h>
-#include <asm/bug.h>
-#include <asm/cp15.h>
-#include <asm/page.h>
-#include <asm/unistd.h>
-#include <asm/vdso_datapage.h>
+#include <linux/types.h>
-#ifndef CONFIG_AEABI
-#error This code depends on AEABI system call conventions
-#endif
-
-extern struct vdso_data *__get_datapage(void);
-
-static notrace u32 __vdso_read_begin(const struct vdso_data *vdata)
+int __vdso_clock_gettime(clockid_t clock,
+ struct old_timespec32 *ts)
{
- u32 seq;
-repeat:
- seq = READ_ONCE(vdata->seq_count);
- if (seq & 1) {
- cpu_relax();
- goto repeat;
- }
- return seq;
+ return __cvdso_clock_gettime32(clock, ts);
}
-static notrace u32 vdso_read_begin(const struct vdso_data *vdata)
+int __vdso_clock_gettime64(clockid_t clock,
+ struct __kernel_timespec *ts)
{
- u32 seq;
-
- seq = __vdso_read_begin(vdata);
-
- smp_rmb(); /* Pairs with smp_wmb in vdso_write_end */
- return seq;
+ return __cvdso_clock_gettime(clock, ts);
}
-static notrace int vdso_read_retry(const struct vdso_data *vdata, u32 start)
+int __vdso_gettimeofday(struct __kernel_old_timeval *tv,
+ struct timezone *tz)
{
- smp_rmb(); /* Pairs with smp_wmb in vdso_write_begin */
- return vdata->seq_count != start;
+ return __cvdso_gettimeofday(tv, tz);
}
-static notrace long clock_gettime_fallback(clockid_t _clkid,
- struct timespec *_ts)
+int __vdso_clock_getres(clockid_t clock_id,
+ struct old_timespec32 *res)
{
- register struct timespec *ts asm("r1") = _ts;
- register clockid_t clkid asm("r0") = _clkid;
- register long ret asm ("r0");
- register long nr asm("r7") = __NR_clock_gettime;
-
- asm volatile(
- " swi #0\n"
- : "=r" (ret)
- : "r" (clkid), "r" (ts), "r" (nr)
- : "memory");
-
- return ret;
-}
-
-static notrace int do_realtime_coarse(struct timespec *ts,
- struct vdso_data *vdata)
-{
- u32 seq;
-
- do {
- seq = vdso_read_begin(vdata);
-
- ts->tv_sec = vdata->xtime_coarse_sec;
- ts->tv_nsec = vdata->xtime_coarse_nsec;
-
- } while (vdso_read_retry(vdata, seq));
-
- return 0;
-}
-
-static notrace int do_monotonic_coarse(struct timespec *ts,
- struct vdso_data *vdata)
-{
- struct timespec tomono;
- u32 seq;
-
- do {
- seq = vdso_read_begin(vdata);
-
- ts->tv_sec = vdata->xtime_coarse_sec;
- ts->tv_nsec = vdata->xtime_coarse_nsec;
-
- tomono.tv_sec = vdata->wtm_clock_sec;
- tomono.tv_nsec = vdata->wtm_clock_nsec;
-
- } while (vdso_read_retry(vdata, seq));
-
- ts->tv_sec += tomono.tv_sec;
- timespec_add_ns(ts, tomono.tv_nsec);
-
- return 0;
-}
-
-#ifdef CONFIG_ARM_ARCH_TIMER
-
-static notrace u64 get_ns(struct vdso_data *vdata)
-{
- u64 cycle_delta;
- u64 cycle_now;
- u64 nsec;
-
- isb();
- cycle_now = read_sysreg(CNTVCT);
-
- cycle_delta = (cycle_now - vdata->cs_cycle_last) & vdata->cs_mask;
-
- nsec = (cycle_delta * vdata->cs_mult) + vdata->xtime_clock_snsec;
- nsec >>= vdata->cs_shift;
-
- return nsec;
-}
-
-static notrace int do_realtime(struct timespec *ts, struct vdso_data *vdata)
-{
- u64 nsecs;
- u32 seq;
-
- do {
- seq = vdso_read_begin(vdata);
-
- if (!vdata->tk_is_cntvct)
- return -1;
-
- ts->tv_sec = vdata->xtime_clock_sec;
- nsecs = get_ns(vdata);
-
- } while (vdso_read_retry(vdata, seq));
-
- ts->tv_nsec = 0;
- timespec_add_ns(ts, nsecs);
-
- return 0;
-}
-
-static notrace int do_monotonic(struct timespec *ts, struct vdso_data *vdata)
-{
- struct timespec tomono;
- u64 nsecs;
- u32 seq;
-
- do {
- seq = vdso_read_begin(vdata);
-
- if (!vdata->tk_is_cntvct)
- return -1;
-
- ts->tv_sec = vdata->xtime_clock_sec;
- nsecs = get_ns(vdata);
-
- tomono.tv_sec = vdata->wtm_clock_sec;
- tomono.tv_nsec = vdata->wtm_clock_nsec;
-
- } while (vdso_read_retry(vdata, seq));
-
- ts->tv_sec += tomono.tv_sec;
- ts->tv_nsec = 0;
- timespec_add_ns(ts, nsecs + tomono.tv_nsec);
-
- return 0;
-}
-
-#else /* CONFIG_ARM_ARCH_TIMER */
-
-static notrace int do_realtime(struct timespec *ts, struct vdso_data *vdata)
-{
- return -1;
-}
-
-static notrace int do_monotonic(struct timespec *ts, struct vdso_data *vdata)
-{
- return -1;
-}
-
-#endif /* CONFIG_ARM_ARCH_TIMER */
-
-notrace int __vdso_clock_gettime(clockid_t clkid, struct timespec *ts)
-{
- struct vdso_data *vdata;
- int ret = -1;
-
- vdata = __get_datapage();
-
- switch (clkid) {
- case CLOCK_REALTIME_COARSE:
- ret = do_realtime_coarse(ts, vdata);
- break;
- case CLOCK_MONOTONIC_COARSE:
- ret = do_monotonic_coarse(ts, vdata);
- break;
- case CLOCK_REALTIME:
- ret = do_realtime(ts, vdata);
- break;
- case CLOCK_MONOTONIC:
- ret = do_monotonic(ts, vdata);
- break;
- default:
- break;
- }
-
- if (ret)
- ret = clock_gettime_fallback(clkid, ts);
-
- return ret;
-}
-
-static notrace long gettimeofday_fallback(struct timeval *_tv,
- struct timezone *_tz)
-{
- register struct timezone *tz asm("r1") = _tz;
- register struct timeval *tv asm("r0") = _tv;
- register long ret asm ("r0");
- register long nr asm("r7") = __NR_gettimeofday;
-
- asm volatile(
- " swi #0\n"
- : "=r" (ret)
- : "r" (tv), "r" (tz), "r" (nr)
- : "memory");
-
- return ret;
-}
-
-notrace int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
-{
- struct timespec ts;
- struct vdso_data *vdata;
- int ret;
-
- vdata = __get_datapage();
-
- ret = do_realtime(&ts, vdata);
- if (ret)
- return gettimeofday_fallback(tv, tz);
-
- if (tv) {
- tv->tv_sec = ts.tv_sec;
- tv->tv_usec = ts.tv_nsec / 1000;
- }
- if (tz) {
- tz->tz_minuteswest = vdata->tz_minuteswest;
- tz->tz_dsttime = vdata->tz_dsttime;
- }
-
- return ret;
+ return __cvdso_clock_getres_time32(clock_id, res);
}
/* Avoid unresolved references emitted by GCC */
diff --git a/arch/arm/vfp/Makefile b/arch/arm/vfp/Makefile
index 9975b63..749901a 100644
--- a/arch/arm/vfp/Makefile
+++ b/arch/arm/vfp/Makefile
@@ -8,6 +8,4 @@
# ccflags-y := -DDEBUG
# asflags-y := -DDEBUG
-KBUILD_AFLAGS :=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp -mfloat-abi=soft)
-
obj-y += vfpmodule.o entry.o vfphw.o vfpsingle.o vfpdouble.o
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index b530db8..d5837bf 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -78,6 +78,7 @@
ENTRY(vfp_support_entry)
DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
+ .fpu vfpv2
VFPFMRX r1, FPEXC @ Is the VFP enabled?
DBGSTR1 "fpexc %08x", r1
tst r1, #FPEXC_EN
@@ -253,11 +254,14 @@
ENTRY(vfp_get_float)
tbl_branch r0, r3, #3
+ .fpu vfpv2
.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
+1: vmov r0, s\dr
ret lr
.org 1b + 8
-1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
+ .endr
+ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1: vmov r0, s\dr
ret lr
.org 1b + 8
.endr
@@ -265,11 +269,14 @@
ENTRY(vfp_put_float)
tbl_branch r1, r3, #3
+ .fpu vfpv2
.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
+1: vmov s\dr, r0
ret lr
.org 1b + 8
-1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
+ .endr
+ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1: vmov s\dr, r0
ret lr
.org 1b + 8
.endr
@@ -277,15 +284,17 @@
ENTRY(vfp_get_double)
tbl_branch r0, r3, #3
+ .fpu vfpv2
.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1: fmrrd r0, r1, d\dr
+1: vmov r0, r1, d\dr
ret lr
.org 1b + 8
.endr
#ifdef CONFIG_VFPv3
@ d16 - d31 registers
- .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
+ .fpu vfpv3
+ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1: vmov r0, r1, d\dr
ret lr
.org 1b + 8
.endr
@@ -299,15 +308,17 @@
ENTRY(vfp_put_double)
tbl_branch r2, r3, #3
+ .fpu vfpv2
.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1: fmdrr d\dr, r0, r1
+1: vmov d\dr, r0, r1
ret lr
.org 1b + 8
.endr
#ifdef CONFIG_VFPv3
+ .fpu vfpv3
@ d16 - d31 registers
- .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr
+ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+1: vmov d\dr, r0, r1
ret lr
.org 1b + 8
.endr
diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h
index 38dc154..3c7938f 100644
--- a/arch/arm/vfp/vfpinstr.h
+++ b/arch/arm/vfp/vfpinstr.h
@@ -62,10 +62,23 @@
#define FPSCR_C (1 << 29)
#define FPSCR_V (1 << 28)
-/*
- * Since we aren't building with -mfpu=vfp, we need to code
- * these instructions using their MRC/MCR equivalents.
- */
+#ifdef CONFIG_AS_VFP_VMRS_FPINST
+
+#define fmrx(_vfp_) ({ \
+ u32 __v; \
+ asm(".fpu vfpv2\n" \
+ "vmrs %0, " #_vfp_ \
+ : "=r" (__v) : : "cc"); \
+ __v; \
+ })
+
+#define fmxr(_vfp_,_var_) \
+ asm(".fpu vfpv2\n" \
+ "vmsr " #_vfp_ ", %0" \
+ : : "r" (_var_) : "cc")
+
+#else
+
#define vfpreg(_vfp_) #_vfp_
#define fmrx(_vfp_) ({ \
@@ -79,6 +92,8 @@
asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
: : "r" (_var_) : "cc")
+#endif
+
u32 vfp_single_cpdo(u32 inst, u32 fpscr);
u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 57dfc13..8ad576e 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -36,7 +36,7 @@
#include <linux/mm.h>
-struct start_info _xen_start_info;
+static struct start_info _xen_start_info;
struct start_info *xen_start_info = &_xen_start_info;
EXPORT_SYMBOL(xen_start_info);
@@ -150,7 +150,7 @@
pr_info("Xen: initializing cpu%d\n", cpu);
vcpup = per_cpu_ptr(xen_vcpu_info, cpu);
- info.mfn = virt_to_gfn(vcpup);
+ info.mfn = percpu_to_gfn(vcpup);
info.offset = xen_offset_in_page(vcpup);
err = HYPERVISOR_vcpu_op(VCPUOP_register_vcpu_info, xen_vcpu_nr(cpu),
@@ -158,7 +158,8 @@
BUG_ON(err);
per_cpu(xen_vcpu, cpu) = vcpup;
- xen_setup_runstate_info(cpu);
+ if (!xen_kernel_unmapped_at_usr())
+ xen_setup_runstate_info(cpu);
after_register_vcpu_info:
enable_percpu_irq(xen_events_irq, 0);
@@ -241,7 +242,6 @@
* see Documentation/devicetree/bindings/arm/xen.txt for the
* documentation of the Xen Device Tree format.
*/
-#define GRANT_TABLE_PHYSADDR 0
void __init xen_early_init(void)
{
of_scan_flat_dt(fdt_find_hyper_node, NULL);
@@ -386,7 +386,8 @@
return -EINVAL;
}
- xen_time_setup_guest();
+ if (!xen_kernel_unmapped_at_usr())
+ xen_time_setup_guest();
if (xen_initial_domain())
pvclock_gtod_register_notifier(&xen_pvclock_gtod_notifier);
diff --git a/arch/arm/xen/mm.c b/arch/arm/xen/mm.c
index 38fa917..467fa22 100644
--- a/arch/arm/xen/mm.c
+++ b/arch/arm/xen/mm.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/cpu.h>
-#include <linux/dma-noncoherent.h>
+#include <linux/dma-direct.h>
+#include <linux/dma-map-ops.h>
#include <linux/gfp.h>
#include <linux/highmem.h>
#include <linux/export.h>
@@ -15,6 +16,7 @@
#include <xen/interface/grant_table.h>
#include <xen/interface/memory.h>
#include <xen/page.h>
+#include <xen/xen-ops.h>
#include <xen/swiotlb-xen.h>
#include <asm/cacheflush.h>
@@ -23,11 +25,12 @@
unsigned long xen_get_swiotlb_free_pages(unsigned int order)
{
- struct memblock_region *reg;
+ phys_addr_t base;
gfp_t flags = __GFP_NOWARN|__GFP_KSWAPD_RECLAIM;
+ u64 i;
- for_each_memblock(memory, reg) {
- if (reg->base < (phys_addr_t)0xffffffff) {
+ for_each_mem_range(i, &base, NULL) {
+ if (base < (phys_addr_t)0xffffffff) {
if (IS_ENABLED(CONFIG_ZONE_DMA32))
flags |= __GFP_DMA32;
else
@@ -41,15 +44,18 @@
static bool hypercall_cflush = false;
/* buffers in highmem or foreign pages cannot cross page boundaries */
-static void dma_cache_maint(dma_addr_t handle, size_t size, u32 op)
+static void dma_cache_maint(struct device *dev, dma_addr_t handle,
+ size_t size, u32 op)
{
struct gnttab_cache_flush cflush;
- cflush.a.dev_bus_addr = handle & XEN_PAGE_MASK;
cflush.offset = xen_offset_in_page(handle);
cflush.op = op;
+ handle &= XEN_PAGE_MASK;
do {
+ cflush.a.dev_bus_addr = dma_to_phys(dev, handle);
+
if (size + cflush.offset > XEN_PAGE_SIZE)
cflush.length = XEN_PAGE_SIZE - cflush.offset;
else
@@ -58,7 +64,7 @@
HYPERVISOR_grant_table_op(GNTTABOP_cache_flush, &cflush, 1);
cflush.offset = 0;
- cflush.a.dev_bus_addr += cflush.length;
+ handle += cflush.length;
size -= cflush.length;
} while (size);
}
@@ -71,23 +77,19 @@
* dma-direct functions, otherwise we call the Xen specific version.
*/
void xen_dma_sync_for_cpu(struct device *dev, dma_addr_t handle,
- phys_addr_t paddr, size_t size, enum dma_data_direction dir)
+ size_t size, enum dma_data_direction dir)
{
- if (pfn_valid(PFN_DOWN(handle)))
- arch_sync_dma_for_cpu(dev, paddr, size, dir);
- else if (dir != DMA_TO_DEVICE)
- dma_cache_maint(handle, size, GNTTAB_CACHE_INVAL);
+ if (dir != DMA_TO_DEVICE)
+ dma_cache_maint(dev, handle, size, GNTTAB_CACHE_INVAL);
}
void xen_dma_sync_for_device(struct device *dev, dma_addr_t handle,
- phys_addr_t paddr, size_t size, enum dma_data_direction dir)
+ size_t size, enum dma_data_direction dir)
{
- if (pfn_valid(PFN_DOWN(handle)))
- arch_sync_dma_for_device(dev, paddr, size, dir);
- else if (dir == DMA_FROM_DEVICE)
- dma_cache_maint(handle, size, GNTTAB_CACHE_INVAL);
+ if (dir == DMA_FROM_DEVICE)
+ dma_cache_maint(dev, handle, size, GNTTAB_CACHE_INVAL);
else
- dma_cache_maint(handle, size, GNTTAB_CACHE_CLEAN);
+ dma_cache_maint(dev, handle, size, GNTTAB_CACHE_CLEAN);
}
bool xen_arch_need_swiotlb(struct device *dev,
@@ -95,7 +97,7 @@
dma_addr_t dev_addr)
{
unsigned int xen_pfn = XEN_PFN_DOWN(phys);
- unsigned int bfn = XEN_PFN_DOWN(dev_addr);
+ unsigned int bfn = XEN_PFN_DOWN(dma_to_phys(dev, dev_addr));
/*
* The swiotlb buffer should be used if
@@ -133,7 +135,7 @@
return;
}
-int __init xen_mm_init(void)
+static int __init xen_mm_init(void)
{
struct gnttab_cache_flush cflush;
if (!xen_initial_domain())