Update Linux to v5.4.2
Change-Id: Idf6911045d9d382da2cfe01b1edff026404ac8fd
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 58351e4..c8b595c 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -1,6 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
# MIPS headers
-generic-(CONFIG_GENERIC_CSUM) += checksum.h
+generated-y += syscall_table_32_o32.h
+generated-y += syscall_table_64_n32.h
+generated-y += syscall_table_64_n64.h
+generated-y += syscall_table_64_o32.h
generic-y += current.h
+generic-y += device.h
generic-y += dma-contiguous.h
generic-y += emergency-restart.h
generic-y += export.h
@@ -15,7 +20,6 @@
generic-y += qrwlock.h
generic-y += qspinlock.h
generic-y += sections.h
-generic-y += segment.h
generic-y += trace_clock.h
generic-y += unaligned.h
generic-y += user.h
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 4856adc..59a48c6 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -135,18 +135,9 @@
*/
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
-#ifndef CONFIG_CPU_R8000
-
-/*
- * The R8000 doesn't have the 32-bit compat spaces so we don't define them
- * in order to catch bugs in the source code.
- */
-
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
-#endif
-
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
diff --git a/arch/mips/include/asm/asm-eva.h b/arch/mips/include/asm/asm-eva.h
index 1e38f0e..d80be38 100644
--- a/arch/mips/include/asm/asm-eva.h
+++ b/arch/mips/include/asm/asm-eva.h
@@ -15,6 +15,7 @@
/* Kernel variants */
#define kernel_cache(op, base) "cache " op ", " base "\n"
+#define kernel_pref(hint, base) "pref " hint ", " base "\n"
#define kernel_ll(reg, addr) "ll " reg ", " addr "\n"
#define kernel_sc(reg, addr) "sc " reg ", " addr "\n"
#define kernel_lw(reg, addr) "lw " reg ", " addr "\n"
@@ -51,6 +52,7 @@
" .set pop\n"
#define user_cache(op, base) __BUILD_EVA_INSN("cachee", op, base)
+#define user_pref(hint, base) __BUILD_EVA_INSN("prefe", hint, base)
#define user_ll(reg, addr) __BUILD_EVA_INSN("lle", reg, addr)
#define user_sc(reg, addr) __BUILD_EVA_INSN("sce", reg, addr)
#define user_lw(reg, addr) __BUILD_EVA_INSN("lwe", reg, addr)
@@ -72,6 +74,7 @@
#else
#define user_cache(op, base) kernel_cache(op, base)
+#define user_pref(hint, base) kernel_pref(hint, base)
#define user_ll(reg, addr) kernel_ll(reg, addr)
#define user_sc(reg, addr) kernel_sc(reg, addr)
#define user_lw(reg, addr) kernel_lw(reg, addr)
@@ -99,6 +102,7 @@
#else /* __ASSEMBLY__ */
#define kernel_cache(op, base) cache op, base
+#define kernel_pref(hint, base) pref hint, base
#define kernel_ll(reg, addr) ll reg, addr
#define kernel_sc(reg, addr) sc reg, addr
#define kernel_lw(reg, addr) lw reg, addr
@@ -135,6 +139,7 @@
.set pop;
#define user_cache(op, base) __BUILD_EVA_INSN(cachee, op, base)
+#define user_pref(hint, base) __BUILD_EVA_INSN(prefe, hint, base)
#define user_ll(reg, addr) __BUILD_EVA_INSN(lle, reg, addr)
#define user_sc(reg, addr) __BUILD_EVA_INSN(sce, reg, addr)
#define user_lw(reg, addr) __BUILD_EVA_INSN(lwe, reg, addr)
@@ -155,6 +160,7 @@
#else
#define user_cache(op, base) kernel_cache(op, base)
+#define user_pref(hint, base) kernel_pref(hint, base)
#define user_ll(reg, addr) kernel_ll(reg, addr)
#define user_sc(reg, addr) kernel_sc(reg, addr)
#define user_lw(reg, addr) kernel_lw(reg, addr)
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 81fae23..c23527b 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -20,32 +20,6 @@
#include <asm/sgidefs.h>
#include <asm/asm-eva.h>
-#ifndef CAT
-#ifdef __STDC__
-#define __CAT(str1, str2) str1##str2
-#else
-#define __CAT(str1, str2) str1/**/str2
-#endif
-#define CAT(str1, str2) __CAT(str1, str2)
-#endif
-
-/*
- * PIC specific declarations
- * Not used for the kernel but here seems to be the right place.
- */
-#ifdef __PIC__
-#define CPRESTORE(register) \
- .cprestore register
-#define CPADD(register) \
- .cpadd register
-#define CPLOAD(register) \
- .cpload register
-#else
-#define CPRESTORE(register)
-#define CPADD(register)
-#define CPLOAD(register)
-#endif
-
/*
* LEAF - declare leaf routine
*/
@@ -130,96 +104,6 @@
.popsection;
/*
- * Build text tables
- */
-#define TTABLE(string) \
- .pushsection .text; \
- .word 1f; \
- .popsection \
- .pushsection .data; \
-1: .asciiz string; \
- .popsection
-
-/*
- * MIPS IV pref instruction.
- * Use with .set noreorder only!
- *
- * MIPS IV implementations are free to treat this as a nop. The R5000
- * is one of them. So we should have an option not to use this instruction.
- */
-#ifdef CONFIG_CPU_HAS_PREFETCH
-
-#define PREF(hint,addr) \
- .set push; \
- .set arch=r5000; \
- pref hint, addr; \
- .set pop
-
-#define PREFE(hint, addr) \
- .set push; \
- .set mips0; \
- .set eva; \
- prefe hint, addr; \
- .set pop
-
-#define PREFX(hint,addr) \
- .set push; \
- .set arch=r5000; \
- prefx hint, addr; \
- .set pop
-
-#else /* !CONFIG_CPU_HAS_PREFETCH */
-
-#define PREF(hint, addr)
-#define PREFE(hint, addr)
-#define PREFX(hint, addr)
-
-#endif /* !CONFIG_CPU_HAS_PREFETCH */
-
-/*
- * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
- */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
-#define MOVN(rd, rs, rt) \
- .set push; \
- .set reorder; \
- beqz rt, 9f; \
- move rd, rs; \
- .set pop; \
-9:
-#define MOVZ(rd, rs, rt) \
- .set push; \
- .set reorder; \
- bnez rt, 9f; \
- move rd, rs; \
- .set pop; \
-9:
-#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
-#define MOVN(rd, rs, rt) \
- .set push; \
- .set noreorder; \
- bnezl rt, 9f; \
- move rd, rs; \
- .set pop; \
-9:
-#define MOVZ(rd, rs, rt) \
- .set push; \
- .set noreorder; \
- beqzl rt, 9f; \
- move rd, rs; \
- .set pop; \
-9:
-#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
- (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-#define MOVN(rd, rs, rt) \
- movn rd, rs, rt
-#define MOVZ(rd, rs, rt) \
- movz rd, rs, rt
-#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
-
-/*
* Stack alignment
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index d4ea7a5..bb8658c 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -58,15 +58,17 @@
if (kernel_uses_llsc) { \
int temp; \
\
+ loongson_llsc_mb(); \
__asm__ __volatile__( \
+ " .set push \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: ll %0, %1 # atomic_" #op " \n" \
" " #asm_op " %0, %2 \n" \
" sc %0, %1 \n" \
"\t" __scbeqz " %0, 1b \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
- : "Ir" (i)); \
+ : "Ir" (i) : __LLSC_CLOBBER); \
} else { \
unsigned long flags; \
\
@@ -84,17 +86,19 @@
if (kernel_uses_llsc) { \
int temp; \
\
+ loongson_llsc_mb(); \
__asm__ __volatile__( \
+ " .set push \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: ll %1, %2 # atomic_" #op "_return \n" \
" " #asm_op " %0, %1, %3 \n" \
" sc %0, %2 \n" \
"\t" __scbeqz " %0, 1b \n" \
" " #asm_op " %0, %1, %3 \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
- : "Ir" (i)); \
+ : "Ir" (i) : __LLSC_CLOBBER); \
} else { \
unsigned long flags; \
\
@@ -116,17 +120,19 @@
if (kernel_uses_llsc) { \
int temp; \
\
+ loongson_llsc_mb(); \
__asm__ __volatile__( \
+ " .set push \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: ll %1, %2 # atomic_fetch_" #op " \n" \
" " #asm_op " %0, %1, %3 \n" \
" sc %0, %2 \n" \
"\t" __scbeqz " %0, 1b \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
" move %0, %1 \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
- : "Ir" (i)); \
+ : "Ir" (i) : __LLSC_CLOBBER); \
} else { \
unsigned long flags; \
\
@@ -187,21 +193,24 @@
if (kernel_uses_llsc) {
int temp;
+ loongson_llsc_mb();
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_LEVEL" \n"
"1: ll %1, %2 # atomic_sub_if_positive\n"
- " .set mips0 \n"
+ " .set pop \n"
" subu %0, %1, %3 \n"
" move %1, %0 \n"
- " bltz %0, 1f \n"
+ " bltz %0, 2f \n"
+ " .set push \n"
" .set "MIPS_ISA_LEVEL" \n"
" sc %1, %2 \n"
"\t" __scbeqz " %1, 1b \n"
- "1: \n"
- " .set mips0 \n"
+ "2: \n"
+ " .set pop \n"
: "=&r" (result), "=&r" (temp),
"+" GCC_OFF_SMALL_ASM() (v->counter)
- : "Ir" (i));
+ : "Ir" (i) : __LLSC_CLOBBER);
} else {
unsigned long flags;
@@ -246,20 +255,22 @@
#define atomic64_set(v, i) WRITE_ONCE((v)->counter, (i))
#define ATOMIC64_OP(op, c_op, asm_op) \
-static __inline__ void atomic64_##op(long i, atomic64_t * v) \
+static __inline__ void atomic64_##op(s64 i, atomic64_t * v) \
{ \
if (kernel_uses_llsc) { \
- long temp; \
+ s64 temp; \
\
+ loongson_llsc_mb(); \
__asm__ __volatile__( \
+ " .set push \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: lld %0, %1 # atomic64_" #op " \n" \
" " #asm_op " %0, %2 \n" \
" scd %0, %1 \n" \
"\t" __scbeqz " %0, 1b \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
- : "Ir" (i)); \
+ : "Ir" (i) : __LLSC_CLOBBER); \
} else { \
unsigned long flags; \
\
@@ -270,24 +281,26 @@
}
#define ATOMIC64_OP_RETURN(op, c_op, asm_op) \
-static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v) \
+static __inline__ s64 atomic64_##op##_return_relaxed(s64 i, atomic64_t * v) \
{ \
- long result; \
+ s64 result; \
\
if (kernel_uses_llsc) { \
- long temp; \
+ s64 temp; \
\
+ loongson_llsc_mb(); \
__asm__ __volatile__( \
+ " .set push \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: lld %1, %2 # atomic64_" #op "_return\n" \
" " #asm_op " %0, %1, %3 \n" \
" scd %0, %2 \n" \
"\t" __scbeqz " %0, 1b \n" \
" " #asm_op " %0, %1, %3 \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
- : "Ir" (i)); \
+ : "Ir" (i) : __LLSC_CLOBBER); \
} else { \
unsigned long flags; \
\
@@ -302,24 +315,26 @@
}
#define ATOMIC64_FETCH_OP(op, c_op, asm_op) \
-static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v) \
+static __inline__ s64 atomic64_fetch_##op##_relaxed(s64 i, atomic64_t * v) \
{ \
- long result; \
+ s64 result; \
\
- if (kernel_uses_llsc && R10000_LLSC_WAR) { \
- long temp; \
+ if (kernel_uses_llsc) { \
+ s64 temp; \
\
+ loongson_llsc_mb(); \
__asm__ __volatile__( \
+ " .set push \n" \
" .set "MIPS_ISA_LEVEL" \n" \
"1: lld %1, %2 # atomic64_fetch_" #op "\n" \
" " #asm_op " %0, %1, %3 \n" \
" scd %0, %2 \n" \
"\t" __scbeqz " %0, 1b \n" \
" move %0, %1 \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
: "=&r" (result), "=&r" (temp), \
"+" GCC_OFF_SMALL_ASM() (v->counter) \
- : "Ir" (i)); \
+ : "Ir" (i) : __LLSC_CLOBBER); \
} else { \
unsigned long flags; \
\
@@ -372,16 +387,17 @@
* Atomically test @v and subtract @i if @v is greater or equal than @i.
* The function returns the old value of @v minus @i.
*/
-static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
+static __inline__ s64 atomic64_sub_if_positive(s64 i, atomic64_t * v)
{
- long result;
+ s64 result;
smp_mb__before_llsc();
if (kernel_uses_llsc) {
- long temp;
+ s64 temp;
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_LEVEL" \n"
"1: lld %1, %2 # atomic64_sub_if_positive\n"
" dsubu %0, %1, %3 \n"
@@ -390,7 +406,7 @@
" scd %1, %2 \n"
"\t" __scbeqz " %1, 1b \n"
"1: \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (result), "=&r" (temp),
"+" GCC_OFF_SMALL_ASM() (v->counter)
: "Ir" (i));
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index a5eb1bb..9228f73 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -105,6 +105,20 @@
*/
#define STYPE_SYNC_MB 0x10
+/*
+ * stype 0x14 - A completion barrier specific to global invalidations
+ *
+ * When a sync instruction of this type completes any preceding GINVI or GINVT
+ * operation has been globalized & completed on all coherent CPUs. Anything
+ * that the GINV* instruction should invalidate will have been invalidated on
+ * all coherent CPUs when this instruction completes. It is implementation
+ * specific whether the GINV* instructions themselves will ensure completion,
+ * or this sync type will.
+ *
+ * In systems implementing global invalidates (ie. with Config5.GI == 2 or 3)
+ * this sync type also requires that previous SYNCI operations have completed.
+ */
+#define STYPE_GINV 0x14
#ifdef CONFIG_CPU_HAS_SYNC
#define __sync() \
@@ -197,14 +211,22 @@
#define __smp_wmb() barrier()
#endif
+/*
+ * When LL/SC does imply order, it must also be a compiler barrier to avoid the
+ * compiler from reordering where the CPU will not. When it does not imply
+ * order, the compiler is also free to reorder across the LL/SC loop and
+ * ordering will be done by smp_llsc_mb() and friends.
+ */
#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
#define __WEAK_LLSC_MB " sync \n"
+#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
+#define __LLSC_CLOBBER
#else
#define __WEAK_LLSC_MB " \n"
+#define smp_llsc_mb() do { } while (0)
+#define __LLSC_CLOBBER "memory"
#endif
-#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
-
#ifdef CONFIG_CPU_CAVIUM_OCTEON
#define smp_mb__before_llsc() smp_wmb()
#define __smp_mb__before_llsc() __smp_wmb()
@@ -222,6 +244,51 @@
#define __smp_mb__before_atomic() __smp_mb__before_llsc()
#define __smp_mb__after_atomic() smp_llsc_mb()
+/*
+ * Some Loongson 3 CPUs have a bug wherein execution of a memory access (load,
+ * store or prefetch) in between an LL & SC can cause the SC instruction to
+ * erroneously succeed, breaking atomicity. Whilst it's unusual to write code
+ * containing such sequences, this bug bites harder than we might otherwise
+ * expect due to reordering & speculation:
+ *
+ * 1) A memory access appearing prior to the LL in program order may actually
+ * be executed after the LL - this is the reordering case.
+ *
+ * In order to avoid this we need to place a memory barrier (ie. a SYNC
+ * instruction) prior to every LL instruction, in between it and any earlier
+ * memory access instructions.
+ *
+ * This reordering case is fixed by 3A R2 CPUs, ie. 3A2000 models and later.
+ *
+ * 2) If a conditional branch exists between an LL & SC with a target outside
+ * of the LL-SC loop, for example an exit upon value mismatch in cmpxchg()
+ * or similar, then misprediction of the branch may allow speculative
+ * execution of memory accesses from outside of the LL-SC loop.
+ *
+ * In order to avoid this we need a memory barrier (ie. a SYNC instruction)
+ * at each affected branch target, for which we also use loongson_llsc_mb()
+ * defined below.
+ *
+ * This case affects all current Loongson 3 CPUs.
+ *
+ * The above described cases cause an error in the cache coherence protocol;
+ * such that the Invalidate of a competing LL-SC goes 'missing' and SC
+ * erroneously observes its core still has Exclusive state and lets the SC
+ * proceed.
+ *
+ * Therefore the error only occurs on SMP systems.
+ */
+#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS /* Loongson-3's LLSC workaround */
+#define loongson_llsc_mb() __asm__ __volatile__("sync" : : :"memory")
+#else
+#define loongson_llsc_mb() do { } while (0)
+#endif
+
+static inline void sync_ginv(void)
+{
+ asm volatile("sync\t%0" :: "i"(STYPE_GINV));
+}
+
#include <asm-generic/barrier.h>
#endif /* __ASM_BARRIER_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index da1b871..985d6a0 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -58,35 +58,42 @@
if (kernel_uses_llsc && R10000_LLSC_WAR) {
__asm__ __volatile__(
+ " .set push \n"
" .set arch=r4000 \n"
"1: " __LL "%0, %1 # set_bit \n"
" or %0, %2 \n"
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*m)
- : "ir" (1UL << bit), GCC_OFF_SMALL_ASM() (*m));
+ : "ir" (1UL << bit), GCC_OFF_SMALL_ASM() (*m)
+ : __LLSC_CLOBBER);
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
+ loongson_llsc_mb();
do {
__asm__ __volatile__(
" " __LL "%0, %1 # set_bit \n"
" " __INS "%0, %3, %2, 1 \n"
" " __SC "%0, %1 \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
- : "ir" (bit), "r" (~0));
+ : "ir" (bit), "r" (~0)
+ : __LLSC_CLOBBER);
} while (unlikely(!temp));
#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
} else if (kernel_uses_llsc) {
+ loongson_llsc_mb();
do {
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __LL "%0, %1 # set_bit \n"
" or %0, %2 \n"
" " __SC "%0, %1 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
- : "ir" (1UL << bit));
+ : "ir" (1UL << bit)
+ : __LLSC_CLOBBER);
} while (unlikely(!temp));
} else
__mips_set_bit(nr, addr);
@@ -110,35 +117,42 @@
if (kernel_uses_llsc && R10000_LLSC_WAR) {
__asm__ __volatile__(
+ " .set push \n"
" .set arch=r4000 \n"
"1: " __LL "%0, %1 # clear_bit \n"
" and %0, %2 \n"
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
- : "ir" (~(1UL << bit)));
+ : "ir" (~(1UL << bit))
+ : __LLSC_CLOBBER);
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
+ loongson_llsc_mb();
do {
__asm__ __volatile__(
" " __LL "%0, %1 # clear_bit \n"
" " __INS "%0, $0, %2, 1 \n"
" " __SC "%0, %1 \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
- : "ir" (bit));
+ : "ir" (bit)
+ : __LLSC_CLOBBER);
} while (unlikely(!temp));
#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
} else if (kernel_uses_llsc) {
+ loongson_llsc_mb();
do {
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __LL "%0, %1 # clear_bit \n"
" and %0, %2 \n"
" " __SC "%0, %1 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
- : "ir" (~(1UL << bit)));
+ : "ir" (~(1UL << bit))
+ : __LLSC_CLOBBER);
} while (unlikely(!temp));
} else
__mips_clear_bit(nr, addr);
@@ -176,27 +190,32 @@
unsigned long temp;
__asm__ __volatile__(
+ " .set push \n"
" .set arch=r4000 \n"
"1: " __LL "%0, %1 # change_bit \n"
" xor %0, %2 \n"
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
- : "ir" (1UL << bit));
+ : "ir" (1UL << bit)
+ : __LLSC_CLOBBER);
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
+ loongson_llsc_mb();
do {
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __LL "%0, %1 # change_bit \n"
" xor %0, %2 \n"
" " __SC "%0, %1 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
- : "ir" (1UL << bit));
+ : "ir" (1UL << bit)
+ : __LLSC_CLOBBER);
} while (unlikely(!temp));
} else
__mips_change_bit(nr, addr);
@@ -223,30 +242,33 @@
unsigned long temp;
__asm__ __volatile__(
+ " .set push \n"
" .set arch=r4000 \n"
"1: " __LL "%0, %1 # test_and_set_bit \n"
" or %2, %0, %3 \n"
" " __SC "%2, %1 \n"
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
- : "memory");
+ : __LLSC_CLOBBER);
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
+ loongson_llsc_mb();
do {
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __LL "%0, %1 # test_and_set_bit \n"
" or %2, %0, %3 \n"
" " __SC "%2, %1 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
- : "memory");
+ : __LLSC_CLOBBER);
} while (unlikely(!res));
res = temp & (1UL << bit);
@@ -277,30 +299,33 @@
unsigned long temp;
__asm__ __volatile__(
+ " .set push \n"
" .set arch=r4000 \n"
"1: " __LL "%0, %1 # test_and_set_bit \n"
" or %2, %0, %3 \n"
" " __SC "%2, %1 \n"
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+m" (*m), "=&r" (res)
: "r" (1UL << bit)
- : "memory");
+ : __LLSC_CLOBBER);
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
+ loongson_llsc_mb();
do {
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __LL "%0, %1 # test_and_set_bit \n"
" or %2, %0, %3 \n"
" " __SC "%2, %1 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
- : "memory");
+ : __LLSC_CLOBBER);
} while (unlikely(!res));
res = temp & (1UL << bit);
@@ -332,6 +357,7 @@
unsigned long temp;
__asm__ __volatile__(
+ " .set push \n"
" .set arch=r4000 \n"
"1: " __LL "%0, %1 # test_and_clear_bit \n"
" or %2, %0, %3 \n"
@@ -339,15 +365,16 @@
" " __SC "%2, %1 \n"
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
- : "memory");
+ : __LLSC_CLOBBER);
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
} else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
+ loongson_llsc_mb();
do {
__asm__ __volatile__(
" " __LL "%0, %1 # test_and_clear_bit \n"
@@ -356,24 +383,26 @@
" " __SC "%0, %1 \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "ir" (bit)
- : "memory");
+ : __LLSC_CLOBBER);
} while (unlikely(!temp));
#endif
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
+ loongson_llsc_mb();
do {
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __LL "%0, %1 # test_and_clear_bit \n"
" or %2, %0, %3 \n"
" xor %2, %3 \n"
" " __SC "%2, %1 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
- : "memory");
+ : __LLSC_CLOBBER);
} while (unlikely(!res));
res = temp & (1UL << bit);
@@ -406,30 +435,33 @@
unsigned long temp;
__asm__ __volatile__(
+ " .set push \n"
" .set arch=r4000 \n"
"1: " __LL "%0, %1 # test_and_change_bit \n"
" xor %2, %0, %3 \n"
" " __SC "%2, %1 \n"
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
- : "memory");
+ : __LLSC_CLOBBER);
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
+ loongson_llsc_mb();
do {
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __LL "%0, %1 # test_and_change_bit \n"
" xor %2, %0, %3 \n"
" " __SC "\t%2, %1 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
: "r" (1UL << bit)
- : "memory");
+ : __LLSC_CLOBBER);
} while (unlikely(!res));
res = temp & (1UL << bit);
@@ -463,7 +495,7 @@
* Return the bit position (0..63) of the most significant 1 bit in a word
* Returns -1 if no 1 bit exists
*/
-static inline unsigned long __fls(unsigned long word)
+static __always_inline unsigned long __fls(unsigned long word)
{
int num;
@@ -529,7 +561,7 @@
* Returns 0..SZLONG-1
* Undefined if no bit exists, so code should check against 0 first.
*/
-static inline unsigned long __ffs(unsigned long word)
+static __always_inline unsigned long __ffs(unsigned long word)
{
return __fls(word & -word);
}
@@ -541,7 +573,7 @@
* This is defined the same way as ffs.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
-static inline int fls(int x)
+static inline int fls(unsigned int x)
{
int r;
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index bf6a8af..581a6a3 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -75,11 +75,11 @@
#endif
}
-extern char bmips_reset_nmi_vec;
-extern char bmips_reset_nmi_vec_end;
-extern char bmips_smp_movevec;
-extern char bmips_smp_int_vec;
-extern char bmips_smp_int_vec_end;
+extern char bmips_reset_nmi_vec[];
+extern char bmips_reset_nmi_vec_end[];
+extern char bmips_smp_movevec[];
+extern char bmips_smp_int_vec[];
+extern char bmips_smp_int_vec_end[];
extern int bmips_smp_enabled;
extern int bmips_cpu_offset;
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index a301a8f..34d6222 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -81,32 +81,18 @@
#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
#define MACH_INGENIC_JZ4770 2 /* JZ4770 SOC */
#define MACH_INGENIC_JZ4780 3 /* JZ4780 SOC */
+#define MACH_INGENIC_X1000 4 /* X1000 SOC */
extern char *system_type;
const char *get_system_type(void);
extern unsigned long mips_machtype;
-#define BOOT_MEM_MAP_MAX 32
#define BOOT_MEM_RAM 1
#define BOOT_MEM_ROM_DATA 2
#define BOOT_MEM_RESERVED 3
#define BOOT_MEM_INIT_RAM 4
-
-/*
- * A memory map that's built upon what was determined
- * or specified on the command line.
- */
-struct boot_mem_map {
- int nr_map;
- struct boot_mem_map_entry {
- phys_addr_t addr; /* start of memory segment */
- phys_addr_t size; /* size of memory segment */
- long type; /* type of memory segment */
- } map[BOOT_MEM_MAP_MAX];
-};
-
-extern struct boot_mem_map boot_mem_map;
+#define BOOT_MEM_NOMAP 5
extern void add_memory_region(phys_addr_t start, phys_addr_t size, long type);
extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max);
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 4812d1f..d687b40 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -25,7 +25,6 @@
*
* MIPS specific flush operations:
*
- * - flush_cache_sigtramp() flush signal trampoline
* - flush_icache_all() flush the entire instruction cache
* - flush_data_cache_page() flushes a page from the data cache
* - __flush_icache_user_range(start, end) flushes range of user instructions
@@ -110,7 +109,6 @@
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len);
-extern void (*flush_cache_sigtramp)(unsigned long addr);
extern void (*flush_icache_all)(void);
extern void (*local_flush_data_cache_page)(void * addr);
extern void (*flush_data_cache_page)(unsigned long addr);
diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
index e8161e4..dcebaaf 100644
--- a/arch/mips/include/asm/checksum.h
+++ b/arch/mips/include/asm/checksum.h
@@ -63,7 +63,7 @@
__wsum csum_and_copy_from_user(const void __user *src, void *dst,
int len, __wsum sum, int *err_ptr)
{
- if (access_ok(VERIFY_READ, src, len))
+ if (access_ok(src, len))
return csum_partial_copy_from_user(src, dst, len, sum,
err_ptr);
if (len)
@@ -81,7 +81,7 @@
__wsum sum, int *err_ptr)
{
might_fault();
- if (access_ok(VERIFY_WRITE, dst, len)) {
+ if (access_ok(dst, len)) {
if (uaccess_kernel())
return __csum_partial_copy_kernel(src,
(__force void *)dst,
diff --git a/arch/mips/include/asm/clocksource.h b/arch/mips/include/asm/clocksource.h
index 3deb1d0..cab9ae9 100644
--- a/arch/mips/include/asm/clocksource.h
+++ b/arch/mips/include/asm/clocksource.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015 Imagination Technologies
* Author: Alex Smith <alex.smith@imgtec.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_CLOCKSOURCE_H
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 89e9fb7..f613687 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -36,6 +36,8 @@
*/
extern unsigned long __cmpxchg_called_with_bad_pointer(void)
__compiletime_error("Bad argument size for cmpxchg");
+extern unsigned long __cmpxchg64_unsupported(void)
+ __compiletime_error("cmpxchg64 not available; cpu_has_64bits may be false");
extern unsigned long __xchg_called_with_bad_pointer(void)
__compiletime_error("Bad argument size for xchg");
@@ -44,12 +46,14 @@
__typeof(*(m)) __ret; \
\
if (kernel_uses_llsc) { \
+ loongson_llsc_mb(); \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
+ " .set push \n" \
" .set " MIPS_ISA_ARCH_LEVEL " \n" \
"1: " ld " %0, %2 # __xchg_asm \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
" move $1, %z3 \n" \
" .set " MIPS_ISA_ARCH_LEVEL " \n" \
" " st " $1, %1 \n" \
@@ -57,7 +61,7 @@
" .set pop \n" \
: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
: GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \
- : "memory"); \
+ : __LLSC_CLOBBER); \
} else { \
unsigned long __flags; \
\
@@ -73,8 +77,8 @@
extern unsigned long __xchg_small(volatile void *ptr, unsigned long val,
unsigned int size);
-static inline unsigned long __xchg(volatile void *ptr, unsigned long x,
- int size)
+static __always_inline
+unsigned long __xchg(volatile void *ptr, unsigned long x, int size)
{
switch (size) {
case 1:
@@ -114,13 +118,15 @@
__typeof(*(m)) __ret; \
\
if (kernel_uses_llsc) { \
+ loongson_llsc_mb(); \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
+ " .set push \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
"1: " ld " %0, %2 # __cmpxchg_asm \n" \
" bne %0, %z3, 2f \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
" move $1, %z4 \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
" " st " $1, %1 \n" \
@@ -128,8 +134,9 @@
" .set pop \n" \
"2: \n" \
: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
- : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
- : "memory"); \
+ : GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new) \
+ : __LLSC_CLOBBER); \
+ loongson_llsc_mb(); \
} else { \
unsigned long __flags; \
\
@@ -146,8 +153,9 @@
extern unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old,
unsigned long new, unsigned int size);
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
- unsigned long new, unsigned int size)
+static __always_inline
+unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+ unsigned long new, unsigned int size)
{
switch (size) {
case 1:
@@ -202,12 +210,107 @@
cmpxchg((ptr), (o), (n)); \
})
#else
-#include <asm-generic/cmpxchg-local.h>
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-#ifndef CONFIG_SMP
-#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
-#endif
-#endif
+
+# include <asm-generic/cmpxchg-local.h>
+# define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+# ifdef CONFIG_SMP
+
+static inline unsigned long __cmpxchg64(volatile void *ptr,
+ unsigned long long old,
+ unsigned long long new)
+{
+ unsigned long long tmp, ret;
+ unsigned long flags;
+
+ /*
+ * The assembly below has to combine 32 bit values into a 64 bit
+ * register, and split 64 bit values from one register into two. If we
+ * were to take an interrupt in the middle of this we'd only save the
+ * least significant 32 bits of each register & probably clobber the
+ * most significant 32 bits of the 64 bit values we're using. In order
+ * to avoid this we must disable interrupts.
+ */
+ local_irq_save(flags);
+
+ loongson_llsc_mb();
+ asm volatile(
+ " .set push \n"
+ " .set " MIPS_ISA_ARCH_LEVEL " \n"
+ /* Load 64 bits from ptr */
+ "1: lld %L0, %3 # __cmpxchg64 \n"
+ /*
+ * Split the 64 bit value we loaded into the 2 registers that hold the
+ * ret variable.
+ */
+ " dsra %M0, %L0, 32 \n"
+ " sll %L0, %L0, 0 \n"
+ /*
+ * Compare ret against old, breaking out of the loop if they don't
+ * match.
+ */
+ " bne %M0, %M4, 2f \n"
+ " bne %L0, %L4, 2f \n"
+ /*
+ * Combine the 32 bit halves from the 2 registers that hold the new
+ * variable into a single 64 bit register.
+ */
+# if MIPS_ISA_REV >= 2
+ " move %L1, %L5 \n"
+ " dins %L1, %M5, 32, 32 \n"
+# else
+ " dsll %L1, %L5, 32 \n"
+ " dsrl %L1, %L1, 32 \n"
+ " .set noat \n"
+ " dsll $at, %M5, 32 \n"
+ " or %L1, %L1, $at \n"
+ " .set at \n"
+# endif
+ /* Attempt to store new at ptr */
+ " scd %L1, %2 \n"
+ /* If we failed, loop! */
+ "\t" __scbeqz " %L1, 1b \n"
+ " .set pop \n"
+ "2: \n"
+ : "=&r"(ret),
+ "=&r"(tmp),
+ "=" GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr)
+ : GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr),
+ "r" (old),
+ "r" (new)
+ : "memory");
+ loongson_llsc_mb();
+
+ local_irq_restore(flags);
+ return ret;
+}
+
+# define cmpxchg64(ptr, o, n) ({ \
+ unsigned long long __old = (__typeof__(*(ptr)))(o); \
+ unsigned long long __new = (__typeof__(*(ptr)))(n); \
+ __typeof__(*(ptr)) __res; \
+ \
+ /* \
+ * We can only use cmpxchg64 if we know that the CPU supports \
+ * 64-bits, ie. lld & scd. Our call to __cmpxchg64_unsupported \
+ * will cause a build error unless cpu_has_64bits is a \
+ * compile-time constant 1. \
+ */ \
+ if (cpu_has_64bits && kernel_uses_llsc) { \
+ smp_mb__before_llsc(); \
+ __res = __cmpxchg64((ptr), __old, __new); \
+ smp_llsc_mb(); \
+ } else { \
+ __res = __cmpxchg64_unsupported(); \
+ } \
+ \
+ __res; \
+})
+
+# else /* !CONFIG_SMP */
+# define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
+# endif /* !CONFIG_SMP */
+#endif /* !CONFIG_64BIT */
#undef __scbeqz
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index 78675f1..c99166e 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -9,43 +9,25 @@
#include <asm/page.h>
#include <asm/ptrace.h>
+#include <asm-generic/compat.h>
+
#define COMPAT_USER_HZ 100
#define COMPAT_UTS_MACHINE "mips\0\0\0"
-typedef u32 compat_size_t;
-typedef s32 compat_ssize_t;
-typedef s32 compat_clock_t;
-typedef s32 compat_suseconds_t;
-
-typedef s32 compat_pid_t;
typedef s32 __compat_uid_t;
typedef s32 __compat_gid_t;
typedef __compat_uid_t __compat_uid32_t;
typedef __compat_gid_t __compat_gid32_t;
typedef u32 compat_mode_t;
-typedef u32 compat_ino_t;
typedef u32 compat_dev_t;
-typedef s32 compat_off_t;
-typedef s64 compat_loff_t;
typedef u32 compat_nlink_t;
typedef s32 compat_ipc_pid_t;
-typedef s32 compat_daddr_t;
typedef s32 compat_caddr_t;
typedef struct {
s32 val[2];
} compat_fsid_t;
-typedef s32 compat_timer_t;
-typedef s32 compat_key_t;
-
-typedef s16 compat_short_t;
-typedef s32 compat_int_t;
-typedef s32 compat_long_t;
typedef s64 compat_s64;
-typedef u16 compat_ushort_t;
-typedef u32 compat_uint_t;
-typedef u32 compat_ulong_t;
typedef u64 compat_u64;
-typedef u32 compat_uptr_t;
struct compat_stat {
compat_dev_t st_dev;
@@ -59,11 +41,11 @@
s32 st_pad2[2];
compat_off_t st_size;
s32 st_pad3;
- compat_time_t st_atime;
+ old_time32_t st_atime;
s32 st_atime_nsec;
- compat_time_t st_mtime;
+ old_time32_t st_mtime;
s32 st_mtime_nsec;
- compat_time_t st_ctime;
+ old_time32_t st_ctime;
s32 st_ctime_nsec;
s32 st_blksize;
s32 st_blocks;
diff --git a/arch/mips/include/asm/compiler.h b/arch/mips/include/asm/compiler.h
index cc2eb1b..f77e99f 100644
--- a/arch/mips/include/asm/compiler.h
+++ b/arch/mips/include/asm/compiler.h
@@ -43,28 +43,16 @@
#undef barrier_before_unreachable
#define barrier_before_unreachable() asm volatile(".insn")
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
-#define GCC_IMM_ASM() "n"
-#define GCC_REG_ACCUM "$0"
+#if !defined(CONFIG_CC_IS_GCC) || \
+ (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
+# define GCC_OFF_SMALL_ASM() "ZC"
+#elif defined(CONFIG_CPU_MICROMIPS)
+# error "microMIPS compilation unsupported with GCC older than 4.9"
#else
-#define GCC_IMM_ASM() "rn"
-#define GCC_REG_ACCUM "accum"
+# define GCC_OFF_SMALL_ASM() "R"
#endif
#ifdef CONFIG_CPU_MIPSR6
-/* All MIPS R6 toolchains support the ZC constrain */
-#define GCC_OFF_SMALL_ASM() "ZC"
-#else
-#ifndef CONFIG_CPU_MICROMIPS
-#define GCC_OFF_SMALL_ASM() "R"
-#elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
-#define GCC_OFF_SMALL_ASM() "ZC"
-#else
-#error "microMIPS compilation unsupported with GCC older than 4.9"
-#endif /* CONFIG_CPU_MICROMIPS */
-#endif /* CONFIG_CPU_MIPSR6 */
-
-#ifdef CONFIG_CPU_MIPSR6
#define MIPS_ISA_LEVEL "mips64r6"
#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
#define MIPS_ISA_LEVEL_RAW mips64r6
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 0edba3e..983a6a7 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -15,6 +15,7 @@
#include <cpu-feature-overrides.h>
#define __ase(ase) (cpu_data[0].ases & (ase))
+#define __isa(isa) (cpu_data[0].isa_level & (isa))
#define __opt(opt) (cpu_data[0].options & (opt))
/*
@@ -53,6 +54,18 @@
#define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt))
/*
+ * Similarly allow for ISA level checks that take into account knowledge of the
+ * ISA targeted by the kernel build, provided by MIPS_ISA_REV.
+ */
+#define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag))
+#define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag))
+#define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag))
+#define __isa_range(ge, lt) \
+ ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
+#define __isa_range_or_flag(ge, lt, flag) \
+ (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
+
+/*
* SMP assumption: Options of CPU 0 are a superset of all processors.
* This is true for all known MIPS systems.
*/
@@ -115,10 +128,15 @@
#endif
/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */
#ifndef cpu_has_fpu
-#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
-#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
+# ifdef CONFIG_MIPS_FP_SUPPORT
+# define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
+# define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
+# else
+# define cpu_has_fpu 0
+# define raw_cpu_has_fpu 0
+# endif
#else
-#define raw_cpu_has_fpu cpu_has_fpu
+# define raw_cpu_has_fpu cpu_has_fpu
#endif
#ifndef cpu_has_32fpr
#define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR)
@@ -195,7 +213,9 @@
#endif
#ifndef cpu_has_mmips
-# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
+# if defined(__mips_micromips)
+# define cpu_has_mmips 1
+# elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
# define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS)
# else
# define cpu_has_mmips 0
@@ -223,9 +243,6 @@
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
-#ifndef cpu_has_local_ebase
-#define cpu_has_local_ebase 1
-#endif
/*
* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
@@ -246,48 +263,38 @@
#endif
#endif
-/* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */
-#if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \
- (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \
- (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \
- (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \
- (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \
- (defined(cpu_has_mips64r6) && cpu_has_mips64r6))
-#define CPU_NO_EFFICIENT_FFS 1
-#endif
-
#ifndef cpu_has_mips_1
-# define cpu_has_mips_1 (!cpu_has_mips_r6)
+# define cpu_has_mips_1 (MIPS_ISA_REV < 6)
#endif
#ifndef cpu_has_mips_2
-# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
+# define cpu_has_mips_2 __isa_lt_and_flag(6, MIPS_CPU_ISA_II)
#endif
#ifndef cpu_has_mips_3
-# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
+# define cpu_has_mips_3 __isa_lt_and_flag(6, MIPS_CPU_ISA_III)
#endif
#ifndef cpu_has_mips_4
-# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
+# define cpu_has_mips_4 __isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
#endif
#ifndef cpu_has_mips_5
-# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
+# define cpu_has_mips_5 __isa_lt_and_flag(6, MIPS_CPU_ISA_V)
#endif
#ifndef cpu_has_mips32r1
-# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
+# define cpu_has_mips32r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
#endif
#ifndef cpu_has_mips32r2
-# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
+# define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
#endif
#ifndef cpu_has_mips32r6
-# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
+# define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
#endif
#ifndef cpu_has_mips64r1
-# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
+# define cpu_has_mips64r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1)
#endif
#ifndef cpu_has_mips64r2
-# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
+# define cpu_has_mips64r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2)
#endif
#ifndef cpu_has_mips64r6
-# define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
+# define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
#endif
/*
@@ -387,6 +394,22 @@
#define cpu_has_dsp3 __ase(MIPS_ASE_DSP3)
#endif
+#ifndef cpu_has_loongson_mmi
+#define cpu_has_loongson_mmi __ase(MIPS_ASE_LOONGSON_MMI)
+#endif
+
+#ifndef cpu_has_loongson_cam
+#define cpu_has_loongson_cam __ase(MIPS_ASE_LOONGSON_CAM)
+#endif
+
+#ifndef cpu_has_loongson_ext
+#define cpu_has_loongson_ext __ase(MIPS_ASE_LOONGSON_EXT)
+#endif
+
+#ifndef cpu_has_loongson_ext2
+#define cpu_has_loongson_ext2 __ase(MIPS_ASE_LOONGSON_EXT2)
+#endif
+
#ifndef cpu_has_mipsmt
#define cpu_has_mipsmt __isa_lt_and_ase(6, MIPS_ASE_MIPSMT)
#endif
@@ -581,6 +604,19 @@
#endif /* CONFIG_MIPS_MT_SMP */
/*
+ * We only enable MMID support for configurations which natively support 64 bit
+ * atomics because getting good performance from the allocator relies upon
+ * efficient atomic64_*() functions.
+ */
+#ifndef cpu_has_mmid
+# ifdef CONFIG_GENERIC_ATOMIC64
+# define cpu_has_mmid 0
+# else
+# define cpu_has_mmid __isa_ge_and_opt(6, MIPS_CPU_MMID)
+# endif
+#endif
+
+/*
* Guest capabilities
*/
#ifndef cpu_guest_has_conf1
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index a41059d..ed7ffe4 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -50,7 +50,7 @@
#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
struct cpuinfo_mips {
- unsigned long asid_cache;
+ u64 asid_cache;
#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
unsigned long asid_mask;
#endif
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index a45af3d..7bbb667 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -38,7 +38,7 @@
#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \
defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
case CPU_4KEC:
- case CPU_JZRISC:
+ case CPU_XBURST:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
@@ -116,11 +116,6 @@
case CPU_VR4181A:
#endif
-#ifdef CONFIG_SYS_HAS_CPU_R4300
- case CPU_R4300:
- case CPU_R4310:
-#endif
-
#ifdef CONFIG_SYS_HAS_CPU_R4X00
case CPU_R4000PC:
case CPU_R4000SC:
@@ -143,10 +138,6 @@
case CPU_R5000:
#endif
-#ifdef CONFIG_SYS_HAS_CPU_R5432
- case CPU_R5432:
-#endif
-
#ifdef CONFIG_SYS_HAS_CPU_R5500
case CPU_R5500:
#endif
@@ -155,10 +146,6 @@
case CPU_NEVADA:
#endif
-#ifdef CONFIG_SYS_HAS_CPU_R8000
- case CPU_R8000:
-#endif
-
#ifdef CONFIG_SYS_HAS_CPU_R10000
case CPU_R10000:
case CPU_R12000:
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index dacbdb8..7fddcb8 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -9,6 +9,8 @@
#ifndef _ASM_CPU_H
#define _ASM_CPU_H
+#include <linux/bits.h>
+
/*
As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
register 15, select 0) is defined in this (backwards compatible) way:
@@ -45,7 +47,7 @@
#define PRID_COMP_CAVIUM 0x0d0000
#define PRID_COMP_LOONGSON 0x140000
#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */
-#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775 */
+#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */
#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
/*
@@ -181,7 +183,7 @@
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
*/
-#define PRID_IMP_JZRISC 0x0200
+#define PRID_IMP_XBURST 0x0200
/*
* These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
@@ -248,8 +250,9 @@
#define PRID_REV_LOONGSON3A_R1 0x0005
#define PRID_REV_LOONGSON3B_R1 0x0006
#define PRID_REV_LOONGSON3B_R2 0x0007
-#define PRID_REV_LOONGSON3A_R2 0x0008
+#define PRID_REV_LOONGSON3A_R2_0 0x0008
#define PRID_REV_LOONGSON3A_R3_0 0x0009
+#define PRID_REV_LOONGSON3A_R2_1 0x000c
#define PRID_REV_LOONGSON3A_R3_1 0x000d
/*
@@ -290,19 +293,14 @@
/*
* R4000 class processors
*/
- CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
+ CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200,
CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
- CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
+ CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R10000,
CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
CPU_SR71000, CPU_TX49XX,
/*
- * R8000 class processors
- */
- CPU_R8000,
-
- /*
* TX3900 class processors
*/
CPU_TX3912, CPU_TX3922, CPU_TX3927,
@@ -312,7 +310,7 @@
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
- CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
+ CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON1, CPU_M14KC,
CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
@@ -352,75 +350,69 @@
MIPS_CPU_ISA_M64R6)
/*
- * Private version of BIT_ULL() to escape include file recursion hell.
- * We soon will have to switch to another mechanism that will work with
- * more than 64 bits anyway.
- */
-#define MBIT_ULL(bit) (1ULL << (bit))
-
-/*
* CPU Option encodings
*/
-#define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */
-#define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */
-#define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */
-#define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */
-#define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */
-#define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */
-#define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */
-#define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */
-#define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */
-#define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */
-#define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */
-#define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
-#define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */
-#define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */
-#define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */
-#define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */
-#define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */
-#define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */
-#define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */
-#define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
-#define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
-#define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */
-#define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */
-#define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
-#define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */
-#define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */
-#define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */
-#define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
-#define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */
-#define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
-#define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */
-#define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */
-#define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */
-#define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */
-#define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */
-#define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */
-#define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */
-#define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */
-#define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */
-#define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */
-#define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
-#define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */
-#define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
-#define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */
-#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */
-#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
-#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */
-#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */
-#define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
-#define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */
-#define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */
-#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
-#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
-#define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */
+#define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
+#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
+#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
+#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
+#define MIPS_CPU_TX39_CACHE BIT_ULL( 4) /* TX3900-style caches */
+#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
+#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
+#define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
+#define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
+#define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
+#define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */
+#define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */
+#define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
+#define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
+#define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */
+#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */
+#define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */
+#define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
+#define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
+#define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
+#define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */
+#define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
+#define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */
+#define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */
+#define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */
+#define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
+#define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */
+#define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
+#define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */
+#define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */
+#define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */
+#define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */
+#define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
+#define MIPS_CPU_BP_GHIST BIT_ULL(35) /* R12K+ Branch Prediction Global History */
+#define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */
+#define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
+#define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */
+#define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */
+#define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
+#define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */
+#define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
+#define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
+#define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */
+#define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */
+#define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */
+#define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */
+#define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
+#define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */
+#define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */
+#define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
+#define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
+#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */
#define MIPS_CPU_SHARED_FTLB_RAM \
- MBIT_ULL(54) /* CPU shares FTLB RAM with another */
+ BIT_ULL(54) /* CPU shares FTLB RAM with another */
#define MIPS_CPU_SHARED_FTLB_ENTRIES \
- MBIT_ULL(55) /* CPU shares FTLB entries with another */
+ BIT_ULL(55) /* CPU shares FTLB entries with another */
#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
- MBIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
+ BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
+#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
/*
* CPU ASE encodings
@@ -436,5 +428,9 @@
#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
#define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/
#define MIPS_ASE_MIPS16E2 0x00000400 /* MIPS16e2 */
+#define MIPS_ASE_LOONGSON_MMI 0x00000800 /* Loongson MultiMedia extensions Instructions */
+#define MIPS_ASE_LOONGSON_CAM 0x00001000 /* Loongson CAM */
+#define MIPS_ASE_LOONGSON_EXT 0x00002000 /* Loongson EXTensions */
+#define MIPS_ASE_LOONGSON_EXT2 0x00004000 /* Loongson EXTensions R2 */
#endif /* _ASM_CPU_H */
diff --git a/arch/mips/include/asm/cpufeature.h b/arch/mips/include/asm/cpufeature.h
index c63ec05..ba9e62f 100644
--- a/arch/mips/include/asm/cpufeature.h
+++ b/arch/mips/include/asm/cpufeature.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* CPU feature definitions for module loading, used by
* module_cpu_feature_match(), see uapi/asm/hwcap.h for MIPS CPU features.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_CPUFEATURE_H
diff --git a/arch/mips/include/asm/debug.h b/arch/mips/include/asm/debug.h
index 254f00d..c7013e1 100644
--- a/arch/mips/include/asm/debug.h
+++ b/arch/mips/include/asm/debug.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015 Imagination Technologies
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_DEBUG_H__
diff --git a/arch/mips/include/asm/dec/ecc.h b/arch/mips/include/asm/dec/ecc.h
index 707ffdb..c3a3f71 100644
--- a/arch/mips/include/asm/dec/ecc.h
+++ b/arch/mips/include/asm/dec/ecc.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/ecc.h
*
@@ -6,11 +7,6 @@
* DECsystem 5900 (KN03), 5900/260 (KN05) systems.
*
* Copyright (C) 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_ECC_H
#define __ASM_MIPS_DEC_ECC_H
diff --git a/arch/mips/include/asm/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h
index be4d62a..6d912f0 100644
--- a/arch/mips/include/asm/dec/ioasic.h
+++ b/arch/mips/include/asm/dec/ioasic.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/ioasic.h
*
* DEC I/O ASIC access operations.
*
* Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_DEC_IOASIC_H
diff --git a/arch/mips/include/asm/dec/kn02ba.h b/arch/mips/include/asm/dec/kn02ba.h
index c957a4f..81a6cc1 100644
--- a/arch/mips/include/asm/dec/kn02ba.h
+++ b/arch/mips/include/asm/dec/kn02ba.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/kn02ba.h
*
* DECstation 5000/1xx (3min or KN02-BA) definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_KN02BA_H
#define __ASM_MIPS_DEC_KN02BA_H
diff --git a/arch/mips/include/asm/dec/kn02ca.h b/arch/mips/include/asm/dec/kn02ca.h
index 92c0fe2..a466101 100644
--- a/arch/mips/include/asm/dec/kn02ca.h
+++ b/arch/mips/include/asm/dec/kn02ca.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/kn02ca.h
*
* Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_KN02CA_H
#define __ASM_MIPS_DEC_KN02CA_H
diff --git a/arch/mips/include/asm/dec/kn05.h b/arch/mips/include/asm/dec/kn05.h
index 8e14f67..3b1524e 100644
--- a/arch/mips/include/asm/dec/kn05.h
+++ b/arch/mips/include/asm/dec/kn05.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/kn05.h
*
@@ -8,11 +9,6 @@
*
* Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
* WARNING! All this information is pure guesswork based on the
* ROM. It is provided here in hope it will give someone some
* food for thought. No documentation for the KN05 nor the KN04
diff --git a/arch/mips/include/asm/dec/kn230.h b/arch/mips/include/asm/dec/kn230.h
index ff1bf17..cb13a77 100644
--- a/arch/mips/include/asm/dec/kn230.h
+++ b/arch/mips/include/asm/dec/kn230.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/kn230.h
*
* DECsystem 5100 (MIPSmate or KN230) definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_KN230_H
#define __ASM_MIPS_DEC_KN230_H
diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
index b59a210..62c7dfb 100644
--- a/arch/mips/include/asm/dec/prom.h
+++ b/arch/mips/include/asm/dec/prom.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/prom.h
*
@@ -5,11 +6,6 @@
*
* Copyright (C) 2002 Maciej W. Rozycki
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
* Based on arch/mips/dec/prom/prom.h by the Anonymous.
*/
#ifndef _ASM_DEC_PROM_H
diff --git a/arch/mips/include/asm/dec/system.h b/arch/mips/include/asm/dec/system.h
index b2afacc..d0873fd 100644
--- a/arch/mips/include/asm/dec/system.h
+++ b/arch/mips/include/asm/dec/system.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/dec/system.h
*
* Generic DECstation/DECsystem bits.
*
* Copyright (C) 2005, 2006 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_DEC_SYSTEM_H
#define __ASM_DEC_SYSTEM_H
diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h
deleted file mode 100644
index 6aa796f..0000000
--- a/arch/mips/include/asm/device.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#ifndef _ASM_MIPS_DEVICE_H
-#define _ASM_MIPS_DEVICE_H
-
-struct dev_archdata {
-#ifdef CONFIG_DMA_PERDEV_COHERENT
- /* Non-zero if DMA is coherent with CPU caches */
- bool dma_coherent;
-#endif
-};
-
-struct pdev_archdata {
-};
-
-#endif /* _ASM_MIPS_DEVICE_H*/
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
index 8eda487..5eaa1fc 100644
--- a/arch/mips/include/asm/dma-coherence.h
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -20,6 +20,12 @@
#elif defined(CONFIG_DMA_MAYBE_COHERENT)
extern enum coherent_io_user_state coherentio;
extern int hw_coherentio;
+
+static inline bool dev_is_dma_coherent(struct device *dev)
+{
+ return coherentio == IO_COHERENCE_ENABLED ||
+ (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio);
+}
#else
#ifdef CONFIG_DMA_NONCOHERENT
#define coherentio IO_COHERENCE_DISABLED
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index e81c4e9..34de7b1 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -10,22 +10,8 @@
{
#if defined(CONFIG_MACH_JAZZ)
return &jazz_dma_ops;
-#elif defined(CONFIG_SWIOTLB)
- return &swiotlb_dma_ops;
-#elif defined(CONFIG_DMA_NONCOHERENT_OPS)
- return &dma_noncoherent_ops;
#else
- return &dma_direct_ops;
-#endif
-}
-
-#define arch_setup_dma_ops arch_setup_dma_ops
-static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
- u64 size, const struct iommu_ops *iommu,
- bool coherent)
-{
-#ifdef CONFIG_DMA_PERDEV_COHERENT
- dev->archdata.dma_coherent = coherent;
+ return NULL;
#endif
}
diff --git a/arch/mips/include/asm/ds1287.h b/arch/mips/include/asm/ds1287.h
index 3af0b8f..46cfb01 100644
--- a/arch/mips/include/asm/ds1287.h
+++ b/arch/mips/include/asm/ds1287.h
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* DS1287 timer functions.
*
* Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __ASM_DS1287_H
#define __ASM_DS1287_H
diff --git a/arch/mips/include/asm/dsemul.h b/arch/mips/include/asm/dsemul.h
index b47a975..08bfe8f 100644
--- a/arch/mips/include/asm/dsemul.h
+++ b/arch/mips/include/asm/dsemul.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2016 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_DSEMUL_H__
@@ -52,7 +48,14 @@
*
* Return: True if an emulation frame was returned from, else false.
*/
+#ifdef CONFIG_MIPS_FP_SUPPORT
extern bool do_dsemulret(struct pt_regs *xcp);
+#else
+static inline bool do_dsemulret(struct pt_regs *xcp)
+{
+ return false;
+}
+#endif
/**
* dsemul_thread_cleanup() - Cleanup thread 'emulation' frame
@@ -63,8 +66,14 @@
*
* Return: True if a frame was freed, else false.
*/
+#ifdef CONFIG_MIPS_FP_SUPPORT
extern bool dsemul_thread_cleanup(struct task_struct *tsk);
-
+#else
+static inline bool dsemul_thread_cleanup(struct task_struct *tsk)
+{
+ return false;
+}
+#endif
/**
* dsemul_thread_rollback() - Rollback from an 'emulation' frame
* @regs: User thread register context.
@@ -77,7 +86,14 @@
*
* Return: True if a frame was exited, else false.
*/
+#ifdef CONFIG_MIPS_FP_SUPPORT
extern bool dsemul_thread_rollback(struct pt_regs *regs);
+#else
+static inline bool dsemul_thread_rollback(struct pt_regs *regs)
+{
+ return false;
+}
+#endif
/**
* dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state
@@ -87,6 +103,13 @@
* for delay slot 'emulation' book-keeping is freed. This is to be called
* before @mm is freed in order to avoid memory leaks.
*/
+#ifdef CONFIG_MIPS_FP_SUPPORT
extern void dsemul_mm_cleanup(struct mm_struct *mm);
+#else
+static inline void dsemul_mm_cleanup(struct mm_struct *mm)
+{
+ /* no-op */
+}
+#endif
#endif /* __MIPS_ASM_DSEMUL_H__ */
diff --git a/arch/mips/include/asm/dsp.h b/arch/mips/include/asm/dsp.h
index 7bfad05..77fe0d6 100644
--- a/arch/mips/include/asm/dsp.h
+++ b/arch/mips/include/asm/dsp.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2005 Mips Technologies
* Author: Chris Dearman, chris@mips.com derived from fpu.h
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef _ASM_DSP_H
#define _ASM_DSP_H
diff --git a/arch/mips/include/asm/edac.h b/arch/mips/include/asm/edac.h
index fc46776..c5d1477 100644
--- a/arch/mips/include/asm/edac.h
+++ b/arch/mips/include/asm/edac.h
@@ -21,12 +21,13 @@
*/
__asm__ __volatile__ (
+ " .set push \n"
" .set mips2 \n"
"1: ll %0, %1 # edac_atomic_scrub \n"
" addu %0, $0 \n"
" sc %0, %1 \n"
" beqz %0, 1b \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*virt_addr)
: GCC_OFF_SMALL_ASM() (*virt_addr));
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 0eb1a75..f8f44b1 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -481,6 +481,8 @@
extern int arch_setup_additional_pages(struct linux_binprm *bprm,
int uses_interp);
+#ifdef CONFIG_MIPS_FP_SUPPORT
+
struct arch_elf_state {
int nan_2008;
int fp_abi;
@@ -497,19 +499,35 @@
.overall_fp_mode = -1, \
}
-/* Whether to accept legacy-NaN and 2008-NaN user binaries. */
-extern bool mips_use_nan_legacy;
-extern bool mips_use_nan_2008;
-
extern int arch_elf_pt_proc(void *ehdr, void *phdr, struct file *elf,
bool is_interp, struct arch_elf_state *state);
extern int arch_check_elf(void *ehdr, bool has_interpreter, void *interp_ehdr,
struct arch_elf_state *state);
+/* Whether to accept legacy-NaN and 2008-NaN user binaries. */
+extern bool mips_use_nan_legacy;
+extern bool mips_use_nan_2008;
+
extern void mips_set_personality_nan(struct arch_elf_state *state);
extern void mips_set_personality_fp(struct arch_elf_state *state);
+#else /* !CONFIG_MIPS_FP_SUPPORT */
+
+struct arch_elf_state;
+
+static inline void mips_set_personality_nan(struct arch_elf_state *state)
+{
+ /* no-op */
+}
+
+static inline void mips_set_personality_fp(struct arch_elf_state *state)
+{
+ /* no-op */
+}
+
+#endif /* !CONFIG_MIPS_FP_SUPPORT */
+
#define elf_read_implies_exec(ex, stk) mips_elf_read_implies_exec(&(ex), stk)
extern int mips_elf_read_implies_exec(void *elf_ex, int exstack);
diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index ecf0596..a25cdb3 100644
--- a/arch/mips/include/asm/emma/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -1,22 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
* Copyright 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_EMMA_EMMA2RH_H
#define __ASM_EMMA_EMMA2RH_H
diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h
index e55a674..2d7e133 100644
--- a/arch/mips/include/asm/emma/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
@@ -1,22 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
* Copyright 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef MARKEINS_H
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index a2813fe..9476e04 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2002 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef _ASM_FPU_H
#define _ASM_FPU_H
@@ -30,13 +26,6 @@
#include <asm/mips_mt.h>
#endif
-struct sigcontext;
-struct sigcontext32;
-
-extern void _init_fpu(unsigned int);
-extern void _save_fp(struct task_struct *);
-extern void _restore_fp(struct task_struct *);
-
/*
* This enum specifies a mode in which we want the FPU to operate, for cores
* which implement the Status.FR bit. Note that the bottom bit of the value
@@ -51,6 +40,11 @@
#define FPU_FR_MASK 0x1
};
+#ifdef CONFIG_MIPS_FP_SUPPORT
+
+extern void _save_fp(struct task_struct *);
+extern void _restore_fp(struct task_struct *);
+
#define __disable_fpu() \
do { \
clear_c0_status(ST0_CU1); \
@@ -198,42 +192,36 @@
preempt_enable();
}
-static inline int init_fpu(void)
+/**
+ * init_fp_ctx() - Initialize task FP context
+ * @target: The task whose FP context should be initialized.
+ *
+ * Initializes the FP context of the target task to sane default values if that
+ * target task does not already have valid FP context. Once the context has
+ * been initialized, the task will be marked as having used FP & thus having
+ * valid FP context.
+ *
+ * Returns: true if context is initialized, else false.
+ */
+static inline bool init_fp_ctx(struct task_struct *target)
{
- unsigned int fcr31 = current->thread.fpu.fcr31;
- int ret = 0;
+ /* If FP has been used then the target already has context */
+ if (tsk_used_math(target))
+ return false;
- if (cpu_has_fpu) {
- unsigned int config5;
+ /* Begin with data registers set to all 1s... */
+ memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr));
- ret = __own_fpu();
- if (ret)
- return ret;
+ /* FCSR has been preset by `mips_set_personality_nan'. */
- if (!cpu_has_fre) {
- _init_fpu(fcr31);
+ /*
+ * Record that the target has "used" math, such that the context
+ * just initialised, and any modifications made by the caller,
+ * aren't discarded.
+ */
+ set_stopped_child_used_math(target);
- return 0;
- }
-
- /*
- * Ensure FRE is clear whilst running _init_fpu, since
- * single precision FP instructions are used. If FRE
- * was set then we'll just end up initialising all 32
- * 64b registers.
- */
- config5 = clear_c0_config5(MIPS_CONF5_FRE);
- enable_fpu_hazard();
-
- _init_fpu(fcr31);
-
- /* Restore FRE */
- write_c0_config5(config5);
- enable_fpu_hazard();
- } else
- fpu_emulator_init_fpu();
-
- return ret;
+ return true;
}
static inline void save_fp(struct task_struct *tsk)
@@ -260,4 +248,81 @@
return tsk->thread.fpu.fpr;
}
+#else /* !CONFIG_MIPS_FP_SUPPORT */
+
+/*
+ * When FP support is disabled we provide only a minimal set of stub functions
+ * to avoid callers needing to care too much about CONFIG_MIPS_FP_SUPPORT.
+ */
+
+static inline int __enable_fpu(enum fpu_mode mode)
+{
+ return SIGILL;
+}
+
+static inline void __disable_fpu(void)
+{
+ /* no-op */
+}
+
+
+static inline int is_fpu_owner(void)
+{
+ return 0;
+}
+
+static inline void clear_fpu_owner(void)
+{
+ /* no-op */
+}
+
+static inline int own_fpu_inatomic(int restore)
+{
+ return SIGILL;
+}
+
+static inline int own_fpu(int restore)
+{
+ return SIGILL;
+}
+
+static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
+{
+ /* no-op */
+}
+
+static inline void lose_fpu(int save)
+{
+ /* no-op */
+}
+
+static inline bool init_fp_ctx(struct task_struct *target)
+{
+ return false;
+}
+
+/*
+ * The following functions should only be called in paths where we know that FP
+ * support is enabled, typically a path where own_fpu() or __enable_fpu() have
+ * returned successfully. When CONFIG_MIPS_FP_SUPPORT=n it is known at compile
+ * time that this should never happen, so calls to these functions should be
+ * optimized away & never actually be emitted.
+ */
+
+extern void save_fp(struct task_struct *tsk)
+ __compiletime_error("save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern void _save_fp(struct task_struct *)
+ __compiletime_error("_save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern void restore_fp(struct task_struct *tsk)
+ __compiletime_error("restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern void _restore_fp(struct task_struct *)
+ __compiletime_error("_restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern union fpureg *get_fpu_regs(struct task_struct *tsk)
+ __compiletime_error("get_fpu_regs() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+#endif /* !CONFIG_MIPS_FP_SUPPORT */
#endif /* _ASM_FPU_H */
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index b36097d..bb7c71f 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -1,16 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Further private data for which no space exists in mips_fpu_struct.
* This should be subsumed into the mips_fpu_struct structure as
@@ -188,17 +177,6 @@
int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
unsigned long *contpc);
-#define SIGNALLING_NAN 0x7ff800007ff80000LL
-
-static inline void fpu_emulator_init_fpu(void)
-{
- struct task_struct *t = current;
- int i;
-
- for (i = 0; i < 32; i++)
- set_fpr64(&t->thread.fpu.fpr[i], 0, SIGNALLING_NAN);
-}
-
/*
* Mask the FCSR Cause bits according to the Enable bits, observing
* that Unimplemented is always enabled.
diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index a9e61ea..b83b039 100644
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -24,9 +24,10 @@
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
+ " .set push \n" \
" .set arch=r4000 \n" \
"1: ll %1, %4 # __futex_atomic_op \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
" " insn " \n" \
" .set arch=r4000 \n" \
"2: sc $1, %2 \n" \
@@ -35,7 +36,6 @@
"3: \n" \
" .insn \n" \
" .set pop \n" \
- " .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %6 \n" \
" j 3b \n" \
@@ -50,12 +50,14 @@
"i" (-EFAULT) \
: "memory"); \
} else if (cpu_has_llsc) { \
+ loongson_llsc_mb(); \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
+ " .set push \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
"1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
- " .set mips0 \n" \
+ " .set pop \n" \
" " insn " \n" \
" .set "MIPS_ISA_ARCH_LEVEL" \n" \
"2: "user_sc("$1", "%2")" \n" \
@@ -64,7 +66,6 @@
"3: \n" \
" .insn \n" \
" .set pop \n" \
- " .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %6 \n" \
" j 3b \n" \
@@ -129,7 +130,7 @@
int ret = 0;
u32 val;
- if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+ if (!access_ok(uaddr, sizeof(u32)))
return -EFAULT;
if (cpu_has_llsc && R10000_LLSC_WAR) {
@@ -137,10 +138,11 @@
"# futex_atomic_cmpxchg_inatomic \n"
" .set push \n"
" .set noat \n"
+ " .set push \n"
" .set arch=r4000 \n"
"1: ll %1, %3 \n"
" bne %1, %z4, 3f \n"
- " .set mips0 \n"
+ " .set pop \n"
" move $1, %z5 \n"
" .set arch=r4000 \n"
"2: sc $1, %2 \n"
@@ -162,14 +164,16 @@
"i" (-EFAULT)
: "memory");
} else if (cpu_has_llsc) {
+ loongson_llsc_mb();
__asm__ __volatile__(
"# futex_atomic_cmpxchg_inatomic \n"
" .set push \n"
" .set noat \n"
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
"1: "user_ll("%1", "%3")" \n"
" bne %1, %z4, 3f \n"
- " .set mips0 \n"
+ " .set pop \n"
" move $1, %z5 \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
"2: "user_sc("$1", "%2")" \n"
@@ -190,6 +194,7 @@
: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
"i" (-EFAULT)
: "memory");
+ loongson_llsc_mb();
} else
return -ENOSYS;
diff --git a/arch/mips/include/asm/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h
index a0ea69e..6457f36 100644
--- a/arch/mips/include/asm/fw/cfe/cfe_api.h
+++ b/arch/mips/include/asm/fw/cfe/cfe_api.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2000, 2001, 2002 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Broadcom Common Firmware Environment (CFE)
diff --git a/arch/mips/include/asm/fw/cfe/cfe_error.h b/arch/mips/include/asm/fw/cfe/cfe_error.h
index fc0e91f..2f04a39 100644
--- a/arch/mips/include/asm/fw/cfe/cfe_error.h
+++ b/arch/mips/include/asm/fw/cfe/cfe_error.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2000, 2001, 2002 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
diff --git a/arch/mips/include/asm/ginvt.h b/arch/mips/include/asm/ginvt.h
new file mode 100644
index 0000000..6eb7c2b
--- /dev/null
+++ b/arch/mips/include/asm/ginvt.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __MIPS_ASM_GINVT_H__
+#define __MIPS_ASM_GINVT_H__
+
+#include <asm/mipsregs.h>
+
+enum ginvt_type {
+ GINVT_FULL,
+ GINVT_VA,
+ GINVT_MMID,
+};
+
+#ifdef TOOLCHAIN_SUPPORTS_GINV
+# define _ASM_SET_GINV ".set ginv\n"
+#else
+_ASM_MACRO_1R1I(ginvt, rs, type,
+ _ASM_INSN_IF_MIPS(0x7c0000bd | (__rs << 21) | (\\type << 8))
+ _ASM_INSN32_IF_MM(0x0000717c | (__rs << 16) | (\\type << 9)));
+# define _ASM_SET_GINV
+#endif
+
+static __always_inline void ginvt(unsigned long addr, enum ginvt_type type)
+{
+ asm volatile(
+ ".set push\n"
+ _ASM_SET_GINV
+ " ginvt %0, %1\n"
+ ".set pop"
+ : /* no outputs */
+ : "r"(addr), "i"(type)
+ : "memory");
+}
+
+static inline void ginvt_full(void)
+{
+ ginvt(0, GINVT_FULL);
+}
+
+static inline void ginvt_va(unsigned long addr)
+{
+ addr &= PAGE_MASK << 1;
+ ginvt(addr, GINVT_VA);
+}
+
+static inline void ginvt_mmid(void)
+{
+ ginvt(0, GINVT_MMID);
+}
+
+static inline void ginvt_va_mmid(unsigned long addr)
+{
+ addr &= PAGE_MASK << 1;
+ ginvt(addr, GINVT_VA | GINVT_MMID);
+}
+
+#endif /* __MIPS_ASM_GINVT_H__ */
diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h
index 2e72abb..5d68d72 100644
--- a/arch/mips/include/asm/gt64120.h
+++ b/arch/mips/include/asm/gt64120.h
@@ -1,22 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc.
* All rights reserved.
* Authors: Carsten Langgaard <carstenl@mips.com>
* Maciej W. Rozycki <macro@mips.com>
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#ifndef _ASM_GT64120_H
#define _ASM_GT64120_H
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index e0fecf2..0fa2744 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -66,10 +66,11 @@
unsigned long tmp; \
\
__asm__ __volatile__( \
+ " .set push \n" \
" .set "MIPS_ISA_LEVEL" \n" \
" dla %0, 1f \n" \
" jr.hb %0 \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
"1: \n" \
: "=r" (tmp)); \
} while (0)
@@ -141,10 +142,11 @@
unsigned long tmp; \
\
__asm__ __volatile__( \
+ " .set push \n" \
" .set mips64r2 \n" \
" dla %0, 1f \n" \
" jr.hb %0 \n" \
- " .set mips0 \n" \
+ " .set pop \n" \
"1: \n" \
: "=r" (tmp)); \
} while (0)
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index 982bc06..425bb6f 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -10,8 +10,6 @@
#define __ASM_HUGETLB_H
#include <asm/page.h>
-#include <asm-generic/hugetlb.h>
-
static inline int is_hugepage_only_range(struct mm_struct *mm,
unsigned long addr,
@@ -20,6 +18,7 @@
return 0;
}
+#define __HAVE_ARCH_PREPARE_HUGEPAGE_RANGE
static inline int prepare_hugepage_range(struct file *file,
unsigned long addr,
unsigned long len)
@@ -38,21 +37,7 @@
return 0;
}
-static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
- unsigned long addr,
- unsigned long end,
- unsigned long floor,
- unsigned long ceiling)
-{
- free_pgd_range(tlb, addr, end, floor, ceiling);
-}
-
-static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
- pte_t *ptep, pte_t pte)
-{
- set_pte_at(mm, addr, ptep, pte);
-}
-
+#define __HAVE_ARCH_HUGE_PTEP_GET_AND_CLEAR
static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
@@ -64,29 +49,21 @@
return pte;
}
+#define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH
static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
flush_tlb_page(vma, addr & huge_page_mask(hstate_vma(vma)));
}
+#define __HAVE_ARCH_HUGE_PTE_NONE
static inline int huge_pte_none(pte_t pte)
{
unsigned long val = pte_val(pte) & ~_PAGE_GLOBAL;
return !val || (val == (unsigned long)invalid_pte_table);
}
-static inline pte_t huge_pte_wrprotect(pte_t pte)
-{
- return pte_wrprotect(pte);
-}
-
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- ptep_set_wrprotect(mm, addr, ptep);
-}
-
+#define __HAVE_ARCH_HUGE_PTEP_SET_ACCESS_FLAGS
static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
unsigned long addr,
pte_t *ptep, pte_t pte,
@@ -105,13 +82,10 @@
return changed;
}
-static inline pte_t huge_ptep_get(pte_t *ptep)
-{
- return *ptep;
-}
-
static inline void arch_clear_hugepage_flags(struct page *page)
{
}
+#include <asm-generic/hugetlb.h>
+
#endif /* __ASM_HUGETLB_H */
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index 47543d5..97a5e41 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/i8259.h
*
@@ -5,11 +6,6 @@
*
* Copyright (C) 2003 Maciej W. Rozycki
* Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_I8259_H
#define _ASM_I8259_H
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 54c730a..2b7b567 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -20,6 +20,7 @@
#include <linux/irqflags.h>
#include <asm/addrspace.h>
+#include <asm/barrier.h>
#include <asm/bug.h>
#include <asm/byteorder.h>
#include <asm/cpu.h>
@@ -34,11 +35,6 @@
#include <mangle-port.h>
/*
- * Slowdown I/O port space accesses for antique hardware.
- */
-#undef CONF_SLOWDOWN_IO
-
-/*
* Raw operations are never swapped in software. OTOH values that raw
* operations are working on may or may not have been swapped by the bus
* hardware. An example use would be for flash memory that's used for
@@ -50,6 +46,11 @@
# define __raw_ioswabq(a, x) (x)
# define ____raw_ioswabq(a, x) (x)
+# define __relaxed_ioswabb ioswabb
+# define __relaxed_ioswabw ioswabw
+# define __relaxed_ioswabl ioswabl
+# define __relaxed_ioswabq ioswabq
+
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
#define IO_SPACE_LIMIT 0xffff
@@ -62,49 +63,34 @@
* instruction, so the lower 16 bits must be zero. Should be true on
* on any sane architecture; generic code does not use this assumption.
*/
-extern const unsigned long mips_io_port_base;
+extern unsigned long mips_io_port_base;
-/*
- * Gcc will generate code to load the value of mips_io_port_base after each
- * function call which may be fairly wasteful in some cases. So we don't
- * play quite by the book. We tell gcc mips_io_port_base is a long variable
- * which solves the code generation issue. Now we need to violate the
- * aliasing rules a little to make initialization possible and finally we
- * will need the barrier() to fight side effects of the aliasing chat.
- * This trickery will eventually collapse under gcc's optimizer. Oh well.
- */
static inline void set_io_port_base(unsigned long base)
{
- * (unsigned long *) &mips_io_port_base = base;
- barrier();
+ mips_io_port_base = base;
}
/*
- * Thanks to James van Artsdalen for a better timing-fix than
- * the two short jumps: using outb's to a nonexistent port seems
- * to guarantee better timings even on fast machines.
- *
- * On the other hand, I'd like to be sure of a non-existent port:
- * I feel a bit unsafe about using 0x80 (should be safe, though)
- *
- * Linus
- *
+ * Provide the necessary definitions for generic iomap. We make use of
+ * mips_io_port_base for iomap(), but we don't reserve any low addresses for
+ * use with I/O ports.
*/
-#define __SLOW_DOWN_IO \
- __asm__ __volatile__( \
- "sb\t$0,0x80(%0)" \
- : : "r" (mips_io_port_base));
+#define HAVE_ARCH_PIO_SIZE
+#define PIO_OFFSET mips_io_port_base
+#define PIO_MASK IO_SPACE_LIMIT
+#define PIO_RESERVED 0x0UL
-#ifdef CONF_SLOWDOWN_IO
-#ifdef REALLY_SLOW_IO
-#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
-#else
-#define SLOW_DOWN_IO __SLOW_DOWN_IO
-#endif
-#else
-#define SLOW_DOWN_IO
-#endif
+/*
+ * Enforce in-order execution of data I/O. In the MIPS architecture
+ * these are equivalent to corresponding platform-specific memory
+ * barriers defined in <asm/barrier.h>. API pinched from PowerPC,
+ * with sync additionally defined.
+ */
+#define iobarrier_rw() mb()
+#define iobarrier_r() rmb()
+#define iobarrier_w() wmb()
+#define iobarrier_sync() iob()
/*
* virt_to_phys - map virtual addresses to physical
@@ -153,8 +139,6 @@
return phys_to_virt(address);
}
-#define isa_page_to_bus page_to_phys
-
/*
* However PCI ones are not necessarily 1:1 and therefore these interfaces
* are forbidden in portable PCI drivers.
@@ -172,11 +156,6 @@
extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
extern void __iounmap(const volatile void __iomem *addr);
-#ifndef CONFIG_PCI
-struct pci_dev;
-static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
-#endif
-
static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
@@ -224,6 +203,18 @@
}
/*
+ * ioremap_prot - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+
+ * ioremap_prot gives the caller control over cache coherency attributes (CCA)
+ */
+static inline void __iomem *ioremap_prot(phys_addr_t offset,
+ unsigned long size, unsigned long prot_val) {
+ return __ioremap_mode(offset, size, prot_val & _CACHE_MASK);
+}
+
+/*
* ioremap - map bus memory into CPU space
* @offset: bus address of the memory
* @size: size of the resource to map
@@ -261,11 +252,11 @@
#define ioremap_uc ioremap_nocache
/*
- * ioremap_cachable - map bus memory into CPU space
+ * ioremap_cache - map bus memory into CPU space
* @offset: bus address of the memory
* @size: size of the resource to map
*
- * ioremap_nocache performs a platform specific sequence of operations to
+ * ioremap_cache performs a platform specific sequence of operations to
* make bus memory CPU accessible via the readb/readw/readl/writeb/
* writew/writel functions and the other mmio helpers. The returned
* address is not guaranteed to be usable directly as a virtual
@@ -275,9 +266,8 @@
* the CPU. Also enables full write-combining. Useful for some
* memory-like regions on I/O busses.
*/
-#define ioremap_cachable(offset, size) \
+#define ioremap_cache(offset, size) \
__ioremap_mode((offset), (size), _page_cachable_default)
-#define ioremap_cache ioremap_cachable
/*
* ioremap_wc - map bus memory into CPU space
@@ -316,13 +306,13 @@
#undef __IS_KSEG1
}
-#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
+#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3)
#define war_io_reorder_wmb() wmb()
#else
#define war_io_reorder_wmb() barrier()
#endif
-#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
+#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \
\
static inline void pfx##write##bwlq(type val, \
volatile void __iomem *mem) \
@@ -330,7 +320,10 @@
volatile type *__mem; \
type __val; \
\
- war_io_reorder_wmb(); \
+ if (barrier) \
+ iobarrier_rw(); \
+ else \
+ war_io_reorder_wmb(); \
\
__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
\
@@ -345,13 +338,14 @@
if (irq) \
local_irq_save(__flags); \
__asm__ __volatile__( \
- ".set arch=r4000" "\t\t# __writeq""\n\t" \
+ ".set push" "\t\t# __writeq""\n\t" \
+ ".set arch=r4000" "\n\t" \
"dsll32 %L0, %L0, 0" "\n\t" \
"dsrl32 %L0, %L0, 0" "\n\t" \
"dsll32 %M0, %M0, 0" "\n\t" \
"or %L0, %L0, %M0" "\n\t" \
"sd %L0, %2" "\n\t" \
- ".set mips0" "\n" \
+ ".set pop" "\n" \
: "=r" (__tmp) \
: "0" (__val), "m" (*__mem)); \
if (irq) \
@@ -367,6 +361,9 @@
\
__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
\
+ if (barrier) \
+ iobarrier_rw(); \
+ \
if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
__val = *__mem; \
else if (cpu_has_64bits) { \
@@ -375,11 +372,12 @@
if (irq) \
local_irq_save(__flags); \
__asm__ __volatile__( \
- ".set arch=r4000" "\t\t# __readq" "\n\t" \
+ ".set push" "\t\t# __readq" "\n\t" \
+ ".set arch=r4000" "\n\t" \
"ld %L0, %1" "\n\t" \
"dsra32 %M0, %L0, 0" "\n\t" \
"sll %L0, %L0, 0" "\n\t" \
- ".set mips0" "\n" \
+ ".set pop" "\n" \
: "=r" (__val) \
: "m" (*__mem)); \
if (irq) \
@@ -390,18 +388,22 @@
} \
\
/* prevent prefetching of coherent DMA data prematurely */ \
- rmb(); \
+ if (!relax) \
+ rmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}
-#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \
\
static inline void pfx##out##bwlq##p(type val, unsigned long port) \
{ \
volatile type *__addr; \
type __val; \
\
- war_io_reorder_wmb(); \
+ if (barrier) \
+ iobarrier_rw(); \
+ else \
+ war_io_reorder_wmb(); \
\
__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
\
@@ -411,7 +413,6 @@
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
\
*__addr = __val; \
- slow; \
} \
\
static inline type pfx##in##bwlq##p(unsigned long port) \
@@ -423,32 +424,41 @@
\
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
\
+ if (barrier) \
+ iobarrier_rw(); \
+ \
__val = *__addr; \
- slow; \
\
/* prevent prefetching of coherent DMA data prematurely */ \
- rmb(); \
+ if (!relax) \
+ rmb(); \
return pfx##ioswab##bwlq(__addr, __val); \
}
-#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
+#define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \
\
-__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
+__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
#define BUILDIO_MEM(bwlq, type) \
\
-__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
-__BUILD_MEMORY_PFX(, bwlq, type) \
-__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
+__BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \
+__BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \
+__BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \
+__BUILD_MEMORY_PFX(, bwlq, type, 0)
BUILDIO_MEM(b, u8)
BUILDIO_MEM(w, u16)
BUILDIO_MEM(l, u32)
+#ifdef CONFIG_64BIT
BUILDIO_MEM(q, u64)
+#else
+__BUILD_MEMORY_PFX(__raw_, q, u64, 0)
+__BUILD_MEMORY_PFX(__mem_, q, u64, 0)
+#endif
#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
- __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
- __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
+ __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \
+ __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
#define BUILDIO_IOPORT(bwlq, type) \
__BUILD_IOPORT_PFX(, bwlq, type) \
@@ -463,19 +473,23 @@
#define __BUILDIO(bwlq, type) \
\
-__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
__BUILDIO(q, u64)
-#define readb_relaxed readb
-#define readw_relaxed readw
-#define readl_relaxed readl
-#define readq_relaxed readq
+#define readb_relaxed __relaxed_readb
+#define readw_relaxed __relaxed_readw
+#define readl_relaxed __relaxed_readl
+#ifdef CONFIG_64BIT
+#define readq_relaxed __relaxed_readq
+#endif
-#define writeb_relaxed writeb
-#define writew_relaxed writew
-#define writel_relaxed writel
-#define writeq_relaxed writeq
+#define writeb_relaxed __relaxed_writeb
+#define writew_relaxed __relaxed_writew
+#define writel_relaxed __relaxed_writel
+#ifdef CONFIG_64BIT
+#define writeq_relaxed __relaxed_writeq
+#endif
#define readb_be(addr) \
__raw_readb((__force unsigned *)(addr))
@@ -498,8 +512,10 @@
/*
* Some code tests for these symbols
*/
+#ifdef CONFIG_64BIT
#define readq readq
#define writeq writeq
+#endif
#define __BUILD_MEMORY_STRING(bwlq, type) \
\
@@ -561,14 +577,6 @@
BUILDSTRING(q, u64)
#endif
-
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-#define mmiowb() wmb()
-#else
-/* Depends on MIPS II instruction set */
-#define mmiowb() asm volatile ("sync" ::: "memory")
-#endif
-
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
memset((void __force *) addr, val, count);
diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
index 39a160b..8d32118 100644
--- a/arch/mips/include/asm/irq_cpu.h
+++ b/arch/mips/include/asm/irq_cpu.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/irq_cpu.h
*
* MIPS CPU interrupt definitions.
*
* Copyright (C) 2002 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_IRQ_CPU_H
#define _ASM_IRQ_CPU_H
diff --git a/arch/mips/include/asm/irq_gt641xx.h b/arch/mips/include/asm/irq_gt641xx.h
index 250a240..d689c1c 100644
--- a/arch/mips/include/asm/irq_gt641xx.h
+++ b/arch/mips/include/asm/irq_gt641xx.h
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Galileo/Marvell GT641xx IRQ definitions.
*
* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _ASM_IRQ_GT641XX_H
#define _ASM_IRQ_GT641XX_H
diff --git a/arch/mips/include/asm/irq_regs.h b/arch/mips/include/asm/irq_regs.h
index 8c48d6d..7795dc0 100644
--- a/arch/mips/include/asm/irq_regs.h
+++ b/arch/mips/include/asm/irq_regs.h
@@ -1,8 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*
* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
*/
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 9d3610b..f0b862a 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -41,7 +41,7 @@
" .set push \n"
" .set reorder \n"
" .set noat \n"
-#if defined(CONFIG_CPU_LOONGSON3)
+#if defined(CONFIG_CPU_LOONGSON3) || defined (CONFIG_CPU_LOONGSON1)
" mfc0 %[flags], $12 \n"
" di \n"
#else
diff --git a/arch/mips/include/asm/jazzdma.h b/arch/mips/include/asm/jazzdma.h
index d913439..d13f940 100644
--- a/arch/mips/include/asm/jazzdma.h
+++ b/arch/mips/include/asm/jazzdma.h
@@ -40,12 +40,6 @@
#define VDMA_OFFSET(a) ((unsigned int)(a) & (VDMA_PAGESIZE-1))
/*
- * error code returned by vdma_alloc()
- * (See also arch/mips/kernel/jazzdma.c)
- */
-#define VDMA_ERROR 0xffffffff
-
-/*
* VDMA pagetable entry description
*/
typedef volatile struct VDMA_PGTBL_ENTRY {
diff --git a/arch/mips/include/asm/jump_label.h b/arch/mips/include/asm/jump_label.h
index e776725..3185fd3 100644
--- a/arch/mips/include/asm/jump_label.h
+++ b/arch/mips/include/asm/jump_label.h
@@ -11,6 +11,7 @@
#ifndef __ASSEMBLY__
#include <linux/types.h>
+#include <asm/isa-rev.h>
#define JUMP_LABEL_NOP_SIZE 4
@@ -21,15 +22,20 @@
#endif
#ifdef CONFIG_CPU_MICROMIPS
-#define NOP_INSN "nop32"
+# define B_INSN "b32"
+# define J_INSN "j32"
+#elif MIPS_ISA_REV >= 6
+# define B_INSN "bc"
+# define J_INSN "bc"
#else
-#define NOP_INSN "nop"
+# define B_INSN "b"
+# define J_INSN "j"
#endif
static __always_inline bool arch_static_branch(struct static_key *key, bool branch)
{
- asm_volatile_goto("1:\t" NOP_INSN "\n\t"
- "nop\n\t"
+ asm_volatile_goto("1:\t" B_INSN " 2f\n\t"
+ "2:\t.insn\n\t"
".pushsection __jump_table, \"aw\"\n\t"
WORD_INSN " 1b, %l[l_yes], %0\n\t"
".popsection\n\t"
@@ -42,8 +48,7 @@
static __always_inline bool arch_static_branch_jump(struct static_key *key, bool branch)
{
- asm_volatile_goto("1:\tj %l[l_yes]\n\t"
- "nop\n\t"
+ asm_volatile_goto("1:\t" J_INSN " %l[l_yes]\n\t"
".pushsection __jump_table, \"aw\"\n\t"
WORD_INSN " 1b, %l[l_yes], %0\n\t"
".popsection\n\t"
diff --git a/arch/mips/include/asm/kexec.h b/arch/mips/include/asm/kexec.h
index 493a3cc..d6d5fa5 100644
--- a/arch/mips/include/asm/kexec.h
+++ b/arch/mips/include/asm/kexec.h
@@ -1,9 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* kexec.h for kexec
* Created by <nschichan@corp.free.fr> on Thu Oct 12 14:59:34 2006
- *
- * This source code is licensed under the GNU General Public License,
- * Version 2. See the file COPYING for more details.
*/
#ifndef _MIPS_KEXEC
@@ -12,11 +10,11 @@
#include <asm/stacktrace.h>
/* Maximum physical address we can use pages from */
-#define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000)
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
/* Maximum address we can reach in physical address mode */
-#define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000)
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
/* Maximum address we can use for the control code buffer */
-#define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000)
+#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
/* Reserve 3*4096 bytes for board-specific info */
#define KEXEC_CONTROL_PAGE_SIZE (4096 + 3*4096)
@@ -39,11 +37,12 @@
extern int (*_machine_kexec_prepare)(struct kimage *);
extern void (*_machine_kexec_shutdown)(void);
extern void (*_machine_crash_shutdown)(struct pt_regs *regs);
-extern void default_machine_crash_shutdown(struct pt_regs *regs);
+void default_machine_crash_shutdown(struct pt_regs *regs);
+void kexec_nonboot_cpu_jump(void);
+void kexec_reboot(void);
#ifdef CONFIG_SMP
extern const unsigned char kexec_smp_wait[];
extern unsigned long secondary_kexec_args[4];
-extern void (*relocated_kexec_smp_wait) (void *);
extern atomic_t kexec_ready_to_reboot;
extern void (*_crash_smp_send_stop)(void);
#endif
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
index a72dfbf..68b1e5d 100644
--- a/arch/mips/include/asm/kprobes.h
+++ b/arch/mips/include/asm/kprobes.h
@@ -1,22 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Kernel Probes (KProbes)
* include/asm-mips/kprobes.h
*
* Copyright 2006 Sony Corp.
* Copyright 2010 Cavium Networks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _ASM_KPROBES_H
@@ -53,6 +41,7 @@
#define kretprobe_blacklist_size 0
void arch_remove_kprobe(struct kprobe *p);
+int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
/* Architecture specific copy of original instruction*/
struct arch_specific_insn {
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 2c1c53d..41204a4 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -411,11 +411,12 @@
unsigned long temp;
do {
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __LL "%0, %1 \n"
" or %0, %2 \n"
" " __SC "%0, %1 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+m" (*reg)
: "r" (val));
} while (unlikely(!temp));
@@ -427,11 +428,12 @@
unsigned long temp;
do {
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __LL "%0, %1 \n"
" and %0, %2 \n"
" " __SC "%0, %1 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+m" (*reg)
: "r" (~val));
} while (unlikely(!temp));
@@ -444,12 +446,13 @@
unsigned long temp;
do {
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
" " __LL "%0, %1 \n"
" and %0, %2 \n"
" or %0, %3 \n"
" " __SC "%0, %1 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (temp), "+m" (*reg)
: "r" (~change), "r" (val & change));
} while (unlikely(!temp));
@@ -933,7 +936,7 @@
#define KVM_ARCH_WANT_MMU_NOTIFIER
int kvm_unmap_hva_range(struct kvm *kvm,
unsigned long start, unsigned long end);
-void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
+int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
@@ -1131,7 +1134,7 @@
static inline void kvm_arch_sync_events(struct kvm *kvm) {}
static inline void kvm_arch_free_memslot(struct kvm *kvm,
struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
-static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
+static inline void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) {}
static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
diff --git a/arch/mips/include/asm/lasat/lasat.h b/arch/mips/include/asm/lasat/lasat.h
index 9e32b4d..483be60 100644
--- a/arch/mips/include/asm/lasat/lasat.h
+++ b/arch/mips/include/asm/lasat/lasat.h
@@ -1,22 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* lasat.h
*
* Thomas Horsten <thh@lasat.com>
* Copyright (C) 2000 LASAT Networks A/S.
*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
* Configuration for LASAT boards, loads the appropriate include files.
*/
#ifndef _LASAT_H
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index ac8264e..02783e1 100644
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -35,13 +35,14 @@
unsigned long temp;
__asm__ __volatile__(
+ " .set push \n"
" .set arch=r4000 \n"
"1:" __LL "%1, %2 # local_add_return \n"
" addu %0, %1, %3 \n"
__SC "%0, %2 \n"
" beqzl %0, 1b \n"
" addu %0, %1, %3 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
: "Ir" (i), "m" (l->a.counter)
: "memory");
@@ -49,13 +50,14 @@
unsigned long temp;
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
"1:" __LL "%1, %2 # local_add_return \n"
" addu %0, %1, %3 \n"
__SC "%0, %2 \n"
" beqz %0, 1b \n"
" addu %0, %1, %3 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
: "Ir" (i), "m" (l->a.counter)
: "memory");
@@ -80,13 +82,14 @@
unsigned long temp;
__asm__ __volatile__(
+ " .set push \n"
" .set arch=r4000 \n"
"1:" __LL "%1, %2 # local_sub_return \n"
" subu %0, %1, %3 \n"
__SC "%0, %2 \n"
" beqzl %0, 1b \n"
" subu %0, %1, %3 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
: "Ir" (i), "m" (l->a.counter)
: "memory");
@@ -94,13 +97,14 @@
unsigned long temp;
__asm__ __volatile__(
+ " .set push \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
"1:" __LL "%1, %2 # local_sub_return \n"
" subu %0, %1, %3 \n"
__SC "%0, %2 \n"
" beqz %0, 1b \n"
" subu %0, %1, %3 \n"
- " .set mips0 \n"
+ " .set pop \n"
: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
: "Ir" (i), "m" (l->a.counter)
: "memory");
diff --git a/arch/mips/include/asm/maar.h b/arch/mips/include/asm/maar.h
index 1e0da80..6908b93 100644
--- a/arch/mips/include/asm/maar.h
+++ b/arch/mips/include/asm/maar.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2014 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_MIPS_MAAR_H__
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index 468cbd6..dd09c3b 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -1,20 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __AR7_H__
diff --git a/arch/mips/include/asm/mach-ar7/prom.h b/arch/mips/include/asm/mach-ar7/prom.h
index 088f61f..9e1d20b 100644
--- a/arch/mips/include/asm/mach-ar7/prom.h
+++ b/arch/mips/include/asm/mach-ar7/prom.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006, 2007 Florian Fainelli <florian@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __PROM_H__
diff --git a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
index e6a8108..95a0b58 100644
--- a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Atheros AR231x/AR531x SoC specific CPU feature overrides
*
@@ -6,11 +7,6 @@
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
*/
#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 284b4fa..1f9e571 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Atheros AR71XX/AR724X/AR913X SoC register definitions
*
@@ -6,10 +7,6 @@
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*/
#ifndef __ASM_MACH_AR71XX_REGS_H
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
index c2917b3..cacf354 100644
--- a/arch/mips/include/asm/mach-ath79/ar933x_uart.h
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Atheros AR933X UART defines
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*/
#ifndef __AR933X_UART_H
@@ -27,8 +24,8 @@
#define AR933X_UART_CS_PARITY_S 0
#define AR933X_UART_CS_PARITY_M 0x3
#define AR933X_UART_CS_PARITY_NONE 0
-#define AR933X_UART_CS_PARITY_ODD 1
-#define AR933X_UART_CS_PARITY_EVEN 2
+#define AR933X_UART_CS_PARITY_ODD 2
+#define AR933X_UART_CS_PARITY_EVEN 3
#define AR933X_UART_CS_IF_MODE_S 2
#define AR933X_UART_CS_IF_MODE_M 0x3
#define AR933X_UART_CS_IF_MODE_NONE 0
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 73dcd63..70cda74 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Atheros AR71XX/AR724X/AR913X common definitions
*
@@ -5,10 +6,6 @@
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*/
#ifndef __ASM_MACH_ATH79_H
@@ -178,8 +175,4 @@
void ath79_device_reset_set(u32 mask);
void ath79_device_reset_clear(u32 mask);
-void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
-void ath79_misc_irq_init(void __iomem *regs, int irq,
- int irq_base, bool is_ar71xx);
-
#endif /* __ASM_MACH_ATH79_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
deleted file mode 100644
index aa71216..0000000
--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller
- *
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#ifndef _ATH79_SPI_PLATFORM_H
-#define _ATH79_SPI_PLATFORM_H
-
-struct ath79_spi_platform_data {
- unsigned bus_num;
- unsigned num_chipselect;
-};
-
-#endif /* _ATH79_SPI_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
index 026ad90..e7c972f 100644
--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Atheros AR71XX/AR724X/AR913X specific CPU feature overrides
*
@@ -7,11 +8,6 @@
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
*/
#ifndef __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 5c9ca76..2df1abf 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -1,10 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*/
#ifndef __ASM_MACH_ATH79_IRQ_H
#define __ASM_MACH_ATH79_IRQ_H
diff --git a/arch/mips/include/asm/mach-ath79/kernel-entry-init.h b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h
index d8d046b..88db67b 100644
--- a/arch/mips/include/asm/mach-ath79/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-ath79/kernel-entry-init.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Atheros AR71XX/AR724X/AR913X specific kernel entry setup
*
* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
*/
#ifndef __ASM_MACH_ATH79_KERNEL_ENTRY_H
#define __ASM_MACH_ATH79_KERNEL_ENTRY_H
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index f439cf9..ecfbb5a 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -75,10 +75,12 @@
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 0
+#define cpu_tcache_line_size() 0
#define cpu_has_perf_cntr_intr_bit 0
#define cpu_has_vz 0
#define cpu_has_msa 0
+#define cpu_has_ufr 0
#define cpu_has_fre 0
#define cpu_has_cdmm 0
#define cpu_has_small_pages 0
@@ -88,5 +90,6 @@
#define cpu_has_badinstr 0
#define cpu_has_badinstrp 0
#define cpu_has_contextconfig 0
+#define cpu_has_perf 0
#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-au1x00/ioremap.h b/arch/mips/include/asm/mach-au1x00/ioremap.h
index 99fea1f..f6877ed 100644
--- a/arch/mips/include/asm/mach-au1x00/ioremap.h
+++ b/arch/mips/include/asm/mach-au1x00/ioremap.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/mach-au1x00/ioremap.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MACH_AU1X00_IOREMAP_H
#define __ASM_MACH_AU1X00_IOREMAP_H
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index 71e4096..d7f1ef2 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_BCM47XX_H
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
index 0ef8893..f879be3 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
@@ -98,6 +98,7 @@
BCM47XX_BOARD_MOTOROLA_WR850GP,
BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
+ BCM47XX_BOARD_NETGEAR_R6200_V1,
BCM47XX_BOARD_NETGEAR_WGR614V8,
BCM47XX_BOARD_NETGEAR_WGR614V9,
BCM47XX_BOARD_NETGEAR_WGR614_V10,
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h
deleted file mode 100644
index 4e49707..0000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __BCM63XX_DSP_H
-#define __BCM63XX_DSP_H
-
-struct bcm63xx_dsp_platform_data {
- unsigned gpio_rst;
- unsigned gpio_int;
- unsigned cs;
- unsigned ext_irq;
-};
-
-int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd);
-
-#endif /* __BCM63XX_DSP_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index 5e5b1bc..830f53f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -7,7 +7,6 @@
#include <linux/leds.h>
#include <bcm63xx_dev_enet.h>
#include <bcm63xx_dev_usb_usbd.h>
-#include <bcm63xx_dev_dsp.h>
/*
* flash mapping
@@ -31,7 +30,6 @@
unsigned int has_ohci0:1;
unsigned int has_ehci0:1;
unsigned int has_usbd:1;
- unsigned int has_dsp:1;
unsigned int has_uart0:1;
unsigned int has_uart1:1;
@@ -43,9 +41,6 @@
/* USB config */
struct bcm63xx_usbd_platform_data usbd;
- /* DSP config */
- struct bcm63xx_dsp_platform_data dsp;
-
/* GPIO LEDs */
struct gpio_led leds[5];
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index a4f7986..513270c 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -45,7 +45,6 @@
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_64bits 1
#define cpu_has_octeon_cache 1
-#define cpu_has_saa octeon_has_saa()
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
#define cpu_has_mips64r1 1
@@ -60,7 +59,6 @@
#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
-#define ARCH_HAS_IRQ_PER_CPU 1
#define ARCH_HAS_SPINLOCK_PREFETCH 1
#define spin_lock_prefetch(x) prefetch(x)
#define PREFETCH_STRIDE 128
@@ -73,13 +71,6 @@
#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
#endif
-static inline int octeon_has_saa(void)
-{
- int id;
- asm volatile ("mfc0 %0, $15,0" : "=r" (id));
- return id >= 0x000d0300;
-}
-
/*
* The last 256MB are reserved for device to device mappings and the
* BAR1 hole.
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 35c80be..2421411 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -12,7 +12,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-cobalt/mach-gt64120.h b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
index 6fe475b..ddb968a 100644
--- a/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
+++ b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _COBALT_MACH_GT64120_H
#define _COBALT_MACH_GT64120_H
diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
index 2ec1023..00beb69 100644
--- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
@@ -1,13 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* CPU feature overrides for DECstation systems. Two variations
* are generally applicable.
*
* Copyright (C) 2013 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H
@@ -36,7 +32,6 @@
#define cpu_has_vtag_icache 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_pindexed_dcache 0
-#define cpu_has_local_ebase 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_mips_4 0
#define cpu_has_mips_5 0
diff --git a/arch/mips/include/asm/mach-dec/mc146818rtc.h b/arch/mips/include/asm/mach-dec/mc146818rtc.h
index 6724e99..d4614e2 100644
--- a/arch/mips/include/asm/mach-dec/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-dec/mc146818rtc.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* RTC definitions for DECstation style attached Dallas DS1287 chip.
*
* Copyright (C) 1998, 2001 by Ralf Baechle
* Copyright (C) 1998 by Harald Koerfgen
* Copyright (C) 2002, 2005 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_RTC_DEC_H
#define __ASM_MIPS_DEC_RTC_DEC_H
diff --git a/arch/mips/include/asm/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h
index 513371f..4e36ea2 100644
--- a/arch/mips/include/asm/mach-generic/ioremap.h
+++ b/arch/mips/include/asm/mach-generic/ioremap.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/mach-generic/ioremap.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MACH_GENERIC_IOREMAP_H
#define __ASM_MACH_GENERIC_IOREMAP_H
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index a1bc2e7..f0f4a35 100644
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -11,7 +11,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index fba6405..b48eb4a 100644
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -15,7 +15,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 1
#define R4600_V1_HIT_CACHEOP_WAR 1
#define R4600_V2_HIT_CACHEOP_WAR 1
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-ip27/irq.h b/arch/mips/include/asm/mach-ip27/irq.h
index b0b7261..fd91c58 100644
--- a/arch/mips/include/asm/mach-ip27/irq.h
+++ b/arch/mips/include/asm/mach-ip27/irq.h
@@ -10,13 +10,15 @@
#ifndef __ASM_MACH_IP27_IRQ_H
#define __ASM_MACH_IP27_IRQ_H
-/*
- * A hardwired interrupt number is completely stupid for this system - a
- * large configuration might have thousands if not tenthousands of
- * interrupts.
- */
#define NR_IRQS 256
#include_next <irq.h>
+#define IP27_HUB_PEND0_IRQ (MIPS_CPU_IRQ_BASE + 2)
+#define IP27_HUB_PEND1_IRQ (MIPS_CPU_IRQ_BASE + 3)
+#define IP27_RT_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 4)
+
+#define IP27_HUB_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
+#define IP27_HUB_IRQ_COUNT 128
+
#endif /* __ASM_MACH_IP27_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ip27/mmzone.h b/arch/mips/include/asm/mach-ip27/mmzone.h
index 2ed3094..1cd6a23 100644
--- a/arch/mips/include/asm/mach-ip27/mmzone.h
+++ b/arch/mips/include/asm/mach-ip27/mmzone.h
@@ -8,20 +8,11 @@
#define pa_to_nid(addr) NASID_TO_COMPACT_NODEID(NASID_GET(addr))
-#define LEVELS_PER_SLICE 128
-
-struct slice_data {
- unsigned long irq_enable_mask[2];
- int level_to_irq[LEVELS_PER_SLICE];
-};
-
struct hub_data {
kern_vars_t kern_vars;
DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
cpumask_t h_cpus;
unsigned long slice_map;
- unsigned long irq_alloc_mask[2];
- struct slice_data slice[2];
};
struct node_data {
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index 42ea131..965f079 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -7,18 +7,9 @@
#include <asm/mmzone.h>
struct cpuinfo_ip27 {
-// cpuid_t p_cpuid; /* PROM assigned cpuid */
cnodeid_t p_nodeid; /* my node ID in compact-id-space */
nasid_t p_nasid; /* my node ID in numa-as-id-space */
unsigned char p_slice; /* Physical position on node board */
-#if 0
- unsigned long loops_per_sec;
- unsigned long ipi_count;
- unsigned long irq_attempt[NR_IRQS];
- unsigned long smp_local_irq_count;
- unsigned long prof_multiplier;
- unsigned long prof_counter;
-#endif
};
extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
@@ -30,7 +21,7 @@
struct pci_bus;
extern int pcibus_to_node(struct pci_bus *);
-#define cpumask_of_pcibus(bus) (cpu_online_mask)
+#define cpumask_of_pcibus(bus) (cpumask_of_node(pcibus_to_node(bus)))
extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 4ee0e4b..ef3efce 100644
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -11,7 +11,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 4821c7b..61cd673 100644
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -11,7 +11,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 9807ecd..e77b9d1 100644
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -11,7 +11,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h
deleted file mode 100644
index 104d2df..0000000
--- a/arch/mips/include/asm/mach-jz4740/clock.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __ASM_JZ4740_CLOCK_H__
-#define __ASM_JZ4740_CLOCK_H__
-
-enum jz4740_wait_mode {
- JZ4740_WAIT_MODE_IDLE,
- JZ4740_WAIT_MODE_SLEEP,
-};
-
-void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
-
-void jz4740_clock_suspend(void);
-void jz4740_clock_resume(void);
-
-void jz4740_clock_udc_enable_auto_suspend(void);
-void jz4740_clock_udc_disable_auto_suspend(void);
-
-#endif
diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h
index 14ecc53..e5d2a53 100644
--- a/arch/mips/include/asm/mach-jz4740/dma.h
+++ b/arch/mips/include/asm/mach-jz4740/dma.h
@@ -1,16 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ7420/JZ4740 DMA definitions
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
*/
#ifndef __ASM_MACH_JZ4740_DMA_H__
diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h
deleted file mode 100644
index fd847c9..0000000
--- a/arch/mips/include/asm/mach-jz4740/gpio.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 GPIO pin definitions
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef _JZ_GPIO_H
-#define _JZ_GPIO_H
-
-#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
-#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
-#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
-#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
-
-#endif
diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
index 9b439fc..09c38ea 100644
--- a/arch/mips/include/asm/mach-jz4740/irq.h
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -1,16 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
*/
#ifndef __ASM_MACH_JZ4740_IRQ_H__
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_fb.h b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
deleted file mode 100644
index 6a50e6f..0000000
--- a/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __ASM_MACH_JZ4740_JZ4740_FB_H__
-#define __ASM_MACH_JZ4740_JZ4740_FB_H__
-
-#include <linux/fb.h>
-
-enum jz4740_fb_lcd_type {
- JZ_LCD_TYPE_GENERIC_16_BIT = 0,
- JZ_LCD_TYPE_GENERIC_18_BIT = 0 | (1 << 4),
- JZ_LCD_TYPE_SPECIAL_TFT_1 = 1,
- JZ_LCD_TYPE_SPECIAL_TFT_2 = 2,
- JZ_LCD_TYPE_SPECIAL_TFT_3 = 3,
- JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5,
- JZ_LCD_TYPE_INTERLACED_CCIR656 = 7,
- JZ_LCD_TYPE_SINGLE_COLOR_STN = 8,
- JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9,
- JZ_LCD_TYPE_DUAL_COLOR_STN = 10,
- JZ_LCD_TYPE_DUAL_MONOCHROME_STN = 11,
- JZ_LCD_TYPE_8BIT_SERIAL = 12,
-};
-
-#define JZ4740_FB_SPECIAL_TFT_CONFIG(start, stop) (((start) << 16) | (stop))
-
-/*
-* width: width of the lcd display in mm
-* height: height of the lcd display in mm
-* num_modes: size of modes
-* modes: list of valid video modes
-* bpp: bits per pixel for the lcd
-* lcd_type: lcd type
-*/
-
-struct jz4740_fb_platform_data {
- unsigned int width;
- unsigned int height;
-
- size_t num_modes;
- struct fb_videomode *modes;
-
- unsigned int bpp;
- enum jz4740_fb_lcd_type lcd_type;
-
- struct {
- uint32_t spl;
- uint32_t cls;
- uint32_t ps;
- uint32_t rev;
- } special_tft_config;
-
- unsigned pixclk_falling_edge:1;
- unsigned date_enable_active_low:1;
-};
-
-#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
deleted file mode 100644
index e9cc62c..0000000
--- a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __LINUX_MMC_JZ4740_MMC
-#define __LINUX_MMC_JZ4740_MMC
-
-struct jz4740_mmc_platform_data {
- int gpio_power;
- int gpio_card_detect;
- int gpio_read_only;
- unsigned card_detect_active_low:1;
- unsigned read_only_active_low:1;
- unsigned power_active_low:1;
-
- unsigned data_1bit:1;
-};
-
-#endif
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
deleted file mode 100644
index c0c932a..0000000
--- a/arch/mips/include/asm/mach-jz4740/platform.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 platform device definitions
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-
-#ifndef __JZ4740_PLATFORM_H
-#define __JZ4740_PLATFORM_H
-
-#include <linux/platform_device.h>
-
-extern struct platform_device jz4740_udc_device;
-extern struct platform_device jz4740_udc_xceiv_device;
-extern struct platform_device jz4740_mmc_device;
-extern struct platform_device jz4740_i2c_device;
-extern struct platform_device jz4740_nand_device;
-extern struct platform_device jz4740_framebuffer_device;
-extern struct platform_device jz4740_i2s_device;
-extern struct platform_device jz4740_pcm_device;
-extern struct platform_device jz4740_codec_device;
-extern struct platform_device jz4740_adc_device;
-extern struct platform_device jz4740_pwm_device;
-extern struct platform_device jz4740_dma_device;
-
-#endif
diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h
index 8750a1d..8a19cfe 100644
--- a/arch/mips/include/asm/mach-jz4740/timer.h
+++ b/arch/mips/include/asm/mach-jz4740/timer.h
@@ -1,16 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 platform timer support
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
*/
#ifndef __ASM_MACH_JZ4740_TIMER
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
index 096a100..f03c1c4 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Lantiq FALCON specific CPU feature overrides
*
@@ -6,11 +7,6 @@
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
*/
#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
index c6b63a4..6eeda90 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
*/
@@ -18,8 +16,6 @@
#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32)
#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
-#define MIPS_CPU_TIMER_IRQ 7
-
#define MAX_IM 5
#endif /* _FALCON_IRQ__ */
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
index 2caccd9..91d2bc0 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/irq.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
*/
diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index 8e9b022..5855ba1 100644
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index d750f93..6ceb028 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
index 17d2fdc..70ebb4d 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
diff --git a/arch/mips/include/asm/mach-lantiq/xway/irq.h b/arch/mips/include/asm/mach-lantiq/xway/irq.h
index 83e5f03..76ebbf6 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/irq.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
index 1410763..5f0d0ba 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
@@ -19,8 +17,6 @@
#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
-#define MIPS_CPU_TIMER_IRQ 7
-
#define MAX_IM 5
#endif
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 17b41bb..4790cfa 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Copyright (C) 2010 John Crispin <john@phrozen.org>
*/
diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
index 8441b26..8218a13 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
@@ -1,16 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2011 John Crispin <john@phrozen.org>
*/
diff --git a/arch/mips/include/asm/mach-loongson32/cpufreq.h b/arch/mips/include/asm/mach-loongson32/cpufreq.h
index 2f1ecb0..e422a32 100644
--- a/arch/mips/include/asm/mach-loongson32/cpufreq.h
+++ b/arch/mips/include/asm/mach-loongson32/cpufreq.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 CPUFreq platform support.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_CPUFREQ_H
diff --git a/arch/mips/include/asm/mach-loongson32/dma.h b/arch/mips/include/asm/mach-loongson32/dma.h
index ad1dec7..e917b3c 100644
--- a/arch/mips/include/asm/mach-loongson32/dma.h
+++ b/arch/mips/include/asm/mach-loongson32/dma.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 NAND platform support.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_DMA_H
diff --git a/arch/mips/include/asm/mach-loongson32/irq.h b/arch/mips/include/asm/mach-loongson32/irq.h
index 8c01b30..6115f02 100644
--- a/arch/mips/include/asm/mach-loongson32/irq.h
+++ b/arch/mips/include/asm/mach-loongson32/irq.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*
* IRQ mappings for Loongson 1
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_IRQ_H
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 84c28a8..eb3ddbe 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Register mappings for Loongson 1
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
diff --git a/arch/mips/include/asm/mach-loongson32/nand.h b/arch/mips/include/asm/mach-loongson32/nand.h
index e274912..aaf5ed1 100644
--- a/arch/mips/include/asm/mach-loongson32/nand.h
+++ b/arch/mips/include/asm/mach-loongson32/nand.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 NAND platform support.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_NAND_H
diff --git a/arch/mips/include/asm/mach-loongson32/platform.h b/arch/mips/include/asm/mach-loongson32/platform.h
index 8f8fa43..eb83e27 100644
--- a/arch/mips/include/asm/mach-loongson32/platform.h
+++ b/arch/mips/include/asm/mach-loongson32/platform.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_PLATFORM_H
@@ -17,19 +13,15 @@
extern struct platform_device ls1x_uart_pdev;
extern struct platform_device ls1x_cpufreq_pdev;
-extern struct platform_device ls1x_dma_pdev;
extern struct platform_device ls1x_eth0_pdev;
extern struct platform_device ls1x_eth1_pdev;
extern struct platform_device ls1x_ehci_pdev;
extern struct platform_device ls1x_gpio0_pdev;
extern struct platform_device ls1x_gpio1_pdev;
-extern struct platform_device ls1x_nand_pdev;
extern struct platform_device ls1x_rtc_pdev;
extern struct platform_device ls1x_wdt_pdev;
void __init ls1x_clk_init(void);
-void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata);
-void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata);
void __init ls1x_rtc_set_extclk(struct platform_device *pdev);
void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
diff --git a/arch/mips/include/asm/mach-loongson32/prom.h b/arch/mips/include/asm/mach-loongson32/prom.h
index a08503c..cb789f1 100644
--- a/arch/mips/include/asm/mach-loongson32/prom.h
+++ b/arch/mips/include/asm/mach-loongson32/prom.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_PROM_H
diff --git a/arch/mips/include/asm/mach-loongson32/regs-clk.h b/arch/mips/include/asm/mach-loongson32/regs-clk.h
index e5e8f11..98136fa 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-clk.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 Clock Register Definitions.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H
diff --git a/arch/mips/include/asm/mach-loongson32/regs-mux.h b/arch/mips/include/asm/mach-loongson32/regs-mux.h
index 4a0bdeb..95788a4 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-mux.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-mux.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 MUX Register Definitions.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_REGS_MUX_H
diff --git a/arch/mips/include/asm/mach-loongson32/regs-pwm.h b/arch/mips/include/asm/mach-loongson32/regs-pwm.h
index 4119600..ec870c8 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-pwm.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-pwm.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 PWM Register Definitions.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_REGS_PWM_H
diff --git a/arch/mips/include/asm/mach-loongson32/regs-rtc.h b/arch/mips/include/asm/mach-loongson32/regs-rtc.h
index e67fda2..a3d096b 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-rtc.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-rtc.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
*
* Loongson 1 RTC timer Register Definitions.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_REGS_RTC_H
diff --git a/arch/mips/include/asm/mach-loongson32/regs-wdt.h b/arch/mips/include/asm/mach-loongson32/regs-wdt.h
index 6644ab6..c6d345f 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-wdt.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-wdt.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
*
* Loongson 1 Watchdog Register Definitions.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON32_REGS_WDT_H
diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
index 581915c..4aca25f 100644
--- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -43,7 +43,6 @@
#define cpu_has_vint 0
#define cpu_has_vtag_icache 0
#define cpu_has_watch 1
-#define cpu_has_local_ebase 0
#ifdef CONFIG_CPU_LOONGSON3
#define cpu_has_wsbh 1
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
index 3127391..b5e288a 100644
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -11,6 +11,8 @@
#ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
#define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
+#include <asm/cpu.h>
+
/*
* Override macros used in arch/mips/kernel/head.S.
*/
@@ -26,12 +28,15 @@
mfc0 t0, CP0_PAGEGRAIN
or t0, (0x1 << 29)
mtc0 t0, CP0_PAGEGRAIN
-#ifdef CONFIG_LOONGSON3_ENHANCEMENT
/* Enable STFill Buffer */
+ mfc0 t0, CP0_PRID
+ andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
+ slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0)
+ bnez t0, 1f
mfc0 t0, CP0_CONFIG6
or t0, 0x100
mtc0 t0, CP0_CONFIG6
-#endif
+1:
_ehb
.set pop
#endif
@@ -52,12 +57,15 @@
mfc0 t0, CP0_PAGEGRAIN
or t0, (0x1 << 29)
mtc0 t0, CP0_PAGEGRAIN
-#ifdef CONFIG_LOONGSON3_ENHANCEMENT
/* Enable STFill Buffer */
+ mfc0 t0, CP0_PRID
+ andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
+ slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0)
+ bnez t0, 1f
mfc0 t0, CP0_CONFIG6
or t0, 0x100
mtc0 t0, CP0_CONFIG6
-#endif
+1:
_ehb
.set pop
#endif
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index d0ae5d5..694a585 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2009 Lemote, Inc.
* Author: Wu Zhangjin <wuzhangjin@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON64_LOONGSON_H
@@ -113,7 +109,7 @@
#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
-#if defined(CONFIG_HT_PCI)
+#ifdef CONFIG_CPU_LOONGSON3
#define LOONGSON_PCIIO_BASE loongson_sysconf.pci_io_base
#else
#define LOONGSON_PCIIO_BASE 0x1fd00000
diff --git a/arch/mips/include/asm/mach-loongson64/machine.h b/arch/mips/include/asm/mach-loongson64/machine.h
index c52549b..8ef7ea9 100644
--- a/arch/mips/include/asm/mach-loongson64/machine.h
+++ b/arch/mips/include/asm/mach-loongson64/machine.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2009 Lemote, Inc.
* Author: Wu Zhangjin <wuzhangjin@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON64_MACHINE_H
diff --git a/arch/mips/include/asm/mach-loongson64/mem.h b/arch/mips/include/asm/mach-loongson64/mem.h
index 75c16be..ce33c17 100644
--- a/arch/mips/include/asm/mach-loongson64/mem.h
+++ b/arch/mips/include/asm/mach-loongson64/mem.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2009 Lemote, Inc.
* Author: Wu Zhangjin <wuzhangjin@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON64_MEM_H
diff --git a/arch/mips/include/asm/mach-loongson64/mmzone.h b/arch/mips/include/asm/mach-loongson64/mmzone.h
index c9f7e23..62073d6 100644
--- a/arch/mips/include/asm/mach-loongson64/mmzone.h
+++ b/arch/mips/include/asm/mach-loongson64/mmzone.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2010 Loongson Inc. & Lemote Inc. &
* Institute of Computing Technology
* Author: Xiang Gao, gaoxiang@ict.ac.cn
* Huacai Chen, chenhc@lemote.com
* Xiaofu Meng, Shuangshuang Zhang
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef _ASM_MACH_MMZONE_H
#define _ASM_MACH_MMZONE_H
@@ -21,6 +17,7 @@
#define NODE3_ADDRSPACE_OFFSET 0x300000000000UL
#define pa_to_nid(addr) (((addr) & 0xf00000000000) >> NODE_ADDRSPACE_SHIFT)
+#define nid_to_addrbase(nid) ((nid) << NODE_ADDRSPACE_SHIFT)
#define LEVELS_PER_SLICE 128
diff --git a/arch/mips/include/asm/mach-loongson64/pci.h b/arch/mips/include/asm/mach-loongson64/pci.h
index 3401f55..97f807f 100644
--- a/arch/mips/include/asm/mach-loongson64/pci.h
+++ b/arch/mips/include/asm/mach-loongson64/pci.h
@@ -1,12 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
* Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
- *
- * This program is free software; you can redistribute it
- * and/or modify it under the terms of the GNU General
- * Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MACH_LOONGSON64_PCI_H_
diff --git a/arch/mips/include/asm/mach-malta/malta-dtshim.h b/arch/mips/include/asm/mach-malta/malta-dtshim.h
index d696a75..7c97b71 100644
--- a/arch/mips/include/asm/mach-malta/malta-dtshim.h
+++ b/arch/mips/include/asm/mach-malta/malta-dtshim.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_MALTA_DTSHIM_H__
diff --git a/arch/mips/include/asm/mach-malta/malta-pm.h b/arch/mips/include/asm/mach-malta/malta-pm.h
index 347b53d..2a5146d 100644
--- a/arch/mips/include/asm/mach-malta/malta-pm.h
+++ b/arch/mips/include/asm/mach-malta/malta-pm.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2014 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_MIPS_MACH_MALTA_PM_H__
diff --git a/arch/mips/include/asm/mach-malta/mc146818rtc.h b/arch/mips/include/asm/mach-malta/mc146818rtc.h
index ea612f3..e8cc7fd 100644
--- a/arch/mips/include/asm/mach-malta/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-malta/mc146818rtc.h
@@ -1,21 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2003 by Ralf Baechle
*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
* RTC routines for Malta style attached PIIX4 device, which contains a
* Motorola MC146818A-compatible Real Time Clock.
*/
diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index d068fc4..d62d2ff 100644
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -11,7 +11,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1
diff --git a/arch/mips/include/asm/mach-pic32/irq.h b/arch/mips/include/asm/mach-pic32/irq.h
index 864330c..d239694 100644
--- a/arch/mips/include/asm/mach-pic32/irq.h
+++ b/arch/mips/include/asm/mach-pic32/irq.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Joshua Henderson <joshua.henderson@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
*/
#ifndef __ASM_MACH_PIC32_IRQ_H
#define __ASM_MACH_PIC32_IRQ_H
diff --git a/arch/mips/include/asm/mach-pic32/pic32.h b/arch/mips/include/asm/mach-pic32/pic32.h
index ce52e91..53918a6 100644
--- a/arch/mips/include/asm/mach-pic32/pic32.h
+++ b/arch/mips/include/asm/mach-pic32/pic32.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Joshua Henderson <joshua.henderson@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
*/
#ifndef _ASM_MACH_PIC32_H
#define _ASM_MACH_PIC32_H
diff --git a/arch/mips/include/asm/mach-pic32/spaces.h b/arch/mips/include/asm/mach-pic32/spaces.h
index a1b9783..eb557b5 100644
--- a/arch/mips/include/asm/mach-pic32/spaces.h
+++ b/arch/mips/include/asm/mach-pic32/spaces.h
@@ -1,15 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Joshua Henderson <joshua.henderson@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
*/
#ifndef _ASM_MACH_PIC32_SPACES_H
#define _ASM_MACH_PIC32_SPACES_H
diff --git a/arch/mips/include/asm/mach-pistachio/irq.h b/arch/mips/include/asm/mach-pistachio/irq.h
index b94a09a..93bc380 100644
--- a/arch/mips/include/asm/mach-pistachio/irq.h
+++ b/arch/mips/include/asm/mach-pistachio/irq.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Pistachio IRQ setup
*
* Copyright (C) 2014 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
*/
#ifndef __ASM_MACH_PISTACHIO_IRQ_H
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h
index ac863e2..50de687 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_cic_int.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the MSP interrupt controller.
*
@@ -6,19 +7,6 @@
*
* ########################################################################
*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
* ########################################################################
*/
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_int.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_int.h
index 29f8bf7..55078b4 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_int.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_int.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the MSP interrupt handlers.
*
@@ -6,19 +7,6 @@
*
* ########################################################################
*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
* ########################################################################
*/
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_pci.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_pci.h
index 24948cc..5b2535e 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_pci.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_pci.h
@@ -1,23 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2000-2006 PMC-Sierra INC.
*
- * This program is free software; you can redistribute it
- * and/or modify it under the terms of the GNU General
- * Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be
- * useful, but WITHOUT ANY WARRANTY; without even the implied
- * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
- * PURPOSE. See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this program; if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
- * 02139, USA.
- *
* PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
* SOFTWARE.
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h
index 4d3052a..4120a01 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_prom.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* MIPS boards bootprom interface for the Linux kernel.
*
@@ -6,19 +7,6 @@
*
* ########################################################################
*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
* ########################################################################
*/
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h
index da3a8de..e2ce9be 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the address space, registers and register configuration
* (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
@@ -13,19 +14,6 @@
*
* ########################################################################
*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
* ########################################################################
*/
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_slp_int.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_slp_int.h
index 51a66dc..9a763eb 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_slp_int.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_slp_int.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Defines for the MSP interrupt controller.
*
@@ -6,19 +7,6 @@
*
* ########################################################################
*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
* ########################################################################
*/
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h
index fe1566f..3cc3edb 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h
@@ -1,23 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/******************************************************************
* Copyright (c) 2000-2007 PMC-Sierra INC.
*
- * This program is free software; you can redistribute it
- * and/or modify it under the terms of the GNU General
- * Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be
- * useful, but WITHOUT ANY WARRANTY; without even the implied
- * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
- * PURPOSE. See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this program; if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
- * 02139, USA.
- *
* PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
* SOFTWARE.
diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/war.h b/arch/mips/include/asm/mach-pmcs-msp71xx/war.h
index a60bf9d..31c546f 100644
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/war.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/war.h
@@ -11,7 +11,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h
index f192acf..85b5b8e 100644
--- a/arch/mips/include/asm/mach-pnx833x/gpio.h
+++ b/arch/mips/include/asm/mach-pnx833x/gpio.h
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* gpio.h: GPIO Support for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
#define __ASM_MIPS_MACH_PNX833X_GPIO_H
diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
index daa85ce..32d8063 100644
--- a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
+++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* irq.h: IRQ mappings for PNX833X.
@@ -5,20 +6,6 @@
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_MAPPING_H
diff --git a/arch/mips/include/asm/mach-pnx833x/irq.h b/arch/mips/include/asm/mach-pnx833x/irq.h
index 745114b..b7a6dab 100644
--- a/arch/mips/include/asm/mach-pnx833x/irq.h
+++ b/arch/mips/include/asm/mach-pnx833x/irq.h
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* irq.h: IRQ mappings for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_MIPS_MACH_PNX833X_IRQ_H
diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
index e6fc3a9..00bb67a 100644
--- a/arch/mips/include/asm/mach-pnx833x/pnx833x.h
+++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* pnx833x.h: Register mappings for PNX833X.
*
* Copyright 2008 NXP Semiconductors
* Chris Steel <chris.steel@nxp.com>
* Daniel Laird <daniel.j.laird@nxp.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H
#define __ASM_MIPS_MACH_PNX833X_PNX833X_H
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index 66af4cc..757ce53 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Parts of this file are based on Ralink's 2.6.21 BSP
*
diff --git a/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h
index f7bb8cf..6ea5908 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Ralink MT7620 specific CPU feature overrides
*
@@ -7,11 +8,6 @@
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
*/
#ifndef _MT7620_CPU_FEATURE_OVERRIDES_H
#define _MT7620_CPU_FEATURE_OVERRIDES_H
diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h
index a672e06..65483a4 100644
--- a/arch/mips/include/asm/mach-ralink/mt7621.h
+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Copyright (C) 2015 John Crispin <john@phrozen.org>
*/
diff --git a/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
index 15db1b3..e06f517 100644
--- a/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Ralink MT7621 specific CPU feature overrides
*
@@ -8,11 +9,6 @@
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
*/
#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H
#define _MT7621_CPU_FEATURE_OVERRIDES_H
diff --git a/arch/mips/include/asm/mach-ralink/pinmux.h b/arch/mips/include/asm/mach-ralink/pinmux.h
index ba8ac33..0483093 100644
--- a/arch/mips/include/asm/mach-ralink/pinmux.h
+++ b/arch/mips/include/asm/mach-ralink/pinmux.h
@@ -1,8 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- *
* Copyright (C) 2012 John Crispin <john@phrozen.org>
*/
diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
index b4e7dfa..9dbd9f0 100644
--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -1,13 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Ralink SoC register definitions
*
* Copyright (C) 2013 John Crispin <john@phrozen.org>
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*/
#ifndef _RALINK_REGS_H_
diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
index 25ae104..5d10178 100644
--- a/arch/mips/include/asm/mach-ralink/rt288x.h
+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Parts of this file are based on Ralink's 2.6.21 BSP
*
diff --git a/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
index 72fc106..9c06964 100644
--- a/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ralink/rt288x/cpu-feature-overrides.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Ralink RT288x specific CPU feature overrides
*
@@ -7,11 +8,6 @@
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
*/
#ifndef _RT288X_CPU_FEATURE_OVERRIDES_H
#define _RT288X_CPU_FEATURE_OVERRIDES_H
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index ac2d65c..b54619d 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -1,7 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*
* Parts of this file are based on Ralink's 2.6.21 BSP
*
diff --git a/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
index 917c286..2e423fd 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x/cpu-feature-overrides.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Ralink RT305x specific CPU feature overrides
*
@@ -7,11 +8,6 @@
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
*/
#ifndef _RT305X_CPU_FEATURE_OVERRIDES_H
#define _RT305X_CPU_FEATURE_OVERRIDES_H
diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h
index 0fbe6f9..565f254 100644
--- a/arch/mips/include/asm/mach-ralink/rt3883.h
+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Ralink RT3662/RT3883 SoC register definitions
*
* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
*/
#ifndef _RT3883_REGS_H_
diff --git a/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
index 181fbf4..7cee0e2 100644
--- a/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ralink/rt3883/cpu-feature-overrides.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Ralink RT3662/RT3883 specific CPU feature overrides
*
@@ -6,11 +7,6 @@
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
*/
#ifndef _RT3883_CPU_FEATURE_OVERRIDES_H
#define _RT3883_CPU_FEATURE_OVERRIDES_H
diff --git a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
index 6a1087e..bc46179 100644
--- a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* IDT RC32434 specific CPU feature overrides
*
@@ -6,21 +7,6 @@
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the
- * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA 02110-1301, USA.
*/
#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
index aac8ce8..d502673 100644
--- a/arch/mips/include/asm/mach-rc32434/rb.h
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -1,13 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*
* Copyright (C) 2004 IDT Inc.
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
@@ -71,12 +63,6 @@
struct net_device *dev;
};
-struct cf_device {
- int gpio_pin;
- void *dev;
- struct gendisk *gd;
-};
-
struct mpmc_device {
unsigned char state;
spinlock_t lock;
diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 1bfd489..af430d2 100644
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -11,7 +11,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1
diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index a3dde98..eca16d1 100644
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -15,7 +15,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 1
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 520f8fc..4755b61 100644
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -11,7 +11,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
diff --git a/arch/mips/include/asm/mach-tx39xx/ioremap.h b/arch/mips/include/asm/mach-tx39xx/ioremap.h
index 0874cd2..077b3c9 100644
--- a/arch/mips/include/asm/mach-tx39xx/ioremap.h
+++ b/arch/mips/include/asm/mach-tx39xx/ioremap.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/mach-tx39xx/ioremap.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MACH_TX39XX_IOREMAP_H
#define __ASM_MACH_TX39XX_IOREMAP_H
diff --git a/arch/mips/include/asm/mach-tx49xx/ioremap.h b/arch/mips/include/asm/mach-tx49xx/ioremap.h
index 4b6a844..c6b9e05 100644
--- a/arch/mips/include/asm/mach-tx49xx/ioremap.h
+++ b/arch/mips/include/asm/mach-tx49xx/ioremap.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/mach-tx49xx/ioremap.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MACH_TX49XX_IOREMAP_H
#define __ASM_MACH_TX49XX_IOREMAP_H
diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index a8e2c58..445abb4 100644
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -11,7 +11,6 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
diff --git a/arch/mips/include/asm/mach-xilfpga/irq.h b/arch/mips/include/asm/mach-xilfpga/irq.h
index 0132a5b..b8e93fa 100644
--- a/arch/mips/include/asm/mach-xilfpga/irq.h
+++ b/arch/mips/include/asm/mach-xilfpga/irq.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015 Imagination Technologies
* Author: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_MACH_XILFPGA_IRQ_H__
diff --git a/arch/mips/include/asm/machine.h b/arch/mips/include/asm/machine.h
index f83879d..29ca344 100644
--- a/arch/mips/include/asm/machine.h
+++ b/arch/mips/include/asm/machine.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2016 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_MACHINE_H__
diff --git a/arch/mips/include/asm/mips-boards/malta.h b/arch/mips/include/asm/mips-boards/malta.h
index fd97742..65de4fb 100644
--- a/arch/mips/include/asm/mips-boards/malta.h
+++ b/arch/mips/include/asm/mips-boards/malta.h
@@ -1,20 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
* Defines of the Malta board specific address-MAP, registers, etc.
*/
#ifndef __ASM_MIPS_BOARDS_MALTA_H
diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index 9e340be..e174bc7 100644
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -1,21 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2013 Imagination Technologies Ltd.
*
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
* Register definitions for Intel PIIX4 South Bridge Device.
*/
#ifndef __ASM_MIPS_BOARDS_PIIX4_H
diff --git a/arch/mips/include/asm/mips-boards/sim.h b/arch/mips/include/asm/mips-boards/sim.h
index b112fdc..ca37a4f 100644
--- a/arch/mips/include/asm/mips-boards/sim.h
+++ b/arch/mips/include/asm/mips-boards/sim.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
*/
#ifndef _ASM_MIPS_BOARDS_SIM_H
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 8bc5df4..aeae2ef 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2013 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_MIPS_CPS_H__
diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h
index b55e335..b54453f 100644
--- a/arch/mips/include/asm/mips-cpc.h
+++ b/arch/mips/include/asm/mips-cpc.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2013 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_MIPS_CPS_H__
diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h
index 8ad4a85..fd43d87 100644
--- a/arch/mips/include/asm/mips-cps.h
+++ b/arch/mips/include/asm/mips-cps.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2017 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_MIPS_CPS_H__
diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h
index 558059a..084cac1 100644
--- a/arch/mips/include/asm/mips-gic.h
+++ b/arch/mips/include/asm/mips-gic.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2017 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_MIPS_CPS_H__
@@ -315,6 +311,36 @@
}
/**
+ * mips_gic_vx_map_reg() - Return GIC_Vx_<intr>_MAP register offset
+ * @intr: A GIC local interrupt
+ *
+ * Determine the index of the GIC_VL_<intr>_MAP or GIC_VO_<intr>_MAP register
+ * within the block of GIC map registers. This is almost the same as the order
+ * of interrupts in the pending & mask registers, as used by enum
+ * mips_gic_local_interrupt, but moves the FDC interrupt & thus offsets the
+ * interrupts after it...
+ *
+ * Return: The map register index corresponding to @intr.
+ *
+ * The return value is suitable for use with the (read|write)_gic_v[lo]_map
+ * accessor functions.
+ */
+static inline unsigned int
+mips_gic_vx_map_reg(enum mips_gic_local_interrupt intr)
+{
+ /* WD, Compare & Timer are 1:1 */
+ if (intr <= GIC_LOCAL_INT_TIMER)
+ return intr;
+
+ /* FDC moves to after Timer... */
+ if (intr == GIC_LOCAL_INT_FDC)
+ return GIC_LOCAL_INT_TIMER + 1;
+
+ /* As a result everything else is offset by 1 */
+ return intr + 1;
+}
+
+/**
* gic_get_c0_compare_int() - Return cp0 count/compare interrupt virq
*
* Determine the virq number to use for the coprocessor 0 count/compare
diff --git a/arch/mips/include/asm/mips_machine.h b/arch/mips/include/asm/mips_machine.h
index 9d00aeb..4efecb7 100644
--- a/arch/mips/include/asm/mips_machine.h
+++ b/arch/mips/include/asm/mips_machine.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
*/
#ifndef __ASM_MIPS_MACHINE_H
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index 212336b..be4cf9d 100644
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -255,12 +255,12 @@
static inline void __raw_emt(void)
{
__asm__ __volatile__(
+ " .set push \n"
" .set noreorder \n"
" .set mips32r2 \n"
" .word 0x41600be1 # emt \n"
" ehb \n"
- " .set mips0 \n"
- " .set reorder");
+ " .set pop");
}
/* enable multi-threaded execution if previous suggested it should be.
@@ -277,9 +277,10 @@
static inline void ehb(void)
{
__asm__ __volatile__(
+ " .set push \n"
" .set mips32r2 \n"
" ehb \n"
- " .set mips0 \n");
+ " .set pop \n");
}
#define mftc0(rt,sel) \
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 01df9ad..bdbdc19 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -667,6 +667,7 @@
#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
+#define MIPS_CONF5_MI (_ULCAST_(1) << 17)
#define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
@@ -688,6 +689,9 @@
#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
+/* Ingenic Config7 bits */
+#define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
+
/* Config7 Bits specific to MIPS Technologies. */
/* Performance counters implemented Per TC */
@@ -1247,6 +1251,13 @@
ENC \
".endm")
+/* Instructions with 1 register operand & 1 immediate operand */
+#define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \
+ __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \
+ "parse_r __" #R1 ", \\" #R1 "\n\t" \
+ ENC \
+ ".endm")
+
/* Instructions with 2 register operands */
#define _ASM_MACRO_2R(OP, R1, R2, ENC) \
__asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
@@ -1345,9 +1356,10 @@
: "=r" (__res)); \
else \
__asm__ vol( \
+ ".set\tpush\n\t" \
".set\tmips32\n\t" \
"mfc0\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
+ ".set\tpop\n\t" \
: "=r" (__res)); \
__res; \
})
@@ -1358,15 +1370,17 @@
__res = __read_64bit_c0_split(source, sel, vol); \
else if (sel == 0) \
__asm__ vol( \
+ ".set\tpush\n\t" \
".set\tmips3\n\t" \
"dmfc0\t%0, " #source "\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: "=r" (__res)); \
else \
__asm__ vol( \
+ ".set\tpush\n\t" \
".set\tmips64\n\t" \
"dmfc0\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: "=r" (__res)); \
__res; \
})
@@ -1391,9 +1405,10 @@
: : "Jr" ((unsigned int)(value))); \
else \
__asm__ __volatile__( \
+ ".set\tpush\n\t" \
".set\tmips32\n\t" \
"mtc0\t%z0, " #register ", " #sel "\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: : "Jr" ((unsigned int)(value))); \
} while (0)
@@ -1403,15 +1418,17 @@
__write_64bit_c0_split(register, sel, value); \
else if (sel == 0) \
__asm__ __volatile__( \
+ ".set\tpush\n\t" \
".set\tmips3\n\t" \
"dmtc0\t%z0, " #register "\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: : "Jr" (value)); \
else \
__asm__ __volatile__( \
+ ".set\tpush\n\t" \
".set\tmips64\n\t" \
"dmtc0\t%z0, " #register ", " #sel "\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: : "Jr" (value)); \
} while (0)
@@ -1463,19 +1480,21 @@
local_irq_save(__flags); \
if (sel == 0) \
__asm__ vol( \
+ ".set\tpush\n\t" \
".set\tmips64\n\t" \
"dmfc0\t%L0, " #source "\n\t" \
"dsra\t%M0, %L0, 32\n\t" \
"sll\t%L0, %L0, 0\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: "=r" (__val)); \
else \
__asm__ vol( \
+ ".set\tpush\n\t" \
".set\tmips64\n\t" \
"dmfc0\t%L0, " #source ", " #sel "\n\t" \
"dsra\t%M0, %L0, 32\n\t" \
"sll\t%L0, %L0, 0\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: "=r" (__val)); \
local_irq_restore(__flags); \
\
@@ -1498,23 +1517,25 @@
: "+r" (__tmp)); \
else if (sel == 0) \
__asm__ __volatile__( \
+ ".set\tpush\n\t" \
".set\tmips64\n\t" \
"dsll\t%L0, %L0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
"dsll\t%M0, %M0, 32\n\t" \
"or\t%L0, %L0, %M0\n\t" \
"dmtc0\t%L0, " #source "\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: "+r" (__tmp)); \
else \
__asm__ __volatile__( \
+ ".set\tpush\n\t" \
".set\tmips64\n\t" \
"dsll\t%L0, %L0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
"dsll\t%M0, %M0, 32\n\t" \
"or\t%L0, %L0, %M0\n\t" \
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
- ".set\tmips0" \
+ ".set\tpop" \
: "+r" (__tmp)); \
local_irq_restore(__flags); \
} while (0)
@@ -1593,6 +1614,9 @@
#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
+#define read_c0_memorymapid() __read_32bit_c0_register($4, 5)
+#define write_c0_memorymapid(val) __write_32bit_c0_register($4, 5, val)
+
#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
@@ -2287,13 +2311,14 @@
_write_32bit_cp1_register(dest, val, )
#endif
-#ifdef HAVE_AS_DSP
+#ifdef TOOLCHAIN_SUPPORTS_DSP
#define rddsp(mask) \
({ \
unsigned int __dspctl; \
\
__asm__ __volatile__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" rddsp %0, %x1 \n" \
" .set pop \n" \
@@ -2306,6 +2331,7 @@
do { \
__asm__ __volatile__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" wrdsp %0, %x1 \n" \
" .set pop \n" \
@@ -2318,6 +2344,7 @@
long mflo0; \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac0 \n" \
" .set pop \n" \
@@ -2330,6 +2357,7 @@
long mflo1; \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac1 \n" \
" .set pop \n" \
@@ -2342,6 +2370,7 @@
long mflo2; \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac2 \n" \
" .set pop \n" \
@@ -2354,6 +2383,7 @@
long mflo3; \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mflo %0, $ac3 \n" \
" .set pop \n" \
@@ -2366,6 +2396,7 @@
long mfhi0; \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac0 \n" \
" .set pop \n" \
@@ -2378,6 +2409,7 @@
long mfhi1; \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac1 \n" \
" .set pop \n" \
@@ -2390,6 +2422,7 @@
long mfhi2; \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac2 \n" \
" .set pop \n" \
@@ -2402,6 +2435,7 @@
long mfhi3; \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mfhi %0, $ac3 \n" \
" .set pop \n" \
@@ -2414,6 +2448,7 @@
({ \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mtlo %0, $ac0 \n" \
" .set pop \n" \
@@ -2425,6 +2460,7 @@
({ \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mtlo %0, $ac1 \n" \
" .set pop \n" \
@@ -2436,6 +2472,7 @@
({ \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mtlo %0, $ac2 \n" \
" .set pop \n" \
@@ -2447,6 +2484,7 @@
({ \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mtlo %0, $ac3 \n" \
" .set pop \n" \
@@ -2458,6 +2496,7 @@
({ \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mthi %0, $ac0 \n" \
" .set pop \n" \
@@ -2469,6 +2508,7 @@
({ \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mthi %0, $ac1 \n" \
" .set pop \n" \
@@ -2480,6 +2520,7 @@
({ \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mthi %0, $ac2 \n" \
" .set pop \n" \
@@ -2491,6 +2532,7 @@
({ \
__asm__( \
" .set push \n" \
+ " .set " MIPS_ISA_LEVEL " \n" \
" .set dsp \n" \
" mthi %0, $ac3 \n" \
" .set pop \n" \
@@ -2774,6 +2816,7 @@
__BUILD_SET_C0(cause)
__BUILD_SET_C0(config)
__BUILD_SET_C0(config5)
+__BUILD_SET_C0(config7)
__BUILD_SET_C0(intcontrol)
__BUILD_SET_C0(intctl)
__BUILD_SET_C0(srsmap)
diff --git a/arch/mips/include/asm/mmiowb.h b/arch/mips/include/asm/mmiowb.h
new file mode 100644
index 0000000..a40824e
--- /dev/null
+++ b/arch/mips/include/asm/mmiowb.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_MMIOWB_H
+#define _ASM_MMIOWB_H
+
+#include <asm/io.h>
+
+#define mmiowb() iobarrier_w()
+
+#include <asm-generic/mmiowb.h>
+
+#endif /* _ASM_MMIOWB_H */
diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h
index 0740be7..5df0238 100644
--- a/arch/mips/include/asm/mmu.h
+++ b/arch/mips/include/asm/mmu.h
@@ -7,9 +7,12 @@
#include <linux/wait.h>
typedef struct {
- unsigned long asid[NR_CPUS];
+ union {
+ u64 asid[NR_CPUS];
+ atomic64_t mmid;
+ };
+
void *vdso;
- atomic_t fp_mode_switching;
/* lock to be held whilst modifying fp_bd_emupage_allocmap */
spinlock_t bd_emupage_lock;
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 9441456..cddead9 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -17,8 +17,10 @@
#include <linux/smp.h>
#include <linux/slab.h>
+#include <asm/barrier.h>
#include <asm/cacheflush.h>
#include <asm/dsemul.h>
+#include <asm/ginvt.h>
#include <asm/hazards.h>
#include <asm/tlbflush.h>
#include <asm-generic/mm_hooks.h>
@@ -73,22 +75,51 @@
#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
/*
+ * The ginvt instruction will invalidate wired entries when its type field
+ * targets anything other than the entire TLB. That means that if we were to
+ * allow the kernel to create wired entries with the MMID of current->active_mm
+ * then those wired entries could be invalidated when we later use ginvt to
+ * invalidate TLB entries with that MMID.
+ *
+ * In order to prevent ginvt from trashing wired entries, we reserve one MMID
+ * for use by the kernel when creating wired entries. This MMID will never be
+ * assigned to a struct mm, and we'll never target it with a ginvt instruction.
+ */
+#define MMID_KERNEL_WIRED 0
+
+/*
* All unused by hardware upper bits will be considered
* as a software asid extension.
*/
-static unsigned long asid_version_mask(unsigned int cpu)
+static inline u64 asid_version_mask(unsigned int cpu)
{
unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]);
- return ~(asid_mask | (asid_mask - 1));
+ return ~(u64)(asid_mask | (asid_mask - 1));
}
-static unsigned long asid_first_version(unsigned int cpu)
+static inline u64 asid_first_version(unsigned int cpu)
{
return ~asid_version_mask(cpu) + 1;
}
-#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
+static inline u64 cpu_context(unsigned int cpu, const struct mm_struct *mm)
+{
+ if (cpu_has_mmid)
+ return atomic64_read(&mm->context.mmid);
+
+ return mm->context.asid[cpu];
+}
+
+static inline void set_cpu_context(unsigned int cpu,
+ struct mm_struct *mm, u64 ctx)
+{
+ if (cpu_has_mmid)
+ atomic64_set(&mm->context.mmid, ctx);
+ else
+ mm->context.asid[cpu] = ctx;
+}
+
#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
#define cpu_asid(cpu, mm) \
(cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
@@ -97,23 +128,9 @@
{
}
-
-/* Normal, classic MIPS get_new_mmu_context */
-static inline void
-get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
-{
- unsigned long asid = asid_cache(cpu);
-
- if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) {
- if (cpu_has_vtag_icache)
- flush_icache_all();
- local_flush_tlb_all(); /* start new asid cycle */
- if (!asid) /* fix version if needed */
- asid = asid_first_version(cpu);
- }
-
- cpu_context(cpu, mm) = asid_cache(cpu) = asid;
-}
+extern void get_new_mmu_context(struct mm_struct *mm);
+extern void check_mmu_context(struct mm_struct *mm);
+extern void check_switch_mmu_context(struct mm_struct *mm);
/*
* Initialize the context related info for a new mm_struct
@@ -124,8 +141,12 @@
{
int i;
- for_each_possible_cpu(i)
- cpu_context(i, mm) = 0;
+ if (cpu_has_mmid) {
+ set_cpu_context(0, mm, 0);
+ } else {
+ for_each_possible_cpu(i)
+ set_cpu_context(i, mm, 0);
+ }
mm->context.bd_emupage_allocmap = NULL;
spin_lock_init(&mm->context.bd_emupage_lock);
@@ -142,11 +163,7 @@
local_irq_save(flags);
htw_stop();
- /* Check if our ASID is of an older version and thus invalid */
- if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu))
- get_new_mmu_context(next, cpu);
- write_c0_entryhi(cpu_asid(cpu, next));
- TLBMISS_HANDLER_SETUP_PGD(next->pgd);
+ check_switch_mmu_context(next);
/*
* Mark current->active_mm as not "active" anymore.
@@ -168,55 +185,55 @@
dsemul_mm_cleanup(mm);
}
+#define activate_mm(prev, next) switch_mm(prev, next, current)
#define deactivate_mm(tsk, mm) do { } while (0)
-/*
- * After we have set current->mm to a new value, this activates
- * the context for the new mm so we see the new mappings.
- */
static inline void
-activate_mm(struct mm_struct *prev, struct mm_struct *next)
+drop_mmu_context(struct mm_struct *mm)
{
unsigned long flags;
- unsigned int cpu = smp_processor_id();
+ unsigned int cpu;
+ u32 old_mmid;
+ u64 ctx;
local_irq_save(flags);
- htw_stop();
- /* Unconditionally get a new ASID. */
- get_new_mmu_context(next, cpu);
+ cpu = smp_processor_id();
+ ctx = cpu_context(cpu, mm);
- write_c0_entryhi(cpu_asid(cpu, next));
- TLBMISS_HANDLER_SETUP_PGD(next->pgd);
-
- /* mark mmu ownership change */
- cpumask_clear_cpu(cpu, mm_cpumask(prev));
- cpumask_set_cpu(cpu, mm_cpumask(next));
- htw_start();
-
- local_irq_restore(flags);
-}
-
-/*
- * If mm is currently active_mm, we can't really drop it. Instead,
- * we will get a new one for it.
- */
-static inline void
-drop_mmu_context(struct mm_struct *mm, unsigned cpu)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- htw_stop();
-
- if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
- get_new_mmu_context(mm, cpu);
+ if (!ctx) {
+ /* no-op */
+ } else if (cpu_has_mmid) {
+ /*
+ * Globally invalidating TLB entries associated with the MMID
+ * is pretty cheap using the GINVT instruction, so we'll do
+ * that rather than incur the overhead of allocating a new
+ * MMID. The latter would be especially difficult since MMIDs
+ * are global & other CPUs may be actively using ctx.
+ */
+ htw_stop();
+ old_mmid = read_c0_memorymapid();
+ write_c0_memorymapid(ctx & cpu_asid_mask(&cpu_data[cpu]));
+ mtc0_tlbw_hazard();
+ ginvt_mmid();
+ sync_ginv();
+ write_c0_memorymapid(old_mmid);
+ instruction_hazard();
+ htw_start();
+ } else if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
+ /*
+ * mm is currently active, so we can't really drop it.
+ * Instead we bump the ASID.
+ */
+ htw_stop();
+ get_new_mmu_context(mm);
write_c0_entryhi(cpu_asid(cpu, mm));
+ htw_start();
} else {
/* will get a new context next time */
- cpu_context(cpu, mm) = 0;
+ set_cpu_context(cpu, mm, 0);
}
- htw_start();
+
local_irq_restore(flags);
}
diff --git a/arch/mips/include/asm/mmzone.h b/arch/mips/include/asm/mmzone.h
index f085fba..b826b84 100644
--- a/arch/mips/include/asm/mmzone.h
+++ b/arch/mips/include/asm/mmzone.h
@@ -7,7 +7,18 @@
#define _ASM_MMZONE_H_
#include <asm/page.h>
-#include <mmzone.h>
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+# include <mmzone.h>
+#endif
+
+#ifndef pa_to_nid
+#define pa_to_nid(addr) 0
+#endif
+
+#ifndef nid_to_addrbase
+#define nid_to_addrbase(nid) 0
+#endif
#ifdef CONFIG_DISCONTIGMEM
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 6dc0b21..ed70994 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -103,22 +103,16 @@
#define MODULE_PROC_FAMILY "TX39XX "
#elif defined CONFIG_CPU_VR41XX
#define MODULE_PROC_FAMILY "VR41XX "
-#elif defined CONFIG_CPU_R4300
-#define MODULE_PROC_FAMILY "R4300 "
#elif defined CONFIG_CPU_R4X00
#define MODULE_PROC_FAMILY "R4X00 "
#elif defined CONFIG_CPU_TX49XX
#define MODULE_PROC_FAMILY "TX49XX "
#elif defined CONFIG_CPU_R5000
#define MODULE_PROC_FAMILY "R5000 "
-#elif defined CONFIG_CPU_R5432
-#define MODULE_PROC_FAMILY "R5432 "
#elif defined CONFIG_CPU_R5500
#define MODULE_PROC_FAMILY "R5500 "
#elif defined CONFIG_CPU_NEVADA
#define MODULE_PROC_FAMILY "NEVADA "
-#elif defined CONFIG_CPU_R8000
-#define MODULE_PROC_FAMILY "R8000 "
#elif defined CONFIG_CPU_R10000
#define MODULE_PROC_FAMILY "R10000 "
#elif defined CONFIG_CPU_RM7000
diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h
index b4f9577..e0a3dd5 100644
--- a/arch/mips/include/asm/msa.h
+++ b/arch/mips/include/asm/msa.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2013 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef _ASM_MSA_H
#define _ASM_MSA_H
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
index 542ee09..3635ab3 100644
--- a/arch/mips/include/asm/octeon/cvmx-agl-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -171,7 +171,6 @@
uint64_t reserved_38_63:26;
#endif
} cn52xx;
- struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
struct cvmx_agl_gmx_bad_reg_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_35_63:29;
@@ -199,13 +198,6 @@
uint64_t reserved_35_63:29;
#endif
} cn56xx;
- struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
- struct cvmx_agl_gmx_bad_reg_s cn61xx;
- struct cvmx_agl_gmx_bad_reg_s cn63xx;
- struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
- struct cvmx_agl_gmx_bad_reg_s cn66xx;
- struct cvmx_agl_gmx_bad_reg_s cn68xx;
- struct cvmx_agl_gmx_bad_reg_s cn68xxp1;
};
union cvmx_agl_gmx_bist {
@@ -228,15 +220,6 @@
uint64_t reserved_10_63:54;
#endif
} cn52xx;
- struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
- struct cvmx_agl_gmx_bist_cn52xx cn56xx;
- struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
- struct cvmx_agl_gmx_bist_s cn61xx;
- struct cvmx_agl_gmx_bist_s cn63xx;
- struct cvmx_agl_gmx_bist_s cn63xxp1;
- struct cvmx_agl_gmx_bist_s cn66xx;
- struct cvmx_agl_gmx_bist_s cn68xx;
- struct cvmx_agl_gmx_bist_s cn68xxp1;
};
union cvmx_agl_gmx_drv_ctl {
@@ -270,8 +253,6 @@
uint64_t reserved_49_63:15;
#endif
} s;
- struct cvmx_agl_gmx_drv_ctl_s cn52xx;
- struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
struct cvmx_agl_gmx_drv_ctl_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
@@ -289,7 +270,6 @@
uint64_t reserved_17_63:47;
#endif
} cn56xx;
- struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
};
union cvmx_agl_gmx_inf_mode {
@@ -305,10 +285,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_agl_gmx_inf_mode_s cn52xx;
- struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
- struct cvmx_agl_gmx_inf_mode_s cn56xx;
- struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
};
union cvmx_agl_gmx_prtx_cfg {
@@ -363,15 +339,6 @@
uint64_t reserved_6_63:58;
#endif
} cn52xx;
- struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
- struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
- struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
- struct cvmx_agl_gmx_prtx_cfg_s cn61xx;
- struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
- struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
- struct cvmx_agl_gmx_prtx_cfg_s cn66xx;
- struct cvmx_agl_gmx_prtx_cfg_s cn68xx;
- struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam0 {
@@ -383,16 +350,6 @@
uint64_t adr:64;
#endif
} s;
- struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
- struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
- struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx;
- struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
- struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx;
- struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx;
- struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam1 {
@@ -404,16 +361,6 @@
uint64_t adr:64;
#endif
} s;
- struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
- struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
- struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx;
- struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
- struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx;
- struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx;
- struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam2 {
@@ -425,16 +372,6 @@
uint64_t adr:64;
#endif
} s;
- struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
- struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
- struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx;
- struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
- struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx;
- struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx;
- struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam3 {
@@ -446,16 +383,6 @@
uint64_t adr:64;
#endif
} s;
- struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
- struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
- struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx;
- struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
- struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx;
- struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx;
- struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam4 {
@@ -467,16 +394,6 @@
uint64_t adr:64;
#endif
} s;
- struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
- struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
- struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx;
- struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
- struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx;
- struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx;
- struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam5 {
@@ -488,16 +405,6 @@
uint64_t adr:64;
#endif
} s;
- struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
- struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
- struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx;
- struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
- struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx;
- struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx;
- struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_adr_cam_en {
@@ -511,16 +418,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx;
- struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_adr_ctl {
@@ -538,16 +435,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
- struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
- struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx;
- struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
- struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx;
- struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx;
- struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_decision {
@@ -561,16 +448,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_agl_gmx_rxx_decision_s cn52xx;
- struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_decision_s cn56xx;
- struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_decision_s cn61xx;
- struct cvmx_agl_gmx_rxx_decision_s cn63xx;
- struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_decision_s cn66xx;
- struct cvmx_agl_gmx_rxx_decision_s cn68xx;
- struct cvmx_agl_gmx_rxx_decision_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_frm_chk {
@@ -627,15 +504,6 @@
uint64_t reserved_9_63:55;
#endif
} cn52xx;
- struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
- struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
- struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx;
- struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_frm_ctl {
@@ -700,15 +568,6 @@
uint64_t reserved_10_63:54;
#endif
} cn52xx;
- struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
- struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
- struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx;
- struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_frm_max {
@@ -722,16 +581,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
- struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
- struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_frm_max_s cn61xx;
- struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
- struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_frm_max_s cn66xx;
- struct cvmx_agl_gmx_rxx_frm_max_s cn68xx;
- struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_frm_min {
@@ -745,16 +594,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
- struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
- struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_frm_min_s cn61xx;
- struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
- struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_frm_min_s cn66xx;
- struct cvmx_agl_gmx_rxx_frm_min_s cn68xx;
- struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_ifg {
@@ -768,16 +607,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
- struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
- struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_ifg_s cn61xx;
- struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
- struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_ifg_s cn66xx;
- struct cvmx_agl_gmx_rxx_ifg_s cn68xx;
- struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_int_en {
@@ -872,15 +701,6 @@
uint64_t reserved_20_63:44;
#endif
} cn52xx;
- struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
- struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
- struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
- struct cvmx_agl_gmx_rxx_int_en_s cn61xx;
- struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
- struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_int_en_s cn66xx;
- struct cvmx_agl_gmx_rxx_int_en_s cn68xx;
- struct cvmx_agl_gmx_rxx_int_en_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_int_reg {
@@ -975,15 +795,6 @@
uint64_t reserved_20_63:44;
#endif
} cn52xx;
- struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
- struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
- struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
- struct cvmx_agl_gmx_rxx_int_reg_s cn61xx;
- struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
- struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_int_reg_s cn66xx;
- struct cvmx_agl_gmx_rxx_int_reg_s cn68xx;
- struct cvmx_agl_gmx_rxx_int_reg_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_jabber {
@@ -997,16 +808,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
- struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
- struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_jabber_s cn61xx;
- struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
- struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_jabber_s cn66xx;
- struct cvmx_agl_gmx_rxx_jabber_s cn68xx;
- struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_pause_drop_time {
@@ -1020,16 +821,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx;
- struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_rx_inbnd {
@@ -1047,12 +838,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx;
- struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
- struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx;
- struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx;
- struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_stats_ctl {
@@ -1066,16 +851,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
- struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
- struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx;
- struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
- struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx;
- struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx;
- struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs {
@@ -1089,16 +864,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
- struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
- struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx;
- struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
- struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx;
- struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx;
- struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs_ctl {
@@ -1112,16 +877,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx;
- struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs_dmac {
@@ -1135,16 +890,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx;
- struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_stats_octs_drp {
@@ -1158,16 +903,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx;
- struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts {
@@ -1181,16 +916,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_bad {
@@ -1204,16 +929,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_ctl {
@@ -1227,16 +942,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_dmac {
@@ -1250,16 +955,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_stats_pkts_drp {
@@ -1273,16 +968,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx;
- struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1;
};
union cvmx_agl_gmx_rxx_udd_skp {
@@ -1300,16 +985,6 @@
uint64_t reserved_9_63:55;
#endif
} s;
- struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
- struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
- struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
- struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
- struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx;
- struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
- struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
- struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx;
- struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx;
- struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1;
};
union cvmx_agl_gmx_rx_bp_dropx {
@@ -1323,16 +998,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
- struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
- struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
- struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
- struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx;
- struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
- struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
- struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx;
- struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx;
- struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1;
};
union cvmx_agl_gmx_rx_bp_offx {
@@ -1346,16 +1011,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
- struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
- struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
- struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
- struct cvmx_agl_gmx_rx_bp_offx_s cn61xx;
- struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
- struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
- struct cvmx_agl_gmx_rx_bp_offx_s cn66xx;
- struct cvmx_agl_gmx_rx_bp_offx_s cn68xx;
- struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1;
};
union cvmx_agl_gmx_rx_bp_onx {
@@ -1369,16 +1024,6 @@
uint64_t reserved_9_63:55;
#endif
} s;
- struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
- struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
- struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
- struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
- struct cvmx_agl_gmx_rx_bp_onx_s cn61xx;
- struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
- struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
- struct cvmx_agl_gmx_rx_bp_onx_s cn66xx;
- struct cvmx_agl_gmx_rx_bp_onx_s cn68xx;
- struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1;
};
union cvmx_agl_gmx_rx_prt_info {
@@ -1396,8 +1041,6 @@
uint64_t reserved_18_63:46;
#endif
} s;
- struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
- struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
struct cvmx_agl_gmx_rx_prt_info_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
@@ -1411,13 +1054,6 @@
uint64_t reserved_17_63:47;
#endif
} cn56xx;
- struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
- struct cvmx_agl_gmx_rx_prt_info_s cn61xx;
- struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
- struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
- struct cvmx_agl_gmx_rx_prt_info_s cn66xx;
- struct cvmx_agl_gmx_rx_prt_info_s cn68xx;
- struct cvmx_agl_gmx_rx_prt_info_s cn68xxp1;
};
union cvmx_agl_gmx_rx_tx_status {
@@ -1435,8 +1071,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
- struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
struct cvmx_agl_gmx_rx_tx_status_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_5_63:59;
@@ -1450,13 +1084,6 @@
uint64_t reserved_5_63:59;
#endif
} cn56xx;
- struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
- struct cvmx_agl_gmx_rx_tx_status_s cn61xx;
- struct cvmx_agl_gmx_rx_tx_status_s cn63xx;
- struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;
- struct cvmx_agl_gmx_rx_tx_status_s cn66xx;
- struct cvmx_agl_gmx_rx_tx_status_s cn68xx;
- struct cvmx_agl_gmx_rx_tx_status_s cn68xxp1;
};
union cvmx_agl_gmx_smacx {
@@ -1470,16 +1097,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_agl_gmx_smacx_s cn52xx;
- struct cvmx_agl_gmx_smacx_s cn52xxp1;
- struct cvmx_agl_gmx_smacx_s cn56xx;
- struct cvmx_agl_gmx_smacx_s cn56xxp1;
- struct cvmx_agl_gmx_smacx_s cn61xx;
- struct cvmx_agl_gmx_smacx_s cn63xx;
- struct cvmx_agl_gmx_smacx_s cn63xxp1;
- struct cvmx_agl_gmx_smacx_s cn66xx;
- struct cvmx_agl_gmx_smacx_s cn68xx;
- struct cvmx_agl_gmx_smacx_s cn68xxp1;
};
union cvmx_agl_gmx_stat_bp {
@@ -1495,16 +1112,6 @@
uint64_t reserved_17_63:47;
#endif
} s;
- struct cvmx_agl_gmx_stat_bp_s cn52xx;
- struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
- struct cvmx_agl_gmx_stat_bp_s cn56xx;
- struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
- struct cvmx_agl_gmx_stat_bp_s cn61xx;
- struct cvmx_agl_gmx_stat_bp_s cn63xx;
- struct cvmx_agl_gmx_stat_bp_s cn63xxp1;
- struct cvmx_agl_gmx_stat_bp_s cn66xx;
- struct cvmx_agl_gmx_stat_bp_s cn68xx;
- struct cvmx_agl_gmx_stat_bp_s cn68xxp1;
};
union cvmx_agl_gmx_txx_append {
@@ -1524,16 +1131,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_agl_gmx_txx_append_s cn52xx;
- struct cvmx_agl_gmx_txx_append_s cn52xxp1;
- struct cvmx_agl_gmx_txx_append_s cn56xx;
- struct cvmx_agl_gmx_txx_append_s cn56xxp1;
- struct cvmx_agl_gmx_txx_append_s cn61xx;
- struct cvmx_agl_gmx_txx_append_s cn63xx;
- struct cvmx_agl_gmx_txx_append_s cn63xxp1;
- struct cvmx_agl_gmx_txx_append_s cn66xx;
- struct cvmx_agl_gmx_txx_append_s cn68xx;
- struct cvmx_agl_gmx_txx_append_s cn68xxp1;
};
union cvmx_agl_gmx_txx_clk {
@@ -1547,12 +1144,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_agl_gmx_txx_clk_s cn61xx;
- struct cvmx_agl_gmx_txx_clk_s cn63xx;
- struct cvmx_agl_gmx_txx_clk_s cn63xxp1;
- struct cvmx_agl_gmx_txx_clk_s cn66xx;
- struct cvmx_agl_gmx_txx_clk_s cn68xx;
- struct cvmx_agl_gmx_txx_clk_s cn68xxp1;
};
union cvmx_agl_gmx_txx_ctl {
@@ -1568,16 +1159,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_agl_gmx_txx_ctl_s cn52xx;
- struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
- struct cvmx_agl_gmx_txx_ctl_s cn56xx;
- struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
- struct cvmx_agl_gmx_txx_ctl_s cn61xx;
- struct cvmx_agl_gmx_txx_ctl_s cn63xx;
- struct cvmx_agl_gmx_txx_ctl_s cn63xxp1;
- struct cvmx_agl_gmx_txx_ctl_s cn66xx;
- struct cvmx_agl_gmx_txx_ctl_s cn68xx;
- struct cvmx_agl_gmx_txx_ctl_s cn68xxp1;
};
union cvmx_agl_gmx_txx_min_pkt {
@@ -1591,16 +1172,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
- struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
- struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
- struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
- struct cvmx_agl_gmx_txx_min_pkt_s cn61xx;
- struct cvmx_agl_gmx_txx_min_pkt_s cn63xx;
- struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;
- struct cvmx_agl_gmx_txx_min_pkt_s cn66xx;
- struct cvmx_agl_gmx_txx_min_pkt_s cn68xx;
- struct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1;
};
union cvmx_agl_gmx_txx_pause_pkt_interval {
@@ -1614,16 +1185,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx;
- struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1;
};
union cvmx_agl_gmx_txx_pause_pkt_time {
@@ -1637,16 +1198,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx;
- struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1;
};
union cvmx_agl_gmx_txx_pause_togo {
@@ -1660,16 +1211,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
- struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
- struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
- struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
- struct cvmx_agl_gmx_txx_pause_togo_s cn61xx;
- struct cvmx_agl_gmx_txx_pause_togo_s cn63xx;
- struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;
- struct cvmx_agl_gmx_txx_pause_togo_s cn66xx;
- struct cvmx_agl_gmx_txx_pause_togo_s cn68xx;
- struct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1;
};
union cvmx_agl_gmx_txx_pause_zero {
@@ -1683,16 +1224,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
- struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
- struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
- struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
- struct cvmx_agl_gmx_txx_pause_zero_s cn61xx;
- struct cvmx_agl_gmx_txx_pause_zero_s cn63xx;
- struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;
- struct cvmx_agl_gmx_txx_pause_zero_s cn66xx;
- struct cvmx_agl_gmx_txx_pause_zero_s cn68xx;
- struct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1;
};
union cvmx_agl_gmx_txx_soft_pause {
@@ -1706,16 +1237,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
- struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
- struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
- struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
- struct cvmx_agl_gmx_txx_soft_pause_s cn61xx;
- struct cvmx_agl_gmx_txx_soft_pause_s cn63xx;
- struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;
- struct cvmx_agl_gmx_txx_soft_pause_s cn66xx;
- struct cvmx_agl_gmx_txx_soft_pause_s cn68xx;
- struct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stat0 {
@@ -1729,16 +1250,6 @@
uint64_t xsdef:32;
#endif
} s;
- struct cvmx_agl_gmx_txx_stat0_s cn52xx;
- struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stat0_s cn56xx;
- struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stat0_s cn61xx;
- struct cvmx_agl_gmx_txx_stat0_s cn63xx;
- struct cvmx_agl_gmx_txx_stat0_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stat0_s cn66xx;
- struct cvmx_agl_gmx_txx_stat0_s cn68xx;
- struct cvmx_agl_gmx_txx_stat0_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stat1 {
@@ -1752,16 +1263,6 @@
uint64_t scol:32;
#endif
} s;
- struct cvmx_agl_gmx_txx_stat1_s cn52xx;
- struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stat1_s cn56xx;
- struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stat1_s cn61xx;
- struct cvmx_agl_gmx_txx_stat1_s cn63xx;
- struct cvmx_agl_gmx_txx_stat1_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stat1_s cn66xx;
- struct cvmx_agl_gmx_txx_stat1_s cn68xx;
- struct cvmx_agl_gmx_txx_stat1_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stat2 {
@@ -1775,16 +1276,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_agl_gmx_txx_stat2_s cn52xx;
- struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stat2_s cn56xx;
- struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stat2_s cn61xx;
- struct cvmx_agl_gmx_txx_stat2_s cn63xx;
- struct cvmx_agl_gmx_txx_stat2_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stat2_s cn66xx;
- struct cvmx_agl_gmx_txx_stat2_s cn68xx;
- struct cvmx_agl_gmx_txx_stat2_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stat3 {
@@ -1798,16 +1289,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_agl_gmx_txx_stat3_s cn52xx;
- struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stat3_s cn56xx;
- struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stat3_s cn61xx;
- struct cvmx_agl_gmx_txx_stat3_s cn63xx;
- struct cvmx_agl_gmx_txx_stat3_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stat3_s cn66xx;
- struct cvmx_agl_gmx_txx_stat3_s cn68xx;
- struct cvmx_agl_gmx_txx_stat3_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stat4 {
@@ -1821,16 +1302,6 @@
uint64_t hist1:32;
#endif
} s;
- struct cvmx_agl_gmx_txx_stat4_s cn52xx;
- struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stat4_s cn56xx;
- struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stat4_s cn61xx;
- struct cvmx_agl_gmx_txx_stat4_s cn63xx;
- struct cvmx_agl_gmx_txx_stat4_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stat4_s cn66xx;
- struct cvmx_agl_gmx_txx_stat4_s cn68xx;
- struct cvmx_agl_gmx_txx_stat4_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stat5 {
@@ -1844,16 +1315,6 @@
uint64_t hist3:32;
#endif
} s;
- struct cvmx_agl_gmx_txx_stat5_s cn52xx;
- struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stat5_s cn56xx;
- struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stat5_s cn61xx;
- struct cvmx_agl_gmx_txx_stat5_s cn63xx;
- struct cvmx_agl_gmx_txx_stat5_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stat5_s cn66xx;
- struct cvmx_agl_gmx_txx_stat5_s cn68xx;
- struct cvmx_agl_gmx_txx_stat5_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stat6 {
@@ -1867,16 +1328,6 @@
uint64_t hist5:32;
#endif
} s;
- struct cvmx_agl_gmx_txx_stat6_s cn52xx;
- struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stat6_s cn56xx;
- struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stat6_s cn61xx;
- struct cvmx_agl_gmx_txx_stat6_s cn63xx;
- struct cvmx_agl_gmx_txx_stat6_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stat6_s cn66xx;
- struct cvmx_agl_gmx_txx_stat6_s cn68xx;
- struct cvmx_agl_gmx_txx_stat6_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stat7 {
@@ -1890,16 +1341,6 @@
uint64_t hist7:32;
#endif
} s;
- struct cvmx_agl_gmx_txx_stat7_s cn52xx;
- struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stat7_s cn56xx;
- struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stat7_s cn61xx;
- struct cvmx_agl_gmx_txx_stat7_s cn63xx;
- struct cvmx_agl_gmx_txx_stat7_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stat7_s cn66xx;
- struct cvmx_agl_gmx_txx_stat7_s cn68xx;
- struct cvmx_agl_gmx_txx_stat7_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stat8 {
@@ -1913,16 +1354,6 @@
uint64_t mcst:32;
#endif
} s;
- struct cvmx_agl_gmx_txx_stat8_s cn52xx;
- struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stat8_s cn56xx;
- struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stat8_s cn61xx;
- struct cvmx_agl_gmx_txx_stat8_s cn63xx;
- struct cvmx_agl_gmx_txx_stat8_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stat8_s cn66xx;
- struct cvmx_agl_gmx_txx_stat8_s cn68xx;
- struct cvmx_agl_gmx_txx_stat8_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stat9 {
@@ -1936,16 +1367,6 @@
uint64_t undflw:32;
#endif
} s;
- struct cvmx_agl_gmx_txx_stat9_s cn52xx;
- struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stat9_s cn56xx;
- struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stat9_s cn61xx;
- struct cvmx_agl_gmx_txx_stat9_s cn63xx;
- struct cvmx_agl_gmx_txx_stat9_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stat9_s cn66xx;
- struct cvmx_agl_gmx_txx_stat9_s cn68xx;
- struct cvmx_agl_gmx_txx_stat9_s cn68xxp1;
};
union cvmx_agl_gmx_txx_stats_ctl {
@@ -1959,16 +1380,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
- struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
- struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
- struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
- struct cvmx_agl_gmx_txx_stats_ctl_s cn61xx;
- struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;
- struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;
- struct cvmx_agl_gmx_txx_stats_ctl_s cn66xx;
- struct cvmx_agl_gmx_txx_stats_ctl_s cn68xx;
- struct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1;
};
union cvmx_agl_gmx_txx_thresh {
@@ -1982,16 +1393,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_agl_gmx_txx_thresh_s cn52xx;
- struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
- struct cvmx_agl_gmx_txx_thresh_s cn56xx;
- struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
- struct cvmx_agl_gmx_txx_thresh_s cn61xx;
- struct cvmx_agl_gmx_txx_thresh_s cn63xx;
- struct cvmx_agl_gmx_txx_thresh_s cn63xxp1;
- struct cvmx_agl_gmx_txx_thresh_s cn66xx;
- struct cvmx_agl_gmx_txx_thresh_s cn68xx;
- struct cvmx_agl_gmx_txx_thresh_s cn68xxp1;
};
union cvmx_agl_gmx_tx_bp {
@@ -2005,8 +1406,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_agl_gmx_tx_bp_s cn52xx;
- struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
struct cvmx_agl_gmx_tx_bp_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
@@ -2016,13 +1415,6 @@
uint64_t reserved_1_63:63;
#endif
} cn56xx;
- struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
- struct cvmx_agl_gmx_tx_bp_s cn61xx;
- struct cvmx_agl_gmx_tx_bp_s cn63xx;
- struct cvmx_agl_gmx_tx_bp_s cn63xxp1;
- struct cvmx_agl_gmx_tx_bp_s cn66xx;
- struct cvmx_agl_gmx_tx_bp_s cn68xx;
- struct cvmx_agl_gmx_tx_bp_s cn68xxp1;
};
union cvmx_agl_gmx_tx_col_attempt {
@@ -2036,16 +1428,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
- struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
- struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
- struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
- struct cvmx_agl_gmx_tx_col_attempt_s cn61xx;
- struct cvmx_agl_gmx_tx_col_attempt_s cn63xx;
- struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;
- struct cvmx_agl_gmx_tx_col_attempt_s cn66xx;
- struct cvmx_agl_gmx_tx_col_attempt_s cn68xx;
- struct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1;
};
union cvmx_agl_gmx_tx_ifg {
@@ -2061,16 +1443,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_agl_gmx_tx_ifg_s cn52xx;
- struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
- struct cvmx_agl_gmx_tx_ifg_s cn56xx;
- struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
- struct cvmx_agl_gmx_tx_ifg_s cn61xx;
- struct cvmx_agl_gmx_tx_ifg_s cn63xx;
- struct cvmx_agl_gmx_tx_ifg_s cn63xxp1;
- struct cvmx_agl_gmx_tx_ifg_s cn66xx;
- struct cvmx_agl_gmx_tx_ifg_s cn68xx;
- struct cvmx_agl_gmx_tx_ifg_s cn68xxp1;
};
union cvmx_agl_gmx_tx_int_en {
@@ -2129,7 +1501,6 @@
uint64_t reserved_18_63:46;
#endif
} cn52xx;
- struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;
struct cvmx_agl_gmx_tx_int_en_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
@@ -2155,13 +1526,6 @@
uint64_t reserved_17_63:47;
#endif
} cn56xx;
- struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
- struct cvmx_agl_gmx_tx_int_en_s cn61xx;
- struct cvmx_agl_gmx_tx_int_en_s cn63xx;
- struct cvmx_agl_gmx_tx_int_en_s cn63xxp1;
- struct cvmx_agl_gmx_tx_int_en_s cn66xx;
- struct cvmx_agl_gmx_tx_int_en_s cn68xx;
- struct cvmx_agl_gmx_tx_int_en_s cn68xxp1;
};
union cvmx_agl_gmx_tx_int_reg {
@@ -2220,7 +1584,6 @@
uint64_t reserved_18_63:46;
#endif
} cn52xx;
- struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
struct cvmx_agl_gmx_tx_int_reg_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
@@ -2246,13 +1609,6 @@
uint64_t reserved_17_63:47;
#endif
} cn56xx;
- struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
- struct cvmx_agl_gmx_tx_int_reg_s cn61xx;
- struct cvmx_agl_gmx_tx_int_reg_s cn63xx;
- struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;
- struct cvmx_agl_gmx_tx_int_reg_s cn66xx;
- struct cvmx_agl_gmx_tx_int_reg_s cn68xx;
- struct cvmx_agl_gmx_tx_int_reg_s cn68xxp1;
};
union cvmx_agl_gmx_tx_jam {
@@ -2266,16 +1622,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_agl_gmx_tx_jam_s cn52xx;
- struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
- struct cvmx_agl_gmx_tx_jam_s cn56xx;
- struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
- struct cvmx_agl_gmx_tx_jam_s cn61xx;
- struct cvmx_agl_gmx_tx_jam_s cn63xx;
- struct cvmx_agl_gmx_tx_jam_s cn63xxp1;
- struct cvmx_agl_gmx_tx_jam_s cn66xx;
- struct cvmx_agl_gmx_tx_jam_s cn68xx;
- struct cvmx_agl_gmx_tx_jam_s cn68xxp1;
};
union cvmx_agl_gmx_tx_lfsr {
@@ -2289,16 +1635,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
- struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
- struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
- struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
- struct cvmx_agl_gmx_tx_lfsr_s cn61xx;
- struct cvmx_agl_gmx_tx_lfsr_s cn63xx;
- struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;
- struct cvmx_agl_gmx_tx_lfsr_s cn66xx;
- struct cvmx_agl_gmx_tx_lfsr_s cn68xx;
- struct cvmx_agl_gmx_tx_lfsr_s cn68xxp1;
};
union cvmx_agl_gmx_tx_ovr_bp {
@@ -2320,8 +1656,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
- struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
@@ -2339,13 +1673,6 @@
uint64_t reserved_9_63:55;
#endif
} cn56xx;
- struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
- struct cvmx_agl_gmx_tx_ovr_bp_s cn61xx;
- struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;
- struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;
- struct cvmx_agl_gmx_tx_ovr_bp_s cn66xx;
- struct cvmx_agl_gmx_tx_ovr_bp_s cn68xx;
- struct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1;
};
union cvmx_agl_gmx_tx_pause_pkt_dmac {
@@ -2359,16 +1686,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx;
- struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1;
};
union cvmx_agl_gmx_tx_pause_pkt_type {
@@ -2382,16 +1699,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx;
- struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1;
};
union cvmx_agl_prtx_ctl {
@@ -2447,12 +1754,6 @@
uint64_t drv_byp:1;
#endif
} s;
- struct cvmx_agl_prtx_ctl_s cn61xx;
- struct cvmx_agl_prtx_ctl_s cn63xx;
- struct cvmx_agl_prtx_ctl_s cn63xxp1;
- struct cvmx_agl_prtx_ctl_s cn66xx;
- struct cvmx_agl_prtx_ctl_s cn68xx;
- struct cvmx_agl_prtx_ctl_s cn68xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
index 1eef155..70f4a57 100644
--- a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
@@ -68,9 +68,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
- struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
- struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
};
union cvmx_asxx_gmii_rx_dat_set {
@@ -84,9 +81,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
- struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
- struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
};
union cvmx_asxx_int_en {
@@ -121,12 +115,6 @@
uint64_t reserved_11_63:53;
#endif
} cn30xx;
- struct cvmx_asxx_int_en_cn30xx cn31xx;
- struct cvmx_asxx_int_en_s cn38xx;
- struct cvmx_asxx_int_en_s cn38xxp2;
- struct cvmx_asxx_int_en_cn30xx cn50xx;
- struct cvmx_asxx_int_en_s cn58xx;
- struct cvmx_asxx_int_en_s cn58xxp1;
};
union cvmx_asxx_int_reg {
@@ -161,12 +149,6 @@
uint64_t reserved_11_63:53;
#endif
} cn30xx;
- struct cvmx_asxx_int_reg_cn30xx cn31xx;
- struct cvmx_asxx_int_reg_s cn38xx;
- struct cvmx_asxx_int_reg_s cn38xxp2;
- struct cvmx_asxx_int_reg_cn30xx cn50xx;
- struct cvmx_asxx_int_reg_s cn58xx;
- struct cvmx_asxx_int_reg_s cn58xxp1;
};
union cvmx_asxx_mii_rx_dat_set {
@@ -180,8 +162,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
- struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
};
union cvmx_asxx_prt_loop {
@@ -210,12 +190,6 @@
uint64_t reserved_7_63:57;
#endif
} cn30xx;
- struct cvmx_asxx_prt_loop_cn30xx cn31xx;
- struct cvmx_asxx_prt_loop_s cn38xx;
- struct cvmx_asxx_prt_loop_s cn38xxp2;
- struct cvmx_asxx_prt_loop_cn30xx cn50xx;
- struct cvmx_asxx_prt_loop_s cn58xx;
- struct cvmx_asxx_prt_loop_s cn58xxp1;
};
union cvmx_asxx_rld_bypass {
@@ -229,10 +203,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_asxx_rld_bypass_s cn38xx;
- struct cvmx_asxx_rld_bypass_s cn38xxp2;
- struct cvmx_asxx_rld_bypass_s cn58xx;
- struct cvmx_asxx_rld_bypass_s cn58xxp1;
};
union cvmx_asxx_rld_bypass_setting {
@@ -246,10 +216,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_asxx_rld_bypass_setting_s cn38xx;
- struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
- struct cvmx_asxx_rld_bypass_setting_s cn58xx;
- struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
};
union cvmx_asxx_rld_comp {
@@ -276,9 +242,6 @@
uint64_t reserved_8_63:56;
#endif
} cn38xx;
- struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
- struct cvmx_asxx_rld_comp_s cn58xx;
- struct cvmx_asxx_rld_comp_s cn58xxp1;
};
union cvmx_asxx_rld_data_drv {
@@ -294,10 +257,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_asxx_rld_data_drv_s cn38xx;
- struct cvmx_asxx_rld_data_drv_s cn38xxp2;
- struct cvmx_asxx_rld_data_drv_s cn58xx;
- struct cvmx_asxx_rld_data_drv_s cn58xxp1;
};
union cvmx_asxx_rld_fcram_mode {
@@ -311,8 +270,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_asxx_rld_fcram_mode_s cn38xx;
- struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
};
union cvmx_asxx_rld_nctl_strong {
@@ -326,10 +283,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_asxx_rld_nctl_strong_s cn38xx;
- struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
- struct cvmx_asxx_rld_nctl_strong_s cn58xx;
- struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
};
union cvmx_asxx_rld_nctl_weak {
@@ -343,10 +296,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_asxx_rld_nctl_weak_s cn38xx;
- struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
- struct cvmx_asxx_rld_nctl_weak_s cn58xx;
- struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
};
union cvmx_asxx_rld_pctl_strong {
@@ -360,10 +309,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_asxx_rld_pctl_strong_s cn38xx;
- struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
- struct cvmx_asxx_rld_pctl_strong_s cn58xx;
- struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
};
union cvmx_asxx_rld_pctl_weak {
@@ -377,10 +322,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_asxx_rld_pctl_weak_s cn38xx;
- struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
- struct cvmx_asxx_rld_pctl_weak_s cn58xx;
- struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
};
union cvmx_asxx_rld_setting {
@@ -411,9 +352,6 @@
uint64_t reserved_5_63:59;
#endif
} cn38xx;
- struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
- struct cvmx_asxx_rld_setting_s cn58xx;
- struct cvmx_asxx_rld_setting_s cn58xxp1;
};
union cvmx_asxx_rx_clk_setx {
@@ -427,13 +365,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_asxx_rx_clk_setx_s cn30xx;
- struct cvmx_asxx_rx_clk_setx_s cn31xx;
- struct cvmx_asxx_rx_clk_setx_s cn38xx;
- struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
- struct cvmx_asxx_rx_clk_setx_s cn50xx;
- struct cvmx_asxx_rx_clk_setx_s cn58xx;
- struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
};
union cvmx_asxx_rx_prt_en {
@@ -456,12 +387,6 @@
uint64_t reserved_3_63:61;
#endif
} cn30xx;
- struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
- struct cvmx_asxx_rx_prt_en_s cn38xx;
- struct cvmx_asxx_rx_prt_en_s cn38xxp2;
- struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
- struct cvmx_asxx_rx_prt_en_s cn58xx;
- struct cvmx_asxx_rx_prt_en_s cn58xxp1;
};
union cvmx_asxx_rx_wol {
@@ -477,8 +402,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_asxx_rx_wol_s cn38xx;
- struct cvmx_asxx_rx_wol_s cn38xxp2;
};
union cvmx_asxx_rx_wol_msk {
@@ -490,8 +413,6 @@
uint64_t msk:64;
#endif
} s;
- struct cvmx_asxx_rx_wol_msk_s cn38xx;
- struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
};
union cvmx_asxx_rx_wol_powok {
@@ -505,8 +426,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_asxx_rx_wol_powok_s cn38xx;
- struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
};
union cvmx_asxx_rx_wol_sig {
@@ -520,8 +439,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_asxx_rx_wol_sig_s cn38xx;
- struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
};
union cvmx_asxx_tx_clk_setx {
@@ -535,13 +452,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_asxx_tx_clk_setx_s cn30xx;
- struct cvmx_asxx_tx_clk_setx_s cn31xx;
- struct cvmx_asxx_tx_clk_setx_s cn38xx;
- struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
- struct cvmx_asxx_tx_clk_setx_s cn50xx;
- struct cvmx_asxx_tx_clk_setx_s cn58xx;
- struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
};
union cvmx_asxx_tx_comp_byp {
@@ -566,7 +476,6 @@
uint64_t reserved_9_63:55;
#endif
} cn30xx;
- struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
struct cvmx_asxx_tx_comp_byp_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
@@ -578,7 +487,6 @@
uint64_t reserved_8_63:56;
#endif
} cn38xx;
- struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
struct cvmx_asxx_tx_comp_byp_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
@@ -609,7 +517,6 @@
uint64_t reserved_13_63:51;
#endif
} cn58xx;
- struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
};
union cvmx_asxx_tx_hi_waterx {
@@ -632,12 +539,6 @@
uint64_t reserved_3_63:61;
#endif
} cn30xx;
- struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
- struct cvmx_asxx_tx_hi_waterx_s cn38xx;
- struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
- struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
- struct cvmx_asxx_tx_hi_waterx_s cn58xx;
- struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
};
union cvmx_asxx_tx_prt_en {
@@ -660,12 +561,6 @@
uint64_t reserved_3_63:61;
#endif
} cn30xx;
- struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
- struct cvmx_asxx_tx_prt_en_s cn38xx;
- struct cvmx_asxx_tx_prt_en_s cn38xxp2;
- struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
- struct cvmx_asxx_tx_prt_en_s cn58xx;
- struct cvmx_asxx_tx_prt_en_s cn58xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 72d2e40..689a82c 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -146,18 +146,6 @@
extern int cvmx_bootmem_init(void *mem_desc_ptr);
/**
- * Allocate a block of memory from the free list that was passed
- * to the application by the bootloader.
- * This is an allocate-only algorithm, so freeing memory is not possible.
- *
- * @size: Size in bytes of block to allocate
- * @alignment: Alignment required - must be power of 2
- *
- * Returns pointer to block of memory, NULL on error
- */
-extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
-
-/**
* Allocate a block of memory from the free list that was
* passed to the application by the bootloader at a specific
* address. This is an allocate-only algorithm, so
@@ -174,22 +162,6 @@
uint64_t alignment);
/**
- * Allocate a block of memory from the free list that was
- * passed to the application by the bootloader within a specified
- * address range. This is an allocate-only algorithm, so
- * freeing memory is not possible. Allocation will fail if
- * memory cannot be allocated in the requested range.
- *
- * @size: Size in bytes of block to allocate
- * @min_addr: defines the minimum address of the range
- * @max_addr: defines the maximum address of the range
- * @alignment: Alignment required - must be power of 2
- * Returns pointer to block of memory, NULL on error
- */
-extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
- uint64_t min_addr, uint64_t max_addr);
-
-/**
* Frees a previously allocated named bootmem block.
*
* @name: name of block to free
@@ -214,27 +186,6 @@
extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment,
char *name);
-
-
-/**
- * Allocate a block of memory from the free list that was passed
- * to the application by the bootloader, and assign it a name in the
- * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
- * Named blocks can later be freed.
- *
- * @size: Size in bytes of block to allocate
- * @address: Physical address to allocate memory at. If this
- * memory is not available, the allocation fails.
- * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN
- * bytes
- *
- * Returns a pointer to block of memory, NULL on error
- */
-extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
- char *name);
-
-
-
/**
* Allocate a block of memory from a specific range of the free list
* that was passed to the application by the bootloader, and assign it
@@ -351,33 +302,6 @@
char *name, uint32_t flags);
/**
- * Finds a named memory block by name.
- * Also used for finding an unused entry in the named block table.
- *
- * @name: Name of memory block to find. If NULL pointer given, then
- * finds unused descriptor, if available.
- *
- * @flags: Flags to control options for the allocation.
- *
- * Returns Pointer to memory block descriptor, NULL if not found.
- * If NULL returned when name parameter is NULL, then no memory
- * block descriptors are available.
- */
-struct cvmx_bootmem_named_block_desc *
-cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags);
-
-/**
- * Frees a named block.
- *
- * @name: name of block to free
- * @flags: flags for passing options
- *
- * Returns 0 on failure
- * 1 on success
- */
-int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags);
-
-/**
* Frees a block to the bootmem allocator list. This must
* be used with care, as the size provided must match the size
* of the block that was allocated, or the list will become
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
index 148bc9a..5babd88 100644
--- a/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ciu2-defs.h
@@ -28,7081 +28,21 @@
#ifndef __CVMX_CIU2_DEFS_H__
#define __CVMX_CIU2_DEFS_H__
-#define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull)
#define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_ACK_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull))
-#define CVMX_CIU2_INTR_RAM_ECC_CTL (CVMX_ADD_IO_SEG(0x0001070100102010ull))
-#define CVMX_CIU2_INTR_RAM_ECC_ST (CVMX_ADD_IO_SEG(0x0001070100102018ull))
-#define CVMX_CIU2_INTR_SLOWDOWN (CVMX_ADD_IO_SEG(0x0001070100102000ull))
-#define CVMX_CIU2_MSIRED_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_MSIRED_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_MSIRED_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_MSI_RCVX(offset) (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8)
-#define CVMX_CIU2_MSI_SELX(offset) (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8)
-#define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull)
#define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull)
-#define CVMX_CIU2_SUM_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8)
#define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8)
#define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8)
-#define CVMX_CIU2_SUM_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8)
-
-union cvmx_ciu2_ack_iox_int {
- uint64_t u64;
- struct cvmx_ciu2_ack_iox_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t ack:1;
-#else
- uint64_t ack:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_ciu2_ack_iox_int_s cn68xx;
- struct cvmx_ciu2_ack_iox_int_s cn68xxp1;
-};
-
-union cvmx_ciu2_ack_ppx_ip2 {
- uint64_t u64;
- struct cvmx_ciu2_ack_ppx_ip2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t ack:1;
-#else
- uint64_t ack:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_ciu2_ack_ppx_ip2_s cn68xx;
- struct cvmx_ciu2_ack_ppx_ip2_s cn68xxp1;
-};
-
-union cvmx_ciu2_ack_ppx_ip3 {
- uint64_t u64;
- struct cvmx_ciu2_ack_ppx_ip3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t ack:1;
-#else
- uint64_t ack:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_ciu2_ack_ppx_ip3_s cn68xx;
- struct cvmx_ciu2_ack_ppx_ip3_s cn68xxp1;
-};
-
-union cvmx_ciu2_ack_ppx_ip4 {
- uint64_t u64;
- struct cvmx_ciu2_ack_ppx_ip4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t ack:1;
-#else
- uint64_t ack:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_ciu2_ack_ppx_ip4_s cn68xx;
- struct cvmx_ciu2_ack_ppx_ip4_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_gpio {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_gpio_s cn68xx;
- struct cvmx_ciu2_en_iox_int_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_gpio_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_gpio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xx;
- struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_gpio_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_gpio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xx;
- struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_io {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_io_s cn68xx;
- struct cvmx_ciu2_en_iox_int_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_io_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_io_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xx;
- struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_io_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_io_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xx;
- struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mbox {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_mbox_s cn68xx;
- struct cvmx_ciu2_en_iox_int_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mbox_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_mbox_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xx;
- struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mbox_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_mbox_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xx;
- struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mem {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_mem_s cn68xx;
- struct cvmx_ciu2_en_iox_int_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mem_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_mem_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xx;
- struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mem_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_mem_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xx;
- struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mio {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_mio_s cn68xx;
- struct cvmx_ciu2_en_iox_int_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mio_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_mio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xx;
- struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_mio_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_mio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xx;
- struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_pkt {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_pkt_s cn68xx;
- struct cvmx_ciu2_en_iox_int_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_pkt_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_pkt_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_pkt_w1c_s cn68xx;
- struct cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_pkt_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_pkt_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_pkt_w1s_s cn68xx;
- struct cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_rml {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_rml_s cn68xx;
- struct cvmx_ciu2_en_iox_int_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_rml_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_rml_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_rml_w1c_s cn68xx;
- struct cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_rml_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_rml_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_rml_w1s_s cn68xx;
- struct cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wdog {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_wdog_s cn68xx;
- struct cvmx_ciu2_en_iox_int_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wdog_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_wdog_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xx;
- struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wdog_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_wdog_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xx;
- struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_wrkq_s cn68xx;
- struct cvmx_ciu2_en_iox_int_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wrkq_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_wrkq_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xx;
- struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_iox_int_wrkq_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_iox_int_wrkq_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xx;
- struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_gpio {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_gpio_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_gpio_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_io {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_io_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_io_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_io_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_io_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_io_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mbox {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mbox_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mbox_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mem {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mem_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mem_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mio {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mio_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_mio_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_pkt {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_pkt_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_pkt_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_pkt_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_rml {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_rml_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_rml_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_rml_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wdog {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wdog_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wdog_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wrkq_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip2_wrkq_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_gpio {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_gpio_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_gpio_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_io {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_io_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_io_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_io_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_io_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_io_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mbox {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mbox_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mbox_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mem {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mem_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mem_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mio {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mio_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_mio_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_pkt {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_pkt_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_pkt_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_pkt_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_rml {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_rml_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_rml_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_rml_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wdog {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wdog_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wdog_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wrkq_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip3_wrkq_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_gpio {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_gpio_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_gpio_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_io {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_io_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_io_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_io_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_io_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_io_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mbox {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mbox_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mbox_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mem {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mem_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mem_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mio {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mio_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_mio_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_pkt {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_pkt_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_pkt_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_pkt_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_rml {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_rml_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_rml_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_rml_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wdog {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wdog_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wdog_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wrkq_w1c {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xxp1;
-};
-
-union cvmx_ciu2_en_ppx_ip4_wrkq_w1s {
- uint64_t u64;
- struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xx;
- struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xxp1;
-};
-
-union cvmx_ciu2_intr_ciu_ready {
- uint64_t u64;
- struct cvmx_ciu2_intr_ciu_ready_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t ready:1;
-#else
- uint64_t ready:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_ciu2_intr_ciu_ready_s cn68xx;
- struct cvmx_ciu2_intr_ciu_ready_s cn68xxp1;
-};
-
-union cvmx_ciu2_intr_ram_ecc_ctl {
- uint64_t u64;
- struct cvmx_ciu2_intr_ram_ecc_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_3_63:61;
- uint64_t flip_synd:2;
- uint64_t ecc_ena:1;
-#else
- uint64_t ecc_ena:1;
- uint64_t flip_synd:2;
- uint64_t reserved_3_63:61;
-#endif
- } s;
- struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xx;
- struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xxp1;
-};
-
-union cvmx_ciu2_intr_ram_ecc_st {
- uint64_t u64;
- struct cvmx_ciu2_intr_ram_ecc_st_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_23_63:41;
- uint64_t addr:7;
- uint64_t reserved_13_15:3;
- uint64_t syndrom:9;
- uint64_t reserved_2_3:2;
- uint64_t dbe:1;
- uint64_t sbe:1;
-#else
- uint64_t sbe:1;
- uint64_t dbe:1;
- uint64_t reserved_2_3:2;
- uint64_t syndrom:9;
- uint64_t reserved_13_15:3;
- uint64_t addr:7;
- uint64_t reserved_23_63:41;
-#endif
- } s;
- struct cvmx_ciu2_intr_ram_ecc_st_s cn68xx;
- struct cvmx_ciu2_intr_ram_ecc_st_s cn68xxp1;
-};
-
-union cvmx_ciu2_intr_slowdown {
- uint64_t u64;
- struct cvmx_ciu2_intr_slowdown_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_3_63:61;
- uint64_t ctl:3;
-#else
- uint64_t ctl:3;
- uint64_t reserved_3_63:61;
-#endif
- } s;
- struct cvmx_ciu2_intr_slowdown_s cn68xx;
- struct cvmx_ciu2_intr_slowdown_s cn68xxp1;
-};
-
-union cvmx_ciu2_msi_rcvx {
- uint64_t u64;
- struct cvmx_ciu2_msi_rcvx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t msi_rcv:1;
-#else
- uint64_t msi_rcv:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_ciu2_msi_rcvx_s cn68xx;
- struct cvmx_ciu2_msi_rcvx_s cn68xxp1;
-};
-
-union cvmx_ciu2_msi_selx {
- uint64_t u64;
- struct cvmx_ciu2_msi_selx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_13_63:51;
- uint64_t pp_num:5;
- uint64_t reserved_6_7:2;
- uint64_t ip_num:2;
- uint64_t reserved_1_3:3;
- uint64_t en:1;
-#else
- uint64_t en:1;
- uint64_t reserved_1_3:3;
- uint64_t ip_num:2;
- uint64_t reserved_6_7:2;
- uint64_t pp_num:5;
- uint64_t reserved_13_63:51;
-#endif
- } s;
- struct cvmx_ciu2_msi_selx_s cn68xx;
- struct cvmx_ciu2_msi_selx_s cn68xxp1;
-};
-
-union cvmx_ciu2_msired_ppx_ip2 {
- uint64_t u64;
- struct cvmx_ciu2_msired_ppx_ip2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_21_63:43;
- uint64_t intr:1;
- uint64_t reserved_17_19:3;
- uint64_t newint:1;
- uint64_t reserved_8_15:8;
- uint64_t msi_num:8;
-#else
- uint64_t msi_num:8;
- uint64_t reserved_8_15:8;
- uint64_t newint:1;
- uint64_t reserved_17_19:3;
- uint64_t intr:1;
- uint64_t reserved_21_63:43;
-#endif
- } s;
- struct cvmx_ciu2_msired_ppx_ip2_s cn68xx;
- struct cvmx_ciu2_msired_ppx_ip2_s cn68xxp1;
-};
-
-union cvmx_ciu2_msired_ppx_ip3 {
- uint64_t u64;
- struct cvmx_ciu2_msired_ppx_ip3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_21_63:43;
- uint64_t intr:1;
- uint64_t reserved_17_19:3;
- uint64_t newint:1;
- uint64_t reserved_8_15:8;
- uint64_t msi_num:8;
-#else
- uint64_t msi_num:8;
- uint64_t reserved_8_15:8;
- uint64_t newint:1;
- uint64_t reserved_17_19:3;
- uint64_t intr:1;
- uint64_t reserved_21_63:43;
-#endif
- } s;
- struct cvmx_ciu2_msired_ppx_ip3_s cn68xx;
- struct cvmx_ciu2_msired_ppx_ip3_s cn68xxp1;
-};
-
-union cvmx_ciu2_msired_ppx_ip4 {
- uint64_t u64;
- struct cvmx_ciu2_msired_ppx_ip4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_21_63:43;
- uint64_t intr:1;
- uint64_t reserved_17_19:3;
- uint64_t newint:1;
- uint64_t reserved_8_15:8;
- uint64_t msi_num:8;
-#else
- uint64_t msi_num:8;
- uint64_t reserved_8_15:8;
- uint64_t newint:1;
- uint64_t reserved_17_19:3;
- uint64_t intr:1;
- uint64_t reserved_21_63:43;
-#endif
- } s;
- struct cvmx_ciu2_msired_ppx_ip4_s cn68xx;
- struct cvmx_ciu2_msired_ppx_ip4_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_gpio {
- uint64_t u64;
- struct cvmx_ciu2_raw_iox_int_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_raw_iox_int_gpio_s cn68xx;
- struct cvmx_ciu2_raw_iox_int_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_io {
- uint64_t u64;
- struct cvmx_ciu2_raw_iox_int_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_raw_iox_int_io_s cn68xx;
- struct cvmx_ciu2_raw_iox_int_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_mem {
- uint64_t u64;
- struct cvmx_ciu2_raw_iox_int_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_raw_iox_int_mem_s cn68xx;
- struct cvmx_ciu2_raw_iox_int_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_mio {
- uint64_t u64;
- struct cvmx_ciu2_raw_iox_int_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_raw_iox_int_mio_s cn68xx;
- struct cvmx_ciu2_raw_iox_int_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_pkt {
- uint64_t u64;
- struct cvmx_ciu2_raw_iox_int_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_raw_iox_int_pkt_s cn68xx;
- struct cvmx_ciu2_raw_iox_int_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_rml {
- uint64_t u64;
- struct cvmx_ciu2_raw_iox_int_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_raw_iox_int_rml_s cn68xx;
- struct cvmx_ciu2_raw_iox_int_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_wdog {
- uint64_t u64;
- struct cvmx_ciu2_raw_iox_int_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_raw_iox_int_wdog_s cn68xx;
- struct cvmx_ciu2_raw_iox_int_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_iox_int_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_raw_iox_int_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xx;
- struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_gpio {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip2_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_io {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip2_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_mem {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip2_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_mio {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip2_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_pkt {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip2_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip2_pkt_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_rml {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip2_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip2_rml_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_wdog {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip2_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip2_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip2_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_gpio {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip3_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_io {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip3_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_mem {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip3_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_mio {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip3_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_pkt {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip3_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip3_pkt_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_rml {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip3_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip3_rml_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_wdog {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip3_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip3_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip3_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_gpio {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip4_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_io {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip4_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_mem {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip4_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_mio {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip4_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_pkt {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip4_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip4_pkt_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_rml {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip4_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip4_rml_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_wdog {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip4_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_raw_ppx_ip4_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_raw_ppx_ip4_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xx;
- struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_gpio {
- uint64_t u64;
- struct cvmx_ciu2_src_iox_int_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_src_iox_int_gpio_s cn68xx;
- struct cvmx_ciu2_src_iox_int_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_io {
- uint64_t u64;
- struct cvmx_ciu2_src_iox_int_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_src_iox_int_io_s cn68xx;
- struct cvmx_ciu2_src_iox_int_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_mbox {
- uint64_t u64;
- struct cvmx_ciu2_src_iox_int_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_src_iox_int_mbox_s cn68xx;
- struct cvmx_ciu2_src_iox_int_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_mem {
- uint64_t u64;
- struct cvmx_ciu2_src_iox_int_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_src_iox_int_mem_s cn68xx;
- struct cvmx_ciu2_src_iox_int_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_mio {
- uint64_t u64;
- struct cvmx_ciu2_src_iox_int_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_src_iox_int_mio_s cn68xx;
- struct cvmx_ciu2_src_iox_int_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_pkt {
- uint64_t u64;
- struct cvmx_ciu2_src_iox_int_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_src_iox_int_pkt_s cn68xx;
- struct cvmx_ciu2_src_iox_int_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_rml {
- uint64_t u64;
- struct cvmx_ciu2_src_iox_int_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_src_iox_int_rml_s cn68xx;
- struct cvmx_ciu2_src_iox_int_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_wdog {
- uint64_t u64;
- struct cvmx_ciu2_src_iox_int_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_src_iox_int_wdog_s cn68xx;
- struct cvmx_ciu2_src_iox_int_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_iox_int_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_src_iox_int_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_src_iox_int_wrkq_s cn68xx;
- struct cvmx_ciu2_src_iox_int_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_gpio {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip2_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_io {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip2_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip2_io_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip2_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_mbox {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip2_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_mem {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip2_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_mio {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip2_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_pkt {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip2_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip2_pkt_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_rml {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip2_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip2_rml_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_wdog {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip2_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip2_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip2_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_gpio {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip3_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_io {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip3_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip3_io_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip3_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_mbox {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip3_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_mem {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip3_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_mio {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip3_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_pkt {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip3_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip3_pkt_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_rml {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip3_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip3_rml_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_wdog {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip3_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip3_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip3_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_gpio {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip4_gpio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t gpio:16;
-#else
- uint64_t gpio:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_io {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip4_io_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_34_63:30;
- uint64_t pem:2;
- uint64_t reserved_18_31:14;
- uint64_t pci_inta:2;
- uint64_t reserved_13_15:3;
- uint64_t msired:1;
- uint64_t pci_msi:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_intr:4;
-#else
- uint64_t pci_intr:4;
- uint64_t reserved_4_7:4;
- uint64_t pci_msi:4;
- uint64_t msired:1;
- uint64_t reserved_13_15:3;
- uint64_t pci_inta:2;
- uint64_t reserved_18_31:14;
- uint64_t pem:2;
- uint64_t reserved_34_63:30;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip4_io_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip4_io_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_mbox {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip4_mbox_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t mbox:4;
-#else
- uint64_t mbox:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_mem {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip4_mem_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t lmc:4;
-#else
- uint64_t lmc:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_mio {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip4_mio_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t rst:1;
- uint64_t reserved_49_62:14;
- uint64_t ptp:1;
- uint64_t reserved_45_47:3;
- uint64_t usb_hci:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_uctl:1;
- uint64_t reserved_38_39:2;
- uint64_t uart:2;
- uint64_t reserved_34_35:2;
- uint64_t twsi:2;
- uint64_t reserved_19_31:13;
- uint64_t bootdma:1;
- uint64_t mio:1;
- uint64_t nand:1;
- uint64_t reserved_12_15:4;
- uint64_t timer:4;
- uint64_t reserved_3_7:5;
- uint64_t ipd_drp:1;
- uint64_t ssoiq:1;
- uint64_t ipdppthr:1;
-#else
- uint64_t ipdppthr:1;
- uint64_t ssoiq:1;
- uint64_t ipd_drp:1;
- uint64_t reserved_3_7:5;
- uint64_t timer:4;
- uint64_t reserved_12_15:4;
- uint64_t nand:1;
- uint64_t mio:1;
- uint64_t bootdma:1;
- uint64_t reserved_19_31:13;
- uint64_t twsi:2;
- uint64_t reserved_34_35:2;
- uint64_t uart:2;
- uint64_t reserved_38_39:2;
- uint64_t usb_uctl:1;
- uint64_t reserved_41_43:3;
- uint64_t usb_hci:1;
- uint64_t reserved_45_47:3;
- uint64_t ptp:1;
- uint64_t reserved_49_62:14;
- uint64_t rst:1;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_pkt {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip4_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_54_63:10;
- uint64_t ilk_drp:2;
- uint64_t reserved_49_51:3;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_51:3;
- uint64_t ilk_drp:2;
- uint64_t reserved_54_63:10;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip4_pkt_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_49_63:15;
- uint64_t ilk:1;
- uint64_t reserved_41_47:7;
- uint64_t mii:1;
- uint64_t reserved_33_39:7;
- uint64_t agl:1;
- uint64_t reserved_13_31:19;
- uint64_t gmx_drp:5;
- uint64_t reserved_5_7:3;
- uint64_t agx:5;
-#else
- uint64_t agx:5;
- uint64_t reserved_5_7:3;
- uint64_t gmx_drp:5;
- uint64_t reserved_13_31:19;
- uint64_t agl:1;
- uint64_t reserved_33_39:7;
- uint64_t mii:1;
- uint64_t reserved_41_47:7;
- uint64_t ilk:1;
- uint64_t reserved_49_63:15;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_rml {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip4_rml_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_37_39:3;
- uint64_t dpi_dma:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_35:2;
- uint64_t dpi_dma:1;
- uint64_t reserved_37_39:3;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip4_rml_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1 {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_56_63:8;
- uint64_t trace:4;
- uint64_t reserved_49_51:3;
- uint64_t l2c:1;
- uint64_t reserved_41_47:7;
- uint64_t dfa:1;
- uint64_t reserved_34_39:6;
- uint64_t dpi:1;
- uint64_t sli:1;
- uint64_t reserved_31_31:1;
- uint64_t key:1;
- uint64_t rad:1;
- uint64_t tim:1;
- uint64_t reserved_25_27:3;
- uint64_t zip:1;
- uint64_t reserved_17_23:7;
- uint64_t sso:1;
- uint64_t reserved_8_15:8;
- uint64_t pko:1;
- uint64_t pip:1;
- uint64_t ipd:1;
- uint64_t fpa:1;
- uint64_t reserved_1_3:3;
- uint64_t iob:1;
-#else
- uint64_t iob:1;
- uint64_t reserved_1_3:3;
- uint64_t fpa:1;
- uint64_t ipd:1;
- uint64_t pip:1;
- uint64_t pko:1;
- uint64_t reserved_8_15:8;
- uint64_t sso:1;
- uint64_t reserved_17_23:7;
- uint64_t zip:1;
- uint64_t reserved_25_27:3;
- uint64_t tim:1;
- uint64_t rad:1;
- uint64_t key:1;
- uint64_t reserved_31_31:1;
- uint64_t sli:1;
- uint64_t dpi:1;
- uint64_t reserved_34_39:6;
- uint64_t dfa:1;
- uint64_t reserved_41_47:7;
- uint64_t l2c:1;
- uint64_t reserved_49_51:3;
- uint64_t trace:4;
- uint64_t reserved_56_63:8;
-#endif
- } cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_wdog {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip4_wdog_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t wdog:32;
-#else
- uint64_t wdog:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xxp1;
-};
-
-union cvmx_ciu2_src_ppx_ip4_wrkq {
- uint64_t u64;
- struct cvmx_ciu2_src_ppx_ip4_wrkq_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t workq:64;
-#else
- uint64_t workq:64;
-#endif
- } s;
- struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xx;
- struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xxp1;
-};
-
-union cvmx_ciu2_sum_iox_int {
- uint64_t u64;
- struct cvmx_ciu2_sum_iox_int_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t mbox:4;
- uint64_t reserved_8_59:52;
- uint64_t gpio:1;
- uint64_t pkt:1;
- uint64_t mem:1;
- uint64_t io:1;
- uint64_t mio:1;
- uint64_t rml:1;
- uint64_t wdog:1;
- uint64_t workq:1;
-#else
- uint64_t workq:1;
- uint64_t wdog:1;
- uint64_t rml:1;
- uint64_t mio:1;
- uint64_t io:1;
- uint64_t mem:1;
- uint64_t pkt:1;
- uint64_t gpio:1;
- uint64_t reserved_8_59:52;
- uint64_t mbox:4;
-#endif
- } s;
- struct cvmx_ciu2_sum_iox_int_s cn68xx;
- struct cvmx_ciu2_sum_iox_int_s cn68xxp1;
-};
-
-union cvmx_ciu2_sum_ppx_ip2 {
- uint64_t u64;
- struct cvmx_ciu2_sum_ppx_ip2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t mbox:4;
- uint64_t reserved_8_59:52;
- uint64_t gpio:1;
- uint64_t pkt:1;
- uint64_t mem:1;
- uint64_t io:1;
- uint64_t mio:1;
- uint64_t rml:1;
- uint64_t wdog:1;
- uint64_t workq:1;
-#else
- uint64_t workq:1;
- uint64_t wdog:1;
- uint64_t rml:1;
- uint64_t mio:1;
- uint64_t io:1;
- uint64_t mem:1;
- uint64_t pkt:1;
- uint64_t gpio:1;
- uint64_t reserved_8_59:52;
- uint64_t mbox:4;
-#endif
- } s;
- struct cvmx_ciu2_sum_ppx_ip2_s cn68xx;
- struct cvmx_ciu2_sum_ppx_ip2_s cn68xxp1;
-};
-
-union cvmx_ciu2_sum_ppx_ip3 {
- uint64_t u64;
- struct cvmx_ciu2_sum_ppx_ip3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t mbox:4;
- uint64_t reserved_8_59:52;
- uint64_t gpio:1;
- uint64_t pkt:1;
- uint64_t mem:1;
- uint64_t io:1;
- uint64_t mio:1;
- uint64_t rml:1;
- uint64_t wdog:1;
- uint64_t workq:1;
-#else
- uint64_t workq:1;
- uint64_t wdog:1;
- uint64_t rml:1;
- uint64_t mio:1;
- uint64_t io:1;
- uint64_t mem:1;
- uint64_t pkt:1;
- uint64_t gpio:1;
- uint64_t reserved_8_59:52;
- uint64_t mbox:4;
-#endif
- } s;
- struct cvmx_ciu2_sum_ppx_ip3_s cn68xx;
- struct cvmx_ciu2_sum_ppx_ip3_s cn68xxp1;
-};
-
-union cvmx_ciu2_sum_ppx_ip4 {
- uint64_t u64;
- struct cvmx_ciu2_sum_ppx_ip4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t mbox:4;
- uint64_t reserved_8_59:52;
- uint64_t gpio:1;
- uint64_t pkt:1;
- uint64_t mem:1;
- uint64_t io:1;
- uint64_t mio:1;
- uint64_t rml:1;
- uint64_t wdog:1;
- uint64_t workq:1;
-#else
- uint64_t workq:1;
- uint64_t wdog:1;
- uint64_t rml:1;
- uint64_t mio:1;
- uint64_t io:1;
- uint64_t mem:1;
- uint64_t pkt:1;
- uint64_t gpio:1;
- uint64_t reserved_8_59:52;
- uint64_t mbox:4;
-#endif
- } s;
- struct cvmx_ciu2_sum_ppx_ip4_s cn68xx;
- struct cvmx_ciu2_sum_ppx_ip4_s cn68xxp1;
-};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
index 40799cd..828d07d 100644
--- a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
@@ -62,7 +62,6 @@
uint64_t reserved_31_63:33;
#endif
} cn30xx;
- struct cvmx_dbg_data_cn30xx cn31xx;
struct cvmx_dbg_data_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
@@ -82,8 +81,6 @@
uint64_t reserved_29_63:35;
#endif
} cn38xx;
- struct cvmx_dbg_data_cn38xx cn38xxp2;
- struct cvmx_dbg_data_cn30xx cn50xx;
struct cvmx_dbg_data_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
@@ -99,7 +96,6 @@
uint64_t reserved_29_63:35;
#endif
} cn58xx;
- struct cvmx_dbg_data_cn58xx cn58xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
index dd5b042..e8613e1 100644
--- a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
@@ -89,7 +89,6 @@
uint64_t reserved_47_63:17;
#endif
} s;
- struct cvmx_dpi_bist_status_s cn61xx;
struct cvmx_dpi_bist_status_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_45_63:19;
@@ -108,10 +107,6 @@
uint64_t reserved_37_63:27;
#endif
} cn63xxp1;
- struct cvmx_dpi_bist_status_s cn66xx;
- struct cvmx_dpi_bist_status_cn63xx cn68xx;
- struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
- struct cvmx_dpi_bist_status_s cnf71xx;
};
union cvmx_dpi_ctl {
@@ -136,12 +131,6 @@
uint64_t reserved_1_63:63;
#endif
} cn61xx;
- struct cvmx_dpi_ctl_s cn63xx;
- struct cvmx_dpi_ctl_s cn63xxp1;
- struct cvmx_dpi_ctl_s cn66xx;
- struct cvmx_dpi_ctl_s cn68xx;
- struct cvmx_dpi_ctl_s cn68xxp1;
- struct cvmx_dpi_ctl_cn61xx cnf71xx;
};
union cvmx_dpi_dmax_counts {
@@ -157,13 +146,6 @@
uint64_t reserved_39_63:25;
#endif
} s;
- struct cvmx_dpi_dmax_counts_s cn61xx;
- struct cvmx_dpi_dmax_counts_s cn63xx;
- struct cvmx_dpi_dmax_counts_s cn63xxp1;
- struct cvmx_dpi_dmax_counts_s cn66xx;
- struct cvmx_dpi_dmax_counts_s cn68xx;
- struct cvmx_dpi_dmax_counts_s cn68xxp1;
- struct cvmx_dpi_dmax_counts_s cnf71xx;
};
union cvmx_dpi_dmax_dbell {
@@ -177,13 +159,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_dpi_dmax_dbell_s cn61xx;
- struct cvmx_dpi_dmax_dbell_s cn63xx;
- struct cvmx_dpi_dmax_dbell_s cn63xxp1;
- struct cvmx_dpi_dmax_dbell_s cn66xx;
- struct cvmx_dpi_dmax_dbell_s cn68xx;
- struct cvmx_dpi_dmax_dbell_s cn68xxp1;
- struct cvmx_dpi_dmax_dbell_s cnf71xx;
};
union cvmx_dpi_dmax_err_rsp_status {
@@ -197,11 +172,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
- struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
- struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
- struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
- struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;
};
union cvmx_dpi_dmax_ibuff_saddr {
@@ -242,12 +212,6 @@
uint64_t reserved_62_63:2;
#endif
} cn61xx;
- struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
- struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
- struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
- struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
- struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
- struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;
};
union cvmx_dpi_dmax_iflight {
@@ -261,11 +225,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_dpi_dmax_iflight_s cn61xx;
- struct cvmx_dpi_dmax_iflight_s cn66xx;
- struct cvmx_dpi_dmax_iflight_s cn68xx;
- struct cvmx_dpi_dmax_iflight_s cn68xxp1;
- struct cvmx_dpi_dmax_iflight_s cnf71xx;
};
union cvmx_dpi_dmax_naddr {
@@ -288,12 +247,6 @@
uint64_t reserved_36_63:28;
#endif
} cn61xx;
- struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
- struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
- struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
- struct cvmx_dpi_dmax_naddr_s cn68xx;
- struct cvmx_dpi_dmax_naddr_s cn68xxp1;
- struct cvmx_dpi_dmax_naddr_cn61xx cnf71xx;
};
union cvmx_dpi_dmax_reqbnk0 {
@@ -305,13 +258,6 @@
uint64_t state:64;
#endif
} s;
- struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
- struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
- struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
- struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
- struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
- struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
- struct cvmx_dpi_dmax_reqbnk0_s cnf71xx;
};
union cvmx_dpi_dmax_reqbnk1 {
@@ -323,13 +269,6 @@
uint64_t state:64;
#endif
} s;
- struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
- struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
- struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
- struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
- struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
- struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
- struct cvmx_dpi_dmax_reqbnk1_s cnf71xx;
};
union cvmx_dpi_dma_control {
@@ -379,7 +318,6 @@
uint64_t reserved_62_63:2;
#endif
} s;
- struct cvmx_dpi_dma_control_s cn61xx;
struct cvmx_dpi_dma_control_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_61_63:3;
@@ -462,10 +400,6 @@
uint64_t reserved_59_63:5;
#endif
} cn63xxp1;
- struct cvmx_dpi_dma_control_cn63xx cn66xx;
- struct cvmx_dpi_dma_control_s cn68xx;
- struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
- struct cvmx_dpi_dma_control_s cnf71xx;
};
union cvmx_dpi_dma_engx_en {
@@ -479,13 +413,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_dpi_dma_engx_en_s cn61xx;
- struct cvmx_dpi_dma_engx_en_s cn63xx;
- struct cvmx_dpi_dma_engx_en_s cn63xxp1;
- struct cvmx_dpi_dma_engx_en_s cn66xx;
- struct cvmx_dpi_dma_engx_en_s cn68xx;
- struct cvmx_dpi_dma_engx_en_s cn68xxp1;
- struct cvmx_dpi_dma_engx_en_s cnf71xx;
};
union cvmx_dpi_dma_ppx_cnt {
@@ -499,9 +426,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
- struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
- struct cvmx_dpi_dma_ppx_cnt_s cnf71xx;
};
union cvmx_dpi_engx_buf {
@@ -521,7 +445,6 @@
uint64_t reserved_37_63:27;
#endif
} s;
- struct cvmx_dpi_engx_buf_s cn61xx;
struct cvmx_dpi_engx_buf_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
@@ -533,11 +456,6 @@
uint64_t reserved_8_63:56;
#endif
} cn63xx;
- struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
- struct cvmx_dpi_engx_buf_s cn66xx;
- struct cvmx_dpi_engx_buf_s cn68xx;
- struct cvmx_dpi_engx_buf_s cn68xxp1;
- struct cvmx_dpi_engx_buf_s cnf71xx;
};
union cvmx_dpi_info_reg {
@@ -557,8 +475,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_dpi_info_reg_s cn61xx;
- struct cvmx_dpi_info_reg_s cn63xx;
struct cvmx_dpi_info_reg_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
@@ -570,10 +486,6 @@
uint64_t reserved_2_63:62;
#endif
} cn63xxp1;
- struct cvmx_dpi_info_reg_s cn66xx;
- struct cvmx_dpi_info_reg_s cn68xx;
- struct cvmx_dpi_info_reg_s cn68xxp1;
- struct cvmx_dpi_info_reg_s cnf71xx;
};
union cvmx_dpi_int_en {
@@ -617,7 +529,6 @@
uint64_t reserved_28_63:36;
#endif
} s;
- struct cvmx_dpi_int_en_s cn61xx;
struct cvmx_dpi_int_en_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_26_63:38;
@@ -653,11 +564,6 @@
uint64_t reserved_26_63:38;
#endif
} cn63xx;
- struct cvmx_dpi_int_en_cn63xx cn63xxp1;
- struct cvmx_dpi_int_en_s cn66xx;
- struct cvmx_dpi_int_en_cn63xx cn68xx;
- struct cvmx_dpi_int_en_cn63xx cn68xxp1;
- struct cvmx_dpi_int_en_s cnf71xx;
};
union cvmx_dpi_int_reg {
@@ -701,7 +607,6 @@
uint64_t reserved_28_63:36;
#endif
} s;
- struct cvmx_dpi_int_reg_s cn61xx;
struct cvmx_dpi_int_reg_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_26_63:38;
@@ -737,11 +642,6 @@
uint64_t reserved_26_63:38;
#endif
} cn63xx;
- struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
- struct cvmx_dpi_int_reg_s cn66xx;
- struct cvmx_dpi_int_reg_cn63xx cn68xx;
- struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
- struct cvmx_dpi_int_reg_s cnf71xx;
};
union cvmx_dpi_ncbx_cfg {
@@ -755,10 +655,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_dpi_ncbx_cfg_s cn61xx;
- struct cvmx_dpi_ncbx_cfg_s cn66xx;
- struct cvmx_dpi_ncbx_cfg_s cn68xx;
- struct cvmx_dpi_ncbx_cfg_s cnf71xx;
};
union cvmx_dpi_pint_info {
@@ -776,13 +672,6 @@
uint64_t reserved_14_63:50;
#endif
} s;
- struct cvmx_dpi_pint_info_s cn61xx;
- struct cvmx_dpi_pint_info_s cn63xx;
- struct cvmx_dpi_pint_info_s cn63xxp1;
- struct cvmx_dpi_pint_info_s cn66xx;
- struct cvmx_dpi_pint_info_s cn68xx;
- struct cvmx_dpi_pint_info_s cn68xxp1;
- struct cvmx_dpi_pint_info_s cnf71xx;
};
union cvmx_dpi_pkt_err_rsp {
@@ -796,13 +685,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_dpi_pkt_err_rsp_s cn61xx;
- struct cvmx_dpi_pkt_err_rsp_s cn63xx;
- struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
- struct cvmx_dpi_pkt_err_rsp_s cn66xx;
- struct cvmx_dpi_pkt_err_rsp_s cn68xx;
- struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
- struct cvmx_dpi_pkt_err_rsp_s cnf71xx;
};
union cvmx_dpi_req_err_rsp {
@@ -816,13 +698,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_dpi_req_err_rsp_s cn61xx;
- struct cvmx_dpi_req_err_rsp_s cn63xx;
- struct cvmx_dpi_req_err_rsp_s cn63xxp1;
- struct cvmx_dpi_req_err_rsp_s cn66xx;
- struct cvmx_dpi_req_err_rsp_s cn68xx;
- struct cvmx_dpi_req_err_rsp_s cn68xxp1;
- struct cvmx_dpi_req_err_rsp_s cnf71xx;
};
union cvmx_dpi_req_err_rsp_en {
@@ -836,13 +711,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_dpi_req_err_rsp_en_s cn61xx;
- struct cvmx_dpi_req_err_rsp_en_s cn63xx;
- struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
- struct cvmx_dpi_req_err_rsp_en_s cn66xx;
- struct cvmx_dpi_req_err_rsp_en_s cn68xx;
- struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
- struct cvmx_dpi_req_err_rsp_en_s cnf71xx;
};
union cvmx_dpi_req_err_rst {
@@ -856,13 +724,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_dpi_req_err_rst_s cn61xx;
- struct cvmx_dpi_req_err_rst_s cn63xx;
- struct cvmx_dpi_req_err_rst_s cn63xxp1;
- struct cvmx_dpi_req_err_rst_s cn66xx;
- struct cvmx_dpi_req_err_rst_s cn68xx;
- struct cvmx_dpi_req_err_rst_s cn68xxp1;
- struct cvmx_dpi_req_err_rst_s cnf71xx;
};
union cvmx_dpi_req_err_rst_en {
@@ -876,13 +737,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_dpi_req_err_rst_en_s cn61xx;
- struct cvmx_dpi_req_err_rst_en_s cn63xx;
- struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
- struct cvmx_dpi_req_err_rst_en_s cn66xx;
- struct cvmx_dpi_req_err_rst_en_s cn68xx;
- struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
- struct cvmx_dpi_req_err_rst_en_s cnf71xx;
};
union cvmx_dpi_req_err_skip_comp {
@@ -900,11 +754,6 @@
uint64_t reserved_24_63:40;
#endif
} s;
- struct cvmx_dpi_req_err_skip_comp_s cn61xx;
- struct cvmx_dpi_req_err_skip_comp_s cn66xx;
- struct cvmx_dpi_req_err_skip_comp_s cn68xx;
- struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
- struct cvmx_dpi_req_err_skip_comp_s cnf71xx;
};
union cvmx_dpi_req_gbl_en {
@@ -918,13 +767,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_dpi_req_gbl_en_s cn61xx;
- struct cvmx_dpi_req_gbl_en_s cn63xx;
- struct cvmx_dpi_req_gbl_en_s cn63xxp1;
- struct cvmx_dpi_req_gbl_en_s cn66xx;
- struct cvmx_dpi_req_gbl_en_s cn68xx;
- struct cvmx_dpi_req_gbl_en_s cn68xxp1;
- struct cvmx_dpi_req_gbl_en_s cnf71xx;
};
union cvmx_dpi_sli_prtx_cfg {
@@ -960,7 +802,6 @@
uint64_t reserved_25_63:39;
#endif
} s;
- struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
struct cvmx_dpi_sli_prtx_cfg_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63:39;
@@ -994,11 +835,6 @@
uint64_t reserved_25_63:39;
#endif
} cn63xx;
- struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
- struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
- struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
- struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
- struct cvmx_dpi_sli_prtx_cfg_s cnf71xx;
};
union cvmx_dpi_sli_prtx_err {
@@ -1012,13 +848,6 @@
uint64_t addr:61;
#endif
} s;
- struct cvmx_dpi_sli_prtx_err_s cn61xx;
- struct cvmx_dpi_sli_prtx_err_s cn63xx;
- struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
- struct cvmx_dpi_sli_prtx_err_s cn66xx;
- struct cvmx_dpi_sli_prtx_err_s cn68xx;
- struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
- struct cvmx_dpi_sli_prtx_err_s cnf71xx;
};
union cvmx_dpi_sli_prtx_err_info {
@@ -1040,13 +869,6 @@
uint64_t reserved_9_63:55;
#endif
} s;
- struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
- struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
- struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
- struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
- struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
- struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
- struct cvmx_dpi_sli_prtx_err_info_s cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
index 887ff8e..322943f 100644
--- a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
@@ -81,11 +81,6 @@
uint64_t reserved_38_63:26;
#endif
} s;
- struct cvmx_fpa_addr_range_error_s cn61xx;
- struct cvmx_fpa_addr_range_error_s cn66xx;
- struct cvmx_fpa_addr_range_error_s cn68xx;
- struct cvmx_fpa_addr_range_error_s cn68xxp1;
- struct cvmx_fpa_addr_range_error_s cnf71xx;
};
union cvmx_fpa_bist_status {
@@ -107,24 +102,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_fpa_bist_status_s cn30xx;
- struct cvmx_fpa_bist_status_s cn31xx;
- struct cvmx_fpa_bist_status_s cn38xx;
- struct cvmx_fpa_bist_status_s cn38xxp2;
- struct cvmx_fpa_bist_status_s cn50xx;
- struct cvmx_fpa_bist_status_s cn52xx;
- struct cvmx_fpa_bist_status_s cn52xxp1;
- struct cvmx_fpa_bist_status_s cn56xx;
- struct cvmx_fpa_bist_status_s cn56xxp1;
- struct cvmx_fpa_bist_status_s cn58xx;
- struct cvmx_fpa_bist_status_s cn58xxp1;
- struct cvmx_fpa_bist_status_s cn61xx;
- struct cvmx_fpa_bist_status_s cn63xx;
- struct cvmx_fpa_bist_status_s cn63xxp1;
- struct cvmx_fpa_bist_status_s cn66xx;
- struct cvmx_fpa_bist_status_s cn68xx;
- struct cvmx_fpa_bist_status_s cn68xxp1;
- struct cvmx_fpa_bist_status_s cnf71xx;
};
union cvmx_fpa_ctl_status {
@@ -173,23 +150,6 @@
uint64_t reserved_18_63:46;
#endif
} cn30xx;
- struct cvmx_fpa_ctl_status_cn30xx cn31xx;
- struct cvmx_fpa_ctl_status_cn30xx cn38xx;
- struct cvmx_fpa_ctl_status_cn30xx cn38xxp2;
- struct cvmx_fpa_ctl_status_cn30xx cn50xx;
- struct cvmx_fpa_ctl_status_cn30xx cn52xx;
- struct cvmx_fpa_ctl_status_cn30xx cn52xxp1;
- struct cvmx_fpa_ctl_status_cn30xx cn56xx;
- struct cvmx_fpa_ctl_status_cn30xx cn56xxp1;
- struct cvmx_fpa_ctl_status_cn30xx cn58xx;
- struct cvmx_fpa_ctl_status_cn30xx cn58xxp1;
- struct cvmx_fpa_ctl_status_s cn61xx;
- struct cvmx_fpa_ctl_status_s cn63xx;
- struct cvmx_fpa_ctl_status_cn30xx cn63xxp1;
- struct cvmx_fpa_ctl_status_s cn66xx;
- struct cvmx_fpa_ctl_status_s cn68xx;
- struct cvmx_fpa_ctl_status_s cn68xxp1;
- struct cvmx_fpa_ctl_status_s cnf71xx;
};
union cvmx_fpa_fpfx_marks {
@@ -205,19 +165,6 @@
uint64_t reserved_22_63:42;
#endif
} s;
- struct cvmx_fpa_fpfx_marks_s cn38xx;
- struct cvmx_fpa_fpfx_marks_s cn38xxp2;
- struct cvmx_fpa_fpfx_marks_s cn56xx;
- struct cvmx_fpa_fpfx_marks_s cn56xxp1;
- struct cvmx_fpa_fpfx_marks_s cn58xx;
- struct cvmx_fpa_fpfx_marks_s cn58xxp1;
- struct cvmx_fpa_fpfx_marks_s cn61xx;
- struct cvmx_fpa_fpfx_marks_s cn63xx;
- struct cvmx_fpa_fpfx_marks_s cn63xxp1;
- struct cvmx_fpa_fpfx_marks_s cn66xx;
- struct cvmx_fpa_fpfx_marks_s cn68xx;
- struct cvmx_fpa_fpfx_marks_s cn68xxp1;
- struct cvmx_fpa_fpfx_marks_s cnf71xx;
};
union cvmx_fpa_fpfx_size {
@@ -231,19 +178,6 @@
uint64_t reserved_11_63:53;
#endif
} s;
- struct cvmx_fpa_fpfx_size_s cn38xx;
- struct cvmx_fpa_fpfx_size_s cn38xxp2;
- struct cvmx_fpa_fpfx_size_s cn56xx;
- struct cvmx_fpa_fpfx_size_s cn56xxp1;
- struct cvmx_fpa_fpfx_size_s cn58xx;
- struct cvmx_fpa_fpfx_size_s cn58xxp1;
- struct cvmx_fpa_fpfx_size_s cn61xx;
- struct cvmx_fpa_fpfx_size_s cn63xx;
- struct cvmx_fpa_fpfx_size_s cn63xxp1;
- struct cvmx_fpa_fpfx_size_s cn66xx;
- struct cvmx_fpa_fpfx_size_s cn68xx;
- struct cvmx_fpa_fpfx_size_s cn68xxp1;
- struct cvmx_fpa_fpfx_size_s cnf71xx;
};
union cvmx_fpa_fpf0_marks {
@@ -259,19 +193,6 @@
uint64_t reserved_24_63:40;
#endif
} s;
- struct cvmx_fpa_fpf0_marks_s cn38xx;
- struct cvmx_fpa_fpf0_marks_s cn38xxp2;
- struct cvmx_fpa_fpf0_marks_s cn56xx;
- struct cvmx_fpa_fpf0_marks_s cn56xxp1;
- struct cvmx_fpa_fpf0_marks_s cn58xx;
- struct cvmx_fpa_fpf0_marks_s cn58xxp1;
- struct cvmx_fpa_fpf0_marks_s cn61xx;
- struct cvmx_fpa_fpf0_marks_s cn63xx;
- struct cvmx_fpa_fpf0_marks_s cn63xxp1;
- struct cvmx_fpa_fpf0_marks_s cn66xx;
- struct cvmx_fpa_fpf0_marks_s cn68xx;
- struct cvmx_fpa_fpf0_marks_s cn68xxp1;
- struct cvmx_fpa_fpf0_marks_s cnf71xx;
};
union cvmx_fpa_fpf0_size {
@@ -285,19 +206,6 @@
uint64_t reserved_12_63:52;
#endif
} s;
- struct cvmx_fpa_fpf0_size_s cn38xx;
- struct cvmx_fpa_fpf0_size_s cn38xxp2;
- struct cvmx_fpa_fpf0_size_s cn56xx;
- struct cvmx_fpa_fpf0_size_s cn56xxp1;
- struct cvmx_fpa_fpf0_size_s cn58xx;
- struct cvmx_fpa_fpf0_size_s cn58xxp1;
- struct cvmx_fpa_fpf0_size_s cn61xx;
- struct cvmx_fpa_fpf0_size_s cn63xx;
- struct cvmx_fpa_fpf0_size_s cn63xxp1;
- struct cvmx_fpa_fpf0_size_s cn66xx;
- struct cvmx_fpa_fpf0_size_s cn68xx;
- struct cvmx_fpa_fpf0_size_s cn68xxp1;
- struct cvmx_fpa_fpf0_size_s cnf71xx;
};
union cvmx_fpa_fpf8_marks {
@@ -313,8 +221,6 @@
uint64_t reserved_22_63:42;
#endif
} s;
- struct cvmx_fpa_fpf8_marks_s cn68xx;
- struct cvmx_fpa_fpf8_marks_s cn68xxp1;
};
union cvmx_fpa_fpf8_size {
@@ -328,8 +234,6 @@
uint64_t reserved_12_63:52;
#endif
} s;
- struct cvmx_fpa_fpf8_size_s cn68xx;
- struct cvmx_fpa_fpf8_size_s cn68xxp1;
};
union cvmx_fpa_int_enb {
@@ -496,16 +400,6 @@
uint64_t reserved_28_63:36;
#endif
} cn30xx;
- struct cvmx_fpa_int_enb_cn30xx cn31xx;
- struct cvmx_fpa_int_enb_cn30xx cn38xx;
- struct cvmx_fpa_int_enb_cn30xx cn38xxp2;
- struct cvmx_fpa_int_enb_cn30xx cn50xx;
- struct cvmx_fpa_int_enb_cn30xx cn52xx;
- struct cvmx_fpa_int_enb_cn30xx cn52xxp1;
- struct cvmx_fpa_int_enb_cn30xx cn56xx;
- struct cvmx_fpa_int_enb_cn30xx cn56xxp1;
- struct cvmx_fpa_int_enb_cn30xx cn58xx;
- struct cvmx_fpa_int_enb_cn30xx cn58xxp1;
struct cvmx_fpa_int_enb_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_50_63:14;
@@ -700,8 +594,6 @@
uint64_t reserved_44_63:20;
#endif
} cn63xx;
- struct cvmx_fpa_int_enb_cn30xx cn63xxp1;
- struct cvmx_fpa_int_enb_cn61xx cn66xx;
struct cvmx_fpa_int_enb_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_50_63:14;
@@ -809,8 +701,6 @@
uint64_t reserved_50_63:14;
#endif
} cn68xx;
- struct cvmx_fpa_int_enb_cn68xx cn68xxp1;
- struct cvmx_fpa_int_enb_cn61xx cnf71xx;
};
union cvmx_fpa_int_sum {
@@ -985,16 +875,6 @@
uint64_t reserved_28_63:36;
#endif
} cn30xx;
- struct cvmx_fpa_int_sum_cn30xx cn31xx;
- struct cvmx_fpa_int_sum_cn30xx cn38xx;
- struct cvmx_fpa_int_sum_cn30xx cn38xxp2;
- struct cvmx_fpa_int_sum_cn30xx cn50xx;
- struct cvmx_fpa_int_sum_cn30xx cn52xx;
- struct cvmx_fpa_int_sum_cn30xx cn52xxp1;
- struct cvmx_fpa_int_sum_cn30xx cn56xx;
- struct cvmx_fpa_int_sum_cn30xx cn56xxp1;
- struct cvmx_fpa_int_sum_cn30xx cn58xx;
- struct cvmx_fpa_int_sum_cn30xx cn58xxp1;
struct cvmx_fpa_int_sum_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_50_63:14;
@@ -1189,11 +1069,6 @@
uint64_t reserved_44_63:20;
#endif
} cn63xx;
- struct cvmx_fpa_int_sum_cn30xx cn63xxp1;
- struct cvmx_fpa_int_sum_cn61xx cn66xx;
- struct cvmx_fpa_int_sum_s cn68xx;
- struct cvmx_fpa_int_sum_s cn68xxp1;
- struct cvmx_fpa_int_sum_cn61xx cnf71xx;
};
union cvmx_fpa_packet_threshold {
@@ -1207,12 +1082,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_fpa_packet_threshold_s cn61xx;
- struct cvmx_fpa_packet_threshold_s cn63xx;
- struct cvmx_fpa_packet_threshold_s cn66xx;
- struct cvmx_fpa_packet_threshold_s cn68xx;
- struct cvmx_fpa_packet_threshold_s cn68xxp1;
- struct cvmx_fpa_packet_threshold_s cnf71xx;
};
union cvmx_fpa_poolx_end_addr {
@@ -1226,11 +1095,6 @@
uint64_t reserved_33_63:31;
#endif
} s;
- struct cvmx_fpa_poolx_end_addr_s cn61xx;
- struct cvmx_fpa_poolx_end_addr_s cn66xx;
- struct cvmx_fpa_poolx_end_addr_s cn68xx;
- struct cvmx_fpa_poolx_end_addr_s cn68xxp1;
- struct cvmx_fpa_poolx_end_addr_s cnf71xx;
};
union cvmx_fpa_poolx_start_addr {
@@ -1244,11 +1108,6 @@
uint64_t reserved_33_63:31;
#endif
} s;
- struct cvmx_fpa_poolx_start_addr_s cn61xx;
- struct cvmx_fpa_poolx_start_addr_s cn66xx;
- struct cvmx_fpa_poolx_start_addr_s cn68xx;
- struct cvmx_fpa_poolx_start_addr_s cn68xxp1;
- struct cvmx_fpa_poolx_start_addr_s cnf71xx;
};
union cvmx_fpa_poolx_threshold {
@@ -1271,11 +1130,6 @@
uint64_t reserved_29_63:35;
#endif
} cn61xx;
- struct cvmx_fpa_poolx_threshold_cn61xx cn63xx;
- struct cvmx_fpa_poolx_threshold_cn61xx cn66xx;
- struct cvmx_fpa_poolx_threshold_s cn68xx;
- struct cvmx_fpa_poolx_threshold_s cn68xxp1;
- struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx;
};
union cvmx_fpa_quex_available {
@@ -1298,23 +1152,6 @@
uint64_t reserved_29_63:35;
#endif
} cn30xx;
- struct cvmx_fpa_quex_available_cn30xx cn31xx;
- struct cvmx_fpa_quex_available_cn30xx cn38xx;
- struct cvmx_fpa_quex_available_cn30xx cn38xxp2;
- struct cvmx_fpa_quex_available_cn30xx cn50xx;
- struct cvmx_fpa_quex_available_cn30xx cn52xx;
- struct cvmx_fpa_quex_available_cn30xx cn52xxp1;
- struct cvmx_fpa_quex_available_cn30xx cn56xx;
- struct cvmx_fpa_quex_available_cn30xx cn56xxp1;
- struct cvmx_fpa_quex_available_cn30xx cn58xx;
- struct cvmx_fpa_quex_available_cn30xx cn58xxp1;
- struct cvmx_fpa_quex_available_cn30xx cn61xx;
- struct cvmx_fpa_quex_available_cn30xx cn63xx;
- struct cvmx_fpa_quex_available_cn30xx cn63xxp1;
- struct cvmx_fpa_quex_available_cn30xx cn66xx;
- struct cvmx_fpa_quex_available_s cn68xx;
- struct cvmx_fpa_quex_available_s cn68xxp1;
- struct cvmx_fpa_quex_available_cn30xx cnf71xx;
};
union cvmx_fpa_quex_page_index {
@@ -1328,24 +1165,6 @@
uint64_t reserved_25_63:39;
#endif
} s;
- struct cvmx_fpa_quex_page_index_s cn30xx;
- struct cvmx_fpa_quex_page_index_s cn31xx;
- struct cvmx_fpa_quex_page_index_s cn38xx;
- struct cvmx_fpa_quex_page_index_s cn38xxp2;
- struct cvmx_fpa_quex_page_index_s cn50xx;
- struct cvmx_fpa_quex_page_index_s cn52xx;
- struct cvmx_fpa_quex_page_index_s cn52xxp1;
- struct cvmx_fpa_quex_page_index_s cn56xx;
- struct cvmx_fpa_quex_page_index_s cn56xxp1;
- struct cvmx_fpa_quex_page_index_s cn58xx;
- struct cvmx_fpa_quex_page_index_s cn58xxp1;
- struct cvmx_fpa_quex_page_index_s cn61xx;
- struct cvmx_fpa_quex_page_index_s cn63xx;
- struct cvmx_fpa_quex_page_index_s cn63xxp1;
- struct cvmx_fpa_quex_page_index_s cn66xx;
- struct cvmx_fpa_quex_page_index_s cn68xx;
- struct cvmx_fpa_quex_page_index_s cn68xxp1;
- struct cvmx_fpa_quex_page_index_s cnf71xx;
};
union cvmx_fpa_que8_page_index {
@@ -1359,8 +1178,6 @@
uint64_t reserved_25_63:39;
#endif
} s;
- struct cvmx_fpa_que8_page_index_s cn68xx;
- struct cvmx_fpa_que8_page_index_s cn68xxp1;
};
union cvmx_fpa_que_act {
@@ -1376,24 +1193,6 @@
uint64_t reserved_29_63:35;
#endif
} s;
- struct cvmx_fpa_que_act_s cn30xx;
- struct cvmx_fpa_que_act_s cn31xx;
- struct cvmx_fpa_que_act_s cn38xx;
- struct cvmx_fpa_que_act_s cn38xxp2;
- struct cvmx_fpa_que_act_s cn50xx;
- struct cvmx_fpa_que_act_s cn52xx;
- struct cvmx_fpa_que_act_s cn52xxp1;
- struct cvmx_fpa_que_act_s cn56xx;
- struct cvmx_fpa_que_act_s cn56xxp1;
- struct cvmx_fpa_que_act_s cn58xx;
- struct cvmx_fpa_que_act_s cn58xxp1;
- struct cvmx_fpa_que_act_s cn61xx;
- struct cvmx_fpa_que_act_s cn63xx;
- struct cvmx_fpa_que_act_s cn63xxp1;
- struct cvmx_fpa_que_act_s cn66xx;
- struct cvmx_fpa_que_act_s cn68xx;
- struct cvmx_fpa_que_act_s cn68xxp1;
- struct cvmx_fpa_que_act_s cnf71xx;
};
union cvmx_fpa_que_exp {
@@ -1409,24 +1208,6 @@
uint64_t reserved_29_63:35;
#endif
} s;
- struct cvmx_fpa_que_exp_s cn30xx;
- struct cvmx_fpa_que_exp_s cn31xx;
- struct cvmx_fpa_que_exp_s cn38xx;
- struct cvmx_fpa_que_exp_s cn38xxp2;
- struct cvmx_fpa_que_exp_s cn50xx;
- struct cvmx_fpa_que_exp_s cn52xx;
- struct cvmx_fpa_que_exp_s cn52xxp1;
- struct cvmx_fpa_que_exp_s cn56xx;
- struct cvmx_fpa_que_exp_s cn56xxp1;
- struct cvmx_fpa_que_exp_s cn58xx;
- struct cvmx_fpa_que_exp_s cn58xxp1;
- struct cvmx_fpa_que_exp_s cn61xx;
- struct cvmx_fpa_que_exp_s cn63xx;
- struct cvmx_fpa_que_exp_s cn63xxp1;
- struct cvmx_fpa_que_exp_s cn66xx;
- struct cvmx_fpa_que_exp_s cn68xx;
- struct cvmx_fpa_que_exp_s cn68xxp1;
- struct cvmx_fpa_que_exp_s cnf71xx;
};
union cvmx_fpa_wart_ctl {
@@ -1440,17 +1221,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_fpa_wart_ctl_s cn30xx;
- struct cvmx_fpa_wart_ctl_s cn31xx;
- struct cvmx_fpa_wart_ctl_s cn38xx;
- struct cvmx_fpa_wart_ctl_s cn38xxp2;
- struct cvmx_fpa_wart_ctl_s cn50xx;
- struct cvmx_fpa_wart_ctl_s cn52xx;
- struct cvmx_fpa_wart_ctl_s cn52xxp1;
- struct cvmx_fpa_wart_ctl_s cn56xx;
- struct cvmx_fpa_wart_ctl_s cn56xxp1;
- struct cvmx_fpa_wart_ctl_s cn58xx;
- struct cvmx_fpa_wart_ctl_s cn58xxp1;
};
union cvmx_fpa_wart_status {
@@ -1464,17 +1234,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_fpa_wart_status_s cn30xx;
- struct cvmx_fpa_wart_status_s cn31xx;
- struct cvmx_fpa_wart_status_s cn38xx;
- struct cvmx_fpa_wart_status_s cn38xxp2;
- struct cvmx_fpa_wart_status_s cn50xx;
- struct cvmx_fpa_wart_status_s cn52xx;
- struct cvmx_fpa_wart_status_s cn52xxp1;
- struct cvmx_fpa_wart_status_s cn56xx;
- struct cvmx_fpa_wart_status_s cn56xxp1;
- struct cvmx_fpa_wart_status_s cn58xx;
- struct cvmx_fpa_wart_status_s cn58xxp1;
};
union cvmx_fpa_wqe_threshold {
@@ -1488,12 +1247,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_fpa_wqe_threshold_s cn61xx;
- struct cvmx_fpa_wqe_threshold_s cn63xx;
- struct cvmx_fpa_wqe_threshold_s cn66xx;
- struct cvmx_fpa_wqe_threshold_s cn68xx;
- struct cvmx_fpa_wqe_threshold_s cn68xxp1;
- struct cvmx_fpa_wqe_threshold_s cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
index 80e4f835..bdba676 100644
--- a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
@@ -28,82 +28,9 @@
#ifndef __CVMX_GMXX_DEFS_H__
#define __CVMX_GMXX_DEFS_H__
-static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000518ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000400ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8)
-#define CVMX_GMXX_BPID_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000700ull) + ((block_id) & 7) * 0x1000000ull)
-static inline uint64_t CVMX_GMXX_CLK_EN(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080007F0ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_EBP_DIS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000608ull) + ((block_id) & 7) * 0x1000000ull)
-#define CVMX_GMXX_EBP_MSK(block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + ((block_id) & 7) * 0x1000000ull)
static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull;
}
@@ -113,82 +40,15 @@
static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
}
-static inline uint64_t CVMX_GMXX_NXA_ADR(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000510ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_PIPE_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180008000760ull) + ((block_id) & 7) * 0x1000000ull)
-static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000580ull) + (block_id) * 0x8000000ull;
-}
-
static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -197,23 +57,9 @@
return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
}
-#define CVMX_GMXX_RXAUI_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180008000740ull) + ((block_id) & 7) * 0x1000000ull)
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -225,19 +71,6 @@
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -249,19 +82,6 @@
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -273,19 +93,6 @@
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -297,19 +104,6 @@
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -321,19 +115,6 @@
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -342,37 +123,9 @@
return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
}
-static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000110ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -384,20 +137,6 @@
static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -406,73 +145,9 @@
return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
}
-static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000040ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000020ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -483,48 +158,10 @@
#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000058ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -536,20 +173,6 @@
static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -561,20 +184,6 @@
static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -583,471 +192,20 @@
return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
}
-static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000068ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
-static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000050ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000088ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000098ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000080ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000090ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000048ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x0ull) * 8;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x200000ull) * 8;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000420ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-}
-
-static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x0ull) * 8;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x200000ull) * 8;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000460ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-}
-
-static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x0ull) * 8;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x200000ull) * 8;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000440ull) + ((offset) + (block_id) * 0x1000000ull) * 8;
-}
-
-static inline uint64_t CVMX_GMXX_RX_HG2_STATUS(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000548ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_RX_PASS_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800080005F8ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8)
static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
}
-static inline uint64_t CVMX_GMXX_RX_PRT_INFO(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080004E8ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_RX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800080007E8ull))
-static inline uint64_t CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000538ull) + (block_id) * 0x8000000ull;
-}
-
static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull;
}
@@ -1057,20 +215,6 @@
static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -1079,97 +223,9 @@
return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
}
-static inline uint64_t CVMX_GMXX_SOFT_BIST(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080007E8ull) + (block_id) * 0x1000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_STAT_BP(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000520ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TB_REG(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080007E0ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000218ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -1178,58 +234,10 @@
return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
}
-static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080005A0ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080005C0ull) + (block_id) * 0x8000000ull;
-}
-
#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -1238,48 +246,9 @@
return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
}
-static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000240ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -1291,20 +260,6 @@
static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -1313,92 +268,9 @@
return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
}
-static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000258ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000260ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-#define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048)
-static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000300ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -1407,323 +279,9 @@
return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
}
-static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000250ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000280ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000288ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000290ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000298ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
-static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x0ull) * 2048;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000268ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
-}
-
static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
@@ -1732,145 +290,9 @@
return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
}
-static inline uint64_t CVMX_GMXX_TX_BP(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080004D0ull) + (block_id) * 0x8000000ull;
-}
-
-#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
-static inline uint64_t CVMX_GMXX_TX_COL_ATTEMPT(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000498ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_CORRUPT(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080004D8ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_HG2_REG1(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000558ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_HG2_REG2(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000560ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_IFG(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000488ull) + (block_id) * 0x8000000ull;
-}
-
static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull;
}
@@ -1880,151 +302,24 @@
static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
}
-static inline uint64_t CVMX_GMXX_TX_JAM(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000490ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_LFSR(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080004F8ull) + (block_id) * 0x8000000ull;
-}
-
static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
}
-static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080004A0ull) + (block_id) * 0x8000000ull;
-}
-
-static inline uint64_t CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x00011800080004A8ull) + (block_id) * 0x8000000ull;
-}
-
static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull;
}
@@ -2032,286 +327,19 @@
}
#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_GMXX_TX_SPI_DRAIN(block_id) (CVMX_ADD_IO_SEG(0x00011800080004E0ull) + ((block_id) & 1) * 0x8000000ull)
#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull)
-#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
{
switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull;
}
return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
}
-static inline uint64_t CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long block_id)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x1000000ull;
- }
- return CVMX_ADD_IO_SEG(0x0001180008000540ull) + (block_id) * 0x8000000ull;
-}
-
void __cvmx_interrupt_gmxx_enable(int interface);
-union cvmx_gmxx_bad_reg {
- uint64_t u64;
- struct cvmx_gmxx_bad_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_31_63:33;
- uint64_t inb_nxa:4;
- uint64_t statovr:1;
- uint64_t loststat:4;
- uint64_t reserved_18_21:4;
- uint64_t out_ovr:16;
- uint64_t ncb_ovr:1;
- uint64_t out_col:1;
-#else
- uint64_t out_col:1;
- uint64_t ncb_ovr:1;
- uint64_t out_ovr:16;
- uint64_t reserved_18_21:4;
- uint64_t loststat:4;
- uint64_t statovr:1;
- uint64_t inb_nxa:4;
- uint64_t reserved_31_63:33;
-#endif
- } s;
- struct cvmx_gmxx_bad_reg_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_31_63:33;
- uint64_t inb_nxa:4;
- uint64_t statovr:1;
- uint64_t reserved_25_25:1;
- uint64_t loststat:3;
- uint64_t reserved_5_21:17;
- uint64_t out_ovr:3;
- uint64_t reserved_0_1:2;
-#else
- uint64_t reserved_0_1:2;
- uint64_t out_ovr:3;
- uint64_t reserved_5_21:17;
- uint64_t loststat:3;
- uint64_t reserved_25_25:1;
- uint64_t statovr:1;
- uint64_t inb_nxa:4;
- uint64_t reserved_31_63:33;
-#endif
- } cn30xx;
- struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
- struct cvmx_gmxx_bad_reg_s cn38xx;
- struct cvmx_gmxx_bad_reg_s cn38xxp2;
- struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
- struct cvmx_gmxx_bad_reg_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_31_63:33;
- uint64_t inb_nxa:4;
- uint64_t statovr:1;
- uint64_t loststat:4;
- uint64_t reserved_6_21:16;
- uint64_t out_ovr:4;
- uint64_t reserved_0_1:2;
-#else
- uint64_t reserved_0_1:2;
- uint64_t out_ovr:4;
- uint64_t reserved_6_21:16;
- uint64_t loststat:4;
- uint64_t statovr:1;
- uint64_t inb_nxa:4;
- uint64_t reserved_31_63:33;
-#endif
- } cn52xx;
- struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
- struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
- struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
- struct cvmx_gmxx_bad_reg_s cn58xx;
- struct cvmx_gmxx_bad_reg_s cn58xxp1;
- struct cvmx_gmxx_bad_reg_cn52xx cn61xx;
- struct cvmx_gmxx_bad_reg_cn52xx cn63xx;
- struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1;
- struct cvmx_gmxx_bad_reg_cn52xx cn66xx;
- struct cvmx_gmxx_bad_reg_cn52xx cn68xx;
- struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1;
- struct cvmx_gmxx_bad_reg_cn52xx cnf71xx;
-};
-
-union cvmx_gmxx_bist {
- uint64_t u64;
- struct cvmx_gmxx_bist_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_25_63:39;
- uint64_t status:25;
-#else
- uint64_t status:25;
- uint64_t reserved_25_63:39;
-#endif
- } s;
- struct cvmx_gmxx_bist_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_10_63:54;
- uint64_t status:10;
-#else
- uint64_t status:10;
- uint64_t reserved_10_63:54;
-#endif
- } cn30xx;
- struct cvmx_gmxx_bist_cn30xx cn31xx;
- struct cvmx_gmxx_bist_cn30xx cn38xx;
- struct cvmx_gmxx_bist_cn30xx cn38xxp2;
- struct cvmx_gmxx_bist_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_12_63:52;
- uint64_t status:12;
-#else
- uint64_t status:12;
- uint64_t reserved_12_63:52;
-#endif
- } cn50xx;
- struct cvmx_gmxx_bist_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t status:16;
-#else
- uint64_t status:16;
- uint64_t reserved_16_63:48;
-#endif
- } cn52xx;
- struct cvmx_gmxx_bist_cn52xx cn52xxp1;
- struct cvmx_gmxx_bist_cn52xx cn56xx;
- struct cvmx_gmxx_bist_cn52xx cn56xxp1;
- struct cvmx_gmxx_bist_cn58xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_17_63:47;
- uint64_t status:17;
-#else
- uint64_t status:17;
- uint64_t reserved_17_63:47;
-#endif
- } cn58xx;
- struct cvmx_gmxx_bist_cn58xx cn58xxp1;
- struct cvmx_gmxx_bist_s cn61xx;
- struct cvmx_gmxx_bist_s cn63xx;
- struct cvmx_gmxx_bist_s cn63xxp1;
- struct cvmx_gmxx_bist_s cn66xx;
- struct cvmx_gmxx_bist_s cn68xx;
- struct cvmx_gmxx_bist_s cn68xxp1;
- struct cvmx_gmxx_bist_s cnf71xx;
-};
-
-union cvmx_gmxx_bpid_mapx {
- uint64_t u64;
- struct cvmx_gmxx_bpid_mapx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_17_63:47;
- uint64_t status:1;
- uint64_t reserved_9_15:7;
- uint64_t val:1;
- uint64_t reserved_6_7:2;
- uint64_t bpid:6;
-#else
- uint64_t bpid:6;
- uint64_t reserved_6_7:2;
- uint64_t val:1;
- uint64_t reserved_9_15:7;
- uint64_t status:1;
- uint64_t reserved_17_63:47;
-#endif
- } s;
- struct cvmx_gmxx_bpid_mapx_s cn68xx;
- struct cvmx_gmxx_bpid_mapx_s cn68xxp1;
-};
-
-union cvmx_gmxx_bpid_msk {
- uint64_t u64;
- struct cvmx_gmxx_bpid_msk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_48_63:16;
- uint64_t msk_or:16;
- uint64_t reserved_16_31:16;
- uint64_t msk_and:16;
-#else
- uint64_t msk_and:16;
- uint64_t reserved_16_31:16;
- uint64_t msk_or:16;
- uint64_t reserved_48_63:16;
-#endif
- } s;
- struct cvmx_gmxx_bpid_msk_s cn68xx;
- struct cvmx_gmxx_bpid_msk_s cn68xxp1;
-};
-
-union cvmx_gmxx_clk_en {
- uint64_t u64;
- struct cvmx_gmxx_clk_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t clk_en:1;
-#else
- uint64_t clk_en:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_gmxx_clk_en_s cn52xx;
- struct cvmx_gmxx_clk_en_s cn52xxp1;
- struct cvmx_gmxx_clk_en_s cn56xx;
- struct cvmx_gmxx_clk_en_s cn56xxp1;
- struct cvmx_gmxx_clk_en_s cn61xx;
- struct cvmx_gmxx_clk_en_s cn63xx;
- struct cvmx_gmxx_clk_en_s cn63xxp1;
- struct cvmx_gmxx_clk_en_s cn66xx;
- struct cvmx_gmxx_clk_en_s cn68xx;
- struct cvmx_gmxx_clk_en_s cn68xxp1;
- struct cvmx_gmxx_clk_en_s cnf71xx;
-};
-
-union cvmx_gmxx_ebp_dis {
- uint64_t u64;
- struct cvmx_gmxx_ebp_dis_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t dis:16;
-#else
- uint64_t dis:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_ebp_dis_s cn68xx;
- struct cvmx_gmxx_ebp_dis_s cn68xxp1;
-};
-
-union cvmx_gmxx_ebp_msk {
- uint64_t u64;
- struct cvmx_gmxx_ebp_msk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t msk:16;
-#else
- uint64_t msk:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_ebp_msk_s cn68xx;
- struct cvmx_gmxx_ebp_msk_s cn68xxp1;
-};
-
union cvmx_gmxx_hg2_control {
uint64_t u64;
struct cvmx_gmxx_hg2_control_s {
@@ -2329,16 +357,6 @@
uint64_t reserved_19_63:45;
#endif
} s;
- struct cvmx_gmxx_hg2_control_s cn52xx;
- struct cvmx_gmxx_hg2_control_s cn52xxp1;
- struct cvmx_gmxx_hg2_control_s cn56xx;
- struct cvmx_gmxx_hg2_control_s cn61xx;
- struct cvmx_gmxx_hg2_control_s cn63xx;
- struct cvmx_gmxx_hg2_control_s cn63xxp1;
- struct cvmx_gmxx_hg2_control_s cn66xx;
- struct cvmx_gmxx_hg2_control_s cn68xx;
- struct cvmx_gmxx_hg2_control_s cn68xxp1;
- struct cvmx_gmxx_hg2_control_s cnf71xx;
};
union cvmx_gmxx_inf_mode {
@@ -2392,9 +410,6 @@
uint64_t reserved_2_63:62;
#endif
} cn31xx;
- struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
- struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
- struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
struct cvmx_gmxx_inf_mode_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
@@ -2414,11 +429,6 @@
uint64_t reserved_10_63:54;
#endif
} cn52xx;
- struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
- struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
- struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
- struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
- struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
struct cvmx_gmxx_inf_mode_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -2438,8 +448,6 @@
uint64_t reserved_12_63:52;
#endif
} cn61xx;
- struct cvmx_gmxx_inf_mode_cn61xx cn63xx;
- struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1;
struct cvmx_gmxx_inf_mode_cn66xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -2482,108 +490,6 @@
uint64_t reserved_12_63:52;
#endif
} cn68xx;
- struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1;
- struct cvmx_gmxx_inf_mode_cn61xx cnf71xx;
-};
-
-union cvmx_gmxx_nxa_adr {
- uint64_t u64;
- struct cvmx_gmxx_nxa_adr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_23_63:41;
- uint64_t pipe:7;
- uint64_t reserved_6_15:10;
- uint64_t prt:6;
-#else
- uint64_t prt:6;
- uint64_t reserved_6_15:10;
- uint64_t pipe:7;
- uint64_t reserved_23_63:41;
-#endif
- } s;
- struct cvmx_gmxx_nxa_adr_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_6_63:58;
- uint64_t prt:6;
-#else
- uint64_t prt:6;
- uint64_t reserved_6_63:58;
-#endif
- } cn30xx;
- struct cvmx_gmxx_nxa_adr_cn30xx cn31xx;
- struct cvmx_gmxx_nxa_adr_cn30xx cn38xx;
- struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2;
- struct cvmx_gmxx_nxa_adr_cn30xx cn50xx;
- struct cvmx_gmxx_nxa_adr_cn30xx cn52xx;
- struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1;
- struct cvmx_gmxx_nxa_adr_cn30xx cn56xx;
- struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1;
- struct cvmx_gmxx_nxa_adr_cn30xx cn58xx;
- struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1;
- struct cvmx_gmxx_nxa_adr_cn30xx cn61xx;
- struct cvmx_gmxx_nxa_adr_cn30xx cn63xx;
- struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1;
- struct cvmx_gmxx_nxa_adr_cn30xx cn66xx;
- struct cvmx_gmxx_nxa_adr_s cn68xx;
- struct cvmx_gmxx_nxa_adr_s cn68xxp1;
- struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx;
-};
-
-union cvmx_gmxx_pipe_status {
- uint64_t u64;
- struct cvmx_gmxx_pipe_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_20_63:44;
- uint64_t ovr:4;
- uint64_t reserved_12_15:4;
- uint64_t bp:4;
- uint64_t reserved_4_7:4;
- uint64_t stop:4;
-#else
- uint64_t stop:4;
- uint64_t reserved_4_7:4;
- uint64_t bp:4;
- uint64_t reserved_12_15:4;
- uint64_t ovr:4;
- uint64_t reserved_20_63:44;
-#endif
- } s;
- struct cvmx_gmxx_pipe_status_s cn68xx;
- struct cvmx_gmxx_pipe_status_s cn68xxp1;
-};
-
-union cvmx_gmxx_prtx_cbfc_ctl {
- uint64_t u64;
- struct cvmx_gmxx_prtx_cbfc_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t phys_en:16;
- uint64_t logl_en:16;
- uint64_t phys_bp:16;
- uint64_t reserved_4_15:12;
- uint64_t bck_en:1;
- uint64_t drp_en:1;
- uint64_t tx_en:1;
- uint64_t rx_en:1;
-#else
- uint64_t rx_en:1;
- uint64_t tx_en:1;
- uint64_t drp_en:1;
- uint64_t bck_en:1;
- uint64_t reserved_4_15:12;
- uint64_t phys_bp:16;
- uint64_t logl_en:16;
- uint64_t phys_en:16;
-#endif
- } s;
- struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
- struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
- struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx;
- struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx;
- struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1;
- struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx;
- struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx;
- struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1;
- struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx;
};
union cvmx_gmxx_prtx_cfg {
@@ -2632,10 +538,6 @@
uint64_t reserved_4_63:60;
#endif
} cn30xx;
- struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
- struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
- struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
- struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
struct cvmx_gmxx_prtx_cfg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
@@ -2661,240 +563,6 @@
uint64_t reserved_14_63:50;
#endif
} cn52xx;
- struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1;
- struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx;
- struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1;
- struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
- struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
- struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx;
- struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx;
- struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1;
- struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx;
- struct cvmx_gmxx_prtx_cfg_s cn68xx;
- struct cvmx_gmxx_prtx_cfg_s cn68xxp1;
- struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam0 {
- uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t adr:64;
-#else
- uint64_t adr:64;
-#endif
- } s;
- struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn38xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;
- struct cvmx_gmxx_rxx_adr_cam0_s cn50xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn52xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;
- struct cvmx_gmxx_rxx_adr_cam0_s cn56xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
- struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
- struct cvmx_gmxx_rxx_adr_cam0_s cn61xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn63xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1;
- struct cvmx_gmxx_rxx_adr_cam0_s cn66xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn68xx;
- struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1;
- struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam1 {
- uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t adr:64;
-#else
- uint64_t adr:64;
-#endif
- } s;
- struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn38xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;
- struct cvmx_gmxx_rxx_adr_cam1_s cn50xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn52xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;
- struct cvmx_gmxx_rxx_adr_cam1_s cn56xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
- struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
- struct cvmx_gmxx_rxx_adr_cam1_s cn61xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn63xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1;
- struct cvmx_gmxx_rxx_adr_cam1_s cn66xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn68xx;
- struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1;
- struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam2 {
- uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t adr:64;
-#else
- uint64_t adr:64;
-#endif
- } s;
- struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn38xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;
- struct cvmx_gmxx_rxx_adr_cam2_s cn50xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn52xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;
- struct cvmx_gmxx_rxx_adr_cam2_s cn56xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
- struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
- struct cvmx_gmxx_rxx_adr_cam2_s cn61xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn63xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1;
- struct cvmx_gmxx_rxx_adr_cam2_s cn66xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn68xx;
- struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1;
- struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam3 {
- uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t adr:64;
-#else
- uint64_t adr:64;
-#endif
- } s;
- struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn38xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;
- struct cvmx_gmxx_rxx_adr_cam3_s cn50xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn52xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;
- struct cvmx_gmxx_rxx_adr_cam3_s cn56xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
- struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
- struct cvmx_gmxx_rxx_adr_cam3_s cn61xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn63xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1;
- struct cvmx_gmxx_rxx_adr_cam3_s cn66xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn68xx;
- struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1;
- struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam4 {
- uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t adr:64;
-#else
- uint64_t adr:64;
-#endif
- } s;
- struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn38xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;
- struct cvmx_gmxx_rxx_adr_cam4_s cn50xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn52xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;
- struct cvmx_gmxx_rxx_adr_cam4_s cn56xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
- struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
- struct cvmx_gmxx_rxx_adr_cam4_s cn61xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn63xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1;
- struct cvmx_gmxx_rxx_adr_cam4_s cn66xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn68xx;
- struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1;
- struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam5 {
- uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam5_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t adr:64;
-#else
- uint64_t adr:64;
-#endif
- } s;
- struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn38xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;
- struct cvmx_gmxx_rxx_adr_cam5_s cn50xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn52xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;
- struct cvmx_gmxx_rxx_adr_cam5_s cn56xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
- struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
- struct cvmx_gmxx_rxx_adr_cam5_s cn61xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn63xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1;
- struct cvmx_gmxx_rxx_adr_cam5_s cn66xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn68xx;
- struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1;
- struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam_all_en {
- uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam_all_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t en:32;
-#else
- uint64_t en:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx;
- struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx;
- struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx;
- struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_adr_cam_en {
- uint64_t u64;
- struct cvmx_gmxx_rxx_adr_cam_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_8_63:56;
- uint64_t en:8;
-#else
- uint64_t en:8;
- uint64_t reserved_8_63:56;
-#endif
- } s;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx;
- struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1;
- struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx;
};
union cvmx_gmxx_rxx_adr_ctl {
@@ -2912,174 +580,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn38xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;
- struct cvmx_gmxx_rxx_adr_ctl_s cn50xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn52xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;
- struct cvmx_gmxx_rxx_adr_ctl_s cn56xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
- struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
- struct cvmx_gmxx_rxx_adr_ctl_s cn61xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn63xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1;
- struct cvmx_gmxx_rxx_adr_ctl_s cn66xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn68xx;
- struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1;
- struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_decision {
- uint64_t u64;
- struct cvmx_gmxx_rxx_decision_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_5_63:59;
- uint64_t cnt:5;
-#else
- uint64_t cnt:5;
- uint64_t reserved_5_63:59;
-#endif
- } s;
- struct cvmx_gmxx_rxx_decision_s cn30xx;
- struct cvmx_gmxx_rxx_decision_s cn31xx;
- struct cvmx_gmxx_rxx_decision_s cn38xx;
- struct cvmx_gmxx_rxx_decision_s cn38xxp2;
- struct cvmx_gmxx_rxx_decision_s cn50xx;
- struct cvmx_gmxx_rxx_decision_s cn52xx;
- struct cvmx_gmxx_rxx_decision_s cn52xxp1;
- struct cvmx_gmxx_rxx_decision_s cn56xx;
- struct cvmx_gmxx_rxx_decision_s cn56xxp1;
- struct cvmx_gmxx_rxx_decision_s cn58xx;
- struct cvmx_gmxx_rxx_decision_s cn58xxp1;
- struct cvmx_gmxx_rxx_decision_s cn61xx;
- struct cvmx_gmxx_rxx_decision_s cn63xx;
- struct cvmx_gmxx_rxx_decision_s cn63xxp1;
- struct cvmx_gmxx_rxx_decision_s cn66xx;
- struct cvmx_gmxx_rxx_decision_s cn68xx;
- struct cvmx_gmxx_rxx_decision_s cn68xxp1;
- struct cvmx_gmxx_rxx_decision_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_frm_chk {
- uint64_t u64;
- struct cvmx_gmxx_rxx_frm_chk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_10_63:54;
- uint64_t niberr:1;
- uint64_t skperr:1;
- uint64_t rcverr:1;
- uint64_t lenerr:1;
- uint64_t alnerr:1;
- uint64_t fcserr:1;
- uint64_t jabber:1;
- uint64_t maxerr:1;
- uint64_t carext:1;
- uint64_t minerr:1;
-#else
- uint64_t minerr:1;
- uint64_t carext:1;
- uint64_t maxerr:1;
- uint64_t jabber:1;
- uint64_t fcserr:1;
- uint64_t alnerr:1;
- uint64_t lenerr:1;
- uint64_t rcverr:1;
- uint64_t skperr:1;
- uint64_t niberr:1;
- uint64_t reserved_10_63:54;
-#endif
- } s;
- struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
- struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
- struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
- struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
- struct cvmx_gmxx_rxx_frm_chk_cn50xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_10_63:54;
- uint64_t niberr:1;
- uint64_t skperr:1;
- uint64_t rcverr:1;
- uint64_t reserved_6_6:1;
- uint64_t alnerr:1;
- uint64_t fcserr:1;
- uint64_t jabber:1;
- uint64_t reserved_2_2:1;
- uint64_t carext:1;
- uint64_t reserved_0_0:1;
-#else
- uint64_t reserved_0_0:1;
- uint64_t carext:1;
- uint64_t reserved_2_2:1;
- uint64_t jabber:1;
- uint64_t fcserr:1;
- uint64_t alnerr:1;
- uint64_t reserved_6_6:1;
- uint64_t rcverr:1;
- uint64_t skperr:1;
- uint64_t niberr:1;
- uint64_t reserved_10_63:54;
-#endif
- } cn50xx;
- struct cvmx_gmxx_rxx_frm_chk_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_9_63:55;
- uint64_t skperr:1;
- uint64_t rcverr:1;
- uint64_t reserved_5_6:2;
- uint64_t fcserr:1;
- uint64_t jabber:1;
- uint64_t reserved_2_2:1;
- uint64_t carext:1;
- uint64_t reserved_0_0:1;
-#else
- uint64_t reserved_0_0:1;
- uint64_t carext:1;
- uint64_t reserved_2_2:1;
- uint64_t jabber:1;
- uint64_t fcserr:1;
- uint64_t reserved_5_6:2;
- uint64_t rcverr:1;
- uint64_t skperr:1;
- uint64_t reserved_9_63:55;
-#endif
- } cn52xx;
- struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
- struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
- struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
- struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
- struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
- struct cvmx_gmxx_rxx_frm_chk_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_9_63:55;
- uint64_t skperr:1;
- uint64_t rcverr:1;
- uint64_t reserved_5_6:2;
- uint64_t fcserr:1;
- uint64_t jabber:1;
- uint64_t reserved_2_2:1;
- uint64_t carext:1;
- uint64_t minerr:1;
-#else
- uint64_t minerr:1;
- uint64_t carext:1;
- uint64_t reserved_2_2:1;
- uint64_t jabber:1;
- uint64_t fcserr:1;
- uint64_t reserved_5_6:2;
- uint64_t rcverr:1;
- uint64_t skperr:1;
- uint64_t reserved_9_63:55;
-#endif
- } cn61xx;
- struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx;
- struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1;
- struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx;
- struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx;
- struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1;
- struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx;
};
union cvmx_gmxx_rxx_frm_ctl {
@@ -3165,8 +665,6 @@
uint64_t reserved_8_63:56;
#endif
} cn31xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
@@ -3194,9 +692,6 @@
uint64_t reserved_11_63:53;
#endif
} cn50xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
- struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
@@ -3251,7 +746,6 @@
uint64_t reserved_11_63:53;
#endif
} cn58xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
@@ -3283,12 +777,6 @@
uint64_t reserved_13_63:51;
#endif
} cn61xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1;
- struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx;
- struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1;
- struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx;
};
union cvmx_gmxx_rxx_frm_max {
@@ -3302,12 +790,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_gmxx_rxx_frm_max_s cn30xx;
- struct cvmx_gmxx_rxx_frm_max_s cn31xx;
- struct cvmx_gmxx_rxx_frm_max_s cn38xx;
- struct cvmx_gmxx_rxx_frm_max_s cn38xxp2;
- struct cvmx_gmxx_rxx_frm_max_s cn58xx;
- struct cvmx_gmxx_rxx_frm_max_s cn58xxp1;
};
union cvmx_gmxx_rxx_frm_min {
@@ -3321,43 +803,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_gmxx_rxx_frm_min_s cn30xx;
- struct cvmx_gmxx_rxx_frm_min_s cn31xx;
- struct cvmx_gmxx_rxx_frm_min_s cn38xx;
- struct cvmx_gmxx_rxx_frm_min_s cn38xxp2;
- struct cvmx_gmxx_rxx_frm_min_s cn58xx;
- struct cvmx_gmxx_rxx_frm_min_s cn58xxp1;
-};
-
-union cvmx_gmxx_rxx_ifg {
- uint64_t u64;
- struct cvmx_gmxx_rxx_ifg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t ifg:4;
-#else
- uint64_t ifg:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_gmxx_rxx_ifg_s cn30xx;
- struct cvmx_gmxx_rxx_ifg_s cn31xx;
- struct cvmx_gmxx_rxx_ifg_s cn38xx;
- struct cvmx_gmxx_rxx_ifg_s cn38xxp2;
- struct cvmx_gmxx_rxx_ifg_s cn50xx;
- struct cvmx_gmxx_rxx_ifg_s cn52xx;
- struct cvmx_gmxx_rxx_ifg_s cn52xxp1;
- struct cvmx_gmxx_rxx_ifg_s cn56xx;
- struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
- struct cvmx_gmxx_rxx_ifg_s cn58xx;
- struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
- struct cvmx_gmxx_rxx_ifg_s cn61xx;
- struct cvmx_gmxx_rxx_ifg_s cn63xx;
- struct cvmx_gmxx_rxx_ifg_s cn63xxp1;
- struct cvmx_gmxx_rxx_ifg_s cn66xx;
- struct cvmx_gmxx_rxx_ifg_s cn68xx;
- struct cvmx_gmxx_rxx_ifg_s cn68xxp1;
- struct cvmx_gmxx_rxx_ifg_s cnf71xx;
};
union cvmx_gmxx_rxx_int_en {
@@ -3472,9 +917,6 @@
uint64_t reserved_19_63:45;
#endif
} cn30xx;
- struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
- struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
- struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
struct cvmx_gmxx_rxx_int_en_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -3581,8 +1023,6 @@
uint64_t reserved_29_63:35;
#endif
} cn52xx;
- struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
- struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_27_63:37;
@@ -3685,7 +1125,6 @@
uint64_t reserved_20_63:44;
#endif
} cn58xx;
- struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
struct cvmx_gmxx_rxx_int_en_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
@@ -3745,12 +1184,6 @@
uint64_t reserved_29_63:35;
#endif
} cn61xx;
- struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx;
- struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1;
- struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx;
- struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx;
- struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1;
- struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx;
};
union cvmx_gmxx_rxx_int_reg {
@@ -3865,9 +1298,6 @@
uint64_t reserved_19_63:45;
#endif
} cn30xx;
- struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
- struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
- struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
struct cvmx_gmxx_rxx_int_reg_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -3974,8 +1404,6 @@
uint64_t reserved_29_63:35;
#endif
} cn52xx;
- struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;
- struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;
struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_27_63:37;
@@ -4078,7 +1506,6 @@
uint64_t reserved_20_63:44;
#endif
} cn58xx;
- struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;
struct cvmx_gmxx_rxx_int_reg_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
@@ -4138,12 +1565,6 @@
uint64_t reserved_29_63:35;
#endif
} cn61xx;
- struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx;
- struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1;
- struct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx;
- struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx;
- struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1;
- struct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx;
};
union cvmx_gmxx_rxx_jabber {
@@ -4157,51 +1578,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_gmxx_rxx_jabber_s cn30xx;
- struct cvmx_gmxx_rxx_jabber_s cn31xx;
- struct cvmx_gmxx_rxx_jabber_s cn38xx;
- struct cvmx_gmxx_rxx_jabber_s cn38xxp2;
- struct cvmx_gmxx_rxx_jabber_s cn50xx;
- struct cvmx_gmxx_rxx_jabber_s cn52xx;
- struct cvmx_gmxx_rxx_jabber_s cn52xxp1;
- struct cvmx_gmxx_rxx_jabber_s cn56xx;
- struct cvmx_gmxx_rxx_jabber_s cn56xxp1;
- struct cvmx_gmxx_rxx_jabber_s cn58xx;
- struct cvmx_gmxx_rxx_jabber_s cn58xxp1;
- struct cvmx_gmxx_rxx_jabber_s cn61xx;
- struct cvmx_gmxx_rxx_jabber_s cn63xx;
- struct cvmx_gmxx_rxx_jabber_s cn63xxp1;
- struct cvmx_gmxx_rxx_jabber_s cn66xx;
- struct cvmx_gmxx_rxx_jabber_s cn68xx;
- struct cvmx_gmxx_rxx_jabber_s cn68xxp1;
- struct cvmx_gmxx_rxx_jabber_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_pause_drop_time {
- uint64_t u64;
- struct cvmx_gmxx_rxx_pause_drop_time_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t status:16;
-#else
- uint64_t status:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx;
- struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1;
- struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx;
};
union cvmx_gmxx_rxx_rx_inbnd {
@@ -4219,588 +1595,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx;
- struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx;
- struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx;
- struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2;
- struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx;
- struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx;
- struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1;
-};
-
-union cvmx_gmxx_rxx_stats_ctl {
- uint64_t u64;
- struct cvmx_gmxx_rxx_stats_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t rd_clr:1;
-#else
- uint64_t rd_clr:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_gmxx_rxx_stats_ctl_s cn30xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn31xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn38xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2;
- struct cvmx_gmxx_rxx_stats_ctl_s cn50xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn52xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1;
- struct cvmx_gmxx_rxx_stats_ctl_s cn56xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;
- struct cvmx_gmxx_rxx_stats_ctl_s cn58xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;
- struct cvmx_gmxx_rxx_stats_ctl_s cn61xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn63xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1;
- struct cvmx_gmxx_rxx_stats_ctl_s cn66xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn68xx;
- struct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1;
- struct cvmx_gmxx_rxx_stats_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_octs {
- uint64_t u64;
- struct cvmx_gmxx_rxx_stats_octs_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_48_63:16;
- uint64_t cnt:48;
-#else
- uint64_t cnt:48;
- uint64_t reserved_48_63:16;
-#endif
- } s;
- struct cvmx_gmxx_rxx_stats_octs_s cn30xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn31xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn38xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2;
- struct cvmx_gmxx_rxx_stats_octs_s cn50xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn52xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1;
- struct cvmx_gmxx_rxx_stats_octs_s cn56xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;
- struct cvmx_gmxx_rxx_stats_octs_s cn58xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;
- struct cvmx_gmxx_rxx_stats_octs_s cn61xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn63xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn63xxp1;
- struct cvmx_gmxx_rxx_stats_octs_s cn66xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn68xx;
- struct cvmx_gmxx_rxx_stats_octs_s cn68xxp1;
- struct cvmx_gmxx_rxx_stats_octs_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_octs_ctl {
- uint64_t u64;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_48_63:16;
- uint64_t cnt:48;
-#else
- uint64_t cnt:48;
- uint64_t reserved_48_63:16;
-#endif
- } s;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1;
- struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_octs_dmac {
- uint64_t u64;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_48_63:16;
- uint64_t cnt:48;
-#else
- uint64_t cnt:48;
- uint64_t reserved_48_63:16;
-#endif
- } s;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1;
- struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_octs_drp {
- uint64_t u64;
- struct cvmx_gmxx_rxx_stats_octs_drp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_48_63:16;
- uint64_t cnt:48;
-#else
- uint64_t cnt:48;
- uint64_t reserved_48_63:16;
-#endif
- } s;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1;
- struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_pkts {
- uint64_t u64;
- struct cvmx_gmxx_rxx_stats_pkts_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t cnt:32;
-#else
- uint64_t cnt:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_gmxx_rxx_stats_pkts_s cn30xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn31xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn38xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2;
- struct cvmx_gmxx_rxx_stats_pkts_s cn50xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn52xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_s cn56xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_s cn58xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_s cn61xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn63xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_s cn66xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn68xx;
- struct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_pkts_bad {
- uint64_t u64;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t cnt:32;
-#else
- uint64_t cnt:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_pkts_ctl {
- uint64_t u64;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t cnt:32;
-#else
- uint64_t cnt:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_pkts_dmac {
- uint64_t u64;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t cnt:32;
-#else
- uint64_t cnt:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_stats_pkts_drp {
- uint64_t u64;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t cnt:32;
-#else
- uint64_t cnt:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1;
- struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx;
-};
-
-union cvmx_gmxx_rxx_udd_skp {
- uint64_t u64;
- struct cvmx_gmxx_rxx_udd_skp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_9_63:55;
- uint64_t fcssel:1;
- uint64_t reserved_7_7:1;
- uint64_t len:7;
-#else
- uint64_t len:7;
- uint64_t reserved_7_7:1;
- uint64_t fcssel:1;
- uint64_t reserved_9_63:55;
-#endif
- } s;
- struct cvmx_gmxx_rxx_udd_skp_s cn30xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn31xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn38xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2;
- struct cvmx_gmxx_rxx_udd_skp_s cn50xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn52xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1;
- struct cvmx_gmxx_rxx_udd_skp_s cn56xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;
- struct cvmx_gmxx_rxx_udd_skp_s cn58xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;
- struct cvmx_gmxx_rxx_udd_skp_s cn61xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn63xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn63xxp1;
- struct cvmx_gmxx_rxx_udd_skp_s cn66xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn68xx;
- struct cvmx_gmxx_rxx_udd_skp_s cn68xxp1;
- struct cvmx_gmxx_rxx_udd_skp_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_bp_dropx {
- uint64_t u64;
- struct cvmx_gmxx_rx_bp_dropx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_6_63:58;
- uint64_t mark:6;
-#else
- uint64_t mark:6;
- uint64_t reserved_6_63:58;
-#endif
- } s;
- struct cvmx_gmxx_rx_bp_dropx_s cn30xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn31xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn38xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2;
- struct cvmx_gmxx_rx_bp_dropx_s cn50xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn52xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1;
- struct cvmx_gmxx_rx_bp_dropx_s cn56xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;
- struct cvmx_gmxx_rx_bp_dropx_s cn58xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;
- struct cvmx_gmxx_rx_bp_dropx_s cn61xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn63xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn63xxp1;
- struct cvmx_gmxx_rx_bp_dropx_s cn66xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn68xx;
- struct cvmx_gmxx_rx_bp_dropx_s cn68xxp1;
- struct cvmx_gmxx_rx_bp_dropx_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_bp_offx {
- uint64_t u64;
- struct cvmx_gmxx_rx_bp_offx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_6_63:58;
- uint64_t mark:6;
-#else
- uint64_t mark:6;
- uint64_t reserved_6_63:58;
-#endif
- } s;
- struct cvmx_gmxx_rx_bp_offx_s cn30xx;
- struct cvmx_gmxx_rx_bp_offx_s cn31xx;
- struct cvmx_gmxx_rx_bp_offx_s cn38xx;
- struct cvmx_gmxx_rx_bp_offx_s cn38xxp2;
- struct cvmx_gmxx_rx_bp_offx_s cn50xx;
- struct cvmx_gmxx_rx_bp_offx_s cn52xx;
- struct cvmx_gmxx_rx_bp_offx_s cn52xxp1;
- struct cvmx_gmxx_rx_bp_offx_s cn56xx;
- struct cvmx_gmxx_rx_bp_offx_s cn56xxp1;
- struct cvmx_gmxx_rx_bp_offx_s cn58xx;
- struct cvmx_gmxx_rx_bp_offx_s cn58xxp1;
- struct cvmx_gmxx_rx_bp_offx_s cn61xx;
- struct cvmx_gmxx_rx_bp_offx_s cn63xx;
- struct cvmx_gmxx_rx_bp_offx_s cn63xxp1;
- struct cvmx_gmxx_rx_bp_offx_s cn66xx;
- struct cvmx_gmxx_rx_bp_offx_s cn68xx;
- struct cvmx_gmxx_rx_bp_offx_s cn68xxp1;
- struct cvmx_gmxx_rx_bp_offx_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_bp_onx {
- uint64_t u64;
- struct cvmx_gmxx_rx_bp_onx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_11_63:53;
- uint64_t mark:11;
-#else
- uint64_t mark:11;
- uint64_t reserved_11_63:53;
-#endif
- } s;
- struct cvmx_gmxx_rx_bp_onx_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_9_63:55;
- uint64_t mark:9;
-#else
- uint64_t mark:9;
- uint64_t reserved_9_63:55;
-#endif
- } cn30xx;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx;
- struct cvmx_gmxx_rx_bp_onx_s cn68xx;
- struct cvmx_gmxx_rx_bp_onx_s cn68xxp1;
- struct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx;
-};
-
-union cvmx_gmxx_rx_hg2_status {
- uint64_t u64;
- struct cvmx_gmxx_rx_hg2_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_48_63:16;
- uint64_t phtim2go:16;
- uint64_t xof:16;
- uint64_t lgtim2go:16;
-#else
- uint64_t lgtim2go:16;
- uint64_t xof:16;
- uint64_t phtim2go:16;
- uint64_t reserved_48_63:16;
-#endif
- } s;
- struct cvmx_gmxx_rx_hg2_status_s cn52xx;
- struct cvmx_gmxx_rx_hg2_status_s cn52xxp1;
- struct cvmx_gmxx_rx_hg2_status_s cn56xx;
- struct cvmx_gmxx_rx_hg2_status_s cn61xx;
- struct cvmx_gmxx_rx_hg2_status_s cn63xx;
- struct cvmx_gmxx_rx_hg2_status_s cn63xxp1;
- struct cvmx_gmxx_rx_hg2_status_s cn66xx;
- struct cvmx_gmxx_rx_hg2_status_s cn68xx;
- struct cvmx_gmxx_rx_hg2_status_s cn68xxp1;
- struct cvmx_gmxx_rx_hg2_status_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_pass_en {
- uint64_t u64;
- struct cvmx_gmxx_rx_pass_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t en:16;
-#else
- uint64_t en:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_rx_pass_en_s cn38xx;
- struct cvmx_gmxx_rx_pass_en_s cn38xxp2;
- struct cvmx_gmxx_rx_pass_en_s cn58xx;
- struct cvmx_gmxx_rx_pass_en_s cn58xxp1;
-};
-
-union cvmx_gmxx_rx_pass_mapx {
- uint64_t u64;
- struct cvmx_gmxx_rx_pass_mapx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t dprt:4;
-#else
- uint64_t dprt:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_gmxx_rx_pass_mapx_s cn38xx;
- struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2;
- struct cvmx_gmxx_rx_pass_mapx_s cn58xx;
- struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1;
-};
-
-union cvmx_gmxx_rx_prt_info {
- uint64_t u64;
- struct cvmx_gmxx_rx_prt_info_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t drop:16;
- uint64_t commit:16;
-#else
- uint64_t commit:16;
- uint64_t drop:16;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_gmxx_rx_prt_info_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_19_63:45;
- uint64_t drop:3;
- uint64_t reserved_3_15:13;
- uint64_t commit:3;
-#else
- uint64_t commit:3;
- uint64_t reserved_3_15:13;
- uint64_t drop:3;
- uint64_t reserved_19_63:45;
-#endif
- } cn30xx;
- struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;
- struct cvmx_gmxx_rx_prt_info_s cn38xx;
- struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;
- struct cvmx_gmxx_rx_prt_info_cn52xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_20_63:44;
- uint64_t drop:4;
- uint64_t reserved_4_15:12;
- uint64_t commit:4;
-#else
- uint64_t commit:4;
- uint64_t reserved_4_15:12;
- uint64_t drop:4;
- uint64_t reserved_20_63:44;
-#endif
- } cn52xx;
- struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1;
- struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx;
- struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;
- struct cvmx_gmxx_rx_prt_info_s cn58xx;
- struct cvmx_gmxx_rx_prt_info_s cn58xxp1;
- struct cvmx_gmxx_rx_prt_info_cn52xx cn61xx;
- struct cvmx_gmxx_rx_prt_info_cn52xx cn63xx;
- struct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1;
- struct cvmx_gmxx_rx_prt_info_cn52xx cn66xx;
- struct cvmx_gmxx_rx_prt_info_cn52xx cn68xx;
- struct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1;
- struct cvmx_gmxx_rx_prt_info_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_18_63:46;
- uint64_t drop:2;
- uint64_t reserved_2_15:14;
- uint64_t commit:2;
-#else
- uint64_t commit:2;
- uint64_t reserved_2_15:14;
- uint64_t drop:2;
- uint64_t reserved_18_63:46;
-#endif
- } cnf71xx;
};
union cvmx_gmxx_rx_prts {
@@ -4814,74 +1608,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_gmxx_rx_prts_s cn30xx;
- struct cvmx_gmxx_rx_prts_s cn31xx;
- struct cvmx_gmxx_rx_prts_s cn38xx;
- struct cvmx_gmxx_rx_prts_s cn38xxp2;
- struct cvmx_gmxx_rx_prts_s cn50xx;
- struct cvmx_gmxx_rx_prts_s cn52xx;
- struct cvmx_gmxx_rx_prts_s cn52xxp1;
- struct cvmx_gmxx_rx_prts_s cn56xx;
- struct cvmx_gmxx_rx_prts_s cn56xxp1;
- struct cvmx_gmxx_rx_prts_s cn58xx;
- struct cvmx_gmxx_rx_prts_s cn58xxp1;
- struct cvmx_gmxx_rx_prts_s cn61xx;
- struct cvmx_gmxx_rx_prts_s cn63xx;
- struct cvmx_gmxx_rx_prts_s cn63xxp1;
- struct cvmx_gmxx_rx_prts_s cn66xx;
- struct cvmx_gmxx_rx_prts_s cn68xx;
- struct cvmx_gmxx_rx_prts_s cn68xxp1;
- struct cvmx_gmxx_rx_prts_s cnf71xx;
-};
-
-union cvmx_gmxx_rx_tx_status {
- uint64_t u64;
- struct cvmx_gmxx_rx_tx_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_7_63:57;
- uint64_t tx:3;
- uint64_t reserved_3_3:1;
- uint64_t rx:3;
-#else
- uint64_t rx:3;
- uint64_t reserved_3_3:1;
- uint64_t tx:3;
- uint64_t reserved_7_63:57;
-#endif
- } s;
- struct cvmx_gmxx_rx_tx_status_s cn30xx;
- struct cvmx_gmxx_rx_tx_status_s cn31xx;
- struct cvmx_gmxx_rx_tx_status_s cn50xx;
-};
-
-union cvmx_gmxx_rx_xaui_bad_col {
- uint64_t u64;
- struct cvmx_gmxx_rx_xaui_bad_col_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_40_63:24;
- uint64_t val:1;
- uint64_t state:3;
- uint64_t lane_rxc:4;
- uint64_t lane_rxd:32;
-#else
- uint64_t lane_rxd:32;
- uint64_t lane_rxc:4;
- uint64_t state:3;
- uint64_t val:1;
- uint64_t reserved_40_63:24;
-#endif
- } s;
- struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx;
- struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;
- struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;
- struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;
- struct cvmx_gmxx_rx_xaui_bad_col_s cn61xx;
- struct cvmx_gmxx_rx_xaui_bad_col_s cn63xx;
- struct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1;
- struct cvmx_gmxx_rx_xaui_bad_col_s cn66xx;
- struct cvmx_gmxx_rx_xaui_bad_col_s cn68xx;
- struct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1;
- struct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx;
};
union cvmx_gmxx_rx_xaui_ctl {
@@ -4895,913 +1621,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_gmxx_rx_xaui_ctl_s cn52xx;
- struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;
- struct cvmx_gmxx_rx_xaui_ctl_s cn56xx;
- struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;
- struct cvmx_gmxx_rx_xaui_ctl_s cn61xx;
- struct cvmx_gmxx_rx_xaui_ctl_s cn63xx;
- struct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1;
- struct cvmx_gmxx_rx_xaui_ctl_s cn66xx;
- struct cvmx_gmxx_rx_xaui_ctl_s cn68xx;
- struct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1;
- struct cvmx_gmxx_rx_xaui_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_rxaui_ctl {
- uint64_t u64;
- struct cvmx_gmxx_rxaui_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t disparity:1;
-#else
- uint64_t disparity:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_gmxx_rxaui_ctl_s cn68xx;
- struct cvmx_gmxx_rxaui_ctl_s cn68xxp1;
-};
-
-union cvmx_gmxx_smacx {
- uint64_t u64;
- struct cvmx_gmxx_smacx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_48_63:16;
- uint64_t smac:48;
-#else
- uint64_t smac:48;
- uint64_t reserved_48_63:16;
-#endif
- } s;
- struct cvmx_gmxx_smacx_s cn30xx;
- struct cvmx_gmxx_smacx_s cn31xx;
- struct cvmx_gmxx_smacx_s cn38xx;
- struct cvmx_gmxx_smacx_s cn38xxp2;
- struct cvmx_gmxx_smacx_s cn50xx;
- struct cvmx_gmxx_smacx_s cn52xx;
- struct cvmx_gmxx_smacx_s cn52xxp1;
- struct cvmx_gmxx_smacx_s cn56xx;
- struct cvmx_gmxx_smacx_s cn56xxp1;
- struct cvmx_gmxx_smacx_s cn58xx;
- struct cvmx_gmxx_smacx_s cn58xxp1;
- struct cvmx_gmxx_smacx_s cn61xx;
- struct cvmx_gmxx_smacx_s cn63xx;
- struct cvmx_gmxx_smacx_s cn63xxp1;
- struct cvmx_gmxx_smacx_s cn66xx;
- struct cvmx_gmxx_smacx_s cn68xx;
- struct cvmx_gmxx_smacx_s cn68xxp1;
- struct cvmx_gmxx_smacx_s cnf71xx;
-};
-
-union cvmx_gmxx_soft_bist {
- uint64_t u64;
- struct cvmx_gmxx_soft_bist_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_2_63:62;
- uint64_t start_bist:1;
- uint64_t clear_bist:1;
-#else
- uint64_t clear_bist:1;
- uint64_t start_bist:1;
- uint64_t reserved_2_63:62;
-#endif
- } s;
- struct cvmx_gmxx_soft_bist_s cn63xx;
- struct cvmx_gmxx_soft_bist_s cn63xxp1;
- struct cvmx_gmxx_soft_bist_s cn66xx;
- struct cvmx_gmxx_soft_bist_s cn68xx;
- struct cvmx_gmxx_soft_bist_s cn68xxp1;
-};
-
-union cvmx_gmxx_stat_bp {
- uint64_t u64;
- struct cvmx_gmxx_stat_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_17_63:47;
- uint64_t bp:1;
- uint64_t cnt:16;
-#else
- uint64_t cnt:16;
- uint64_t bp:1;
- uint64_t reserved_17_63:47;
-#endif
- } s;
- struct cvmx_gmxx_stat_bp_s cn30xx;
- struct cvmx_gmxx_stat_bp_s cn31xx;
- struct cvmx_gmxx_stat_bp_s cn38xx;
- struct cvmx_gmxx_stat_bp_s cn38xxp2;
- struct cvmx_gmxx_stat_bp_s cn50xx;
- struct cvmx_gmxx_stat_bp_s cn52xx;
- struct cvmx_gmxx_stat_bp_s cn52xxp1;
- struct cvmx_gmxx_stat_bp_s cn56xx;
- struct cvmx_gmxx_stat_bp_s cn56xxp1;
- struct cvmx_gmxx_stat_bp_s cn58xx;
- struct cvmx_gmxx_stat_bp_s cn58xxp1;
- struct cvmx_gmxx_stat_bp_s cn61xx;
- struct cvmx_gmxx_stat_bp_s cn63xx;
- struct cvmx_gmxx_stat_bp_s cn63xxp1;
- struct cvmx_gmxx_stat_bp_s cn66xx;
- struct cvmx_gmxx_stat_bp_s cn68xx;
- struct cvmx_gmxx_stat_bp_s cn68xxp1;
- struct cvmx_gmxx_stat_bp_s cnf71xx;
-};
-
-union cvmx_gmxx_tb_reg {
- uint64_t u64;
- struct cvmx_gmxx_tb_reg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t wr_magic:1;
-#else
- uint64_t wr_magic:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_gmxx_tb_reg_s cn61xx;
- struct cvmx_gmxx_tb_reg_s cn66xx;
- struct cvmx_gmxx_tb_reg_s cn68xx;
- struct cvmx_gmxx_tb_reg_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_append {
- uint64_t u64;
- struct cvmx_gmxx_txx_append_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t force_fcs:1;
- uint64_t fcs:1;
- uint64_t pad:1;
- uint64_t preamble:1;
-#else
- uint64_t preamble:1;
- uint64_t pad:1;
- uint64_t fcs:1;
- uint64_t force_fcs:1;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_gmxx_txx_append_s cn30xx;
- struct cvmx_gmxx_txx_append_s cn31xx;
- struct cvmx_gmxx_txx_append_s cn38xx;
- struct cvmx_gmxx_txx_append_s cn38xxp2;
- struct cvmx_gmxx_txx_append_s cn50xx;
- struct cvmx_gmxx_txx_append_s cn52xx;
- struct cvmx_gmxx_txx_append_s cn52xxp1;
- struct cvmx_gmxx_txx_append_s cn56xx;
- struct cvmx_gmxx_txx_append_s cn56xxp1;
- struct cvmx_gmxx_txx_append_s cn58xx;
- struct cvmx_gmxx_txx_append_s cn58xxp1;
- struct cvmx_gmxx_txx_append_s cn61xx;
- struct cvmx_gmxx_txx_append_s cn63xx;
- struct cvmx_gmxx_txx_append_s cn63xxp1;
- struct cvmx_gmxx_txx_append_s cn66xx;
- struct cvmx_gmxx_txx_append_s cn68xx;
- struct cvmx_gmxx_txx_append_s cn68xxp1;
- struct cvmx_gmxx_txx_append_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_burst {
- uint64_t u64;
- struct cvmx_gmxx_txx_burst_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t burst:16;
-#else
- uint64_t burst:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_txx_burst_s cn30xx;
- struct cvmx_gmxx_txx_burst_s cn31xx;
- struct cvmx_gmxx_txx_burst_s cn38xx;
- struct cvmx_gmxx_txx_burst_s cn38xxp2;
- struct cvmx_gmxx_txx_burst_s cn50xx;
- struct cvmx_gmxx_txx_burst_s cn52xx;
- struct cvmx_gmxx_txx_burst_s cn52xxp1;
- struct cvmx_gmxx_txx_burst_s cn56xx;
- struct cvmx_gmxx_txx_burst_s cn56xxp1;
- struct cvmx_gmxx_txx_burst_s cn58xx;
- struct cvmx_gmxx_txx_burst_s cn58xxp1;
- struct cvmx_gmxx_txx_burst_s cn61xx;
- struct cvmx_gmxx_txx_burst_s cn63xx;
- struct cvmx_gmxx_txx_burst_s cn63xxp1;
- struct cvmx_gmxx_txx_burst_s cn66xx;
- struct cvmx_gmxx_txx_burst_s cn68xx;
- struct cvmx_gmxx_txx_burst_s cn68xxp1;
- struct cvmx_gmxx_txx_burst_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_cbfc_xoff {
- uint64_t u64;
- struct cvmx_gmxx_txx_cbfc_xoff_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t xoff:16;
-#else
- uint64_t xoff:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;
- struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;
- struct cvmx_gmxx_txx_cbfc_xoff_s cn61xx;
- struct cvmx_gmxx_txx_cbfc_xoff_s cn63xx;
- struct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1;
- struct cvmx_gmxx_txx_cbfc_xoff_s cn66xx;
- struct cvmx_gmxx_txx_cbfc_xoff_s cn68xx;
- struct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1;
- struct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_cbfc_xon {
- uint64_t u64;
- struct cvmx_gmxx_txx_cbfc_xon_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t xon:16;
-#else
- uint64_t xon:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_txx_cbfc_xon_s cn52xx;
- struct cvmx_gmxx_txx_cbfc_xon_s cn56xx;
- struct cvmx_gmxx_txx_cbfc_xon_s cn61xx;
- struct cvmx_gmxx_txx_cbfc_xon_s cn63xx;
- struct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1;
- struct cvmx_gmxx_txx_cbfc_xon_s cn66xx;
- struct cvmx_gmxx_txx_cbfc_xon_s cn68xx;
- struct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1;
- struct cvmx_gmxx_txx_cbfc_xon_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_clk {
- uint64_t u64;
- struct cvmx_gmxx_txx_clk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_6_63:58;
- uint64_t clk_cnt:6;
-#else
- uint64_t clk_cnt:6;
- uint64_t reserved_6_63:58;
-#endif
- } s;
- struct cvmx_gmxx_txx_clk_s cn30xx;
- struct cvmx_gmxx_txx_clk_s cn31xx;
- struct cvmx_gmxx_txx_clk_s cn38xx;
- struct cvmx_gmxx_txx_clk_s cn38xxp2;
- struct cvmx_gmxx_txx_clk_s cn50xx;
- struct cvmx_gmxx_txx_clk_s cn58xx;
- struct cvmx_gmxx_txx_clk_s cn58xxp1;
-};
-
-union cvmx_gmxx_txx_ctl {
- uint64_t u64;
- struct cvmx_gmxx_txx_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_2_63:62;
- uint64_t xsdef_en:1;
- uint64_t xscol_en:1;
-#else
- uint64_t xscol_en:1;
- uint64_t xsdef_en:1;
- uint64_t reserved_2_63:62;
-#endif
- } s;
- struct cvmx_gmxx_txx_ctl_s cn30xx;
- struct cvmx_gmxx_txx_ctl_s cn31xx;
- struct cvmx_gmxx_txx_ctl_s cn38xx;
- struct cvmx_gmxx_txx_ctl_s cn38xxp2;
- struct cvmx_gmxx_txx_ctl_s cn50xx;
- struct cvmx_gmxx_txx_ctl_s cn52xx;
- struct cvmx_gmxx_txx_ctl_s cn52xxp1;
- struct cvmx_gmxx_txx_ctl_s cn56xx;
- struct cvmx_gmxx_txx_ctl_s cn56xxp1;
- struct cvmx_gmxx_txx_ctl_s cn58xx;
- struct cvmx_gmxx_txx_ctl_s cn58xxp1;
- struct cvmx_gmxx_txx_ctl_s cn61xx;
- struct cvmx_gmxx_txx_ctl_s cn63xx;
- struct cvmx_gmxx_txx_ctl_s cn63xxp1;
- struct cvmx_gmxx_txx_ctl_s cn66xx;
- struct cvmx_gmxx_txx_ctl_s cn68xx;
- struct cvmx_gmxx_txx_ctl_s cn68xxp1;
- struct cvmx_gmxx_txx_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_min_pkt {
- uint64_t u64;
- struct cvmx_gmxx_txx_min_pkt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_8_63:56;
- uint64_t min_size:8;
-#else
- uint64_t min_size:8;
- uint64_t reserved_8_63:56;
-#endif
- } s;
- struct cvmx_gmxx_txx_min_pkt_s cn30xx;
- struct cvmx_gmxx_txx_min_pkt_s cn31xx;
- struct cvmx_gmxx_txx_min_pkt_s cn38xx;
- struct cvmx_gmxx_txx_min_pkt_s cn38xxp2;
- struct cvmx_gmxx_txx_min_pkt_s cn50xx;
- struct cvmx_gmxx_txx_min_pkt_s cn52xx;
- struct cvmx_gmxx_txx_min_pkt_s cn52xxp1;
- struct cvmx_gmxx_txx_min_pkt_s cn56xx;
- struct cvmx_gmxx_txx_min_pkt_s cn56xxp1;
- struct cvmx_gmxx_txx_min_pkt_s cn58xx;
- struct cvmx_gmxx_txx_min_pkt_s cn58xxp1;
- struct cvmx_gmxx_txx_min_pkt_s cn61xx;
- struct cvmx_gmxx_txx_min_pkt_s cn63xx;
- struct cvmx_gmxx_txx_min_pkt_s cn63xxp1;
- struct cvmx_gmxx_txx_min_pkt_s cn66xx;
- struct cvmx_gmxx_txx_min_pkt_s cn68xx;
- struct cvmx_gmxx_txx_min_pkt_s cn68xxp1;
- struct cvmx_gmxx_txx_min_pkt_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_pause_pkt_interval {
- uint64_t u64;
- struct cvmx_gmxx_txx_pause_pkt_interval_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t interval:16;
-#else
- uint64_t interval:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1;
- struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_pause_pkt_time {
- uint64_t u64;
- struct cvmx_gmxx_txx_pause_pkt_time_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t time:16;
-#else
- uint64_t time:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx;
- struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1;
- struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_pause_togo {
- uint64_t u64;
- struct cvmx_gmxx_txx_pause_togo_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t msg_time:16;
- uint64_t time:16;
-#else
- uint64_t time:16;
- uint64_t msg_time:16;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_gmxx_txx_pause_togo_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t time:16;
-#else
- uint64_t time:16;
- uint64_t reserved_16_63:48;
-#endif
- } cn30xx;
- struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
- struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
- struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
- struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
- struct cvmx_gmxx_txx_pause_togo_s cn52xx;
- struct cvmx_gmxx_txx_pause_togo_s cn52xxp1;
- struct cvmx_gmxx_txx_pause_togo_s cn56xx;
- struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
- struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
- struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
- struct cvmx_gmxx_txx_pause_togo_s cn61xx;
- struct cvmx_gmxx_txx_pause_togo_s cn63xx;
- struct cvmx_gmxx_txx_pause_togo_s cn63xxp1;
- struct cvmx_gmxx_txx_pause_togo_s cn66xx;
- struct cvmx_gmxx_txx_pause_togo_s cn68xx;
- struct cvmx_gmxx_txx_pause_togo_s cn68xxp1;
- struct cvmx_gmxx_txx_pause_togo_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_pause_zero {
- uint64_t u64;
- struct cvmx_gmxx_txx_pause_zero_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t send:1;
-#else
- uint64_t send:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_gmxx_txx_pause_zero_s cn30xx;
- struct cvmx_gmxx_txx_pause_zero_s cn31xx;
- struct cvmx_gmxx_txx_pause_zero_s cn38xx;
- struct cvmx_gmxx_txx_pause_zero_s cn38xxp2;
- struct cvmx_gmxx_txx_pause_zero_s cn50xx;
- struct cvmx_gmxx_txx_pause_zero_s cn52xx;
- struct cvmx_gmxx_txx_pause_zero_s cn52xxp1;
- struct cvmx_gmxx_txx_pause_zero_s cn56xx;
- struct cvmx_gmxx_txx_pause_zero_s cn56xxp1;
- struct cvmx_gmxx_txx_pause_zero_s cn58xx;
- struct cvmx_gmxx_txx_pause_zero_s cn58xxp1;
- struct cvmx_gmxx_txx_pause_zero_s cn61xx;
- struct cvmx_gmxx_txx_pause_zero_s cn63xx;
- struct cvmx_gmxx_txx_pause_zero_s cn63xxp1;
- struct cvmx_gmxx_txx_pause_zero_s cn66xx;
- struct cvmx_gmxx_txx_pause_zero_s cn68xx;
- struct cvmx_gmxx_txx_pause_zero_s cn68xxp1;
- struct cvmx_gmxx_txx_pause_zero_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_pipe {
- uint64_t u64;
- struct cvmx_gmxx_txx_pipe_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_33_63:31;
- uint64_t ign_bp:1;
- uint64_t reserved_21_31:11;
- uint64_t nump:5;
- uint64_t reserved_7_15:9;
- uint64_t base:7;
-#else
- uint64_t base:7;
- uint64_t reserved_7_15:9;
- uint64_t nump:5;
- uint64_t reserved_21_31:11;
- uint64_t ign_bp:1;
- uint64_t reserved_33_63:31;
-#endif
- } s;
- struct cvmx_gmxx_txx_pipe_s cn68xx;
- struct cvmx_gmxx_txx_pipe_s cn68xxp1;
-};
-
-union cvmx_gmxx_txx_sgmii_ctl {
- uint64_t u64;
- struct cvmx_gmxx_txx_sgmii_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t align:1;
-#else
- uint64_t align:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx;
- struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;
- struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;
- struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;
- struct cvmx_gmxx_txx_sgmii_ctl_s cn61xx;
- struct cvmx_gmxx_txx_sgmii_ctl_s cn63xx;
- struct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1;
- struct cvmx_gmxx_txx_sgmii_ctl_s cn66xx;
- struct cvmx_gmxx_txx_sgmii_ctl_s cn68xx;
- struct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1;
- struct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_slot {
- uint64_t u64;
- struct cvmx_gmxx_txx_slot_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_10_63:54;
- uint64_t slot:10;
-#else
- uint64_t slot:10;
- uint64_t reserved_10_63:54;
-#endif
- } s;
- struct cvmx_gmxx_txx_slot_s cn30xx;
- struct cvmx_gmxx_txx_slot_s cn31xx;
- struct cvmx_gmxx_txx_slot_s cn38xx;
- struct cvmx_gmxx_txx_slot_s cn38xxp2;
- struct cvmx_gmxx_txx_slot_s cn50xx;
- struct cvmx_gmxx_txx_slot_s cn52xx;
- struct cvmx_gmxx_txx_slot_s cn52xxp1;
- struct cvmx_gmxx_txx_slot_s cn56xx;
- struct cvmx_gmxx_txx_slot_s cn56xxp1;
- struct cvmx_gmxx_txx_slot_s cn58xx;
- struct cvmx_gmxx_txx_slot_s cn58xxp1;
- struct cvmx_gmxx_txx_slot_s cn61xx;
- struct cvmx_gmxx_txx_slot_s cn63xx;
- struct cvmx_gmxx_txx_slot_s cn63xxp1;
- struct cvmx_gmxx_txx_slot_s cn66xx;
- struct cvmx_gmxx_txx_slot_s cn68xx;
- struct cvmx_gmxx_txx_slot_s cn68xxp1;
- struct cvmx_gmxx_txx_slot_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_soft_pause {
- uint64_t u64;
- struct cvmx_gmxx_txx_soft_pause_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t time:16;
-#else
- uint64_t time:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_txx_soft_pause_s cn30xx;
- struct cvmx_gmxx_txx_soft_pause_s cn31xx;
- struct cvmx_gmxx_txx_soft_pause_s cn38xx;
- struct cvmx_gmxx_txx_soft_pause_s cn38xxp2;
- struct cvmx_gmxx_txx_soft_pause_s cn50xx;
- struct cvmx_gmxx_txx_soft_pause_s cn52xx;
- struct cvmx_gmxx_txx_soft_pause_s cn52xxp1;
- struct cvmx_gmxx_txx_soft_pause_s cn56xx;
- struct cvmx_gmxx_txx_soft_pause_s cn56xxp1;
- struct cvmx_gmxx_txx_soft_pause_s cn58xx;
- struct cvmx_gmxx_txx_soft_pause_s cn58xxp1;
- struct cvmx_gmxx_txx_soft_pause_s cn61xx;
- struct cvmx_gmxx_txx_soft_pause_s cn63xx;
- struct cvmx_gmxx_txx_soft_pause_s cn63xxp1;
- struct cvmx_gmxx_txx_soft_pause_s cn66xx;
- struct cvmx_gmxx_txx_soft_pause_s cn68xx;
- struct cvmx_gmxx_txx_soft_pause_s cn68xxp1;
- struct cvmx_gmxx_txx_soft_pause_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat0 {
- uint64_t u64;
- struct cvmx_gmxx_txx_stat0_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t xsdef:32;
- uint64_t xscol:32;
-#else
- uint64_t xscol:32;
- uint64_t xsdef:32;
-#endif
- } s;
- struct cvmx_gmxx_txx_stat0_s cn30xx;
- struct cvmx_gmxx_txx_stat0_s cn31xx;
- struct cvmx_gmxx_txx_stat0_s cn38xx;
- struct cvmx_gmxx_txx_stat0_s cn38xxp2;
- struct cvmx_gmxx_txx_stat0_s cn50xx;
- struct cvmx_gmxx_txx_stat0_s cn52xx;
- struct cvmx_gmxx_txx_stat0_s cn52xxp1;
- struct cvmx_gmxx_txx_stat0_s cn56xx;
- struct cvmx_gmxx_txx_stat0_s cn56xxp1;
- struct cvmx_gmxx_txx_stat0_s cn58xx;
- struct cvmx_gmxx_txx_stat0_s cn58xxp1;
- struct cvmx_gmxx_txx_stat0_s cn61xx;
- struct cvmx_gmxx_txx_stat0_s cn63xx;
- struct cvmx_gmxx_txx_stat0_s cn63xxp1;
- struct cvmx_gmxx_txx_stat0_s cn66xx;
- struct cvmx_gmxx_txx_stat0_s cn68xx;
- struct cvmx_gmxx_txx_stat0_s cn68xxp1;
- struct cvmx_gmxx_txx_stat0_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat1 {
- uint64_t u64;
- struct cvmx_gmxx_txx_stat1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t scol:32;
- uint64_t mcol:32;
-#else
- uint64_t mcol:32;
- uint64_t scol:32;
-#endif
- } s;
- struct cvmx_gmxx_txx_stat1_s cn30xx;
- struct cvmx_gmxx_txx_stat1_s cn31xx;
- struct cvmx_gmxx_txx_stat1_s cn38xx;
- struct cvmx_gmxx_txx_stat1_s cn38xxp2;
- struct cvmx_gmxx_txx_stat1_s cn50xx;
- struct cvmx_gmxx_txx_stat1_s cn52xx;
- struct cvmx_gmxx_txx_stat1_s cn52xxp1;
- struct cvmx_gmxx_txx_stat1_s cn56xx;
- struct cvmx_gmxx_txx_stat1_s cn56xxp1;
- struct cvmx_gmxx_txx_stat1_s cn58xx;
- struct cvmx_gmxx_txx_stat1_s cn58xxp1;
- struct cvmx_gmxx_txx_stat1_s cn61xx;
- struct cvmx_gmxx_txx_stat1_s cn63xx;
- struct cvmx_gmxx_txx_stat1_s cn63xxp1;
- struct cvmx_gmxx_txx_stat1_s cn66xx;
- struct cvmx_gmxx_txx_stat1_s cn68xx;
- struct cvmx_gmxx_txx_stat1_s cn68xxp1;
- struct cvmx_gmxx_txx_stat1_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat2 {
- uint64_t u64;
- struct cvmx_gmxx_txx_stat2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_48_63:16;
- uint64_t octs:48;
-#else
- uint64_t octs:48;
- uint64_t reserved_48_63:16;
-#endif
- } s;
- struct cvmx_gmxx_txx_stat2_s cn30xx;
- struct cvmx_gmxx_txx_stat2_s cn31xx;
- struct cvmx_gmxx_txx_stat2_s cn38xx;
- struct cvmx_gmxx_txx_stat2_s cn38xxp2;
- struct cvmx_gmxx_txx_stat2_s cn50xx;
- struct cvmx_gmxx_txx_stat2_s cn52xx;
- struct cvmx_gmxx_txx_stat2_s cn52xxp1;
- struct cvmx_gmxx_txx_stat2_s cn56xx;
- struct cvmx_gmxx_txx_stat2_s cn56xxp1;
- struct cvmx_gmxx_txx_stat2_s cn58xx;
- struct cvmx_gmxx_txx_stat2_s cn58xxp1;
- struct cvmx_gmxx_txx_stat2_s cn61xx;
- struct cvmx_gmxx_txx_stat2_s cn63xx;
- struct cvmx_gmxx_txx_stat2_s cn63xxp1;
- struct cvmx_gmxx_txx_stat2_s cn66xx;
- struct cvmx_gmxx_txx_stat2_s cn68xx;
- struct cvmx_gmxx_txx_stat2_s cn68xxp1;
- struct cvmx_gmxx_txx_stat2_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat3 {
- uint64_t u64;
- struct cvmx_gmxx_txx_stat3_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_32_63:32;
- uint64_t pkts:32;
-#else
- uint64_t pkts:32;
- uint64_t reserved_32_63:32;
-#endif
- } s;
- struct cvmx_gmxx_txx_stat3_s cn30xx;
- struct cvmx_gmxx_txx_stat3_s cn31xx;
- struct cvmx_gmxx_txx_stat3_s cn38xx;
- struct cvmx_gmxx_txx_stat3_s cn38xxp2;
- struct cvmx_gmxx_txx_stat3_s cn50xx;
- struct cvmx_gmxx_txx_stat3_s cn52xx;
- struct cvmx_gmxx_txx_stat3_s cn52xxp1;
- struct cvmx_gmxx_txx_stat3_s cn56xx;
- struct cvmx_gmxx_txx_stat3_s cn56xxp1;
- struct cvmx_gmxx_txx_stat3_s cn58xx;
- struct cvmx_gmxx_txx_stat3_s cn58xxp1;
- struct cvmx_gmxx_txx_stat3_s cn61xx;
- struct cvmx_gmxx_txx_stat3_s cn63xx;
- struct cvmx_gmxx_txx_stat3_s cn63xxp1;
- struct cvmx_gmxx_txx_stat3_s cn66xx;
- struct cvmx_gmxx_txx_stat3_s cn68xx;
- struct cvmx_gmxx_txx_stat3_s cn68xxp1;
- struct cvmx_gmxx_txx_stat3_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat4 {
- uint64_t u64;
- struct cvmx_gmxx_txx_stat4_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t hist1:32;
- uint64_t hist0:32;
-#else
- uint64_t hist0:32;
- uint64_t hist1:32;
-#endif
- } s;
- struct cvmx_gmxx_txx_stat4_s cn30xx;
- struct cvmx_gmxx_txx_stat4_s cn31xx;
- struct cvmx_gmxx_txx_stat4_s cn38xx;
- struct cvmx_gmxx_txx_stat4_s cn38xxp2;
- struct cvmx_gmxx_txx_stat4_s cn50xx;
- struct cvmx_gmxx_txx_stat4_s cn52xx;
- struct cvmx_gmxx_txx_stat4_s cn52xxp1;
- struct cvmx_gmxx_txx_stat4_s cn56xx;
- struct cvmx_gmxx_txx_stat4_s cn56xxp1;
- struct cvmx_gmxx_txx_stat4_s cn58xx;
- struct cvmx_gmxx_txx_stat4_s cn58xxp1;
- struct cvmx_gmxx_txx_stat4_s cn61xx;
- struct cvmx_gmxx_txx_stat4_s cn63xx;
- struct cvmx_gmxx_txx_stat4_s cn63xxp1;
- struct cvmx_gmxx_txx_stat4_s cn66xx;
- struct cvmx_gmxx_txx_stat4_s cn68xx;
- struct cvmx_gmxx_txx_stat4_s cn68xxp1;
- struct cvmx_gmxx_txx_stat4_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat5 {
- uint64_t u64;
- struct cvmx_gmxx_txx_stat5_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t hist3:32;
- uint64_t hist2:32;
-#else
- uint64_t hist2:32;
- uint64_t hist3:32;
-#endif
- } s;
- struct cvmx_gmxx_txx_stat5_s cn30xx;
- struct cvmx_gmxx_txx_stat5_s cn31xx;
- struct cvmx_gmxx_txx_stat5_s cn38xx;
- struct cvmx_gmxx_txx_stat5_s cn38xxp2;
- struct cvmx_gmxx_txx_stat5_s cn50xx;
- struct cvmx_gmxx_txx_stat5_s cn52xx;
- struct cvmx_gmxx_txx_stat5_s cn52xxp1;
- struct cvmx_gmxx_txx_stat5_s cn56xx;
- struct cvmx_gmxx_txx_stat5_s cn56xxp1;
- struct cvmx_gmxx_txx_stat5_s cn58xx;
- struct cvmx_gmxx_txx_stat5_s cn58xxp1;
- struct cvmx_gmxx_txx_stat5_s cn61xx;
- struct cvmx_gmxx_txx_stat5_s cn63xx;
- struct cvmx_gmxx_txx_stat5_s cn63xxp1;
- struct cvmx_gmxx_txx_stat5_s cn66xx;
- struct cvmx_gmxx_txx_stat5_s cn68xx;
- struct cvmx_gmxx_txx_stat5_s cn68xxp1;
- struct cvmx_gmxx_txx_stat5_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat6 {
- uint64_t u64;
- struct cvmx_gmxx_txx_stat6_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t hist5:32;
- uint64_t hist4:32;
-#else
- uint64_t hist4:32;
- uint64_t hist5:32;
-#endif
- } s;
- struct cvmx_gmxx_txx_stat6_s cn30xx;
- struct cvmx_gmxx_txx_stat6_s cn31xx;
- struct cvmx_gmxx_txx_stat6_s cn38xx;
- struct cvmx_gmxx_txx_stat6_s cn38xxp2;
- struct cvmx_gmxx_txx_stat6_s cn50xx;
- struct cvmx_gmxx_txx_stat6_s cn52xx;
- struct cvmx_gmxx_txx_stat6_s cn52xxp1;
- struct cvmx_gmxx_txx_stat6_s cn56xx;
- struct cvmx_gmxx_txx_stat6_s cn56xxp1;
- struct cvmx_gmxx_txx_stat6_s cn58xx;
- struct cvmx_gmxx_txx_stat6_s cn58xxp1;
- struct cvmx_gmxx_txx_stat6_s cn61xx;
- struct cvmx_gmxx_txx_stat6_s cn63xx;
- struct cvmx_gmxx_txx_stat6_s cn63xxp1;
- struct cvmx_gmxx_txx_stat6_s cn66xx;
- struct cvmx_gmxx_txx_stat6_s cn68xx;
- struct cvmx_gmxx_txx_stat6_s cn68xxp1;
- struct cvmx_gmxx_txx_stat6_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat7 {
- uint64_t u64;
- struct cvmx_gmxx_txx_stat7_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t hist7:32;
- uint64_t hist6:32;
-#else
- uint64_t hist6:32;
- uint64_t hist7:32;
-#endif
- } s;
- struct cvmx_gmxx_txx_stat7_s cn30xx;
- struct cvmx_gmxx_txx_stat7_s cn31xx;
- struct cvmx_gmxx_txx_stat7_s cn38xx;
- struct cvmx_gmxx_txx_stat7_s cn38xxp2;
- struct cvmx_gmxx_txx_stat7_s cn50xx;
- struct cvmx_gmxx_txx_stat7_s cn52xx;
- struct cvmx_gmxx_txx_stat7_s cn52xxp1;
- struct cvmx_gmxx_txx_stat7_s cn56xx;
- struct cvmx_gmxx_txx_stat7_s cn56xxp1;
- struct cvmx_gmxx_txx_stat7_s cn58xx;
- struct cvmx_gmxx_txx_stat7_s cn58xxp1;
- struct cvmx_gmxx_txx_stat7_s cn61xx;
- struct cvmx_gmxx_txx_stat7_s cn63xx;
- struct cvmx_gmxx_txx_stat7_s cn63xxp1;
- struct cvmx_gmxx_txx_stat7_s cn66xx;
- struct cvmx_gmxx_txx_stat7_s cn68xx;
- struct cvmx_gmxx_txx_stat7_s cn68xxp1;
- struct cvmx_gmxx_txx_stat7_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat8 {
- uint64_t u64;
- struct cvmx_gmxx_txx_stat8_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t mcst:32;
- uint64_t bcst:32;
-#else
- uint64_t bcst:32;
- uint64_t mcst:32;
-#endif
- } s;
- struct cvmx_gmxx_txx_stat8_s cn30xx;
- struct cvmx_gmxx_txx_stat8_s cn31xx;
- struct cvmx_gmxx_txx_stat8_s cn38xx;
- struct cvmx_gmxx_txx_stat8_s cn38xxp2;
- struct cvmx_gmxx_txx_stat8_s cn50xx;
- struct cvmx_gmxx_txx_stat8_s cn52xx;
- struct cvmx_gmxx_txx_stat8_s cn52xxp1;
- struct cvmx_gmxx_txx_stat8_s cn56xx;
- struct cvmx_gmxx_txx_stat8_s cn56xxp1;
- struct cvmx_gmxx_txx_stat8_s cn58xx;
- struct cvmx_gmxx_txx_stat8_s cn58xxp1;
- struct cvmx_gmxx_txx_stat8_s cn61xx;
- struct cvmx_gmxx_txx_stat8_s cn63xx;
- struct cvmx_gmxx_txx_stat8_s cn63xxp1;
- struct cvmx_gmxx_txx_stat8_s cn66xx;
- struct cvmx_gmxx_txx_stat8_s cn68xx;
- struct cvmx_gmxx_txx_stat8_s cn68xxp1;
- struct cvmx_gmxx_txx_stat8_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stat9 {
- uint64_t u64;
- struct cvmx_gmxx_txx_stat9_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t undflw:32;
- uint64_t ctl:32;
-#else
- uint64_t ctl:32;
- uint64_t undflw:32;
-#endif
- } s;
- struct cvmx_gmxx_txx_stat9_s cn30xx;
- struct cvmx_gmxx_txx_stat9_s cn31xx;
- struct cvmx_gmxx_txx_stat9_s cn38xx;
- struct cvmx_gmxx_txx_stat9_s cn38xxp2;
- struct cvmx_gmxx_txx_stat9_s cn50xx;
- struct cvmx_gmxx_txx_stat9_s cn52xx;
- struct cvmx_gmxx_txx_stat9_s cn52xxp1;
- struct cvmx_gmxx_txx_stat9_s cn56xx;
- struct cvmx_gmxx_txx_stat9_s cn56xxp1;
- struct cvmx_gmxx_txx_stat9_s cn58xx;
- struct cvmx_gmxx_txx_stat9_s cn58xxp1;
- struct cvmx_gmxx_txx_stat9_s cn61xx;
- struct cvmx_gmxx_txx_stat9_s cn63xx;
- struct cvmx_gmxx_txx_stat9_s cn63xxp1;
- struct cvmx_gmxx_txx_stat9_s cn66xx;
- struct cvmx_gmxx_txx_stat9_s cn68xx;
- struct cvmx_gmxx_txx_stat9_s cn68xxp1;
- struct cvmx_gmxx_txx_stat9_s cnf71xx;
-};
-
-union cvmx_gmxx_txx_stats_ctl {
- uint64_t u64;
- struct cvmx_gmxx_txx_stats_ctl_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t rd_clr:1;
-#else
- uint64_t rd_clr:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_gmxx_txx_stats_ctl_s cn30xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn31xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn38xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2;
- struct cvmx_gmxx_txx_stats_ctl_s cn50xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn52xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1;
- struct cvmx_gmxx_txx_stats_ctl_s cn56xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;
- struct cvmx_gmxx_txx_stats_ctl_s cn58xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;
- struct cvmx_gmxx_txx_stats_ctl_s cn61xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn63xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn63xxp1;
- struct cvmx_gmxx_txx_stats_ctl_s cn66xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn68xx;
- struct cvmx_gmxx_txx_stats_ctl_s cn68xxp1;
- struct cvmx_gmxx_txx_stats_ctl_s cnf71xx;
};
union cvmx_gmxx_txx_thresh {
@@ -5824,7 +1643,6 @@
uint64_t reserved_7_63:57;
#endif
} cn30xx;
- struct cvmx_gmxx_txx_thresh_cn30xx cn31xx;
struct cvmx_gmxx_txx_thresh_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
@@ -5834,240 +1652,6 @@
uint64_t reserved_9_63:55;
#endif
} cn38xx;
- struct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2;
- struct cvmx_gmxx_txx_thresh_cn30xx cn50xx;
- struct cvmx_gmxx_txx_thresh_cn38xx cn52xx;
- struct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1;
- struct cvmx_gmxx_txx_thresh_cn38xx cn56xx;
- struct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1;
- struct cvmx_gmxx_txx_thresh_cn38xx cn58xx;
- struct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1;
- struct cvmx_gmxx_txx_thresh_cn38xx cn61xx;
- struct cvmx_gmxx_txx_thresh_cn38xx cn63xx;
- struct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1;
- struct cvmx_gmxx_txx_thresh_cn38xx cn66xx;
- struct cvmx_gmxx_txx_thresh_s cn68xx;
- struct cvmx_gmxx_txx_thresh_s cn68xxp1;
- struct cvmx_gmxx_txx_thresh_cn38xx cnf71xx;
-};
-
-union cvmx_gmxx_tx_bp {
- uint64_t u64;
- struct cvmx_gmxx_tx_bp_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t bp:4;
-#else
- uint64_t bp:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_gmxx_tx_bp_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_3_63:61;
- uint64_t bp:3;
-#else
- uint64_t bp:3;
- uint64_t reserved_3_63:61;
-#endif
- } cn30xx;
- struct cvmx_gmxx_tx_bp_cn30xx cn31xx;
- struct cvmx_gmxx_tx_bp_s cn38xx;
- struct cvmx_gmxx_tx_bp_s cn38xxp2;
- struct cvmx_gmxx_tx_bp_cn30xx cn50xx;
- struct cvmx_gmxx_tx_bp_s cn52xx;
- struct cvmx_gmxx_tx_bp_s cn52xxp1;
- struct cvmx_gmxx_tx_bp_s cn56xx;
- struct cvmx_gmxx_tx_bp_s cn56xxp1;
- struct cvmx_gmxx_tx_bp_s cn58xx;
- struct cvmx_gmxx_tx_bp_s cn58xxp1;
- struct cvmx_gmxx_tx_bp_s cn61xx;
- struct cvmx_gmxx_tx_bp_s cn63xx;
- struct cvmx_gmxx_tx_bp_s cn63xxp1;
- struct cvmx_gmxx_tx_bp_s cn66xx;
- struct cvmx_gmxx_tx_bp_s cn68xx;
- struct cvmx_gmxx_tx_bp_s cn68xxp1;
- struct cvmx_gmxx_tx_bp_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_2_63:62;
- uint64_t bp:2;
-#else
- uint64_t bp:2;
- uint64_t reserved_2_63:62;
-#endif
- } cnf71xx;
-};
-
-union cvmx_gmxx_tx_clk_mskx {
- uint64_t u64;
- struct cvmx_gmxx_tx_clk_mskx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t msk:1;
-#else
- uint64_t msk:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_gmxx_tx_clk_mskx_s cn30xx;
- struct cvmx_gmxx_tx_clk_mskx_s cn50xx;
-};
-
-union cvmx_gmxx_tx_col_attempt {
- uint64_t u64;
- struct cvmx_gmxx_tx_col_attempt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_5_63:59;
- uint64_t limit:5;
-#else
- uint64_t limit:5;
- uint64_t reserved_5_63:59;
-#endif
- } s;
- struct cvmx_gmxx_tx_col_attempt_s cn30xx;
- struct cvmx_gmxx_tx_col_attempt_s cn31xx;
- struct cvmx_gmxx_tx_col_attempt_s cn38xx;
- struct cvmx_gmxx_tx_col_attempt_s cn38xxp2;
- struct cvmx_gmxx_tx_col_attempt_s cn50xx;
- struct cvmx_gmxx_tx_col_attempt_s cn52xx;
- struct cvmx_gmxx_tx_col_attempt_s cn52xxp1;
- struct cvmx_gmxx_tx_col_attempt_s cn56xx;
- struct cvmx_gmxx_tx_col_attempt_s cn56xxp1;
- struct cvmx_gmxx_tx_col_attempt_s cn58xx;
- struct cvmx_gmxx_tx_col_attempt_s cn58xxp1;
- struct cvmx_gmxx_tx_col_attempt_s cn61xx;
- struct cvmx_gmxx_tx_col_attempt_s cn63xx;
- struct cvmx_gmxx_tx_col_attempt_s cn63xxp1;
- struct cvmx_gmxx_tx_col_attempt_s cn66xx;
- struct cvmx_gmxx_tx_col_attempt_s cn68xx;
- struct cvmx_gmxx_tx_col_attempt_s cn68xxp1;
- struct cvmx_gmxx_tx_col_attempt_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_corrupt {
- uint64_t u64;
- struct cvmx_gmxx_tx_corrupt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_4_63:60;
- uint64_t corrupt:4;
-#else
- uint64_t corrupt:4;
- uint64_t reserved_4_63:60;
-#endif
- } s;
- struct cvmx_gmxx_tx_corrupt_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_3_63:61;
- uint64_t corrupt:3;
-#else
- uint64_t corrupt:3;
- uint64_t reserved_3_63:61;
-#endif
- } cn30xx;
- struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx;
- struct cvmx_gmxx_tx_corrupt_s cn38xx;
- struct cvmx_gmxx_tx_corrupt_s cn38xxp2;
- struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx;
- struct cvmx_gmxx_tx_corrupt_s cn52xx;
- struct cvmx_gmxx_tx_corrupt_s cn52xxp1;
- struct cvmx_gmxx_tx_corrupt_s cn56xx;
- struct cvmx_gmxx_tx_corrupt_s cn56xxp1;
- struct cvmx_gmxx_tx_corrupt_s cn58xx;
- struct cvmx_gmxx_tx_corrupt_s cn58xxp1;
- struct cvmx_gmxx_tx_corrupt_s cn61xx;
- struct cvmx_gmxx_tx_corrupt_s cn63xx;
- struct cvmx_gmxx_tx_corrupt_s cn63xxp1;
- struct cvmx_gmxx_tx_corrupt_s cn66xx;
- struct cvmx_gmxx_tx_corrupt_s cn68xx;
- struct cvmx_gmxx_tx_corrupt_s cn68xxp1;
- struct cvmx_gmxx_tx_corrupt_cnf71xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_2_63:62;
- uint64_t corrupt:2;
-#else
- uint64_t corrupt:2;
- uint64_t reserved_2_63:62;
-#endif
- } cnf71xx;
-};
-
-union cvmx_gmxx_tx_hg2_reg1 {
- uint64_t u64;
- struct cvmx_gmxx_tx_hg2_reg1_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t tx_xof:16;
-#else
- uint64_t tx_xof:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_tx_hg2_reg1_s cn52xx;
- struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;
- struct cvmx_gmxx_tx_hg2_reg1_s cn56xx;
- struct cvmx_gmxx_tx_hg2_reg1_s cn61xx;
- struct cvmx_gmxx_tx_hg2_reg1_s cn63xx;
- struct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1;
- struct cvmx_gmxx_tx_hg2_reg1_s cn66xx;
- struct cvmx_gmxx_tx_hg2_reg1_s cn68xx;
- struct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1;
- struct cvmx_gmxx_tx_hg2_reg1_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_hg2_reg2 {
- uint64_t u64;
- struct cvmx_gmxx_tx_hg2_reg2_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t tx_xon:16;
-#else
- uint64_t tx_xon:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_tx_hg2_reg2_s cn52xx;
- struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;
- struct cvmx_gmxx_tx_hg2_reg2_s cn56xx;
- struct cvmx_gmxx_tx_hg2_reg2_s cn61xx;
- struct cvmx_gmxx_tx_hg2_reg2_s cn63xx;
- struct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1;
- struct cvmx_gmxx_tx_hg2_reg2_s cn66xx;
- struct cvmx_gmxx_tx_hg2_reg2_s cn68xx;
- struct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1;
- struct cvmx_gmxx_tx_hg2_reg2_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_ifg {
- uint64_t u64;
- struct cvmx_gmxx_tx_ifg_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_8_63:56;
- uint64_t ifg2:4;
- uint64_t ifg1:4;
-#else
- uint64_t ifg1:4;
- uint64_t ifg2:4;
- uint64_t reserved_8_63:56;
-#endif
- } s;
- struct cvmx_gmxx_tx_ifg_s cn30xx;
- struct cvmx_gmxx_tx_ifg_s cn31xx;
- struct cvmx_gmxx_tx_ifg_s cn38xx;
- struct cvmx_gmxx_tx_ifg_s cn38xxp2;
- struct cvmx_gmxx_tx_ifg_s cn50xx;
- struct cvmx_gmxx_tx_ifg_s cn52xx;
- struct cvmx_gmxx_tx_ifg_s cn52xxp1;
- struct cvmx_gmxx_tx_ifg_s cn56xx;
- struct cvmx_gmxx_tx_ifg_s cn56xxp1;
- struct cvmx_gmxx_tx_ifg_s cn58xx;
- struct cvmx_gmxx_tx_ifg_s cn58xxp1;
- struct cvmx_gmxx_tx_ifg_s cn61xx;
- struct cvmx_gmxx_tx_ifg_s cn63xx;
- struct cvmx_gmxx_tx_ifg_s cn63xxp1;
- struct cvmx_gmxx_tx_ifg_s cn66xx;
- struct cvmx_gmxx_tx_ifg_s cn68xx;
- struct cvmx_gmxx_tx_ifg_s cn68xxp1;
- struct cvmx_gmxx_tx_ifg_s cnf71xx;
};
union cvmx_gmxx_tx_int_en {
@@ -6183,7 +1767,6 @@
uint64_t reserved_16_63:48;
#endif
} cn38xxp2;
- struct cvmx_gmxx_tx_int_en_cn30xx cn50xx;
struct cvmx_gmxx_tx_int_en_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -6205,12 +1788,6 @@
uint64_t reserved_20_63:44;
#endif
} cn52xx;
- struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1;
- struct cvmx_gmxx_tx_int_en_cn52xx cn56xx;
- struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;
- struct cvmx_gmxx_tx_int_en_cn38xx cn58xx;
- struct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1;
- struct cvmx_gmxx_tx_int_en_s cn61xx;
struct cvmx_gmxx_tx_int_en_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
@@ -6234,8 +1811,6 @@
uint64_t reserved_24_63:40;
#endif
} cn63xx;
- struct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1;
- struct cvmx_gmxx_tx_int_en_s cn66xx;
struct cvmx_gmxx_tx_int_en_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63:39;
@@ -6261,7 +1836,6 @@
uint64_t reserved_25_63:39;
#endif
} cn68xx;
- struct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1;
struct cvmx_gmxx_tx_int_en_cnf71xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63:39;
@@ -6410,7 +1984,6 @@
uint64_t reserved_16_63:48;
#endif
} cn38xxp2;
- struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;
struct cvmx_gmxx_tx_int_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -6432,12 +2005,6 @@
uint64_t reserved_20_63:44;
#endif
} cn52xx;
- struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1;
- struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx;
- struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;
- struct cvmx_gmxx_tx_int_reg_cn38xx cn58xx;
- struct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1;
- struct cvmx_gmxx_tx_int_reg_s cn61xx;
struct cvmx_gmxx_tx_int_reg_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
@@ -6461,8 +2028,6 @@
uint64_t reserved_24_63:40;
#endif
} cn63xx;
- struct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1;
- struct cvmx_gmxx_tx_int_reg_s cn66xx;
struct cvmx_gmxx_tx_int_reg_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63:39;
@@ -6488,7 +2053,6 @@
uint64_t reserved_25_63:39;
#endif
} cn68xx;
- struct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1;
struct cvmx_gmxx_tx_int_reg_cnf71xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_25_63:39;
@@ -6524,68 +2088,6 @@
} cnf71xx;
};
-union cvmx_gmxx_tx_jam {
- uint64_t u64;
- struct cvmx_gmxx_tx_jam_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_8_63:56;
- uint64_t jam:8;
-#else
- uint64_t jam:8;
- uint64_t reserved_8_63:56;
-#endif
- } s;
- struct cvmx_gmxx_tx_jam_s cn30xx;
- struct cvmx_gmxx_tx_jam_s cn31xx;
- struct cvmx_gmxx_tx_jam_s cn38xx;
- struct cvmx_gmxx_tx_jam_s cn38xxp2;
- struct cvmx_gmxx_tx_jam_s cn50xx;
- struct cvmx_gmxx_tx_jam_s cn52xx;
- struct cvmx_gmxx_tx_jam_s cn52xxp1;
- struct cvmx_gmxx_tx_jam_s cn56xx;
- struct cvmx_gmxx_tx_jam_s cn56xxp1;
- struct cvmx_gmxx_tx_jam_s cn58xx;
- struct cvmx_gmxx_tx_jam_s cn58xxp1;
- struct cvmx_gmxx_tx_jam_s cn61xx;
- struct cvmx_gmxx_tx_jam_s cn63xx;
- struct cvmx_gmxx_tx_jam_s cn63xxp1;
- struct cvmx_gmxx_tx_jam_s cn66xx;
- struct cvmx_gmxx_tx_jam_s cn68xx;
- struct cvmx_gmxx_tx_jam_s cn68xxp1;
- struct cvmx_gmxx_tx_jam_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_lfsr {
- uint64_t u64;
- struct cvmx_gmxx_tx_lfsr_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t lfsr:16;
-#else
- uint64_t lfsr:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_tx_lfsr_s cn30xx;
- struct cvmx_gmxx_tx_lfsr_s cn31xx;
- struct cvmx_gmxx_tx_lfsr_s cn38xx;
- struct cvmx_gmxx_tx_lfsr_s cn38xxp2;
- struct cvmx_gmxx_tx_lfsr_s cn50xx;
- struct cvmx_gmxx_tx_lfsr_s cn52xx;
- struct cvmx_gmxx_tx_lfsr_s cn52xxp1;
- struct cvmx_gmxx_tx_lfsr_s cn56xx;
- struct cvmx_gmxx_tx_lfsr_s cn56xxp1;
- struct cvmx_gmxx_tx_lfsr_s cn58xx;
- struct cvmx_gmxx_tx_lfsr_s cn58xxp1;
- struct cvmx_gmxx_tx_lfsr_s cn61xx;
- struct cvmx_gmxx_tx_lfsr_s cn63xx;
- struct cvmx_gmxx_tx_lfsr_s cn63xxp1;
- struct cvmx_gmxx_tx_lfsr_s cn66xx;
- struct cvmx_gmxx_tx_lfsr_s cn68xx;
- struct cvmx_gmxx_tx_lfsr_s cn68xxp1;
- struct cvmx_gmxx_tx_lfsr_s cnf71xx;
-};
-
union cvmx_gmxx_tx_ovr_bp {
uint64_t u64;
struct cvmx_gmxx_tx_ovr_bp_s {
@@ -6622,7 +2124,6 @@
uint64_t reserved_11_63:53;
#endif
} cn30xx;
- struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;
struct cvmx_gmxx_tx_ovr_bp_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -6636,20 +2137,6 @@
uint64_t reserved_12_63:52;
#endif
} cn38xx;
- struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2;
- struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx;
- struct cvmx_gmxx_tx_ovr_bp_s cn52xx;
- struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1;
- struct cvmx_gmxx_tx_ovr_bp_s cn56xx;
- struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;
- struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;
- struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;
- struct cvmx_gmxx_tx_ovr_bp_s cn61xx;
- struct cvmx_gmxx_tx_ovr_bp_s cn63xx;
- struct cvmx_gmxx_tx_ovr_bp_s cn63xxp1;
- struct cvmx_gmxx_tx_ovr_bp_s cn66xx;
- struct cvmx_gmxx_tx_ovr_bp_s cn68xx;
- struct cvmx_gmxx_tx_ovr_bp_s cn68xxp1;
struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63:16;
@@ -6673,68 +2160,6 @@
} cnf71xx;
};
-union cvmx_gmxx_tx_pause_pkt_dmac {
- uint64_t u64;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_48_63:16;
- uint64_t dmac:48;
-#else
- uint64_t dmac:48;
- uint64_t reserved_48_63:16;
-#endif
- } s;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1;
- struct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx;
-};
-
-union cvmx_gmxx_tx_pause_pkt_type {
- uint64_t u64;
- struct cvmx_gmxx_tx_pause_pkt_type_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t type:16;
-#else
- uint64_t type:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn61xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn63xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn66xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn68xx;
- struct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1;
- struct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx;
-};
-
union cvmx_gmxx_tx_prts {
uint64_t u64;
struct cvmx_gmxx_tx_prts_s {
@@ -6746,24 +2171,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_gmxx_tx_prts_s cn30xx;
- struct cvmx_gmxx_tx_prts_s cn31xx;
- struct cvmx_gmxx_tx_prts_s cn38xx;
- struct cvmx_gmxx_tx_prts_s cn38xxp2;
- struct cvmx_gmxx_tx_prts_s cn50xx;
- struct cvmx_gmxx_tx_prts_s cn52xx;
- struct cvmx_gmxx_tx_prts_s cn52xxp1;
- struct cvmx_gmxx_tx_prts_s cn56xx;
- struct cvmx_gmxx_tx_prts_s cn56xxp1;
- struct cvmx_gmxx_tx_prts_s cn58xx;
- struct cvmx_gmxx_tx_prts_s cn58xxp1;
- struct cvmx_gmxx_tx_prts_s cn61xx;
- struct cvmx_gmxx_tx_prts_s cn63xx;
- struct cvmx_gmxx_tx_prts_s cn63xxp1;
- struct cvmx_gmxx_tx_prts_s cn66xx;
- struct cvmx_gmxx_tx_prts_s cn68xx;
- struct cvmx_gmxx_tx_prts_s cn68xxp1;
- struct cvmx_gmxx_tx_prts_s cnf71xx;
};
union cvmx_gmxx_tx_spi_ctl {
@@ -6779,26 +2186,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_gmxx_tx_spi_ctl_s cn38xx;
- struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2;
- struct cvmx_gmxx_tx_spi_ctl_s cn58xx;
- struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1;
-};
-
-union cvmx_gmxx_tx_spi_drain {
- uint64_t u64;
- struct cvmx_gmxx_tx_spi_drain_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t drain:16;
-#else
- uint64_t drain:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_tx_spi_drain_s cn38xx;
- struct cvmx_gmxx_tx_spi_drain_s cn58xx;
- struct cvmx_gmxx_tx_spi_drain_s cn58xxp1;
};
union cvmx_gmxx_tx_spi_max {
@@ -6827,24 +2214,6 @@
uint64_t reserved_16_63:48;
#endif
} cn38xx;
- struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2;
- struct cvmx_gmxx_tx_spi_max_s cn58xx;
- struct cvmx_gmxx_tx_spi_max_s cn58xxp1;
-};
-
-union cvmx_gmxx_tx_spi_roundx {
- uint64_t u64;
- struct cvmx_gmxx_tx_spi_roundx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_16_63:48;
- uint64_t round:16;
-#else
- uint64_t round:16;
- uint64_t reserved_16_63:48;
-#endif
- } s;
- struct cvmx_gmxx_tx_spi_roundx_s cn58xx;
- struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1;
};
union cvmx_gmxx_tx_spi_thresh {
@@ -6858,10 +2227,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_gmxx_tx_spi_thresh_s cn38xx;
- struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2;
- struct cvmx_gmxx_tx_spi_thresh_s cn58xx;
- struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1;
};
union cvmx_gmxx_tx_xaui_ctl {
@@ -6889,43 +2254,6 @@
uint64_t reserved_11_63:53;
#endif
} s;
- struct cvmx_gmxx_tx_xaui_ctl_s cn52xx;
- struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;
- struct cvmx_gmxx_tx_xaui_ctl_s cn56xx;
- struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;
- struct cvmx_gmxx_tx_xaui_ctl_s cn61xx;
- struct cvmx_gmxx_tx_xaui_ctl_s cn63xx;
- struct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1;
- struct cvmx_gmxx_tx_xaui_ctl_s cn66xx;
- struct cvmx_gmxx_tx_xaui_ctl_s cn68xx;
- struct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1;
- struct cvmx_gmxx_tx_xaui_ctl_s cnf71xx;
-};
-
-union cvmx_gmxx_xaui_ext_loopback {
- uint64_t u64;
- struct cvmx_gmxx_xaui_ext_loopback_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_5_63:59;
- uint64_t en:1;
- uint64_t thresh:4;
-#else
- uint64_t thresh:4;
- uint64_t en:1;
- uint64_t reserved_5_63:59;
-#endif
- } s;
- struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
- struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
- struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
- struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
- struct cvmx_gmxx_xaui_ext_loopback_s cn61xx;
- struct cvmx_gmxx_xaui_ext_loopback_s cn63xx;
- struct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1;
- struct cvmx_gmxx_xaui_ext_loopback_s cn66xx;
- struct cvmx_gmxx_xaui_ext_loopback_s cn68xx;
- struct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1;
- struct cvmx_gmxx_xaui_ext_loopback_s cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
index 8123b82..5420fa6 100644
--- a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
@@ -90,10 +90,6 @@
uint64_t reserved_12_63:52;
#endif
} cn30xx;
- struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
- struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
- struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
- struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
struct cvmx_gpio_bit_cfgx_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_15_63:49;
@@ -117,20 +113,6 @@
uint64_t reserved_15_63:49;
#endif
} cn52xx;
- struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
- struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
- struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
- struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
- struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
- struct cvmx_gpio_bit_cfgx_s cn61xx;
- struct cvmx_gpio_bit_cfgx_s cn63xx;
- struct cvmx_gpio_bit_cfgx_s cn63xxp1;
- struct cvmx_gpio_bit_cfgx_s cn66xx;
- struct cvmx_gpio_bit_cfgx_s cn68xx;
- struct cvmx_gpio_bit_cfgx_s cn68xxp1;
- struct cvmx_gpio_bit_cfgx_s cn70xx;
- struct cvmx_gpio_bit_cfgx_s cn73xx;
- struct cvmx_gpio_bit_cfgx_s cnf71xx;
};
union cvmx_gpio_boot_ena {
@@ -146,9 +128,6 @@
uint64_t reserved_12_63:52;
#endif
} s;
- struct cvmx_gpio_boot_ena_s cn30xx;
- struct cvmx_gpio_boot_ena_s cn31xx;
- struct cvmx_gpio_boot_ena_s cn50xx;
};
union cvmx_gpio_clk_genx {
@@ -162,17 +141,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_gpio_clk_genx_s cn52xx;
- struct cvmx_gpio_clk_genx_s cn52xxp1;
- struct cvmx_gpio_clk_genx_s cn56xx;
- struct cvmx_gpio_clk_genx_s cn56xxp1;
- struct cvmx_gpio_clk_genx_s cn61xx;
- struct cvmx_gpio_clk_genx_s cn63xx;
- struct cvmx_gpio_clk_genx_s cn63xxp1;
- struct cvmx_gpio_clk_genx_s cn66xx;
- struct cvmx_gpio_clk_genx_s cn68xx;
- struct cvmx_gpio_clk_genx_s cn68xxp1;
- struct cvmx_gpio_clk_genx_s cnf71xx;
};
union cvmx_gpio_clk_qlmx {
@@ -218,11 +186,6 @@
uint64_t reserved_3_63:61;
#endif
} cn63xx;
- struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1;
- struct cvmx_gpio_clk_qlmx_cn61xx cn66xx;
- struct cvmx_gpio_clk_qlmx_s cn68xx;
- struct cvmx_gpio_clk_qlmx_s cn68xxp1;
- struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx;
};
union cvmx_gpio_dbg_ena {
@@ -236,9 +199,6 @@
uint64_t reserved_21_63:43;
#endif
} s;
- struct cvmx_gpio_dbg_ena_s cn30xx;
- struct cvmx_gpio_dbg_ena_s cn31xx;
- struct cvmx_gpio_dbg_ena_s cn50xx;
};
union cvmx_gpio_int_clr {
@@ -252,24 +212,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_gpio_int_clr_s cn30xx;
- struct cvmx_gpio_int_clr_s cn31xx;
- struct cvmx_gpio_int_clr_s cn38xx;
- struct cvmx_gpio_int_clr_s cn38xxp2;
- struct cvmx_gpio_int_clr_s cn50xx;
- struct cvmx_gpio_int_clr_s cn52xx;
- struct cvmx_gpio_int_clr_s cn52xxp1;
- struct cvmx_gpio_int_clr_s cn56xx;
- struct cvmx_gpio_int_clr_s cn56xxp1;
- struct cvmx_gpio_int_clr_s cn58xx;
- struct cvmx_gpio_int_clr_s cn58xxp1;
- struct cvmx_gpio_int_clr_s cn61xx;
- struct cvmx_gpio_int_clr_s cn63xx;
- struct cvmx_gpio_int_clr_s cn63xxp1;
- struct cvmx_gpio_int_clr_s cn66xx;
- struct cvmx_gpio_int_clr_s cn68xx;
- struct cvmx_gpio_int_clr_s cn68xxp1;
- struct cvmx_gpio_int_clr_s cnf71xx;
};
union cvmx_gpio_multi_cast {
@@ -283,8 +225,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_gpio_multi_cast_s cn61xx;
- struct cvmx_gpio_multi_cast_s cnf71xx;
};
union cvmx_gpio_pin_ena {
@@ -302,7 +242,6 @@
uint64_t reserved_20_63:44;
#endif
} s;
- struct cvmx_gpio_pin_ena_s cn66xx;
};
union cvmx_gpio_rx_dat {
@@ -316,8 +255,6 @@
uint64_t reserved_24_63:40;
#endif
} s;
- struct cvmx_gpio_rx_dat_s cn30xx;
- struct cvmx_gpio_rx_dat_s cn31xx;
struct cvmx_gpio_rx_dat_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
@@ -327,14 +264,6 @@
uint64_t reserved_16_63:48;
#endif
} cn38xx;
- struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
- struct cvmx_gpio_rx_dat_s cn50xx;
- struct cvmx_gpio_rx_dat_cn38xx cn52xx;
- struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
- struct cvmx_gpio_rx_dat_cn38xx cn56xx;
- struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
- struct cvmx_gpio_rx_dat_cn38xx cn58xx;
- struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
struct cvmx_gpio_rx_dat_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -344,12 +273,6 @@
uint64_t reserved_20_63:44;
#endif
} cn61xx;
- struct cvmx_gpio_rx_dat_cn38xx cn63xx;
- struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
- struct cvmx_gpio_rx_dat_cn61xx cn66xx;
- struct cvmx_gpio_rx_dat_cn38xx cn68xx;
- struct cvmx_gpio_rx_dat_cn38xx cn68xxp1;
- struct cvmx_gpio_rx_dat_cn61xx cnf71xx;
};
union cvmx_gpio_tim_ctl {
@@ -363,8 +286,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_gpio_tim_ctl_s cn68xx;
- struct cvmx_gpio_tim_ctl_s cn68xxp1;
};
union cvmx_gpio_tx_clr {
@@ -378,8 +299,6 @@
uint64_t reserved_24_63:40;
#endif
} s;
- struct cvmx_gpio_tx_clr_s cn30xx;
- struct cvmx_gpio_tx_clr_s cn31xx;
struct cvmx_gpio_tx_clr_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
@@ -389,14 +308,6 @@
uint64_t reserved_16_63:48;
#endif
} cn38xx;
- struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
- struct cvmx_gpio_tx_clr_s cn50xx;
- struct cvmx_gpio_tx_clr_cn38xx cn52xx;
- struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
- struct cvmx_gpio_tx_clr_cn38xx cn56xx;
- struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
- struct cvmx_gpio_tx_clr_cn38xx cn58xx;
- struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
struct cvmx_gpio_tx_clr_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -406,12 +317,6 @@
uint64_t reserved_20_63:44;
#endif
} cn61xx;
- struct cvmx_gpio_tx_clr_cn38xx cn63xx;
- struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
- struct cvmx_gpio_tx_clr_cn61xx cn66xx;
- struct cvmx_gpio_tx_clr_cn38xx cn68xx;
- struct cvmx_gpio_tx_clr_cn38xx cn68xxp1;
- struct cvmx_gpio_tx_clr_cn61xx cnf71xx;
};
union cvmx_gpio_tx_set {
@@ -425,8 +330,6 @@
uint64_t reserved_24_63:40;
#endif
} s;
- struct cvmx_gpio_tx_set_s cn30xx;
- struct cvmx_gpio_tx_set_s cn31xx;
struct cvmx_gpio_tx_set_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
@@ -436,14 +339,6 @@
uint64_t reserved_16_63:48;
#endif
} cn38xx;
- struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
- struct cvmx_gpio_tx_set_s cn50xx;
- struct cvmx_gpio_tx_set_cn38xx cn52xx;
- struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
- struct cvmx_gpio_tx_set_cn38xx cn56xx;
- struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
- struct cvmx_gpio_tx_set_cn38xx cn58xx;
- struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
struct cvmx_gpio_tx_set_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -453,12 +348,6 @@
uint64_t reserved_20_63:44;
#endif
} cn61xx;
- struct cvmx_gpio_tx_set_cn38xx cn63xx;
- struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
- struct cvmx_gpio_tx_set_cn61xx cn66xx;
- struct cvmx_gpio_tx_set_cn38xx cn68xx;
- struct cvmx_gpio_tx_set_cn38xx cn68xxp1;
- struct cvmx_gpio_tx_set_cn61xx cnf71xx;
};
union cvmx_gpio_xbit_cfgx {
@@ -505,11 +394,6 @@
uint64_t reserved_12_63:52;
#endif
} cn30xx;
- struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx;
- struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx;
- struct cvmx_gpio_xbit_cfgx_s cn61xx;
- struct cvmx_gpio_xbit_cfgx_s cn66xx;
- struct cvmx_gpio_xbit_cfgx_s cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
index b4d19c2..d7fdcf0 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-board.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -119,18 +119,6 @@
extern int __cvmx_helper_board_interface_probe(int interface,
int supported_ports);
-/**
- * Enable packet input/output from the hardware. This function is
- * called after by cvmx_helper_packet_hardware_enable() to
- * perform board specific initialization. For most boards
- * nothing is needed.
- *
- * @interface: Interface to enable
- *
- * Returns Zero on success, negative on failure
- */
-extern int __cvmx_helper_board_hardware_enable(int interface);
-
enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void);
#endif /* __CVMX_HELPER_BOARD_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
index f7a95d7..ac42b50 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
@@ -90,21 +90,4 @@
extern int __cvmx_helper_rgmii_link_set(int ipd_port,
cvmx_helper_link_info_t link_info);
-/**
- * Configure a port for internal and/or external loopback. Internal loopback
- * causes packets sent by the port to be received by Octeon. External loopback
- * causes packets received from the wire to sent out again.
- *
- * @ipd_port: IPD/PKO port to loopback.
- * @enable_internal:
- * Non zero if you want internal loopback
- * @enable_external:
- * Non zero if you want external loopback
- *
- * Returns Zero on success, negative on failure.
- */
-extern int __cvmx_helper_rgmii_configure_loopback(int ipd_port,
- int enable_internal,
- int enable_external);
-
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
index 63fd213..3a54dea 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
@@ -84,21 +84,4 @@
extern int __cvmx_helper_sgmii_link_set(int ipd_port,
cvmx_helper_link_info_t link_info);
-/**
- * Configure a port for internal and/or external loopback. Internal loopback
- * causes packets sent by the port to be received by Octeon. External loopback
- * causes packets received from the wire to sent out again.
- *
- * @ipd_port: IPD/PKO port to loopback.
- * @enable_internal:
- * Non zero if you want internal loopback
- * @enable_external:
- * Non zero if you want external loopback
- *
- * Returns Zero on success, negative on failure.
- */
-extern int __cvmx_helper_sgmii_configure_loopback(int ipd_port,
- int enable_internal,
- int enable_external);
-
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h
index f446f21..e9a97e7 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-util.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
@@ -45,29 +45,6 @@
*cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);
/**
- * Debug routine to dump the packet structure to the console
- *
- * @work: Work queue entry containing the packet to dump
- * Returns
- */
-extern int cvmx_helper_dump_packet(cvmx_wqe_t *work);
-
-/**
- * Setup Random Early Drop on a specific input queue
- *
- * @queue: Input queue to setup RED on (0-7)
- * @pass_thresh:
- * Packets will begin slowly dropping when there are less than
- * this many packet buffers free in FPA 0.
- * @drop_thresh:
- * All incoming packets will be dropped when there are less
- * than this many free packet buffers in FPA 0.
- * Returns Zero on success. Negative on failure
- */
-extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
- int drop_thresh);
-
-/**
* Setup Random Early Drop to automatically begin dropping packets.
*
* @pass_thresh:
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
index f8ce53f..51f45b4 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
@@ -84,20 +84,4 @@
extern int __cvmx_helper_xaui_link_set(int ipd_port,
cvmx_helper_link_info_t link_info);
-/**
- * Configure a port for internal and/or external loopback. Internal loopback
- * causes packets sent by the port to be received by Octeon. External loopback
- * causes packets received from the wire to sent out again.
- *
- * @ipd_port: IPD/PKO port to loopback.
- * @enable_internal:
- * Non zero if you want internal loopback
- * @enable_external:
- * Non zero if you want external loopback
- *
- * Returns Zero on success, negative on failure.
- */
-extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
- int enable_internal,
- int enable_external);
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
index 0ed87cb..ba0e76f 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper.h
@@ -71,26 +71,6 @@
#include <asm/octeon/cvmx-helper-xaui.h>
/**
- * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
- * priorities[16]) is a function pointer. It is meant to allow
- * customization of the PKO queue priorities based on the port
- * number. Users should set this pointer to a function before
- * calling any cvmx-helper operations.
- */
-extern void (*cvmx_override_pko_queue_priority) (int pko_port,
- uint64_t priorities[16]);
-
-/**
- * cvmx_override_ipd_port_setup(int ipd_port) is a function
- * pointer. It is meant to allow customization of the IPD port
- * setup before packet input/output comes online. It is called
- * after cvmx-helper does the default IPD configuration, but
- * before IPD is enabled. Users should set this pointer to a
- * function before calling any cvmx-helper operations.
- */
-extern void (*cvmx_override_ipd_port_setup) (int ipd_port);
-
-/**
* This function enables the IPD and also enables the packet interfaces.
* The packet interfaces (RGMII and SPI) must be enabled after the
* IPD. This should be called by the user program after any additional
@@ -195,20 +175,4 @@
extern int cvmx_helper_interface_probe(int interface);
extern int cvmx_helper_interface_enumerate(int interface);
-/**
- * Configure a port for internal and/or external loopback. Internal loopback
- * causes packets sent by the port to be received by Octeon. External loopback
- * causes packets received from the wire to sent out again.
- *
- * @ipd_port: IPD/PKO port to loopback.
- * @enable_internal:
- * Non zero if you want internal loopback
- * @enable_external:
- * Non zero if you want external loopback
- *
- * Returns Zero on success, negative on failure.
- */
-extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal,
- int enable_external);
-
#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
index 7936f81..989b67b 100644
--- a/arch/mips/include/asm/octeon/cvmx-iob-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
@@ -119,16 +119,6 @@
uint64_t reserved_18_63:46;
#endif
} cn30xx;
- struct cvmx_iob_bist_status_cn30xx cn31xx;
- struct cvmx_iob_bist_status_cn30xx cn38xx;
- struct cvmx_iob_bist_status_cn30xx cn38xxp2;
- struct cvmx_iob_bist_status_cn30xx cn50xx;
- struct cvmx_iob_bist_status_cn30xx cn52xx;
- struct cvmx_iob_bist_status_cn30xx cn52xxp1;
- struct cvmx_iob_bist_status_cn30xx cn56xx;
- struct cvmx_iob_bist_status_cn30xx cn56xxp1;
- struct cvmx_iob_bist_status_cn30xx cn58xx;
- struct cvmx_iob_bist_status_cn30xx cn58xxp1;
struct cvmx_iob_bist_status_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_23_63:41;
@@ -182,9 +172,6 @@
uint64_t reserved_23_63:41;
#endif
} cn61xx;
- struct cvmx_iob_bist_status_cn61xx cn63xx;
- struct cvmx_iob_bist_status_cn61xx cn63xxp1;
- struct cvmx_iob_bist_status_cn61xx cn66xx;
struct cvmx_iob_bist_status_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63:46;
@@ -228,8 +215,6 @@
uint64_t reserved_18_63:46;
#endif
} cn68xx;
- struct cvmx_iob_bist_status_cn68xx cn68xxp1;
- struct cvmx_iob_bist_status_cn61xx cnf71xx;
};
union cvmx_iob_ctl_status {
@@ -274,10 +259,6 @@
uint64_t reserved_5_63:59;
#endif
} cn30xx;
- struct cvmx_iob_ctl_status_cn30xx cn31xx;
- struct cvmx_iob_ctl_status_cn30xx cn38xx;
- struct cvmx_iob_ctl_status_cn30xx cn38xxp2;
- struct cvmx_iob_ctl_status_cn30xx cn50xx;
struct cvmx_iob_ctl_status_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
@@ -297,11 +278,6 @@
uint64_t reserved_6_63:58;
#endif
} cn52xx;
- struct cvmx_iob_ctl_status_cn30xx cn52xxp1;
- struct cvmx_iob_ctl_status_cn30xx cn56xx;
- struct cvmx_iob_ctl_status_cn30xx cn56xxp1;
- struct cvmx_iob_ctl_status_cn30xx cn58xx;
- struct cvmx_iob_ctl_status_cn30xx cn58xxp1;
struct cvmx_iob_ctl_status_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
@@ -346,8 +322,6 @@
uint64_t reserved_10_63:54;
#endif
} cn63xx;
- struct cvmx_iob_ctl_status_cn63xx cn63xxp1;
- struct cvmx_iob_ctl_status_cn61xx cn66xx;
struct cvmx_iob_ctl_status_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
@@ -371,8 +345,6 @@
uint64_t reserved_11_63:53;
#endif
} cn68xx;
- struct cvmx_iob_ctl_status_cn68xx cn68xxp1;
- struct cvmx_iob_ctl_status_cn61xx cnf71xx;
};
union cvmx_iob_dwb_pri_cnt {
@@ -388,19 +360,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_iob_dwb_pri_cnt_s cn38xx;
- struct cvmx_iob_dwb_pri_cnt_s cn38xxp2;
- struct cvmx_iob_dwb_pri_cnt_s cn52xx;
- struct cvmx_iob_dwb_pri_cnt_s cn52xxp1;
- struct cvmx_iob_dwb_pri_cnt_s cn56xx;
- struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
- struct cvmx_iob_dwb_pri_cnt_s cn58xx;
- struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
- struct cvmx_iob_dwb_pri_cnt_s cn61xx;
- struct cvmx_iob_dwb_pri_cnt_s cn63xx;
- struct cvmx_iob_dwb_pri_cnt_s cn63xxp1;
- struct cvmx_iob_dwb_pri_cnt_s cn66xx;
- struct cvmx_iob_dwb_pri_cnt_s cnf71xx;
};
union cvmx_iob_fau_timeout {
@@ -416,24 +375,6 @@
uint64_t reserved_13_63:51;
#endif
} s;
- struct cvmx_iob_fau_timeout_s cn30xx;
- struct cvmx_iob_fau_timeout_s cn31xx;
- struct cvmx_iob_fau_timeout_s cn38xx;
- struct cvmx_iob_fau_timeout_s cn38xxp2;
- struct cvmx_iob_fau_timeout_s cn50xx;
- struct cvmx_iob_fau_timeout_s cn52xx;
- struct cvmx_iob_fau_timeout_s cn52xxp1;
- struct cvmx_iob_fau_timeout_s cn56xx;
- struct cvmx_iob_fau_timeout_s cn56xxp1;
- struct cvmx_iob_fau_timeout_s cn58xx;
- struct cvmx_iob_fau_timeout_s cn58xxp1;
- struct cvmx_iob_fau_timeout_s cn61xx;
- struct cvmx_iob_fau_timeout_s cn63xx;
- struct cvmx_iob_fau_timeout_s cn63xxp1;
- struct cvmx_iob_fau_timeout_s cn66xx;
- struct cvmx_iob_fau_timeout_s cn68xx;
- struct cvmx_iob_fau_timeout_s cn68xxp1;
- struct cvmx_iob_fau_timeout_s cnf71xx;
};
union cvmx_iob_i2c_pri_cnt {
@@ -449,19 +390,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_iob_i2c_pri_cnt_s cn38xx;
- struct cvmx_iob_i2c_pri_cnt_s cn38xxp2;
- struct cvmx_iob_i2c_pri_cnt_s cn52xx;
- struct cvmx_iob_i2c_pri_cnt_s cn52xxp1;
- struct cvmx_iob_i2c_pri_cnt_s cn56xx;
- struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
- struct cvmx_iob_i2c_pri_cnt_s cn58xx;
- struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
- struct cvmx_iob_i2c_pri_cnt_s cn61xx;
- struct cvmx_iob_i2c_pri_cnt_s cn63xx;
- struct cvmx_iob_i2c_pri_cnt_s cn63xxp1;
- struct cvmx_iob_i2c_pri_cnt_s cn66xx;
- struct cvmx_iob_i2c_pri_cnt_s cnf71xx;
};
union cvmx_iob_inb_control_match {
@@ -481,24 +409,6 @@
uint64_t reserved_29_63:35;
#endif
} s;
- struct cvmx_iob_inb_control_match_s cn30xx;
- struct cvmx_iob_inb_control_match_s cn31xx;
- struct cvmx_iob_inb_control_match_s cn38xx;
- struct cvmx_iob_inb_control_match_s cn38xxp2;
- struct cvmx_iob_inb_control_match_s cn50xx;
- struct cvmx_iob_inb_control_match_s cn52xx;
- struct cvmx_iob_inb_control_match_s cn52xxp1;
- struct cvmx_iob_inb_control_match_s cn56xx;
- struct cvmx_iob_inb_control_match_s cn56xxp1;
- struct cvmx_iob_inb_control_match_s cn58xx;
- struct cvmx_iob_inb_control_match_s cn58xxp1;
- struct cvmx_iob_inb_control_match_s cn61xx;
- struct cvmx_iob_inb_control_match_s cn63xx;
- struct cvmx_iob_inb_control_match_s cn63xxp1;
- struct cvmx_iob_inb_control_match_s cn66xx;
- struct cvmx_iob_inb_control_match_s cn68xx;
- struct cvmx_iob_inb_control_match_s cn68xxp1;
- struct cvmx_iob_inb_control_match_s cnf71xx;
};
union cvmx_iob_inb_control_match_enb {
@@ -518,24 +428,6 @@
uint64_t reserved_29_63:35;
#endif
} s;
- struct cvmx_iob_inb_control_match_enb_s cn30xx;
- struct cvmx_iob_inb_control_match_enb_s cn31xx;
- struct cvmx_iob_inb_control_match_enb_s cn38xx;
- struct cvmx_iob_inb_control_match_enb_s cn38xxp2;
- struct cvmx_iob_inb_control_match_enb_s cn50xx;
- struct cvmx_iob_inb_control_match_enb_s cn52xx;
- struct cvmx_iob_inb_control_match_enb_s cn52xxp1;
- struct cvmx_iob_inb_control_match_enb_s cn56xx;
- struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
- struct cvmx_iob_inb_control_match_enb_s cn58xx;
- struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
- struct cvmx_iob_inb_control_match_enb_s cn61xx;
- struct cvmx_iob_inb_control_match_enb_s cn63xx;
- struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
- struct cvmx_iob_inb_control_match_enb_s cn66xx;
- struct cvmx_iob_inb_control_match_enb_s cn68xx;
- struct cvmx_iob_inb_control_match_enb_s cn68xxp1;
- struct cvmx_iob_inb_control_match_enb_s cnf71xx;
};
union cvmx_iob_inb_data_match {
@@ -547,24 +439,6 @@
uint64_t data:64;
#endif
} s;
- struct cvmx_iob_inb_data_match_s cn30xx;
- struct cvmx_iob_inb_data_match_s cn31xx;
- struct cvmx_iob_inb_data_match_s cn38xx;
- struct cvmx_iob_inb_data_match_s cn38xxp2;
- struct cvmx_iob_inb_data_match_s cn50xx;
- struct cvmx_iob_inb_data_match_s cn52xx;
- struct cvmx_iob_inb_data_match_s cn52xxp1;
- struct cvmx_iob_inb_data_match_s cn56xx;
- struct cvmx_iob_inb_data_match_s cn56xxp1;
- struct cvmx_iob_inb_data_match_s cn58xx;
- struct cvmx_iob_inb_data_match_s cn58xxp1;
- struct cvmx_iob_inb_data_match_s cn61xx;
- struct cvmx_iob_inb_data_match_s cn63xx;
- struct cvmx_iob_inb_data_match_s cn63xxp1;
- struct cvmx_iob_inb_data_match_s cn66xx;
- struct cvmx_iob_inb_data_match_s cn68xx;
- struct cvmx_iob_inb_data_match_s cn68xxp1;
- struct cvmx_iob_inb_data_match_s cnf71xx;
};
union cvmx_iob_inb_data_match_enb {
@@ -576,24 +450,6 @@
uint64_t data:64;
#endif
} s;
- struct cvmx_iob_inb_data_match_enb_s cn30xx;
- struct cvmx_iob_inb_data_match_enb_s cn31xx;
- struct cvmx_iob_inb_data_match_enb_s cn38xx;
- struct cvmx_iob_inb_data_match_enb_s cn38xxp2;
- struct cvmx_iob_inb_data_match_enb_s cn50xx;
- struct cvmx_iob_inb_data_match_enb_s cn52xx;
- struct cvmx_iob_inb_data_match_enb_s cn52xxp1;
- struct cvmx_iob_inb_data_match_enb_s cn56xx;
- struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
- struct cvmx_iob_inb_data_match_enb_s cn58xx;
- struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
- struct cvmx_iob_inb_data_match_enb_s cn61xx;
- struct cvmx_iob_inb_data_match_enb_s cn63xx;
- struct cvmx_iob_inb_data_match_enb_s cn63xxp1;
- struct cvmx_iob_inb_data_match_enb_s cn66xx;
- struct cvmx_iob_inb_data_match_enb_s cn68xx;
- struct cvmx_iob_inb_data_match_enb_s cn68xxp1;
- struct cvmx_iob_inb_data_match_enb_s cnf71xx;
};
union cvmx_iob_int_enb {
@@ -632,20 +488,6 @@
uint64_t reserved_4_63:60;
#endif
} cn30xx;
- struct cvmx_iob_int_enb_cn30xx cn31xx;
- struct cvmx_iob_int_enb_cn30xx cn38xx;
- struct cvmx_iob_int_enb_cn30xx cn38xxp2;
- struct cvmx_iob_int_enb_s cn50xx;
- struct cvmx_iob_int_enb_s cn52xx;
- struct cvmx_iob_int_enb_s cn52xxp1;
- struct cvmx_iob_int_enb_s cn56xx;
- struct cvmx_iob_int_enb_s cn56xxp1;
- struct cvmx_iob_int_enb_s cn58xx;
- struct cvmx_iob_int_enb_s cn58xxp1;
- struct cvmx_iob_int_enb_s cn61xx;
- struct cvmx_iob_int_enb_s cn63xx;
- struct cvmx_iob_int_enb_s cn63xxp1;
- struct cvmx_iob_int_enb_s cn66xx;
struct cvmx_iob_int_enb_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_0_63:64;
@@ -653,8 +495,6 @@
uint64_t reserved_0_63:64;
#endif
} cn68xx;
- struct cvmx_iob_int_enb_cn68xx cn68xxp1;
- struct cvmx_iob_int_enb_s cnf71xx;
};
union cvmx_iob_int_sum {
@@ -693,20 +533,6 @@
uint64_t reserved_4_63:60;
#endif
} cn30xx;
- struct cvmx_iob_int_sum_cn30xx cn31xx;
- struct cvmx_iob_int_sum_cn30xx cn38xx;
- struct cvmx_iob_int_sum_cn30xx cn38xxp2;
- struct cvmx_iob_int_sum_s cn50xx;
- struct cvmx_iob_int_sum_s cn52xx;
- struct cvmx_iob_int_sum_s cn52xxp1;
- struct cvmx_iob_int_sum_s cn56xx;
- struct cvmx_iob_int_sum_s cn56xxp1;
- struct cvmx_iob_int_sum_s cn58xx;
- struct cvmx_iob_int_sum_s cn58xxp1;
- struct cvmx_iob_int_sum_s cn61xx;
- struct cvmx_iob_int_sum_s cn63xx;
- struct cvmx_iob_int_sum_s cn63xxp1;
- struct cvmx_iob_int_sum_s cn66xx;
struct cvmx_iob_int_sum_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_0_63:64;
@@ -714,8 +540,6 @@
uint64_t reserved_0_63:64;
#endif
} cn68xx;
- struct cvmx_iob_int_sum_cn68xx cn68xxp1;
- struct cvmx_iob_int_sum_s cnf71xx;
};
union cvmx_iob_n2c_l2c_pri_cnt {
@@ -731,19 +555,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xx;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xxp1;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xx;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn61xx;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cn66xx;
- struct cvmx_iob_n2c_l2c_pri_cnt_s cnf71xx;
};
union cvmx_iob_n2c_rsp_pri_cnt {
@@ -759,19 +570,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xx;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xxp1;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xx;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn61xx;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cn66xx;
- struct cvmx_iob_n2c_rsp_pri_cnt_s cnf71xx;
};
union cvmx_iob_outb_com_pri_cnt {
@@ -787,21 +585,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_iob_outb_com_pri_cnt_s cn38xx;
- struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2;
- struct cvmx_iob_outb_com_pri_cnt_s cn52xx;
- struct cvmx_iob_outb_com_pri_cnt_s cn52xxp1;
- struct cvmx_iob_outb_com_pri_cnt_s cn56xx;
- struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
- struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
- struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
- struct cvmx_iob_outb_com_pri_cnt_s cn61xx;
- struct cvmx_iob_outb_com_pri_cnt_s cn63xx;
- struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1;
- struct cvmx_iob_outb_com_pri_cnt_s cn66xx;
- struct cvmx_iob_outb_com_pri_cnt_s cn68xx;
- struct cvmx_iob_outb_com_pri_cnt_s cn68xxp1;
- struct cvmx_iob_outb_com_pri_cnt_s cnf71xx;
};
union cvmx_iob_outb_control_match {
@@ -821,24 +604,6 @@
uint64_t reserved_26_63:38;
#endif
} s;
- struct cvmx_iob_outb_control_match_s cn30xx;
- struct cvmx_iob_outb_control_match_s cn31xx;
- struct cvmx_iob_outb_control_match_s cn38xx;
- struct cvmx_iob_outb_control_match_s cn38xxp2;
- struct cvmx_iob_outb_control_match_s cn50xx;
- struct cvmx_iob_outb_control_match_s cn52xx;
- struct cvmx_iob_outb_control_match_s cn52xxp1;
- struct cvmx_iob_outb_control_match_s cn56xx;
- struct cvmx_iob_outb_control_match_s cn56xxp1;
- struct cvmx_iob_outb_control_match_s cn58xx;
- struct cvmx_iob_outb_control_match_s cn58xxp1;
- struct cvmx_iob_outb_control_match_s cn61xx;
- struct cvmx_iob_outb_control_match_s cn63xx;
- struct cvmx_iob_outb_control_match_s cn63xxp1;
- struct cvmx_iob_outb_control_match_s cn66xx;
- struct cvmx_iob_outb_control_match_s cn68xx;
- struct cvmx_iob_outb_control_match_s cn68xxp1;
- struct cvmx_iob_outb_control_match_s cnf71xx;
};
union cvmx_iob_outb_control_match_enb {
@@ -858,24 +623,6 @@
uint64_t reserved_26_63:38;
#endif
} s;
- struct cvmx_iob_outb_control_match_enb_s cn30xx;
- struct cvmx_iob_outb_control_match_enb_s cn31xx;
- struct cvmx_iob_outb_control_match_enb_s cn38xx;
- struct cvmx_iob_outb_control_match_enb_s cn38xxp2;
- struct cvmx_iob_outb_control_match_enb_s cn50xx;
- struct cvmx_iob_outb_control_match_enb_s cn52xx;
- struct cvmx_iob_outb_control_match_enb_s cn52xxp1;
- struct cvmx_iob_outb_control_match_enb_s cn56xx;
- struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
- struct cvmx_iob_outb_control_match_enb_s cn58xx;
- struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
- struct cvmx_iob_outb_control_match_enb_s cn61xx;
- struct cvmx_iob_outb_control_match_enb_s cn63xx;
- struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
- struct cvmx_iob_outb_control_match_enb_s cn66xx;
- struct cvmx_iob_outb_control_match_enb_s cn68xx;
- struct cvmx_iob_outb_control_match_enb_s cn68xxp1;
- struct cvmx_iob_outb_control_match_enb_s cnf71xx;
};
union cvmx_iob_outb_data_match {
@@ -887,24 +634,6 @@
uint64_t data:64;
#endif
} s;
- struct cvmx_iob_outb_data_match_s cn30xx;
- struct cvmx_iob_outb_data_match_s cn31xx;
- struct cvmx_iob_outb_data_match_s cn38xx;
- struct cvmx_iob_outb_data_match_s cn38xxp2;
- struct cvmx_iob_outb_data_match_s cn50xx;
- struct cvmx_iob_outb_data_match_s cn52xx;
- struct cvmx_iob_outb_data_match_s cn52xxp1;
- struct cvmx_iob_outb_data_match_s cn56xx;
- struct cvmx_iob_outb_data_match_s cn56xxp1;
- struct cvmx_iob_outb_data_match_s cn58xx;
- struct cvmx_iob_outb_data_match_s cn58xxp1;
- struct cvmx_iob_outb_data_match_s cn61xx;
- struct cvmx_iob_outb_data_match_s cn63xx;
- struct cvmx_iob_outb_data_match_s cn63xxp1;
- struct cvmx_iob_outb_data_match_s cn66xx;
- struct cvmx_iob_outb_data_match_s cn68xx;
- struct cvmx_iob_outb_data_match_s cn68xxp1;
- struct cvmx_iob_outb_data_match_s cnf71xx;
};
union cvmx_iob_outb_data_match_enb {
@@ -916,24 +645,6 @@
uint64_t data:64;
#endif
} s;
- struct cvmx_iob_outb_data_match_enb_s cn30xx;
- struct cvmx_iob_outb_data_match_enb_s cn31xx;
- struct cvmx_iob_outb_data_match_enb_s cn38xx;
- struct cvmx_iob_outb_data_match_enb_s cn38xxp2;
- struct cvmx_iob_outb_data_match_enb_s cn50xx;
- struct cvmx_iob_outb_data_match_enb_s cn52xx;
- struct cvmx_iob_outb_data_match_enb_s cn52xxp1;
- struct cvmx_iob_outb_data_match_enb_s cn56xx;
- struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
- struct cvmx_iob_outb_data_match_enb_s cn58xx;
- struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
- struct cvmx_iob_outb_data_match_enb_s cn61xx;
- struct cvmx_iob_outb_data_match_enb_s cn63xx;
- struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
- struct cvmx_iob_outb_data_match_enb_s cn66xx;
- struct cvmx_iob_outb_data_match_enb_s cn68xx;
- struct cvmx_iob_outb_data_match_enb_s cn68xxp1;
- struct cvmx_iob_outb_data_match_enb_s cnf71xx;
};
union cvmx_iob_outb_fpa_pri_cnt {
@@ -949,21 +660,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn52xx;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn52xxp1;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn56xx;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn61xx;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn66xx;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn68xx;
- struct cvmx_iob_outb_fpa_pri_cnt_s cn68xxp1;
- struct cvmx_iob_outb_fpa_pri_cnt_s cnf71xx;
};
union cvmx_iob_outb_req_pri_cnt {
@@ -979,21 +675,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_iob_outb_req_pri_cnt_s cn38xx;
- struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2;
- struct cvmx_iob_outb_req_pri_cnt_s cn52xx;
- struct cvmx_iob_outb_req_pri_cnt_s cn52xxp1;
- struct cvmx_iob_outb_req_pri_cnt_s cn56xx;
- struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
- struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
- struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
- struct cvmx_iob_outb_req_pri_cnt_s cn61xx;
- struct cvmx_iob_outb_req_pri_cnt_s cn63xx;
- struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1;
- struct cvmx_iob_outb_req_pri_cnt_s cn66xx;
- struct cvmx_iob_outb_req_pri_cnt_s cn68xx;
- struct cvmx_iob_outb_req_pri_cnt_s cn68xxp1;
- struct cvmx_iob_outb_req_pri_cnt_s cnf71xx;
};
union cvmx_iob_p2c_req_pri_cnt {
@@ -1009,19 +690,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_iob_p2c_req_pri_cnt_s cn38xx;
- struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2;
- struct cvmx_iob_p2c_req_pri_cnt_s cn52xx;
- struct cvmx_iob_p2c_req_pri_cnt_s cn52xxp1;
- struct cvmx_iob_p2c_req_pri_cnt_s cn56xx;
- struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
- struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
- struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
- struct cvmx_iob_p2c_req_pri_cnt_s cn61xx;
- struct cvmx_iob_p2c_req_pri_cnt_s cn63xx;
- struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1;
- struct cvmx_iob_p2c_req_pri_cnt_s cn66xx;
- struct cvmx_iob_p2c_req_pri_cnt_s cnf71xx;
};
union cvmx_iob_pkt_err {
@@ -1046,21 +714,6 @@
uint64_t reserved_6_63:58;
#endif
} cn30xx;
- struct cvmx_iob_pkt_err_cn30xx cn31xx;
- struct cvmx_iob_pkt_err_cn30xx cn38xx;
- struct cvmx_iob_pkt_err_cn30xx cn38xxp2;
- struct cvmx_iob_pkt_err_cn30xx cn50xx;
- struct cvmx_iob_pkt_err_cn30xx cn52xx;
- struct cvmx_iob_pkt_err_cn30xx cn52xxp1;
- struct cvmx_iob_pkt_err_cn30xx cn56xx;
- struct cvmx_iob_pkt_err_cn30xx cn56xxp1;
- struct cvmx_iob_pkt_err_cn30xx cn58xx;
- struct cvmx_iob_pkt_err_cn30xx cn58xxp1;
- struct cvmx_iob_pkt_err_s cn61xx;
- struct cvmx_iob_pkt_err_s cn63xx;
- struct cvmx_iob_pkt_err_s cn63xxp1;
- struct cvmx_iob_pkt_err_s cn66xx;
- struct cvmx_iob_pkt_err_s cnf71xx;
};
union cvmx_iob_to_cmb_credits {
@@ -1089,10 +742,6 @@
uint64_t reserved_9_63:55;
#endif
} cn52xx;
- struct cvmx_iob_to_cmb_credits_cn52xx cn61xx;
- struct cvmx_iob_to_cmb_credits_cn52xx cn63xx;
- struct cvmx_iob_to_cmb_credits_cn52xx cn63xxp1;
- struct cvmx_iob_to_cmb_credits_cn52xx cn66xx;
struct cvmx_iob_to_cmb_credits_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
@@ -1106,8 +755,6 @@
uint64_t reserved_9_63:55;
#endif
} cn68xx;
- struct cvmx_iob_to_cmb_credits_cn68xx cn68xxp1;
- struct cvmx_iob_to_cmb_credits_cn52xx cnf71xx;
};
union cvmx_iob_to_ncb_did_00_credits {
@@ -1121,8 +768,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_00_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_00_credits_s cn68xxp1;
};
union cvmx_iob_to_ncb_did_111_credits {
@@ -1136,8 +781,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_111_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_111_credits_s cn68xxp1;
};
union cvmx_iob_to_ncb_did_223_credits {
@@ -1151,8 +794,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_223_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_223_credits_s cn68xxp1;
};
union cvmx_iob_to_ncb_did_24_credits {
@@ -1166,8 +807,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_24_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_24_credits_s cn68xxp1;
};
union cvmx_iob_to_ncb_did_32_credits {
@@ -1181,8 +820,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_32_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_32_credits_s cn68xxp1;
};
union cvmx_iob_to_ncb_did_40_credits {
@@ -1196,8 +833,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_40_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_40_credits_s cn68xxp1;
};
union cvmx_iob_to_ncb_did_55_credits {
@@ -1211,8 +846,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_55_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_55_credits_s cn68xxp1;
};
union cvmx_iob_to_ncb_did_64_credits {
@@ -1226,8 +859,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_64_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_64_credits_s cn68xxp1;
};
union cvmx_iob_to_ncb_did_79_credits {
@@ -1241,8 +872,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_79_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_79_credits_s cn68xxp1;
};
union cvmx_iob_to_ncb_did_96_credits {
@@ -1256,8 +885,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_96_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_96_credits_s cn68xxp1;
};
union cvmx_iob_to_ncb_did_98_credits {
@@ -1271,8 +898,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_iob_to_ncb_did_98_credits_s cn68xx;
- struct cvmx_iob_to_ncb_did_98_credits_s cn68xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
index 1193f73..c0a4ac7 100644
--- a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
@@ -108,24 +108,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_ipd_1st_mbuff_skip_s cn30xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn31xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn38xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn38xxp2;
- struct cvmx_ipd_1st_mbuff_skip_s cn50xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn52xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn52xxp1;
- struct cvmx_ipd_1st_mbuff_skip_s cn56xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
- struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
- struct cvmx_ipd_1st_mbuff_skip_s cn61xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn63xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1;
- struct cvmx_ipd_1st_mbuff_skip_s cn66xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn68xx;
- struct cvmx_ipd_1st_mbuff_skip_s cn68xxp1;
- struct cvmx_ipd_1st_mbuff_skip_s cnf71xx;
};
union cvmx_ipd_1st_next_ptr_back {
@@ -139,24 +121,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_ipd_1st_next_ptr_back_s cn30xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn31xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn38xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn38xxp2;
- struct cvmx_ipd_1st_next_ptr_back_s cn50xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn52xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn52xxp1;
- struct cvmx_ipd_1st_next_ptr_back_s cn56xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
- struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
- struct cvmx_ipd_1st_next_ptr_back_s cn61xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn63xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1;
- struct cvmx_ipd_1st_next_ptr_back_s cn66xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn68xx;
- struct cvmx_ipd_1st_next_ptr_back_s cn68xxp1;
- struct cvmx_ipd_1st_next_ptr_back_s cnf71xx;
};
union cvmx_ipd_2nd_next_ptr_back {
@@ -170,24 +134,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_ipd_2nd_next_ptr_back_s cn30xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn31xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn38xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2;
- struct cvmx_ipd_2nd_next_ptr_back_s cn50xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn52xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1;
- struct cvmx_ipd_2nd_next_ptr_back_s cn56xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
- struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
- struct cvmx_ipd_2nd_next_ptr_back_s cn61xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn63xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1;
- struct cvmx_ipd_2nd_next_ptr_back_s cn66xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn68xx;
- struct cvmx_ipd_2nd_next_ptr_back_s cn68xxp1;
- struct cvmx_ipd_2nd_next_ptr_back_s cnf71xx;
};
union cvmx_ipd_bist_status {
@@ -284,10 +230,6 @@
uint64_t reserved_16_63:48;
#endif
} cn30xx;
- struct cvmx_ipd_bist_status_cn30xx cn31xx;
- struct cvmx_ipd_bist_status_cn30xx cn38xx;
- struct cvmx_ipd_bist_status_cn30xx cn38xxp2;
- struct cvmx_ipd_bist_status_cn30xx cn50xx;
struct cvmx_ipd_bist_status_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_18_63:46;
@@ -331,18 +273,6 @@
uint64_t reserved_18_63:46;
#endif
} cn52xx;
- struct cvmx_ipd_bist_status_cn52xx cn52xxp1;
- struct cvmx_ipd_bist_status_cn52xx cn56xx;
- struct cvmx_ipd_bist_status_cn52xx cn56xxp1;
- struct cvmx_ipd_bist_status_cn30xx cn58xx;
- struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
- struct cvmx_ipd_bist_status_cn52xx cn61xx;
- struct cvmx_ipd_bist_status_cn52xx cn63xx;
- struct cvmx_ipd_bist_status_cn52xx cn63xxp1;
- struct cvmx_ipd_bist_status_cn52xx cn66xx;
- struct cvmx_ipd_bist_status_s cn68xx;
- struct cvmx_ipd_bist_status_s cn68xxp1;
- struct cvmx_ipd_bist_status_cn52xx cnf71xx;
};
union cvmx_ipd_bp_prt_red_end {
@@ -365,10 +295,6 @@
uint64_t reserved_36_63:28;
#endif
} cn30xx;
- struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx;
- struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
- struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
- struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
struct cvmx_ipd_bp_prt_red_end_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_40_63:24;
@@ -378,12 +304,6 @@
uint64_t reserved_40_63:24;
#endif
} cn52xx;
- struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1;
- struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx;
- struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1;
- struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
- struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
- struct cvmx_ipd_bp_prt_red_end_s cn61xx;
struct cvmx_ipd_bp_prt_red_end_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_44_63:20;
@@ -393,9 +313,6 @@
uint64_t reserved_44_63:20;
#endif
} cn63xx;
- struct cvmx_ipd_bp_prt_red_end_cn63xx cn63xxp1;
- struct cvmx_ipd_bp_prt_red_end_s cn66xx;
- struct cvmx_ipd_bp_prt_red_end_s cnf71xx;
};
union cvmx_ipd_bpidx_mbuf_th {
@@ -411,8 +328,6 @@
uint64_t reserved_18_63:46;
#endif
} s;
- struct cvmx_ipd_bpidx_mbuf_th_s cn68xx;
- struct cvmx_ipd_bpidx_mbuf_th_s cn68xxp1;
};
union cvmx_ipd_bpid_bp_counterx {
@@ -426,8 +341,6 @@
uint64_t reserved_25_63:39;
#endif
} s;
- struct cvmx_ipd_bpid_bp_counterx_s cn68xx;
- struct cvmx_ipd_bpid_bp_counterx_s cn68xxp1;
};
union cvmx_ipd_clk_count {
@@ -439,24 +352,6 @@
uint64_t clk_cnt:64;
#endif
} s;
- struct cvmx_ipd_clk_count_s cn30xx;
- struct cvmx_ipd_clk_count_s cn31xx;
- struct cvmx_ipd_clk_count_s cn38xx;
- struct cvmx_ipd_clk_count_s cn38xxp2;
- struct cvmx_ipd_clk_count_s cn50xx;
- struct cvmx_ipd_clk_count_s cn52xx;
- struct cvmx_ipd_clk_count_s cn52xxp1;
- struct cvmx_ipd_clk_count_s cn56xx;
- struct cvmx_ipd_clk_count_s cn56xxp1;
- struct cvmx_ipd_clk_count_s cn58xx;
- struct cvmx_ipd_clk_count_s cn58xxp1;
- struct cvmx_ipd_clk_count_s cn61xx;
- struct cvmx_ipd_clk_count_s cn63xx;
- struct cvmx_ipd_clk_count_s cn63xxp1;
- struct cvmx_ipd_clk_count_s cn66xx;
- struct cvmx_ipd_clk_count_s cn68xx;
- struct cvmx_ipd_clk_count_s cn68xxp1;
- struct cvmx_ipd_clk_count_s cnf71xx;
};
union cvmx_ipd_credits {
@@ -472,8 +367,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_ipd_credits_s cn68xx;
- struct cvmx_ipd_credits_s cn68xxp1;
};
union cvmx_ipd_ctl_status {
@@ -544,8 +437,6 @@
uint64_t reserved_10_63:54;
#endif
} cn30xx;
- struct cvmx_ipd_ctl_status_cn30xx cn31xx;
- struct cvmx_ipd_ctl_status_cn30xx cn38xx;
struct cvmx_ipd_ctl_status_cn38xxp2 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
@@ -604,10 +495,6 @@
uint64_t reserved_15_63:49;
#endif
} cn50xx;
- struct cvmx_ipd_ctl_status_cn50xx cn52xx;
- struct cvmx_ipd_ctl_status_cn50xx cn52xxp1;
- struct cvmx_ipd_ctl_status_cn50xx cn56xx;
- struct cvmx_ipd_ctl_status_cn50xx cn56xxp1;
struct cvmx_ipd_ctl_status_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -637,9 +524,6 @@
uint64_t reserved_12_63:52;
#endif
} cn58xx;
- struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
- struct cvmx_ipd_ctl_status_s cn61xx;
- struct cvmx_ipd_ctl_status_s cn63xx;
struct cvmx_ipd_ctl_status_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_16_63:48;
@@ -677,10 +561,6 @@
uint64_t reserved_16_63:48;
#endif
} cn63xxp1;
- struct cvmx_ipd_ctl_status_s cn66xx;
- struct cvmx_ipd_ctl_status_s cn68xx;
- struct cvmx_ipd_ctl_status_s cn68xxp1;
- struct cvmx_ipd_ctl_status_s cnf71xx;
};
union cvmx_ipd_ecc_ctl {
@@ -700,8 +580,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_ipd_ecc_ctl_s cn68xx;
- struct cvmx_ipd_ecc_ctl_s cn68xxp1;
};
union cvmx_ipd_free_ptr_fifo_ctl {
@@ -723,8 +601,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xx;
- struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xxp1;
};
union cvmx_ipd_free_ptr_value {
@@ -738,8 +614,6 @@
uint64_t reserved_33_63:31;
#endif
} s;
- struct cvmx_ipd_free_ptr_value_s cn68xx;
- struct cvmx_ipd_free_ptr_value_s cn68xxp1;
};
union cvmx_ipd_hold_ptr_fifo_ctl {
@@ -761,8 +635,6 @@
uint64_t reserved_43_63:21;
#endif
} s;
- struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xx;
- struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xxp1;
};
union cvmx_ipd_int_enb {
@@ -837,7 +709,6 @@
uint64_t reserved_5_63:59;
#endif
} cn30xx;
- struct cvmx_ipd_int_enb_cn30xx cn31xx;
struct cvmx_ipd_int_enb_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
@@ -865,8 +736,6 @@
uint64_t reserved_10_63:54;
#endif
} cn38xx;
- struct cvmx_ipd_int_enb_cn30xx cn38xxp2;
- struct cvmx_ipd_int_enb_cn38xx cn50xx;
struct cvmx_ipd_int_enb_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -898,18 +767,6 @@
uint64_t reserved_12_63:52;
#endif
} cn52xx;
- struct cvmx_ipd_int_enb_cn52xx cn52xxp1;
- struct cvmx_ipd_int_enb_cn52xx cn56xx;
- struct cvmx_ipd_int_enb_cn52xx cn56xxp1;
- struct cvmx_ipd_int_enb_cn38xx cn58xx;
- struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
- struct cvmx_ipd_int_enb_cn52xx cn61xx;
- struct cvmx_ipd_int_enb_cn52xx cn63xx;
- struct cvmx_ipd_int_enb_cn52xx cn63xxp1;
- struct cvmx_ipd_int_enb_cn52xx cn66xx;
- struct cvmx_ipd_int_enb_s cn68xx;
- struct cvmx_ipd_int_enb_s cn68xxp1;
- struct cvmx_ipd_int_enb_cn52xx cnf71xx;
};
union cvmx_ipd_int_sum {
@@ -984,7 +841,6 @@
uint64_t reserved_5_63:59;
#endif
} cn30xx;
- struct cvmx_ipd_int_sum_cn30xx cn31xx;
struct cvmx_ipd_int_sum_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
@@ -1012,8 +868,6 @@
uint64_t reserved_10_63:54;
#endif
} cn38xx;
- struct cvmx_ipd_int_sum_cn30xx cn38xxp2;
- struct cvmx_ipd_int_sum_cn38xx cn50xx;
struct cvmx_ipd_int_sum_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -1045,18 +899,6 @@
uint64_t reserved_12_63:52;
#endif
} cn52xx;
- struct cvmx_ipd_int_sum_cn52xx cn52xxp1;
- struct cvmx_ipd_int_sum_cn52xx cn56xx;
- struct cvmx_ipd_int_sum_cn52xx cn56xxp1;
- struct cvmx_ipd_int_sum_cn38xx cn58xx;
- struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
- struct cvmx_ipd_int_sum_cn52xx cn61xx;
- struct cvmx_ipd_int_sum_cn52xx cn63xx;
- struct cvmx_ipd_int_sum_cn52xx cn63xxp1;
- struct cvmx_ipd_int_sum_cn52xx cn66xx;
- struct cvmx_ipd_int_sum_s cn68xx;
- struct cvmx_ipd_int_sum_s cn68xxp1;
- struct cvmx_ipd_int_sum_cn52xx cnf71xx;
};
union cvmx_ipd_next_pkt_ptr {
@@ -1070,8 +912,6 @@
uint64_t reserved_33_63:31;
#endif
} s;
- struct cvmx_ipd_next_pkt_ptr_s cn68xx;
- struct cvmx_ipd_next_pkt_ptr_s cn68xxp1;
};
union cvmx_ipd_next_wqe_ptr {
@@ -1085,8 +925,6 @@
uint64_t reserved_33_63:31;
#endif
} s;
- struct cvmx_ipd_next_wqe_ptr_s cn68xx;
- struct cvmx_ipd_next_wqe_ptr_s cn68xxp1;
};
union cvmx_ipd_not_1st_mbuff_skip {
@@ -1100,24 +938,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn61xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn66xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn68xx;
- struct cvmx_ipd_not_1st_mbuff_skip_s cn68xxp1;
- struct cvmx_ipd_not_1st_mbuff_skip_s cnf71xx;
};
union cvmx_ipd_on_bp_drop_pktx {
@@ -1129,8 +949,6 @@
uint64_t prt_enb:64;
#endif
} s;
- struct cvmx_ipd_on_bp_drop_pktx_s cn68xx;
- struct cvmx_ipd_on_bp_drop_pktx_s cn68xxp1;
};
union cvmx_ipd_packet_mbuff_size {
@@ -1144,24 +962,6 @@
uint64_t reserved_12_63:52;
#endif
} s;
- struct cvmx_ipd_packet_mbuff_size_s cn30xx;
- struct cvmx_ipd_packet_mbuff_size_s cn31xx;
- struct cvmx_ipd_packet_mbuff_size_s cn38xx;
- struct cvmx_ipd_packet_mbuff_size_s cn38xxp2;
- struct cvmx_ipd_packet_mbuff_size_s cn50xx;
- struct cvmx_ipd_packet_mbuff_size_s cn52xx;
- struct cvmx_ipd_packet_mbuff_size_s cn52xxp1;
- struct cvmx_ipd_packet_mbuff_size_s cn56xx;
- struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
- struct cvmx_ipd_packet_mbuff_size_s cn58xx;
- struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
- struct cvmx_ipd_packet_mbuff_size_s cn61xx;
- struct cvmx_ipd_packet_mbuff_size_s cn63xx;
- struct cvmx_ipd_packet_mbuff_size_s cn63xxp1;
- struct cvmx_ipd_packet_mbuff_size_s cn66xx;
- struct cvmx_ipd_packet_mbuff_size_s cn68xx;
- struct cvmx_ipd_packet_mbuff_size_s cn68xxp1;
- struct cvmx_ipd_packet_mbuff_size_s cnf71xx;
};
union cvmx_ipd_pkt_err {
@@ -1175,8 +975,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_ipd_pkt_err_s cn68xx;
- struct cvmx_ipd_pkt_err_s cn68xxp1;
};
union cvmx_ipd_pkt_ptr_valid {
@@ -1190,21 +988,6 @@
uint64_t reserved_29_63:35;
#endif
} s;
- struct cvmx_ipd_pkt_ptr_valid_s cn30xx;
- struct cvmx_ipd_pkt_ptr_valid_s cn31xx;
- struct cvmx_ipd_pkt_ptr_valid_s cn38xx;
- struct cvmx_ipd_pkt_ptr_valid_s cn50xx;
- struct cvmx_ipd_pkt_ptr_valid_s cn52xx;
- struct cvmx_ipd_pkt_ptr_valid_s cn52xxp1;
- struct cvmx_ipd_pkt_ptr_valid_s cn56xx;
- struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
- struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
- struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
- struct cvmx_ipd_pkt_ptr_valid_s cn61xx;
- struct cvmx_ipd_pkt_ptr_valid_s cn63xx;
- struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1;
- struct cvmx_ipd_pkt_ptr_valid_s cn66xx;
- struct cvmx_ipd_pkt_ptr_valid_s cnf71xx;
};
union cvmx_ipd_portx_bp_page_cnt {
@@ -1220,22 +1003,6 @@
uint64_t reserved_18_63:46;
#endif
} s;
- struct cvmx_ipd_portx_bp_page_cnt_s cn30xx;
- struct cvmx_ipd_portx_bp_page_cnt_s cn31xx;
- struct cvmx_ipd_portx_bp_page_cnt_s cn38xx;
- struct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2;
- struct cvmx_ipd_portx_bp_page_cnt_s cn50xx;
- struct cvmx_ipd_portx_bp_page_cnt_s cn52xx;
- struct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1;
- struct cvmx_ipd_portx_bp_page_cnt_s cn56xx;
- struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
- struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
- struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
- struct cvmx_ipd_portx_bp_page_cnt_s cn61xx;
- struct cvmx_ipd_portx_bp_page_cnt_s cn63xx;
- struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1;
- struct cvmx_ipd_portx_bp_page_cnt_s cn66xx;
- struct cvmx_ipd_portx_bp_page_cnt_s cnf71xx;
};
union cvmx_ipd_portx_bp_page_cnt2 {
@@ -1251,15 +1018,6 @@
uint64_t reserved_18_63:46;
#endif
} s;
- struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx;
- struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
- struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
- struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
- struct cvmx_ipd_portx_bp_page_cnt2_s cn61xx;
- struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx;
- struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1;
- struct cvmx_ipd_portx_bp_page_cnt2_s cn66xx;
- struct cvmx_ipd_portx_bp_page_cnt2_s cnf71xx;
};
union cvmx_ipd_portx_bp_page_cnt3 {
@@ -1275,11 +1033,6 @@
uint64_t reserved_18_63:46;
#endif
} s;
- struct cvmx_ipd_portx_bp_page_cnt3_s cn61xx;
- struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx;
- struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1;
- struct cvmx_ipd_portx_bp_page_cnt3_s cn66xx;
- struct cvmx_ipd_portx_bp_page_cnt3_s cnf71xx;
};
union cvmx_ipd_port_bp_counters2_pairx {
@@ -1293,15 +1046,6 @@
uint64_t reserved_25_63:39;
#endif
} s;
- struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx;
- struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
- struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
- struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
- struct cvmx_ipd_port_bp_counters2_pairx_s cn61xx;
- struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx;
- struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1;
- struct cvmx_ipd_port_bp_counters2_pairx_s cn66xx;
- struct cvmx_ipd_port_bp_counters2_pairx_s cnf71xx;
};
union cvmx_ipd_port_bp_counters3_pairx {
@@ -1315,11 +1059,6 @@
uint64_t reserved_25_63:39;
#endif
} s;
- struct cvmx_ipd_port_bp_counters3_pairx_s cn61xx;
- struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx;
- struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1;
- struct cvmx_ipd_port_bp_counters3_pairx_s cn66xx;
- struct cvmx_ipd_port_bp_counters3_pairx_s cnf71xx;
};
union cvmx_ipd_port_bp_counters4_pairx {
@@ -1333,9 +1072,6 @@
uint64_t reserved_25_63:39;
#endif
} s;
- struct cvmx_ipd_port_bp_counters4_pairx_s cn61xx;
- struct cvmx_ipd_port_bp_counters4_pairx_s cn66xx;
- struct cvmx_ipd_port_bp_counters4_pairx_s cnf71xx;
};
union cvmx_ipd_port_bp_counters_pairx {
@@ -1349,22 +1085,6 @@
uint64_t reserved_25_63:39;
#endif
} s;
- struct cvmx_ipd_port_bp_counters_pairx_s cn30xx;
- struct cvmx_ipd_port_bp_counters_pairx_s cn31xx;
- struct cvmx_ipd_port_bp_counters_pairx_s cn38xx;
- struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2;
- struct cvmx_ipd_port_bp_counters_pairx_s cn50xx;
- struct cvmx_ipd_port_bp_counters_pairx_s cn52xx;
- struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1;
- struct cvmx_ipd_port_bp_counters_pairx_s cn56xx;
- struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
- struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
- struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
- struct cvmx_ipd_port_bp_counters_pairx_s cn61xx;
- struct cvmx_ipd_port_bp_counters_pairx_s cn63xx;
- struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1;
- struct cvmx_ipd_port_bp_counters_pairx_s cn66xx;
- struct cvmx_ipd_port_bp_counters_pairx_s cnf71xx;
};
union cvmx_ipd_port_ptr_fifo_ctl {
@@ -1384,8 +1104,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xx;
- struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xxp1;
};
union cvmx_ipd_port_qos_x_cnt {
@@ -1399,17 +1117,6 @@
uint64_t wmark:32;
#endif
} s;
- struct cvmx_ipd_port_qos_x_cnt_s cn52xx;
- struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
- struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
- struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
- struct cvmx_ipd_port_qos_x_cnt_s cn61xx;
- struct cvmx_ipd_port_qos_x_cnt_s cn63xx;
- struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1;
- struct cvmx_ipd_port_qos_x_cnt_s cn66xx;
- struct cvmx_ipd_port_qos_x_cnt_s cn68xx;
- struct cvmx_ipd_port_qos_x_cnt_s cn68xxp1;
- struct cvmx_ipd_port_qos_x_cnt_s cnf71xx;
};
union cvmx_ipd_port_qos_intx {
@@ -1421,17 +1128,6 @@
uint64_t intr:64;
#endif
} s;
- struct cvmx_ipd_port_qos_intx_s cn52xx;
- struct cvmx_ipd_port_qos_intx_s cn52xxp1;
- struct cvmx_ipd_port_qos_intx_s cn56xx;
- struct cvmx_ipd_port_qos_intx_s cn56xxp1;
- struct cvmx_ipd_port_qos_intx_s cn61xx;
- struct cvmx_ipd_port_qos_intx_s cn63xx;
- struct cvmx_ipd_port_qos_intx_s cn63xxp1;
- struct cvmx_ipd_port_qos_intx_s cn66xx;
- struct cvmx_ipd_port_qos_intx_s cn68xx;
- struct cvmx_ipd_port_qos_intx_s cn68xxp1;
- struct cvmx_ipd_port_qos_intx_s cnf71xx;
};
union cvmx_ipd_port_qos_int_enbx {
@@ -1443,17 +1139,6 @@
uint64_t enb:64;
#endif
} s;
- struct cvmx_ipd_port_qos_int_enbx_s cn52xx;
- struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
- struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
- struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
- struct cvmx_ipd_port_qos_int_enbx_s cn61xx;
- struct cvmx_ipd_port_qos_int_enbx_s cn63xx;
- struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1;
- struct cvmx_ipd_port_qos_int_enbx_s cn66xx;
- struct cvmx_ipd_port_qos_int_enbx_s cn68xx;
- struct cvmx_ipd_port_qos_int_enbx_s cn68xxp1;
- struct cvmx_ipd_port_qos_int_enbx_s cnf71xx;
};
union cvmx_ipd_port_sopx {
@@ -1465,8 +1150,6 @@
uint64_t sop:64;
#endif
} s;
- struct cvmx_ipd_port_sopx_s cn68xx;
- struct cvmx_ipd_port_sopx_s cn68xxp1;
};
union cvmx_ipd_prc_hold_ptr_fifo_ctl {
@@ -1488,21 +1171,6 @@
uint64_t reserved_39_63:25;
#endif
} s;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn61xx;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn66xx;
- struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cnf71xx;
};
union cvmx_ipd_prc_port_ptr_fifo_ctl {
@@ -1522,21 +1190,6 @@
uint64_t reserved_44_63:20;
#endif
} s;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn61xx;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn66xx;
- struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cnf71xx;
};
union cvmx_ipd_ptr_count {
@@ -1558,24 +1211,6 @@
uint64_t reserved_19_63:45;
#endif
} s;
- struct cvmx_ipd_ptr_count_s cn30xx;
- struct cvmx_ipd_ptr_count_s cn31xx;
- struct cvmx_ipd_ptr_count_s cn38xx;
- struct cvmx_ipd_ptr_count_s cn38xxp2;
- struct cvmx_ipd_ptr_count_s cn50xx;
- struct cvmx_ipd_ptr_count_s cn52xx;
- struct cvmx_ipd_ptr_count_s cn52xxp1;
- struct cvmx_ipd_ptr_count_s cn56xx;
- struct cvmx_ipd_ptr_count_s cn56xxp1;
- struct cvmx_ipd_ptr_count_s cn58xx;
- struct cvmx_ipd_ptr_count_s cn58xxp1;
- struct cvmx_ipd_ptr_count_s cn61xx;
- struct cvmx_ipd_ptr_count_s cn63xx;
- struct cvmx_ipd_ptr_count_s cn63xxp1;
- struct cvmx_ipd_ptr_count_s cn66xx;
- struct cvmx_ipd_ptr_count_s cn68xx;
- struct cvmx_ipd_ptr_count_s cn68xxp1;
- struct cvmx_ipd_ptr_count_s cnf71xx;
};
union cvmx_ipd_pwp_ptr_fifo_ctl {
@@ -1599,21 +1234,6 @@
uint64_t reserved_61_63:3;
#endif
} s;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn61xx;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn66xx;
- struct cvmx_ipd_pwp_ptr_fifo_ctl_s cnf71xx;
};
union cvmx_ipd_qosx_red_marks {
@@ -1627,24 +1247,6 @@
uint64_t drop:32;
#endif
} s;
- struct cvmx_ipd_qosx_red_marks_s cn30xx;
- struct cvmx_ipd_qosx_red_marks_s cn31xx;
- struct cvmx_ipd_qosx_red_marks_s cn38xx;
- struct cvmx_ipd_qosx_red_marks_s cn38xxp2;
- struct cvmx_ipd_qosx_red_marks_s cn50xx;
- struct cvmx_ipd_qosx_red_marks_s cn52xx;
- struct cvmx_ipd_qosx_red_marks_s cn52xxp1;
- struct cvmx_ipd_qosx_red_marks_s cn56xx;
- struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
- struct cvmx_ipd_qosx_red_marks_s cn58xx;
- struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
- struct cvmx_ipd_qosx_red_marks_s cn61xx;
- struct cvmx_ipd_qosx_red_marks_s cn63xx;
- struct cvmx_ipd_qosx_red_marks_s cn63xxp1;
- struct cvmx_ipd_qosx_red_marks_s cn66xx;
- struct cvmx_ipd_qosx_red_marks_s cn68xx;
- struct cvmx_ipd_qosx_red_marks_s cn68xxp1;
- struct cvmx_ipd_qosx_red_marks_s cnf71xx;
};
union cvmx_ipd_que0_free_page_cnt {
@@ -1658,24 +1260,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_ipd_que0_free_page_cnt_s cn30xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn31xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn38xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2;
- struct cvmx_ipd_que0_free_page_cnt_s cn50xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn52xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1;
- struct cvmx_ipd_que0_free_page_cnt_s cn56xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
- struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
- struct cvmx_ipd_que0_free_page_cnt_s cn61xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn63xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1;
- struct cvmx_ipd_que0_free_page_cnt_s cn66xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn68xx;
- struct cvmx_ipd_que0_free_page_cnt_s cn68xxp1;
- struct cvmx_ipd_que0_free_page_cnt_s cnf71xx;
};
union cvmx_ipd_red_bpid_enablex {
@@ -1687,8 +1271,6 @@
uint64_t prt_enb:64;
#endif
} s;
- struct cvmx_ipd_red_bpid_enablex_s cn68xx;
- struct cvmx_ipd_red_bpid_enablex_s cn68xxp1;
};
union cvmx_ipd_red_delay {
@@ -1704,8 +1286,6 @@
uint64_t reserved_28_63:36;
#endif
} s;
- struct cvmx_ipd_red_delay_s cn68xx;
- struct cvmx_ipd_red_delay_s cn68xxp1;
};
union cvmx_ipd_red_port_enable {
@@ -1721,22 +1301,6 @@
uint64_t prb_dly:14;
#endif
} s;
- struct cvmx_ipd_red_port_enable_s cn30xx;
- struct cvmx_ipd_red_port_enable_s cn31xx;
- struct cvmx_ipd_red_port_enable_s cn38xx;
- struct cvmx_ipd_red_port_enable_s cn38xxp2;
- struct cvmx_ipd_red_port_enable_s cn50xx;
- struct cvmx_ipd_red_port_enable_s cn52xx;
- struct cvmx_ipd_red_port_enable_s cn52xxp1;
- struct cvmx_ipd_red_port_enable_s cn56xx;
- struct cvmx_ipd_red_port_enable_s cn56xxp1;
- struct cvmx_ipd_red_port_enable_s cn58xx;
- struct cvmx_ipd_red_port_enable_s cn58xxp1;
- struct cvmx_ipd_red_port_enable_s cn61xx;
- struct cvmx_ipd_red_port_enable_s cn63xx;
- struct cvmx_ipd_red_port_enable_s cn63xxp1;
- struct cvmx_ipd_red_port_enable_s cn66xx;
- struct cvmx_ipd_red_port_enable_s cnf71xx;
};
union cvmx_ipd_red_port_enable2 {
@@ -1759,10 +1323,6 @@
uint64_t reserved_4_63:60;
#endif
} cn52xx;
- struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1;
- struct cvmx_ipd_red_port_enable2_cn52xx cn56xx;
- struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1;
- struct cvmx_ipd_red_port_enable2_s cn61xx;
struct cvmx_ipd_red_port_enable2_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
@@ -1772,9 +1332,6 @@
uint64_t reserved_8_63:56;
#endif
} cn63xx;
- struct cvmx_ipd_red_port_enable2_cn63xx cn63xxp1;
- struct cvmx_ipd_red_port_enable2_s cn66xx;
- struct cvmx_ipd_red_port_enable2_s cnf71xx;
};
union cvmx_ipd_red_quex_param {
@@ -1794,24 +1351,6 @@
uint64_t reserved_49_63:15;
#endif
} s;
- struct cvmx_ipd_red_quex_param_s cn30xx;
- struct cvmx_ipd_red_quex_param_s cn31xx;
- struct cvmx_ipd_red_quex_param_s cn38xx;
- struct cvmx_ipd_red_quex_param_s cn38xxp2;
- struct cvmx_ipd_red_quex_param_s cn50xx;
- struct cvmx_ipd_red_quex_param_s cn52xx;
- struct cvmx_ipd_red_quex_param_s cn52xxp1;
- struct cvmx_ipd_red_quex_param_s cn56xx;
- struct cvmx_ipd_red_quex_param_s cn56xxp1;
- struct cvmx_ipd_red_quex_param_s cn58xx;
- struct cvmx_ipd_red_quex_param_s cn58xxp1;
- struct cvmx_ipd_red_quex_param_s cn61xx;
- struct cvmx_ipd_red_quex_param_s cn63xx;
- struct cvmx_ipd_red_quex_param_s cn63xxp1;
- struct cvmx_ipd_red_quex_param_s cn66xx;
- struct cvmx_ipd_red_quex_param_s cn68xx;
- struct cvmx_ipd_red_quex_param_s cn68xxp1;
- struct cvmx_ipd_red_quex_param_s cnf71xx;
};
union cvmx_ipd_req_wgt {
@@ -1837,7 +1376,6 @@
uint64_t wgt7:8;
#endif
} s;
- struct cvmx_ipd_req_wgt_s cn68xx;
};
union cvmx_ipd_sub_port_bp_page_cnt {
@@ -1853,24 +1391,6 @@
uint64_t reserved_31_63:33;
#endif
} s;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn61xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn66xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xx;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xxp1;
- struct cvmx_ipd_sub_port_bp_page_cnt_s cnf71xx;
};
union cvmx_ipd_sub_port_fcs {
@@ -1897,7 +1417,6 @@
uint64_t reserved_3_63:61;
#endif
} cn30xx;
- struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx;
struct cvmx_ipd_sub_port_fcs_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
@@ -1907,19 +1426,6 @@
uint64_t reserved_32_63:32;
#endif
} cn38xx;
- struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2;
- struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx;
- struct cvmx_ipd_sub_port_fcs_s cn52xx;
- struct cvmx_ipd_sub_port_fcs_s cn52xxp1;
- struct cvmx_ipd_sub_port_fcs_s cn56xx;
- struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
- struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
- struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
- struct cvmx_ipd_sub_port_fcs_s cn61xx;
- struct cvmx_ipd_sub_port_fcs_s cn63xx;
- struct cvmx_ipd_sub_port_fcs_s cn63xxp1;
- struct cvmx_ipd_sub_port_fcs_s cn66xx;
- struct cvmx_ipd_sub_port_fcs_s cnf71xx;
};
union cvmx_ipd_sub_port_qos_cnt {
@@ -1935,17 +1441,6 @@
uint64_t reserved_41_63:23;
#endif
} s;
- struct cvmx_ipd_sub_port_qos_cnt_s cn52xx;
- struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
- struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
- struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
- struct cvmx_ipd_sub_port_qos_cnt_s cn61xx;
- struct cvmx_ipd_sub_port_qos_cnt_s cn63xx;
- struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1;
- struct cvmx_ipd_sub_port_qos_cnt_s cn66xx;
- struct cvmx_ipd_sub_port_qos_cnt_s cn68xx;
- struct cvmx_ipd_sub_port_qos_cnt_s cn68xxp1;
- struct cvmx_ipd_sub_port_qos_cnt_s cnf71xx;
};
union cvmx_ipd_wqe_fpa_queue {
@@ -1959,24 +1454,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_ipd_wqe_fpa_queue_s cn30xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn31xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn38xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn38xxp2;
- struct cvmx_ipd_wqe_fpa_queue_s cn50xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn52xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn52xxp1;
- struct cvmx_ipd_wqe_fpa_queue_s cn56xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
- struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
- struct cvmx_ipd_wqe_fpa_queue_s cn61xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn63xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1;
- struct cvmx_ipd_wqe_fpa_queue_s cn66xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn68xx;
- struct cvmx_ipd_wqe_fpa_queue_s cn68xxp1;
- struct cvmx_ipd_wqe_fpa_queue_s cnf71xx;
};
union cvmx_ipd_wqe_ptr_valid {
@@ -1990,21 +1467,6 @@
uint64_t reserved_29_63:35;
#endif
} s;
- struct cvmx_ipd_wqe_ptr_valid_s cn30xx;
- struct cvmx_ipd_wqe_ptr_valid_s cn31xx;
- struct cvmx_ipd_wqe_ptr_valid_s cn38xx;
- struct cvmx_ipd_wqe_ptr_valid_s cn50xx;
- struct cvmx_ipd_wqe_ptr_valid_s cn52xx;
- struct cvmx_ipd_wqe_ptr_valid_s cn52xxp1;
- struct cvmx_ipd_wqe_ptr_valid_s cn56xx;
- struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
- struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
- struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
- struct cvmx_ipd_wqe_ptr_valid_s cn61xx;
- struct cvmx_ipd_wqe_ptr_valid_s cn63xx;
- struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1;
- struct cvmx_ipd_wqe_ptr_valid_s cn66xx;
- struct cvmx_ipd_wqe_ptr_valid_s cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h
index cbdc14b..adab7b5 100644
--- a/arch/mips/include/asm/octeon/cvmx-ipd.h
+++ b/arch/mips/include/asm/octeon/cvmx-ipd.h
@@ -36,6 +36,7 @@
#include <asm/octeon/octeon-feature.h>
#include <asm/octeon/cvmx-ipd-defs.h>
+#include <asm/octeon/cvmx-pip-defs.h>
enum cvmx_ipd_mode {
CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
index fe50671..06ea132 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -104,7 +104,6 @@
__BITFIELD_FIELD(uint64_t ecc_ena:1,
;)))))))))))))
} cn38xx;
- struct cvmx_l2t_err_cn38xx cn38xxp2;
struct cvmx_l2t_err_cn50xx {
__BITFIELD_FIELD(uint64_t reserved_28_63:36,
__BITFIELD_FIELD(uint64_t lck_intena2:1,
@@ -139,11 +138,6 @@
__BITFIELD_FIELD(uint64_t ecc_ena:1,
;))))))))))))))
} cn52xx;
- struct cvmx_l2t_err_cn52xx cn52xxp1;
- struct cvmx_l2t_err_s cn56xx;
- struct cvmx_l2t_err_s cn56xxp1;
- struct cvmx_l2t_err_s cn58xx;
- struct cvmx_l2t_err_s cn58xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h
index d36d42b..0237907 100644
--- a/arch/mips/include/asm/octeon/cvmx-led-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h
@@ -53,12 +53,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_led_blink_s cn38xx;
- struct cvmx_led_blink_s cn38xxp2;
- struct cvmx_led_blink_s cn56xx;
- struct cvmx_led_blink_s cn56xxp1;
- struct cvmx_led_blink_s cn58xx;
- struct cvmx_led_blink_s cn58xxp1;
};
union cvmx_led_clk_phase {
@@ -72,12 +66,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_led_clk_phase_s cn38xx;
- struct cvmx_led_clk_phase_s cn38xxp2;
- struct cvmx_led_clk_phase_s cn56xx;
- struct cvmx_led_clk_phase_s cn56xxp1;
- struct cvmx_led_clk_phase_s cn58xx;
- struct cvmx_led_clk_phase_s cn58xxp1;
};
union cvmx_led_cylon {
@@ -91,12 +79,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_led_cylon_s cn38xx;
- struct cvmx_led_cylon_s cn38xxp2;
- struct cvmx_led_cylon_s cn56xx;
- struct cvmx_led_cylon_s cn56xxp1;
- struct cvmx_led_cylon_s cn58xx;
- struct cvmx_led_cylon_s cn58xxp1;
};
union cvmx_led_dbg {
@@ -110,12 +92,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_led_dbg_s cn38xx;
- struct cvmx_led_dbg_s cn38xxp2;
- struct cvmx_led_dbg_s cn56xx;
- struct cvmx_led_dbg_s cn56xxp1;
- struct cvmx_led_dbg_s cn58xx;
- struct cvmx_led_dbg_s cn58xxp1;
};
union cvmx_led_en {
@@ -129,12 +105,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_led_en_s cn38xx;
- struct cvmx_led_en_s cn38xxp2;
- struct cvmx_led_en_s cn56xx;
- struct cvmx_led_en_s cn56xxp1;
- struct cvmx_led_en_s cn58xx;
- struct cvmx_led_en_s cn58xxp1;
};
union cvmx_led_polarity {
@@ -148,12 +118,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_led_polarity_s cn38xx;
- struct cvmx_led_polarity_s cn38xxp2;
- struct cvmx_led_polarity_s cn56xx;
- struct cvmx_led_polarity_s cn56xxp1;
- struct cvmx_led_polarity_s cn58xx;
- struct cvmx_led_polarity_s cn58xxp1;
};
union cvmx_led_prt {
@@ -167,12 +131,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_led_prt_s cn38xx;
- struct cvmx_led_prt_s cn38xxp2;
- struct cvmx_led_prt_s cn56xx;
- struct cvmx_led_prt_s cn56xxp1;
- struct cvmx_led_prt_s cn58xx;
- struct cvmx_led_prt_s cn58xxp1;
};
union cvmx_led_prt_fmt {
@@ -186,12 +144,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_led_prt_fmt_s cn38xx;
- struct cvmx_led_prt_fmt_s cn38xxp2;
- struct cvmx_led_prt_fmt_s cn56xx;
- struct cvmx_led_prt_fmt_s cn56xxp1;
- struct cvmx_led_prt_fmt_s cn58xx;
- struct cvmx_led_prt_fmt_s cn58xxp1;
};
union cvmx_led_prt_statusx {
@@ -205,12 +157,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_led_prt_statusx_s cn38xx;
- struct cvmx_led_prt_statusx_s cn38xxp2;
- struct cvmx_led_prt_statusx_s cn56xx;
- struct cvmx_led_prt_statusx_s cn56xxp1;
- struct cvmx_led_prt_statusx_s cn58xx;
- struct cvmx_led_prt_statusx_s cn58xxp1;
};
union cvmx_led_udd_cntx {
@@ -224,12 +170,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_led_udd_cntx_s cn38xx;
- struct cvmx_led_udd_cntx_s cn38xxp2;
- struct cvmx_led_udd_cntx_s cn56xx;
- struct cvmx_led_udd_cntx_s cn56xxp1;
- struct cvmx_led_udd_cntx_s cn58xx;
- struct cvmx_led_udd_cntx_s cn58xxp1;
};
union cvmx_led_udd_datx {
@@ -243,12 +183,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_led_udd_datx_s cn38xx;
- struct cvmx_led_udd_datx_s cn38xxp2;
- struct cvmx_led_udd_datx_s cn56xx;
- struct cvmx_led_udd_datx_s cn56xxp1;
- struct cvmx_led_udd_datx_s cn58xx;
- struct cvmx_led_udd_datx_s cn58xxp1;
};
union cvmx_led_udd_dat_clrx {
@@ -262,12 +196,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_led_udd_dat_clrx_s cn38xx;
- struct cvmx_led_udd_dat_clrx_s cn38xxp2;
- struct cvmx_led_udd_dat_clrx_s cn56xx;
- struct cvmx_led_udd_dat_clrx_s cn56xxp1;
- struct cvmx_led_udd_dat_clrx_s cn58xx;
- struct cvmx_led_udd_dat_clrx_s cn58xxp1;
};
union cvmx_led_udd_dat_setx {
@@ -281,12 +209,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_led_udd_dat_setx_s cn38xx;
- struct cvmx_led_udd_dat_setx_s cn38xxp2;
- struct cvmx_led_udd_dat_setx_s cn56xx;
- struct cvmx_led_udd_dat_setx_s cn56xxp1;
- struct cvmx_led_udd_dat_setx_s cn58xx;
- struct cvmx_led_udd_dat_setx_s cn58xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
index 36f5107..4167a4c 100644
--- a/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-lmcx-defs.h
@@ -189,11 +189,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_lmcx_bist_ctl_s cn50xx;
- struct cvmx_lmcx_bist_ctl_s cn52xx;
- struct cvmx_lmcx_bist_ctl_s cn52xxp1;
- struct cvmx_lmcx_bist_ctl_s cn56xx;
- struct cvmx_lmcx_bist_ctl_s cn56xxp1;
};
union cvmx_lmcx_bist_result {
@@ -236,10 +231,6 @@
uint64_t reserved_9_63:55;
#endif
} cn50xx;
- struct cvmx_lmcx_bist_result_s cn52xx;
- struct cvmx_lmcx_bist_result_s cn52xxp1;
- struct cvmx_lmcx_bist_result_s cn56xx;
- struct cvmx_lmcx_bist_result_s cn56xxp1;
};
union cvmx_lmcx_char_ctl {
@@ -263,7 +254,6 @@
uint64_t reserved_44_63:20;
#endif
} s;
- struct cvmx_lmcx_char_ctl_s cn61xx;
struct cvmx_lmcx_char_ctl_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_42_63:22;
@@ -279,11 +269,6 @@
uint64_t reserved_42_63:22;
#endif
} cn63xx;
- struct cvmx_lmcx_char_ctl_cn63xx cn63xxp1;
- struct cvmx_lmcx_char_ctl_s cn66xx;
- struct cvmx_lmcx_char_ctl_s cn68xx;
- struct cvmx_lmcx_char_ctl_cn63xx cn68xxp1;
- struct cvmx_lmcx_char_ctl_s cnf71xx;
};
union cvmx_lmcx_char_mask0 {
@@ -295,13 +280,6 @@
uint64_t mask:64;
#endif
} s;
- struct cvmx_lmcx_char_mask0_s cn61xx;
- struct cvmx_lmcx_char_mask0_s cn63xx;
- struct cvmx_lmcx_char_mask0_s cn63xxp1;
- struct cvmx_lmcx_char_mask0_s cn66xx;
- struct cvmx_lmcx_char_mask0_s cn68xx;
- struct cvmx_lmcx_char_mask0_s cn68xxp1;
- struct cvmx_lmcx_char_mask0_s cnf71xx;
};
union cvmx_lmcx_char_mask1 {
@@ -315,13 +293,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_lmcx_char_mask1_s cn61xx;
- struct cvmx_lmcx_char_mask1_s cn63xx;
- struct cvmx_lmcx_char_mask1_s cn63xxp1;
- struct cvmx_lmcx_char_mask1_s cn66xx;
- struct cvmx_lmcx_char_mask1_s cn68xx;
- struct cvmx_lmcx_char_mask1_s cn68xxp1;
- struct cvmx_lmcx_char_mask1_s cnf71xx;
};
union cvmx_lmcx_char_mask2 {
@@ -333,13 +304,6 @@
uint64_t mask:64;
#endif
} s;
- struct cvmx_lmcx_char_mask2_s cn61xx;
- struct cvmx_lmcx_char_mask2_s cn63xx;
- struct cvmx_lmcx_char_mask2_s cn63xxp1;
- struct cvmx_lmcx_char_mask2_s cn66xx;
- struct cvmx_lmcx_char_mask2_s cn68xx;
- struct cvmx_lmcx_char_mask2_s cn68xxp1;
- struct cvmx_lmcx_char_mask2_s cnf71xx;
};
union cvmx_lmcx_char_mask3 {
@@ -353,13 +317,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_lmcx_char_mask3_s cn61xx;
- struct cvmx_lmcx_char_mask3_s cn63xx;
- struct cvmx_lmcx_char_mask3_s cn63xxp1;
- struct cvmx_lmcx_char_mask3_s cn66xx;
- struct cvmx_lmcx_char_mask3_s cn68xx;
- struct cvmx_lmcx_char_mask3_s cn68xxp1;
- struct cvmx_lmcx_char_mask3_s cnf71xx;
};
union cvmx_lmcx_char_mask4 {
@@ -393,13 +350,6 @@
uint64_t reserved_33_63:31;
#endif
} s;
- struct cvmx_lmcx_char_mask4_s cn61xx;
- struct cvmx_lmcx_char_mask4_s cn63xx;
- struct cvmx_lmcx_char_mask4_s cn63xxp1;
- struct cvmx_lmcx_char_mask4_s cn66xx;
- struct cvmx_lmcx_char_mask4_s cn68xx;
- struct cvmx_lmcx_char_mask4_s cn68xxp1;
- struct cvmx_lmcx_char_mask4_s cnf71xx;
};
union cvmx_lmcx_comp_ctl {
@@ -448,9 +398,6 @@
uint64_t reserved_32_63:32;
#endif
} cn30xx;
- struct cvmx_lmcx_comp_ctl_cn30xx cn31xx;
- struct cvmx_lmcx_comp_ctl_cn30xx cn38xx;
- struct cvmx_lmcx_comp_ctl_cn30xx cn38xxp2;
struct cvmx_lmcx_comp_ctl_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
@@ -470,11 +417,6 @@
uint64_t reserved_32_63:32;
#endif
} cn50xx;
- struct cvmx_lmcx_comp_ctl_cn50xx cn52xx;
- struct cvmx_lmcx_comp_ctl_cn50xx cn52xxp1;
- struct cvmx_lmcx_comp_ctl_cn50xx cn56xx;
- struct cvmx_lmcx_comp_ctl_cn50xx cn56xxp1;
- struct cvmx_lmcx_comp_ctl_cn50xx cn58xx;
struct cvmx_lmcx_comp_ctl_cn58xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
@@ -525,13 +467,6 @@
uint64_t reserved_34_63:30;
#endif
} s;
- struct cvmx_lmcx_comp_ctl2_s cn61xx;
- struct cvmx_lmcx_comp_ctl2_s cn63xx;
- struct cvmx_lmcx_comp_ctl2_s cn63xxp1;
- struct cvmx_lmcx_comp_ctl2_s cn66xx;
- struct cvmx_lmcx_comp_ctl2_s cn68xx;
- struct cvmx_lmcx_comp_ctl2_s cn68xxp1;
- struct cvmx_lmcx_comp_ctl2_s cnf71xx;
};
union cvmx_lmcx_config {
@@ -587,7 +522,6 @@
uint64_t reserved_61_63:3;
#endif
} s;
- struct cvmx_lmcx_config_s cn61xx;
struct cvmx_lmcx_config_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_59_63:5;
@@ -723,9 +657,6 @@
uint64_t reserved_60_63:4;
#endif
} cn66xx;
- struct cvmx_lmcx_config_cn63xx cn68xx;
- struct cvmx_lmcx_config_cn63xx cn68xxp1;
- struct cvmx_lmcx_config_s cnf71xx;
};
union cvmx_lmcx_control {
@@ -787,7 +718,6 @@
uint64_t scramble_ena:1;
#endif
} s;
- struct cvmx_lmcx_control_s cn61xx;
struct cvmx_lmcx_control_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
@@ -833,7 +763,6 @@
uint64_t reserved_24_63:40;
#endif
} cn63xx;
- struct cvmx_lmcx_control_cn63xx cn63xxp1;
struct cvmx_lmcx_control_cn66xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t scramble_ena:1;
@@ -938,8 +867,6 @@
uint64_t reserved_63_63:1;
#endif
} cn68xx;
- struct cvmx_lmcx_control_cn68xx cn68xxp1;
- struct cvmx_lmcx_control_cn66xx cnf71xx;
};
union cvmx_lmcx_ctl {
@@ -1032,7 +959,6 @@
uint64_t reserved_32_63:32;
#endif
} cn30xx;
- struct cvmx_lmcx_ctl_cn30xx cn31xx;
struct cvmx_lmcx_ctl_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
@@ -1076,7 +1002,6 @@
uint64_t reserved_32_63:32;
#endif
} cn38xx;
- struct cvmx_lmcx_ctl_cn38xx cn38xxp2;
struct cvmx_lmcx_ctl_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
@@ -1165,9 +1090,6 @@
uint64_t reserved_32_63:32;
#endif
} cn52xx;
- struct cvmx_lmcx_ctl_cn52xx cn52xxp1;
- struct cvmx_lmcx_ctl_cn52xx cn56xx;
- struct cvmx_lmcx_ctl_cn52xx cn56xxp1;
struct cvmx_lmcx_ctl_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
@@ -1211,7 +1133,6 @@
uint64_t reserved_32_63:32;
#endif
} cn58xx;
- struct cvmx_lmcx_ctl_cn58xx cn58xxp1;
};
union cvmx_lmcx_ctl1 {
@@ -1284,9 +1205,6 @@
uint64_t reserved_21_63:43;
#endif
} cn52xx;
- struct cvmx_lmcx_ctl1_cn52xx cn52xxp1;
- struct cvmx_lmcx_ctl1_cn52xx cn56xx;
- struct cvmx_lmcx_ctl1_cn52xx cn56xxp1;
struct cvmx_lmcx_ctl1_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
@@ -1300,7 +1218,6 @@
uint64_t reserved_10_63:54;
#endif
} cn58xx;
- struct cvmx_lmcx_ctl1_cn58xx cn58xxp1;
};
union cvmx_lmcx_dclk_cnt {
@@ -1312,13 +1229,6 @@
uint64_t dclkcnt:64;
#endif
} s;
- struct cvmx_lmcx_dclk_cnt_s cn61xx;
- struct cvmx_lmcx_dclk_cnt_s cn63xx;
- struct cvmx_lmcx_dclk_cnt_s cn63xxp1;
- struct cvmx_lmcx_dclk_cnt_s cn66xx;
- struct cvmx_lmcx_dclk_cnt_s cn68xx;
- struct cvmx_lmcx_dclk_cnt_s cn68xxp1;
- struct cvmx_lmcx_dclk_cnt_s cnf71xx;
};
union cvmx_lmcx_dclk_cnt_hi {
@@ -1332,17 +1242,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_dclk_cnt_hi_s cn30xx;
- struct cvmx_lmcx_dclk_cnt_hi_s cn31xx;
- struct cvmx_lmcx_dclk_cnt_hi_s cn38xx;
- struct cvmx_lmcx_dclk_cnt_hi_s cn38xxp2;
- struct cvmx_lmcx_dclk_cnt_hi_s cn50xx;
- struct cvmx_lmcx_dclk_cnt_hi_s cn52xx;
- struct cvmx_lmcx_dclk_cnt_hi_s cn52xxp1;
- struct cvmx_lmcx_dclk_cnt_hi_s cn56xx;
- struct cvmx_lmcx_dclk_cnt_hi_s cn56xxp1;
- struct cvmx_lmcx_dclk_cnt_hi_s cn58xx;
- struct cvmx_lmcx_dclk_cnt_hi_s cn58xxp1;
};
union cvmx_lmcx_dclk_cnt_lo {
@@ -1356,17 +1255,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_dclk_cnt_lo_s cn30xx;
- struct cvmx_lmcx_dclk_cnt_lo_s cn31xx;
- struct cvmx_lmcx_dclk_cnt_lo_s cn38xx;
- struct cvmx_lmcx_dclk_cnt_lo_s cn38xxp2;
- struct cvmx_lmcx_dclk_cnt_lo_s cn50xx;
- struct cvmx_lmcx_dclk_cnt_lo_s cn52xx;
- struct cvmx_lmcx_dclk_cnt_lo_s cn52xxp1;
- struct cvmx_lmcx_dclk_cnt_lo_s cn56xx;
- struct cvmx_lmcx_dclk_cnt_lo_s cn56xxp1;
- struct cvmx_lmcx_dclk_cnt_lo_s cn58xx;
- struct cvmx_lmcx_dclk_cnt_lo_s cn58xxp1;
};
union cvmx_lmcx_dclk_ctl {
@@ -1386,8 +1274,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_lmcx_dclk_ctl_s cn56xx;
- struct cvmx_lmcx_dclk_ctl_s cn56xxp1;
};
union cvmx_lmcx_ddr2_ctl {
@@ -1474,16 +1360,6 @@
uint64_t reserved_32_63:32;
#endif
} cn30xx;
- struct cvmx_lmcx_ddr2_ctl_cn30xx cn31xx;
- struct cvmx_lmcx_ddr2_ctl_s cn38xx;
- struct cvmx_lmcx_ddr2_ctl_s cn38xxp2;
- struct cvmx_lmcx_ddr2_ctl_s cn50xx;
- struct cvmx_lmcx_ddr2_ctl_s cn52xx;
- struct cvmx_lmcx_ddr2_ctl_s cn52xxp1;
- struct cvmx_lmcx_ddr2_ctl_s cn56xx;
- struct cvmx_lmcx_ddr2_ctl_s cn56xxp1;
- struct cvmx_lmcx_ddr2_ctl_s cn58xx;
- struct cvmx_lmcx_ddr2_ctl_s cn58xxp1;
};
union cvmx_lmcx_ddr_pll_ctl {
@@ -1515,13 +1391,6 @@
uint64_t reserved_27_63:37;
#endif
} s;
- struct cvmx_lmcx_ddr_pll_ctl_s cn61xx;
- struct cvmx_lmcx_ddr_pll_ctl_s cn63xx;
- struct cvmx_lmcx_ddr_pll_ctl_s cn63xxp1;
- struct cvmx_lmcx_ddr_pll_ctl_s cn66xx;
- struct cvmx_lmcx_ddr_pll_ctl_s cn68xx;
- struct cvmx_lmcx_ddr_pll_ctl_s cn68xxp1;
- struct cvmx_lmcx_ddr_pll_ctl_s cnf71xx;
};
union cvmx_lmcx_delay_cfg {
@@ -1539,7 +1408,6 @@
uint64_t reserved_15_63:49;
#endif
} s;
- struct cvmx_lmcx_delay_cfg_s cn30xx;
struct cvmx_lmcx_delay_cfg_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
@@ -1557,13 +1425,6 @@
uint64_t reserved_14_63:50;
#endif
} cn38xx;
- struct cvmx_lmcx_delay_cfg_cn38xx cn50xx;
- struct cvmx_lmcx_delay_cfg_cn38xx cn52xx;
- struct cvmx_lmcx_delay_cfg_cn38xx cn52xxp1;
- struct cvmx_lmcx_delay_cfg_cn38xx cn56xx;
- struct cvmx_lmcx_delay_cfg_cn38xx cn56xxp1;
- struct cvmx_lmcx_delay_cfg_cn38xx cn58xx;
- struct cvmx_lmcx_delay_cfg_cn38xx cn58xxp1;
};
union cvmx_lmcx_dimmx_params {
@@ -1605,13 +1466,6 @@
uint64_t rc15:4;
#endif
} s;
- struct cvmx_lmcx_dimmx_params_s cn61xx;
- struct cvmx_lmcx_dimmx_params_s cn63xx;
- struct cvmx_lmcx_dimmx_params_s cn63xxp1;
- struct cvmx_lmcx_dimmx_params_s cn66xx;
- struct cvmx_lmcx_dimmx_params_s cn68xx;
- struct cvmx_lmcx_dimmx_params_s cn68xxp1;
- struct cvmx_lmcx_dimmx_params_s cnf71xx;
};
union cvmx_lmcx_dimm_ctl {
@@ -1631,13 +1485,6 @@
uint64_t reserved_46_63:18;
#endif
} s;
- struct cvmx_lmcx_dimm_ctl_s cn61xx;
- struct cvmx_lmcx_dimm_ctl_s cn63xx;
- struct cvmx_lmcx_dimm_ctl_s cn63xxp1;
- struct cvmx_lmcx_dimm_ctl_s cn66xx;
- struct cvmx_lmcx_dimm_ctl_s cn68xx;
- struct cvmx_lmcx_dimm_ctl_s cn68xxp1;
- struct cvmx_lmcx_dimm_ctl_s cnf71xx;
};
union cvmx_lmcx_dll_ctl {
@@ -1657,10 +1504,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_lmcx_dll_ctl_s cn52xx;
- struct cvmx_lmcx_dll_ctl_s cn52xxp1;
- struct cvmx_lmcx_dll_ctl_s cn56xx;
- struct cvmx_lmcx_dll_ctl_s cn56xxp1;
};
union cvmx_lmcx_dll_ctl2 {
@@ -1684,7 +1527,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_lmcx_dll_ctl2_s cn61xx;
struct cvmx_lmcx_dll_ctl2_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_15_63:49;
@@ -1702,11 +1544,6 @@
uint64_t reserved_15_63:49;
#endif
} cn63xx;
- struct cvmx_lmcx_dll_ctl2_cn63xx cn63xxp1;
- struct cvmx_lmcx_dll_ctl2_cn63xx cn66xx;
- struct cvmx_lmcx_dll_ctl2_s cn68xx;
- struct cvmx_lmcx_dll_ctl2_s cn68xxp1;
- struct cvmx_lmcx_dll_ctl2_s cnf71xx;
};
union cvmx_lmcx_dll_ctl3 {
@@ -1748,7 +1585,6 @@
uint64_t reserved_41_63:23;
#endif
} s;
- struct cvmx_lmcx_dll_ctl3_s cn61xx;
struct cvmx_lmcx_dll_ctl3_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
@@ -1776,11 +1612,6 @@
uint64_t reserved_29_63:35;
#endif
} cn63xx;
- struct cvmx_lmcx_dll_ctl3_cn63xx cn63xxp1;
- struct cvmx_lmcx_dll_ctl3_cn63xx cn66xx;
- struct cvmx_lmcx_dll_ctl3_s cn68xx;
- struct cvmx_lmcx_dll_ctl3_s cn68xxp1;
- struct cvmx_lmcx_dll_ctl3_s cnf71xx;
};
union cvmx_lmcx_dual_memcfg {
@@ -1800,13 +1631,6 @@
uint64_t reserved_20_63:44;
#endif
} s;
- struct cvmx_lmcx_dual_memcfg_s cn50xx;
- struct cvmx_lmcx_dual_memcfg_s cn52xx;
- struct cvmx_lmcx_dual_memcfg_s cn52xxp1;
- struct cvmx_lmcx_dual_memcfg_s cn56xx;
- struct cvmx_lmcx_dual_memcfg_s cn56xxp1;
- struct cvmx_lmcx_dual_memcfg_s cn58xx;
- struct cvmx_lmcx_dual_memcfg_s cn58xxp1;
struct cvmx_lmcx_dual_memcfg_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_19_63:45;
@@ -1820,12 +1644,6 @@
uint64_t reserved_19_63:45;
#endif
} cn61xx;
- struct cvmx_lmcx_dual_memcfg_cn61xx cn63xx;
- struct cvmx_lmcx_dual_memcfg_cn61xx cn63xxp1;
- struct cvmx_lmcx_dual_memcfg_cn61xx cn66xx;
- struct cvmx_lmcx_dual_memcfg_cn61xx cn68xx;
- struct cvmx_lmcx_dual_memcfg_cn61xx cn68xxp1;
- struct cvmx_lmcx_dual_memcfg_cn61xx cnf71xx;
};
union cvmx_lmcx_ecc_synd {
@@ -1845,24 +1663,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_ecc_synd_s cn30xx;
- struct cvmx_lmcx_ecc_synd_s cn31xx;
- struct cvmx_lmcx_ecc_synd_s cn38xx;
- struct cvmx_lmcx_ecc_synd_s cn38xxp2;
- struct cvmx_lmcx_ecc_synd_s cn50xx;
- struct cvmx_lmcx_ecc_synd_s cn52xx;
- struct cvmx_lmcx_ecc_synd_s cn52xxp1;
- struct cvmx_lmcx_ecc_synd_s cn56xx;
- struct cvmx_lmcx_ecc_synd_s cn56xxp1;
- struct cvmx_lmcx_ecc_synd_s cn58xx;
- struct cvmx_lmcx_ecc_synd_s cn58xxp1;
- struct cvmx_lmcx_ecc_synd_s cn61xx;
- struct cvmx_lmcx_ecc_synd_s cn63xx;
- struct cvmx_lmcx_ecc_synd_s cn63xxp1;
- struct cvmx_lmcx_ecc_synd_s cn66xx;
- struct cvmx_lmcx_ecc_synd_s cn68xx;
- struct cvmx_lmcx_ecc_synd_s cn68xxp1;
- struct cvmx_lmcx_ecc_synd_s cnf71xx;
};
union cvmx_lmcx_fadr {
@@ -1891,16 +1691,6 @@
uint64_t reserved_32_63:32;
#endif
} cn30xx;
- struct cvmx_lmcx_fadr_cn30xx cn31xx;
- struct cvmx_lmcx_fadr_cn30xx cn38xx;
- struct cvmx_lmcx_fadr_cn30xx cn38xxp2;
- struct cvmx_lmcx_fadr_cn30xx cn50xx;
- struct cvmx_lmcx_fadr_cn30xx cn52xx;
- struct cvmx_lmcx_fadr_cn30xx cn52xxp1;
- struct cvmx_lmcx_fadr_cn30xx cn56xx;
- struct cvmx_lmcx_fadr_cn30xx cn56xxp1;
- struct cvmx_lmcx_fadr_cn30xx cn58xx;
- struct cvmx_lmcx_fadr_cn30xx cn58xxp1;
struct cvmx_lmcx_fadr_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63:28;
@@ -1918,12 +1708,6 @@
uint64_t reserved_36_63:28;
#endif
} cn61xx;
- struct cvmx_lmcx_fadr_cn61xx cn63xx;
- struct cvmx_lmcx_fadr_cn61xx cn63xxp1;
- struct cvmx_lmcx_fadr_cn61xx cn66xx;
- struct cvmx_lmcx_fadr_cn61xx cn68xx;
- struct cvmx_lmcx_fadr_cn61xx cn68xxp1;
- struct cvmx_lmcx_fadr_cn61xx cnf71xx;
};
union cvmx_lmcx_ifb_cnt {
@@ -1935,13 +1719,6 @@
uint64_t ifbcnt:64;
#endif
} s;
- struct cvmx_lmcx_ifb_cnt_s cn61xx;
- struct cvmx_lmcx_ifb_cnt_s cn63xx;
- struct cvmx_lmcx_ifb_cnt_s cn63xxp1;
- struct cvmx_lmcx_ifb_cnt_s cn66xx;
- struct cvmx_lmcx_ifb_cnt_s cn68xx;
- struct cvmx_lmcx_ifb_cnt_s cn68xxp1;
- struct cvmx_lmcx_ifb_cnt_s cnf71xx;
};
union cvmx_lmcx_ifb_cnt_hi {
@@ -1955,17 +1732,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_ifb_cnt_hi_s cn30xx;
- struct cvmx_lmcx_ifb_cnt_hi_s cn31xx;
- struct cvmx_lmcx_ifb_cnt_hi_s cn38xx;
- struct cvmx_lmcx_ifb_cnt_hi_s cn38xxp2;
- struct cvmx_lmcx_ifb_cnt_hi_s cn50xx;
- struct cvmx_lmcx_ifb_cnt_hi_s cn52xx;
- struct cvmx_lmcx_ifb_cnt_hi_s cn52xxp1;
- struct cvmx_lmcx_ifb_cnt_hi_s cn56xx;
- struct cvmx_lmcx_ifb_cnt_hi_s cn56xxp1;
- struct cvmx_lmcx_ifb_cnt_hi_s cn58xx;
- struct cvmx_lmcx_ifb_cnt_hi_s cn58xxp1;
};
union cvmx_lmcx_ifb_cnt_lo {
@@ -1979,17 +1745,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_ifb_cnt_lo_s cn30xx;
- struct cvmx_lmcx_ifb_cnt_lo_s cn31xx;
- struct cvmx_lmcx_ifb_cnt_lo_s cn38xx;
- struct cvmx_lmcx_ifb_cnt_lo_s cn38xxp2;
- struct cvmx_lmcx_ifb_cnt_lo_s cn50xx;
- struct cvmx_lmcx_ifb_cnt_lo_s cn52xx;
- struct cvmx_lmcx_ifb_cnt_lo_s cn52xxp1;
- struct cvmx_lmcx_ifb_cnt_lo_s cn56xx;
- struct cvmx_lmcx_ifb_cnt_lo_s cn56xxp1;
- struct cvmx_lmcx_ifb_cnt_lo_s cn58xx;
- struct cvmx_lmcx_ifb_cnt_lo_s cn58xxp1;
};
union cvmx_lmcx_int {
@@ -2007,13 +1762,6 @@
uint64_t reserved_9_63:55;
#endif
} s;
- struct cvmx_lmcx_int_s cn61xx;
- struct cvmx_lmcx_int_s cn63xx;
- struct cvmx_lmcx_int_s cn63xxp1;
- struct cvmx_lmcx_int_s cn66xx;
- struct cvmx_lmcx_int_s cn68xx;
- struct cvmx_lmcx_int_s cn68xxp1;
- struct cvmx_lmcx_int_s cnf71xx;
};
union cvmx_lmcx_int_en {
@@ -2031,13 +1779,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_lmcx_int_en_s cn61xx;
- struct cvmx_lmcx_int_en_s cn63xx;
- struct cvmx_lmcx_int_en_s cn63xxp1;
- struct cvmx_lmcx_int_en_s cn66xx;
- struct cvmx_lmcx_int_en_s cn68xx;
- struct cvmx_lmcx_int_en_s cn68xxp1;
- struct cvmx_lmcx_int_en_s cnf71xx;
};
union cvmx_lmcx_mem_cfg0 {
@@ -2075,17 +1816,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_mem_cfg0_s cn30xx;
- struct cvmx_lmcx_mem_cfg0_s cn31xx;
- struct cvmx_lmcx_mem_cfg0_s cn38xx;
- struct cvmx_lmcx_mem_cfg0_s cn38xxp2;
- struct cvmx_lmcx_mem_cfg0_s cn50xx;
- struct cvmx_lmcx_mem_cfg0_s cn52xx;
- struct cvmx_lmcx_mem_cfg0_s cn52xxp1;
- struct cvmx_lmcx_mem_cfg0_s cn56xx;
- struct cvmx_lmcx_mem_cfg0_s cn56xxp1;
- struct cvmx_lmcx_mem_cfg0_s cn58xx;
- struct cvmx_lmcx_mem_cfg0_s cn58xxp1;
};
union cvmx_lmcx_mem_cfg1 {
@@ -2115,8 +1845,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_mem_cfg1_s cn30xx;
- struct cvmx_lmcx_mem_cfg1_s cn31xx;
struct cvmx_lmcx_mem_cfg1_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63:33;
@@ -2140,14 +1868,6 @@
uint64_t reserved_31_63:33;
#endif
} cn38xx;
- struct cvmx_lmcx_mem_cfg1_cn38xx cn38xxp2;
- struct cvmx_lmcx_mem_cfg1_s cn50xx;
- struct cvmx_lmcx_mem_cfg1_cn38xx cn52xx;
- struct cvmx_lmcx_mem_cfg1_cn38xx cn52xxp1;
- struct cvmx_lmcx_mem_cfg1_cn38xx cn56xx;
- struct cvmx_lmcx_mem_cfg1_cn38xx cn56xxp1;
- struct cvmx_lmcx_mem_cfg1_cn38xx cn58xx;
- struct cvmx_lmcx_mem_cfg1_cn38xx cn58xxp1;
};
union cvmx_lmcx_modereg_params0 {
@@ -2189,13 +1909,6 @@
uint64_t reserved_25_63:39;
#endif
} s;
- struct cvmx_lmcx_modereg_params0_s cn61xx;
- struct cvmx_lmcx_modereg_params0_s cn63xx;
- struct cvmx_lmcx_modereg_params0_s cn63xxp1;
- struct cvmx_lmcx_modereg_params0_s cn66xx;
- struct cvmx_lmcx_modereg_params0_s cn68xx;
- struct cvmx_lmcx_modereg_params0_s cn68xxp1;
- struct cvmx_lmcx_modereg_params0_s cnf71xx;
};
union cvmx_lmcx_modereg_params1 {
@@ -2255,13 +1968,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_lmcx_modereg_params1_s cn61xx;
- struct cvmx_lmcx_modereg_params1_s cn63xx;
- struct cvmx_lmcx_modereg_params1_s cn63xxp1;
- struct cvmx_lmcx_modereg_params1_s cn66xx;
- struct cvmx_lmcx_modereg_params1_s cn68xx;
- struct cvmx_lmcx_modereg_params1_s cn68xxp1;
- struct cvmx_lmcx_modereg_params1_s cnf71xx;
};
union cvmx_lmcx_nxm {
@@ -2300,15 +2006,6 @@
uint64_t reserved_8_63:56;
#endif
} cn52xx;
- struct cvmx_lmcx_nxm_cn52xx cn56xx;
- struct cvmx_lmcx_nxm_cn52xx cn58xx;
- struct cvmx_lmcx_nxm_s cn61xx;
- struct cvmx_lmcx_nxm_s cn63xx;
- struct cvmx_lmcx_nxm_s cn63xxp1;
- struct cvmx_lmcx_nxm_s cn66xx;
- struct cvmx_lmcx_nxm_s cn68xx;
- struct cvmx_lmcx_nxm_s cn68xxp1;
- struct cvmx_lmcx_nxm_s cnf71xx;
};
union cvmx_lmcx_ops_cnt {
@@ -2320,13 +2017,6 @@
uint64_t opscnt:64;
#endif
} s;
- struct cvmx_lmcx_ops_cnt_s cn61xx;
- struct cvmx_lmcx_ops_cnt_s cn63xx;
- struct cvmx_lmcx_ops_cnt_s cn63xxp1;
- struct cvmx_lmcx_ops_cnt_s cn66xx;
- struct cvmx_lmcx_ops_cnt_s cn68xx;
- struct cvmx_lmcx_ops_cnt_s cn68xxp1;
- struct cvmx_lmcx_ops_cnt_s cnf71xx;
};
union cvmx_lmcx_ops_cnt_hi {
@@ -2340,17 +2030,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_ops_cnt_hi_s cn30xx;
- struct cvmx_lmcx_ops_cnt_hi_s cn31xx;
- struct cvmx_lmcx_ops_cnt_hi_s cn38xx;
- struct cvmx_lmcx_ops_cnt_hi_s cn38xxp2;
- struct cvmx_lmcx_ops_cnt_hi_s cn50xx;
- struct cvmx_lmcx_ops_cnt_hi_s cn52xx;
- struct cvmx_lmcx_ops_cnt_hi_s cn52xxp1;
- struct cvmx_lmcx_ops_cnt_hi_s cn56xx;
- struct cvmx_lmcx_ops_cnt_hi_s cn56xxp1;
- struct cvmx_lmcx_ops_cnt_hi_s cn58xx;
- struct cvmx_lmcx_ops_cnt_hi_s cn58xxp1;
};
union cvmx_lmcx_ops_cnt_lo {
@@ -2364,17 +2043,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_ops_cnt_lo_s cn30xx;
- struct cvmx_lmcx_ops_cnt_lo_s cn31xx;
- struct cvmx_lmcx_ops_cnt_lo_s cn38xx;
- struct cvmx_lmcx_ops_cnt_lo_s cn38xxp2;
- struct cvmx_lmcx_ops_cnt_lo_s cn50xx;
- struct cvmx_lmcx_ops_cnt_lo_s cn52xx;
- struct cvmx_lmcx_ops_cnt_lo_s cn52xxp1;
- struct cvmx_lmcx_ops_cnt_lo_s cn56xx;
- struct cvmx_lmcx_ops_cnt_lo_s cn56xxp1;
- struct cvmx_lmcx_ops_cnt_lo_s cn58xx;
- struct cvmx_lmcx_ops_cnt_lo_s cn58xxp1;
};
union cvmx_lmcx_phy_ctl {
@@ -2404,8 +2072,6 @@
uint64_t reserved_15_63:49;
#endif
} s;
- struct cvmx_lmcx_phy_ctl_s cn61xx;
- struct cvmx_lmcx_phy_ctl_s cn63xx;
struct cvmx_lmcx_phy_ctl_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
@@ -2429,10 +2095,6 @@
uint64_t reserved_14_63:50;
#endif
} cn63xxp1;
- struct cvmx_lmcx_phy_ctl_s cn66xx;
- struct cvmx_lmcx_phy_ctl_s cn68xx;
- struct cvmx_lmcx_phy_ctl_s cn68xxp1;
- struct cvmx_lmcx_phy_ctl_s cnf71xx;
};
union cvmx_lmcx_pll_bwctl {
@@ -2448,10 +2110,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_lmcx_pll_bwctl_s cn30xx;
- struct cvmx_lmcx_pll_bwctl_s cn31xx;
- struct cvmx_lmcx_pll_bwctl_s cn38xx;
- struct cvmx_lmcx_pll_bwctl_s cn38xxp2;
};
union cvmx_lmcx_pll_ctl {
@@ -2520,9 +2178,6 @@
uint64_t reserved_29_63:35;
#endif
} cn50xx;
- struct cvmx_lmcx_pll_ctl_s cn52xx;
- struct cvmx_lmcx_pll_ctl_s cn52xxp1;
- struct cvmx_lmcx_pll_ctl_cn50xx cn56xx;
struct cvmx_lmcx_pll_ctl_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
@@ -2552,8 +2207,6 @@
uint64_t reserved_28_63:36;
#endif
} cn56xxp1;
- struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xx;
- struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xxp1;
};
union cvmx_lmcx_pll_status {
@@ -2575,12 +2228,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_pll_status_s cn50xx;
- struct cvmx_lmcx_pll_status_s cn52xx;
- struct cvmx_lmcx_pll_status_s cn52xxp1;
- struct cvmx_lmcx_pll_status_s cn56xx;
- struct cvmx_lmcx_pll_status_s cn56xxp1;
- struct cvmx_lmcx_pll_status_s cn58xx;
struct cvmx_lmcx_pll_status_cn58xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
@@ -2615,10 +2262,6 @@
uint64_t reserved_44_63:20;
#endif
} s;
- struct cvmx_lmcx_read_level_ctl_s cn52xx;
- struct cvmx_lmcx_read_level_ctl_s cn52xxp1;
- struct cvmx_lmcx_read_level_ctl_s cn56xx;
- struct cvmx_lmcx_read_level_ctl_s cn56xxp1;
};
union cvmx_lmcx_read_level_dbg {
@@ -2636,10 +2279,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_read_level_dbg_s cn52xx;
- struct cvmx_lmcx_read_level_dbg_s cn52xxp1;
- struct cvmx_lmcx_read_level_dbg_s cn56xx;
- struct cvmx_lmcx_read_level_dbg_s cn56xxp1;
};
union cvmx_lmcx_read_level_rankx {
@@ -2671,10 +2310,6 @@
uint64_t reserved_38_63:26;
#endif
} s;
- struct cvmx_lmcx_read_level_rankx_s cn52xx;
- struct cvmx_lmcx_read_level_rankx_s cn52xxp1;
- struct cvmx_lmcx_read_level_rankx_s cn56xx;
- struct cvmx_lmcx_read_level_rankx_s cn56xxp1;
};
union cvmx_lmcx_reset_ctl {
@@ -2694,13 +2329,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_lmcx_reset_ctl_s cn61xx;
- struct cvmx_lmcx_reset_ctl_s cn63xx;
- struct cvmx_lmcx_reset_ctl_s cn63xxp1;
- struct cvmx_lmcx_reset_ctl_s cn66xx;
- struct cvmx_lmcx_reset_ctl_s cn68xx;
- struct cvmx_lmcx_reset_ctl_s cn68xxp1;
- struct cvmx_lmcx_reset_ctl_s cnf71xx;
};
union cvmx_lmcx_rlevel_ctl {
@@ -2730,8 +2358,6 @@
uint64_t reserved_22_63:42;
#endif
} s;
- struct cvmx_lmcx_rlevel_ctl_s cn61xx;
- struct cvmx_lmcx_rlevel_ctl_s cn63xx;
struct cvmx_lmcx_rlevel_ctl_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
@@ -2745,10 +2371,6 @@
uint64_t reserved_9_63:55;
#endif
} cn63xxp1;
- struct cvmx_lmcx_rlevel_ctl_s cn66xx;
- struct cvmx_lmcx_rlevel_ctl_s cn68xx;
- struct cvmx_lmcx_rlevel_ctl_s cn68xxp1;
- struct cvmx_lmcx_rlevel_ctl_s cnf71xx;
};
union cvmx_lmcx_rlevel_dbg {
@@ -2760,13 +2382,6 @@
uint64_t bitmask:64;
#endif
} s;
- struct cvmx_lmcx_rlevel_dbg_s cn61xx;
- struct cvmx_lmcx_rlevel_dbg_s cn63xx;
- struct cvmx_lmcx_rlevel_dbg_s cn63xxp1;
- struct cvmx_lmcx_rlevel_dbg_s cn66xx;
- struct cvmx_lmcx_rlevel_dbg_s cn68xx;
- struct cvmx_lmcx_rlevel_dbg_s cn68xxp1;
- struct cvmx_lmcx_rlevel_dbg_s cnf71xx;
};
union cvmx_lmcx_rlevel_rankx {
@@ -2798,13 +2413,6 @@
uint64_t reserved_56_63:8;
#endif
} s;
- struct cvmx_lmcx_rlevel_rankx_s cn61xx;
- struct cvmx_lmcx_rlevel_rankx_s cn63xx;
- struct cvmx_lmcx_rlevel_rankx_s cn63xxp1;
- struct cvmx_lmcx_rlevel_rankx_s cn66xx;
- struct cvmx_lmcx_rlevel_rankx_s cn68xx;
- struct cvmx_lmcx_rlevel_rankx_s cn68xxp1;
- struct cvmx_lmcx_rlevel_rankx_s cnf71xx;
};
union cvmx_lmcx_rodt_comp_ctl {
@@ -2826,13 +2434,6 @@
uint64_t reserved_17_63:47;
#endif
} s;
- struct cvmx_lmcx_rodt_comp_ctl_s cn50xx;
- struct cvmx_lmcx_rodt_comp_ctl_s cn52xx;
- struct cvmx_lmcx_rodt_comp_ctl_s cn52xxp1;
- struct cvmx_lmcx_rodt_comp_ctl_s cn56xx;
- struct cvmx_lmcx_rodt_comp_ctl_s cn56xxp1;
- struct cvmx_lmcx_rodt_comp_ctl_s cn58xx;
- struct cvmx_lmcx_rodt_comp_ctl_s cn58xxp1;
};
union cvmx_lmcx_rodt_ctl {
@@ -2860,17 +2461,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_rodt_ctl_s cn30xx;
- struct cvmx_lmcx_rodt_ctl_s cn31xx;
- struct cvmx_lmcx_rodt_ctl_s cn38xx;
- struct cvmx_lmcx_rodt_ctl_s cn38xxp2;
- struct cvmx_lmcx_rodt_ctl_s cn50xx;
- struct cvmx_lmcx_rodt_ctl_s cn52xx;
- struct cvmx_lmcx_rodt_ctl_s cn52xxp1;
- struct cvmx_lmcx_rodt_ctl_s cn56xx;
- struct cvmx_lmcx_rodt_ctl_s cn56xxp1;
- struct cvmx_lmcx_rodt_ctl_s cn58xx;
- struct cvmx_lmcx_rodt_ctl_s cn58xxp1;
};
union cvmx_lmcx_rodt_mask {
@@ -2896,13 +2486,6 @@
uint64_t rodt_d3_r1:8;
#endif
} s;
- struct cvmx_lmcx_rodt_mask_s cn61xx;
- struct cvmx_lmcx_rodt_mask_s cn63xx;
- struct cvmx_lmcx_rodt_mask_s cn63xxp1;
- struct cvmx_lmcx_rodt_mask_s cn66xx;
- struct cvmx_lmcx_rodt_mask_s cn68xx;
- struct cvmx_lmcx_rodt_mask_s cn68xxp1;
- struct cvmx_lmcx_rodt_mask_s cnf71xx;
};
union cvmx_lmcx_scramble_cfg0 {
@@ -2914,9 +2497,6 @@
uint64_t key:64;
#endif
} s;
- struct cvmx_lmcx_scramble_cfg0_s cn61xx;
- struct cvmx_lmcx_scramble_cfg0_s cn66xx;
- struct cvmx_lmcx_scramble_cfg0_s cnf71xx;
};
union cvmx_lmcx_scramble_cfg1 {
@@ -2928,9 +2508,6 @@
uint64_t key:64;
#endif
} s;
- struct cvmx_lmcx_scramble_cfg1_s cn61xx;
- struct cvmx_lmcx_scramble_cfg1_s cn66xx;
- struct cvmx_lmcx_scramble_cfg1_s cnf71xx;
};
union cvmx_lmcx_scrambled_fadr {
@@ -2952,9 +2529,6 @@
uint64_t reserved_36_63:28;
#endif
} s;
- struct cvmx_lmcx_scrambled_fadr_s cn61xx;
- struct cvmx_lmcx_scrambled_fadr_s cn66xx;
- struct cvmx_lmcx_scrambled_fadr_s cnf71xx;
};
union cvmx_lmcx_slot_ctl0 {
@@ -2974,13 +2548,6 @@
uint64_t reserved_24_63:40;
#endif
} s;
- struct cvmx_lmcx_slot_ctl0_s cn61xx;
- struct cvmx_lmcx_slot_ctl0_s cn63xx;
- struct cvmx_lmcx_slot_ctl0_s cn63xxp1;
- struct cvmx_lmcx_slot_ctl0_s cn66xx;
- struct cvmx_lmcx_slot_ctl0_s cn68xx;
- struct cvmx_lmcx_slot_ctl0_s cn68xxp1;
- struct cvmx_lmcx_slot_ctl0_s cnf71xx;
};
union cvmx_lmcx_slot_ctl1 {
@@ -3000,13 +2567,6 @@
uint64_t reserved_24_63:40;
#endif
} s;
- struct cvmx_lmcx_slot_ctl1_s cn61xx;
- struct cvmx_lmcx_slot_ctl1_s cn63xx;
- struct cvmx_lmcx_slot_ctl1_s cn63xxp1;
- struct cvmx_lmcx_slot_ctl1_s cn66xx;
- struct cvmx_lmcx_slot_ctl1_s cn68xx;
- struct cvmx_lmcx_slot_ctl1_s cn68xxp1;
- struct cvmx_lmcx_slot_ctl1_s cnf71xx;
};
union cvmx_lmcx_slot_ctl2 {
@@ -3026,13 +2586,6 @@
uint64_t reserved_24_63:40;
#endif
} s;
- struct cvmx_lmcx_slot_ctl2_s cn61xx;
- struct cvmx_lmcx_slot_ctl2_s cn63xx;
- struct cvmx_lmcx_slot_ctl2_s cn63xxp1;
- struct cvmx_lmcx_slot_ctl2_s cn66xx;
- struct cvmx_lmcx_slot_ctl2_s cn68xx;
- struct cvmx_lmcx_slot_ctl2_s cn68xxp1;
- struct cvmx_lmcx_slot_ctl2_s cnf71xx;
};
union cvmx_lmcx_timing_params0 {
@@ -3095,7 +2648,6 @@
uint64_t reserved_47_63:17;
#endif
} cn61xx;
- struct cvmx_lmcx_timing_params0_cn61xx cn63xx;
struct cvmx_lmcx_timing_params0_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_46_63:18;
@@ -3123,10 +2675,6 @@
uint64_t reserved_46_63:18;
#endif
} cn63xxp1;
- struct cvmx_lmcx_timing_params0_cn61xx cn66xx;
- struct cvmx_lmcx_timing_params0_cn61xx cn68xx;
- struct cvmx_lmcx_timing_params0_cn61xx cn68xxp1;
- struct cvmx_lmcx_timing_params0_cn61xx cnf71xx;
};
union cvmx_lmcx_timing_params1 {
@@ -3162,8 +2710,6 @@
uint64_t reserved_47_63:17;
#endif
} s;
- struct cvmx_lmcx_timing_params1_s cn61xx;
- struct cvmx_lmcx_timing_params1_s cn63xx;
struct cvmx_lmcx_timing_params1_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_46_63:18;
@@ -3193,10 +2739,6 @@
uint64_t reserved_46_63:18;
#endif
} cn63xxp1;
- struct cvmx_lmcx_timing_params1_s cn66xx;
- struct cvmx_lmcx_timing_params1_s cn68xx;
- struct cvmx_lmcx_timing_params1_s cn68xxp1;
- struct cvmx_lmcx_timing_params1_s cnf71xx;
};
union cvmx_lmcx_tro_ctl {
@@ -3212,13 +2754,6 @@
uint64_t reserved_33_63:31;
#endif
} s;
- struct cvmx_lmcx_tro_ctl_s cn61xx;
- struct cvmx_lmcx_tro_ctl_s cn63xx;
- struct cvmx_lmcx_tro_ctl_s cn63xxp1;
- struct cvmx_lmcx_tro_ctl_s cn66xx;
- struct cvmx_lmcx_tro_ctl_s cn68xx;
- struct cvmx_lmcx_tro_ctl_s cn68xxp1;
- struct cvmx_lmcx_tro_ctl_s cnf71xx;
};
union cvmx_lmcx_tro_stat {
@@ -3232,13 +2767,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_tro_stat_s cn61xx;
- struct cvmx_lmcx_tro_stat_s cn63xx;
- struct cvmx_lmcx_tro_stat_s cn63xxp1;
- struct cvmx_lmcx_tro_stat_s cn66xx;
- struct cvmx_lmcx_tro_stat_s cn68xx;
- struct cvmx_lmcx_tro_stat_s cn68xxp1;
- struct cvmx_lmcx_tro_stat_s cnf71xx;
};
union cvmx_lmcx_wlevel_ctl {
@@ -3260,8 +2788,6 @@
uint64_t reserved_22_63:42;
#endif
} s;
- struct cvmx_lmcx_wlevel_ctl_s cn61xx;
- struct cvmx_lmcx_wlevel_ctl_s cn63xx;
struct cvmx_lmcx_wlevel_ctl_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
@@ -3273,10 +2799,6 @@
uint64_t reserved_10_63:54;
#endif
} cn63xxp1;
- struct cvmx_lmcx_wlevel_ctl_s cn66xx;
- struct cvmx_lmcx_wlevel_ctl_s cn68xx;
- struct cvmx_lmcx_wlevel_ctl_s cn68xxp1;
- struct cvmx_lmcx_wlevel_ctl_s cnf71xx;
};
union cvmx_lmcx_wlevel_dbg {
@@ -3292,13 +2814,6 @@
uint64_t reserved_12_63:52;
#endif
} s;
- struct cvmx_lmcx_wlevel_dbg_s cn61xx;
- struct cvmx_lmcx_wlevel_dbg_s cn63xx;
- struct cvmx_lmcx_wlevel_dbg_s cn63xxp1;
- struct cvmx_lmcx_wlevel_dbg_s cn66xx;
- struct cvmx_lmcx_wlevel_dbg_s cn68xx;
- struct cvmx_lmcx_wlevel_dbg_s cn68xxp1;
- struct cvmx_lmcx_wlevel_dbg_s cnf71xx;
};
union cvmx_lmcx_wlevel_rankx {
@@ -3330,13 +2845,6 @@
uint64_t reserved_47_63:17;
#endif
} s;
- struct cvmx_lmcx_wlevel_rankx_s cn61xx;
- struct cvmx_lmcx_wlevel_rankx_s cn63xx;
- struct cvmx_lmcx_wlevel_rankx_s cn63xxp1;
- struct cvmx_lmcx_wlevel_rankx_s cn66xx;
- struct cvmx_lmcx_wlevel_rankx_s cn68xx;
- struct cvmx_lmcx_wlevel_rankx_s cn68xxp1;
- struct cvmx_lmcx_wlevel_rankx_s cnf71xx;
};
union cvmx_lmcx_wodt_ctl0 {
@@ -3363,7 +2871,6 @@
uint64_t reserved_32_63:32;
#endif
} cn30xx;
- struct cvmx_lmcx_wodt_ctl0_cn30xx cn31xx;
struct cvmx_lmcx_wodt_ctl0_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
@@ -3387,14 +2894,6 @@
uint64_t reserved_32_63:32;
#endif
} cn38xx;
- struct cvmx_lmcx_wodt_ctl0_cn38xx cn38xxp2;
- struct cvmx_lmcx_wodt_ctl0_cn38xx cn50xx;
- struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xx;
- struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xxp1;
- struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xx;
- struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xxp1;
- struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xx;
- struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xxp1;
};
union cvmx_lmcx_wodt_ctl1 {
@@ -3414,12 +2913,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_lmcx_wodt_ctl1_s cn30xx;
- struct cvmx_lmcx_wodt_ctl1_s cn31xx;
- struct cvmx_lmcx_wodt_ctl1_s cn52xx;
- struct cvmx_lmcx_wodt_ctl1_s cn52xxp1;
- struct cvmx_lmcx_wodt_ctl1_s cn56xx;
- struct cvmx_lmcx_wodt_ctl1_s cn56xxp1;
};
union cvmx_lmcx_wodt_mask {
@@ -3445,13 +2938,6 @@
uint64_t wodt_d3_r1:8;
#endif
} s;
- struct cvmx_lmcx_wodt_mask_s cn61xx;
- struct cvmx_lmcx_wodt_mask_s cn63xx;
- struct cvmx_lmcx_wodt_mask_s cn63xxp1;
- struct cvmx_lmcx_wodt_mask_s cn66xx;
- struct cvmx_lmcx_wodt_mask_s cn68xx;
- struct cvmx_lmcx_wodt_mask_s cn68xxp1;
- struct cvmx_lmcx_wodt_mask_s cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index 5196c04..4ad95d0 100644
--- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -188,7 +188,6 @@
uint64_t reserved_4_63:60;
#endif
} cn30xx;
- struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
struct cvmx_mio_boot_bist_stat_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63:61;
@@ -202,7 +201,6 @@
uint64_t reserved_3_63:61;
#endif
} cn38xx;
- struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
struct cvmx_mio_boot_bist_stat_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_6_63:58;
@@ -254,10 +252,6 @@
uint64_t reserved_4_63:60;
#endif
} cn52xxp1;
- struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
- struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
- struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
- struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
struct cvmx_mio_boot_bist_stat_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -276,7 +270,6 @@
uint64_t reserved_9_63:55;
#endif
} cn63xx;
- struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
struct cvmx_mio_boot_bist_stat_cn66xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
@@ -286,9 +279,6 @@
uint64_t reserved_10_63:54;
#endif
} cn66xx;
- struct cvmx_mio_boot_bist_stat_cn66xx cn68xx;
- struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1;
- struct cvmx_mio_boot_bist_stat_cn61xx cnf71xx;
};
union cvmx_mio_boot_comp {
@@ -311,10 +301,6 @@
uint64_t reserved_10_63:54;
#endif
} cn50xx;
- struct cvmx_mio_boot_comp_cn50xx cn52xx;
- struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
- struct cvmx_mio_boot_comp_cn50xx cn56xx;
- struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
struct cvmx_mio_boot_comp_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -326,12 +312,6 @@
uint64_t reserved_12_63:52;
#endif
} cn61xx;
- struct cvmx_mio_boot_comp_cn61xx cn63xx;
- struct cvmx_mio_boot_comp_cn61xx cn63xxp1;
- struct cvmx_mio_boot_comp_cn61xx cn66xx;
- struct cvmx_mio_boot_comp_cn61xx cn68xx;
- struct cvmx_mio_boot_comp_cn61xx cn68xxp1;
- struct cvmx_mio_boot_comp_cn61xx cnf71xx;
};
union cvmx_mio_boot_dma_cfgx {
@@ -361,17 +341,6 @@
uint64_t en:1;
#endif
} s;
- struct cvmx_mio_boot_dma_cfgx_s cn52xx;
- struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
- struct cvmx_mio_boot_dma_cfgx_s cn56xx;
- struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
- struct cvmx_mio_boot_dma_cfgx_s cn61xx;
- struct cvmx_mio_boot_dma_cfgx_s cn63xx;
- struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
- struct cvmx_mio_boot_dma_cfgx_s cn66xx;
- struct cvmx_mio_boot_dma_cfgx_s cn68xx;
- struct cvmx_mio_boot_dma_cfgx_s cn68xxp1;
- struct cvmx_mio_boot_dma_cfgx_s cnf71xx;
};
union cvmx_mio_boot_dma_intx {
@@ -387,17 +356,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_mio_boot_dma_intx_s cn52xx;
- struct cvmx_mio_boot_dma_intx_s cn52xxp1;
- struct cvmx_mio_boot_dma_intx_s cn56xx;
- struct cvmx_mio_boot_dma_intx_s cn56xxp1;
- struct cvmx_mio_boot_dma_intx_s cn61xx;
- struct cvmx_mio_boot_dma_intx_s cn63xx;
- struct cvmx_mio_boot_dma_intx_s cn63xxp1;
- struct cvmx_mio_boot_dma_intx_s cn66xx;
- struct cvmx_mio_boot_dma_intx_s cn68xx;
- struct cvmx_mio_boot_dma_intx_s cn68xxp1;
- struct cvmx_mio_boot_dma_intx_s cnf71xx;
};
union cvmx_mio_boot_dma_int_enx {
@@ -413,17 +371,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_mio_boot_dma_int_enx_s cn52xx;
- struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
- struct cvmx_mio_boot_dma_int_enx_s cn56xx;
- struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
- struct cvmx_mio_boot_dma_int_enx_s cn61xx;
- struct cvmx_mio_boot_dma_int_enx_s cn63xx;
- struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
- struct cvmx_mio_boot_dma_int_enx_s cn66xx;
- struct cvmx_mio_boot_dma_int_enx_s cn68xx;
- struct cvmx_mio_boot_dma_int_enx_s cn68xxp1;
- struct cvmx_mio_boot_dma_int_enx_s cnf71xx;
};
union cvmx_mio_boot_dma_timx {
@@ -463,17 +410,6 @@
uint64_t dmack_pi:1;
#endif
} s;
- struct cvmx_mio_boot_dma_timx_s cn52xx;
- struct cvmx_mio_boot_dma_timx_s cn52xxp1;
- struct cvmx_mio_boot_dma_timx_s cn56xx;
- struct cvmx_mio_boot_dma_timx_s cn56xxp1;
- struct cvmx_mio_boot_dma_timx_s cn61xx;
- struct cvmx_mio_boot_dma_timx_s cn63xx;
- struct cvmx_mio_boot_dma_timx_s cn63xxp1;
- struct cvmx_mio_boot_dma_timx_s cn66xx;
- struct cvmx_mio_boot_dma_timx_s cn68xx;
- struct cvmx_mio_boot_dma_timx_s cn68xxp1;
- struct cvmx_mio_boot_dma_timx_s cnf71xx;
};
union cvmx_mio_boot_err {
@@ -489,24 +425,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_mio_boot_err_s cn30xx;
- struct cvmx_mio_boot_err_s cn31xx;
- struct cvmx_mio_boot_err_s cn38xx;
- struct cvmx_mio_boot_err_s cn38xxp2;
- struct cvmx_mio_boot_err_s cn50xx;
- struct cvmx_mio_boot_err_s cn52xx;
- struct cvmx_mio_boot_err_s cn52xxp1;
- struct cvmx_mio_boot_err_s cn56xx;
- struct cvmx_mio_boot_err_s cn56xxp1;
- struct cvmx_mio_boot_err_s cn58xx;
- struct cvmx_mio_boot_err_s cn58xxp1;
- struct cvmx_mio_boot_err_s cn61xx;
- struct cvmx_mio_boot_err_s cn63xx;
- struct cvmx_mio_boot_err_s cn63xxp1;
- struct cvmx_mio_boot_err_s cn66xx;
- struct cvmx_mio_boot_err_s cn68xx;
- struct cvmx_mio_boot_err_s cn68xxp1;
- struct cvmx_mio_boot_err_s cnf71xx;
};
union cvmx_mio_boot_int {
@@ -522,24 +440,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_mio_boot_int_s cn30xx;
- struct cvmx_mio_boot_int_s cn31xx;
- struct cvmx_mio_boot_int_s cn38xx;
- struct cvmx_mio_boot_int_s cn38xxp2;
- struct cvmx_mio_boot_int_s cn50xx;
- struct cvmx_mio_boot_int_s cn52xx;
- struct cvmx_mio_boot_int_s cn52xxp1;
- struct cvmx_mio_boot_int_s cn56xx;
- struct cvmx_mio_boot_int_s cn56xxp1;
- struct cvmx_mio_boot_int_s cn58xx;
- struct cvmx_mio_boot_int_s cn58xxp1;
- struct cvmx_mio_boot_int_s cn61xx;
- struct cvmx_mio_boot_int_s cn63xx;
- struct cvmx_mio_boot_int_s cn63xxp1;
- struct cvmx_mio_boot_int_s cn66xx;
- struct cvmx_mio_boot_int_s cn68xx;
- struct cvmx_mio_boot_int_s cn68xxp1;
- struct cvmx_mio_boot_int_s cnf71xx;
};
union cvmx_mio_boot_loc_adr {
@@ -555,24 +455,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_boot_loc_adr_s cn30xx;
- struct cvmx_mio_boot_loc_adr_s cn31xx;
- struct cvmx_mio_boot_loc_adr_s cn38xx;
- struct cvmx_mio_boot_loc_adr_s cn38xxp2;
- struct cvmx_mio_boot_loc_adr_s cn50xx;
- struct cvmx_mio_boot_loc_adr_s cn52xx;
- struct cvmx_mio_boot_loc_adr_s cn52xxp1;
- struct cvmx_mio_boot_loc_adr_s cn56xx;
- struct cvmx_mio_boot_loc_adr_s cn56xxp1;
- struct cvmx_mio_boot_loc_adr_s cn58xx;
- struct cvmx_mio_boot_loc_adr_s cn58xxp1;
- struct cvmx_mio_boot_loc_adr_s cn61xx;
- struct cvmx_mio_boot_loc_adr_s cn63xx;
- struct cvmx_mio_boot_loc_adr_s cn63xxp1;
- struct cvmx_mio_boot_loc_adr_s cn66xx;
- struct cvmx_mio_boot_loc_adr_s cn68xx;
- struct cvmx_mio_boot_loc_adr_s cn68xxp1;
- struct cvmx_mio_boot_loc_adr_s cnf71xx;
};
union cvmx_mio_boot_loc_cfgx {
@@ -592,24 +474,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_mio_boot_loc_cfgx_s cn30xx;
- struct cvmx_mio_boot_loc_cfgx_s cn31xx;
- struct cvmx_mio_boot_loc_cfgx_s cn38xx;
- struct cvmx_mio_boot_loc_cfgx_s cn38xxp2;
- struct cvmx_mio_boot_loc_cfgx_s cn50xx;
- struct cvmx_mio_boot_loc_cfgx_s cn52xx;
- struct cvmx_mio_boot_loc_cfgx_s cn52xxp1;
- struct cvmx_mio_boot_loc_cfgx_s cn56xx;
- struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
- struct cvmx_mio_boot_loc_cfgx_s cn58xx;
- struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
- struct cvmx_mio_boot_loc_cfgx_s cn61xx;
- struct cvmx_mio_boot_loc_cfgx_s cn63xx;
- struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
- struct cvmx_mio_boot_loc_cfgx_s cn66xx;
- struct cvmx_mio_boot_loc_cfgx_s cn68xx;
- struct cvmx_mio_boot_loc_cfgx_s cn68xxp1;
- struct cvmx_mio_boot_loc_cfgx_s cnf71xx;
};
union cvmx_mio_boot_loc_dat {
@@ -621,24 +485,6 @@
uint64_t data:64;
#endif
} s;
- struct cvmx_mio_boot_loc_dat_s cn30xx;
- struct cvmx_mio_boot_loc_dat_s cn31xx;
- struct cvmx_mio_boot_loc_dat_s cn38xx;
- struct cvmx_mio_boot_loc_dat_s cn38xxp2;
- struct cvmx_mio_boot_loc_dat_s cn50xx;
- struct cvmx_mio_boot_loc_dat_s cn52xx;
- struct cvmx_mio_boot_loc_dat_s cn52xxp1;
- struct cvmx_mio_boot_loc_dat_s cn56xx;
- struct cvmx_mio_boot_loc_dat_s cn56xxp1;
- struct cvmx_mio_boot_loc_dat_s cn58xx;
- struct cvmx_mio_boot_loc_dat_s cn58xxp1;
- struct cvmx_mio_boot_loc_dat_s cn61xx;
- struct cvmx_mio_boot_loc_dat_s cn63xx;
- struct cvmx_mio_boot_loc_dat_s cn63xxp1;
- struct cvmx_mio_boot_loc_dat_s cn66xx;
- struct cvmx_mio_boot_loc_dat_s cn68xx;
- struct cvmx_mio_boot_loc_dat_s cn68xxp1;
- struct cvmx_mio_boot_loc_dat_s cnf71xx;
};
union cvmx_mio_boot_pin_defs {
@@ -737,12 +583,6 @@
uint64_t reserved_32_63:32;
#endif
} cn61xx;
- struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
- struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
- struct cvmx_mio_boot_pin_defs_cn52xx cn66xx;
- struct cvmx_mio_boot_pin_defs_cn52xx cn68xx;
- struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1;
- struct cvmx_mio_boot_pin_defs_cn61xx cnf71xx;
};
union cvmx_mio_boot_reg_cfgx {
@@ -803,7 +643,6 @@
uint64_t reserved_37_63:27;
#endif
} cn30xx;
- struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx;
struct cvmx_mio_boot_reg_cfgx_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
@@ -821,7 +660,6 @@
uint64_t reserved_32_63:32;
#endif
} cn38xx;
- struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2;
struct cvmx_mio_boot_reg_cfgx_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_42_63:22;
@@ -851,19 +689,6 @@
uint64_t reserved_42_63:22;
#endif
} cn50xx;
- struct cvmx_mio_boot_reg_cfgx_s cn52xx;
- struct cvmx_mio_boot_reg_cfgx_s cn52xxp1;
- struct cvmx_mio_boot_reg_cfgx_s cn56xx;
- struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
- struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
- struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
- struct cvmx_mio_boot_reg_cfgx_s cn61xx;
- struct cvmx_mio_boot_reg_cfgx_s cn63xx;
- struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
- struct cvmx_mio_boot_reg_cfgx_s cn66xx;
- struct cvmx_mio_boot_reg_cfgx_s cn68xx;
- struct cvmx_mio_boot_reg_cfgx_s cn68xxp1;
- struct cvmx_mio_boot_reg_cfgx_s cnf71xx;
};
union cvmx_mio_boot_reg_timx {
@@ -899,8 +724,6 @@
uint64_t pagem:1;
#endif
} s;
- struct cvmx_mio_boot_reg_timx_s cn30xx;
- struct cvmx_mio_boot_reg_timx_s cn31xx;
struct cvmx_mio_boot_reg_timx_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t pagem:1;
@@ -932,21 +755,6 @@
uint64_t pagem:1;
#endif
} cn38xx;
- struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2;
- struct cvmx_mio_boot_reg_timx_s cn50xx;
- struct cvmx_mio_boot_reg_timx_s cn52xx;
- struct cvmx_mio_boot_reg_timx_s cn52xxp1;
- struct cvmx_mio_boot_reg_timx_s cn56xx;
- struct cvmx_mio_boot_reg_timx_s cn56xxp1;
- struct cvmx_mio_boot_reg_timx_s cn58xx;
- struct cvmx_mio_boot_reg_timx_s cn58xxp1;
- struct cvmx_mio_boot_reg_timx_s cn61xx;
- struct cvmx_mio_boot_reg_timx_s cn63xx;
- struct cvmx_mio_boot_reg_timx_s cn63xxp1;
- struct cvmx_mio_boot_reg_timx_s cn66xx;
- struct cvmx_mio_boot_reg_timx_s cn68xx;
- struct cvmx_mio_boot_reg_timx_s cn68xxp1;
- struct cvmx_mio_boot_reg_timx_s cnf71xx;
};
union cvmx_mio_boot_thr {
@@ -981,23 +789,6 @@
uint64_t reserved_14_63:50;
#endif
} cn30xx;
- struct cvmx_mio_boot_thr_cn30xx cn31xx;
- struct cvmx_mio_boot_thr_cn30xx cn38xx;
- struct cvmx_mio_boot_thr_cn30xx cn38xxp2;
- struct cvmx_mio_boot_thr_cn30xx cn50xx;
- struct cvmx_mio_boot_thr_s cn52xx;
- struct cvmx_mio_boot_thr_s cn52xxp1;
- struct cvmx_mio_boot_thr_s cn56xx;
- struct cvmx_mio_boot_thr_s cn56xxp1;
- struct cvmx_mio_boot_thr_cn30xx cn58xx;
- struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
- struct cvmx_mio_boot_thr_s cn61xx;
- struct cvmx_mio_boot_thr_s cn63xx;
- struct cvmx_mio_boot_thr_s cn63xxp1;
- struct cvmx_mio_boot_thr_s cn66xx;
- struct cvmx_mio_boot_thr_s cn68xx;
- struct cvmx_mio_boot_thr_s cn68xxp1;
- struct cvmx_mio_boot_thr_s cnf71xx;
};
union cvmx_mio_emm_buf_dat {
@@ -1009,8 +800,6 @@
uint64_t dat:64;
#endif
} s;
- struct cvmx_mio_emm_buf_dat_s cn61xx;
- struct cvmx_mio_emm_buf_dat_s cnf71xx;
};
union cvmx_mio_emm_buf_idx {
@@ -1030,8 +819,6 @@
uint64_t reserved_17_63:47;
#endif
} s;
- struct cvmx_mio_emm_buf_idx_s cn61xx;
- struct cvmx_mio_emm_buf_idx_s cnf71xx;
};
union cvmx_mio_emm_cfg {
@@ -1049,8 +836,6 @@
uint64_t reserved_17_63:47;
#endif
} s;
- struct cvmx_mio_emm_cfg_s cn61xx;
- struct cvmx_mio_emm_cfg_s cnf71xx;
};
union cvmx_mio_emm_cmd {
@@ -1082,8 +867,6 @@
uint64_t reserved_62_63:2;
#endif
} s;
- struct cvmx_mio_emm_cmd_s cn61xx;
- struct cvmx_mio_emm_cmd_s cnf71xx;
};
union cvmx_mio_emm_dma {
@@ -1115,8 +898,6 @@
uint64_t reserved_62_63:2;
#endif
} s;
- struct cvmx_mio_emm_dma_s cn61xx;
- struct cvmx_mio_emm_dma_s cnf71xx;
};
union cvmx_mio_emm_int {
@@ -1142,8 +923,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_mio_emm_int_s cn61xx;
- struct cvmx_mio_emm_int_s cnf71xx;
};
union cvmx_mio_emm_int_en {
@@ -1169,8 +948,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_mio_emm_int_en_s cn61xx;
- struct cvmx_mio_emm_int_en_s cnf71xx;
};
union cvmx_mio_emm_modex {
@@ -1196,8 +973,6 @@
uint64_t reserved_49_63:15;
#endif
} s;
- struct cvmx_mio_emm_modex_s cn61xx;
- struct cvmx_mio_emm_modex_s cnf71xx;
};
union cvmx_mio_emm_rca {
@@ -1211,8 +986,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_mio_emm_rca_s cn61xx;
- struct cvmx_mio_emm_rca_s cnf71xx;
};
union cvmx_mio_emm_rsp_hi {
@@ -1224,8 +997,6 @@
uint64_t dat:64;
#endif
} s;
- struct cvmx_mio_emm_rsp_hi_s cn61xx;
- struct cvmx_mio_emm_rsp_hi_s cnf71xx;
};
union cvmx_mio_emm_rsp_lo {
@@ -1237,8 +1008,6 @@
uint64_t dat:64;
#endif
} s;
- struct cvmx_mio_emm_rsp_lo_s cn61xx;
- struct cvmx_mio_emm_rsp_lo_s cnf71xx;
};
union cvmx_mio_emm_rsp_sts {
@@ -1298,8 +1067,6 @@
uint64_t reserved_62_63:2;
#endif
} s;
- struct cvmx_mio_emm_rsp_sts_s cn61xx;
- struct cvmx_mio_emm_rsp_sts_s cnf71xx;
};
union cvmx_mio_emm_sample {
@@ -1317,8 +1084,6 @@
uint64_t reserved_26_63:38;
#endif
} s;
- struct cvmx_mio_emm_sample_s cn61xx;
- struct cvmx_mio_emm_sample_s cnf71xx;
};
union cvmx_mio_emm_sts_mask {
@@ -1332,8 +1097,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_mio_emm_sts_mask_s cn61xx;
- struct cvmx_mio_emm_sts_mask_s cnf71xx;
};
union cvmx_mio_emm_switch {
@@ -1371,8 +1134,6 @@
uint64_t reserved_62_63:2;
#endif
} s;
- struct cvmx_mio_emm_switch_s cn61xx;
- struct cvmx_mio_emm_switch_s cnf71xx;
};
union cvmx_mio_emm_wdog {
@@ -1386,8 +1147,6 @@
uint64_t reserved_26_63:38;
#endif
} s;
- struct cvmx_mio_emm_wdog_s cn61xx;
- struct cvmx_mio_emm_wdog_s cnf71xx;
};
union cvmx_mio_fus_bnk_datx {
@@ -1399,20 +1158,6 @@
uint64_t dat:64;
#endif
} s;
- struct cvmx_mio_fus_bnk_datx_s cn50xx;
- struct cvmx_mio_fus_bnk_datx_s cn52xx;
- struct cvmx_mio_fus_bnk_datx_s cn52xxp1;
- struct cvmx_mio_fus_bnk_datx_s cn56xx;
- struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
- struct cvmx_mio_fus_bnk_datx_s cn58xx;
- struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
- struct cvmx_mio_fus_bnk_datx_s cn61xx;
- struct cvmx_mio_fus_bnk_datx_s cn63xx;
- struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
- struct cvmx_mio_fus_bnk_datx_s cn66xx;
- struct cvmx_mio_fus_bnk_datx_s cn68xx;
- struct cvmx_mio_fus_bnk_datx_s cn68xxp1;
- struct cvmx_mio_fus_bnk_datx_s cnf71xx;
};
union cvmx_mio_fus_dat0 {
@@ -1426,24 +1171,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_mio_fus_dat0_s cn30xx;
- struct cvmx_mio_fus_dat0_s cn31xx;
- struct cvmx_mio_fus_dat0_s cn38xx;
- struct cvmx_mio_fus_dat0_s cn38xxp2;
- struct cvmx_mio_fus_dat0_s cn50xx;
- struct cvmx_mio_fus_dat0_s cn52xx;
- struct cvmx_mio_fus_dat0_s cn52xxp1;
- struct cvmx_mio_fus_dat0_s cn56xx;
- struct cvmx_mio_fus_dat0_s cn56xxp1;
- struct cvmx_mio_fus_dat0_s cn58xx;
- struct cvmx_mio_fus_dat0_s cn58xxp1;
- struct cvmx_mio_fus_dat0_s cn61xx;
- struct cvmx_mio_fus_dat0_s cn63xx;
- struct cvmx_mio_fus_dat0_s cn63xxp1;
- struct cvmx_mio_fus_dat0_s cn66xx;
- struct cvmx_mio_fus_dat0_s cn68xx;
- struct cvmx_mio_fus_dat0_s cn68xxp1;
- struct cvmx_mio_fus_dat0_s cnf71xx;
};
union cvmx_mio_fus_dat1 {
@@ -1457,24 +1184,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_mio_fus_dat1_s cn30xx;
- struct cvmx_mio_fus_dat1_s cn31xx;
- struct cvmx_mio_fus_dat1_s cn38xx;
- struct cvmx_mio_fus_dat1_s cn38xxp2;
- struct cvmx_mio_fus_dat1_s cn50xx;
- struct cvmx_mio_fus_dat1_s cn52xx;
- struct cvmx_mio_fus_dat1_s cn52xxp1;
- struct cvmx_mio_fus_dat1_s cn56xx;
- struct cvmx_mio_fus_dat1_s cn56xxp1;
- struct cvmx_mio_fus_dat1_s cn58xx;
- struct cvmx_mio_fus_dat1_s cn58xxp1;
- struct cvmx_mio_fus_dat1_s cn61xx;
- struct cvmx_mio_fus_dat1_s cn63xx;
- struct cvmx_mio_fus_dat1_s cn63xxp1;
- struct cvmx_mio_fus_dat1_s cn66xx;
- struct cvmx_mio_fus_dat1_s cn68xx;
- struct cvmx_mio_fus_dat1_s cn68xxp1;
- struct cvmx_mio_fus_dat1_s cnf71xx;
};
union cvmx_mio_fus_dat2 {
@@ -1591,7 +1300,6 @@
uint64_t reserved_29_63:35;
#endif
} cn38xx;
- struct cvmx_mio_fus_dat2_cn38xx cn38xxp2;
struct cvmx_mio_fus_dat2_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63:30;
@@ -1654,7 +1362,6 @@
uint64_t reserved_34_63:30;
#endif
} cn52xx;
- struct cvmx_mio_fus_dat2_cn52xx cn52xxp1;
struct cvmx_mio_fus_dat2_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_34_63:30;
@@ -1686,7 +1393,6 @@
uint64_t reserved_34_63:30;
#endif
} cn56xx;
- struct cvmx_mio_fus_dat2_cn56xx cn56xxp1;
struct cvmx_mio_fus_dat2_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_30_63:34;
@@ -1710,7 +1416,6 @@
uint64_t reserved_30_63:34;
#endif
} cn58xx;
- struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
struct cvmx_mio_fus_dat2_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63:16;
@@ -1775,7 +1480,6 @@
uint64_t reserved_35_63:29;
#endif
} cn63xx;
- struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
struct cvmx_mio_fus_dat2_cn66xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63:16;
@@ -1840,7 +1544,6 @@
uint64_t reserved_37_63:27;
#endif
} cn68xx;
- struct cvmx_mio_fus_dat2_cn68xx cn68xxp1;
struct cvmx_mio_fus_dat2_cn70xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63:16;
@@ -1874,7 +1577,6 @@
uint64_t reserved_48_63:16;
#endif
} cn70xx;
- struct cvmx_mio_fus_dat2_cn70xx cn70xxp1;
struct cvmx_mio_fus_dat2_cn73xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_59_63:5;
@@ -1986,8 +1688,6 @@
uint64_t reserved_59_63:5;
#endif
} cn78xxp2;
- struct cvmx_mio_fus_dat2_cn61xx cnf71xx;
- struct cvmx_mio_fus_dat2_cn73xx cnf75xx;
};
union cvmx_mio_fus_dat3 {
@@ -2115,13 +1815,6 @@
uint64_t reserved_29_63:35;
#endif
} cn38xxp2;
- struct cvmx_mio_fus_dat3_cn38xx cn50xx;
- struct cvmx_mio_fus_dat3_cn38xx cn52xx;
- struct cvmx_mio_fus_dat3_cn38xx cn52xxp1;
- struct cvmx_mio_fus_dat3_cn38xx cn56xx;
- struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
- struct cvmx_mio_fus_dat3_cn38xx cn58xx;
- struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
struct cvmx_mio_fus_dat3_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_58_63:6;
@@ -2163,11 +1856,6 @@
uint64_t reserved_58_63:6;
#endif
} cn61xx;
- struct cvmx_mio_fus_dat3_cn61xx cn63xx;
- struct cvmx_mio_fus_dat3_cn61xx cn63xxp1;
- struct cvmx_mio_fus_dat3_cn61xx cn66xx;
- struct cvmx_mio_fus_dat3_cn61xx cn68xx;
- struct cvmx_mio_fus_dat3_cn61xx cn68xxp1;
struct cvmx_mio_fus_dat3_cn70xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t ema0:6;
@@ -2352,8 +2040,6 @@
uint64_t ema0:6;
#endif
} cn78xx;
- struct cvmx_mio_fus_dat3_cn73xx cn78xxp2;
- struct cvmx_mio_fus_dat3_cn61xx cnf71xx;
struct cvmx_mio_fus_dat3_cnf75xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t ema0:6;
@@ -2418,11 +2104,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_mio_fus_ema_s cn50xx;
- struct cvmx_mio_fus_ema_s cn52xx;
- struct cvmx_mio_fus_ema_s cn52xxp1;
- struct cvmx_mio_fus_ema_s cn56xx;
- struct cvmx_mio_fus_ema_s cn56xxp1;
struct cvmx_mio_fus_ema_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
@@ -2432,14 +2113,6 @@
uint64_t reserved_2_63:62;
#endif
} cn58xx;
- struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
- struct cvmx_mio_fus_ema_s cn61xx;
- struct cvmx_mio_fus_ema_s cn63xx;
- struct cvmx_mio_fus_ema_s cn63xxp1;
- struct cvmx_mio_fus_ema_s cn66xx;
- struct cvmx_mio_fus_ema_s cn68xx;
- struct cvmx_mio_fus_ema_s cn68xxp1;
- struct cvmx_mio_fus_ema_s cnf71xx;
};
union cvmx_mio_fus_pdf {
@@ -2451,19 +2124,6 @@
uint64_t pdf:64;
#endif
} s;
- struct cvmx_mio_fus_pdf_s cn50xx;
- struct cvmx_mio_fus_pdf_s cn52xx;
- struct cvmx_mio_fus_pdf_s cn52xxp1;
- struct cvmx_mio_fus_pdf_s cn56xx;
- struct cvmx_mio_fus_pdf_s cn56xxp1;
- struct cvmx_mio_fus_pdf_s cn58xx;
- struct cvmx_mio_fus_pdf_s cn61xx;
- struct cvmx_mio_fus_pdf_s cn63xx;
- struct cvmx_mio_fus_pdf_s cn63xxp1;
- struct cvmx_mio_fus_pdf_s cn66xx;
- struct cvmx_mio_fus_pdf_s cn68xx;
- struct cvmx_mio_fus_pdf_s cn68xxp1;
- struct cvmx_mio_fus_pdf_s cnf71xx;
};
union cvmx_mio_fus_pll {
@@ -2504,12 +2164,6 @@
uint64_t reserved_2_63:62;
#endif
} cn50xx;
- struct cvmx_mio_fus_pll_cn50xx cn52xx;
- struct cvmx_mio_fus_pll_cn50xx cn52xxp1;
- struct cvmx_mio_fus_pll_cn50xx cn56xx;
- struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
- struct cvmx_mio_fus_pll_cn50xx cn58xx;
- struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
struct cvmx_mio_fus_pll_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_8_63:56;
@@ -2529,12 +2183,6 @@
uint64_t reserved_8_63:56;
#endif
} cn61xx;
- struct cvmx_mio_fus_pll_cn61xx cn63xx;
- struct cvmx_mio_fus_pll_cn61xx cn63xxp1;
- struct cvmx_mio_fus_pll_cn61xx cn66xx;
- struct cvmx_mio_fus_pll_s cn68xx;
- struct cvmx_mio_fus_pll_s cn68xxp1;
- struct cvmx_mio_fus_pll_cn61xx cnf71xx;
};
union cvmx_mio_fus_prog {
@@ -2559,23 +2207,6 @@
uint64_t reserved_1_63:63;
#endif
} cn30xx;
- struct cvmx_mio_fus_prog_cn30xx cn31xx;
- struct cvmx_mio_fus_prog_cn30xx cn38xx;
- struct cvmx_mio_fus_prog_cn30xx cn38xxp2;
- struct cvmx_mio_fus_prog_cn30xx cn50xx;
- struct cvmx_mio_fus_prog_cn30xx cn52xx;
- struct cvmx_mio_fus_prog_cn30xx cn52xxp1;
- struct cvmx_mio_fus_prog_cn30xx cn56xx;
- struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
- struct cvmx_mio_fus_prog_cn30xx cn58xx;
- struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
- struct cvmx_mio_fus_prog_s cn61xx;
- struct cvmx_mio_fus_prog_s cn63xx;
- struct cvmx_mio_fus_prog_s cn63xxp1;
- struct cvmx_mio_fus_prog_s cn66xx;
- struct cvmx_mio_fus_prog_s cn68xx;
- struct cvmx_mio_fus_prog_s cn68xxp1;
- struct cvmx_mio_fus_prog_s cnf71xx;
};
union cvmx_mio_fus_prog_times {
@@ -2614,12 +2245,6 @@
uint64_t reserved_33_63:31;
#endif
} cn50xx;
- struct cvmx_mio_fus_prog_times_cn50xx cn52xx;
- struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1;
- struct cvmx_mio_fus_prog_times_cn50xx cn56xx;
- struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
- struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
- struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
struct cvmx_mio_fus_prog_times_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_35_63:29;
@@ -2641,12 +2266,6 @@
uint64_t reserved_35_63:29;
#endif
} cn61xx;
- struct cvmx_mio_fus_prog_times_cn61xx cn63xx;
- struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1;
- struct cvmx_mio_fus_prog_times_cn61xx cn66xx;
- struct cvmx_mio_fus_prog_times_cn61xx cn68xx;
- struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1;
- struct cvmx_mio_fus_prog_times_cn61xx cnf71xx;
};
union cvmx_mio_fus_rcmd {
@@ -2691,23 +2310,6 @@
uint64_t reserved_24_63:40;
#endif
} cn30xx;
- struct cvmx_mio_fus_rcmd_cn30xx cn31xx;
- struct cvmx_mio_fus_rcmd_cn30xx cn38xx;
- struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2;
- struct cvmx_mio_fus_rcmd_cn30xx cn50xx;
- struct cvmx_mio_fus_rcmd_s cn52xx;
- struct cvmx_mio_fus_rcmd_s cn52xxp1;
- struct cvmx_mio_fus_rcmd_s cn56xx;
- struct cvmx_mio_fus_rcmd_s cn56xxp1;
- struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
- struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
- struct cvmx_mio_fus_rcmd_s cn61xx;
- struct cvmx_mio_fus_rcmd_s cn63xx;
- struct cvmx_mio_fus_rcmd_s cn63xxp1;
- struct cvmx_mio_fus_rcmd_s cn66xx;
- struct cvmx_mio_fus_rcmd_s cn68xx;
- struct cvmx_mio_fus_rcmd_s cn68xxp1;
- struct cvmx_mio_fus_rcmd_s cnf71xx;
};
union cvmx_mio_fus_read_times {
@@ -2729,13 +2331,6 @@
uint64_t reserved_26_63:38;
#endif
} s;
- struct cvmx_mio_fus_read_times_s cn61xx;
- struct cvmx_mio_fus_read_times_s cn63xx;
- struct cvmx_mio_fus_read_times_s cn63xxp1;
- struct cvmx_mio_fus_read_times_s cn66xx;
- struct cvmx_mio_fus_read_times_s cn68xx;
- struct cvmx_mio_fus_read_times_s cn68xxp1;
- struct cvmx_mio_fus_read_times_s cnf71xx;
};
union cvmx_mio_fus_repair_res0 {
@@ -2755,13 +2350,6 @@
uint64_t reserved_55_63:9;
#endif
} s;
- struct cvmx_mio_fus_repair_res0_s cn61xx;
- struct cvmx_mio_fus_repair_res0_s cn63xx;
- struct cvmx_mio_fus_repair_res0_s cn63xxp1;
- struct cvmx_mio_fus_repair_res0_s cn66xx;
- struct cvmx_mio_fus_repair_res0_s cn68xx;
- struct cvmx_mio_fus_repair_res0_s cn68xxp1;
- struct cvmx_mio_fus_repair_res0_s cnf71xx;
};
union cvmx_mio_fus_repair_res1 {
@@ -2779,13 +2367,6 @@
uint64_t reserved_54_63:10;
#endif
} s;
- struct cvmx_mio_fus_repair_res1_s cn61xx;
- struct cvmx_mio_fus_repair_res1_s cn63xx;
- struct cvmx_mio_fus_repair_res1_s cn63xxp1;
- struct cvmx_mio_fus_repair_res1_s cn66xx;
- struct cvmx_mio_fus_repair_res1_s cn68xx;
- struct cvmx_mio_fus_repair_res1_s cn68xxp1;
- struct cvmx_mio_fus_repair_res1_s cnf71xx;
};
union cvmx_mio_fus_repair_res2 {
@@ -2799,13 +2380,6 @@
uint64_t reserved_18_63:46;
#endif
} s;
- struct cvmx_mio_fus_repair_res2_s cn61xx;
- struct cvmx_mio_fus_repair_res2_s cn63xx;
- struct cvmx_mio_fus_repair_res2_s cn63xxp1;
- struct cvmx_mio_fus_repair_res2_s cn66xx;
- struct cvmx_mio_fus_repair_res2_s cn68xx;
- struct cvmx_mio_fus_repair_res2_s cn68xxp1;
- struct cvmx_mio_fus_repair_res2_s cnf71xx;
};
union cvmx_mio_fus_spr_repair_res {
@@ -2823,23 +2397,6 @@
uint64_t reserved_42_63:22;
#endif
} s;
- struct cvmx_mio_fus_spr_repair_res_s cn30xx;
- struct cvmx_mio_fus_spr_repair_res_s cn31xx;
- struct cvmx_mio_fus_spr_repair_res_s cn38xx;
- struct cvmx_mio_fus_spr_repair_res_s cn50xx;
- struct cvmx_mio_fus_spr_repair_res_s cn52xx;
- struct cvmx_mio_fus_spr_repair_res_s cn52xxp1;
- struct cvmx_mio_fus_spr_repair_res_s cn56xx;
- struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
- struct cvmx_mio_fus_spr_repair_res_s cn58xx;
- struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
- struct cvmx_mio_fus_spr_repair_res_s cn61xx;
- struct cvmx_mio_fus_spr_repair_res_s cn63xx;
- struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
- struct cvmx_mio_fus_spr_repair_res_s cn66xx;
- struct cvmx_mio_fus_spr_repair_res_s cn68xx;
- struct cvmx_mio_fus_spr_repair_res_s cn68xxp1;
- struct cvmx_mio_fus_spr_repair_res_s cnf71xx;
};
union cvmx_mio_fus_spr_repair_sum {
@@ -2853,23 +2410,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_fus_spr_repair_sum_s cn30xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn31xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn38xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn50xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn52xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1;
- struct cvmx_mio_fus_spr_repair_sum_s cn56xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
- struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
- struct cvmx_mio_fus_spr_repair_sum_s cn61xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
- struct cvmx_mio_fus_spr_repair_sum_s cn66xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn68xx;
- struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1;
- struct cvmx_mio_fus_spr_repair_sum_s cnf71xx;
};
union cvmx_mio_fus_tgg {
@@ -2883,9 +2423,6 @@
uint64_t val:1;
#endif
} s;
- struct cvmx_mio_fus_tgg_s cn61xx;
- struct cvmx_mio_fus_tgg_s cn66xx;
- struct cvmx_mio_fus_tgg_s cnf71xx;
};
union cvmx_mio_fus_unlock {
@@ -2899,8 +2436,6 @@
uint64_t reserved_24_63:40;
#endif
} s;
- struct cvmx_mio_fus_unlock_s cn30xx;
- struct cvmx_mio_fus_unlock_s cn31xx;
};
union cvmx_mio_fus_wadr {
@@ -2914,10 +2449,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_mio_fus_wadr_s cn30xx;
- struct cvmx_mio_fus_wadr_s cn31xx;
- struct cvmx_mio_fus_wadr_s cn38xx;
- struct cvmx_mio_fus_wadr_s cn38xxp2;
struct cvmx_mio_fus_wadr_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
@@ -2936,11 +2467,6 @@
uint64_t reserved_3_63:61;
#endif
} cn52xx;
- struct cvmx_mio_fus_wadr_cn52xx cn52xxp1;
- struct cvmx_mio_fus_wadr_cn52xx cn56xx;
- struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
- struct cvmx_mio_fus_wadr_cn50xx cn58xx;
- struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
struct cvmx_mio_fus_wadr_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_4_63:60;
@@ -2950,12 +2476,6 @@
uint64_t reserved_4_63:60;
#endif
} cn61xx;
- struct cvmx_mio_fus_wadr_cn61xx cn63xx;
- struct cvmx_mio_fus_wadr_cn61xx cn63xxp1;
- struct cvmx_mio_fus_wadr_cn61xx cn66xx;
- struct cvmx_mio_fus_wadr_cn61xx cn68xx;
- struct cvmx_mio_fus_wadr_cn61xx cn68xxp1;
- struct cvmx_mio_fus_wadr_cn61xx cnf71xx;
};
union cvmx_mio_gpio_comp {
@@ -2971,13 +2491,6 @@
uint64_t reserved_12_63:52;
#endif
} s;
- struct cvmx_mio_gpio_comp_s cn61xx;
- struct cvmx_mio_gpio_comp_s cn63xx;
- struct cvmx_mio_gpio_comp_s cn63xxp1;
- struct cvmx_mio_gpio_comp_s cn66xx;
- struct cvmx_mio_gpio_comp_s cn68xx;
- struct cvmx_mio_gpio_comp_s cn68xxp1;
- struct cvmx_mio_gpio_comp_s cnf71xx;
};
union cvmx_mio_ndf_dma_cfg {
@@ -3007,14 +2520,6 @@
uint64_t en:1;
#endif
} s;
- struct cvmx_mio_ndf_dma_cfg_s cn52xx;
- struct cvmx_mio_ndf_dma_cfg_s cn61xx;
- struct cvmx_mio_ndf_dma_cfg_s cn63xx;
- struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
- struct cvmx_mio_ndf_dma_cfg_s cn66xx;
- struct cvmx_mio_ndf_dma_cfg_s cn68xx;
- struct cvmx_mio_ndf_dma_cfg_s cn68xxp1;
- struct cvmx_mio_ndf_dma_cfg_s cnf71xx;
};
union cvmx_mio_ndf_dma_int {
@@ -3028,14 +2533,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_ndf_dma_int_s cn52xx;
- struct cvmx_mio_ndf_dma_int_s cn61xx;
- struct cvmx_mio_ndf_dma_int_s cn63xx;
- struct cvmx_mio_ndf_dma_int_s cn63xxp1;
- struct cvmx_mio_ndf_dma_int_s cn66xx;
- struct cvmx_mio_ndf_dma_int_s cn68xx;
- struct cvmx_mio_ndf_dma_int_s cn68xxp1;
- struct cvmx_mio_ndf_dma_int_s cnf71xx;
};
union cvmx_mio_ndf_dma_int_en {
@@ -3049,14 +2546,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_ndf_dma_int_en_s cn52xx;
- struct cvmx_mio_ndf_dma_int_en_s cn61xx;
- struct cvmx_mio_ndf_dma_int_en_s cn63xx;
- struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
- struct cvmx_mio_ndf_dma_int_en_s cn66xx;
- struct cvmx_mio_ndf_dma_int_en_s cn68xx;
- struct cvmx_mio_ndf_dma_int_en_s cn68xxp1;
- struct cvmx_mio_ndf_dma_int_en_s cnf71xx;
};
union cvmx_mio_pll_ctl {
@@ -3070,8 +2559,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_mio_pll_ctl_s cn30xx;
- struct cvmx_mio_pll_ctl_s cn31xx;
};
union cvmx_mio_pll_setting {
@@ -3085,8 +2572,6 @@
uint64_t reserved_17_63:47;
#endif
} s;
- struct cvmx_mio_pll_setting_s cn30xx;
- struct cvmx_mio_pll_setting_s cn31xx;
};
union cvmx_mio_ptp_ckout_hi_incr {
@@ -3100,10 +2585,6 @@
uint64_t nanosec:32;
#endif
} s;
- struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx;
- struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx;
- struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx;
- struct cvmx_mio_ptp_ckout_hi_incr_s cnf71xx;
};
union cvmx_mio_ptp_ckout_lo_incr {
@@ -3117,10 +2598,6 @@
uint64_t nanosec:32;
#endif
} s;
- struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx;
- struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx;
- struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx;
- struct cvmx_mio_ptp_ckout_lo_incr_s cnf71xx;
};
union cvmx_mio_ptp_ckout_thresh_hi {
@@ -3132,10 +2609,6 @@
uint64_t nanosec:64;
#endif
} s;
- struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx;
- struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx;
- struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx;
- struct cvmx_mio_ptp_ckout_thresh_hi_s cnf71xx;
};
union cvmx_mio_ptp_ckout_thresh_lo {
@@ -3149,10 +2622,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx;
- struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx;
- struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx;
- struct cvmx_mio_ptp_ckout_thresh_lo_s cnf71xx;
};
union cvmx_mio_ptp_clock_cfg {
@@ -3202,7 +2671,6 @@
uint64_t reserved_42_63:22;
#endif
} s;
- struct cvmx_mio_ptp_clock_cfg_s cn61xx;
struct cvmx_mio_ptp_clock_cfg_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
@@ -3228,7 +2696,6 @@
uint64_t reserved_24_63:40;
#endif
} cn63xx;
- struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;
struct cvmx_mio_ptp_clock_cfg_cn66xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_40_63:24;
@@ -3270,9 +2737,6 @@
uint64_t reserved_40_63:24;
#endif
} cn66xx;
- struct cvmx_mio_ptp_clock_cfg_s cn68xx;
- struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;
- struct cvmx_mio_ptp_clock_cfg_s cnf71xx;
};
union cvmx_mio_ptp_clock_comp {
@@ -3286,13 +2750,6 @@
uint64_t nanosec:32;
#endif
} s;
- struct cvmx_mio_ptp_clock_comp_s cn61xx;
- struct cvmx_mio_ptp_clock_comp_s cn63xx;
- struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
- struct cvmx_mio_ptp_clock_comp_s cn66xx;
- struct cvmx_mio_ptp_clock_comp_s cn68xx;
- struct cvmx_mio_ptp_clock_comp_s cn68xxp1;
- struct cvmx_mio_ptp_clock_comp_s cnf71xx;
};
union cvmx_mio_ptp_clock_hi {
@@ -3304,13 +2761,6 @@
uint64_t nanosec:64;
#endif
} s;
- struct cvmx_mio_ptp_clock_hi_s cn61xx;
- struct cvmx_mio_ptp_clock_hi_s cn63xx;
- struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
- struct cvmx_mio_ptp_clock_hi_s cn66xx;
- struct cvmx_mio_ptp_clock_hi_s cn68xx;
- struct cvmx_mio_ptp_clock_hi_s cn68xxp1;
- struct cvmx_mio_ptp_clock_hi_s cnf71xx;
};
union cvmx_mio_ptp_clock_lo {
@@ -3324,13 +2774,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_mio_ptp_clock_lo_s cn61xx;
- struct cvmx_mio_ptp_clock_lo_s cn63xx;
- struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
- struct cvmx_mio_ptp_clock_lo_s cn66xx;
- struct cvmx_mio_ptp_clock_lo_s cn68xx;
- struct cvmx_mio_ptp_clock_lo_s cn68xxp1;
- struct cvmx_mio_ptp_clock_lo_s cnf71xx;
};
union cvmx_mio_ptp_evt_cnt {
@@ -3342,13 +2785,6 @@
uint64_t cntr:64;
#endif
} s;
- struct cvmx_mio_ptp_evt_cnt_s cn61xx;
- struct cvmx_mio_ptp_evt_cnt_s cn63xx;
- struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
- struct cvmx_mio_ptp_evt_cnt_s cn66xx;
- struct cvmx_mio_ptp_evt_cnt_s cn68xx;
- struct cvmx_mio_ptp_evt_cnt_s cn68xxp1;
- struct cvmx_mio_ptp_evt_cnt_s cnf71xx;
};
union cvmx_mio_ptp_phy_1pps_in {
@@ -3362,7 +2798,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_mio_ptp_phy_1pps_in_s cnf71xx;
};
union cvmx_mio_ptp_pps_hi_incr {
@@ -3376,10 +2811,6 @@
uint64_t nanosec:32;
#endif
} s;
- struct cvmx_mio_ptp_pps_hi_incr_s cn61xx;
- struct cvmx_mio_ptp_pps_hi_incr_s cn66xx;
- struct cvmx_mio_ptp_pps_hi_incr_s cn68xx;
- struct cvmx_mio_ptp_pps_hi_incr_s cnf71xx;
};
union cvmx_mio_ptp_pps_lo_incr {
@@ -3393,10 +2824,6 @@
uint64_t nanosec:32;
#endif
} s;
- struct cvmx_mio_ptp_pps_lo_incr_s cn61xx;
- struct cvmx_mio_ptp_pps_lo_incr_s cn66xx;
- struct cvmx_mio_ptp_pps_lo_incr_s cn68xx;
- struct cvmx_mio_ptp_pps_lo_incr_s cnf71xx;
};
union cvmx_mio_ptp_pps_thresh_hi {
@@ -3408,10 +2835,6 @@
uint64_t nanosec:64;
#endif
} s;
- struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx;
- struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx;
- struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx;
- struct cvmx_mio_ptp_pps_thresh_hi_s cnf71xx;
};
union cvmx_mio_ptp_pps_thresh_lo {
@@ -3425,10 +2848,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx;
- struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx;
- struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx;
- struct cvmx_mio_ptp_pps_thresh_lo_s cnf71xx;
};
union cvmx_mio_ptp_timestamp {
@@ -3440,13 +2859,6 @@
uint64_t nanosec:64;
#endif
} s;
- struct cvmx_mio_ptp_timestamp_s cn61xx;
- struct cvmx_mio_ptp_timestamp_s cn63xx;
- struct cvmx_mio_ptp_timestamp_s cn63xxp1;
- struct cvmx_mio_ptp_timestamp_s cn66xx;
- struct cvmx_mio_ptp_timestamp_s cn68xx;
- struct cvmx_mio_ptp_timestamp_s cn68xxp1;
- struct cvmx_mio_ptp_timestamp_s cnf71xx;
};
union cvmx_mio_qlmx_cfg {
@@ -3511,8 +2923,6 @@
uint64_t reserved_12_63:52;
#endif
} cn68xx;
- struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1;
- struct cvmx_mio_qlmx_cfg_cn61xx cnf71xx;
};
union cvmx_mio_rst_boot {
@@ -3622,7 +3032,6 @@
uint64_t reserved_36_63:28;
#endif
} cn63xx;
- struct cvmx_mio_rst_boot_cn63xx cn63xxp1;
struct cvmx_mio_rst_boot_cn66xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t chipkill:1;
@@ -3718,7 +3127,6 @@
uint64_t reserved_44_63:20;
#endif
} cn68xxp1;
- struct cvmx_mio_rst_boot_cn61xx cnf71xx;
};
union cvmx_mio_rst_cfg {
@@ -3751,7 +3159,6 @@
uint64_t bist_delay:58;
#endif
} cn61xx;
- struct cvmx_mio_rst_cfg_cn61xx cn63xx;
struct cvmx_mio_rst_cfg_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bist_delay:58;
@@ -3765,7 +3172,6 @@
uint64_t bist_delay:58;
#endif
} cn63xxp1;
- struct cvmx_mio_rst_cfg_cn61xx cn66xx;
struct cvmx_mio_rst_cfg_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t bist_delay:56;
@@ -3781,8 +3187,6 @@
uint64_t bist_delay:56;
#endif
} cn68xx;
- struct cvmx_mio_rst_cfg_cn68xx cn68xxp1;
- struct cvmx_mio_rst_cfg_cn61xx cnf71xx;
};
union cvmx_mio_rst_ckill {
@@ -3796,9 +3200,6 @@
uint64_t reserved_47_63:17;
#endif
} s;
- struct cvmx_mio_rst_ckill_s cn61xx;
- struct cvmx_mio_rst_ckill_s cn66xx;
- struct cvmx_mio_rst_ckill_s cnf71xx;
};
union cvmx_mio_rst_cntlx {
@@ -3834,7 +3235,6 @@
uint64_t reserved_13_63:51;
#endif
} s;
- struct cvmx_mio_rst_cntlx_s cn61xx;
struct cvmx_mio_rst_cntlx_cn66xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
@@ -3860,8 +3260,6 @@
uint64_t reserved_10_63:54;
#endif
} cn66xx;
- struct cvmx_mio_rst_cntlx_cn66xx cn68xx;
- struct cvmx_mio_rst_cntlx_s cnf71xx;
};
union cvmx_mio_rst_ctlx {
@@ -3897,7 +3295,6 @@
uint64_t reserved_13_63:51;
#endif
} s;
- struct cvmx_mio_rst_ctlx_s cn61xx;
struct cvmx_mio_rst_ctlx_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
@@ -3946,10 +3343,6 @@
uint64_t reserved_9_63:55;
#endif
} cn63xxp1;
- struct cvmx_mio_rst_ctlx_cn63xx cn66xx;
- struct cvmx_mio_rst_ctlx_cn63xx cn68xx;
- struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1;
- struct cvmx_mio_rst_ctlx_s cnf71xx;
};
union cvmx_mio_rst_delay {
@@ -3965,13 +3358,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_mio_rst_delay_s cn61xx;
- struct cvmx_mio_rst_delay_s cn63xx;
- struct cvmx_mio_rst_delay_s cn63xxp1;
- struct cvmx_mio_rst_delay_s cn66xx;
- struct cvmx_mio_rst_delay_s cn68xx;
- struct cvmx_mio_rst_delay_s cn68xxp1;
- struct cvmx_mio_rst_delay_s cnf71xx;
};
union cvmx_mio_rst_int {
@@ -4014,12 +3400,6 @@
uint64_t reserved_10_63:54;
#endif
} cn61xx;
- struct cvmx_mio_rst_int_cn61xx cn63xx;
- struct cvmx_mio_rst_int_cn61xx cn63xxp1;
- struct cvmx_mio_rst_int_s cn66xx;
- struct cvmx_mio_rst_int_cn61xx cn68xx;
- struct cvmx_mio_rst_int_cn61xx cn68xxp1;
- struct cvmx_mio_rst_int_cn61xx cnf71xx;
};
union cvmx_mio_rst_int_en {
@@ -4062,12 +3442,6 @@
uint64_t reserved_10_63:54;
#endif
} cn61xx;
- struct cvmx_mio_rst_int_en_cn61xx cn63xx;
- struct cvmx_mio_rst_int_en_cn61xx cn63xxp1;
- struct cvmx_mio_rst_int_en_s cn66xx;
- struct cvmx_mio_rst_int_en_cn61xx cn68xx;
- struct cvmx_mio_rst_int_en_cn61xx cn68xxp1;
- struct cvmx_mio_rst_int_en_cn61xx cnf71xx;
};
union cvmx_mio_twsx_int {
@@ -4103,9 +3477,6 @@
uint64_t reserved_12_63:52;
#endif
} s;
- struct cvmx_mio_twsx_int_s cn30xx;
- struct cvmx_mio_twsx_int_s cn31xx;
- struct cvmx_mio_twsx_int_s cn38xx;
struct cvmx_mio_twsx_int_cn38xxp2 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
@@ -4127,20 +3498,6 @@
uint64_t reserved_7_63:57;
#endif
} cn38xxp2;
- struct cvmx_mio_twsx_int_s cn50xx;
- struct cvmx_mio_twsx_int_s cn52xx;
- struct cvmx_mio_twsx_int_s cn52xxp1;
- struct cvmx_mio_twsx_int_s cn56xx;
- struct cvmx_mio_twsx_int_s cn56xxp1;
- struct cvmx_mio_twsx_int_s cn58xx;
- struct cvmx_mio_twsx_int_s cn58xxp1;
- struct cvmx_mio_twsx_int_s cn61xx;
- struct cvmx_mio_twsx_int_s cn63xx;
- struct cvmx_mio_twsx_int_s cn63xxp1;
- struct cvmx_mio_twsx_int_s cn66xx;
- struct cvmx_mio_twsx_int_s cn68xx;
- struct cvmx_mio_twsx_int_s cn68xxp1;
- struct cvmx_mio_twsx_int_s cnf71xx;
};
union cvmx_mio_twsx_sw_twsi {
@@ -4174,24 +3531,6 @@
uint64_t v:1;
#endif
} s;
- struct cvmx_mio_twsx_sw_twsi_s cn30xx;
- struct cvmx_mio_twsx_sw_twsi_s cn31xx;
- struct cvmx_mio_twsx_sw_twsi_s cn38xx;
- struct cvmx_mio_twsx_sw_twsi_s cn38xxp2;
- struct cvmx_mio_twsx_sw_twsi_s cn50xx;
- struct cvmx_mio_twsx_sw_twsi_s cn52xx;
- struct cvmx_mio_twsx_sw_twsi_s cn52xxp1;
- struct cvmx_mio_twsx_sw_twsi_s cn56xx;
- struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
- struct cvmx_mio_twsx_sw_twsi_s cn58xx;
- struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
- struct cvmx_mio_twsx_sw_twsi_s cn61xx;
- struct cvmx_mio_twsx_sw_twsi_s cn63xx;
- struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
- struct cvmx_mio_twsx_sw_twsi_s cn66xx;
- struct cvmx_mio_twsx_sw_twsi_s cn68xx;
- struct cvmx_mio_twsx_sw_twsi_s cn68xxp1;
- struct cvmx_mio_twsx_sw_twsi_s cnf71xx;
};
union cvmx_mio_twsx_sw_twsi_ext {
@@ -4207,24 +3546,6 @@
uint64_t reserved_40_63:24;
#endif
} s;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx;
- struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1;
- struct cvmx_mio_twsx_sw_twsi_ext_s cnf71xx;
};
union cvmx_mio_twsx_twsi_sw {
@@ -4240,24 +3561,6 @@
uint64_t v:2;
#endif
} s;
- struct cvmx_mio_twsx_twsi_sw_s cn30xx;
- struct cvmx_mio_twsx_twsi_sw_s cn31xx;
- struct cvmx_mio_twsx_twsi_sw_s cn38xx;
- struct cvmx_mio_twsx_twsi_sw_s cn38xxp2;
- struct cvmx_mio_twsx_twsi_sw_s cn50xx;
- struct cvmx_mio_twsx_twsi_sw_s cn52xx;
- struct cvmx_mio_twsx_twsi_sw_s cn52xxp1;
- struct cvmx_mio_twsx_twsi_sw_s cn56xx;
- struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
- struct cvmx_mio_twsx_twsi_sw_s cn58xx;
- struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
- struct cvmx_mio_twsx_twsi_sw_s cn61xx;
- struct cvmx_mio_twsx_twsi_sw_s cn63xx;
- struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
- struct cvmx_mio_twsx_twsi_sw_s cn66xx;
- struct cvmx_mio_twsx_twsi_sw_s cn68xx;
- struct cvmx_mio_twsx_twsi_sw_s cn68xxp1;
- struct cvmx_mio_twsx_twsi_sw_s cnf71xx;
};
union cvmx_mio_uartx_dlh {
@@ -4271,24 +3574,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_dlh_s cn30xx;
- struct cvmx_mio_uartx_dlh_s cn31xx;
- struct cvmx_mio_uartx_dlh_s cn38xx;
- struct cvmx_mio_uartx_dlh_s cn38xxp2;
- struct cvmx_mio_uartx_dlh_s cn50xx;
- struct cvmx_mio_uartx_dlh_s cn52xx;
- struct cvmx_mio_uartx_dlh_s cn52xxp1;
- struct cvmx_mio_uartx_dlh_s cn56xx;
- struct cvmx_mio_uartx_dlh_s cn56xxp1;
- struct cvmx_mio_uartx_dlh_s cn58xx;
- struct cvmx_mio_uartx_dlh_s cn58xxp1;
- struct cvmx_mio_uartx_dlh_s cn61xx;
- struct cvmx_mio_uartx_dlh_s cn63xx;
- struct cvmx_mio_uartx_dlh_s cn63xxp1;
- struct cvmx_mio_uartx_dlh_s cn66xx;
- struct cvmx_mio_uartx_dlh_s cn68xx;
- struct cvmx_mio_uartx_dlh_s cn68xxp1;
- struct cvmx_mio_uartx_dlh_s cnf71xx;
};
union cvmx_mio_uartx_dll {
@@ -4302,24 +3587,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_dll_s cn30xx;
- struct cvmx_mio_uartx_dll_s cn31xx;
- struct cvmx_mio_uartx_dll_s cn38xx;
- struct cvmx_mio_uartx_dll_s cn38xxp2;
- struct cvmx_mio_uartx_dll_s cn50xx;
- struct cvmx_mio_uartx_dll_s cn52xx;
- struct cvmx_mio_uartx_dll_s cn52xxp1;
- struct cvmx_mio_uartx_dll_s cn56xx;
- struct cvmx_mio_uartx_dll_s cn56xxp1;
- struct cvmx_mio_uartx_dll_s cn58xx;
- struct cvmx_mio_uartx_dll_s cn58xxp1;
- struct cvmx_mio_uartx_dll_s cn61xx;
- struct cvmx_mio_uartx_dll_s cn63xx;
- struct cvmx_mio_uartx_dll_s cn63xxp1;
- struct cvmx_mio_uartx_dll_s cn66xx;
- struct cvmx_mio_uartx_dll_s cn68xx;
- struct cvmx_mio_uartx_dll_s cn68xxp1;
- struct cvmx_mio_uartx_dll_s cnf71xx;
};
union cvmx_mio_uartx_far {
@@ -4333,24 +3600,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_uartx_far_s cn30xx;
- struct cvmx_mio_uartx_far_s cn31xx;
- struct cvmx_mio_uartx_far_s cn38xx;
- struct cvmx_mio_uartx_far_s cn38xxp2;
- struct cvmx_mio_uartx_far_s cn50xx;
- struct cvmx_mio_uartx_far_s cn52xx;
- struct cvmx_mio_uartx_far_s cn52xxp1;
- struct cvmx_mio_uartx_far_s cn56xx;
- struct cvmx_mio_uartx_far_s cn56xxp1;
- struct cvmx_mio_uartx_far_s cn58xx;
- struct cvmx_mio_uartx_far_s cn58xxp1;
- struct cvmx_mio_uartx_far_s cn61xx;
- struct cvmx_mio_uartx_far_s cn63xx;
- struct cvmx_mio_uartx_far_s cn63xxp1;
- struct cvmx_mio_uartx_far_s cn66xx;
- struct cvmx_mio_uartx_far_s cn68xx;
- struct cvmx_mio_uartx_far_s cn68xxp1;
- struct cvmx_mio_uartx_far_s cnf71xx;
};
union cvmx_mio_uartx_fcr {
@@ -4374,24 +3623,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_fcr_s cn30xx;
- struct cvmx_mio_uartx_fcr_s cn31xx;
- struct cvmx_mio_uartx_fcr_s cn38xx;
- struct cvmx_mio_uartx_fcr_s cn38xxp2;
- struct cvmx_mio_uartx_fcr_s cn50xx;
- struct cvmx_mio_uartx_fcr_s cn52xx;
- struct cvmx_mio_uartx_fcr_s cn52xxp1;
- struct cvmx_mio_uartx_fcr_s cn56xx;
- struct cvmx_mio_uartx_fcr_s cn56xxp1;
- struct cvmx_mio_uartx_fcr_s cn58xx;
- struct cvmx_mio_uartx_fcr_s cn58xxp1;
- struct cvmx_mio_uartx_fcr_s cn61xx;
- struct cvmx_mio_uartx_fcr_s cn63xx;
- struct cvmx_mio_uartx_fcr_s cn63xxp1;
- struct cvmx_mio_uartx_fcr_s cn66xx;
- struct cvmx_mio_uartx_fcr_s cn68xx;
- struct cvmx_mio_uartx_fcr_s cn68xxp1;
- struct cvmx_mio_uartx_fcr_s cnf71xx;
};
union cvmx_mio_uartx_htx {
@@ -4405,24 +3636,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_uartx_htx_s cn30xx;
- struct cvmx_mio_uartx_htx_s cn31xx;
- struct cvmx_mio_uartx_htx_s cn38xx;
- struct cvmx_mio_uartx_htx_s cn38xxp2;
- struct cvmx_mio_uartx_htx_s cn50xx;
- struct cvmx_mio_uartx_htx_s cn52xx;
- struct cvmx_mio_uartx_htx_s cn52xxp1;
- struct cvmx_mio_uartx_htx_s cn56xx;
- struct cvmx_mio_uartx_htx_s cn56xxp1;
- struct cvmx_mio_uartx_htx_s cn58xx;
- struct cvmx_mio_uartx_htx_s cn58xxp1;
- struct cvmx_mio_uartx_htx_s cn61xx;
- struct cvmx_mio_uartx_htx_s cn63xx;
- struct cvmx_mio_uartx_htx_s cn63xxp1;
- struct cvmx_mio_uartx_htx_s cn66xx;
- struct cvmx_mio_uartx_htx_s cn68xx;
- struct cvmx_mio_uartx_htx_s cn68xxp1;
- struct cvmx_mio_uartx_htx_s cnf71xx;
};
union cvmx_mio_uartx_ier {
@@ -4446,24 +3659,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_ier_s cn30xx;
- struct cvmx_mio_uartx_ier_s cn31xx;
- struct cvmx_mio_uartx_ier_s cn38xx;
- struct cvmx_mio_uartx_ier_s cn38xxp2;
- struct cvmx_mio_uartx_ier_s cn50xx;
- struct cvmx_mio_uartx_ier_s cn52xx;
- struct cvmx_mio_uartx_ier_s cn52xxp1;
- struct cvmx_mio_uartx_ier_s cn56xx;
- struct cvmx_mio_uartx_ier_s cn56xxp1;
- struct cvmx_mio_uartx_ier_s cn58xx;
- struct cvmx_mio_uartx_ier_s cn58xxp1;
- struct cvmx_mio_uartx_ier_s cn61xx;
- struct cvmx_mio_uartx_ier_s cn63xx;
- struct cvmx_mio_uartx_ier_s cn63xxp1;
- struct cvmx_mio_uartx_ier_s cn66xx;
- struct cvmx_mio_uartx_ier_s cn68xx;
- struct cvmx_mio_uartx_ier_s cn68xxp1;
- struct cvmx_mio_uartx_ier_s cnf71xx;
};
union cvmx_mio_uartx_iir {
@@ -4481,24 +3676,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_iir_s cn30xx;
- struct cvmx_mio_uartx_iir_s cn31xx;
- struct cvmx_mio_uartx_iir_s cn38xx;
- struct cvmx_mio_uartx_iir_s cn38xxp2;
- struct cvmx_mio_uartx_iir_s cn50xx;
- struct cvmx_mio_uartx_iir_s cn52xx;
- struct cvmx_mio_uartx_iir_s cn52xxp1;
- struct cvmx_mio_uartx_iir_s cn56xx;
- struct cvmx_mio_uartx_iir_s cn56xxp1;
- struct cvmx_mio_uartx_iir_s cn58xx;
- struct cvmx_mio_uartx_iir_s cn58xxp1;
- struct cvmx_mio_uartx_iir_s cn61xx;
- struct cvmx_mio_uartx_iir_s cn63xx;
- struct cvmx_mio_uartx_iir_s cn63xxp1;
- struct cvmx_mio_uartx_iir_s cn66xx;
- struct cvmx_mio_uartx_iir_s cn68xx;
- struct cvmx_mio_uartx_iir_s cn68xxp1;
- struct cvmx_mio_uartx_iir_s cnf71xx;
};
union cvmx_mio_uartx_lcr {
@@ -4524,24 +3701,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_lcr_s cn30xx;
- struct cvmx_mio_uartx_lcr_s cn31xx;
- struct cvmx_mio_uartx_lcr_s cn38xx;
- struct cvmx_mio_uartx_lcr_s cn38xxp2;
- struct cvmx_mio_uartx_lcr_s cn50xx;
- struct cvmx_mio_uartx_lcr_s cn52xx;
- struct cvmx_mio_uartx_lcr_s cn52xxp1;
- struct cvmx_mio_uartx_lcr_s cn56xx;
- struct cvmx_mio_uartx_lcr_s cn56xxp1;
- struct cvmx_mio_uartx_lcr_s cn58xx;
- struct cvmx_mio_uartx_lcr_s cn58xxp1;
- struct cvmx_mio_uartx_lcr_s cn61xx;
- struct cvmx_mio_uartx_lcr_s cn63xx;
- struct cvmx_mio_uartx_lcr_s cn63xxp1;
- struct cvmx_mio_uartx_lcr_s cn66xx;
- struct cvmx_mio_uartx_lcr_s cn68xx;
- struct cvmx_mio_uartx_lcr_s cn68xxp1;
- struct cvmx_mio_uartx_lcr_s cnf71xx;
};
union cvmx_mio_uartx_lsr {
@@ -4569,24 +3728,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_lsr_s cn30xx;
- struct cvmx_mio_uartx_lsr_s cn31xx;
- struct cvmx_mio_uartx_lsr_s cn38xx;
- struct cvmx_mio_uartx_lsr_s cn38xxp2;
- struct cvmx_mio_uartx_lsr_s cn50xx;
- struct cvmx_mio_uartx_lsr_s cn52xx;
- struct cvmx_mio_uartx_lsr_s cn52xxp1;
- struct cvmx_mio_uartx_lsr_s cn56xx;
- struct cvmx_mio_uartx_lsr_s cn56xxp1;
- struct cvmx_mio_uartx_lsr_s cn58xx;
- struct cvmx_mio_uartx_lsr_s cn58xxp1;
- struct cvmx_mio_uartx_lsr_s cn61xx;
- struct cvmx_mio_uartx_lsr_s cn63xx;
- struct cvmx_mio_uartx_lsr_s cn63xxp1;
- struct cvmx_mio_uartx_lsr_s cn66xx;
- struct cvmx_mio_uartx_lsr_s cn68xx;
- struct cvmx_mio_uartx_lsr_s cn68xxp1;
- struct cvmx_mio_uartx_lsr_s cnf71xx;
};
union cvmx_mio_uartx_mcr {
@@ -4610,24 +3751,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_mio_uartx_mcr_s cn30xx;
- struct cvmx_mio_uartx_mcr_s cn31xx;
- struct cvmx_mio_uartx_mcr_s cn38xx;
- struct cvmx_mio_uartx_mcr_s cn38xxp2;
- struct cvmx_mio_uartx_mcr_s cn50xx;
- struct cvmx_mio_uartx_mcr_s cn52xx;
- struct cvmx_mio_uartx_mcr_s cn52xxp1;
- struct cvmx_mio_uartx_mcr_s cn56xx;
- struct cvmx_mio_uartx_mcr_s cn56xxp1;
- struct cvmx_mio_uartx_mcr_s cn58xx;
- struct cvmx_mio_uartx_mcr_s cn58xxp1;
- struct cvmx_mio_uartx_mcr_s cn61xx;
- struct cvmx_mio_uartx_mcr_s cn63xx;
- struct cvmx_mio_uartx_mcr_s cn63xxp1;
- struct cvmx_mio_uartx_mcr_s cn66xx;
- struct cvmx_mio_uartx_mcr_s cn68xx;
- struct cvmx_mio_uartx_mcr_s cn68xxp1;
- struct cvmx_mio_uartx_mcr_s cnf71xx;
};
union cvmx_mio_uartx_msr {
@@ -4655,24 +3778,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_msr_s cn30xx;
- struct cvmx_mio_uartx_msr_s cn31xx;
- struct cvmx_mio_uartx_msr_s cn38xx;
- struct cvmx_mio_uartx_msr_s cn38xxp2;
- struct cvmx_mio_uartx_msr_s cn50xx;
- struct cvmx_mio_uartx_msr_s cn52xx;
- struct cvmx_mio_uartx_msr_s cn52xxp1;
- struct cvmx_mio_uartx_msr_s cn56xx;
- struct cvmx_mio_uartx_msr_s cn56xxp1;
- struct cvmx_mio_uartx_msr_s cn58xx;
- struct cvmx_mio_uartx_msr_s cn58xxp1;
- struct cvmx_mio_uartx_msr_s cn61xx;
- struct cvmx_mio_uartx_msr_s cn63xx;
- struct cvmx_mio_uartx_msr_s cn63xxp1;
- struct cvmx_mio_uartx_msr_s cn66xx;
- struct cvmx_mio_uartx_msr_s cn68xx;
- struct cvmx_mio_uartx_msr_s cn68xxp1;
- struct cvmx_mio_uartx_msr_s cnf71xx;
};
union cvmx_mio_uartx_rbr {
@@ -4686,24 +3791,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_rbr_s cn30xx;
- struct cvmx_mio_uartx_rbr_s cn31xx;
- struct cvmx_mio_uartx_rbr_s cn38xx;
- struct cvmx_mio_uartx_rbr_s cn38xxp2;
- struct cvmx_mio_uartx_rbr_s cn50xx;
- struct cvmx_mio_uartx_rbr_s cn52xx;
- struct cvmx_mio_uartx_rbr_s cn52xxp1;
- struct cvmx_mio_uartx_rbr_s cn56xx;
- struct cvmx_mio_uartx_rbr_s cn56xxp1;
- struct cvmx_mio_uartx_rbr_s cn58xx;
- struct cvmx_mio_uartx_rbr_s cn58xxp1;
- struct cvmx_mio_uartx_rbr_s cn61xx;
- struct cvmx_mio_uartx_rbr_s cn63xx;
- struct cvmx_mio_uartx_rbr_s cn63xxp1;
- struct cvmx_mio_uartx_rbr_s cn66xx;
- struct cvmx_mio_uartx_rbr_s cn68xx;
- struct cvmx_mio_uartx_rbr_s cn68xxp1;
- struct cvmx_mio_uartx_rbr_s cnf71xx;
};
union cvmx_mio_uartx_rfl {
@@ -4717,24 +3804,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_mio_uartx_rfl_s cn30xx;
- struct cvmx_mio_uartx_rfl_s cn31xx;
- struct cvmx_mio_uartx_rfl_s cn38xx;
- struct cvmx_mio_uartx_rfl_s cn38xxp2;
- struct cvmx_mio_uartx_rfl_s cn50xx;
- struct cvmx_mio_uartx_rfl_s cn52xx;
- struct cvmx_mio_uartx_rfl_s cn52xxp1;
- struct cvmx_mio_uartx_rfl_s cn56xx;
- struct cvmx_mio_uartx_rfl_s cn56xxp1;
- struct cvmx_mio_uartx_rfl_s cn58xx;
- struct cvmx_mio_uartx_rfl_s cn58xxp1;
- struct cvmx_mio_uartx_rfl_s cn61xx;
- struct cvmx_mio_uartx_rfl_s cn63xx;
- struct cvmx_mio_uartx_rfl_s cn63xxp1;
- struct cvmx_mio_uartx_rfl_s cn66xx;
- struct cvmx_mio_uartx_rfl_s cn68xx;
- struct cvmx_mio_uartx_rfl_s cn68xxp1;
- struct cvmx_mio_uartx_rfl_s cnf71xx;
};
union cvmx_mio_uartx_rfw {
@@ -4752,24 +3821,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_mio_uartx_rfw_s cn30xx;
- struct cvmx_mio_uartx_rfw_s cn31xx;
- struct cvmx_mio_uartx_rfw_s cn38xx;
- struct cvmx_mio_uartx_rfw_s cn38xxp2;
- struct cvmx_mio_uartx_rfw_s cn50xx;
- struct cvmx_mio_uartx_rfw_s cn52xx;
- struct cvmx_mio_uartx_rfw_s cn52xxp1;
- struct cvmx_mio_uartx_rfw_s cn56xx;
- struct cvmx_mio_uartx_rfw_s cn56xxp1;
- struct cvmx_mio_uartx_rfw_s cn58xx;
- struct cvmx_mio_uartx_rfw_s cn58xxp1;
- struct cvmx_mio_uartx_rfw_s cn61xx;
- struct cvmx_mio_uartx_rfw_s cn63xx;
- struct cvmx_mio_uartx_rfw_s cn63xxp1;
- struct cvmx_mio_uartx_rfw_s cn66xx;
- struct cvmx_mio_uartx_rfw_s cn68xx;
- struct cvmx_mio_uartx_rfw_s cn68xxp1;
- struct cvmx_mio_uartx_rfw_s cnf71xx;
};
union cvmx_mio_uartx_sbcr {
@@ -4783,24 +3834,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_uartx_sbcr_s cn30xx;
- struct cvmx_mio_uartx_sbcr_s cn31xx;
- struct cvmx_mio_uartx_sbcr_s cn38xx;
- struct cvmx_mio_uartx_sbcr_s cn38xxp2;
- struct cvmx_mio_uartx_sbcr_s cn50xx;
- struct cvmx_mio_uartx_sbcr_s cn52xx;
- struct cvmx_mio_uartx_sbcr_s cn52xxp1;
- struct cvmx_mio_uartx_sbcr_s cn56xx;
- struct cvmx_mio_uartx_sbcr_s cn56xxp1;
- struct cvmx_mio_uartx_sbcr_s cn58xx;
- struct cvmx_mio_uartx_sbcr_s cn58xxp1;
- struct cvmx_mio_uartx_sbcr_s cn61xx;
- struct cvmx_mio_uartx_sbcr_s cn63xx;
- struct cvmx_mio_uartx_sbcr_s cn63xxp1;
- struct cvmx_mio_uartx_sbcr_s cn66xx;
- struct cvmx_mio_uartx_sbcr_s cn68xx;
- struct cvmx_mio_uartx_sbcr_s cn68xxp1;
- struct cvmx_mio_uartx_sbcr_s cnf71xx;
};
union cvmx_mio_uartx_scr {
@@ -4814,24 +3847,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_scr_s cn30xx;
- struct cvmx_mio_uartx_scr_s cn31xx;
- struct cvmx_mio_uartx_scr_s cn38xx;
- struct cvmx_mio_uartx_scr_s cn38xxp2;
- struct cvmx_mio_uartx_scr_s cn50xx;
- struct cvmx_mio_uartx_scr_s cn52xx;
- struct cvmx_mio_uartx_scr_s cn52xxp1;
- struct cvmx_mio_uartx_scr_s cn56xx;
- struct cvmx_mio_uartx_scr_s cn56xxp1;
- struct cvmx_mio_uartx_scr_s cn58xx;
- struct cvmx_mio_uartx_scr_s cn58xxp1;
- struct cvmx_mio_uartx_scr_s cn61xx;
- struct cvmx_mio_uartx_scr_s cn63xx;
- struct cvmx_mio_uartx_scr_s cn63xxp1;
- struct cvmx_mio_uartx_scr_s cn66xx;
- struct cvmx_mio_uartx_scr_s cn68xx;
- struct cvmx_mio_uartx_scr_s cn68xxp1;
- struct cvmx_mio_uartx_scr_s cnf71xx;
};
union cvmx_mio_uartx_sfe {
@@ -4845,24 +3860,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_uartx_sfe_s cn30xx;
- struct cvmx_mio_uartx_sfe_s cn31xx;
- struct cvmx_mio_uartx_sfe_s cn38xx;
- struct cvmx_mio_uartx_sfe_s cn38xxp2;
- struct cvmx_mio_uartx_sfe_s cn50xx;
- struct cvmx_mio_uartx_sfe_s cn52xx;
- struct cvmx_mio_uartx_sfe_s cn52xxp1;
- struct cvmx_mio_uartx_sfe_s cn56xx;
- struct cvmx_mio_uartx_sfe_s cn56xxp1;
- struct cvmx_mio_uartx_sfe_s cn58xx;
- struct cvmx_mio_uartx_sfe_s cn58xxp1;
- struct cvmx_mio_uartx_sfe_s cn61xx;
- struct cvmx_mio_uartx_sfe_s cn63xx;
- struct cvmx_mio_uartx_sfe_s cn63xxp1;
- struct cvmx_mio_uartx_sfe_s cn66xx;
- struct cvmx_mio_uartx_sfe_s cn68xx;
- struct cvmx_mio_uartx_sfe_s cn68xxp1;
- struct cvmx_mio_uartx_sfe_s cnf71xx;
};
union cvmx_mio_uartx_srr {
@@ -4880,24 +3877,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_mio_uartx_srr_s cn30xx;
- struct cvmx_mio_uartx_srr_s cn31xx;
- struct cvmx_mio_uartx_srr_s cn38xx;
- struct cvmx_mio_uartx_srr_s cn38xxp2;
- struct cvmx_mio_uartx_srr_s cn50xx;
- struct cvmx_mio_uartx_srr_s cn52xx;
- struct cvmx_mio_uartx_srr_s cn52xxp1;
- struct cvmx_mio_uartx_srr_s cn56xx;
- struct cvmx_mio_uartx_srr_s cn56xxp1;
- struct cvmx_mio_uartx_srr_s cn58xx;
- struct cvmx_mio_uartx_srr_s cn58xxp1;
- struct cvmx_mio_uartx_srr_s cn61xx;
- struct cvmx_mio_uartx_srr_s cn63xx;
- struct cvmx_mio_uartx_srr_s cn63xxp1;
- struct cvmx_mio_uartx_srr_s cn66xx;
- struct cvmx_mio_uartx_srr_s cn68xx;
- struct cvmx_mio_uartx_srr_s cn68xxp1;
- struct cvmx_mio_uartx_srr_s cnf71xx;
};
union cvmx_mio_uartx_srt {
@@ -4911,24 +3890,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_mio_uartx_srt_s cn30xx;
- struct cvmx_mio_uartx_srt_s cn31xx;
- struct cvmx_mio_uartx_srt_s cn38xx;
- struct cvmx_mio_uartx_srt_s cn38xxp2;
- struct cvmx_mio_uartx_srt_s cn50xx;
- struct cvmx_mio_uartx_srt_s cn52xx;
- struct cvmx_mio_uartx_srt_s cn52xxp1;
- struct cvmx_mio_uartx_srt_s cn56xx;
- struct cvmx_mio_uartx_srt_s cn56xxp1;
- struct cvmx_mio_uartx_srt_s cn58xx;
- struct cvmx_mio_uartx_srt_s cn58xxp1;
- struct cvmx_mio_uartx_srt_s cn61xx;
- struct cvmx_mio_uartx_srt_s cn63xx;
- struct cvmx_mio_uartx_srt_s cn63xxp1;
- struct cvmx_mio_uartx_srt_s cn66xx;
- struct cvmx_mio_uartx_srt_s cn68xx;
- struct cvmx_mio_uartx_srt_s cn68xxp1;
- struct cvmx_mio_uartx_srt_s cnf71xx;
};
union cvmx_mio_uartx_srts {
@@ -4942,24 +3903,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_uartx_srts_s cn30xx;
- struct cvmx_mio_uartx_srts_s cn31xx;
- struct cvmx_mio_uartx_srts_s cn38xx;
- struct cvmx_mio_uartx_srts_s cn38xxp2;
- struct cvmx_mio_uartx_srts_s cn50xx;
- struct cvmx_mio_uartx_srts_s cn52xx;
- struct cvmx_mio_uartx_srts_s cn52xxp1;
- struct cvmx_mio_uartx_srts_s cn56xx;
- struct cvmx_mio_uartx_srts_s cn56xxp1;
- struct cvmx_mio_uartx_srts_s cn58xx;
- struct cvmx_mio_uartx_srts_s cn58xxp1;
- struct cvmx_mio_uartx_srts_s cn61xx;
- struct cvmx_mio_uartx_srts_s cn63xx;
- struct cvmx_mio_uartx_srts_s cn63xxp1;
- struct cvmx_mio_uartx_srts_s cn66xx;
- struct cvmx_mio_uartx_srts_s cn68xx;
- struct cvmx_mio_uartx_srts_s cn68xxp1;
- struct cvmx_mio_uartx_srts_s cnf71xx;
};
union cvmx_mio_uartx_stt {
@@ -4973,24 +3916,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_mio_uartx_stt_s cn30xx;
- struct cvmx_mio_uartx_stt_s cn31xx;
- struct cvmx_mio_uartx_stt_s cn38xx;
- struct cvmx_mio_uartx_stt_s cn38xxp2;
- struct cvmx_mio_uartx_stt_s cn50xx;
- struct cvmx_mio_uartx_stt_s cn52xx;
- struct cvmx_mio_uartx_stt_s cn52xxp1;
- struct cvmx_mio_uartx_stt_s cn56xx;
- struct cvmx_mio_uartx_stt_s cn56xxp1;
- struct cvmx_mio_uartx_stt_s cn58xx;
- struct cvmx_mio_uartx_stt_s cn58xxp1;
- struct cvmx_mio_uartx_stt_s cn61xx;
- struct cvmx_mio_uartx_stt_s cn63xx;
- struct cvmx_mio_uartx_stt_s cn63xxp1;
- struct cvmx_mio_uartx_stt_s cn66xx;
- struct cvmx_mio_uartx_stt_s cn68xx;
- struct cvmx_mio_uartx_stt_s cn68xxp1;
- struct cvmx_mio_uartx_stt_s cnf71xx;
};
union cvmx_mio_uartx_tfl {
@@ -5004,24 +3929,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_mio_uartx_tfl_s cn30xx;
- struct cvmx_mio_uartx_tfl_s cn31xx;
- struct cvmx_mio_uartx_tfl_s cn38xx;
- struct cvmx_mio_uartx_tfl_s cn38xxp2;
- struct cvmx_mio_uartx_tfl_s cn50xx;
- struct cvmx_mio_uartx_tfl_s cn52xx;
- struct cvmx_mio_uartx_tfl_s cn52xxp1;
- struct cvmx_mio_uartx_tfl_s cn56xx;
- struct cvmx_mio_uartx_tfl_s cn56xxp1;
- struct cvmx_mio_uartx_tfl_s cn58xx;
- struct cvmx_mio_uartx_tfl_s cn58xxp1;
- struct cvmx_mio_uartx_tfl_s cn61xx;
- struct cvmx_mio_uartx_tfl_s cn63xx;
- struct cvmx_mio_uartx_tfl_s cn63xxp1;
- struct cvmx_mio_uartx_tfl_s cn66xx;
- struct cvmx_mio_uartx_tfl_s cn68xx;
- struct cvmx_mio_uartx_tfl_s cn68xxp1;
- struct cvmx_mio_uartx_tfl_s cnf71xx;
};
union cvmx_mio_uartx_tfr {
@@ -5035,24 +3942,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_tfr_s cn30xx;
- struct cvmx_mio_uartx_tfr_s cn31xx;
- struct cvmx_mio_uartx_tfr_s cn38xx;
- struct cvmx_mio_uartx_tfr_s cn38xxp2;
- struct cvmx_mio_uartx_tfr_s cn50xx;
- struct cvmx_mio_uartx_tfr_s cn52xx;
- struct cvmx_mio_uartx_tfr_s cn52xxp1;
- struct cvmx_mio_uartx_tfr_s cn56xx;
- struct cvmx_mio_uartx_tfr_s cn56xxp1;
- struct cvmx_mio_uartx_tfr_s cn58xx;
- struct cvmx_mio_uartx_tfr_s cn58xxp1;
- struct cvmx_mio_uartx_tfr_s cn61xx;
- struct cvmx_mio_uartx_tfr_s cn63xx;
- struct cvmx_mio_uartx_tfr_s cn63xxp1;
- struct cvmx_mio_uartx_tfr_s cn66xx;
- struct cvmx_mio_uartx_tfr_s cn68xx;
- struct cvmx_mio_uartx_tfr_s cn68xxp1;
- struct cvmx_mio_uartx_tfr_s cnf71xx;
};
union cvmx_mio_uartx_thr {
@@ -5066,24 +3955,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uartx_thr_s cn30xx;
- struct cvmx_mio_uartx_thr_s cn31xx;
- struct cvmx_mio_uartx_thr_s cn38xx;
- struct cvmx_mio_uartx_thr_s cn38xxp2;
- struct cvmx_mio_uartx_thr_s cn50xx;
- struct cvmx_mio_uartx_thr_s cn52xx;
- struct cvmx_mio_uartx_thr_s cn52xxp1;
- struct cvmx_mio_uartx_thr_s cn56xx;
- struct cvmx_mio_uartx_thr_s cn56xxp1;
- struct cvmx_mio_uartx_thr_s cn58xx;
- struct cvmx_mio_uartx_thr_s cn58xxp1;
- struct cvmx_mio_uartx_thr_s cn61xx;
- struct cvmx_mio_uartx_thr_s cn63xx;
- struct cvmx_mio_uartx_thr_s cn63xxp1;
- struct cvmx_mio_uartx_thr_s cn66xx;
- struct cvmx_mio_uartx_thr_s cn68xx;
- struct cvmx_mio_uartx_thr_s cn68xxp1;
- struct cvmx_mio_uartx_thr_s cnf71xx;
};
union cvmx_mio_uartx_usr {
@@ -5105,24 +3976,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_mio_uartx_usr_s cn30xx;
- struct cvmx_mio_uartx_usr_s cn31xx;
- struct cvmx_mio_uartx_usr_s cn38xx;
- struct cvmx_mio_uartx_usr_s cn38xxp2;
- struct cvmx_mio_uartx_usr_s cn50xx;
- struct cvmx_mio_uartx_usr_s cn52xx;
- struct cvmx_mio_uartx_usr_s cn52xxp1;
- struct cvmx_mio_uartx_usr_s cn56xx;
- struct cvmx_mio_uartx_usr_s cn56xxp1;
- struct cvmx_mio_uartx_usr_s cn58xx;
- struct cvmx_mio_uartx_usr_s cn58xxp1;
- struct cvmx_mio_uartx_usr_s cn61xx;
- struct cvmx_mio_uartx_usr_s cn63xx;
- struct cvmx_mio_uartx_usr_s cn63xxp1;
- struct cvmx_mio_uartx_usr_s cn66xx;
- struct cvmx_mio_uartx_usr_s cn68xx;
- struct cvmx_mio_uartx_usr_s cn68xxp1;
- struct cvmx_mio_uartx_usr_s cnf71xx;
};
union cvmx_mio_uart2_dlh {
@@ -5136,8 +3989,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_dlh_s cn52xx;
- struct cvmx_mio_uart2_dlh_s cn52xxp1;
};
union cvmx_mio_uart2_dll {
@@ -5151,8 +4002,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_dll_s cn52xx;
- struct cvmx_mio_uart2_dll_s cn52xxp1;
};
union cvmx_mio_uart2_far {
@@ -5166,8 +4015,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_uart2_far_s cn52xx;
- struct cvmx_mio_uart2_far_s cn52xxp1;
};
union cvmx_mio_uart2_fcr {
@@ -5191,8 +4038,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_fcr_s cn52xx;
- struct cvmx_mio_uart2_fcr_s cn52xxp1;
};
union cvmx_mio_uart2_htx {
@@ -5206,8 +4051,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_uart2_htx_s cn52xx;
- struct cvmx_mio_uart2_htx_s cn52xxp1;
};
union cvmx_mio_uart2_ier {
@@ -5231,8 +4074,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_ier_s cn52xx;
- struct cvmx_mio_uart2_ier_s cn52xxp1;
};
union cvmx_mio_uart2_iir {
@@ -5250,8 +4091,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_iir_s cn52xx;
- struct cvmx_mio_uart2_iir_s cn52xxp1;
};
union cvmx_mio_uart2_lcr {
@@ -5277,8 +4116,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_lcr_s cn52xx;
- struct cvmx_mio_uart2_lcr_s cn52xxp1;
};
union cvmx_mio_uart2_lsr {
@@ -5306,8 +4143,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_lsr_s cn52xx;
- struct cvmx_mio_uart2_lsr_s cn52xxp1;
};
union cvmx_mio_uart2_mcr {
@@ -5331,8 +4166,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_mio_uart2_mcr_s cn52xx;
- struct cvmx_mio_uart2_mcr_s cn52xxp1;
};
union cvmx_mio_uart2_msr {
@@ -5360,8 +4193,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_msr_s cn52xx;
- struct cvmx_mio_uart2_msr_s cn52xxp1;
};
union cvmx_mio_uart2_rbr {
@@ -5375,8 +4206,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_rbr_s cn52xx;
- struct cvmx_mio_uart2_rbr_s cn52xxp1;
};
union cvmx_mio_uart2_rfl {
@@ -5390,8 +4219,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_mio_uart2_rfl_s cn52xx;
- struct cvmx_mio_uart2_rfl_s cn52xxp1;
};
union cvmx_mio_uart2_rfw {
@@ -5409,8 +4236,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_mio_uart2_rfw_s cn52xx;
- struct cvmx_mio_uart2_rfw_s cn52xxp1;
};
union cvmx_mio_uart2_sbcr {
@@ -5424,8 +4249,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_uart2_sbcr_s cn52xx;
- struct cvmx_mio_uart2_sbcr_s cn52xxp1;
};
union cvmx_mio_uart2_scr {
@@ -5439,8 +4262,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_scr_s cn52xx;
- struct cvmx_mio_uart2_scr_s cn52xxp1;
};
union cvmx_mio_uart2_sfe {
@@ -5454,8 +4275,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_uart2_sfe_s cn52xx;
- struct cvmx_mio_uart2_sfe_s cn52xxp1;
};
union cvmx_mio_uart2_srr {
@@ -5473,8 +4292,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_mio_uart2_srr_s cn52xx;
- struct cvmx_mio_uart2_srr_s cn52xxp1;
};
union cvmx_mio_uart2_srt {
@@ -5488,8 +4305,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_mio_uart2_srt_s cn52xx;
- struct cvmx_mio_uart2_srt_s cn52xxp1;
};
union cvmx_mio_uart2_srts {
@@ -5503,8 +4318,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_mio_uart2_srts_s cn52xx;
- struct cvmx_mio_uart2_srts_s cn52xxp1;
};
union cvmx_mio_uart2_stt {
@@ -5518,8 +4331,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_mio_uart2_stt_s cn52xx;
- struct cvmx_mio_uart2_stt_s cn52xxp1;
};
union cvmx_mio_uart2_tfl {
@@ -5533,8 +4344,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_mio_uart2_tfl_s cn52xx;
- struct cvmx_mio_uart2_tfl_s cn52xxp1;
};
union cvmx_mio_uart2_tfr {
@@ -5548,8 +4357,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_tfr_s cn52xx;
- struct cvmx_mio_uart2_tfr_s cn52xxp1;
};
union cvmx_mio_uart2_thr {
@@ -5563,8 +4370,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_mio_uart2_thr_s cn52xx;
- struct cvmx_mio_uart2_thr_s cn52xxp1;
};
union cvmx_mio_uart2_usr {
@@ -5586,8 +4391,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_mio_uart2_usr_s cn52xx;
- struct cvmx_mio_uart2_usr_s cn52xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
index 3155e60..cd60d43 100644
--- a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -80,15 +80,6 @@
uint64_t reserved_4_63:60;
#endif
} cn52xx;
- struct cvmx_mixx_bist_cn52xx cn52xxp1;
- struct cvmx_mixx_bist_cn52xx cn56xx;
- struct cvmx_mixx_bist_cn52xx cn56xxp1;
- struct cvmx_mixx_bist_s cn61xx;
- struct cvmx_mixx_bist_s cn63xx;
- struct cvmx_mixx_bist_s cn63xxp1;
- struct cvmx_mixx_bist_s cn66xx;
- struct cvmx_mixx_bist_s cn68xx;
- struct cvmx_mixx_bist_s cn68xxp1;
};
union cvmx_mixx_ctl {
@@ -137,15 +128,6 @@
uint64_t reserved_8_63:56;
#endif
} cn52xx;
- struct cvmx_mixx_ctl_cn52xx cn52xxp1;
- struct cvmx_mixx_ctl_cn52xx cn56xx;
- struct cvmx_mixx_ctl_cn52xx cn56xxp1;
- struct cvmx_mixx_ctl_s cn61xx;
- struct cvmx_mixx_ctl_s cn63xx;
- struct cvmx_mixx_ctl_s cn63xxp1;
- struct cvmx_mixx_ctl_s cn66xx;
- struct cvmx_mixx_ctl_s cn68xx;
- struct cvmx_mixx_ctl_s cn68xxp1;
};
union cvmx_mixx_intena {
@@ -194,15 +176,6 @@
uint64_t reserved_7_63:57;
#endif
} cn52xx;
- struct cvmx_mixx_intena_cn52xx cn52xxp1;
- struct cvmx_mixx_intena_cn52xx cn56xx;
- struct cvmx_mixx_intena_cn52xx cn56xxp1;
- struct cvmx_mixx_intena_s cn61xx;
- struct cvmx_mixx_intena_s cn63xx;
- struct cvmx_mixx_intena_s cn63xxp1;
- struct cvmx_mixx_intena_s cn66xx;
- struct cvmx_mixx_intena_s cn68xx;
- struct cvmx_mixx_intena_s cn68xxp1;
};
union cvmx_mixx_ircnt {
@@ -216,16 +189,6 @@
uint64_t reserved_20_63:44;
#endif
} s;
- struct cvmx_mixx_ircnt_s cn52xx;
- struct cvmx_mixx_ircnt_s cn52xxp1;
- struct cvmx_mixx_ircnt_s cn56xx;
- struct cvmx_mixx_ircnt_s cn56xxp1;
- struct cvmx_mixx_ircnt_s cn61xx;
- struct cvmx_mixx_ircnt_s cn63xx;
- struct cvmx_mixx_ircnt_s cn63xxp1;
- struct cvmx_mixx_ircnt_s cn66xx;
- struct cvmx_mixx_ircnt_s cn68xx;
- struct cvmx_mixx_ircnt_s cn68xxp1;
};
union cvmx_mixx_irhwm {
@@ -241,16 +204,6 @@
uint64_t reserved_40_63:24;
#endif
} s;
- struct cvmx_mixx_irhwm_s cn52xx;
- struct cvmx_mixx_irhwm_s cn52xxp1;
- struct cvmx_mixx_irhwm_s cn56xx;
- struct cvmx_mixx_irhwm_s cn56xxp1;
- struct cvmx_mixx_irhwm_s cn61xx;
- struct cvmx_mixx_irhwm_s cn63xx;
- struct cvmx_mixx_irhwm_s cn63xxp1;
- struct cvmx_mixx_irhwm_s cn66xx;
- struct cvmx_mixx_irhwm_s cn68xx;
- struct cvmx_mixx_irhwm_s cn68xxp1;
};
union cvmx_mixx_iring1 {
@@ -283,15 +236,6 @@
uint64_t reserved_60_63:4;
#endif
} cn52xx;
- struct cvmx_mixx_iring1_cn52xx cn52xxp1;
- struct cvmx_mixx_iring1_cn52xx cn56xx;
- struct cvmx_mixx_iring1_cn52xx cn56xxp1;
- struct cvmx_mixx_iring1_s cn61xx;
- struct cvmx_mixx_iring1_s cn63xx;
- struct cvmx_mixx_iring1_s cn63xxp1;
- struct cvmx_mixx_iring1_s cn66xx;
- struct cvmx_mixx_iring1_s cn68xx;
- struct cvmx_mixx_iring1_s cn68xxp1;
};
union cvmx_mixx_iring2 {
@@ -309,16 +253,6 @@
uint64_t reserved_52_63:12;
#endif
} s;
- struct cvmx_mixx_iring2_s cn52xx;
- struct cvmx_mixx_iring2_s cn52xxp1;
- struct cvmx_mixx_iring2_s cn56xx;
- struct cvmx_mixx_iring2_s cn56xxp1;
- struct cvmx_mixx_iring2_s cn61xx;
- struct cvmx_mixx_iring2_s cn63xx;
- struct cvmx_mixx_iring2_s cn63xxp1;
- struct cvmx_mixx_iring2_s cn66xx;
- struct cvmx_mixx_iring2_s cn68xx;
- struct cvmx_mixx_iring2_s cn68xxp1;
};
union cvmx_mixx_isr {
@@ -367,15 +301,6 @@
uint64_t reserved_7_63:57;
#endif
} cn52xx;
- struct cvmx_mixx_isr_cn52xx cn52xxp1;
- struct cvmx_mixx_isr_cn52xx cn56xx;
- struct cvmx_mixx_isr_cn52xx cn56xxp1;
- struct cvmx_mixx_isr_s cn61xx;
- struct cvmx_mixx_isr_s cn63xx;
- struct cvmx_mixx_isr_s cn63xxp1;
- struct cvmx_mixx_isr_s cn66xx;
- struct cvmx_mixx_isr_s cn68xx;
- struct cvmx_mixx_isr_s cn68xxp1;
};
union cvmx_mixx_orcnt {
@@ -389,16 +314,6 @@
uint64_t reserved_20_63:44;
#endif
} s;
- struct cvmx_mixx_orcnt_s cn52xx;
- struct cvmx_mixx_orcnt_s cn52xxp1;
- struct cvmx_mixx_orcnt_s cn56xx;
- struct cvmx_mixx_orcnt_s cn56xxp1;
- struct cvmx_mixx_orcnt_s cn61xx;
- struct cvmx_mixx_orcnt_s cn63xx;
- struct cvmx_mixx_orcnt_s cn63xxp1;
- struct cvmx_mixx_orcnt_s cn66xx;
- struct cvmx_mixx_orcnt_s cn68xx;
- struct cvmx_mixx_orcnt_s cn68xxp1;
};
union cvmx_mixx_orhwm {
@@ -412,16 +327,6 @@
uint64_t reserved_20_63:44;
#endif
} s;
- struct cvmx_mixx_orhwm_s cn52xx;
- struct cvmx_mixx_orhwm_s cn52xxp1;
- struct cvmx_mixx_orhwm_s cn56xx;
- struct cvmx_mixx_orhwm_s cn56xxp1;
- struct cvmx_mixx_orhwm_s cn61xx;
- struct cvmx_mixx_orhwm_s cn63xx;
- struct cvmx_mixx_orhwm_s cn63xxp1;
- struct cvmx_mixx_orhwm_s cn66xx;
- struct cvmx_mixx_orhwm_s cn68xx;
- struct cvmx_mixx_orhwm_s cn68xxp1;
};
union cvmx_mixx_oring1 {
@@ -454,15 +359,6 @@
uint64_t reserved_60_63:4;
#endif
} cn52xx;
- struct cvmx_mixx_oring1_cn52xx cn52xxp1;
- struct cvmx_mixx_oring1_cn52xx cn56xx;
- struct cvmx_mixx_oring1_cn52xx cn56xxp1;
- struct cvmx_mixx_oring1_s cn61xx;
- struct cvmx_mixx_oring1_s cn63xx;
- struct cvmx_mixx_oring1_s cn63xxp1;
- struct cvmx_mixx_oring1_s cn66xx;
- struct cvmx_mixx_oring1_s cn68xx;
- struct cvmx_mixx_oring1_s cn68xxp1;
};
union cvmx_mixx_oring2 {
@@ -480,16 +376,6 @@
uint64_t reserved_52_63:12;
#endif
} s;
- struct cvmx_mixx_oring2_s cn52xx;
- struct cvmx_mixx_oring2_s cn52xxp1;
- struct cvmx_mixx_oring2_s cn56xx;
- struct cvmx_mixx_oring2_s cn56xxp1;
- struct cvmx_mixx_oring2_s cn61xx;
- struct cvmx_mixx_oring2_s cn63xx;
- struct cvmx_mixx_oring2_s cn63xxp1;
- struct cvmx_mixx_oring2_s cn66xx;
- struct cvmx_mixx_oring2_s cn68xx;
- struct cvmx_mixx_oring2_s cn68xxp1;
};
union cvmx_mixx_remcnt {
@@ -507,16 +393,6 @@
uint64_t reserved_52_63:12;
#endif
} s;
- struct cvmx_mixx_remcnt_s cn52xx;
- struct cvmx_mixx_remcnt_s cn52xxp1;
- struct cvmx_mixx_remcnt_s cn56xx;
- struct cvmx_mixx_remcnt_s cn56xxp1;
- struct cvmx_mixx_remcnt_s cn61xx;
- struct cvmx_mixx_remcnt_s cn63xx;
- struct cvmx_mixx_remcnt_s cn63xxp1;
- struct cvmx_mixx_remcnt_s cn66xx;
- struct cvmx_mixx_remcnt_s cn68xx;
- struct cvmx_mixx_remcnt_s cn68xxp1;
};
union cvmx_mixx_tsctl {
@@ -538,12 +414,6 @@
uint64_t reserved_21_63:43;
#endif
} s;
- struct cvmx_mixx_tsctl_s cn61xx;
- struct cvmx_mixx_tsctl_s cn63xx;
- struct cvmx_mixx_tsctl_s cn63xxp1;
- struct cvmx_mixx_tsctl_s cn66xx;
- struct cvmx_mixx_tsctl_s cn68xx;
- struct cvmx_mixx_tsctl_s cn68xxp1;
};
union cvmx_mixx_tstamp {
@@ -555,12 +425,6 @@
uint64_t tstamp:64;
#endif
} s;
- struct cvmx_mixx_tstamp_s cn61xx;
- struct cvmx_mixx_tstamp_s cn63xx;
- struct cvmx_mixx_tstamp_s cn63xxp1;
- struct cvmx_mixx_tstamp_s cn66xx;
- struct cvmx_mixx_tstamp_s cn68xx;
- struct cvmx_mixx_tstamp_s cn68xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 58114d4..6a51b1e 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -154,10 +154,6 @@
uint32_t reserved_18_31:14;
#endif
} s;
- struct cvmx_npei_bar1_indexx_s cn52xx;
- struct cvmx_npei_bar1_indexx_s cn52xxp1;
- struct cvmx_npei_bar1_indexx_s cn56xx;
- struct cvmx_npei_bar1_indexx_s cn56xxp1;
};
union cvmx_npei_bist_status {
@@ -485,7 +481,6 @@
uint64_t reserved_46_63:18;
#endif
} cn52xxp1;
- struct cvmx_npei_bist_status_cn52xx cn56xx;
struct cvmx_npei_bist_status_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_58_63:6;
@@ -648,8 +643,6 @@
uint64_t reserved_14_63:50;
#endif
} s;
- struct cvmx_npei_bist_status2_s cn52xx;
- struct cvmx_npei_bist_status2_s cn56xx;
};
union cvmx_npei_ctl_port0 {
@@ -693,10 +686,6 @@
uint64_t reserved_21_63:43;
#endif
} s;
- struct cvmx_npei_ctl_port0_s cn52xx;
- struct cvmx_npei_ctl_port0_s cn52xxp1;
- struct cvmx_npei_ctl_port0_s cn56xx;
- struct cvmx_npei_ctl_port0_s cn56xxp1;
};
union cvmx_npei_ctl_port1 {
@@ -740,10 +729,6 @@
uint64_t reserved_21_63:43;
#endif
} s;
- struct cvmx_npei_ctl_port1_s cn52xx;
- struct cvmx_npei_ctl_port1_s cn52xxp1;
- struct cvmx_npei_ctl_port1_s cn56xx;
- struct cvmx_npei_ctl_port1_s cn56xxp1;
};
union cvmx_npei_ctl_status {
@@ -773,7 +758,6 @@
uint64_t reserved_44_63:20;
#endif
} s;
- struct cvmx_npei_ctl_status_s cn52xx;
struct cvmx_npei_ctl_status_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_44_63:20;
@@ -799,7 +783,6 @@
uint64_t reserved_44_63:20;
#endif
} cn52xxp1;
- struct cvmx_npei_ctl_status_s cn56xx;
struct cvmx_npei_ctl_status_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_15_63:49;
@@ -848,10 +831,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_npei_ctl_status2_s cn52xx;
- struct cvmx_npei_ctl_status2_s cn52xxp1;
- struct cvmx_npei_ctl_status2_s cn56xx;
- struct cvmx_npei_ctl_status2_s cn56xxp1;
};
union cvmx_npei_data_out_cnt {
@@ -871,10 +850,6 @@
uint64_t reserved_44_63:20;
#endif
} s;
- struct cvmx_npei_data_out_cnt_s cn52xx;
- struct cvmx_npei_data_out_cnt_s cn52xxp1;
- struct cvmx_npei_data_out_cnt_s cn56xx;
- struct cvmx_npei_data_out_cnt_s cn56xxp1;
};
union cvmx_npei_dbg_data {
@@ -919,7 +894,6 @@
uint64_t reserved_29_63:35;
#endif
} cn52xx;
- struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
struct cvmx_npei_dbg_data_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
@@ -941,7 +915,6 @@
uint64_t reserved_29_63:35;
#endif
} cn56xx;
- struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
};
union cvmx_npei_dbg_select {
@@ -955,10 +928,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_npei_dbg_select_s cn52xx;
- struct cvmx_npei_dbg_select_s cn52xxp1;
- struct cvmx_npei_dbg_select_s cn56xx;
- struct cvmx_npei_dbg_select_s cn56xxp1;
};
union cvmx_npei_dmax_counts {
@@ -974,10 +943,6 @@
uint64_t reserved_39_63:25;
#endif
} s;
- struct cvmx_npei_dmax_counts_s cn52xx;
- struct cvmx_npei_dmax_counts_s cn52xxp1;
- struct cvmx_npei_dmax_counts_s cn56xx;
- struct cvmx_npei_dmax_counts_s cn56xxp1;
};
union cvmx_npei_dmax_dbell {
@@ -991,10 +956,6 @@
uint32_t reserved_16_31:16;
#endif
} s;
- struct cvmx_npei_dmax_dbell_s cn52xx;
- struct cvmx_npei_dmax_dbell_s cn52xxp1;
- struct cvmx_npei_dmax_dbell_s cn56xx;
- struct cvmx_npei_dmax_dbell_s cn56xxp1;
};
union cvmx_npei_dmax_ibuff_saddr {
@@ -1012,7 +973,6 @@
uint64_t reserved_37_63:27;
#endif
} s;
- struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63:28;
@@ -1024,8 +984,6 @@
uint64_t reserved_36_63:28;
#endif
} cn52xxp1;
- struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
- struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
};
union cvmx_npei_dmax_naddr {
@@ -1039,10 +997,6 @@
uint64_t reserved_36_63:28;
#endif
} s;
- struct cvmx_npei_dmax_naddr_s cn52xx;
- struct cvmx_npei_dmax_naddr_s cn52xxp1;
- struct cvmx_npei_dmax_naddr_s cn56xx;
- struct cvmx_npei_dmax_naddr_s cn56xxp1;
};
union cvmx_npei_dma0_int_level {
@@ -1056,10 +1010,6 @@
uint64_t time:32;
#endif
} s;
- struct cvmx_npei_dma0_int_level_s cn52xx;
- struct cvmx_npei_dma0_int_level_s cn52xxp1;
- struct cvmx_npei_dma0_int_level_s cn56xx;
- struct cvmx_npei_dma0_int_level_s cn56xxp1;
};
union cvmx_npei_dma1_int_level {
@@ -1073,10 +1023,6 @@
uint64_t time:32;
#endif
} s;
- struct cvmx_npei_dma1_int_level_s cn52xx;
- struct cvmx_npei_dma1_int_level_s cn52xxp1;
- struct cvmx_npei_dma1_int_level_s cn56xx;
- struct cvmx_npei_dma1_int_level_s cn56xxp1;
};
union cvmx_npei_dma_cnts {
@@ -1090,10 +1036,6 @@
uint64_t dma1:32;
#endif
} s;
- struct cvmx_npei_dma_cnts_s cn52xx;
- struct cvmx_npei_dma_cnts_s cn52xxp1;
- struct cvmx_npei_dma_cnts_s cn56xx;
- struct cvmx_npei_dma_cnts_s cn56xxp1;
};
union cvmx_npei_dma_control {
@@ -1137,7 +1079,6 @@
uint64_t reserved_40_63:24;
#endif
} s;
- struct cvmx_npei_dma_control_s cn52xx;
struct cvmx_npei_dma_control_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_38_63:26;
@@ -1173,7 +1114,6 @@
uint64_t reserved_38_63:26;
#endif
} cn52xxp1;
- struct cvmx_npei_dma_control_s cn56xx;
struct cvmx_npei_dma_control_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_39_63:25;
@@ -1250,8 +1190,6 @@
uint64_t dma_arb:1;
#endif
} s;
- struct cvmx_npei_dma_pcie_req_num_s cn52xx;
- struct cvmx_npei_dma_pcie_req_num_s cn56xx;
};
union cvmx_npei_dma_state1 {
@@ -1273,7 +1211,6 @@
uint64_t reserved_40_63:24;
#endif
} s;
- struct cvmx_npei_dma_state1_s cn52xx;
};
union cvmx_npei_dma_state1_p1 {
@@ -1332,7 +1269,6 @@
uint64_t reserved_60_63:4;
#endif
} cn52xxp1;
- struct cvmx_npei_dma_state1_p1_s cn56xxp1;
};
union cvmx_npei_dma_state2 {
@@ -1354,7 +1290,6 @@
uint64_t reserved_28_63:36;
#endif
} s;
- struct cvmx_npei_dma_state2_s cn52xx;
};
union cvmx_npei_dma_state2_p1 {
@@ -1393,7 +1328,6 @@
uint64_t reserved_45_63:19;
#endif
} cn52xxp1;
- struct cvmx_npei_dma_state2_p1_s cn56xxp1;
};
union cvmx_npei_dma_state3_p1 {
@@ -1413,8 +1347,6 @@
uint64_t reserved_60_63:4;
#endif
} s;
- struct cvmx_npei_dma_state3_p1_s cn52xxp1;
- struct cvmx_npei_dma_state3_p1_s cn56xxp1;
};
union cvmx_npei_dma_state4_p1 {
@@ -1434,8 +1366,6 @@
uint64_t reserved_52_63:12;
#endif
} s;
- struct cvmx_npei_dma_state4_p1_s cn52xxp1;
- struct cvmx_npei_dma_state4_p1_s cn56xxp1;
};
union cvmx_npei_dma_state5_p1 {
@@ -1451,7 +1381,6 @@
uint64_t reserved_28_63:36;
#endif
} s;
- struct cvmx_npei_dma_state5_p1_s cn56xxp1;
};
union cvmx_npei_int_a_enb {
@@ -1483,7 +1412,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_npei_int_a_enb_s cn52xx;
struct cvmx_npei_int_a_enb_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
@@ -1495,7 +1423,6 @@
uint64_t reserved_2_63:62;
#endif
} cn52xxp1;
- struct cvmx_npei_int_a_enb_s cn56xx;
};
union cvmx_npei_int_a_enb2 {
@@ -1527,7 +1454,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_npei_int_a_enb2_s cn52xx;
struct cvmx_npei_int_a_enb2_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
@@ -1539,7 +1465,6 @@
uint64_t reserved_2_63:62;
#endif
} cn52xxp1;
- struct cvmx_npei_int_a_enb2_s cn56xx;
};
union cvmx_npei_int_a_sum {
@@ -1571,7 +1496,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_npei_int_a_sum_s cn52xx;
struct cvmx_npei_int_a_sum_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
@@ -1583,7 +1507,6 @@
uint64_t reserved_2_63:62;
#endif
} cn52xxp1;
- struct cvmx_npei_int_a_sum_s cn56xx;
};
union cvmx_npei_int_enb {
@@ -1721,7 +1644,6 @@
uint64_t mio_inta:1;
#endif
} s;
- struct cvmx_npei_int_enb_s cn52xx;
struct cvmx_npei_int_enb_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t mio_inta:1;
@@ -1855,7 +1777,6 @@
uint64_t mio_inta:1;
#endif
} cn52xxp1;
- struct cvmx_npei_int_enb_s cn56xx;
struct cvmx_npei_int_enb_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t mio_inta:1;
@@ -2122,7 +2043,6 @@
uint64_t reserved_62_63:2;
#endif
} s;
- struct cvmx_npei_int_enb2_s cn52xx;
struct cvmx_npei_int_enb2_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_62_63:2;
@@ -2254,7 +2174,6 @@
uint64_t reserved_62_63:2;
#endif
} cn52xxp1;
- struct cvmx_npei_int_enb2_s cn56xx;
struct cvmx_npei_int_enb2_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_61_63:3;
@@ -2399,9 +2318,6 @@
uint64_t reserved_12_63:52;
#endif
} s;
- struct cvmx_npei_int_info_s cn52xx;
- struct cvmx_npei_int_info_s cn56xx;
- struct cvmx_npei_int_info_s cn56xxp1;
};
union cvmx_npei_int_sum {
@@ -2539,7 +2455,6 @@
uint64_t mio_inta:1;
#endif
} s;
- struct cvmx_npei_int_sum_s cn52xx;
struct cvmx_npei_int_sum_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t mio_inta:1;
@@ -2667,7 +2582,6 @@
uint64_t mio_inta:1;
#endif
} cn52xxp1;
- struct cvmx_npei_int_sum_s cn56xx;
struct cvmx_npei_int_sum_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t mio_inta:1;
@@ -2924,9 +2838,6 @@
uint64_t mio_inta:1;
#endif
} s;
- struct cvmx_npei_int_sum2_s cn52xx;
- struct cvmx_npei_int_sum2_s cn52xxp1;
- struct cvmx_npei_int_sum2_s cn56xx;
};
union cvmx_npei_last_win_rdata0 {
@@ -2938,10 +2849,6 @@
uint64_t data:64;
#endif
} s;
- struct cvmx_npei_last_win_rdata0_s cn52xx;
- struct cvmx_npei_last_win_rdata0_s cn52xxp1;
- struct cvmx_npei_last_win_rdata0_s cn56xx;
- struct cvmx_npei_last_win_rdata0_s cn56xxp1;
};
union cvmx_npei_last_win_rdata1 {
@@ -2953,10 +2860,6 @@
uint64_t data:64;
#endif
} s;
- struct cvmx_npei_last_win_rdata1_s cn52xx;
- struct cvmx_npei_last_win_rdata1_s cn52xxp1;
- struct cvmx_npei_last_win_rdata1_s cn56xx;
- struct cvmx_npei_last_win_rdata1_s cn56xxp1;
};
union cvmx_npei_mem_access_ctl {
@@ -2972,10 +2875,6 @@
uint64_t reserved_14_63:50;
#endif
} s;
- struct cvmx_npei_mem_access_ctl_s cn52xx;
- struct cvmx_npei_mem_access_ctl_s cn52xxp1;
- struct cvmx_npei_mem_access_ctl_s cn56xx;
- struct cvmx_npei_mem_access_ctl_s cn56xxp1;
};
union cvmx_npei_mem_access_subidx {
@@ -3007,10 +2906,6 @@
uint64_t reserved_42_63:22;
#endif
} s;
- struct cvmx_npei_mem_access_subidx_s cn52xx;
- struct cvmx_npei_mem_access_subidx_s cn52xxp1;
- struct cvmx_npei_mem_access_subidx_s cn56xx;
- struct cvmx_npei_mem_access_subidx_s cn56xxp1;
};
union cvmx_npei_msi_enb0 {
@@ -3022,10 +2917,6 @@
uint64_t enb:64;
#endif
} s;
- struct cvmx_npei_msi_enb0_s cn52xx;
- struct cvmx_npei_msi_enb0_s cn52xxp1;
- struct cvmx_npei_msi_enb0_s cn56xx;
- struct cvmx_npei_msi_enb0_s cn56xxp1;
};
union cvmx_npei_msi_enb1 {
@@ -3037,10 +2928,6 @@
uint64_t enb:64;
#endif
} s;
- struct cvmx_npei_msi_enb1_s cn52xx;
- struct cvmx_npei_msi_enb1_s cn52xxp1;
- struct cvmx_npei_msi_enb1_s cn56xx;
- struct cvmx_npei_msi_enb1_s cn56xxp1;
};
union cvmx_npei_msi_enb2 {
@@ -3052,10 +2939,6 @@
uint64_t enb:64;
#endif
} s;
- struct cvmx_npei_msi_enb2_s cn52xx;
- struct cvmx_npei_msi_enb2_s cn52xxp1;
- struct cvmx_npei_msi_enb2_s cn56xx;
- struct cvmx_npei_msi_enb2_s cn56xxp1;
};
union cvmx_npei_msi_enb3 {
@@ -3067,10 +2950,6 @@
uint64_t enb:64;
#endif
} s;
- struct cvmx_npei_msi_enb3_s cn52xx;
- struct cvmx_npei_msi_enb3_s cn52xxp1;
- struct cvmx_npei_msi_enb3_s cn56xx;
- struct cvmx_npei_msi_enb3_s cn56xxp1;
};
union cvmx_npei_msi_rcv0 {
@@ -3082,10 +2961,6 @@
uint64_t intr:64;
#endif
} s;
- struct cvmx_npei_msi_rcv0_s cn52xx;
- struct cvmx_npei_msi_rcv0_s cn52xxp1;
- struct cvmx_npei_msi_rcv0_s cn56xx;
- struct cvmx_npei_msi_rcv0_s cn56xxp1;
};
union cvmx_npei_msi_rcv1 {
@@ -3097,10 +2972,6 @@
uint64_t intr:64;
#endif
} s;
- struct cvmx_npei_msi_rcv1_s cn52xx;
- struct cvmx_npei_msi_rcv1_s cn52xxp1;
- struct cvmx_npei_msi_rcv1_s cn56xx;
- struct cvmx_npei_msi_rcv1_s cn56xxp1;
};
union cvmx_npei_msi_rcv2 {
@@ -3112,10 +2983,6 @@
uint64_t intr:64;
#endif
} s;
- struct cvmx_npei_msi_rcv2_s cn52xx;
- struct cvmx_npei_msi_rcv2_s cn52xxp1;
- struct cvmx_npei_msi_rcv2_s cn56xx;
- struct cvmx_npei_msi_rcv2_s cn56xxp1;
};
union cvmx_npei_msi_rcv3 {
@@ -3127,10 +2994,6 @@
uint64_t intr:64;
#endif
} s;
- struct cvmx_npei_msi_rcv3_s cn52xx;
- struct cvmx_npei_msi_rcv3_s cn52xxp1;
- struct cvmx_npei_msi_rcv3_s cn56xx;
- struct cvmx_npei_msi_rcv3_s cn56xxp1;
};
union cvmx_npei_msi_rd_map {
@@ -3146,10 +3009,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_npei_msi_rd_map_s cn52xx;
- struct cvmx_npei_msi_rd_map_s cn52xxp1;
- struct cvmx_npei_msi_rd_map_s cn56xx;
- struct cvmx_npei_msi_rd_map_s cn56xxp1;
};
union cvmx_npei_msi_w1c_enb0 {
@@ -3161,8 +3020,6 @@
uint64_t clr:64;
#endif
} s;
- struct cvmx_npei_msi_w1c_enb0_s cn52xx;
- struct cvmx_npei_msi_w1c_enb0_s cn56xx;
};
union cvmx_npei_msi_w1c_enb1 {
@@ -3174,8 +3031,6 @@
uint64_t clr:64;
#endif
} s;
- struct cvmx_npei_msi_w1c_enb1_s cn52xx;
- struct cvmx_npei_msi_w1c_enb1_s cn56xx;
};
union cvmx_npei_msi_w1c_enb2 {
@@ -3187,8 +3042,6 @@
uint64_t clr:64;
#endif
} s;
- struct cvmx_npei_msi_w1c_enb2_s cn52xx;
- struct cvmx_npei_msi_w1c_enb2_s cn56xx;
};
union cvmx_npei_msi_w1c_enb3 {
@@ -3200,8 +3053,6 @@
uint64_t clr:64;
#endif
} s;
- struct cvmx_npei_msi_w1c_enb3_s cn52xx;
- struct cvmx_npei_msi_w1c_enb3_s cn56xx;
};
union cvmx_npei_msi_w1s_enb0 {
@@ -3213,8 +3064,6 @@
uint64_t set:64;
#endif
} s;
- struct cvmx_npei_msi_w1s_enb0_s cn52xx;
- struct cvmx_npei_msi_w1s_enb0_s cn56xx;
};
union cvmx_npei_msi_w1s_enb1 {
@@ -3226,8 +3075,6 @@
uint64_t set:64;
#endif
} s;
- struct cvmx_npei_msi_w1s_enb1_s cn52xx;
- struct cvmx_npei_msi_w1s_enb1_s cn56xx;
};
union cvmx_npei_msi_w1s_enb2 {
@@ -3239,8 +3086,6 @@
uint64_t set:64;
#endif
} s;
- struct cvmx_npei_msi_w1s_enb2_s cn52xx;
- struct cvmx_npei_msi_w1s_enb2_s cn56xx;
};
union cvmx_npei_msi_w1s_enb3 {
@@ -3252,8 +3097,6 @@
uint64_t set:64;
#endif
} s;
- struct cvmx_npei_msi_w1s_enb3_s cn52xx;
- struct cvmx_npei_msi_w1s_enb3_s cn56xx;
};
union cvmx_npei_msi_wr_map {
@@ -3269,10 +3112,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_npei_msi_wr_map_s cn52xx;
- struct cvmx_npei_msi_wr_map_s cn52xxp1;
- struct cvmx_npei_msi_wr_map_s cn56xx;
- struct cvmx_npei_msi_wr_map_s cn56xxp1;
};
union cvmx_npei_pcie_credit_cnt {
@@ -3296,8 +3135,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_npei_pcie_credit_cnt_s cn52xx;
- struct cvmx_npei_pcie_credit_cnt_s cn56xx;
};
union cvmx_npei_pcie_msi_rcv {
@@ -3311,10 +3148,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_npei_pcie_msi_rcv_s cn52xx;
- struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
- struct cvmx_npei_pcie_msi_rcv_s cn56xx;
- struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
};
union cvmx_npei_pcie_msi_rcv_b1 {
@@ -3330,10 +3163,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
- struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
- struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
- struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
};
union cvmx_npei_pcie_msi_rcv_b2 {
@@ -3349,10 +3178,6 @@
uint64_t reserved_24_63:40;
#endif
} s;
- struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
- struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
- struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
- struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
};
union cvmx_npei_pcie_msi_rcv_b3 {
@@ -3368,10 +3193,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
- struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
- struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
- struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
};
union cvmx_npei_pktx_cnts {
@@ -3387,8 +3208,6 @@
uint64_t reserved_54_63:10;
#endif
} s;
- struct cvmx_npei_pktx_cnts_s cn52xx;
- struct cvmx_npei_pktx_cnts_s cn56xx;
};
union cvmx_npei_pktx_in_bp {
@@ -3402,8 +3221,6 @@
uint64_t wmark:32;
#endif
} s;
- struct cvmx_npei_pktx_in_bp_s cn52xx;
- struct cvmx_npei_pktx_in_bp_s cn56xx;
};
union cvmx_npei_pktx_instr_baddr {
@@ -3417,8 +3234,6 @@
uint64_t addr:61;
#endif
} s;
- struct cvmx_npei_pktx_instr_baddr_s cn52xx;
- struct cvmx_npei_pktx_instr_baddr_s cn56xx;
};
union cvmx_npei_pktx_instr_baoff_dbell {
@@ -3432,8 +3247,6 @@
uint64_t aoff:32;
#endif
} s;
- struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
- struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
};
union cvmx_npei_pktx_instr_fifo_rsize {
@@ -3453,8 +3266,6 @@
uint64_t max:9;
#endif
} s;
- struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
- struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
};
union cvmx_npei_pktx_instr_header {
@@ -3490,8 +3301,6 @@
uint64_t reserved_44_63:20;
#endif
} s;
- struct cvmx_npei_pktx_instr_header_s cn52xx;
- struct cvmx_npei_pktx_instr_header_s cn56xx;
};
union cvmx_npei_pktx_slist_baddr {
@@ -3505,8 +3314,6 @@
uint64_t addr:60;
#endif
} s;
- struct cvmx_npei_pktx_slist_baddr_s cn52xx;
- struct cvmx_npei_pktx_slist_baddr_s cn56xx;
};
union cvmx_npei_pktx_slist_baoff_dbell {
@@ -3520,8 +3327,6 @@
uint64_t aoff:32;
#endif
} s;
- struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
- struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
};
union cvmx_npei_pktx_slist_fifo_rsize {
@@ -3535,8 +3340,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
- struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
};
union cvmx_npei_pkt_cnt_int {
@@ -3550,8 +3353,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_cnt_int_s cn52xx;
- struct cvmx_npei_pkt_cnt_int_s cn56xx;
};
union cvmx_npei_pkt_cnt_int_enb {
@@ -3565,8 +3366,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
- struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
};
union cvmx_npei_pkt_data_out_es {
@@ -3578,8 +3377,6 @@
uint64_t es:64;
#endif
} s;
- struct cvmx_npei_pkt_data_out_es_s cn52xx;
- struct cvmx_npei_pkt_data_out_es_s cn56xx;
};
union cvmx_npei_pkt_data_out_ns {
@@ -3593,8 +3390,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_data_out_ns_s cn52xx;
- struct cvmx_npei_pkt_data_out_ns_s cn56xx;
};
union cvmx_npei_pkt_data_out_ror {
@@ -3608,8 +3403,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_data_out_ror_s cn52xx;
- struct cvmx_npei_pkt_data_out_ror_s cn56xx;
};
union cvmx_npei_pkt_dpaddr {
@@ -3623,8 +3416,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_dpaddr_s cn52xx;
- struct cvmx_npei_pkt_dpaddr_s cn56xx;
};
union cvmx_npei_pkt_in_bp {
@@ -3638,8 +3429,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_in_bp_s cn52xx;
- struct cvmx_npei_pkt_in_bp_s cn56xx;
};
union cvmx_npei_pkt_in_donex_cnts {
@@ -3653,8 +3442,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
- struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
};
union cvmx_npei_pkt_in_instr_counts {
@@ -3668,8 +3455,6 @@
uint64_t wr_cnt:32;
#endif
} s;
- struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
- struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
};
union cvmx_npei_pkt_in_pcie_port {
@@ -3681,8 +3466,6 @@
uint64_t pp:64;
#endif
} s;
- struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
- struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
};
union cvmx_npei_pkt_input_control {
@@ -3712,8 +3495,6 @@
uint64_t reserved_23_63:41;
#endif
} s;
- struct cvmx_npei_pkt_input_control_s cn52xx;
- struct cvmx_npei_pkt_input_control_s cn56xx;
};
union cvmx_npei_pkt_instr_enb {
@@ -3727,8 +3508,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_instr_enb_s cn52xx;
- struct cvmx_npei_pkt_instr_enb_s cn56xx;
};
union cvmx_npei_pkt_instr_rd_size {
@@ -3740,8 +3519,6 @@
uint64_t rdsize:64;
#endif
} s;
- struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
- struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
};
union cvmx_npei_pkt_instr_size {
@@ -3755,8 +3532,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_instr_size_s cn52xx;
- struct cvmx_npei_pkt_instr_size_s cn56xx;
};
union cvmx_npei_pkt_int_levels {
@@ -3772,8 +3547,6 @@
uint64_t reserved_54_63:10;
#endif
} s;
- struct cvmx_npei_pkt_int_levels_s cn52xx;
- struct cvmx_npei_pkt_int_levels_s cn56xx;
};
union cvmx_npei_pkt_iptr {
@@ -3787,8 +3560,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_iptr_s cn52xx;
- struct cvmx_npei_pkt_iptr_s cn56xx;
};
union cvmx_npei_pkt_out_bmode {
@@ -3802,8 +3573,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_out_bmode_s cn52xx;
- struct cvmx_npei_pkt_out_bmode_s cn56xx;
};
union cvmx_npei_pkt_out_enb {
@@ -3817,8 +3586,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_out_enb_s cn52xx;
- struct cvmx_npei_pkt_out_enb_s cn56xx;
};
union cvmx_npei_pkt_output_wmark {
@@ -3832,8 +3599,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_output_wmark_s cn52xx;
- struct cvmx_npei_pkt_output_wmark_s cn56xx;
};
union cvmx_npei_pkt_pcie_port {
@@ -3845,8 +3610,6 @@
uint64_t pp:64;
#endif
} s;
- struct cvmx_npei_pkt_pcie_port_s cn52xx;
- struct cvmx_npei_pkt_pcie_port_s cn56xx;
};
union cvmx_npei_pkt_port_in_rst {
@@ -3860,8 +3623,6 @@
uint64_t in_rst:32;
#endif
} s;
- struct cvmx_npei_pkt_port_in_rst_s cn52xx;
- struct cvmx_npei_pkt_port_in_rst_s cn56xx;
};
union cvmx_npei_pkt_slist_es {
@@ -3873,8 +3634,6 @@
uint64_t es:64;
#endif
} s;
- struct cvmx_npei_pkt_slist_es_s cn52xx;
- struct cvmx_npei_pkt_slist_es_s cn56xx;
};
union cvmx_npei_pkt_slist_id_size {
@@ -3890,8 +3649,6 @@
uint64_t reserved_23_63:41;
#endif
} s;
- struct cvmx_npei_pkt_slist_id_size_s cn52xx;
- struct cvmx_npei_pkt_slist_id_size_s cn56xx;
};
union cvmx_npei_pkt_slist_ns {
@@ -3905,8 +3662,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_slist_ns_s cn52xx;
- struct cvmx_npei_pkt_slist_ns_s cn56xx;
};
union cvmx_npei_pkt_slist_ror {
@@ -3920,8 +3675,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_slist_ror_s cn52xx;
- struct cvmx_npei_pkt_slist_ror_s cn56xx;
};
union cvmx_npei_pkt_time_int {
@@ -3935,8 +3688,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_time_int_s cn52xx;
- struct cvmx_npei_pkt_time_int_s cn56xx;
};
union cvmx_npei_pkt_time_int_enb {
@@ -3950,8 +3701,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_pkt_time_int_enb_s cn52xx;
- struct cvmx_npei_pkt_time_int_enb_s cn56xx;
};
union cvmx_npei_rsl_int_blocks {
@@ -4019,10 +3768,6 @@
uint64_t reserved_31_63:33;
#endif
} s;
- struct cvmx_npei_rsl_int_blocks_s cn52xx;
- struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
- struct cvmx_npei_rsl_int_blocks_s cn56xx;
- struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
};
union cvmx_npei_scratch_1 {
@@ -4034,10 +3779,6 @@
uint64_t data:64;
#endif
} s;
- struct cvmx_npei_scratch_1_s cn52xx;
- struct cvmx_npei_scratch_1_s cn52xxp1;
- struct cvmx_npei_scratch_1_s cn56xx;
- struct cvmx_npei_scratch_1_s cn56xxp1;
};
union cvmx_npei_state1 {
@@ -4055,10 +3796,6 @@
uint64_t cpl1:12;
#endif
} s;
- struct cvmx_npei_state1_s cn52xx;
- struct cvmx_npei_state1_s cn52xxp1;
- struct cvmx_npei_state1_s cn56xx;
- struct cvmx_npei_state1_s cn56xxp1;
};
union cvmx_npei_state2 {
@@ -4082,10 +3819,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_npei_state2_s cn52xx;
- struct cvmx_npei_state2_s cn52xxp1;
- struct cvmx_npei_state2_s cn56xx;
- struct cvmx_npei_state2_s cn56xxp1;
};
union cvmx_npei_state3 {
@@ -4105,10 +3838,6 @@
uint64_t reserved_56_63:8;
#endif
} s;
- struct cvmx_npei_state3_s cn52xx;
- struct cvmx_npei_state3_s cn52xxp1;
- struct cvmx_npei_state3_s cn56xx;
- struct cvmx_npei_state3_s cn56xxp1;
};
union cvmx_npei_win_rd_addr {
@@ -4126,10 +3855,6 @@
uint64_t reserved_51_63:13;
#endif
} s;
- struct cvmx_npei_win_rd_addr_s cn52xx;
- struct cvmx_npei_win_rd_addr_s cn52xxp1;
- struct cvmx_npei_win_rd_addr_s cn56xx;
- struct cvmx_npei_win_rd_addr_s cn56xxp1;
};
union cvmx_npei_win_rd_data {
@@ -4141,10 +3866,6 @@
uint64_t rd_data:64;
#endif
} s;
- struct cvmx_npei_win_rd_data_s cn52xx;
- struct cvmx_npei_win_rd_data_s cn52xxp1;
- struct cvmx_npei_win_rd_data_s cn56xx;
- struct cvmx_npei_win_rd_data_s cn56xxp1;
};
union cvmx_npei_win_wr_addr {
@@ -4162,10 +3883,6 @@
uint64_t reserved_49_63:15;
#endif
} s;
- struct cvmx_npei_win_wr_addr_s cn52xx;
- struct cvmx_npei_win_wr_addr_s cn52xxp1;
- struct cvmx_npei_win_wr_addr_s cn56xx;
- struct cvmx_npei_win_wr_addr_s cn56xxp1;
};
union cvmx_npei_win_wr_data {
@@ -4177,10 +3894,6 @@
uint64_t wr_data:64;
#endif
} s;
- struct cvmx_npei_win_wr_data_s cn52xx;
- struct cvmx_npei_win_wr_data_s cn52xxp1;
- struct cvmx_npei_win_wr_data_s cn56xx;
- struct cvmx_npei_win_wr_data_s cn56xxp1;
};
union cvmx_npei_win_wr_mask {
@@ -4194,10 +3907,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_npei_win_wr_mask_s cn52xx;
- struct cvmx_npei_win_wr_mask_s cn52xxp1;
- struct cvmx_npei_win_wr_mask_s cn56xx;
- struct cvmx_npei_win_wr_mask_s cn56xxp1;
};
union cvmx_npei_window_ctl {
@@ -4211,10 +3920,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npei_window_ctl_s cn52xx;
- struct cvmx_npei_window_ctl_s cn52xxp1;
- struct cvmx_npei_window_ctl_s cn56xx;
- struct cvmx_npei_window_ctl_s cn56xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
index 129bb25..ba4967f 100644
--- a/arch/mips/include/asm/octeon/cvmx-npi-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -160,13 +160,6 @@
uint64_t baddr:61;
#endif
} s;
- struct cvmx_npi_base_addr_inputx_s cn30xx;
- struct cvmx_npi_base_addr_inputx_s cn31xx;
- struct cvmx_npi_base_addr_inputx_s cn38xx;
- struct cvmx_npi_base_addr_inputx_s cn38xxp2;
- struct cvmx_npi_base_addr_inputx_s cn50xx;
- struct cvmx_npi_base_addr_inputx_s cn58xx;
- struct cvmx_npi_base_addr_inputx_s cn58xxp1;
};
union cvmx_npi_base_addr_outputx {
@@ -180,13 +173,6 @@
uint64_t baddr:61;
#endif
} s;
- struct cvmx_npi_base_addr_outputx_s cn30xx;
- struct cvmx_npi_base_addr_outputx_s cn31xx;
- struct cvmx_npi_base_addr_outputx_s cn38xx;
- struct cvmx_npi_base_addr_outputx_s cn38xxp2;
- struct cvmx_npi_base_addr_outputx_s cn50xx;
- struct cvmx_npi_base_addr_outputx_s cn58xx;
- struct cvmx_npi_base_addr_outputx_s cn58xxp1;
};
union cvmx_npi_bist_status {
@@ -281,9 +267,6 @@
uint64_t reserved_20_63:44;
#endif
} cn30xx;
- struct cvmx_npi_bist_status_s cn31xx;
- struct cvmx_npi_bist_status_s cn38xx;
- struct cvmx_npi_bist_status_s cn38xxp2;
struct cvmx_npi_bist_status_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -329,8 +312,6 @@
uint64_t reserved_20_63:44;
#endif
} cn50xx;
- struct cvmx_npi_bist_status_s cn58xx;
- struct cvmx_npi_bist_status_s cn58xxp1;
};
union cvmx_npi_buff_size_outputx {
@@ -346,13 +327,6 @@
uint64_t reserved_23_63:41;
#endif
} s;
- struct cvmx_npi_buff_size_outputx_s cn30xx;
- struct cvmx_npi_buff_size_outputx_s cn31xx;
- struct cvmx_npi_buff_size_outputx_s cn38xx;
- struct cvmx_npi_buff_size_outputx_s cn38xxp2;
- struct cvmx_npi_buff_size_outputx_s cn50xx;
- struct cvmx_npi_buff_size_outputx_s cn58xx;
- struct cvmx_npi_buff_size_outputx_s cn58xxp1;
};
union cvmx_npi_comp_ctl {
@@ -368,9 +342,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_npi_comp_ctl_s cn50xx;
- struct cvmx_npi_comp_ctl_s cn58xx;
- struct cvmx_npi_comp_ctl_s cn58xxp1;
};
union cvmx_npi_ctl_status {
@@ -498,11 +469,6 @@
uint64_t reserved_63_63:1;
#endif
} cn31xx;
- struct cvmx_npi_ctl_status_s cn38xx;
- struct cvmx_npi_ctl_status_s cn38xxp2;
- struct cvmx_npi_ctl_status_cn31xx cn50xx;
- struct cvmx_npi_ctl_status_s cn58xx;
- struct cvmx_npi_ctl_status_s cn58xxp1;
};
union cvmx_npi_dbg_select {
@@ -516,13 +482,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_npi_dbg_select_s cn30xx;
- struct cvmx_npi_dbg_select_s cn31xx;
- struct cvmx_npi_dbg_select_s cn38xx;
- struct cvmx_npi_dbg_select_s cn38xxp2;
- struct cvmx_npi_dbg_select_s cn50xx;
- struct cvmx_npi_dbg_select_s cn58xx;
- struct cvmx_npi_dbg_select_s cn58xxp1;
};
union cvmx_npi_dma_control {
@@ -558,13 +517,6 @@
uint64_t reserved_36_63:28;
#endif
} s;
- struct cvmx_npi_dma_control_s cn30xx;
- struct cvmx_npi_dma_control_s cn31xx;
- struct cvmx_npi_dma_control_s cn38xx;
- struct cvmx_npi_dma_control_s cn38xxp2;
- struct cvmx_npi_dma_control_s cn50xx;
- struct cvmx_npi_dma_control_s cn58xx;
- struct cvmx_npi_dma_control_s cn58xxp1;
};
union cvmx_npi_dma_highp_counts {
@@ -580,13 +532,6 @@
uint64_t reserved_39_63:25;
#endif
} s;
- struct cvmx_npi_dma_highp_counts_s cn30xx;
- struct cvmx_npi_dma_highp_counts_s cn31xx;
- struct cvmx_npi_dma_highp_counts_s cn38xx;
- struct cvmx_npi_dma_highp_counts_s cn38xxp2;
- struct cvmx_npi_dma_highp_counts_s cn50xx;
- struct cvmx_npi_dma_highp_counts_s cn58xx;
- struct cvmx_npi_dma_highp_counts_s cn58xxp1;
};
union cvmx_npi_dma_highp_naddr {
@@ -602,13 +547,6 @@
uint64_t reserved_40_63:24;
#endif
} s;
- struct cvmx_npi_dma_highp_naddr_s cn30xx;
- struct cvmx_npi_dma_highp_naddr_s cn31xx;
- struct cvmx_npi_dma_highp_naddr_s cn38xx;
- struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
- struct cvmx_npi_dma_highp_naddr_s cn50xx;
- struct cvmx_npi_dma_highp_naddr_s cn58xx;
- struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
};
union cvmx_npi_dma_lowp_counts {
@@ -624,13 +562,6 @@
uint64_t reserved_39_63:25;
#endif
} s;
- struct cvmx_npi_dma_lowp_counts_s cn30xx;
- struct cvmx_npi_dma_lowp_counts_s cn31xx;
- struct cvmx_npi_dma_lowp_counts_s cn38xx;
- struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
- struct cvmx_npi_dma_lowp_counts_s cn50xx;
- struct cvmx_npi_dma_lowp_counts_s cn58xx;
- struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
};
union cvmx_npi_dma_lowp_naddr {
@@ -646,13 +577,6 @@
uint64_t reserved_40_63:24;
#endif
} s;
- struct cvmx_npi_dma_lowp_naddr_s cn30xx;
- struct cvmx_npi_dma_lowp_naddr_s cn31xx;
- struct cvmx_npi_dma_lowp_naddr_s cn38xx;
- struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
- struct cvmx_npi_dma_lowp_naddr_s cn50xx;
- struct cvmx_npi_dma_lowp_naddr_s cn58xx;
- struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
};
union cvmx_npi_highp_dbell {
@@ -666,13 +590,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_npi_highp_dbell_s cn30xx;
- struct cvmx_npi_highp_dbell_s cn31xx;
- struct cvmx_npi_highp_dbell_s cn38xx;
- struct cvmx_npi_highp_dbell_s cn38xxp2;
- struct cvmx_npi_highp_dbell_s cn50xx;
- struct cvmx_npi_highp_dbell_s cn58xx;
- struct cvmx_npi_highp_dbell_s cn58xxp1;
};
union cvmx_npi_highp_ibuff_saddr {
@@ -686,13 +603,6 @@
uint64_t reserved_36_63:28;
#endif
} s;
- struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
- struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
- struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
- struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
- struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
- struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
- struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
};
union cvmx_npi_input_control {
@@ -745,12 +655,6 @@
uint64_t reserved_22_63:42;
#endif
} cn30xx;
- struct cvmx_npi_input_control_cn30xx cn31xx;
- struct cvmx_npi_input_control_s cn38xx;
- struct cvmx_npi_input_control_cn30xx cn38xxp2;
- struct cvmx_npi_input_control_s cn50xx;
- struct cvmx_npi_input_control_s cn58xx;
- struct cvmx_npi_input_control_s cn58xxp1;
};
union cvmx_npi_int_enb {
@@ -1094,7 +998,6 @@
uint64_t reserved_62_63:2;
#endif
} cn31xx;
- struct cvmx_npi_int_enb_s cn38xx;
struct cvmx_npi_int_enb_cn38xxp2 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_42_63:22;
@@ -1186,9 +1089,6 @@
uint64_t reserved_42_63:22;
#endif
} cn38xxp2;
- struct cvmx_npi_int_enb_cn31xx cn50xx;
- struct cvmx_npi_int_enb_s cn58xx;
- struct cvmx_npi_int_enb_s cn58xxp1;
};
union cvmx_npi_int_sum {
@@ -1532,7 +1432,6 @@
uint64_t reserved_62_63:2;
#endif
} cn31xx;
- struct cvmx_npi_int_sum_s cn38xx;
struct cvmx_npi_int_sum_cn38xxp2 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_42_63:22;
@@ -1624,9 +1523,6 @@
uint64_t reserved_42_63:22;
#endif
} cn38xxp2;
- struct cvmx_npi_int_sum_cn31xx cn50xx;
- struct cvmx_npi_int_sum_s cn58xx;
- struct cvmx_npi_int_sum_s cn58xxp1;
};
union cvmx_npi_lowp_dbell {
@@ -1640,13 +1536,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_npi_lowp_dbell_s cn30xx;
- struct cvmx_npi_lowp_dbell_s cn31xx;
- struct cvmx_npi_lowp_dbell_s cn38xx;
- struct cvmx_npi_lowp_dbell_s cn38xxp2;
- struct cvmx_npi_lowp_dbell_s cn50xx;
- struct cvmx_npi_lowp_dbell_s cn58xx;
- struct cvmx_npi_lowp_dbell_s cn58xxp1;
};
union cvmx_npi_lowp_ibuff_saddr {
@@ -1660,13 +1549,6 @@
uint64_t reserved_36_63:28;
#endif
} s;
- struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
- struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
- struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
- struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
- struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
- struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
- struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
};
union cvmx_npi_mem_access_subidx {
@@ -1696,7 +1578,6 @@
uint64_t reserved_38_63:26;
#endif
} s;
- struct cvmx_npi_mem_access_subidx_s cn30xx;
struct cvmx_npi_mem_access_subidx_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63:28;
@@ -1718,11 +1599,6 @@
uint64_t reserved_36_63:28;
#endif
} cn31xx;
- struct cvmx_npi_mem_access_subidx_s cn38xx;
- struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
- struct cvmx_npi_mem_access_subidx_s cn50xx;
- struct cvmx_npi_mem_access_subidx_s cn58xx;
- struct cvmx_npi_mem_access_subidx_s cn58xxp1;
};
union cvmx_npi_msi_rcv {
@@ -1734,13 +1610,6 @@
uint64_t int_vec:64;
#endif
} s;
- struct cvmx_npi_msi_rcv_s cn30xx;
- struct cvmx_npi_msi_rcv_s cn31xx;
- struct cvmx_npi_msi_rcv_s cn38xx;
- struct cvmx_npi_msi_rcv_s cn38xxp2;
- struct cvmx_npi_msi_rcv_s cn50xx;
- struct cvmx_npi_msi_rcv_s cn58xx;
- struct cvmx_npi_msi_rcv_s cn58xxp1;
};
union cvmx_npi_num_desc_outputx {
@@ -1754,13 +1623,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npi_num_desc_outputx_s cn30xx;
- struct cvmx_npi_num_desc_outputx_s cn31xx;
- struct cvmx_npi_num_desc_outputx_s cn38xx;
- struct cvmx_npi_num_desc_outputx_s cn38xxp2;
- struct cvmx_npi_num_desc_outputx_s cn50xx;
- struct cvmx_npi_num_desc_outputx_s cn58xx;
- struct cvmx_npi_num_desc_outputx_s cn58xxp1;
};
union cvmx_npi_output_control {
@@ -1932,7 +1794,6 @@
uint64_t reserved_46_63:18;
#endif
} cn31xx;
- struct cvmx_npi_output_control_s cn38xx;
struct cvmx_npi_output_control_cn38xxp2 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63:16;
@@ -2069,8 +1930,6 @@
uint64_t reserved_49_63:15;
#endif
} cn50xx;
- struct cvmx_npi_output_control_s cn58xx;
- struct cvmx_npi_output_control_s cn58xxp1;
};
union cvmx_npi_px_dbpair_addr {
@@ -2086,13 +1945,6 @@
uint64_t reserved_63_63:1;
#endif
} s;
- struct cvmx_npi_px_dbpair_addr_s cn30xx;
- struct cvmx_npi_px_dbpair_addr_s cn31xx;
- struct cvmx_npi_px_dbpair_addr_s cn38xx;
- struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
- struct cvmx_npi_px_dbpair_addr_s cn50xx;
- struct cvmx_npi_px_dbpair_addr_s cn58xx;
- struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
};
union cvmx_npi_px_instr_addr {
@@ -2106,13 +1958,6 @@
uint64_t state:3;
#endif
} s;
- struct cvmx_npi_px_instr_addr_s cn30xx;
- struct cvmx_npi_px_instr_addr_s cn31xx;
- struct cvmx_npi_px_instr_addr_s cn38xx;
- struct cvmx_npi_px_instr_addr_s cn38xxp2;
- struct cvmx_npi_px_instr_addr_s cn50xx;
- struct cvmx_npi_px_instr_addr_s cn58xx;
- struct cvmx_npi_px_instr_addr_s cn58xxp1;
};
union cvmx_npi_px_instr_cnts {
@@ -2128,13 +1973,6 @@
uint64_t reserved_38_63:26;
#endif
} s;
- struct cvmx_npi_px_instr_cnts_s cn30xx;
- struct cvmx_npi_px_instr_cnts_s cn31xx;
- struct cvmx_npi_px_instr_cnts_s cn38xx;
- struct cvmx_npi_px_instr_cnts_s cn38xxp2;
- struct cvmx_npi_px_instr_cnts_s cn50xx;
- struct cvmx_npi_px_instr_cnts_s cn58xx;
- struct cvmx_npi_px_instr_cnts_s cn58xxp1;
};
union cvmx_npi_px_pair_cnts {
@@ -2150,13 +1988,6 @@
uint64_t reserved_37_63:27;
#endif
} s;
- struct cvmx_npi_px_pair_cnts_s cn30xx;
- struct cvmx_npi_px_pair_cnts_s cn31xx;
- struct cvmx_npi_px_pair_cnts_s cn38xx;
- struct cvmx_npi_px_pair_cnts_s cn38xxp2;
- struct cvmx_npi_px_pair_cnts_s cn50xx;
- struct cvmx_npi_px_pair_cnts_s cn58xx;
- struct cvmx_npi_px_pair_cnts_s cn58xxp1;
};
union cvmx_npi_pci_burst_size {
@@ -2172,13 +2003,6 @@
uint64_t reserved_14_63:50;
#endif
} s;
- struct cvmx_npi_pci_burst_size_s cn30xx;
- struct cvmx_npi_pci_burst_size_s cn31xx;
- struct cvmx_npi_pci_burst_size_s cn38xx;
- struct cvmx_npi_pci_burst_size_s cn38xxp2;
- struct cvmx_npi_pci_burst_size_s cn50xx;
- struct cvmx_npi_pci_burst_size_s cn58xx;
- struct cvmx_npi_pci_burst_size_s cn58xxp1;
};
union cvmx_npi_pci_int_arb_cfg {
@@ -2215,12 +2039,6 @@
uint64_t reserved_5_63:59;
#endif
} cn30xx;
- struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
- struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
- struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
- struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
- struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
- struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
};
union cvmx_npi_pci_read_cmd {
@@ -2234,13 +2052,6 @@
uint64_t reserved_11_63:53;
#endif
} s;
- struct cvmx_npi_pci_read_cmd_s cn30xx;
- struct cvmx_npi_pci_read_cmd_s cn31xx;
- struct cvmx_npi_pci_read_cmd_s cn38xx;
- struct cvmx_npi_pci_read_cmd_s cn38xxp2;
- struct cvmx_npi_pci_read_cmd_s cn50xx;
- struct cvmx_npi_pci_read_cmd_s cn58xx;
- struct cvmx_npi_pci_read_cmd_s cn58xxp1;
};
union cvmx_npi_port32_instr_hdr {
@@ -2276,13 +2087,6 @@
uint64_t reserved_44_63:20;
#endif
} s;
- struct cvmx_npi_port32_instr_hdr_s cn30xx;
- struct cvmx_npi_port32_instr_hdr_s cn31xx;
- struct cvmx_npi_port32_instr_hdr_s cn38xx;
- struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
- struct cvmx_npi_port32_instr_hdr_s cn50xx;
- struct cvmx_npi_port32_instr_hdr_s cn58xx;
- struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
};
union cvmx_npi_port33_instr_hdr {
@@ -2318,12 +2122,6 @@
uint64_t reserved_44_63:20;
#endif
} s;
- struct cvmx_npi_port33_instr_hdr_s cn31xx;
- struct cvmx_npi_port33_instr_hdr_s cn38xx;
- struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
- struct cvmx_npi_port33_instr_hdr_s cn50xx;
- struct cvmx_npi_port33_instr_hdr_s cn58xx;
- struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
};
union cvmx_npi_port34_instr_hdr {
@@ -2359,10 +2157,6 @@
uint64_t reserved_44_63:20;
#endif
} s;
- struct cvmx_npi_port34_instr_hdr_s cn38xx;
- struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
- struct cvmx_npi_port34_instr_hdr_s cn58xx;
- struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
};
union cvmx_npi_port35_instr_hdr {
@@ -2398,10 +2192,6 @@
uint64_t reserved_44_63:20;
#endif
} s;
- struct cvmx_npi_port35_instr_hdr_s cn38xx;
- struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
- struct cvmx_npi_port35_instr_hdr_s cn58xx;
- struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
};
union cvmx_npi_port_bp_control {
@@ -2417,13 +2207,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_npi_port_bp_control_s cn30xx;
- struct cvmx_npi_port_bp_control_s cn31xx;
- struct cvmx_npi_port_bp_control_s cn38xx;
- struct cvmx_npi_port_bp_control_s cn38xxp2;
- struct cvmx_npi_port_bp_control_s cn50xx;
- struct cvmx_npi_port_bp_control_s cn58xx;
- struct cvmx_npi_port_bp_control_s cn58xxp1;
};
union cvmx_npi_rsl_int_blocks {
@@ -2566,7 +2349,6 @@
uint64_t reserved_32_63:32;
#endif
} cn30xx;
- struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
struct cvmx_npi_rsl_int_blocks_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_32_63:32;
@@ -2638,7 +2420,6 @@
uint64_t reserved_32_63:32;
#endif
} cn38xx;
- struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
struct cvmx_npi_rsl_int_blocks_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_31_63:33;
@@ -2702,8 +2483,6 @@
uint64_t reserved_31_63:33;
#endif
} cn50xx;
- struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
- struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
};
union cvmx_npi_size_inputx {
@@ -2717,13 +2496,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npi_size_inputx_s cn30xx;
- struct cvmx_npi_size_inputx_s cn31xx;
- struct cvmx_npi_size_inputx_s cn38xx;
- struct cvmx_npi_size_inputx_s cn38xxp2;
- struct cvmx_npi_size_inputx_s cn50xx;
- struct cvmx_npi_size_inputx_s cn58xx;
- struct cvmx_npi_size_inputx_s cn58xxp1;
};
union cvmx_npi_win_read_to {
@@ -2737,13 +2509,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_npi_win_read_to_s cn30xx;
- struct cvmx_npi_win_read_to_s cn31xx;
- struct cvmx_npi_win_read_to_s cn38xx;
- struct cvmx_npi_win_read_to_s cn38xxp2;
- struct cvmx_npi_win_read_to_s cn50xx;
- struct cvmx_npi_win_read_to_s cn58xx;
- struct cvmx_npi_win_read_to_s cn58xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
index 25d603f..be56b69 100644
--- a/arch/mips/include/asm/octeon/cvmx-pci-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
@@ -131,13 +131,6 @@
uint32_t reserved_18_31:14;
#endif
} s;
- struct cvmx_pci_bar1_indexx_s cn30xx;
- struct cvmx_pci_bar1_indexx_s cn31xx;
- struct cvmx_pci_bar1_indexx_s cn38xx;
- struct cvmx_pci_bar1_indexx_s cn38xxp2;
- struct cvmx_pci_bar1_indexx_s cn50xx;
- struct cvmx_pci_bar1_indexx_s cn58xx;
- struct cvmx_pci_bar1_indexx_s cn58xxp1;
};
union cvmx_pci_bist_reg {
@@ -169,7 +162,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_pci_bist_reg_s cn50xx;
};
union cvmx_pci_cfg00 {
@@ -183,13 +175,6 @@
uint32_t devid:16;
#endif
} s;
- struct cvmx_pci_cfg00_s cn30xx;
- struct cvmx_pci_cfg00_s cn31xx;
- struct cvmx_pci_cfg00_s cn38xx;
- struct cvmx_pci_cfg00_s cn38xxp2;
- struct cvmx_pci_cfg00_s cn50xx;
- struct cvmx_pci_cfg00_s cn58xx;
- struct cvmx_pci_cfg00_s cn58xxp1;
};
union cvmx_pci_cfg01 {
@@ -247,13 +232,6 @@
uint32_t dpe:1;
#endif
} s;
- struct cvmx_pci_cfg01_s cn30xx;
- struct cvmx_pci_cfg01_s cn31xx;
- struct cvmx_pci_cfg01_s cn38xx;
- struct cvmx_pci_cfg01_s cn38xxp2;
- struct cvmx_pci_cfg01_s cn50xx;
- struct cvmx_pci_cfg01_s cn58xx;
- struct cvmx_pci_cfg01_s cn58xxp1;
};
union cvmx_pci_cfg02 {
@@ -267,13 +245,6 @@
uint32_t cc:24;
#endif
} s;
- struct cvmx_pci_cfg02_s cn30xx;
- struct cvmx_pci_cfg02_s cn31xx;
- struct cvmx_pci_cfg02_s cn38xx;
- struct cvmx_pci_cfg02_s cn38xxp2;
- struct cvmx_pci_cfg02_s cn50xx;
- struct cvmx_pci_cfg02_s cn58xx;
- struct cvmx_pci_cfg02_s cn58xxp1;
};
union cvmx_pci_cfg03 {
@@ -297,13 +268,6 @@
uint32_t bcap:1;
#endif
} s;
- struct cvmx_pci_cfg03_s cn30xx;
- struct cvmx_pci_cfg03_s cn31xx;
- struct cvmx_pci_cfg03_s cn38xx;
- struct cvmx_pci_cfg03_s cn38xxp2;
- struct cvmx_pci_cfg03_s cn50xx;
- struct cvmx_pci_cfg03_s cn58xx;
- struct cvmx_pci_cfg03_s cn58xxp1;
};
union cvmx_pci_cfg04 {
@@ -323,13 +287,6 @@
uint32_t lbase:20;
#endif
} s;
- struct cvmx_pci_cfg04_s cn30xx;
- struct cvmx_pci_cfg04_s cn31xx;
- struct cvmx_pci_cfg04_s cn38xx;
- struct cvmx_pci_cfg04_s cn38xxp2;
- struct cvmx_pci_cfg04_s cn50xx;
- struct cvmx_pci_cfg04_s cn58xx;
- struct cvmx_pci_cfg04_s cn58xxp1;
};
union cvmx_pci_cfg05 {
@@ -341,13 +298,6 @@
uint32_t hbase:32;
#endif
} s;
- struct cvmx_pci_cfg05_s cn30xx;
- struct cvmx_pci_cfg05_s cn31xx;
- struct cvmx_pci_cfg05_s cn38xx;
- struct cvmx_pci_cfg05_s cn38xxp2;
- struct cvmx_pci_cfg05_s cn50xx;
- struct cvmx_pci_cfg05_s cn58xx;
- struct cvmx_pci_cfg05_s cn58xxp1;
};
union cvmx_pci_cfg06 {
@@ -367,13 +317,6 @@
uint32_t lbase:5;
#endif
} s;
- struct cvmx_pci_cfg06_s cn30xx;
- struct cvmx_pci_cfg06_s cn31xx;
- struct cvmx_pci_cfg06_s cn38xx;
- struct cvmx_pci_cfg06_s cn38xxp2;
- struct cvmx_pci_cfg06_s cn50xx;
- struct cvmx_pci_cfg06_s cn58xx;
- struct cvmx_pci_cfg06_s cn58xxp1;
};
union cvmx_pci_cfg07 {
@@ -385,13 +328,6 @@
uint32_t hbase:32;
#endif
} s;
- struct cvmx_pci_cfg07_s cn30xx;
- struct cvmx_pci_cfg07_s cn31xx;
- struct cvmx_pci_cfg07_s cn38xx;
- struct cvmx_pci_cfg07_s cn38xxp2;
- struct cvmx_pci_cfg07_s cn50xx;
- struct cvmx_pci_cfg07_s cn58xx;
- struct cvmx_pci_cfg07_s cn58xxp1;
};
union cvmx_pci_cfg08 {
@@ -409,13 +345,6 @@
uint32_t lbasez:28;
#endif
} s;
- struct cvmx_pci_cfg08_s cn30xx;
- struct cvmx_pci_cfg08_s cn31xx;
- struct cvmx_pci_cfg08_s cn38xx;
- struct cvmx_pci_cfg08_s cn38xxp2;
- struct cvmx_pci_cfg08_s cn50xx;
- struct cvmx_pci_cfg08_s cn58xx;
- struct cvmx_pci_cfg08_s cn58xxp1;
};
union cvmx_pci_cfg09 {
@@ -429,13 +358,6 @@
uint32_t hbase:25;
#endif
} s;
- struct cvmx_pci_cfg09_s cn30xx;
- struct cvmx_pci_cfg09_s cn31xx;
- struct cvmx_pci_cfg09_s cn38xx;
- struct cvmx_pci_cfg09_s cn38xxp2;
- struct cvmx_pci_cfg09_s cn50xx;
- struct cvmx_pci_cfg09_s cn58xx;
- struct cvmx_pci_cfg09_s cn58xxp1;
};
union cvmx_pci_cfg10 {
@@ -447,13 +369,6 @@
uint32_t cisp:32;
#endif
} s;
- struct cvmx_pci_cfg10_s cn30xx;
- struct cvmx_pci_cfg10_s cn31xx;
- struct cvmx_pci_cfg10_s cn38xx;
- struct cvmx_pci_cfg10_s cn38xxp2;
- struct cvmx_pci_cfg10_s cn50xx;
- struct cvmx_pci_cfg10_s cn58xx;
- struct cvmx_pci_cfg10_s cn58xxp1;
};
union cvmx_pci_cfg11 {
@@ -467,13 +382,6 @@
uint32_t ssid:16;
#endif
} s;
- struct cvmx_pci_cfg11_s cn30xx;
- struct cvmx_pci_cfg11_s cn31xx;
- struct cvmx_pci_cfg11_s cn38xx;
- struct cvmx_pci_cfg11_s cn38xxp2;
- struct cvmx_pci_cfg11_s cn50xx;
- struct cvmx_pci_cfg11_s cn58xx;
- struct cvmx_pci_cfg11_s cn58xxp1;
};
union cvmx_pci_cfg12 {
@@ -491,13 +399,6 @@
uint32_t erbar:16;
#endif
} s;
- struct cvmx_pci_cfg12_s cn30xx;
- struct cvmx_pci_cfg12_s cn31xx;
- struct cvmx_pci_cfg12_s cn38xx;
- struct cvmx_pci_cfg12_s cn38xxp2;
- struct cvmx_pci_cfg12_s cn50xx;
- struct cvmx_pci_cfg12_s cn58xx;
- struct cvmx_pci_cfg12_s cn58xxp1;
};
union cvmx_pci_cfg13 {
@@ -511,13 +412,6 @@
uint32_t reserved_8_31:24;
#endif
} s;
- struct cvmx_pci_cfg13_s cn30xx;
- struct cvmx_pci_cfg13_s cn31xx;
- struct cvmx_pci_cfg13_s cn38xx;
- struct cvmx_pci_cfg13_s cn38xxp2;
- struct cvmx_pci_cfg13_s cn50xx;
- struct cvmx_pci_cfg13_s cn58xx;
- struct cvmx_pci_cfg13_s cn58xxp1;
};
union cvmx_pci_cfg15 {
@@ -535,13 +429,6 @@
uint32_t ml:8;
#endif
} s;
- struct cvmx_pci_cfg15_s cn30xx;
- struct cvmx_pci_cfg15_s cn31xx;
- struct cvmx_pci_cfg15_s cn38xx;
- struct cvmx_pci_cfg15_s cn38xxp2;
- struct cvmx_pci_cfg15_s cn50xx;
- struct cvmx_pci_cfg15_s cn58xx;
- struct cvmx_pci_cfg15_s cn58xxp1;
};
union cvmx_pci_cfg16 {
@@ -583,13 +470,6 @@
uint32_t trdnpr:1;
#endif
} s;
- struct cvmx_pci_cfg16_s cn30xx;
- struct cvmx_pci_cfg16_s cn31xx;
- struct cvmx_pci_cfg16_s cn38xx;
- struct cvmx_pci_cfg16_s cn38xxp2;
- struct cvmx_pci_cfg16_s cn50xx;
- struct cvmx_pci_cfg16_s cn58xx;
- struct cvmx_pci_cfg16_s cn58xxp1;
};
union cvmx_pci_cfg17 {
@@ -601,13 +481,6 @@
uint32_t tscme:32;
#endif
} s;
- struct cvmx_pci_cfg17_s cn30xx;
- struct cvmx_pci_cfg17_s cn31xx;
- struct cvmx_pci_cfg17_s cn38xx;
- struct cvmx_pci_cfg17_s cn38xxp2;
- struct cvmx_pci_cfg17_s cn50xx;
- struct cvmx_pci_cfg17_s cn58xx;
- struct cvmx_pci_cfg17_s cn58xxp1;
};
union cvmx_pci_cfg18 {
@@ -619,13 +492,6 @@
uint32_t tdsrps:32;
#endif
} s;
- struct cvmx_pci_cfg18_s cn30xx;
- struct cvmx_pci_cfg18_s cn31xx;
- struct cvmx_pci_cfg18_s cn38xx;
- struct cvmx_pci_cfg18_s cn38xxp2;
- struct cvmx_pci_cfg18_s cn50xx;
- struct cvmx_pci_cfg18_s cn58xx;
- struct cvmx_pci_cfg18_s cn58xxp1;
};
union cvmx_pci_cfg19 {
@@ -671,13 +537,6 @@
uint32_t mrbcm:1;
#endif
} s;
- struct cvmx_pci_cfg19_s cn30xx;
- struct cvmx_pci_cfg19_s cn31xx;
- struct cvmx_pci_cfg19_s cn38xx;
- struct cvmx_pci_cfg19_s cn38xxp2;
- struct cvmx_pci_cfg19_s cn50xx;
- struct cvmx_pci_cfg19_s cn58xx;
- struct cvmx_pci_cfg19_s cn58xxp1;
};
union cvmx_pci_cfg20 {
@@ -689,13 +548,6 @@
uint32_t mdsp:32;
#endif
} s;
- struct cvmx_pci_cfg20_s cn30xx;
- struct cvmx_pci_cfg20_s cn31xx;
- struct cvmx_pci_cfg20_s cn38xx;
- struct cvmx_pci_cfg20_s cn38xxp2;
- struct cvmx_pci_cfg20_s cn50xx;
- struct cvmx_pci_cfg20_s cn58xx;
- struct cvmx_pci_cfg20_s cn58xxp1;
};
union cvmx_pci_cfg21 {
@@ -707,13 +559,6 @@
uint32_t scmre:32;
#endif
} s;
- struct cvmx_pci_cfg21_s cn30xx;
- struct cvmx_pci_cfg21_s cn31xx;
- struct cvmx_pci_cfg21_s cn38xx;
- struct cvmx_pci_cfg21_s cn38xxp2;
- struct cvmx_pci_cfg21_s cn50xx;
- struct cvmx_pci_cfg21_s cn58xx;
- struct cvmx_pci_cfg21_s cn58xxp1;
};
union cvmx_pci_cfg22 {
@@ -737,13 +582,6 @@
uint32_t mac:7;
#endif
} s;
- struct cvmx_pci_cfg22_s cn30xx;
- struct cvmx_pci_cfg22_s cn31xx;
- struct cvmx_pci_cfg22_s cn38xx;
- struct cvmx_pci_cfg22_s cn38xxp2;
- struct cvmx_pci_cfg22_s cn50xx;
- struct cvmx_pci_cfg22_s cn58xx;
- struct cvmx_pci_cfg22_s cn58xxp1;
};
union cvmx_pci_cfg56 {
@@ -767,13 +605,6 @@
uint32_t reserved_23_31:9;
#endif
} s;
- struct cvmx_pci_cfg56_s cn30xx;
- struct cvmx_pci_cfg56_s cn31xx;
- struct cvmx_pci_cfg56_s cn38xx;
- struct cvmx_pci_cfg56_s cn38xxp2;
- struct cvmx_pci_cfg56_s cn50xx;
- struct cvmx_pci_cfg56_s cn58xx;
- struct cvmx_pci_cfg56_s cn58xxp1;
};
union cvmx_pci_cfg57 {
@@ -809,13 +640,6 @@
uint32_t reserved_30_31:2;
#endif
} s;
- struct cvmx_pci_cfg57_s cn30xx;
- struct cvmx_pci_cfg57_s cn31xx;
- struct cvmx_pci_cfg57_s cn38xx;
- struct cvmx_pci_cfg57_s cn38xxp2;
- struct cvmx_pci_cfg57_s cn50xx;
- struct cvmx_pci_cfg57_s cn58xx;
- struct cvmx_pci_cfg57_s cn58xxp1;
};
union cvmx_pci_cfg58 {
@@ -845,13 +669,6 @@
uint32_t pmes:5;
#endif
} s;
- struct cvmx_pci_cfg58_s cn30xx;
- struct cvmx_pci_cfg58_s cn31xx;
- struct cvmx_pci_cfg58_s cn38xx;
- struct cvmx_pci_cfg58_s cn38xxp2;
- struct cvmx_pci_cfg58_s cn50xx;
- struct cvmx_pci_cfg58_s cn58xx;
- struct cvmx_pci_cfg58_s cn58xxp1;
};
union cvmx_pci_cfg59 {
@@ -881,13 +698,6 @@
uint32_t pmdia:8;
#endif
} s;
- struct cvmx_pci_cfg59_s cn30xx;
- struct cvmx_pci_cfg59_s cn31xx;
- struct cvmx_pci_cfg59_s cn38xx;
- struct cvmx_pci_cfg59_s cn38xxp2;
- struct cvmx_pci_cfg59_s cn50xx;
- struct cvmx_pci_cfg59_s cn58xx;
- struct cvmx_pci_cfg59_s cn58xxp1;
};
union cvmx_pci_cfg60 {
@@ -911,13 +721,6 @@
uint32_t reserved_24_31:8;
#endif
} s;
- struct cvmx_pci_cfg60_s cn30xx;
- struct cvmx_pci_cfg60_s cn31xx;
- struct cvmx_pci_cfg60_s cn38xx;
- struct cvmx_pci_cfg60_s cn38xxp2;
- struct cvmx_pci_cfg60_s cn50xx;
- struct cvmx_pci_cfg60_s cn58xx;
- struct cvmx_pci_cfg60_s cn58xxp1;
};
union cvmx_pci_cfg61 {
@@ -931,13 +734,6 @@
uint32_t msi31t2:30;
#endif
} s;
- struct cvmx_pci_cfg61_s cn30xx;
- struct cvmx_pci_cfg61_s cn31xx;
- struct cvmx_pci_cfg61_s cn38xx;
- struct cvmx_pci_cfg61_s cn38xxp2;
- struct cvmx_pci_cfg61_s cn50xx;
- struct cvmx_pci_cfg61_s cn58xx;
- struct cvmx_pci_cfg61_s cn58xxp1;
};
union cvmx_pci_cfg62 {
@@ -949,13 +745,6 @@
uint32_t msi:32;
#endif
} s;
- struct cvmx_pci_cfg62_s cn30xx;
- struct cvmx_pci_cfg62_s cn31xx;
- struct cvmx_pci_cfg62_s cn38xx;
- struct cvmx_pci_cfg62_s cn38xxp2;
- struct cvmx_pci_cfg62_s cn50xx;
- struct cvmx_pci_cfg62_s cn58xx;
- struct cvmx_pci_cfg62_s cn58xxp1;
};
union cvmx_pci_cfg63 {
@@ -969,13 +758,6 @@
uint32_t reserved_16_31:16;
#endif
} s;
- struct cvmx_pci_cfg63_s cn30xx;
- struct cvmx_pci_cfg63_s cn31xx;
- struct cvmx_pci_cfg63_s cn38xx;
- struct cvmx_pci_cfg63_s cn38xxp2;
- struct cvmx_pci_cfg63_s cn50xx;
- struct cvmx_pci_cfg63_s cn58xx;
- struct cvmx_pci_cfg63_s cn58xxp1;
};
union cvmx_pci_cnt_reg {
@@ -997,9 +779,6 @@
uint64_t reserved_38_63:26;
#endif
} s;
- struct cvmx_pci_cnt_reg_s cn50xx;
- struct cvmx_pci_cnt_reg_s cn58xx;
- struct cvmx_pci_cnt_reg_s cn58xxp1;
};
union cvmx_pci_ctl_status_2 {
@@ -1053,7 +832,6 @@
uint32_t reserved_29_31:3;
#endif
} s;
- struct cvmx_pci_ctl_status_2_s cn30xx;
struct cvmx_pci_ctl_status_2_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_20_31:12;
@@ -1091,11 +869,6 @@
uint32_t reserved_20_31:12;
#endif
} cn31xx;
- struct cvmx_pci_ctl_status_2_s cn38xx;
- struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2;
- struct cvmx_pci_ctl_status_2_s cn50xx;
- struct cvmx_pci_ctl_status_2_s cn58xx;
- struct cvmx_pci_ctl_status_2_s cn58xxp1;
};
union cvmx_pci_dbellx {
@@ -1109,13 +882,6 @@
uint32_t reserved_16_31:16;
#endif
} s;
- struct cvmx_pci_dbellx_s cn30xx;
- struct cvmx_pci_dbellx_s cn31xx;
- struct cvmx_pci_dbellx_s cn38xx;
- struct cvmx_pci_dbellx_s cn38xxp2;
- struct cvmx_pci_dbellx_s cn50xx;
- struct cvmx_pci_dbellx_s cn58xx;
- struct cvmx_pci_dbellx_s cn58xxp1;
};
union cvmx_pci_dma_cntx {
@@ -1127,13 +893,6 @@
uint32_t dma_cnt:32;
#endif
} s;
- struct cvmx_pci_dma_cntx_s cn30xx;
- struct cvmx_pci_dma_cntx_s cn31xx;
- struct cvmx_pci_dma_cntx_s cn38xx;
- struct cvmx_pci_dma_cntx_s cn38xxp2;
- struct cvmx_pci_dma_cntx_s cn50xx;
- struct cvmx_pci_dma_cntx_s cn58xx;
- struct cvmx_pci_dma_cntx_s cn58xxp1;
};
union cvmx_pci_dma_int_levx {
@@ -1145,13 +904,6 @@
uint32_t pkt_cnt:32;
#endif
} s;
- struct cvmx_pci_dma_int_levx_s cn30xx;
- struct cvmx_pci_dma_int_levx_s cn31xx;
- struct cvmx_pci_dma_int_levx_s cn38xx;
- struct cvmx_pci_dma_int_levx_s cn38xxp2;
- struct cvmx_pci_dma_int_levx_s cn50xx;
- struct cvmx_pci_dma_int_levx_s cn58xx;
- struct cvmx_pci_dma_int_levx_s cn58xxp1;
};
union cvmx_pci_dma_timex {
@@ -1163,13 +915,6 @@
uint32_t dma_time:32;
#endif
} s;
- struct cvmx_pci_dma_timex_s cn30xx;
- struct cvmx_pci_dma_timex_s cn31xx;
- struct cvmx_pci_dma_timex_s cn38xx;
- struct cvmx_pci_dma_timex_s cn38xxp2;
- struct cvmx_pci_dma_timex_s cn50xx;
- struct cvmx_pci_dma_timex_s cn58xx;
- struct cvmx_pci_dma_timex_s cn58xxp1;
};
union cvmx_pci_instr_countx {
@@ -1181,13 +926,6 @@
uint32_t icnt:32;
#endif
} s;
- struct cvmx_pci_instr_countx_s cn30xx;
- struct cvmx_pci_instr_countx_s cn31xx;
- struct cvmx_pci_instr_countx_s cn38xx;
- struct cvmx_pci_instr_countx_s cn38xxp2;
- struct cvmx_pci_instr_countx_s cn50xx;
- struct cvmx_pci_instr_countx_s cn58xx;
- struct cvmx_pci_instr_countx_s cn58xxp1;
};
union cvmx_pci_int_enb {
@@ -1405,11 +1143,6 @@
uint64_t reserved_34_63:30;
#endif
} cn31xx;
- struct cvmx_pci_int_enb_s cn38xx;
- struct cvmx_pci_int_enb_s cn38xxp2;
- struct cvmx_pci_int_enb_cn31xx cn50xx;
- struct cvmx_pci_int_enb_s cn58xx;
- struct cvmx_pci_int_enb_s cn58xxp1;
};
union cvmx_pci_int_enb2 {
@@ -1627,11 +1360,6 @@
uint64_t reserved_34_63:30;
#endif
} cn31xx;
- struct cvmx_pci_int_enb2_s cn38xx;
- struct cvmx_pci_int_enb2_s cn38xxp2;
- struct cvmx_pci_int_enb2_cn31xx cn50xx;
- struct cvmx_pci_int_enb2_s cn58xx;
- struct cvmx_pci_int_enb2_s cn58xxp1;
};
union cvmx_pci_int_sum {
@@ -1849,11 +1577,6 @@
uint64_t reserved_34_63:30;
#endif
} cn31xx;
- struct cvmx_pci_int_sum_s cn38xx;
- struct cvmx_pci_int_sum_s cn38xxp2;
- struct cvmx_pci_int_sum_cn31xx cn50xx;
- struct cvmx_pci_int_sum_s cn58xx;
- struct cvmx_pci_int_sum_s cn58xxp1;
};
union cvmx_pci_int_sum2 {
@@ -2071,11 +1794,6 @@
uint64_t reserved_34_63:30;
#endif
} cn31xx;
- struct cvmx_pci_int_sum2_s cn38xx;
- struct cvmx_pci_int_sum2_s cn38xxp2;
- struct cvmx_pci_int_sum2_cn31xx cn50xx;
- struct cvmx_pci_int_sum2_s cn58xx;
- struct cvmx_pci_int_sum2_s cn58xxp1;
};
union cvmx_pci_msi_rcv {
@@ -2089,13 +1807,6 @@
uint32_t reserved_6_31:26;
#endif
} s;
- struct cvmx_pci_msi_rcv_s cn30xx;
- struct cvmx_pci_msi_rcv_s cn31xx;
- struct cvmx_pci_msi_rcv_s cn38xx;
- struct cvmx_pci_msi_rcv_s cn38xxp2;
- struct cvmx_pci_msi_rcv_s cn50xx;
- struct cvmx_pci_msi_rcv_s cn58xx;
- struct cvmx_pci_msi_rcv_s cn58xxp1;
};
union cvmx_pci_pkt_creditsx {
@@ -2109,13 +1820,6 @@
uint32_t pkt_cnt:16;
#endif
} s;
- struct cvmx_pci_pkt_creditsx_s cn30xx;
- struct cvmx_pci_pkt_creditsx_s cn31xx;
- struct cvmx_pci_pkt_creditsx_s cn38xx;
- struct cvmx_pci_pkt_creditsx_s cn38xxp2;
- struct cvmx_pci_pkt_creditsx_s cn50xx;
- struct cvmx_pci_pkt_creditsx_s cn58xx;
- struct cvmx_pci_pkt_creditsx_s cn58xxp1;
};
union cvmx_pci_pkts_sentx {
@@ -2127,13 +1831,6 @@
uint32_t pkt_cnt:32;
#endif
} s;
- struct cvmx_pci_pkts_sentx_s cn30xx;
- struct cvmx_pci_pkts_sentx_s cn31xx;
- struct cvmx_pci_pkts_sentx_s cn38xx;
- struct cvmx_pci_pkts_sentx_s cn38xxp2;
- struct cvmx_pci_pkts_sentx_s cn50xx;
- struct cvmx_pci_pkts_sentx_s cn58xx;
- struct cvmx_pci_pkts_sentx_s cn58xxp1;
};
union cvmx_pci_pkts_sent_int_levx {
@@ -2145,13 +1842,6 @@
uint32_t pkt_cnt:32;
#endif
} s;
- struct cvmx_pci_pkts_sent_int_levx_s cn30xx;
- struct cvmx_pci_pkts_sent_int_levx_s cn31xx;
- struct cvmx_pci_pkts_sent_int_levx_s cn38xx;
- struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2;
- struct cvmx_pci_pkts_sent_int_levx_s cn50xx;
- struct cvmx_pci_pkts_sent_int_levx_s cn58xx;
- struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1;
};
union cvmx_pci_pkts_sent_timex {
@@ -2163,13 +1853,6 @@
uint32_t pkt_time:32;
#endif
} s;
- struct cvmx_pci_pkts_sent_timex_s cn30xx;
- struct cvmx_pci_pkts_sent_timex_s cn31xx;
- struct cvmx_pci_pkts_sent_timex_s cn38xx;
- struct cvmx_pci_pkts_sent_timex_s cn38xxp2;
- struct cvmx_pci_pkts_sent_timex_s cn50xx;
- struct cvmx_pci_pkts_sent_timex_s cn58xx;
- struct cvmx_pci_pkts_sent_timex_s cn58xxp1;
};
union cvmx_pci_read_cmd_6 {
@@ -2185,13 +1868,6 @@
uint32_t reserved_9_31:23;
#endif
} s;
- struct cvmx_pci_read_cmd_6_s cn30xx;
- struct cvmx_pci_read_cmd_6_s cn31xx;
- struct cvmx_pci_read_cmd_6_s cn38xx;
- struct cvmx_pci_read_cmd_6_s cn38xxp2;
- struct cvmx_pci_read_cmd_6_s cn50xx;
- struct cvmx_pci_read_cmd_6_s cn58xx;
- struct cvmx_pci_read_cmd_6_s cn58xxp1;
};
union cvmx_pci_read_cmd_c {
@@ -2207,13 +1883,6 @@
uint32_t reserved_9_31:23;
#endif
} s;
- struct cvmx_pci_read_cmd_c_s cn30xx;
- struct cvmx_pci_read_cmd_c_s cn31xx;
- struct cvmx_pci_read_cmd_c_s cn38xx;
- struct cvmx_pci_read_cmd_c_s cn38xxp2;
- struct cvmx_pci_read_cmd_c_s cn50xx;
- struct cvmx_pci_read_cmd_c_s cn58xx;
- struct cvmx_pci_read_cmd_c_s cn58xxp1;
};
union cvmx_pci_read_cmd_e {
@@ -2229,13 +1898,6 @@
uint32_t reserved_9_31:23;
#endif
} s;
- struct cvmx_pci_read_cmd_e_s cn30xx;
- struct cvmx_pci_read_cmd_e_s cn31xx;
- struct cvmx_pci_read_cmd_e_s cn38xx;
- struct cvmx_pci_read_cmd_e_s cn38xxp2;
- struct cvmx_pci_read_cmd_e_s cn50xx;
- struct cvmx_pci_read_cmd_e_s cn58xx;
- struct cvmx_pci_read_cmd_e_s cn58xxp1;
};
union cvmx_pci_read_timeout {
@@ -2251,13 +1913,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pci_read_timeout_s cn30xx;
- struct cvmx_pci_read_timeout_s cn31xx;
- struct cvmx_pci_read_timeout_s cn38xx;
- struct cvmx_pci_read_timeout_s cn38xxp2;
- struct cvmx_pci_read_timeout_s cn50xx;
- struct cvmx_pci_read_timeout_s cn58xx;
- struct cvmx_pci_read_timeout_s cn58xxp1;
};
union cvmx_pci_scm_reg {
@@ -2271,13 +1926,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pci_scm_reg_s cn30xx;
- struct cvmx_pci_scm_reg_s cn31xx;
- struct cvmx_pci_scm_reg_s cn38xx;
- struct cvmx_pci_scm_reg_s cn38xxp2;
- struct cvmx_pci_scm_reg_s cn50xx;
- struct cvmx_pci_scm_reg_s cn58xx;
- struct cvmx_pci_scm_reg_s cn58xxp1;
};
union cvmx_pci_tsr_reg {
@@ -2291,13 +1939,6 @@
uint64_t reserved_36_63:28;
#endif
} s;
- struct cvmx_pci_tsr_reg_s cn30xx;
- struct cvmx_pci_tsr_reg_s cn31xx;
- struct cvmx_pci_tsr_reg_s cn38xx;
- struct cvmx_pci_tsr_reg_s cn38xxp2;
- struct cvmx_pci_tsr_reg_s cn50xx;
- struct cvmx_pci_tsr_reg_s cn58xx;
- struct cvmx_pci_tsr_reg_s cn58xxp1;
};
union cvmx_pci_win_rd_addr {
@@ -2326,7 +1967,6 @@
uint64_t reserved_49_63:15;
#endif
} cn30xx;
- struct cvmx_pci_win_rd_addr_cn30xx cn31xx;
struct cvmx_pci_win_rd_addr_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_49_63:15;
@@ -2340,10 +1980,6 @@
uint64_t reserved_49_63:15;
#endif
} cn38xx;
- struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2;
- struct cvmx_pci_win_rd_addr_cn30xx cn50xx;
- struct cvmx_pci_win_rd_addr_cn38xx cn58xx;
- struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1;
};
union cvmx_pci_win_rd_data {
@@ -2355,13 +1991,6 @@
uint64_t rd_data:64;
#endif
} s;
- struct cvmx_pci_win_rd_data_s cn30xx;
- struct cvmx_pci_win_rd_data_s cn31xx;
- struct cvmx_pci_win_rd_data_s cn38xx;
- struct cvmx_pci_win_rd_data_s cn38xxp2;
- struct cvmx_pci_win_rd_data_s cn50xx;
- struct cvmx_pci_win_rd_data_s cn58xx;
- struct cvmx_pci_win_rd_data_s cn58xxp1;
};
union cvmx_pci_win_wr_addr {
@@ -2379,13 +2008,6 @@
uint64_t reserved_49_63:15;
#endif
} s;
- struct cvmx_pci_win_wr_addr_s cn30xx;
- struct cvmx_pci_win_wr_addr_s cn31xx;
- struct cvmx_pci_win_wr_addr_s cn38xx;
- struct cvmx_pci_win_wr_addr_s cn38xxp2;
- struct cvmx_pci_win_wr_addr_s cn50xx;
- struct cvmx_pci_win_wr_addr_s cn58xx;
- struct cvmx_pci_win_wr_addr_s cn58xxp1;
};
union cvmx_pci_win_wr_data {
@@ -2397,13 +2019,6 @@
uint64_t wr_data:64;
#endif
} s;
- struct cvmx_pci_win_wr_data_s cn30xx;
- struct cvmx_pci_win_wr_data_s cn31xx;
- struct cvmx_pci_win_wr_data_s cn38xx;
- struct cvmx_pci_win_wr_data_s cn38xxp2;
- struct cvmx_pci_win_wr_data_s cn50xx;
- struct cvmx_pci_win_wr_data_s cn58xx;
- struct cvmx_pci_win_wr_data_s cn58xxp1;
};
union cvmx_pci_win_wr_mask {
@@ -2417,13 +2032,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_pci_win_wr_mask_s cn30xx;
- struct cvmx_pci_win_wr_mask_s cn31xx;
- struct cvmx_pci_win_wr_mask_s cn38xx;
- struct cvmx_pci_win_wr_mask_s cn38xxp2;
- struct cvmx_pci_win_wr_mask_s cn50xx;
- struct cvmx_pci_win_wr_mask_s cn58xx;
- struct cvmx_pci_win_wr_mask_s cn58xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
index 39da7f9..5f01326 100644
--- a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
@@ -361,17 +361,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsx_anx_adv_reg_s cn52xx;
- struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
- struct cvmx_pcsx_anx_adv_reg_s cn56xx;
- struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
- struct cvmx_pcsx_anx_adv_reg_s cn61xx;
- struct cvmx_pcsx_anx_adv_reg_s cn63xx;
- struct cvmx_pcsx_anx_adv_reg_s cn63xxp1;
- struct cvmx_pcsx_anx_adv_reg_s cn66xx;
- struct cvmx_pcsx_anx_adv_reg_s cn68xx;
- struct cvmx_pcsx_anx_adv_reg_s cn68xxp1;
- struct cvmx_pcsx_anx_adv_reg_s cnf71xx;
};
union cvmx_pcsx_anx_ext_st_reg {
@@ -393,17 +382,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
- struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
- struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
- struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
- struct cvmx_pcsx_anx_ext_st_reg_s cn61xx;
- struct cvmx_pcsx_anx_ext_st_reg_s cn63xx;
- struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1;
- struct cvmx_pcsx_anx_ext_st_reg_s cn66xx;
- struct cvmx_pcsx_anx_ext_st_reg_s cn68xx;
- struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1;
- struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx;
};
union cvmx_pcsx_anx_lp_abil_reg {
@@ -431,17 +409,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
- struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
- struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
- struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
- struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx;
- struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx;
- struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1;
- struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx;
- struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx;
- struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1;
- struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx;
};
union cvmx_pcsx_anx_results_reg {
@@ -463,17 +430,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_pcsx_anx_results_reg_s cn52xx;
- struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
- struct cvmx_pcsx_anx_results_reg_s cn56xx;
- struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
- struct cvmx_pcsx_anx_results_reg_s cn61xx;
- struct cvmx_pcsx_anx_results_reg_s cn63xx;
- struct cvmx_pcsx_anx_results_reg_s cn63xxp1;
- struct cvmx_pcsx_anx_results_reg_s cn66xx;
- struct cvmx_pcsx_anx_results_reg_s cn68xx;
- struct cvmx_pcsx_anx_results_reg_s cn68xxp1;
- struct cvmx_pcsx_anx_results_reg_s cnf71xx;
};
union cvmx_pcsx_intx_en_reg {
@@ -542,16 +498,6 @@
uint64_t reserved_12_63:52;
#endif
} cn52xx;
- struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1;
- struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx;
- struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1;
- struct cvmx_pcsx_intx_en_reg_s cn61xx;
- struct cvmx_pcsx_intx_en_reg_s cn63xx;
- struct cvmx_pcsx_intx_en_reg_s cn63xxp1;
- struct cvmx_pcsx_intx_en_reg_s cn66xx;
- struct cvmx_pcsx_intx_en_reg_s cn68xx;
- struct cvmx_pcsx_intx_en_reg_s cn68xxp1;
- struct cvmx_pcsx_intx_en_reg_s cnf71xx;
};
union cvmx_pcsx_intx_reg {
@@ -620,16 +566,6 @@
uint64_t reserved_12_63:52;
#endif
} cn52xx;
- struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1;
- struct cvmx_pcsx_intx_reg_cn52xx cn56xx;
- struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1;
- struct cvmx_pcsx_intx_reg_s cn61xx;
- struct cvmx_pcsx_intx_reg_s cn63xx;
- struct cvmx_pcsx_intx_reg_s cn63xxp1;
- struct cvmx_pcsx_intx_reg_s cn66xx;
- struct cvmx_pcsx_intx_reg_s cn68xx;
- struct cvmx_pcsx_intx_reg_s cn68xxp1;
- struct cvmx_pcsx_intx_reg_s cnf71xx;
};
union cvmx_pcsx_linkx_timer_count_reg {
@@ -643,17 +579,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
- struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
- struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
- struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
- struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx;
- struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;
- struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;
- struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx;
- struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx;
- struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1;
- struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx;
};
union cvmx_pcsx_log_anlx_reg {
@@ -671,17 +596,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_pcsx_log_anlx_reg_s cn52xx;
- struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
- struct cvmx_pcsx_log_anlx_reg_s cn56xx;
- struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
- struct cvmx_pcsx_log_anlx_reg_s cn61xx;
- struct cvmx_pcsx_log_anlx_reg_s cn63xx;
- struct cvmx_pcsx_log_anlx_reg_s cn63xxp1;
- struct cvmx_pcsx_log_anlx_reg_s cn66xx;
- struct cvmx_pcsx_log_anlx_reg_s cn68xx;
- struct cvmx_pcsx_log_anlx_reg_s cn68xxp1;
- struct cvmx_pcsx_log_anlx_reg_s cnf71xx;
};
union cvmx_pcsx_miscx_ctl_reg {
@@ -707,17 +621,6 @@
uint64_t reserved_13_63:51;
#endif
} s;
- struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
- struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
- struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
- struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
- struct cvmx_pcsx_miscx_ctl_reg_s cn61xx;
- struct cvmx_pcsx_miscx_ctl_reg_s cn63xx;
- struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1;
- struct cvmx_pcsx_miscx_ctl_reg_s cn66xx;
- struct cvmx_pcsx_miscx_ctl_reg_s cn68xx;
- struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1;
- struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx;
};
union cvmx_pcsx_mrx_control_reg {
@@ -753,17 +656,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsx_mrx_control_reg_s cn52xx;
- struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
- struct cvmx_pcsx_mrx_control_reg_s cn56xx;
- struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
- struct cvmx_pcsx_mrx_control_reg_s cn61xx;
- struct cvmx_pcsx_mrx_control_reg_s cn63xx;
- struct cvmx_pcsx_mrx_control_reg_s cn63xxp1;
- struct cvmx_pcsx_mrx_control_reg_s cn66xx;
- struct cvmx_pcsx_mrx_control_reg_s cn68xx;
- struct cvmx_pcsx_mrx_control_reg_s cn68xxp1;
- struct cvmx_pcsx_mrx_control_reg_s cnf71xx;
};
union cvmx_pcsx_mrx_status_reg {
@@ -807,17 +699,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsx_mrx_status_reg_s cn52xx;
- struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
- struct cvmx_pcsx_mrx_status_reg_s cn56xx;
- struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
- struct cvmx_pcsx_mrx_status_reg_s cn61xx;
- struct cvmx_pcsx_mrx_status_reg_s cn63xx;
- struct cvmx_pcsx_mrx_status_reg_s cn63xxp1;
- struct cvmx_pcsx_mrx_status_reg_s cn66xx;
- struct cvmx_pcsx_mrx_status_reg_s cn68xx;
- struct cvmx_pcsx_mrx_status_reg_s cn68xxp1;
- struct cvmx_pcsx_mrx_status_reg_s cnf71xx;
};
union cvmx_pcsx_rxx_states_reg {
@@ -841,17 +722,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsx_rxx_states_reg_s cn52xx;
- struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
- struct cvmx_pcsx_rxx_states_reg_s cn56xx;
- struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
- struct cvmx_pcsx_rxx_states_reg_s cn61xx;
- struct cvmx_pcsx_rxx_states_reg_s cn63xx;
- struct cvmx_pcsx_rxx_states_reg_s cn63xxp1;
- struct cvmx_pcsx_rxx_states_reg_s cn66xx;
- struct cvmx_pcsx_rxx_states_reg_s cn68xx;
- struct cvmx_pcsx_rxx_states_reg_s cn68xxp1;
- struct cvmx_pcsx_rxx_states_reg_s cnf71xx;
};
union cvmx_pcsx_rxx_sync_reg {
@@ -867,17 +737,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
- struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
- struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
- struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
- struct cvmx_pcsx_rxx_sync_reg_s cn61xx;
- struct cvmx_pcsx_rxx_sync_reg_s cn63xx;
- struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1;
- struct cvmx_pcsx_rxx_sync_reg_s cn66xx;
- struct cvmx_pcsx_rxx_sync_reg_s cn68xx;
- struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1;
- struct cvmx_pcsx_rxx_sync_reg_s cnf71xx;
};
union cvmx_pcsx_sgmx_an_adv_reg {
@@ -903,17 +762,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1;
- struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx;
};
union cvmx_pcsx_sgmx_lp_adv_reg {
@@ -937,17 +785,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1;
- struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx;
};
union cvmx_pcsx_txx_states_reg {
@@ -965,17 +802,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_pcsx_txx_states_reg_s cn52xx;
- struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
- struct cvmx_pcsx_txx_states_reg_s cn56xx;
- struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
- struct cvmx_pcsx_txx_states_reg_s cn61xx;
- struct cvmx_pcsx_txx_states_reg_s cn63xx;
- struct cvmx_pcsx_txx_states_reg_s cn63xxp1;
- struct cvmx_pcsx_txx_states_reg_s cn66xx;
- struct cvmx_pcsx_txx_states_reg_s cn68xx;
- struct cvmx_pcsx_txx_states_reg_s cn68xxp1;
- struct cvmx_pcsx_txx_states_reg_s cnf71xx;
};
union cvmx_pcsx_tx_rxx_polarity_reg {
@@ -995,17 +821,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1;
- struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
index 847dd9d..b353775 100644
--- a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
@@ -293,16 +293,6 @@
uint64_t reserved_13_63:51;
#endif
} s;
- struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
- struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
- struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
- struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
- struct cvmx_pcsxx_10gbx_status_reg_s cn61xx;
- struct cvmx_pcsxx_10gbx_status_reg_s cn63xx;
- struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1;
- struct cvmx_pcsxx_10gbx_status_reg_s cn66xx;
- struct cvmx_pcsxx_10gbx_status_reg_s cn68xx;
- struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1;
};
union cvmx_pcsxx_bist_status_reg {
@@ -316,16 +306,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_pcsxx_bist_status_reg_s cn52xx;
- struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
- struct cvmx_pcsxx_bist_status_reg_s cn56xx;
- struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
- struct cvmx_pcsxx_bist_status_reg_s cn61xx;
- struct cvmx_pcsxx_bist_status_reg_s cn63xx;
- struct cvmx_pcsxx_bist_status_reg_s cn63xxp1;
- struct cvmx_pcsxx_bist_status_reg_s cn66xx;
- struct cvmx_pcsxx_bist_status_reg_s cn68xx;
- struct cvmx_pcsxx_bist_status_reg_s cn68xxp1;
};
union cvmx_pcsxx_bit_lock_status_reg {
@@ -345,16 +325,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
- struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
- struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
- struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
- struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx;
- struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx;
- struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1;
- struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx;
- struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx;
- struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1;
};
union cvmx_pcsxx_control1_reg {
@@ -384,16 +354,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsxx_control1_reg_s cn52xx;
- struct cvmx_pcsxx_control1_reg_s cn52xxp1;
- struct cvmx_pcsxx_control1_reg_s cn56xx;
- struct cvmx_pcsxx_control1_reg_s cn56xxp1;
- struct cvmx_pcsxx_control1_reg_s cn61xx;
- struct cvmx_pcsxx_control1_reg_s cn63xx;
- struct cvmx_pcsxx_control1_reg_s cn63xxp1;
- struct cvmx_pcsxx_control1_reg_s cn66xx;
- struct cvmx_pcsxx_control1_reg_s cn68xx;
- struct cvmx_pcsxx_control1_reg_s cn68xxp1;
};
union cvmx_pcsxx_control2_reg {
@@ -407,16 +367,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_pcsxx_control2_reg_s cn52xx;
- struct cvmx_pcsxx_control2_reg_s cn52xxp1;
- struct cvmx_pcsxx_control2_reg_s cn56xx;
- struct cvmx_pcsxx_control2_reg_s cn56xxp1;
- struct cvmx_pcsxx_control2_reg_s cn61xx;
- struct cvmx_pcsxx_control2_reg_s cn63xx;
- struct cvmx_pcsxx_control2_reg_s cn63xxp1;
- struct cvmx_pcsxx_control2_reg_s cn66xx;
- struct cvmx_pcsxx_control2_reg_s cn68xx;
- struct cvmx_pcsxx_control2_reg_s cn68xxp1;
};
union cvmx_pcsxx_int_en_reg {
@@ -461,15 +411,6 @@
uint64_t reserved_6_63:58;
#endif
} cn52xx;
- struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1;
- struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx;
- struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1;
- struct cvmx_pcsxx_int_en_reg_s cn61xx;
- struct cvmx_pcsxx_int_en_reg_s cn63xx;
- struct cvmx_pcsxx_int_en_reg_s cn63xxp1;
- struct cvmx_pcsxx_int_en_reg_s cn66xx;
- struct cvmx_pcsxx_int_en_reg_s cn68xx;
- struct cvmx_pcsxx_int_en_reg_s cn68xxp1;
};
union cvmx_pcsxx_int_reg {
@@ -514,15 +455,6 @@
uint64_t reserved_6_63:58;
#endif
} cn52xx;
- struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1;
- struct cvmx_pcsxx_int_reg_cn52xx cn56xx;
- struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1;
- struct cvmx_pcsxx_int_reg_s cn61xx;
- struct cvmx_pcsxx_int_reg_s cn63xx;
- struct cvmx_pcsxx_int_reg_s cn63xxp1;
- struct cvmx_pcsxx_int_reg_s cn66xx;
- struct cvmx_pcsxx_int_reg_s cn68xx;
- struct cvmx_pcsxx_int_reg_s cn68xxp1;
};
union cvmx_pcsxx_log_anl_reg {
@@ -544,16 +476,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_pcsxx_log_anl_reg_s cn52xx;
- struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
- struct cvmx_pcsxx_log_anl_reg_s cn56xx;
- struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
- struct cvmx_pcsxx_log_anl_reg_s cn61xx;
- struct cvmx_pcsxx_log_anl_reg_s cn63xx;
- struct cvmx_pcsxx_log_anl_reg_s cn63xxp1;
- struct cvmx_pcsxx_log_anl_reg_s cn66xx;
- struct cvmx_pcsxx_log_anl_reg_s cn68xx;
- struct cvmx_pcsxx_log_anl_reg_s cn68xxp1;
};
union cvmx_pcsxx_misc_ctl_reg {
@@ -573,16 +495,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
- struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
- struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
- struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
- struct cvmx_pcsxx_misc_ctl_reg_s cn61xx;
- struct cvmx_pcsxx_misc_ctl_reg_s cn63xx;
- struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1;
- struct cvmx_pcsxx_misc_ctl_reg_s cn66xx;
- struct cvmx_pcsxx_misc_ctl_reg_s cn68xx;
- struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1;
};
union cvmx_pcsxx_rx_sync_states_reg {
@@ -602,16 +514,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
- struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
- struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
- struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
- struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx;
- struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx;
- struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1;
- struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx;
- struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx;
- struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1;
};
union cvmx_pcsxx_spd_abil_reg {
@@ -627,16 +529,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
- struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
- struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
- struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
- struct cvmx_pcsxx_spd_abil_reg_s cn61xx;
- struct cvmx_pcsxx_spd_abil_reg_s cn63xx;
- struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1;
- struct cvmx_pcsxx_spd_abil_reg_s cn66xx;
- struct cvmx_pcsxx_spd_abil_reg_s cn68xx;
- struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1;
};
union cvmx_pcsxx_status1_reg {
@@ -658,16 +550,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_pcsxx_status1_reg_s cn52xx;
- struct cvmx_pcsxx_status1_reg_s cn52xxp1;
- struct cvmx_pcsxx_status1_reg_s cn56xx;
- struct cvmx_pcsxx_status1_reg_s cn56xxp1;
- struct cvmx_pcsxx_status1_reg_s cn61xx;
- struct cvmx_pcsxx_status1_reg_s cn63xx;
- struct cvmx_pcsxx_status1_reg_s cn63xxp1;
- struct cvmx_pcsxx_status1_reg_s cn66xx;
- struct cvmx_pcsxx_status1_reg_s cn68xx;
- struct cvmx_pcsxx_status1_reg_s cn68xxp1;
};
union cvmx_pcsxx_status2_reg {
@@ -695,16 +577,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pcsxx_status2_reg_s cn52xx;
- struct cvmx_pcsxx_status2_reg_s cn52xxp1;
- struct cvmx_pcsxx_status2_reg_s cn56xx;
- struct cvmx_pcsxx_status2_reg_s cn56xxp1;
- struct cvmx_pcsxx_status2_reg_s cn61xx;
- struct cvmx_pcsxx_status2_reg_s cn63xx;
- struct cvmx_pcsxx_status2_reg_s cn63xxp1;
- struct cvmx_pcsxx_status2_reg_s cn66xx;
- struct cvmx_pcsxx_status2_reg_s cn68xx;
- struct cvmx_pcsxx_status2_reg_s cn68xxp1;
};
union cvmx_pcsxx_tx_rx_polarity_reg {
@@ -724,7 +596,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_2_63:62;
@@ -736,14 +607,6 @@
uint64_t reserved_2_63:62;
#endif
} cn52xxp1;
- struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
- struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
- struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx;
- struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx;
- struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1;
- struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx;
- struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx;
- struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1;
};
union cvmx_pcsxx_tx_rx_states_reg {
@@ -773,7 +636,6 @@
uint64_t reserved_14_63:50;
#endif
} s;
- struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_13_63:51;
@@ -797,14 +659,6 @@
uint64_t reserved_13_63:51;
#endif
} cn52xxp1;
- struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
- struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
- struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx;
- struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx;
- struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1;
- struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx;
- struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx;
- struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
index 50a916f..d2d6dba 100644
--- a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
@@ -68,13 +68,6 @@
uint64_t reserved_20_63:44;
#endif
} s;
- struct cvmx_pemx_bar1_indexx_s cn61xx;
- struct cvmx_pemx_bar1_indexx_s cn63xx;
- struct cvmx_pemx_bar1_indexx_s cn63xxp1;
- struct cvmx_pemx_bar1_indexx_s cn66xx;
- struct cvmx_pemx_bar1_indexx_s cn68xx;
- struct cvmx_pemx_bar1_indexx_s cn68xxp1;
- struct cvmx_pemx_bar1_indexx_s cnf71xx;
};
union cvmx_pemx_bar2_mask {
@@ -90,11 +83,6 @@
uint64_t reserved_38_63:26;
#endif
} s;
- struct cvmx_pemx_bar2_mask_s cn61xx;
- struct cvmx_pemx_bar2_mask_s cn66xx;
- struct cvmx_pemx_bar2_mask_s cn68xx;
- struct cvmx_pemx_bar2_mask_s cn68xxp1;
- struct cvmx_pemx_bar2_mask_s cnf71xx;
};
union cvmx_pemx_bar_ctl {
@@ -114,13 +102,6 @@
uint64_t reserved_7_63:57;
#endif
} s;
- struct cvmx_pemx_bar_ctl_s cn61xx;
- struct cvmx_pemx_bar_ctl_s cn63xx;
- struct cvmx_pemx_bar_ctl_s cn63xxp1;
- struct cvmx_pemx_bar_ctl_s cn66xx;
- struct cvmx_pemx_bar_ctl_s cn68xx;
- struct cvmx_pemx_bar_ctl_s cn68xxp1;
- struct cvmx_pemx_bar_ctl_s cnf71xx;
};
union cvmx_pemx_bist_status {
@@ -148,13 +129,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_pemx_bist_status_s cn61xx;
- struct cvmx_pemx_bist_status_s cn63xx;
- struct cvmx_pemx_bist_status_s cn63xxp1;
- struct cvmx_pemx_bist_status_s cn66xx;
- struct cvmx_pemx_bist_status_s cn68xx;
- struct cvmx_pemx_bist_status_s cn68xxp1;
- struct cvmx_pemx_bist_status_s cnf71xx;
};
union cvmx_pemx_bist_status2 {
@@ -186,13 +160,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_pemx_bist_status2_s cn61xx;
- struct cvmx_pemx_bist_status2_s cn63xx;
- struct cvmx_pemx_bist_status2_s cn63xxp1;
- struct cvmx_pemx_bist_status2_s cn66xx;
- struct cvmx_pemx_bist_status2_s cn68xx;
- struct cvmx_pemx_bist_status2_s cn68xxp1;
- struct cvmx_pemx_bist_status2_s cnf71xx;
};
union cvmx_pemx_cfg_rd {
@@ -206,13 +173,6 @@
uint64_t data:32;
#endif
} s;
- struct cvmx_pemx_cfg_rd_s cn61xx;
- struct cvmx_pemx_cfg_rd_s cn63xx;
- struct cvmx_pemx_cfg_rd_s cn63xxp1;
- struct cvmx_pemx_cfg_rd_s cn66xx;
- struct cvmx_pemx_cfg_rd_s cn68xx;
- struct cvmx_pemx_cfg_rd_s cn68xxp1;
- struct cvmx_pemx_cfg_rd_s cnf71xx;
};
union cvmx_pemx_cfg_wr {
@@ -226,13 +186,6 @@
uint64_t data:32;
#endif
} s;
- struct cvmx_pemx_cfg_wr_s cn61xx;
- struct cvmx_pemx_cfg_wr_s cn63xx;
- struct cvmx_pemx_cfg_wr_s cn63xxp1;
- struct cvmx_pemx_cfg_wr_s cn66xx;
- struct cvmx_pemx_cfg_wr_s cn68xx;
- struct cvmx_pemx_cfg_wr_s cn68xxp1;
- struct cvmx_pemx_cfg_wr_s cnf71xx;
};
union cvmx_pemx_cpl_lut_valid {
@@ -246,13 +199,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pemx_cpl_lut_valid_s cn61xx;
- struct cvmx_pemx_cpl_lut_valid_s cn63xx;
- struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
- struct cvmx_pemx_cpl_lut_valid_s cn66xx;
- struct cvmx_pemx_cpl_lut_valid_s cn68xx;
- struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
- struct cvmx_pemx_cpl_lut_valid_s cnf71xx;
};
union cvmx_pemx_ctl_status {
@@ -298,13 +244,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_pemx_ctl_status_s cn61xx;
- struct cvmx_pemx_ctl_status_s cn63xx;
- struct cvmx_pemx_ctl_status_s cn63xxp1;
- struct cvmx_pemx_ctl_status_s cn66xx;
- struct cvmx_pemx_ctl_status_s cn68xx;
- struct cvmx_pemx_ctl_status_s cn68xxp1;
- struct cvmx_pemx_ctl_status_s cnf71xx;
};
union cvmx_pemx_dbg_info {
@@ -378,13 +317,6 @@
uint64_t reserved_31_63:33;
#endif
} s;
- struct cvmx_pemx_dbg_info_s cn61xx;
- struct cvmx_pemx_dbg_info_s cn63xx;
- struct cvmx_pemx_dbg_info_s cn63xxp1;
- struct cvmx_pemx_dbg_info_s cn66xx;
- struct cvmx_pemx_dbg_info_s cn68xx;
- struct cvmx_pemx_dbg_info_s cn68xxp1;
- struct cvmx_pemx_dbg_info_s cnf71xx;
};
union cvmx_pemx_dbg_info_en {
@@ -458,13 +390,6 @@
uint64_t reserved_31_63:33;
#endif
} s;
- struct cvmx_pemx_dbg_info_en_s cn61xx;
- struct cvmx_pemx_dbg_info_en_s cn63xx;
- struct cvmx_pemx_dbg_info_en_s cn63xxp1;
- struct cvmx_pemx_dbg_info_en_s cn66xx;
- struct cvmx_pemx_dbg_info_en_s cn68xx;
- struct cvmx_pemx_dbg_info_en_s cn68xxp1;
- struct cvmx_pemx_dbg_info_en_s cnf71xx;
};
union cvmx_pemx_diag_status {
@@ -484,13 +409,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_pemx_diag_status_s cn61xx;
- struct cvmx_pemx_diag_status_s cn63xx;
- struct cvmx_pemx_diag_status_s cn63xxp1;
- struct cvmx_pemx_diag_status_s cn66xx;
- struct cvmx_pemx_diag_status_s cn68xx;
- struct cvmx_pemx_diag_status_s cn68xxp1;
- struct cvmx_pemx_diag_status_s cnf71xx;
};
union cvmx_pemx_inb_read_credits {
@@ -504,10 +422,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_pemx_inb_read_credits_s cn61xx;
- struct cvmx_pemx_inb_read_credits_s cn66xx;
- struct cvmx_pemx_inb_read_credits_s cn68xx;
- struct cvmx_pemx_inb_read_credits_s cnf71xx;
};
union cvmx_pemx_int_enb {
@@ -547,13 +461,6 @@
uint64_t reserved_14_63:50;
#endif
} s;
- struct cvmx_pemx_int_enb_s cn61xx;
- struct cvmx_pemx_int_enb_s cn63xx;
- struct cvmx_pemx_int_enb_s cn63xxp1;
- struct cvmx_pemx_int_enb_s cn66xx;
- struct cvmx_pemx_int_enb_s cn68xx;
- struct cvmx_pemx_int_enb_s cn68xxp1;
- struct cvmx_pemx_int_enb_s cnf71xx;
};
union cvmx_pemx_int_enb_int {
@@ -593,13 +500,6 @@
uint64_t reserved_14_63:50;
#endif
} s;
- struct cvmx_pemx_int_enb_int_s cn61xx;
- struct cvmx_pemx_int_enb_int_s cn63xx;
- struct cvmx_pemx_int_enb_int_s cn63xxp1;
- struct cvmx_pemx_int_enb_int_s cn66xx;
- struct cvmx_pemx_int_enb_int_s cn68xx;
- struct cvmx_pemx_int_enb_int_s cn68xxp1;
- struct cvmx_pemx_int_enb_int_s cnf71xx;
};
union cvmx_pemx_int_sum {
@@ -639,13 +539,6 @@
uint64_t reserved_14_63:50;
#endif
} s;
- struct cvmx_pemx_int_sum_s cn61xx;
- struct cvmx_pemx_int_sum_s cn63xx;
- struct cvmx_pemx_int_sum_s cn63xxp1;
- struct cvmx_pemx_int_sum_s cn66xx;
- struct cvmx_pemx_int_sum_s cn68xx;
- struct cvmx_pemx_int_sum_s cn68xxp1;
- struct cvmx_pemx_int_sum_s cnf71xx;
};
union cvmx_pemx_p2n_bar0_start {
@@ -659,13 +552,6 @@
uint64_t addr:50;
#endif
} s;
- struct cvmx_pemx_p2n_bar0_start_s cn61xx;
- struct cvmx_pemx_p2n_bar0_start_s cn63xx;
- struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
- struct cvmx_pemx_p2n_bar0_start_s cn66xx;
- struct cvmx_pemx_p2n_bar0_start_s cn68xx;
- struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
- struct cvmx_pemx_p2n_bar0_start_s cnf71xx;
};
union cvmx_pemx_p2n_bar1_start {
@@ -679,13 +565,6 @@
uint64_t addr:38;
#endif
} s;
- struct cvmx_pemx_p2n_bar1_start_s cn61xx;
- struct cvmx_pemx_p2n_bar1_start_s cn63xx;
- struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
- struct cvmx_pemx_p2n_bar1_start_s cn66xx;
- struct cvmx_pemx_p2n_bar1_start_s cn68xx;
- struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
- struct cvmx_pemx_p2n_bar1_start_s cnf71xx;
};
union cvmx_pemx_p2n_bar2_start {
@@ -699,13 +578,6 @@
uint64_t addr:23;
#endif
} s;
- struct cvmx_pemx_p2n_bar2_start_s cn61xx;
- struct cvmx_pemx_p2n_bar2_start_s cn63xx;
- struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
- struct cvmx_pemx_p2n_bar2_start_s cn66xx;
- struct cvmx_pemx_p2n_bar2_start_s cn68xx;
- struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
- struct cvmx_pemx_p2n_bar2_start_s cnf71xx;
};
union cvmx_pemx_p2p_barx_end {
@@ -719,11 +591,6 @@
uint64_t addr:52;
#endif
} s;
- struct cvmx_pemx_p2p_barx_end_s cn63xx;
- struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
- struct cvmx_pemx_p2p_barx_end_s cn66xx;
- struct cvmx_pemx_p2p_barx_end_s cn68xx;
- struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
};
union cvmx_pemx_p2p_barx_start {
@@ -737,11 +604,6 @@
uint64_t addr:52;
#endif
} s;
- struct cvmx_pemx_p2p_barx_start_s cn63xx;
- struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
- struct cvmx_pemx_p2p_barx_start_s cn66xx;
- struct cvmx_pemx_p2p_barx_start_s cn68xx;
- struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
};
union cvmx_pemx_tlp_credits {
@@ -784,12 +646,6 @@
uint64_t reserved_56_63:8;
#endif
} cn61xx;
- struct cvmx_pemx_tlp_credits_s cn63xx;
- struct cvmx_pemx_tlp_credits_s cn63xxp1;
- struct cvmx_pemx_tlp_credits_s cn66xx;
- struct cvmx_pemx_tlp_credits_s cn68xx;
- struct cvmx_pemx_tlp_credits_s cn68xxp1;
- struct cvmx_pemx_tlp_credits_cn61xx cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
index 59b3dc5..6656108 100644
--- a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
@@ -80,7 +80,6 @@
uint64_t reserved_13_63:51;
#endif
} s;
- struct cvmx_pescx_bist_status_s cn52xx;
struct cvmx_pescx_bist_status_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -112,8 +111,6 @@
uint64_t reserved_12_63:52;
#endif
} cn52xxp1;
- struct cvmx_pescx_bist_status_s cn56xx;
- struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
};
union cvmx_pescx_bist_status2 {
@@ -153,10 +150,6 @@
uint64_t reserved_14_63:50;
#endif
} s;
- struct cvmx_pescx_bist_status2_s cn52xx;
- struct cvmx_pescx_bist_status2_s cn52xxp1;
- struct cvmx_pescx_bist_status2_s cn56xx;
- struct cvmx_pescx_bist_status2_s cn56xxp1;
};
union cvmx_pescx_cfg_rd {
@@ -170,10 +163,6 @@
uint64_t data:32;
#endif
} s;
- struct cvmx_pescx_cfg_rd_s cn52xx;
- struct cvmx_pescx_cfg_rd_s cn52xxp1;
- struct cvmx_pescx_cfg_rd_s cn56xx;
- struct cvmx_pescx_cfg_rd_s cn56xxp1;
};
union cvmx_pescx_cfg_wr {
@@ -187,10 +176,6 @@
uint64_t data:32;
#endif
} s;
- struct cvmx_pescx_cfg_wr_s cn52xx;
- struct cvmx_pescx_cfg_wr_s cn52xxp1;
- struct cvmx_pescx_cfg_wr_s cn56xx;
- struct cvmx_pescx_cfg_wr_s cn56xxp1;
};
union cvmx_pescx_cpl_lut_valid {
@@ -204,10 +189,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pescx_cpl_lut_valid_s cn52xx;
- struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
- struct cvmx_pescx_cpl_lut_valid_s cn56xx;
- struct cvmx_pescx_cpl_lut_valid_s cn56xxp1;
};
union cvmx_pescx_ctl_status {
@@ -249,8 +230,6 @@
uint64_t reserved_28_63:36;
#endif
} s;
- struct cvmx_pescx_ctl_status_s cn52xx;
- struct cvmx_pescx_ctl_status_s cn52xxp1;
struct cvmx_pescx_ctl_status_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
@@ -288,7 +267,6 @@
uint64_t reserved_28_63:36;
#endif
} cn56xx;
- struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
};
union cvmx_pescx_ctl_status2 {
@@ -304,7 +282,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_pescx_ctl_status2_s cn52xx;
struct cvmx_pescx_ctl_status2_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_1_63:63;
@@ -314,8 +291,6 @@
uint64_t reserved_1_63:63;
#endif
} cn52xxp1;
- struct cvmx_pescx_ctl_status2_s cn56xx;
- struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
};
union cvmx_pescx_dbg_info {
@@ -389,10 +364,6 @@
uint64_t reserved_31_63:33;
#endif
} s;
- struct cvmx_pescx_dbg_info_s cn52xx;
- struct cvmx_pescx_dbg_info_s cn52xxp1;
- struct cvmx_pescx_dbg_info_s cn56xx;
- struct cvmx_pescx_dbg_info_s cn56xxp1;
};
union cvmx_pescx_dbg_info_en {
@@ -466,10 +437,6 @@
uint64_t reserved_31_63:33;
#endif
} s;
- struct cvmx_pescx_dbg_info_en_s cn52xx;
- struct cvmx_pescx_dbg_info_en_s cn52xxp1;
- struct cvmx_pescx_dbg_info_en_s cn56xx;
- struct cvmx_pescx_dbg_info_en_s cn56xxp1;
};
union cvmx_pescx_diag_status {
@@ -489,10 +456,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_pescx_diag_status_s cn52xx;
- struct cvmx_pescx_diag_status_s cn52xxp1;
- struct cvmx_pescx_diag_status_s cn56xx;
- struct cvmx_pescx_diag_status_s cn56xxp1;
};
union cvmx_pescx_p2n_bar0_start {
@@ -506,10 +469,6 @@
uint64_t addr:50;
#endif
} s;
- struct cvmx_pescx_p2n_bar0_start_s cn52xx;
- struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
- struct cvmx_pescx_p2n_bar0_start_s cn56xx;
- struct cvmx_pescx_p2n_bar0_start_s cn56xxp1;
};
union cvmx_pescx_p2n_bar1_start {
@@ -523,10 +482,6 @@
uint64_t addr:38;
#endif
} s;
- struct cvmx_pescx_p2n_bar1_start_s cn52xx;
- struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
- struct cvmx_pescx_p2n_bar1_start_s cn56xx;
- struct cvmx_pescx_p2n_bar1_start_s cn56xxp1;
};
union cvmx_pescx_p2n_bar2_start {
@@ -540,10 +495,6 @@
uint64_t addr:25;
#endif
} s;
- struct cvmx_pescx_p2n_bar2_start_s cn52xx;
- struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
- struct cvmx_pescx_p2n_bar2_start_s cn56xx;
- struct cvmx_pescx_p2n_bar2_start_s cn56xxp1;
};
union cvmx_pescx_p2p_barx_end {
@@ -557,10 +508,6 @@
uint64_t addr:52;
#endif
} s;
- struct cvmx_pescx_p2p_barx_end_s cn52xx;
- struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
- struct cvmx_pescx_p2p_barx_end_s cn56xx;
- struct cvmx_pescx_p2p_barx_end_s cn56xxp1;
};
union cvmx_pescx_p2p_barx_start {
@@ -574,10 +521,6 @@
uint64_t addr:52;
#endif
} s;
- struct cvmx_pescx_p2p_barx_start_s cn52xx;
- struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
- struct cvmx_pescx_p2p_barx_start_s cn56xx;
- struct cvmx_pescx_p2p_barx_start_s cn56xxp1;
};
union cvmx_pescx_tlp_credits {
@@ -631,8 +574,6 @@
uint64_t reserved_38_63:26;
#endif
} cn52xxp1;
- struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
- struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
index e975c7d..e42f411 100644
--- a/arch/mips/include/asm/octeon/cvmx-pip-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
@@ -160,10 +160,6 @@
uint64_t reserved_57_63:7;
#endif
} s;
- struct cvmx_pip_alt_skip_cfgx_s cn61xx;
- struct cvmx_pip_alt_skip_cfgx_s cn66xx;
- struct cvmx_pip_alt_skip_cfgx_s cn68xx;
- struct cvmx_pip_alt_skip_cfgx_s cnf71xx;
};
union cvmx_pip_bck_prs {
@@ -183,19 +179,6 @@
uint64_t bckprs:1;
#endif
} s;
- struct cvmx_pip_bck_prs_s cn38xx;
- struct cvmx_pip_bck_prs_s cn38xxp2;
- struct cvmx_pip_bck_prs_s cn56xx;
- struct cvmx_pip_bck_prs_s cn56xxp1;
- struct cvmx_pip_bck_prs_s cn58xx;
- struct cvmx_pip_bck_prs_s cn58xxp1;
- struct cvmx_pip_bck_prs_s cn61xx;
- struct cvmx_pip_bck_prs_s cn63xx;
- struct cvmx_pip_bck_prs_s cn63xxp1;
- struct cvmx_pip_bck_prs_s cn66xx;
- struct cvmx_pip_bck_prs_s cn68xx;
- struct cvmx_pip_bck_prs_s cn68xxp1;
- struct cvmx_pip_bck_prs_s cnf71xx;
};
union cvmx_pip_bist_status {
@@ -218,9 +201,6 @@
uint64_t reserved_18_63:46;
#endif
} cn30xx;
- struct cvmx_pip_bist_status_cn30xx cn31xx;
- struct cvmx_pip_bist_status_cn30xx cn38xx;
- struct cvmx_pip_bist_status_cn30xx cn38xxp2;
struct cvmx_pip_bist_status_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_17_63:47;
@@ -230,12 +210,6 @@
uint64_t reserved_17_63:47;
#endif
} cn50xx;
- struct cvmx_pip_bist_status_cn30xx cn52xx;
- struct cvmx_pip_bist_status_cn30xx cn52xxp1;
- struct cvmx_pip_bist_status_cn30xx cn56xx;
- struct cvmx_pip_bist_status_cn30xx cn56xxp1;
- struct cvmx_pip_bist_status_cn30xx cn58xx;
- struct cvmx_pip_bist_status_cn30xx cn58xxp1;
struct cvmx_pip_bist_status_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -245,12 +219,6 @@
uint64_t reserved_20_63:44;
#endif
} cn61xx;
- struct cvmx_pip_bist_status_cn30xx cn63xx;
- struct cvmx_pip_bist_status_cn30xx cn63xxp1;
- struct cvmx_pip_bist_status_cn61xx cn66xx;
- struct cvmx_pip_bist_status_s cn68xx;
- struct cvmx_pip_bist_status_cn61xx cn68xxp1;
- struct cvmx_pip_bist_status_cn61xx cnf71xx;
};
union cvmx_pip_bsel_ext_cfgx {
@@ -274,9 +242,6 @@
uint64_t reserved_56_63:8;
#endif
} s;
- struct cvmx_pip_bsel_ext_cfgx_s cn61xx;
- struct cvmx_pip_bsel_ext_cfgx_s cn68xx;
- struct cvmx_pip_bsel_ext_cfgx_s cnf71xx;
};
union cvmx_pip_bsel_ext_posx {
@@ -318,9 +283,6 @@
uint64_t pos7_val:1;
#endif
} s;
- struct cvmx_pip_bsel_ext_posx_s cn61xx;
- struct cvmx_pip_bsel_ext_posx_s cn68xx;
- struct cvmx_pip_bsel_ext_posx_s cnf71xx;
};
union cvmx_pip_bsel_tbl_entx {
@@ -383,8 +345,6 @@
uint64_t tag_en:1;
#endif
} cn61xx;
- struct cvmx_pip_bsel_tbl_entx_s cn68xx;
- struct cvmx_pip_bsel_tbl_entx_cn61xx cnf71xx;
};
union cvmx_pip_clken {
@@ -398,13 +358,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_pip_clken_s cn61xx;
- struct cvmx_pip_clken_s cn63xx;
- struct cvmx_pip_clken_s cn63xxp1;
- struct cvmx_pip_clken_s cn66xx;
- struct cvmx_pip_clken_s cn68xx;
- struct cvmx_pip_clken_s cn68xxp1;
- struct cvmx_pip_clken_s cnf71xx;
};
union cvmx_pip_crc_ctlx {
@@ -420,10 +373,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_pip_crc_ctlx_s cn38xx;
- struct cvmx_pip_crc_ctlx_s cn38xxp2;
- struct cvmx_pip_crc_ctlx_s cn58xx;
- struct cvmx_pip_crc_ctlx_s cn58xxp1;
};
union cvmx_pip_crc_ivx {
@@ -437,10 +386,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pip_crc_ivx_s cn38xx;
- struct cvmx_pip_crc_ivx_s cn38xxp2;
- struct cvmx_pip_crc_ivx_s cn58xx;
- struct cvmx_pip_crc_ivx_s cn58xxp1;
};
union cvmx_pip_dec_ipsecx {
@@ -458,24 +403,6 @@
uint64_t reserved_18_63:46;
#endif
} s;
- struct cvmx_pip_dec_ipsecx_s cn30xx;
- struct cvmx_pip_dec_ipsecx_s cn31xx;
- struct cvmx_pip_dec_ipsecx_s cn38xx;
- struct cvmx_pip_dec_ipsecx_s cn38xxp2;
- struct cvmx_pip_dec_ipsecx_s cn50xx;
- struct cvmx_pip_dec_ipsecx_s cn52xx;
- struct cvmx_pip_dec_ipsecx_s cn52xxp1;
- struct cvmx_pip_dec_ipsecx_s cn56xx;
- struct cvmx_pip_dec_ipsecx_s cn56xxp1;
- struct cvmx_pip_dec_ipsecx_s cn58xx;
- struct cvmx_pip_dec_ipsecx_s cn58xxp1;
- struct cvmx_pip_dec_ipsecx_s cn61xx;
- struct cvmx_pip_dec_ipsecx_s cn63xx;
- struct cvmx_pip_dec_ipsecx_s cn63xxp1;
- struct cvmx_pip_dec_ipsecx_s cn66xx;
- struct cvmx_pip_dec_ipsecx_s cn68xx;
- struct cvmx_pip_dec_ipsecx_s cn68xxp1;
- struct cvmx_pip_dec_ipsecx_s cnf71xx;
};
union cvmx_pip_dsa_src_grp {
@@ -517,16 +444,6 @@
uint64_t map15:4;
#endif
} s;
- struct cvmx_pip_dsa_src_grp_s cn52xx;
- struct cvmx_pip_dsa_src_grp_s cn52xxp1;
- struct cvmx_pip_dsa_src_grp_s cn56xx;
- struct cvmx_pip_dsa_src_grp_s cn61xx;
- struct cvmx_pip_dsa_src_grp_s cn63xx;
- struct cvmx_pip_dsa_src_grp_s cn63xxp1;
- struct cvmx_pip_dsa_src_grp_s cn66xx;
- struct cvmx_pip_dsa_src_grp_s cn68xx;
- struct cvmx_pip_dsa_src_grp_s cn68xxp1;
- struct cvmx_pip_dsa_src_grp_s cnf71xx;
};
union cvmx_pip_dsa_vid_grp {
@@ -568,16 +485,6 @@
uint64_t map15:4;
#endif
} s;
- struct cvmx_pip_dsa_vid_grp_s cn52xx;
- struct cvmx_pip_dsa_vid_grp_s cn52xxp1;
- struct cvmx_pip_dsa_vid_grp_s cn56xx;
- struct cvmx_pip_dsa_vid_grp_s cn61xx;
- struct cvmx_pip_dsa_vid_grp_s cn63xx;
- struct cvmx_pip_dsa_vid_grp_s cn63xxp1;
- struct cvmx_pip_dsa_vid_grp_s cn66xx;
- struct cvmx_pip_dsa_vid_grp_s cn68xx;
- struct cvmx_pip_dsa_vid_grp_s cn68xxp1;
- struct cvmx_pip_dsa_vid_grp_s cnf71xx;
};
union cvmx_pip_frm_len_chkx {
@@ -593,18 +500,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pip_frm_len_chkx_s cn50xx;
- struct cvmx_pip_frm_len_chkx_s cn52xx;
- struct cvmx_pip_frm_len_chkx_s cn52xxp1;
- struct cvmx_pip_frm_len_chkx_s cn56xx;
- struct cvmx_pip_frm_len_chkx_s cn56xxp1;
- struct cvmx_pip_frm_len_chkx_s cn61xx;
- struct cvmx_pip_frm_len_chkx_s cn63xx;
- struct cvmx_pip_frm_len_chkx_s cn63xxp1;
- struct cvmx_pip_frm_len_chkx_s cn66xx;
- struct cvmx_pip_frm_len_chkx_s cn68xx;
- struct cvmx_pip_frm_len_chkx_s cn68xxp1;
- struct cvmx_pip_frm_len_chkx_s cnf71xx;
};
union cvmx_pip_gbl_cfg {
@@ -630,24 +525,6 @@
uint64_t reserved_19_63:45;
#endif
} s;
- struct cvmx_pip_gbl_cfg_s cn30xx;
- struct cvmx_pip_gbl_cfg_s cn31xx;
- struct cvmx_pip_gbl_cfg_s cn38xx;
- struct cvmx_pip_gbl_cfg_s cn38xxp2;
- struct cvmx_pip_gbl_cfg_s cn50xx;
- struct cvmx_pip_gbl_cfg_s cn52xx;
- struct cvmx_pip_gbl_cfg_s cn52xxp1;
- struct cvmx_pip_gbl_cfg_s cn56xx;
- struct cvmx_pip_gbl_cfg_s cn56xxp1;
- struct cvmx_pip_gbl_cfg_s cn58xx;
- struct cvmx_pip_gbl_cfg_s cn58xxp1;
- struct cvmx_pip_gbl_cfg_s cn61xx;
- struct cvmx_pip_gbl_cfg_s cn63xx;
- struct cvmx_pip_gbl_cfg_s cn63xxp1;
- struct cvmx_pip_gbl_cfg_s cn66xx;
- struct cvmx_pip_gbl_cfg_s cn68xx;
- struct cvmx_pip_gbl_cfg_s cn68xxp1;
- struct cvmx_pip_gbl_cfg_s cnf71xx;
};
union cvmx_pip_gbl_ctl {
@@ -742,10 +619,6 @@
uint64_t reserved_17_63:47;
#endif
} cn30xx;
- struct cvmx_pip_gbl_ctl_cn30xx cn31xx;
- struct cvmx_pip_gbl_ctl_cn30xx cn38xx;
- struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2;
- struct cvmx_pip_gbl_ctl_cn30xx cn50xx;
struct cvmx_pip_gbl_ctl_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_27_63:37;
@@ -795,8 +668,6 @@
uint64_t reserved_27_63:37;
#endif
} cn52xx;
- struct cvmx_pip_gbl_ctl_cn52xx cn52xxp1;
- struct cvmx_pip_gbl_ctl_cn52xx cn56xx;
struct cvmx_pip_gbl_ctl_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_21_63:43;
@@ -838,8 +709,6 @@
uint64_t reserved_21_63:43;
#endif
} cn56xxp1;
- struct cvmx_pip_gbl_ctl_cn30xx cn58xx;
- struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1;
struct cvmx_pip_gbl_ctl_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
@@ -891,9 +760,6 @@
uint64_t reserved_28_63:36;
#endif
} cn61xx;
- struct cvmx_pip_gbl_ctl_cn61xx cn63xx;
- struct cvmx_pip_gbl_ctl_cn61xx cn63xxp1;
- struct cvmx_pip_gbl_ctl_cn61xx cn66xx;
struct cvmx_pip_gbl_ctl_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
@@ -990,7 +856,6 @@
uint64_t reserved_28_63:36;
#endif
} cn68xxp1;
- struct cvmx_pip_gbl_ctl_cn61xx cnf71xx;
};
union cvmx_pip_hg_pri_qos {
@@ -1012,14 +877,6 @@
uint64_t reserved_13_63:51;
#endif
} s;
- struct cvmx_pip_hg_pri_qos_s cn52xx;
- struct cvmx_pip_hg_pri_qos_s cn52xxp1;
- struct cvmx_pip_hg_pri_qos_s cn56xx;
- struct cvmx_pip_hg_pri_qos_s cn61xx;
- struct cvmx_pip_hg_pri_qos_s cn63xx;
- struct cvmx_pip_hg_pri_qos_s cn63xxp1;
- struct cvmx_pip_hg_pri_qos_s cn66xx;
- struct cvmx_pip_hg_pri_qos_s cnf71xx;
};
union cvmx_pip_int_en {
@@ -1082,9 +939,6 @@
uint64_t reserved_9_63:55;
#endif
} cn30xx;
- struct cvmx_pip_int_en_cn30xx cn31xx;
- struct cvmx_pip_int_en_cn30xx cn38xx;
- struct cvmx_pip_int_en_cn30xx cn38xxp2;
struct cvmx_pip_int_en_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -1149,8 +1003,6 @@
uint64_t reserved_13_63:51;
#endif
} cn52xx;
- struct cvmx_pip_int_en_cn52xx cn52xxp1;
- struct cvmx_pip_int_en_s cn56xx;
struct cvmx_pip_int_en_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -1211,14 +1063,6 @@
uint64_t reserved_13_63:51;
#endif
} cn58xx;
- struct cvmx_pip_int_en_cn30xx cn58xxp1;
- struct cvmx_pip_int_en_s cn61xx;
- struct cvmx_pip_int_en_s cn63xx;
- struct cvmx_pip_int_en_s cn63xxp1;
- struct cvmx_pip_int_en_s cn66xx;
- struct cvmx_pip_int_en_s cn68xx;
- struct cvmx_pip_int_en_s cn68xxp1;
- struct cvmx_pip_int_en_s cnf71xx;
};
union cvmx_pip_int_reg {
@@ -1281,9 +1125,6 @@
uint64_t reserved_9_63:55;
#endif
} cn30xx;
- struct cvmx_pip_int_reg_cn30xx cn31xx;
- struct cvmx_pip_int_reg_cn30xx cn38xx;
- struct cvmx_pip_int_reg_cn30xx cn38xxp2;
struct cvmx_pip_int_reg_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -1348,8 +1189,6 @@
uint64_t reserved_13_63:51;
#endif
} cn52xx;
- struct cvmx_pip_int_reg_cn52xx cn52xxp1;
- struct cvmx_pip_int_reg_s cn56xx;
struct cvmx_pip_int_reg_cn56xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_12_63:52;
@@ -1410,14 +1249,6 @@
uint64_t reserved_13_63:51;
#endif
} cn58xx;
- struct cvmx_pip_int_reg_cn30xx cn58xxp1;
- struct cvmx_pip_int_reg_s cn61xx;
- struct cvmx_pip_int_reg_s cn63xx;
- struct cvmx_pip_int_reg_s cn63xxp1;
- struct cvmx_pip_int_reg_s cn66xx;
- struct cvmx_pip_int_reg_s cn68xx;
- struct cvmx_pip_int_reg_s cn68xxp1;
- struct cvmx_pip_int_reg_s cnf71xx;
};
union cvmx_pip_ip_offset {
@@ -1431,24 +1262,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_pip_ip_offset_s cn30xx;
- struct cvmx_pip_ip_offset_s cn31xx;
- struct cvmx_pip_ip_offset_s cn38xx;
- struct cvmx_pip_ip_offset_s cn38xxp2;
- struct cvmx_pip_ip_offset_s cn50xx;
- struct cvmx_pip_ip_offset_s cn52xx;
- struct cvmx_pip_ip_offset_s cn52xxp1;
- struct cvmx_pip_ip_offset_s cn56xx;
- struct cvmx_pip_ip_offset_s cn56xxp1;
- struct cvmx_pip_ip_offset_s cn58xx;
- struct cvmx_pip_ip_offset_s cn58xxp1;
- struct cvmx_pip_ip_offset_s cn61xx;
- struct cvmx_pip_ip_offset_s cn63xx;
- struct cvmx_pip_ip_offset_s cn63xxp1;
- struct cvmx_pip_ip_offset_s cn66xx;
- struct cvmx_pip_ip_offset_s cn68xx;
- struct cvmx_pip_ip_offset_s cn68xxp1;
- struct cvmx_pip_ip_offset_s cnf71xx;
};
union cvmx_pip_pri_tblx {
@@ -1488,8 +1301,6 @@
uint64_t diff2_padd:8;
#endif
} s;
- struct cvmx_pip_pri_tblx_s cn68xx;
- struct cvmx_pip_pri_tblx_s cn68xxp1;
};
union cvmx_pip_prt_cfgx {
@@ -1596,7 +1407,6 @@
uint64_t reserved_37_63:27;
#endif
} cn30xx;
- struct cvmx_pip_prt_cfgx_cn30xx cn31xx;
struct cvmx_pip_prt_cfgx_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_37_63:27;
@@ -1638,7 +1448,6 @@
uint64_t reserved_37_63:27;
#endif
} cn38xx;
- struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2;
struct cvmx_pip_prt_cfgx_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_53_63:11;
@@ -1759,9 +1568,6 @@
uint64_t reserved_53_63:11;
#endif
} cn52xx;
- struct cvmx_pip_prt_cfgx_cn52xx cn52xxp1;
- struct cvmx_pip_prt_cfgx_cn52xx cn56xx;
- struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1;
struct cvmx_pip_prt_cfgx_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_37_63:27;
@@ -1805,11 +1611,6 @@
uint64_t reserved_37_63:27;
#endif
} cn58xx;
- struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1;
- struct cvmx_pip_prt_cfgx_cn52xx cn61xx;
- struct cvmx_pip_prt_cfgx_cn52xx cn63xx;
- struct cvmx_pip_prt_cfgx_cn52xx cn63xxp1;
- struct cvmx_pip_prt_cfgx_cn52xx cn66xx;
struct cvmx_pip_prt_cfgx_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_55_63:9;
@@ -1875,8 +1676,6 @@
uint64_t reserved_55_63:9;
#endif
} cn68xx;
- struct cvmx_pip_prt_cfgx_cn68xx cn68xxp1;
- struct cvmx_pip_prt_cfgx_cn52xx cnf71xx;
};
union cvmx_pip_prt_cfgbx {
@@ -1938,7 +1737,6 @@
uint64_t reserved_39_63:25;
#endif
} cn66xx;
- struct cvmx_pip_prt_cfgbx_s cn68xx;
struct cvmx_pip_prt_cfgbx_cn68xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
@@ -1952,7 +1750,6 @@
uint64_t reserved_24_63:40;
#endif
} cn68xxp1;
- struct cvmx_pip_prt_cfgbx_cn61xx cnf71xx;
};
union cvmx_pip_prt_tagx {
@@ -2083,9 +1880,6 @@
uint64_t reserved_40_63:24;
#endif
} cn30xx;
- struct cvmx_pip_prt_tagx_cn30xx cn31xx;
- struct cvmx_pip_prt_tagx_cn30xx cn38xx;
- struct cvmx_pip_prt_tagx_cn30xx cn38xxp2;
struct cvmx_pip_prt_tagx_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_40_63:24;
@@ -2141,19 +1935,6 @@
uint64_t reserved_40_63:24;
#endif
} cn50xx;
- struct cvmx_pip_prt_tagx_cn50xx cn52xx;
- struct cvmx_pip_prt_tagx_cn50xx cn52xxp1;
- struct cvmx_pip_prt_tagx_cn50xx cn56xx;
- struct cvmx_pip_prt_tagx_cn50xx cn56xxp1;
- struct cvmx_pip_prt_tagx_cn30xx cn58xx;
- struct cvmx_pip_prt_tagx_cn30xx cn58xxp1;
- struct cvmx_pip_prt_tagx_cn50xx cn61xx;
- struct cvmx_pip_prt_tagx_cn50xx cn63xx;
- struct cvmx_pip_prt_tagx_cn50xx cn63xxp1;
- struct cvmx_pip_prt_tagx_cn50xx cn66xx;
- struct cvmx_pip_prt_tagx_s cn68xx;
- struct cvmx_pip_prt_tagx_s cn68xxp1;
- struct cvmx_pip_prt_tagx_cn50xx cnf71xx;
};
union cvmx_pip_qos_diffx {
@@ -2167,22 +1948,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_pip_qos_diffx_s cn30xx;
- struct cvmx_pip_qos_diffx_s cn31xx;
- struct cvmx_pip_qos_diffx_s cn38xx;
- struct cvmx_pip_qos_diffx_s cn38xxp2;
- struct cvmx_pip_qos_diffx_s cn50xx;
- struct cvmx_pip_qos_diffx_s cn52xx;
- struct cvmx_pip_qos_diffx_s cn52xxp1;
- struct cvmx_pip_qos_diffx_s cn56xx;
- struct cvmx_pip_qos_diffx_s cn56xxp1;
- struct cvmx_pip_qos_diffx_s cn58xx;
- struct cvmx_pip_qos_diffx_s cn58xxp1;
- struct cvmx_pip_qos_diffx_s cn61xx;
- struct cvmx_pip_qos_diffx_s cn63xx;
- struct cvmx_pip_qos_diffx_s cn63xxp1;
- struct cvmx_pip_qos_diffx_s cn66xx;
- struct cvmx_pip_qos_diffx_s cnf71xx;
};
union cvmx_pip_qos_vlanx {
@@ -2209,21 +1974,6 @@
uint64_t reserved_3_63:61;
#endif
} cn30xx;
- struct cvmx_pip_qos_vlanx_cn30xx cn31xx;
- struct cvmx_pip_qos_vlanx_cn30xx cn38xx;
- struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2;
- struct cvmx_pip_qos_vlanx_cn30xx cn50xx;
- struct cvmx_pip_qos_vlanx_s cn52xx;
- struct cvmx_pip_qos_vlanx_s cn52xxp1;
- struct cvmx_pip_qos_vlanx_s cn56xx;
- struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1;
- struct cvmx_pip_qos_vlanx_cn30xx cn58xx;
- struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1;
- struct cvmx_pip_qos_vlanx_s cn61xx;
- struct cvmx_pip_qos_vlanx_s cn63xx;
- struct cvmx_pip_qos_vlanx_s cn63xxp1;
- struct cvmx_pip_qos_vlanx_s cn66xx;
- struct cvmx_pip_qos_vlanx_s cnf71xx;
};
union cvmx_pip_qos_watchx {
@@ -2274,9 +2024,6 @@
uint64_t reserved_48_63:16;
#endif
} cn30xx;
- struct cvmx_pip_qos_watchx_cn30xx cn31xx;
- struct cvmx_pip_qos_watchx_cn30xx cn38xx;
- struct cvmx_pip_qos_watchx_cn30xx cn38xxp2;
struct cvmx_pip_qos_watchx_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_48_63:16;
@@ -2300,19 +2047,6 @@
uint64_t reserved_48_63:16;
#endif
} cn50xx;
- struct cvmx_pip_qos_watchx_cn50xx cn52xx;
- struct cvmx_pip_qos_watchx_cn50xx cn52xxp1;
- struct cvmx_pip_qos_watchx_cn50xx cn56xx;
- struct cvmx_pip_qos_watchx_cn50xx cn56xxp1;
- struct cvmx_pip_qos_watchx_cn30xx cn58xx;
- struct cvmx_pip_qos_watchx_cn30xx cn58xxp1;
- struct cvmx_pip_qos_watchx_cn50xx cn61xx;
- struct cvmx_pip_qos_watchx_cn50xx cn63xx;
- struct cvmx_pip_qos_watchx_cn50xx cn63xxp1;
- struct cvmx_pip_qos_watchx_cn50xx cn66xx;
- struct cvmx_pip_qos_watchx_s cn68xx;
- struct cvmx_pip_qos_watchx_s cn68xxp1;
- struct cvmx_pip_qos_watchx_cn50xx cnf71xx;
};
union cvmx_pip_raw_word {
@@ -2326,24 +2060,6 @@
uint64_t reserved_56_63:8;
#endif
} s;
- struct cvmx_pip_raw_word_s cn30xx;
- struct cvmx_pip_raw_word_s cn31xx;
- struct cvmx_pip_raw_word_s cn38xx;
- struct cvmx_pip_raw_word_s cn38xxp2;
- struct cvmx_pip_raw_word_s cn50xx;
- struct cvmx_pip_raw_word_s cn52xx;
- struct cvmx_pip_raw_word_s cn52xxp1;
- struct cvmx_pip_raw_word_s cn56xx;
- struct cvmx_pip_raw_word_s cn56xxp1;
- struct cvmx_pip_raw_word_s cn58xx;
- struct cvmx_pip_raw_word_s cn58xxp1;
- struct cvmx_pip_raw_word_s cn61xx;
- struct cvmx_pip_raw_word_s cn63xx;
- struct cvmx_pip_raw_word_s cn63xxp1;
- struct cvmx_pip_raw_word_s cn66xx;
- struct cvmx_pip_raw_word_s cn68xx;
- struct cvmx_pip_raw_word_s cn68xxp1;
- struct cvmx_pip_raw_word_s cnf71xx;
};
union cvmx_pip_sft_rst {
@@ -2357,23 +2073,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_pip_sft_rst_s cn30xx;
- struct cvmx_pip_sft_rst_s cn31xx;
- struct cvmx_pip_sft_rst_s cn38xx;
- struct cvmx_pip_sft_rst_s cn50xx;
- struct cvmx_pip_sft_rst_s cn52xx;
- struct cvmx_pip_sft_rst_s cn52xxp1;
- struct cvmx_pip_sft_rst_s cn56xx;
- struct cvmx_pip_sft_rst_s cn56xxp1;
- struct cvmx_pip_sft_rst_s cn58xx;
- struct cvmx_pip_sft_rst_s cn58xxp1;
- struct cvmx_pip_sft_rst_s cn61xx;
- struct cvmx_pip_sft_rst_s cn63xx;
- struct cvmx_pip_sft_rst_s cn63xxp1;
- struct cvmx_pip_sft_rst_s cn66xx;
- struct cvmx_pip_sft_rst_s cn68xx;
- struct cvmx_pip_sft_rst_s cn68xxp1;
- struct cvmx_pip_sft_rst_s cnf71xx;
};
union cvmx_pip_stat0_x {
@@ -2387,8 +2086,6 @@
uint64_t drp_pkts:32;
#endif
} s;
- struct cvmx_pip_stat0_x_s cn68xx;
- struct cvmx_pip_stat0_x_s cn68xxp1;
};
union cvmx_pip_stat0_prtx {
@@ -2402,22 +2099,6 @@
uint64_t drp_pkts:32;
#endif
} s;
- struct cvmx_pip_stat0_prtx_s cn30xx;
- struct cvmx_pip_stat0_prtx_s cn31xx;
- struct cvmx_pip_stat0_prtx_s cn38xx;
- struct cvmx_pip_stat0_prtx_s cn38xxp2;
- struct cvmx_pip_stat0_prtx_s cn50xx;
- struct cvmx_pip_stat0_prtx_s cn52xx;
- struct cvmx_pip_stat0_prtx_s cn52xxp1;
- struct cvmx_pip_stat0_prtx_s cn56xx;
- struct cvmx_pip_stat0_prtx_s cn56xxp1;
- struct cvmx_pip_stat0_prtx_s cn58xx;
- struct cvmx_pip_stat0_prtx_s cn58xxp1;
- struct cvmx_pip_stat0_prtx_s cn61xx;
- struct cvmx_pip_stat0_prtx_s cn63xx;
- struct cvmx_pip_stat0_prtx_s cn63xxp1;
- struct cvmx_pip_stat0_prtx_s cn66xx;
- struct cvmx_pip_stat0_prtx_s cnf71xx;
};
union cvmx_pip_stat10_x {
@@ -2431,8 +2112,6 @@
uint64_t bcast:32;
#endif
} s;
- struct cvmx_pip_stat10_x_s cn68xx;
- struct cvmx_pip_stat10_x_s cn68xxp1;
};
union cvmx_pip_stat10_prtx {
@@ -2446,15 +2125,6 @@
uint64_t bcast:32;
#endif
} s;
- struct cvmx_pip_stat10_prtx_s cn52xx;
- struct cvmx_pip_stat10_prtx_s cn52xxp1;
- struct cvmx_pip_stat10_prtx_s cn56xx;
- struct cvmx_pip_stat10_prtx_s cn56xxp1;
- struct cvmx_pip_stat10_prtx_s cn61xx;
- struct cvmx_pip_stat10_prtx_s cn63xx;
- struct cvmx_pip_stat10_prtx_s cn63xxp1;
- struct cvmx_pip_stat10_prtx_s cn66xx;
- struct cvmx_pip_stat10_prtx_s cnf71xx;
};
union cvmx_pip_stat11_x {
@@ -2468,8 +2138,6 @@
uint64_t bcast:32;
#endif
} s;
- struct cvmx_pip_stat11_x_s cn68xx;
- struct cvmx_pip_stat11_x_s cn68xxp1;
};
union cvmx_pip_stat11_prtx {
@@ -2483,15 +2151,6 @@
uint64_t bcast:32;
#endif
} s;
- struct cvmx_pip_stat11_prtx_s cn52xx;
- struct cvmx_pip_stat11_prtx_s cn52xxp1;
- struct cvmx_pip_stat11_prtx_s cn56xx;
- struct cvmx_pip_stat11_prtx_s cn56xxp1;
- struct cvmx_pip_stat11_prtx_s cn61xx;
- struct cvmx_pip_stat11_prtx_s cn63xx;
- struct cvmx_pip_stat11_prtx_s cn63xxp1;
- struct cvmx_pip_stat11_prtx_s cn66xx;
- struct cvmx_pip_stat11_prtx_s cnf71xx;
};
union cvmx_pip_stat1_x {
@@ -2505,8 +2164,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_pip_stat1_x_s cn68xx;
- struct cvmx_pip_stat1_x_s cn68xxp1;
};
union cvmx_pip_stat1_prtx {
@@ -2520,22 +2177,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_pip_stat1_prtx_s cn30xx;
- struct cvmx_pip_stat1_prtx_s cn31xx;
- struct cvmx_pip_stat1_prtx_s cn38xx;
- struct cvmx_pip_stat1_prtx_s cn38xxp2;
- struct cvmx_pip_stat1_prtx_s cn50xx;
- struct cvmx_pip_stat1_prtx_s cn52xx;
- struct cvmx_pip_stat1_prtx_s cn52xxp1;
- struct cvmx_pip_stat1_prtx_s cn56xx;
- struct cvmx_pip_stat1_prtx_s cn56xxp1;
- struct cvmx_pip_stat1_prtx_s cn58xx;
- struct cvmx_pip_stat1_prtx_s cn58xxp1;
- struct cvmx_pip_stat1_prtx_s cn61xx;
- struct cvmx_pip_stat1_prtx_s cn63xx;
- struct cvmx_pip_stat1_prtx_s cn63xxp1;
- struct cvmx_pip_stat1_prtx_s cn66xx;
- struct cvmx_pip_stat1_prtx_s cnf71xx;
};
union cvmx_pip_stat2_x {
@@ -2549,8 +2190,6 @@
uint64_t pkts:32;
#endif
} s;
- struct cvmx_pip_stat2_x_s cn68xx;
- struct cvmx_pip_stat2_x_s cn68xxp1;
};
union cvmx_pip_stat2_prtx {
@@ -2564,22 +2203,6 @@
uint64_t pkts:32;
#endif
} s;
- struct cvmx_pip_stat2_prtx_s cn30xx;
- struct cvmx_pip_stat2_prtx_s cn31xx;
- struct cvmx_pip_stat2_prtx_s cn38xx;
- struct cvmx_pip_stat2_prtx_s cn38xxp2;
- struct cvmx_pip_stat2_prtx_s cn50xx;
- struct cvmx_pip_stat2_prtx_s cn52xx;
- struct cvmx_pip_stat2_prtx_s cn52xxp1;
- struct cvmx_pip_stat2_prtx_s cn56xx;
- struct cvmx_pip_stat2_prtx_s cn56xxp1;
- struct cvmx_pip_stat2_prtx_s cn58xx;
- struct cvmx_pip_stat2_prtx_s cn58xxp1;
- struct cvmx_pip_stat2_prtx_s cn61xx;
- struct cvmx_pip_stat2_prtx_s cn63xx;
- struct cvmx_pip_stat2_prtx_s cn63xxp1;
- struct cvmx_pip_stat2_prtx_s cn66xx;
- struct cvmx_pip_stat2_prtx_s cnf71xx;
};
union cvmx_pip_stat3_x {
@@ -2593,8 +2216,6 @@
uint64_t bcst:32;
#endif
} s;
- struct cvmx_pip_stat3_x_s cn68xx;
- struct cvmx_pip_stat3_x_s cn68xxp1;
};
union cvmx_pip_stat3_prtx {
@@ -2608,22 +2229,6 @@
uint64_t bcst:32;
#endif
} s;
- struct cvmx_pip_stat3_prtx_s cn30xx;
- struct cvmx_pip_stat3_prtx_s cn31xx;
- struct cvmx_pip_stat3_prtx_s cn38xx;
- struct cvmx_pip_stat3_prtx_s cn38xxp2;
- struct cvmx_pip_stat3_prtx_s cn50xx;
- struct cvmx_pip_stat3_prtx_s cn52xx;
- struct cvmx_pip_stat3_prtx_s cn52xxp1;
- struct cvmx_pip_stat3_prtx_s cn56xx;
- struct cvmx_pip_stat3_prtx_s cn56xxp1;
- struct cvmx_pip_stat3_prtx_s cn58xx;
- struct cvmx_pip_stat3_prtx_s cn58xxp1;
- struct cvmx_pip_stat3_prtx_s cn61xx;
- struct cvmx_pip_stat3_prtx_s cn63xx;
- struct cvmx_pip_stat3_prtx_s cn63xxp1;
- struct cvmx_pip_stat3_prtx_s cn66xx;
- struct cvmx_pip_stat3_prtx_s cnf71xx;
};
union cvmx_pip_stat4_x {
@@ -2637,8 +2242,6 @@
uint64_t h65to127:32;
#endif
} s;
- struct cvmx_pip_stat4_x_s cn68xx;
- struct cvmx_pip_stat4_x_s cn68xxp1;
};
union cvmx_pip_stat4_prtx {
@@ -2652,22 +2255,6 @@
uint64_t h65to127:32;
#endif
} s;
- struct cvmx_pip_stat4_prtx_s cn30xx;
- struct cvmx_pip_stat4_prtx_s cn31xx;
- struct cvmx_pip_stat4_prtx_s cn38xx;
- struct cvmx_pip_stat4_prtx_s cn38xxp2;
- struct cvmx_pip_stat4_prtx_s cn50xx;
- struct cvmx_pip_stat4_prtx_s cn52xx;
- struct cvmx_pip_stat4_prtx_s cn52xxp1;
- struct cvmx_pip_stat4_prtx_s cn56xx;
- struct cvmx_pip_stat4_prtx_s cn56xxp1;
- struct cvmx_pip_stat4_prtx_s cn58xx;
- struct cvmx_pip_stat4_prtx_s cn58xxp1;
- struct cvmx_pip_stat4_prtx_s cn61xx;
- struct cvmx_pip_stat4_prtx_s cn63xx;
- struct cvmx_pip_stat4_prtx_s cn63xxp1;
- struct cvmx_pip_stat4_prtx_s cn66xx;
- struct cvmx_pip_stat4_prtx_s cnf71xx;
};
union cvmx_pip_stat5_x {
@@ -2681,8 +2268,6 @@
uint64_t h256to511:32;
#endif
} s;
- struct cvmx_pip_stat5_x_s cn68xx;
- struct cvmx_pip_stat5_x_s cn68xxp1;
};
union cvmx_pip_stat5_prtx {
@@ -2696,22 +2281,6 @@
uint64_t h256to511:32;
#endif
} s;
- struct cvmx_pip_stat5_prtx_s cn30xx;
- struct cvmx_pip_stat5_prtx_s cn31xx;
- struct cvmx_pip_stat5_prtx_s cn38xx;
- struct cvmx_pip_stat5_prtx_s cn38xxp2;
- struct cvmx_pip_stat5_prtx_s cn50xx;
- struct cvmx_pip_stat5_prtx_s cn52xx;
- struct cvmx_pip_stat5_prtx_s cn52xxp1;
- struct cvmx_pip_stat5_prtx_s cn56xx;
- struct cvmx_pip_stat5_prtx_s cn56xxp1;
- struct cvmx_pip_stat5_prtx_s cn58xx;
- struct cvmx_pip_stat5_prtx_s cn58xxp1;
- struct cvmx_pip_stat5_prtx_s cn61xx;
- struct cvmx_pip_stat5_prtx_s cn63xx;
- struct cvmx_pip_stat5_prtx_s cn63xxp1;
- struct cvmx_pip_stat5_prtx_s cn66xx;
- struct cvmx_pip_stat5_prtx_s cnf71xx;
};
union cvmx_pip_stat6_x {
@@ -2725,8 +2294,6 @@
uint64_t h1024to1518:32;
#endif
} s;
- struct cvmx_pip_stat6_x_s cn68xx;
- struct cvmx_pip_stat6_x_s cn68xxp1;
};
union cvmx_pip_stat6_prtx {
@@ -2740,22 +2307,6 @@
uint64_t h1024to1518:32;
#endif
} s;
- struct cvmx_pip_stat6_prtx_s cn30xx;
- struct cvmx_pip_stat6_prtx_s cn31xx;
- struct cvmx_pip_stat6_prtx_s cn38xx;
- struct cvmx_pip_stat6_prtx_s cn38xxp2;
- struct cvmx_pip_stat6_prtx_s cn50xx;
- struct cvmx_pip_stat6_prtx_s cn52xx;
- struct cvmx_pip_stat6_prtx_s cn52xxp1;
- struct cvmx_pip_stat6_prtx_s cn56xx;
- struct cvmx_pip_stat6_prtx_s cn56xxp1;
- struct cvmx_pip_stat6_prtx_s cn58xx;
- struct cvmx_pip_stat6_prtx_s cn58xxp1;
- struct cvmx_pip_stat6_prtx_s cn61xx;
- struct cvmx_pip_stat6_prtx_s cn63xx;
- struct cvmx_pip_stat6_prtx_s cn63xxp1;
- struct cvmx_pip_stat6_prtx_s cn66xx;
- struct cvmx_pip_stat6_prtx_s cnf71xx;
};
union cvmx_pip_stat7_x {
@@ -2769,8 +2320,6 @@
uint64_t fcs:32;
#endif
} s;
- struct cvmx_pip_stat7_x_s cn68xx;
- struct cvmx_pip_stat7_x_s cn68xxp1;
};
union cvmx_pip_stat7_prtx {
@@ -2784,22 +2333,6 @@
uint64_t fcs:32;
#endif
} s;
- struct cvmx_pip_stat7_prtx_s cn30xx;
- struct cvmx_pip_stat7_prtx_s cn31xx;
- struct cvmx_pip_stat7_prtx_s cn38xx;
- struct cvmx_pip_stat7_prtx_s cn38xxp2;
- struct cvmx_pip_stat7_prtx_s cn50xx;
- struct cvmx_pip_stat7_prtx_s cn52xx;
- struct cvmx_pip_stat7_prtx_s cn52xxp1;
- struct cvmx_pip_stat7_prtx_s cn56xx;
- struct cvmx_pip_stat7_prtx_s cn56xxp1;
- struct cvmx_pip_stat7_prtx_s cn58xx;
- struct cvmx_pip_stat7_prtx_s cn58xxp1;
- struct cvmx_pip_stat7_prtx_s cn61xx;
- struct cvmx_pip_stat7_prtx_s cn63xx;
- struct cvmx_pip_stat7_prtx_s cn63xxp1;
- struct cvmx_pip_stat7_prtx_s cn66xx;
- struct cvmx_pip_stat7_prtx_s cnf71xx;
};
union cvmx_pip_stat8_x {
@@ -2813,8 +2346,6 @@
uint64_t frag:32;
#endif
} s;
- struct cvmx_pip_stat8_x_s cn68xx;
- struct cvmx_pip_stat8_x_s cn68xxp1;
};
union cvmx_pip_stat8_prtx {
@@ -2828,22 +2359,6 @@
uint64_t frag:32;
#endif
} s;
- struct cvmx_pip_stat8_prtx_s cn30xx;
- struct cvmx_pip_stat8_prtx_s cn31xx;
- struct cvmx_pip_stat8_prtx_s cn38xx;
- struct cvmx_pip_stat8_prtx_s cn38xxp2;
- struct cvmx_pip_stat8_prtx_s cn50xx;
- struct cvmx_pip_stat8_prtx_s cn52xx;
- struct cvmx_pip_stat8_prtx_s cn52xxp1;
- struct cvmx_pip_stat8_prtx_s cn56xx;
- struct cvmx_pip_stat8_prtx_s cn56xxp1;
- struct cvmx_pip_stat8_prtx_s cn58xx;
- struct cvmx_pip_stat8_prtx_s cn58xxp1;
- struct cvmx_pip_stat8_prtx_s cn61xx;
- struct cvmx_pip_stat8_prtx_s cn63xx;
- struct cvmx_pip_stat8_prtx_s cn63xxp1;
- struct cvmx_pip_stat8_prtx_s cn66xx;
- struct cvmx_pip_stat8_prtx_s cnf71xx;
};
union cvmx_pip_stat9_x {
@@ -2857,8 +2372,6 @@
uint64_t jabber:32;
#endif
} s;
- struct cvmx_pip_stat9_x_s cn68xx;
- struct cvmx_pip_stat9_x_s cn68xxp1;
};
union cvmx_pip_stat9_prtx {
@@ -2872,22 +2385,6 @@
uint64_t jabber:32;
#endif
} s;
- struct cvmx_pip_stat9_prtx_s cn30xx;
- struct cvmx_pip_stat9_prtx_s cn31xx;
- struct cvmx_pip_stat9_prtx_s cn38xx;
- struct cvmx_pip_stat9_prtx_s cn38xxp2;
- struct cvmx_pip_stat9_prtx_s cn50xx;
- struct cvmx_pip_stat9_prtx_s cn52xx;
- struct cvmx_pip_stat9_prtx_s cn52xxp1;
- struct cvmx_pip_stat9_prtx_s cn56xx;
- struct cvmx_pip_stat9_prtx_s cn56xxp1;
- struct cvmx_pip_stat9_prtx_s cn58xx;
- struct cvmx_pip_stat9_prtx_s cn58xxp1;
- struct cvmx_pip_stat9_prtx_s cn61xx;
- struct cvmx_pip_stat9_prtx_s cn63xx;
- struct cvmx_pip_stat9_prtx_s cn63xxp1;
- struct cvmx_pip_stat9_prtx_s cn66xx;
- struct cvmx_pip_stat9_prtx_s cnf71xx;
};
union cvmx_pip_stat_ctl {
@@ -2914,23 +2411,6 @@
uint64_t reserved_1_63:63;
#endif
} cn30xx;
- struct cvmx_pip_stat_ctl_cn30xx cn31xx;
- struct cvmx_pip_stat_ctl_cn30xx cn38xx;
- struct cvmx_pip_stat_ctl_cn30xx cn38xxp2;
- struct cvmx_pip_stat_ctl_cn30xx cn50xx;
- struct cvmx_pip_stat_ctl_cn30xx cn52xx;
- struct cvmx_pip_stat_ctl_cn30xx cn52xxp1;
- struct cvmx_pip_stat_ctl_cn30xx cn56xx;
- struct cvmx_pip_stat_ctl_cn30xx cn56xxp1;
- struct cvmx_pip_stat_ctl_cn30xx cn58xx;
- struct cvmx_pip_stat_ctl_cn30xx cn58xxp1;
- struct cvmx_pip_stat_ctl_cn30xx cn61xx;
- struct cvmx_pip_stat_ctl_cn30xx cn63xx;
- struct cvmx_pip_stat_ctl_cn30xx cn63xxp1;
- struct cvmx_pip_stat_ctl_cn30xx cn66xx;
- struct cvmx_pip_stat_ctl_s cn68xx;
- struct cvmx_pip_stat_ctl_s cn68xxp1;
- struct cvmx_pip_stat_ctl_cn30xx cnf71xx;
};
union cvmx_pip_stat_inb_errsx {
@@ -2944,22 +2424,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pip_stat_inb_errsx_s cn30xx;
- struct cvmx_pip_stat_inb_errsx_s cn31xx;
- struct cvmx_pip_stat_inb_errsx_s cn38xx;
- struct cvmx_pip_stat_inb_errsx_s cn38xxp2;
- struct cvmx_pip_stat_inb_errsx_s cn50xx;
- struct cvmx_pip_stat_inb_errsx_s cn52xx;
- struct cvmx_pip_stat_inb_errsx_s cn52xxp1;
- struct cvmx_pip_stat_inb_errsx_s cn56xx;
- struct cvmx_pip_stat_inb_errsx_s cn56xxp1;
- struct cvmx_pip_stat_inb_errsx_s cn58xx;
- struct cvmx_pip_stat_inb_errsx_s cn58xxp1;
- struct cvmx_pip_stat_inb_errsx_s cn61xx;
- struct cvmx_pip_stat_inb_errsx_s cn63xx;
- struct cvmx_pip_stat_inb_errsx_s cn63xxp1;
- struct cvmx_pip_stat_inb_errsx_s cn66xx;
- struct cvmx_pip_stat_inb_errsx_s cnf71xx;
};
union cvmx_pip_stat_inb_errs_pkndx {
@@ -2973,8 +2437,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pip_stat_inb_errs_pkndx_s cn68xx;
- struct cvmx_pip_stat_inb_errs_pkndx_s cn68xxp1;
};
union cvmx_pip_stat_inb_octsx {
@@ -2988,22 +2450,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_pip_stat_inb_octsx_s cn30xx;
- struct cvmx_pip_stat_inb_octsx_s cn31xx;
- struct cvmx_pip_stat_inb_octsx_s cn38xx;
- struct cvmx_pip_stat_inb_octsx_s cn38xxp2;
- struct cvmx_pip_stat_inb_octsx_s cn50xx;
- struct cvmx_pip_stat_inb_octsx_s cn52xx;
- struct cvmx_pip_stat_inb_octsx_s cn52xxp1;
- struct cvmx_pip_stat_inb_octsx_s cn56xx;
- struct cvmx_pip_stat_inb_octsx_s cn56xxp1;
- struct cvmx_pip_stat_inb_octsx_s cn58xx;
- struct cvmx_pip_stat_inb_octsx_s cn58xxp1;
- struct cvmx_pip_stat_inb_octsx_s cn61xx;
- struct cvmx_pip_stat_inb_octsx_s cn63xx;
- struct cvmx_pip_stat_inb_octsx_s cn63xxp1;
- struct cvmx_pip_stat_inb_octsx_s cn66xx;
- struct cvmx_pip_stat_inb_octsx_s cnf71xx;
};
union cvmx_pip_stat_inb_octs_pkndx {
@@ -3017,8 +2463,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_pip_stat_inb_octs_pkndx_s cn68xx;
- struct cvmx_pip_stat_inb_octs_pkndx_s cn68xxp1;
};
union cvmx_pip_stat_inb_pktsx {
@@ -3032,22 +2476,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pip_stat_inb_pktsx_s cn30xx;
- struct cvmx_pip_stat_inb_pktsx_s cn31xx;
- struct cvmx_pip_stat_inb_pktsx_s cn38xx;
- struct cvmx_pip_stat_inb_pktsx_s cn38xxp2;
- struct cvmx_pip_stat_inb_pktsx_s cn50xx;
- struct cvmx_pip_stat_inb_pktsx_s cn52xx;
- struct cvmx_pip_stat_inb_pktsx_s cn52xxp1;
- struct cvmx_pip_stat_inb_pktsx_s cn56xx;
- struct cvmx_pip_stat_inb_pktsx_s cn56xxp1;
- struct cvmx_pip_stat_inb_pktsx_s cn58xx;
- struct cvmx_pip_stat_inb_pktsx_s cn58xxp1;
- struct cvmx_pip_stat_inb_pktsx_s cn61xx;
- struct cvmx_pip_stat_inb_pktsx_s cn63xx;
- struct cvmx_pip_stat_inb_pktsx_s cn63xxp1;
- struct cvmx_pip_stat_inb_pktsx_s cn66xx;
- struct cvmx_pip_stat_inb_pktsx_s cnf71xx;
};
union cvmx_pip_stat_inb_pkts_pkndx {
@@ -3061,8 +2489,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xx;
- struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xxp1;
};
union cvmx_pip_sub_pkind_fcsx {
@@ -3074,8 +2500,6 @@
uint64_t port_bit:64;
#endif
} s;
- struct cvmx_pip_sub_pkind_fcsx_s cn68xx;
- struct cvmx_pip_sub_pkind_fcsx_s cn68xxp1;
};
union cvmx_pip_tag_incx {
@@ -3089,24 +2513,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_pip_tag_incx_s cn30xx;
- struct cvmx_pip_tag_incx_s cn31xx;
- struct cvmx_pip_tag_incx_s cn38xx;
- struct cvmx_pip_tag_incx_s cn38xxp2;
- struct cvmx_pip_tag_incx_s cn50xx;
- struct cvmx_pip_tag_incx_s cn52xx;
- struct cvmx_pip_tag_incx_s cn52xxp1;
- struct cvmx_pip_tag_incx_s cn56xx;
- struct cvmx_pip_tag_incx_s cn56xxp1;
- struct cvmx_pip_tag_incx_s cn58xx;
- struct cvmx_pip_tag_incx_s cn58xxp1;
- struct cvmx_pip_tag_incx_s cn61xx;
- struct cvmx_pip_tag_incx_s cn63xx;
- struct cvmx_pip_tag_incx_s cn63xxp1;
- struct cvmx_pip_tag_incx_s cn66xx;
- struct cvmx_pip_tag_incx_s cn68xx;
- struct cvmx_pip_tag_incx_s cn68xxp1;
- struct cvmx_pip_tag_incx_s cnf71xx;
};
union cvmx_pip_tag_mask {
@@ -3120,24 +2526,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pip_tag_mask_s cn30xx;
- struct cvmx_pip_tag_mask_s cn31xx;
- struct cvmx_pip_tag_mask_s cn38xx;
- struct cvmx_pip_tag_mask_s cn38xxp2;
- struct cvmx_pip_tag_mask_s cn50xx;
- struct cvmx_pip_tag_mask_s cn52xx;
- struct cvmx_pip_tag_mask_s cn52xxp1;
- struct cvmx_pip_tag_mask_s cn56xx;
- struct cvmx_pip_tag_mask_s cn56xxp1;
- struct cvmx_pip_tag_mask_s cn58xx;
- struct cvmx_pip_tag_mask_s cn58xxp1;
- struct cvmx_pip_tag_mask_s cn61xx;
- struct cvmx_pip_tag_mask_s cn63xx;
- struct cvmx_pip_tag_mask_s cn63xxp1;
- struct cvmx_pip_tag_mask_s cn66xx;
- struct cvmx_pip_tag_mask_s cn68xx;
- struct cvmx_pip_tag_mask_s cn68xxp1;
- struct cvmx_pip_tag_mask_s cnf71xx;
};
union cvmx_pip_tag_secret {
@@ -3153,24 +2541,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pip_tag_secret_s cn30xx;
- struct cvmx_pip_tag_secret_s cn31xx;
- struct cvmx_pip_tag_secret_s cn38xx;
- struct cvmx_pip_tag_secret_s cn38xxp2;
- struct cvmx_pip_tag_secret_s cn50xx;
- struct cvmx_pip_tag_secret_s cn52xx;
- struct cvmx_pip_tag_secret_s cn52xxp1;
- struct cvmx_pip_tag_secret_s cn56xx;
- struct cvmx_pip_tag_secret_s cn56xxp1;
- struct cvmx_pip_tag_secret_s cn58xx;
- struct cvmx_pip_tag_secret_s cn58xxp1;
- struct cvmx_pip_tag_secret_s cn61xx;
- struct cvmx_pip_tag_secret_s cn63xx;
- struct cvmx_pip_tag_secret_s cn63xxp1;
- struct cvmx_pip_tag_secret_s cn66xx;
- struct cvmx_pip_tag_secret_s cn68xx;
- struct cvmx_pip_tag_secret_s cn68xxp1;
- struct cvmx_pip_tag_secret_s cnf71xx;
};
union cvmx_pip_todo_entry {
@@ -3186,24 +2556,6 @@
uint64_t val:1;
#endif
} s;
- struct cvmx_pip_todo_entry_s cn30xx;
- struct cvmx_pip_todo_entry_s cn31xx;
- struct cvmx_pip_todo_entry_s cn38xx;
- struct cvmx_pip_todo_entry_s cn38xxp2;
- struct cvmx_pip_todo_entry_s cn50xx;
- struct cvmx_pip_todo_entry_s cn52xx;
- struct cvmx_pip_todo_entry_s cn52xxp1;
- struct cvmx_pip_todo_entry_s cn56xx;
- struct cvmx_pip_todo_entry_s cn56xxp1;
- struct cvmx_pip_todo_entry_s cn58xx;
- struct cvmx_pip_todo_entry_s cn58xxp1;
- struct cvmx_pip_todo_entry_s cn61xx;
- struct cvmx_pip_todo_entry_s cn63xx;
- struct cvmx_pip_todo_entry_s cn63xxp1;
- struct cvmx_pip_todo_entry_s cn66xx;
- struct cvmx_pip_todo_entry_s cn68xx;
- struct cvmx_pip_todo_entry_s cn68xxp1;
- struct cvmx_pip_todo_entry_s cnf71xx;
};
union cvmx_pip_vlan_etypesx {
@@ -3221,10 +2573,6 @@
uint64_t type3:16;
#endif
} s;
- struct cvmx_pip_vlan_etypesx_s cn61xx;
- struct cvmx_pip_vlan_etypesx_s cn66xx;
- struct cvmx_pip_vlan_etypesx_s cn68xx;
- struct cvmx_pip_vlan_etypesx_s cnf71xx;
};
union cvmx_pip_xstat0_prtx {
@@ -3238,9 +2586,6 @@
uint64_t drp_pkts:32;
#endif
} s;
- struct cvmx_pip_xstat0_prtx_s cn63xx;
- struct cvmx_pip_xstat0_prtx_s cn63xxp1;
- struct cvmx_pip_xstat0_prtx_s cn66xx;
};
union cvmx_pip_xstat10_prtx {
@@ -3254,9 +2599,6 @@
uint64_t bcast:32;
#endif
} s;
- struct cvmx_pip_xstat10_prtx_s cn63xx;
- struct cvmx_pip_xstat10_prtx_s cn63xxp1;
- struct cvmx_pip_xstat10_prtx_s cn66xx;
};
union cvmx_pip_xstat11_prtx {
@@ -3270,9 +2612,6 @@
uint64_t bcast:32;
#endif
} s;
- struct cvmx_pip_xstat11_prtx_s cn63xx;
- struct cvmx_pip_xstat11_prtx_s cn63xxp1;
- struct cvmx_pip_xstat11_prtx_s cn66xx;
};
union cvmx_pip_xstat1_prtx {
@@ -3286,9 +2625,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_pip_xstat1_prtx_s cn63xx;
- struct cvmx_pip_xstat1_prtx_s cn63xxp1;
- struct cvmx_pip_xstat1_prtx_s cn66xx;
};
union cvmx_pip_xstat2_prtx {
@@ -3302,9 +2638,6 @@
uint64_t pkts:32;
#endif
} s;
- struct cvmx_pip_xstat2_prtx_s cn63xx;
- struct cvmx_pip_xstat2_prtx_s cn63xxp1;
- struct cvmx_pip_xstat2_prtx_s cn66xx;
};
union cvmx_pip_xstat3_prtx {
@@ -3318,9 +2651,6 @@
uint64_t bcst:32;
#endif
} s;
- struct cvmx_pip_xstat3_prtx_s cn63xx;
- struct cvmx_pip_xstat3_prtx_s cn63xxp1;
- struct cvmx_pip_xstat3_prtx_s cn66xx;
};
union cvmx_pip_xstat4_prtx {
@@ -3334,9 +2664,6 @@
uint64_t h65to127:32;
#endif
} s;
- struct cvmx_pip_xstat4_prtx_s cn63xx;
- struct cvmx_pip_xstat4_prtx_s cn63xxp1;
- struct cvmx_pip_xstat4_prtx_s cn66xx;
};
union cvmx_pip_xstat5_prtx {
@@ -3350,9 +2677,6 @@
uint64_t h256to511:32;
#endif
} s;
- struct cvmx_pip_xstat5_prtx_s cn63xx;
- struct cvmx_pip_xstat5_prtx_s cn63xxp1;
- struct cvmx_pip_xstat5_prtx_s cn66xx;
};
union cvmx_pip_xstat6_prtx {
@@ -3366,9 +2690,6 @@
uint64_t h1024to1518:32;
#endif
} s;
- struct cvmx_pip_xstat6_prtx_s cn63xx;
- struct cvmx_pip_xstat6_prtx_s cn63xxp1;
- struct cvmx_pip_xstat6_prtx_s cn66xx;
};
union cvmx_pip_xstat7_prtx {
@@ -3382,9 +2703,6 @@
uint64_t fcs:32;
#endif
} s;
- struct cvmx_pip_xstat7_prtx_s cn63xx;
- struct cvmx_pip_xstat7_prtx_s cn63xxp1;
- struct cvmx_pip_xstat7_prtx_s cn66xx;
};
union cvmx_pip_xstat8_prtx {
@@ -3398,9 +2716,6 @@
uint64_t frag:32;
#endif
} s;
- struct cvmx_pip_xstat8_prtx_s cn63xx;
- struct cvmx_pip_xstat8_prtx_s cn63xxp1;
- struct cvmx_pip_xstat8_prtx_s cn66xx;
};
union cvmx_pip_xstat9_prtx {
@@ -3414,9 +2729,6 @@
uint64_t jabber:32;
#endif
} s;
- struct cvmx_pip_xstat9_prtx_s cn63xx;
- struct cvmx_pip_xstat9_prtx_s cn63xxp1;
- struct cvmx_pip_xstat9_prtx_s cn66xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
index 87c3b97..7e14c0d 100644
--- a/arch/mips/include/asm/octeon/cvmx-pko-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
@@ -97,24 +97,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pko_mem_count0_s cn30xx;
- struct cvmx_pko_mem_count0_s cn31xx;
- struct cvmx_pko_mem_count0_s cn38xx;
- struct cvmx_pko_mem_count0_s cn38xxp2;
- struct cvmx_pko_mem_count0_s cn50xx;
- struct cvmx_pko_mem_count0_s cn52xx;
- struct cvmx_pko_mem_count0_s cn52xxp1;
- struct cvmx_pko_mem_count0_s cn56xx;
- struct cvmx_pko_mem_count0_s cn56xxp1;
- struct cvmx_pko_mem_count0_s cn58xx;
- struct cvmx_pko_mem_count0_s cn58xxp1;
- struct cvmx_pko_mem_count0_s cn61xx;
- struct cvmx_pko_mem_count0_s cn63xx;
- struct cvmx_pko_mem_count0_s cn63xxp1;
- struct cvmx_pko_mem_count0_s cn66xx;
- struct cvmx_pko_mem_count0_s cn68xx;
- struct cvmx_pko_mem_count0_s cn68xxp1;
- struct cvmx_pko_mem_count0_s cnf71xx;
};
union cvmx_pko_mem_count1 {
@@ -128,24 +110,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_pko_mem_count1_s cn30xx;
- struct cvmx_pko_mem_count1_s cn31xx;
- struct cvmx_pko_mem_count1_s cn38xx;
- struct cvmx_pko_mem_count1_s cn38xxp2;
- struct cvmx_pko_mem_count1_s cn50xx;
- struct cvmx_pko_mem_count1_s cn52xx;
- struct cvmx_pko_mem_count1_s cn52xxp1;
- struct cvmx_pko_mem_count1_s cn56xx;
- struct cvmx_pko_mem_count1_s cn56xxp1;
- struct cvmx_pko_mem_count1_s cn58xx;
- struct cvmx_pko_mem_count1_s cn58xxp1;
- struct cvmx_pko_mem_count1_s cn61xx;
- struct cvmx_pko_mem_count1_s cn63xx;
- struct cvmx_pko_mem_count1_s cn63xxp1;
- struct cvmx_pko_mem_count1_s cn66xx;
- struct cvmx_pko_mem_count1_s cn68xx;
- struct cvmx_pko_mem_count1_s cn68xxp1;
- struct cvmx_pko_mem_count1_s cnf71xx;
};
union cvmx_pko_mem_debug0 {
@@ -163,24 +127,6 @@
uint64_t fau:28;
#endif
} s;
- struct cvmx_pko_mem_debug0_s cn30xx;
- struct cvmx_pko_mem_debug0_s cn31xx;
- struct cvmx_pko_mem_debug0_s cn38xx;
- struct cvmx_pko_mem_debug0_s cn38xxp2;
- struct cvmx_pko_mem_debug0_s cn50xx;
- struct cvmx_pko_mem_debug0_s cn52xx;
- struct cvmx_pko_mem_debug0_s cn52xxp1;
- struct cvmx_pko_mem_debug0_s cn56xx;
- struct cvmx_pko_mem_debug0_s cn56xxp1;
- struct cvmx_pko_mem_debug0_s cn58xx;
- struct cvmx_pko_mem_debug0_s cn58xxp1;
- struct cvmx_pko_mem_debug0_s cn61xx;
- struct cvmx_pko_mem_debug0_s cn63xx;
- struct cvmx_pko_mem_debug0_s cn63xxp1;
- struct cvmx_pko_mem_debug0_s cn66xx;
- struct cvmx_pko_mem_debug0_s cn68xx;
- struct cvmx_pko_mem_debug0_s cn68xxp1;
- struct cvmx_pko_mem_debug0_s cnf71xx;
};
union cvmx_pko_mem_debug1 {
@@ -200,24 +146,6 @@
uint64_t i:1;
#endif
} s;
- struct cvmx_pko_mem_debug1_s cn30xx;
- struct cvmx_pko_mem_debug1_s cn31xx;
- struct cvmx_pko_mem_debug1_s cn38xx;
- struct cvmx_pko_mem_debug1_s cn38xxp2;
- struct cvmx_pko_mem_debug1_s cn50xx;
- struct cvmx_pko_mem_debug1_s cn52xx;
- struct cvmx_pko_mem_debug1_s cn52xxp1;
- struct cvmx_pko_mem_debug1_s cn56xx;
- struct cvmx_pko_mem_debug1_s cn56xxp1;
- struct cvmx_pko_mem_debug1_s cn58xx;
- struct cvmx_pko_mem_debug1_s cn58xxp1;
- struct cvmx_pko_mem_debug1_s cn61xx;
- struct cvmx_pko_mem_debug1_s cn63xx;
- struct cvmx_pko_mem_debug1_s cn63xxp1;
- struct cvmx_pko_mem_debug1_s cn66xx;
- struct cvmx_pko_mem_debug1_s cn68xx;
- struct cvmx_pko_mem_debug1_s cn68xxp1;
- struct cvmx_pko_mem_debug1_s cnf71xx;
};
union cvmx_pko_mem_debug10 {
@@ -242,9 +170,6 @@
uint64_t fau:28;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug10_cn30xx cn31xx;
- struct cvmx_pko_mem_debug10_cn30xx cn38xx;
- struct cvmx_pko_mem_debug10_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug10_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_49_63:15;
@@ -258,19 +183,6 @@
uint64_t reserved_49_63:15;
#endif
} cn50xx;
- struct cvmx_pko_mem_debug10_cn50xx cn52xx;
- struct cvmx_pko_mem_debug10_cn50xx cn52xxp1;
- struct cvmx_pko_mem_debug10_cn50xx cn56xx;
- struct cvmx_pko_mem_debug10_cn50xx cn56xxp1;
- struct cvmx_pko_mem_debug10_cn50xx cn58xx;
- struct cvmx_pko_mem_debug10_cn50xx cn58xxp1;
- struct cvmx_pko_mem_debug10_cn50xx cn61xx;
- struct cvmx_pko_mem_debug10_cn50xx cn63xx;
- struct cvmx_pko_mem_debug10_cn50xx cn63xxp1;
- struct cvmx_pko_mem_debug10_cn50xx cn66xx;
- struct cvmx_pko_mem_debug10_cn50xx cn68xx;
- struct cvmx_pko_mem_debug10_cn50xx cn68xxp1;
- struct cvmx_pko_mem_debug10_cn50xx cnf71xx;
};
union cvmx_pko_mem_debug11 {
@@ -305,9 +217,6 @@
uint64_t i:1;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug11_cn30xx cn31xx;
- struct cvmx_pko_mem_debug11_cn30xx cn38xx;
- struct cvmx_pko_mem_debug11_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug11_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_23_63:41;
@@ -329,19 +238,6 @@
uint64_t reserved_23_63:41;
#endif
} cn50xx;
- struct cvmx_pko_mem_debug11_cn50xx cn52xx;
- struct cvmx_pko_mem_debug11_cn50xx cn52xxp1;
- struct cvmx_pko_mem_debug11_cn50xx cn56xx;
- struct cvmx_pko_mem_debug11_cn50xx cn56xxp1;
- struct cvmx_pko_mem_debug11_cn50xx cn58xx;
- struct cvmx_pko_mem_debug11_cn50xx cn58xxp1;
- struct cvmx_pko_mem_debug11_cn50xx cn61xx;
- struct cvmx_pko_mem_debug11_cn50xx cn63xx;
- struct cvmx_pko_mem_debug11_cn50xx cn63xxp1;
- struct cvmx_pko_mem_debug11_cn50xx cn66xx;
- struct cvmx_pko_mem_debug11_cn50xx cn68xx;
- struct cvmx_pko_mem_debug11_cn50xx cn68xxp1;
- struct cvmx_pko_mem_debug11_cn50xx cnf71xx;
};
union cvmx_pko_mem_debug12 {
@@ -360,9 +256,6 @@
uint64_t data:64;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug12_cn30xx cn31xx;
- struct cvmx_pko_mem_debug12_cn30xx cn38xx;
- struct cvmx_pko_mem_debug12_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug12_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t fau:28;
@@ -376,16 +269,6 @@
uint64_t fau:28;
#endif
} cn50xx;
- struct cvmx_pko_mem_debug12_cn50xx cn52xx;
- struct cvmx_pko_mem_debug12_cn50xx cn52xxp1;
- struct cvmx_pko_mem_debug12_cn50xx cn56xx;
- struct cvmx_pko_mem_debug12_cn50xx cn56xxp1;
- struct cvmx_pko_mem_debug12_cn50xx cn58xx;
- struct cvmx_pko_mem_debug12_cn50xx cn58xxp1;
- struct cvmx_pko_mem_debug12_cn50xx cn61xx;
- struct cvmx_pko_mem_debug12_cn50xx cn63xx;
- struct cvmx_pko_mem_debug12_cn50xx cn63xxp1;
- struct cvmx_pko_mem_debug12_cn50xx cn66xx;
struct cvmx_pko_mem_debug12_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t state:64;
@@ -393,8 +276,6 @@
uint64_t state:64;
#endif
} cn68xx;
- struct cvmx_pko_mem_debug12_cn68xx cn68xxp1;
- struct cvmx_pko_mem_debug12_cn50xx cnf71xx;
};
union cvmx_pko_mem_debug13 {
@@ -419,9 +300,6 @@
uint64_t reserved_51_63:13;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug13_cn30xx cn31xx;
- struct cvmx_pko_mem_debug13_cn30xx cn38xx;
- struct cvmx_pko_mem_debug13_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug13_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t i:1;
@@ -437,16 +315,6 @@
uint64_t i:1;
#endif
} cn50xx;
- struct cvmx_pko_mem_debug13_cn50xx cn52xx;
- struct cvmx_pko_mem_debug13_cn50xx cn52xxp1;
- struct cvmx_pko_mem_debug13_cn50xx cn56xx;
- struct cvmx_pko_mem_debug13_cn50xx cn56xxp1;
- struct cvmx_pko_mem_debug13_cn50xx cn58xx;
- struct cvmx_pko_mem_debug13_cn50xx cn58xxp1;
- struct cvmx_pko_mem_debug13_cn50xx cn61xx;
- struct cvmx_pko_mem_debug13_cn50xx cn63xx;
- struct cvmx_pko_mem_debug13_cn50xx cn63xxp1;
- struct cvmx_pko_mem_debug13_cn50xx cn66xx;
struct cvmx_pko_mem_debug13_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t state:64;
@@ -454,8 +322,6 @@
uint64_t state:64;
#endif
} cn68xx;
- struct cvmx_pko_mem_debug13_cn68xx cn68xxp1;
- struct cvmx_pko_mem_debug13_cn50xx cnf71xx;
};
union cvmx_pko_mem_debug14 {
@@ -476,9 +342,6 @@
uint64_t reserved_17_63:47;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug14_cn30xx cn31xx;
- struct cvmx_pko_mem_debug14_cn30xx cn38xx;
- struct cvmx_pko_mem_debug14_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug14_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t data:64;
@@ -486,14 +349,6 @@
uint64_t data:64;
#endif
} cn52xx;
- struct cvmx_pko_mem_debug14_cn52xx cn52xxp1;
- struct cvmx_pko_mem_debug14_cn52xx cn56xx;
- struct cvmx_pko_mem_debug14_cn52xx cn56xxp1;
- struct cvmx_pko_mem_debug14_cn52xx cn61xx;
- struct cvmx_pko_mem_debug14_cn52xx cn63xx;
- struct cvmx_pko_mem_debug14_cn52xx cn63xxp1;
- struct cvmx_pko_mem_debug14_cn52xx cn66xx;
- struct cvmx_pko_mem_debug14_cn52xx cnf71xx;
};
union cvmx_pko_mem_debug2 {
@@ -513,24 +368,6 @@
uint64_t i:1;
#endif
} s;
- struct cvmx_pko_mem_debug2_s cn30xx;
- struct cvmx_pko_mem_debug2_s cn31xx;
- struct cvmx_pko_mem_debug2_s cn38xx;
- struct cvmx_pko_mem_debug2_s cn38xxp2;
- struct cvmx_pko_mem_debug2_s cn50xx;
- struct cvmx_pko_mem_debug2_s cn52xx;
- struct cvmx_pko_mem_debug2_s cn52xxp1;
- struct cvmx_pko_mem_debug2_s cn56xx;
- struct cvmx_pko_mem_debug2_s cn56xxp1;
- struct cvmx_pko_mem_debug2_s cn58xx;
- struct cvmx_pko_mem_debug2_s cn58xxp1;
- struct cvmx_pko_mem_debug2_s cn61xx;
- struct cvmx_pko_mem_debug2_s cn63xx;
- struct cvmx_pko_mem_debug2_s cn63xxp1;
- struct cvmx_pko_mem_debug2_s cn66xx;
- struct cvmx_pko_mem_debug2_s cn68xx;
- struct cvmx_pko_mem_debug2_s cn68xxp1;
- struct cvmx_pko_mem_debug2_s cnf71xx;
};
union cvmx_pko_mem_debug3 {
@@ -557,9 +394,6 @@
uint64_t i:1;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug3_cn30xx cn31xx;
- struct cvmx_pko_mem_debug3_cn30xx cn38xx;
- struct cvmx_pko_mem_debug3_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug3_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t data:64;
@@ -567,19 +401,6 @@
uint64_t data:64;
#endif
} cn50xx;
- struct cvmx_pko_mem_debug3_cn50xx cn52xx;
- struct cvmx_pko_mem_debug3_cn50xx cn52xxp1;
- struct cvmx_pko_mem_debug3_cn50xx cn56xx;
- struct cvmx_pko_mem_debug3_cn50xx cn56xxp1;
- struct cvmx_pko_mem_debug3_cn50xx cn58xx;
- struct cvmx_pko_mem_debug3_cn50xx cn58xxp1;
- struct cvmx_pko_mem_debug3_cn50xx cn61xx;
- struct cvmx_pko_mem_debug3_cn50xx cn63xx;
- struct cvmx_pko_mem_debug3_cn50xx cn63xxp1;
- struct cvmx_pko_mem_debug3_cn50xx cn66xx;
- struct cvmx_pko_mem_debug3_cn50xx cn68xx;
- struct cvmx_pko_mem_debug3_cn50xx cn68xxp1;
- struct cvmx_pko_mem_debug3_cn50xx cnf71xx;
};
union cvmx_pko_mem_debug4 {
@@ -598,9 +419,6 @@
uint64_t data:64;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug4_cn30xx cn31xx;
- struct cvmx_pko_mem_debug4_cn30xx cn38xx;
- struct cvmx_pko_mem_debug4_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug4_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t cmnd_segs:3;
@@ -673,18 +491,6 @@
uint64_t curr_siz:8;
#endif
} cn52xx;
- struct cvmx_pko_mem_debug4_cn52xx cn52xxp1;
- struct cvmx_pko_mem_debug4_cn52xx cn56xx;
- struct cvmx_pko_mem_debug4_cn52xx cn56xxp1;
- struct cvmx_pko_mem_debug4_cn50xx cn58xx;
- struct cvmx_pko_mem_debug4_cn50xx cn58xxp1;
- struct cvmx_pko_mem_debug4_cn52xx cn61xx;
- struct cvmx_pko_mem_debug4_cn52xx cn63xx;
- struct cvmx_pko_mem_debug4_cn52xx cn63xxp1;
- struct cvmx_pko_mem_debug4_cn52xx cn66xx;
- struct cvmx_pko_mem_debug4_cn52xx cn68xx;
- struct cvmx_pko_mem_debug4_cn52xx cn68xxp1;
- struct cvmx_pko_mem_debug4_cn52xx cnf71xx;
};
union cvmx_pko_mem_debug5 {
@@ -739,9 +545,6 @@
uint64_t dwri_mod:1;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug5_cn30xx cn31xx;
- struct cvmx_pko_mem_debug5_cn30xx cn38xx;
- struct cvmx_pko_mem_debug5_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug5_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t curr_ptr:29;
@@ -768,11 +571,6 @@
uint64_t reserved_54_63:10;
#endif
} cn52xx;
- struct cvmx_pko_mem_debug5_cn52xx cn52xxp1;
- struct cvmx_pko_mem_debug5_cn52xx cn56xx;
- struct cvmx_pko_mem_debug5_cn52xx cn56xxp1;
- struct cvmx_pko_mem_debug5_cn50xx cn58xx;
- struct cvmx_pko_mem_debug5_cn50xx cn58xxp1;
struct cvmx_pko_mem_debug5_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63:8;
@@ -790,9 +588,6 @@
uint64_t reserved_56_63:8;
#endif
} cn61xx;
- struct cvmx_pko_mem_debug5_cn61xx cn63xx;
- struct cvmx_pko_mem_debug5_cn61xx cn63xxp1;
- struct cvmx_pko_mem_debug5_cn61xx cn66xx;
struct cvmx_pko_mem_debug5_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_57_63:7;
@@ -812,8 +607,6 @@
uint64_t reserved_57_63:7;
#endif
} cn68xx;
- struct cvmx_pko_mem_debug5_cn68xx cn68xxp1;
- struct cvmx_pko_mem_debug5_cn61xx cnf71xx;
};
union cvmx_pko_mem_debug6 {
@@ -866,9 +659,6 @@
uint64_t reserved_11_63:53;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug6_cn30xx cn31xx;
- struct cvmx_pko_mem_debug6_cn30xx cn38xx;
- struct cvmx_pko_mem_debug6_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug6_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
@@ -909,18 +699,6 @@
uint64_t reserved_37_63:27;
#endif
} cn52xx;
- struct cvmx_pko_mem_debug6_cn52xx cn52xxp1;
- struct cvmx_pko_mem_debug6_cn52xx cn56xx;
- struct cvmx_pko_mem_debug6_cn52xx cn56xxp1;
- struct cvmx_pko_mem_debug6_cn50xx cn58xx;
- struct cvmx_pko_mem_debug6_cn50xx cn58xxp1;
- struct cvmx_pko_mem_debug6_cn52xx cn61xx;
- struct cvmx_pko_mem_debug6_cn52xx cn63xx;
- struct cvmx_pko_mem_debug6_cn52xx cn63xxp1;
- struct cvmx_pko_mem_debug6_cn52xx cn66xx;
- struct cvmx_pko_mem_debug6_cn52xx cn68xx;
- struct cvmx_pko_mem_debug6_cn52xx cn68xxp1;
- struct cvmx_pko_mem_debug6_cn52xx cnf71xx;
};
union cvmx_pko_mem_debug7 {
@@ -945,9 +723,6 @@
uint64_t reserved_58_63:6;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug7_cn30xx cn31xx;
- struct cvmx_pko_mem_debug7_cn30xx cn38xx;
- struct cvmx_pko_mem_debug7_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug7_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t qos:5;
@@ -965,16 +740,6 @@
uint64_t qos:5;
#endif
} cn50xx;
- struct cvmx_pko_mem_debug7_cn50xx cn52xx;
- struct cvmx_pko_mem_debug7_cn50xx cn52xxp1;
- struct cvmx_pko_mem_debug7_cn50xx cn56xx;
- struct cvmx_pko_mem_debug7_cn50xx cn56xxp1;
- struct cvmx_pko_mem_debug7_cn50xx cn58xx;
- struct cvmx_pko_mem_debug7_cn50xx cn58xxp1;
- struct cvmx_pko_mem_debug7_cn50xx cn61xx;
- struct cvmx_pko_mem_debug7_cn50xx cn63xx;
- struct cvmx_pko_mem_debug7_cn50xx cn63xxp1;
- struct cvmx_pko_mem_debug7_cn50xx cn66xx;
struct cvmx_pko_mem_debug7_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t qos:3;
@@ -992,8 +757,6 @@
uint64_t qos:3;
#endif
} cn68xx;
- struct cvmx_pko_mem_debug7_cn68xx cn68xxp1;
- struct cvmx_pko_mem_debug7_cn50xx cnf71xx;
};
union cvmx_pko_mem_debug8 {
@@ -1028,9 +791,6 @@
uint64_t qos:5;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug8_cn30xx cn31xx;
- struct cvmx_pko_mem_debug8_cn30xx cn38xx;
- struct cvmx_pko_mem_debug8_cn30xx cn38xxp2;
struct cvmx_pko_mem_debug8_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
@@ -1073,11 +833,6 @@
uint64_t reserved_29_63:35;
#endif
} cn52xx;
- struct cvmx_pko_mem_debug8_cn52xx cn52xxp1;
- struct cvmx_pko_mem_debug8_cn52xx cn56xx;
- struct cvmx_pko_mem_debug8_cn52xx cn56xxp1;
- struct cvmx_pko_mem_debug8_cn50xx cn58xx;
- struct cvmx_pko_mem_debug8_cn50xx cn58xxp1;
struct cvmx_pko_mem_debug8_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_42_63:22;
@@ -1107,9 +862,6 @@
uint64_t reserved_42_63:22;
#endif
} cn61xx;
- struct cvmx_pko_mem_debug8_cn52xx cn63xx;
- struct cvmx_pko_mem_debug8_cn52xx cn63xxp1;
- struct cvmx_pko_mem_debug8_cn61xx cn66xx;
struct cvmx_pko_mem_debug8_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_37_63:27;
@@ -1133,8 +885,6 @@
uint64_t reserved_37_63:27;
#endif
} cn68xx;
- struct cvmx_pko_mem_debug8_cn68xx cn68xxp1;
- struct cvmx_pko_mem_debug8_cn61xx cnf71xx;
};
union cvmx_pko_mem_debug9 {
@@ -1167,7 +917,6 @@
uint64_t reserved_28_63:36;
#endif
} cn30xx;
- struct cvmx_pko_mem_debug9_cn30xx cn31xx;
struct cvmx_pko_mem_debug9_cn38xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
@@ -1187,7 +936,6 @@
uint64_t reserved_28_63:36;
#endif
} cn38xx;
- struct cvmx_pko_mem_debug9_cn38xx cn38xxp2;
struct cvmx_pko_mem_debug9_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_49_63:15;
@@ -1201,19 +949,6 @@
uint64_t reserved_49_63:15;
#endif
} cn50xx;
- struct cvmx_pko_mem_debug9_cn50xx cn52xx;
- struct cvmx_pko_mem_debug9_cn50xx cn52xxp1;
- struct cvmx_pko_mem_debug9_cn50xx cn56xx;
- struct cvmx_pko_mem_debug9_cn50xx cn56xxp1;
- struct cvmx_pko_mem_debug9_cn50xx cn58xx;
- struct cvmx_pko_mem_debug9_cn50xx cn58xxp1;
- struct cvmx_pko_mem_debug9_cn50xx cn61xx;
- struct cvmx_pko_mem_debug9_cn50xx cn63xx;
- struct cvmx_pko_mem_debug9_cn50xx cn63xxp1;
- struct cvmx_pko_mem_debug9_cn50xx cn66xx;
- struct cvmx_pko_mem_debug9_cn50xx cn68xx;
- struct cvmx_pko_mem_debug9_cn50xx cn68xxp1;
- struct cvmx_pko_mem_debug9_cn50xx cnf71xx;
};
union cvmx_pko_mem_iport_ptrs {
@@ -1249,8 +984,6 @@
uint64_t reserved_63_63:1;
#endif
} s;
- struct cvmx_pko_mem_iport_ptrs_s cn68xx;
- struct cvmx_pko_mem_iport_ptrs_s cn68xxp1;
};
union cvmx_pko_mem_iport_qos {
@@ -1272,8 +1005,6 @@
uint64_t reserved_61_63:3;
#endif
} s;
- struct cvmx_pko_mem_iport_qos_s cn68xx;
- struct cvmx_pko_mem_iport_qos_s cn68xxp1;
};
union cvmx_pko_mem_iqueue_ptrs {
@@ -1303,8 +1034,6 @@
uint64_t s_tail:1;
#endif
} s;
- struct cvmx_pko_mem_iqueue_ptrs_s cn68xx;
- struct cvmx_pko_mem_iqueue_ptrs_s cn68xxp1;
};
union cvmx_pko_mem_iqueue_qos {
@@ -1324,8 +1053,6 @@
uint64_t reserved_61_63:3;
#endif
} s;
- struct cvmx_pko_mem_iqueue_qos_s cn68xx;
- struct cvmx_pko_mem_iqueue_qos_s cn68xxp1;
};
union cvmx_pko_mem_port_ptrs {
@@ -1349,15 +1076,6 @@
uint64_t reserved_62_63:2;
#endif
} s;
- struct cvmx_pko_mem_port_ptrs_s cn52xx;
- struct cvmx_pko_mem_port_ptrs_s cn52xxp1;
- struct cvmx_pko_mem_port_ptrs_s cn56xx;
- struct cvmx_pko_mem_port_ptrs_s cn56xxp1;
- struct cvmx_pko_mem_port_ptrs_s cn61xx;
- struct cvmx_pko_mem_port_ptrs_s cn63xx;
- struct cvmx_pko_mem_port_ptrs_s cn63xxp1;
- struct cvmx_pko_mem_port_ptrs_s cn66xx;
- struct cvmx_pko_mem_port_ptrs_s cnf71xx;
};
union cvmx_pko_mem_port_qos {
@@ -1377,15 +1095,6 @@
uint64_t reserved_61_63:3;
#endif
} s;
- struct cvmx_pko_mem_port_qos_s cn52xx;
- struct cvmx_pko_mem_port_qos_s cn52xxp1;
- struct cvmx_pko_mem_port_qos_s cn56xx;
- struct cvmx_pko_mem_port_qos_s cn56xxp1;
- struct cvmx_pko_mem_port_qos_s cn61xx;
- struct cvmx_pko_mem_port_qos_s cn63xx;
- struct cvmx_pko_mem_port_qos_s cn63xxp1;
- struct cvmx_pko_mem_port_qos_s cn66xx;
- struct cvmx_pko_mem_port_qos_s cnf71xx;
};
union cvmx_pko_mem_port_rate0 {
@@ -1420,16 +1129,6 @@
uint64_t reserved_51_63:13;
#endif
} cn52xx;
- struct cvmx_pko_mem_port_rate0_cn52xx cn52xxp1;
- struct cvmx_pko_mem_port_rate0_cn52xx cn56xx;
- struct cvmx_pko_mem_port_rate0_cn52xx cn56xxp1;
- struct cvmx_pko_mem_port_rate0_cn52xx cn61xx;
- struct cvmx_pko_mem_port_rate0_cn52xx cn63xx;
- struct cvmx_pko_mem_port_rate0_cn52xx cn63xxp1;
- struct cvmx_pko_mem_port_rate0_cn52xx cn66xx;
- struct cvmx_pko_mem_port_rate0_s cn68xx;
- struct cvmx_pko_mem_port_rate0_s cn68xxp1;
- struct cvmx_pko_mem_port_rate0_cn52xx cnf71xx;
};
union cvmx_pko_mem_port_rate1 {
@@ -1460,16 +1159,6 @@
uint64_t reserved_32_63:32;
#endif
} cn52xx;
- struct cvmx_pko_mem_port_rate1_cn52xx cn52xxp1;
- struct cvmx_pko_mem_port_rate1_cn52xx cn56xx;
- struct cvmx_pko_mem_port_rate1_cn52xx cn56xxp1;
- struct cvmx_pko_mem_port_rate1_cn52xx cn61xx;
- struct cvmx_pko_mem_port_rate1_cn52xx cn63xx;
- struct cvmx_pko_mem_port_rate1_cn52xx cn63xxp1;
- struct cvmx_pko_mem_port_rate1_cn52xx cn66xx;
- struct cvmx_pko_mem_port_rate1_s cn68xx;
- struct cvmx_pko_mem_port_rate1_s cn68xxp1;
- struct cvmx_pko_mem_port_rate1_cn52xx cnf71xx;
};
union cvmx_pko_mem_queue_ptrs {
@@ -1497,22 +1186,6 @@
uint64_t s_tail:1;
#endif
} s;
- struct cvmx_pko_mem_queue_ptrs_s cn30xx;
- struct cvmx_pko_mem_queue_ptrs_s cn31xx;
- struct cvmx_pko_mem_queue_ptrs_s cn38xx;
- struct cvmx_pko_mem_queue_ptrs_s cn38xxp2;
- struct cvmx_pko_mem_queue_ptrs_s cn50xx;
- struct cvmx_pko_mem_queue_ptrs_s cn52xx;
- struct cvmx_pko_mem_queue_ptrs_s cn52xxp1;
- struct cvmx_pko_mem_queue_ptrs_s cn56xx;
- struct cvmx_pko_mem_queue_ptrs_s cn56xxp1;
- struct cvmx_pko_mem_queue_ptrs_s cn58xx;
- struct cvmx_pko_mem_queue_ptrs_s cn58xxp1;
- struct cvmx_pko_mem_queue_ptrs_s cn61xx;
- struct cvmx_pko_mem_queue_ptrs_s cn63xx;
- struct cvmx_pko_mem_queue_ptrs_s cn63xxp1;
- struct cvmx_pko_mem_queue_ptrs_s cn66xx;
- struct cvmx_pko_mem_queue_ptrs_s cnf71xx;
};
union cvmx_pko_mem_queue_qos {
@@ -1532,22 +1205,6 @@
uint64_t reserved_61_63:3;
#endif
} s;
- struct cvmx_pko_mem_queue_qos_s cn30xx;
- struct cvmx_pko_mem_queue_qos_s cn31xx;
- struct cvmx_pko_mem_queue_qos_s cn38xx;
- struct cvmx_pko_mem_queue_qos_s cn38xxp2;
- struct cvmx_pko_mem_queue_qos_s cn50xx;
- struct cvmx_pko_mem_queue_qos_s cn52xx;
- struct cvmx_pko_mem_queue_qos_s cn52xxp1;
- struct cvmx_pko_mem_queue_qos_s cn56xx;
- struct cvmx_pko_mem_queue_qos_s cn56xxp1;
- struct cvmx_pko_mem_queue_qos_s cn58xx;
- struct cvmx_pko_mem_queue_qos_s cn58xxp1;
- struct cvmx_pko_mem_queue_qos_s cn61xx;
- struct cvmx_pko_mem_queue_qos_s cn63xx;
- struct cvmx_pko_mem_queue_qos_s cn63xxp1;
- struct cvmx_pko_mem_queue_qos_s cn66xx;
- struct cvmx_pko_mem_queue_qos_s cnf71xx;
};
union cvmx_pko_mem_throttle_int {
@@ -1569,8 +1226,6 @@
uint64_t reserved_47_63:17;
#endif
} s;
- struct cvmx_pko_mem_throttle_int_s cn68xx;
- struct cvmx_pko_mem_throttle_int_s cn68xxp1;
};
union cvmx_pko_mem_throttle_pipe {
@@ -1592,8 +1247,6 @@
uint64_t reserved_47_63:17;
#endif
} s;
- struct cvmx_pko_mem_throttle_pipe_s cn68xx;
- struct cvmx_pko_mem_throttle_pipe_s cn68xxp1;
};
union cvmx_pko_reg_bist_result {
@@ -1636,9 +1289,6 @@
uint64_t reserved_27_63:37;
#endif
} cn30xx;
- struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
- struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
- struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
struct cvmx_pko_reg_bist_result_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_33_63:31;
@@ -1711,15 +1361,6 @@
uint64_t reserved_35_63:29;
#endif
} cn52xx;
- struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
- struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
- struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
- struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
- struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
- struct cvmx_pko_reg_bist_result_cn52xx cn61xx;
- struct cvmx_pko_reg_bist_result_cn52xx cn63xx;
- struct cvmx_pko_reg_bist_result_cn52xx cn63xxp1;
- struct cvmx_pko_reg_bist_result_cn52xx cn66xx;
struct cvmx_pko_reg_bist_result_cn68xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_36_63:28;
@@ -1808,7 +1449,6 @@
uint64_t reserved_35_63:29;
#endif
} cn68xxp1;
- struct cvmx_pko_reg_bist_result_cn52xx cnf71xx;
};
union cvmx_pko_reg_cmd_buf {
@@ -1826,24 +1466,6 @@
uint64_t reserved_23_63:41;
#endif
} s;
- struct cvmx_pko_reg_cmd_buf_s cn30xx;
- struct cvmx_pko_reg_cmd_buf_s cn31xx;
- struct cvmx_pko_reg_cmd_buf_s cn38xx;
- struct cvmx_pko_reg_cmd_buf_s cn38xxp2;
- struct cvmx_pko_reg_cmd_buf_s cn50xx;
- struct cvmx_pko_reg_cmd_buf_s cn52xx;
- struct cvmx_pko_reg_cmd_buf_s cn52xxp1;
- struct cvmx_pko_reg_cmd_buf_s cn56xx;
- struct cvmx_pko_reg_cmd_buf_s cn56xxp1;
- struct cvmx_pko_reg_cmd_buf_s cn58xx;
- struct cvmx_pko_reg_cmd_buf_s cn58xxp1;
- struct cvmx_pko_reg_cmd_buf_s cn61xx;
- struct cvmx_pko_reg_cmd_buf_s cn63xx;
- struct cvmx_pko_reg_cmd_buf_s cn63xxp1;
- struct cvmx_pko_reg_cmd_buf_s cn66xx;
- struct cvmx_pko_reg_cmd_buf_s cn68xx;
- struct cvmx_pko_reg_cmd_buf_s cn68xxp1;
- struct cvmx_pko_reg_cmd_buf_s cnf71xx;
};
union cvmx_pko_reg_crc_ctlx {
@@ -1859,10 +1481,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_pko_reg_crc_ctlx_s cn38xx;
- struct cvmx_pko_reg_crc_ctlx_s cn38xxp2;
- struct cvmx_pko_reg_crc_ctlx_s cn58xx;
- struct cvmx_pko_reg_crc_ctlx_s cn58xxp1;
};
union cvmx_pko_reg_crc_enable {
@@ -1876,10 +1494,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pko_reg_crc_enable_s cn38xx;
- struct cvmx_pko_reg_crc_enable_s cn38xxp2;
- struct cvmx_pko_reg_crc_enable_s cn58xx;
- struct cvmx_pko_reg_crc_enable_s cn58xxp1;
};
union cvmx_pko_reg_crc_ivx {
@@ -1893,10 +1507,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pko_reg_crc_ivx_s cn38xx;
- struct cvmx_pko_reg_crc_ivx_s cn38xxp2;
- struct cvmx_pko_reg_crc_ivx_s cn58xx;
- struct cvmx_pko_reg_crc_ivx_s cn58xxp1;
};
union cvmx_pko_reg_debug0 {
@@ -1917,23 +1527,6 @@
uint64_t reserved_17_63:47;
#endif
} cn30xx;
- struct cvmx_pko_reg_debug0_cn30xx cn31xx;
- struct cvmx_pko_reg_debug0_cn30xx cn38xx;
- struct cvmx_pko_reg_debug0_cn30xx cn38xxp2;
- struct cvmx_pko_reg_debug0_s cn50xx;
- struct cvmx_pko_reg_debug0_s cn52xx;
- struct cvmx_pko_reg_debug0_s cn52xxp1;
- struct cvmx_pko_reg_debug0_s cn56xx;
- struct cvmx_pko_reg_debug0_s cn56xxp1;
- struct cvmx_pko_reg_debug0_s cn58xx;
- struct cvmx_pko_reg_debug0_s cn58xxp1;
- struct cvmx_pko_reg_debug0_s cn61xx;
- struct cvmx_pko_reg_debug0_s cn63xx;
- struct cvmx_pko_reg_debug0_s cn63xxp1;
- struct cvmx_pko_reg_debug0_s cn66xx;
- struct cvmx_pko_reg_debug0_s cn68xx;
- struct cvmx_pko_reg_debug0_s cn68xxp1;
- struct cvmx_pko_reg_debug0_s cnf71xx;
};
union cvmx_pko_reg_debug1 {
@@ -1945,20 +1538,6 @@
uint64_t asserts:64;
#endif
} s;
- struct cvmx_pko_reg_debug1_s cn50xx;
- struct cvmx_pko_reg_debug1_s cn52xx;
- struct cvmx_pko_reg_debug1_s cn52xxp1;
- struct cvmx_pko_reg_debug1_s cn56xx;
- struct cvmx_pko_reg_debug1_s cn56xxp1;
- struct cvmx_pko_reg_debug1_s cn58xx;
- struct cvmx_pko_reg_debug1_s cn58xxp1;
- struct cvmx_pko_reg_debug1_s cn61xx;
- struct cvmx_pko_reg_debug1_s cn63xx;
- struct cvmx_pko_reg_debug1_s cn63xxp1;
- struct cvmx_pko_reg_debug1_s cn66xx;
- struct cvmx_pko_reg_debug1_s cn68xx;
- struct cvmx_pko_reg_debug1_s cn68xxp1;
- struct cvmx_pko_reg_debug1_s cnf71xx;
};
union cvmx_pko_reg_debug2 {
@@ -1970,20 +1549,6 @@
uint64_t asserts:64;
#endif
} s;
- struct cvmx_pko_reg_debug2_s cn50xx;
- struct cvmx_pko_reg_debug2_s cn52xx;
- struct cvmx_pko_reg_debug2_s cn52xxp1;
- struct cvmx_pko_reg_debug2_s cn56xx;
- struct cvmx_pko_reg_debug2_s cn56xxp1;
- struct cvmx_pko_reg_debug2_s cn58xx;
- struct cvmx_pko_reg_debug2_s cn58xxp1;
- struct cvmx_pko_reg_debug2_s cn61xx;
- struct cvmx_pko_reg_debug2_s cn63xx;
- struct cvmx_pko_reg_debug2_s cn63xxp1;
- struct cvmx_pko_reg_debug2_s cn66xx;
- struct cvmx_pko_reg_debug2_s cn68xx;
- struct cvmx_pko_reg_debug2_s cn68xxp1;
- struct cvmx_pko_reg_debug2_s cnf71xx;
};
union cvmx_pko_reg_debug3 {
@@ -1995,20 +1560,6 @@
uint64_t asserts:64;
#endif
} s;
- struct cvmx_pko_reg_debug3_s cn50xx;
- struct cvmx_pko_reg_debug3_s cn52xx;
- struct cvmx_pko_reg_debug3_s cn52xxp1;
- struct cvmx_pko_reg_debug3_s cn56xx;
- struct cvmx_pko_reg_debug3_s cn56xxp1;
- struct cvmx_pko_reg_debug3_s cn58xx;
- struct cvmx_pko_reg_debug3_s cn58xxp1;
- struct cvmx_pko_reg_debug3_s cn61xx;
- struct cvmx_pko_reg_debug3_s cn63xx;
- struct cvmx_pko_reg_debug3_s cn63xxp1;
- struct cvmx_pko_reg_debug3_s cn66xx;
- struct cvmx_pko_reg_debug3_s cn68xx;
- struct cvmx_pko_reg_debug3_s cn68xxp1;
- struct cvmx_pko_reg_debug3_s cnf71xx;
};
union cvmx_pko_reg_debug4 {
@@ -2020,8 +1571,6 @@
uint64_t asserts:64;
#endif
} s;
- struct cvmx_pko_reg_debug4_s cn68xx;
- struct cvmx_pko_reg_debug4_s cn68xxp1;
};
union cvmx_pko_reg_engine_inflight {
@@ -2090,9 +1639,6 @@
uint64_t reserved_40_63:24;
#endif
} cn52xx;
- struct cvmx_pko_reg_engine_inflight_cn52xx cn52xxp1;
- struct cvmx_pko_reg_engine_inflight_cn52xx cn56xx;
- struct cvmx_pko_reg_engine_inflight_cn52xx cn56xxp1;
struct cvmx_pko_reg_engine_inflight_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_56_63:8;
@@ -2159,11 +1705,6 @@
uint64_t reserved_48_63:16;
#endif
} cn63xx;
- struct cvmx_pko_reg_engine_inflight_cn63xx cn63xxp1;
- struct cvmx_pko_reg_engine_inflight_cn61xx cn66xx;
- struct cvmx_pko_reg_engine_inflight_s cn68xx;
- struct cvmx_pko_reg_engine_inflight_s cn68xxp1;
- struct cvmx_pko_reg_engine_inflight_cn61xx cnf71xx;
};
union cvmx_pko_reg_engine_inflight1 {
@@ -2183,8 +1724,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pko_reg_engine_inflight1_s cn68xx;
- struct cvmx_pko_reg_engine_inflight1_s cn68xxp1;
};
union cvmx_pko_reg_engine_storagex {
@@ -2226,8 +1765,6 @@
uint64_t engine15:4;
#endif
} s;
- struct cvmx_pko_reg_engine_storagex_s cn68xx;
- struct cvmx_pko_reg_engine_storagex_s cn68xxp1;
};
union cvmx_pko_reg_engine_thresh {
@@ -2250,9 +1787,6 @@
uint64_t reserved_10_63:54;
#endif
} cn52xx;
- struct cvmx_pko_reg_engine_thresh_cn52xx cn52xxp1;
- struct cvmx_pko_reg_engine_thresh_cn52xx cn56xx;
- struct cvmx_pko_reg_engine_thresh_cn52xx cn56xxp1;
struct cvmx_pko_reg_engine_thresh_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
@@ -2271,11 +1805,6 @@
uint64_t reserved_12_63:52;
#endif
} cn63xx;
- struct cvmx_pko_reg_engine_thresh_cn63xx cn63xxp1;
- struct cvmx_pko_reg_engine_thresh_cn61xx cn66xx;
- struct cvmx_pko_reg_engine_thresh_s cn68xx;
- struct cvmx_pko_reg_engine_thresh_s cn68xxp1;
- struct cvmx_pko_reg_engine_thresh_cn61xx cnf71xx;
};
union cvmx_pko_reg_error {
@@ -2306,9 +1835,6 @@
uint64_t reserved_2_63:62;
#endif
} cn30xx;
- struct cvmx_pko_reg_error_cn30xx cn31xx;
- struct cvmx_pko_reg_error_cn30xx cn38xx;
- struct cvmx_pko_reg_error_cn30xx cn38xxp2;
struct cvmx_pko_reg_error_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63:61;
@@ -2322,19 +1848,6 @@
uint64_t reserved_3_63:61;
#endif
} cn50xx;
- struct cvmx_pko_reg_error_cn50xx cn52xx;
- struct cvmx_pko_reg_error_cn50xx cn52xxp1;
- struct cvmx_pko_reg_error_cn50xx cn56xx;
- struct cvmx_pko_reg_error_cn50xx cn56xxp1;
- struct cvmx_pko_reg_error_cn50xx cn58xx;
- struct cvmx_pko_reg_error_cn50xx cn58xxp1;
- struct cvmx_pko_reg_error_cn50xx cn61xx;
- struct cvmx_pko_reg_error_cn50xx cn63xx;
- struct cvmx_pko_reg_error_cn50xx cn63xxp1;
- struct cvmx_pko_reg_error_cn50xx cn66xx;
- struct cvmx_pko_reg_error_s cn68xx;
- struct cvmx_pko_reg_error_s cn68xxp1;
- struct cvmx_pko_reg_error_cn50xx cnf71xx;
};
union cvmx_pko_reg_flags {
@@ -2379,16 +1892,6 @@
uint64_t reserved_4_63:60;
#endif
} cn30xx;
- struct cvmx_pko_reg_flags_cn30xx cn31xx;
- struct cvmx_pko_reg_flags_cn30xx cn38xx;
- struct cvmx_pko_reg_flags_cn30xx cn38xxp2;
- struct cvmx_pko_reg_flags_cn30xx cn50xx;
- struct cvmx_pko_reg_flags_cn30xx cn52xx;
- struct cvmx_pko_reg_flags_cn30xx cn52xxp1;
- struct cvmx_pko_reg_flags_cn30xx cn56xx;
- struct cvmx_pko_reg_flags_cn30xx cn56xxp1;
- struct cvmx_pko_reg_flags_cn30xx cn58xx;
- struct cvmx_pko_reg_flags_cn30xx cn58xxp1;
struct cvmx_pko_reg_flags_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
@@ -2410,10 +1913,6 @@
uint64_t reserved_9_63:55;
#endif
} cn61xx;
- struct cvmx_pko_reg_flags_cn30xx cn63xx;
- struct cvmx_pko_reg_flags_cn30xx cn63xxp1;
- struct cvmx_pko_reg_flags_cn61xx cn66xx;
- struct cvmx_pko_reg_flags_s cn68xx;
struct cvmx_pko_reg_flags_cn68xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_7_63:57;
@@ -2435,7 +1934,6 @@
uint64_t reserved_7_63:57;
#endif
} cn68xxp1;
- struct cvmx_pko_reg_flags_cn61xx cnf71xx;
};
union cvmx_pko_reg_gmx_port_mode {
@@ -2451,22 +1949,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_pko_reg_gmx_port_mode_s cn30xx;
- struct cvmx_pko_reg_gmx_port_mode_s cn31xx;
- struct cvmx_pko_reg_gmx_port_mode_s cn38xx;
- struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2;
- struct cvmx_pko_reg_gmx_port_mode_s cn50xx;
- struct cvmx_pko_reg_gmx_port_mode_s cn52xx;
- struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1;
- struct cvmx_pko_reg_gmx_port_mode_s cn56xx;
- struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1;
- struct cvmx_pko_reg_gmx_port_mode_s cn58xx;
- struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1;
- struct cvmx_pko_reg_gmx_port_mode_s cn61xx;
- struct cvmx_pko_reg_gmx_port_mode_s cn63xx;
- struct cvmx_pko_reg_gmx_port_mode_s cn63xxp1;
- struct cvmx_pko_reg_gmx_port_mode_s cn66xx;
- struct cvmx_pko_reg_gmx_port_mode_s cnf71xx;
};
union cvmx_pko_reg_int_mask {
@@ -2497,9 +1979,6 @@
uint64_t reserved_2_63:62;
#endif
} cn30xx;
- struct cvmx_pko_reg_int_mask_cn30xx cn31xx;
- struct cvmx_pko_reg_int_mask_cn30xx cn38xx;
- struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2;
struct cvmx_pko_reg_int_mask_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_3_63:61;
@@ -2513,19 +1992,6 @@
uint64_t reserved_3_63:61;
#endif
} cn50xx;
- struct cvmx_pko_reg_int_mask_cn50xx cn52xx;
- struct cvmx_pko_reg_int_mask_cn50xx cn52xxp1;
- struct cvmx_pko_reg_int_mask_cn50xx cn56xx;
- struct cvmx_pko_reg_int_mask_cn50xx cn56xxp1;
- struct cvmx_pko_reg_int_mask_cn50xx cn58xx;
- struct cvmx_pko_reg_int_mask_cn50xx cn58xxp1;
- struct cvmx_pko_reg_int_mask_cn50xx cn61xx;
- struct cvmx_pko_reg_int_mask_cn50xx cn63xx;
- struct cvmx_pko_reg_int_mask_cn50xx cn63xxp1;
- struct cvmx_pko_reg_int_mask_cn50xx cn66xx;
- struct cvmx_pko_reg_int_mask_s cn68xx;
- struct cvmx_pko_reg_int_mask_s cn68xxp1;
- struct cvmx_pko_reg_int_mask_cn50xx cnf71xx;
};
union cvmx_pko_reg_loopback_bpid {
@@ -2569,8 +2035,6 @@
uint64_t reserved_59_63:5;
#endif
} s;
- struct cvmx_pko_reg_loopback_bpid_s cn68xx;
- struct cvmx_pko_reg_loopback_bpid_s cn68xxp1;
};
union cvmx_pko_reg_loopback_pkind {
@@ -2614,8 +2078,6 @@
uint64_t reserved_59_63:5;
#endif
} s;
- struct cvmx_pko_reg_loopback_pkind_s cn68xx;
- struct cvmx_pko_reg_loopback_pkind_s cn68xxp1;
};
union cvmx_pko_reg_min_pkt {
@@ -2641,8 +2103,6 @@
uint64_t size7:8;
#endif
} s;
- struct cvmx_pko_reg_min_pkt_s cn68xx;
- struct cvmx_pko_reg_min_pkt_s cn68xxp1;
};
union cvmx_pko_reg_preempt {
@@ -2656,17 +2116,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pko_reg_preempt_s cn52xx;
- struct cvmx_pko_reg_preempt_s cn52xxp1;
- struct cvmx_pko_reg_preempt_s cn56xx;
- struct cvmx_pko_reg_preempt_s cn56xxp1;
- struct cvmx_pko_reg_preempt_s cn61xx;
- struct cvmx_pko_reg_preempt_s cn63xx;
- struct cvmx_pko_reg_preempt_s cn63xxp1;
- struct cvmx_pko_reg_preempt_s cn66xx;
- struct cvmx_pko_reg_preempt_s cn68xx;
- struct cvmx_pko_reg_preempt_s cn68xxp1;
- struct cvmx_pko_reg_preempt_s cnf71xx;
};
union cvmx_pko_reg_queue_mode {
@@ -2680,24 +2129,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_pko_reg_queue_mode_s cn30xx;
- struct cvmx_pko_reg_queue_mode_s cn31xx;
- struct cvmx_pko_reg_queue_mode_s cn38xx;
- struct cvmx_pko_reg_queue_mode_s cn38xxp2;
- struct cvmx_pko_reg_queue_mode_s cn50xx;
- struct cvmx_pko_reg_queue_mode_s cn52xx;
- struct cvmx_pko_reg_queue_mode_s cn52xxp1;
- struct cvmx_pko_reg_queue_mode_s cn56xx;
- struct cvmx_pko_reg_queue_mode_s cn56xxp1;
- struct cvmx_pko_reg_queue_mode_s cn58xx;
- struct cvmx_pko_reg_queue_mode_s cn58xxp1;
- struct cvmx_pko_reg_queue_mode_s cn61xx;
- struct cvmx_pko_reg_queue_mode_s cn63xx;
- struct cvmx_pko_reg_queue_mode_s cn63xxp1;
- struct cvmx_pko_reg_queue_mode_s cn66xx;
- struct cvmx_pko_reg_queue_mode_s cn68xx;
- struct cvmx_pko_reg_queue_mode_s cn68xxp1;
- struct cvmx_pko_reg_queue_mode_s cnf71xx;
};
union cvmx_pko_reg_queue_preempt {
@@ -2713,17 +2144,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_pko_reg_queue_preempt_s cn52xx;
- struct cvmx_pko_reg_queue_preempt_s cn52xxp1;
- struct cvmx_pko_reg_queue_preempt_s cn56xx;
- struct cvmx_pko_reg_queue_preempt_s cn56xxp1;
- struct cvmx_pko_reg_queue_preempt_s cn61xx;
- struct cvmx_pko_reg_queue_preempt_s cn63xx;
- struct cvmx_pko_reg_queue_preempt_s cn63xxp1;
- struct cvmx_pko_reg_queue_preempt_s cn66xx;
- struct cvmx_pko_reg_queue_preempt_s cn68xx;
- struct cvmx_pko_reg_queue_preempt_s cn68xxp1;
- struct cvmx_pko_reg_queue_preempt_s cnf71xx;
};
union cvmx_pko_reg_queue_ptrs1 {
@@ -2739,18 +2159,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_pko_reg_queue_ptrs1_s cn50xx;
- struct cvmx_pko_reg_queue_ptrs1_s cn52xx;
- struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1;
- struct cvmx_pko_reg_queue_ptrs1_s cn56xx;
- struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1;
- struct cvmx_pko_reg_queue_ptrs1_s cn58xx;
- struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1;
- struct cvmx_pko_reg_queue_ptrs1_s cn61xx;
- struct cvmx_pko_reg_queue_ptrs1_s cn63xx;
- struct cvmx_pko_reg_queue_ptrs1_s cn63xxp1;
- struct cvmx_pko_reg_queue_ptrs1_s cn66xx;
- struct cvmx_pko_reg_queue_ptrs1_s cnf71xx;
};
union cvmx_pko_reg_read_idx {
@@ -2766,24 +2174,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_pko_reg_read_idx_s cn30xx;
- struct cvmx_pko_reg_read_idx_s cn31xx;
- struct cvmx_pko_reg_read_idx_s cn38xx;
- struct cvmx_pko_reg_read_idx_s cn38xxp2;
- struct cvmx_pko_reg_read_idx_s cn50xx;
- struct cvmx_pko_reg_read_idx_s cn52xx;
- struct cvmx_pko_reg_read_idx_s cn52xxp1;
- struct cvmx_pko_reg_read_idx_s cn56xx;
- struct cvmx_pko_reg_read_idx_s cn56xxp1;
- struct cvmx_pko_reg_read_idx_s cn58xx;
- struct cvmx_pko_reg_read_idx_s cn58xxp1;
- struct cvmx_pko_reg_read_idx_s cn61xx;
- struct cvmx_pko_reg_read_idx_s cn63xx;
- struct cvmx_pko_reg_read_idx_s cn63xxp1;
- struct cvmx_pko_reg_read_idx_s cn66xx;
- struct cvmx_pko_reg_read_idx_s cn68xx;
- struct cvmx_pko_reg_read_idx_s cn68xxp1;
- struct cvmx_pko_reg_read_idx_s cnf71xx;
};
union cvmx_pko_reg_throttle {
@@ -2797,8 +2187,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pko_reg_throttle_s cn68xx;
- struct cvmx_pko_reg_throttle_s cn68xxp1;
};
union cvmx_pko_reg_timestamp {
@@ -2812,13 +2200,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_pko_reg_timestamp_s cn61xx;
- struct cvmx_pko_reg_timestamp_s cn63xx;
- struct cvmx_pko_reg_timestamp_s cn63xxp1;
- struct cvmx_pko_reg_timestamp_s cn66xx;
- struct cvmx_pko_reg_timestamp_s cn68xx;
- struct cvmx_pko_reg_timestamp_s cn68xxp1;
- struct cvmx_pko_reg_timestamp_s cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
index 5f47f76..20eb9c4 100644
--- a/arch/mips/include/asm/octeon/cvmx-pko.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
@@ -611,7 +611,7 @@
pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
- status->doorbell = debug8.cn58xx.doorbell;
+ status->doorbell = debug8.cn50xx.doorbell;
}
}
diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
index 6a3db4b..474dd54 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
@@ -160,8 +160,6 @@
uint64_t reserved_32_63:32;
#endif
} cn38xx;
- struct cvmx_pow_bist_stat_cn38xx cn38xxp2;
- struct cvmx_pow_bist_stat_cn31xx cn50xx;
struct cvmx_pow_bist_stat_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -191,7 +189,6 @@
uint64_t reserved_20_63:44;
#endif
} cn52xx;
- struct cvmx_pow_bist_stat_cn52xx cn52xxp1;
struct cvmx_pow_bist_stat_cn56xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
@@ -223,9 +220,6 @@
uint64_t reserved_28_63:36;
#endif
} cn56xx;
- struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
- struct cvmx_pow_bist_stat_cn38xx cn58xx;
- struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
struct cvmx_pow_bist_stat_cn61xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_20_63:44;
@@ -276,7 +270,6 @@
uint64_t reserved_22_63:42;
#endif
} cn63xx;
- struct cvmx_pow_bist_stat_cn63xx cn63xxp1;
struct cvmx_pow_bist_stat_cn66xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_26_63:38;
@@ -302,7 +295,6 @@
uint64_t reserved_26_63:38;
#endif
} cn66xx;
- struct cvmx_pow_bist_stat_cn61xx cnf71xx;
};
union cvmx_pow_ds_pc {
@@ -316,22 +308,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pow_ds_pc_s cn30xx;
- struct cvmx_pow_ds_pc_s cn31xx;
- struct cvmx_pow_ds_pc_s cn38xx;
- struct cvmx_pow_ds_pc_s cn38xxp2;
- struct cvmx_pow_ds_pc_s cn50xx;
- struct cvmx_pow_ds_pc_s cn52xx;
- struct cvmx_pow_ds_pc_s cn52xxp1;
- struct cvmx_pow_ds_pc_s cn56xx;
- struct cvmx_pow_ds_pc_s cn56xxp1;
- struct cvmx_pow_ds_pc_s cn58xx;
- struct cvmx_pow_ds_pc_s cn58xxp1;
- struct cvmx_pow_ds_pc_s cn61xx;
- struct cvmx_pow_ds_pc_s cn63xx;
- struct cvmx_pow_ds_pc_s cn63xxp1;
- struct cvmx_pow_ds_pc_s cn66xx;
- struct cvmx_pow_ds_pc_s cnf71xx;
};
union cvmx_pow_ecc_err {
@@ -367,7 +343,6 @@
uint64_t reserved_45_63:19;
#endif
} s;
- struct cvmx_pow_ecc_err_s cn30xx;
struct cvmx_pow_ecc_err_cn31xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_14_63:50;
@@ -391,20 +366,6 @@
uint64_t reserved_14_63:50;
#endif
} cn31xx;
- struct cvmx_pow_ecc_err_s cn38xx;
- struct cvmx_pow_ecc_err_cn31xx cn38xxp2;
- struct cvmx_pow_ecc_err_s cn50xx;
- struct cvmx_pow_ecc_err_s cn52xx;
- struct cvmx_pow_ecc_err_s cn52xxp1;
- struct cvmx_pow_ecc_err_s cn56xx;
- struct cvmx_pow_ecc_err_s cn56xxp1;
- struct cvmx_pow_ecc_err_s cn58xx;
- struct cvmx_pow_ecc_err_s cn58xxp1;
- struct cvmx_pow_ecc_err_s cn61xx;
- struct cvmx_pow_ecc_err_s cn63xx;
- struct cvmx_pow_ecc_err_s cn63xxp1;
- struct cvmx_pow_ecc_err_s cn66xx;
- struct cvmx_pow_ecc_err_s cnf71xx;
};
union cvmx_pow_int_ctl {
@@ -420,22 +381,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_pow_int_ctl_s cn30xx;
- struct cvmx_pow_int_ctl_s cn31xx;
- struct cvmx_pow_int_ctl_s cn38xx;
- struct cvmx_pow_int_ctl_s cn38xxp2;
- struct cvmx_pow_int_ctl_s cn50xx;
- struct cvmx_pow_int_ctl_s cn52xx;
- struct cvmx_pow_int_ctl_s cn52xxp1;
- struct cvmx_pow_int_ctl_s cn56xx;
- struct cvmx_pow_int_ctl_s cn56xxp1;
- struct cvmx_pow_int_ctl_s cn58xx;
- struct cvmx_pow_int_ctl_s cn58xxp1;
- struct cvmx_pow_int_ctl_s cn61xx;
- struct cvmx_pow_int_ctl_s cn63xx;
- struct cvmx_pow_int_ctl_s cn63xxp1;
- struct cvmx_pow_int_ctl_s cn66xx;
- struct cvmx_pow_int_ctl_s cnf71xx;
};
union cvmx_pow_iq_cntx {
@@ -449,22 +394,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pow_iq_cntx_s cn30xx;
- struct cvmx_pow_iq_cntx_s cn31xx;
- struct cvmx_pow_iq_cntx_s cn38xx;
- struct cvmx_pow_iq_cntx_s cn38xxp2;
- struct cvmx_pow_iq_cntx_s cn50xx;
- struct cvmx_pow_iq_cntx_s cn52xx;
- struct cvmx_pow_iq_cntx_s cn52xxp1;
- struct cvmx_pow_iq_cntx_s cn56xx;
- struct cvmx_pow_iq_cntx_s cn56xxp1;
- struct cvmx_pow_iq_cntx_s cn58xx;
- struct cvmx_pow_iq_cntx_s cn58xxp1;
- struct cvmx_pow_iq_cntx_s cn61xx;
- struct cvmx_pow_iq_cntx_s cn63xx;
- struct cvmx_pow_iq_cntx_s cn63xxp1;
- struct cvmx_pow_iq_cntx_s cn66xx;
- struct cvmx_pow_iq_cntx_s cnf71xx;
};
union cvmx_pow_iq_com_cnt {
@@ -478,22 +407,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pow_iq_com_cnt_s cn30xx;
- struct cvmx_pow_iq_com_cnt_s cn31xx;
- struct cvmx_pow_iq_com_cnt_s cn38xx;
- struct cvmx_pow_iq_com_cnt_s cn38xxp2;
- struct cvmx_pow_iq_com_cnt_s cn50xx;
- struct cvmx_pow_iq_com_cnt_s cn52xx;
- struct cvmx_pow_iq_com_cnt_s cn52xxp1;
- struct cvmx_pow_iq_com_cnt_s cn56xx;
- struct cvmx_pow_iq_com_cnt_s cn56xxp1;
- struct cvmx_pow_iq_com_cnt_s cn58xx;
- struct cvmx_pow_iq_com_cnt_s cn58xxp1;
- struct cvmx_pow_iq_com_cnt_s cn61xx;
- struct cvmx_pow_iq_com_cnt_s cn63xx;
- struct cvmx_pow_iq_com_cnt_s cn63xxp1;
- struct cvmx_pow_iq_com_cnt_s cn66xx;
- struct cvmx_pow_iq_com_cnt_s cnf71xx;
};
union cvmx_pow_iq_int {
@@ -507,15 +420,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_pow_iq_int_s cn52xx;
- struct cvmx_pow_iq_int_s cn52xxp1;
- struct cvmx_pow_iq_int_s cn56xx;
- struct cvmx_pow_iq_int_s cn56xxp1;
- struct cvmx_pow_iq_int_s cn61xx;
- struct cvmx_pow_iq_int_s cn63xx;
- struct cvmx_pow_iq_int_s cn63xxp1;
- struct cvmx_pow_iq_int_s cn66xx;
- struct cvmx_pow_iq_int_s cnf71xx;
};
union cvmx_pow_iq_int_en {
@@ -529,15 +433,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_pow_iq_int_en_s cn52xx;
- struct cvmx_pow_iq_int_en_s cn52xxp1;
- struct cvmx_pow_iq_int_en_s cn56xx;
- struct cvmx_pow_iq_int_en_s cn56xxp1;
- struct cvmx_pow_iq_int_en_s cn61xx;
- struct cvmx_pow_iq_int_en_s cn63xx;
- struct cvmx_pow_iq_int_en_s cn63xxp1;
- struct cvmx_pow_iq_int_en_s cn66xx;
- struct cvmx_pow_iq_int_en_s cnf71xx;
};
union cvmx_pow_iq_thrx {
@@ -551,15 +446,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pow_iq_thrx_s cn52xx;
- struct cvmx_pow_iq_thrx_s cn52xxp1;
- struct cvmx_pow_iq_thrx_s cn56xx;
- struct cvmx_pow_iq_thrx_s cn56xxp1;
- struct cvmx_pow_iq_thrx_s cn61xx;
- struct cvmx_pow_iq_thrx_s cn63xx;
- struct cvmx_pow_iq_thrx_s cn63xxp1;
- struct cvmx_pow_iq_thrx_s cn66xx;
- struct cvmx_pow_iq_thrx_s cnf71xx;
};
union cvmx_pow_nos_cnt {
@@ -591,9 +477,6 @@
uint64_t reserved_9_63:55;
#endif
} cn31xx;
- struct cvmx_pow_nos_cnt_s cn38xx;
- struct cvmx_pow_nos_cnt_s cn38xxp2;
- struct cvmx_pow_nos_cnt_cn31xx cn50xx;
struct cvmx_pow_nos_cnt_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_10_63:54;
@@ -603,12 +486,6 @@
uint64_t reserved_10_63:54;
#endif
} cn52xx;
- struct cvmx_pow_nos_cnt_cn52xx cn52xxp1;
- struct cvmx_pow_nos_cnt_s cn56xx;
- struct cvmx_pow_nos_cnt_s cn56xxp1;
- struct cvmx_pow_nos_cnt_s cn58xx;
- struct cvmx_pow_nos_cnt_s cn58xxp1;
- struct cvmx_pow_nos_cnt_cn52xx cn61xx;
struct cvmx_pow_nos_cnt_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
@@ -618,9 +495,6 @@
uint64_t reserved_11_63:53;
#endif
} cn63xx;
- struct cvmx_pow_nos_cnt_cn63xx cn63xxp1;
- struct cvmx_pow_nos_cnt_cn63xx cn66xx;
- struct cvmx_pow_nos_cnt_cn52xx cnf71xx;
};
union cvmx_pow_nw_tim {
@@ -634,22 +508,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_pow_nw_tim_s cn30xx;
- struct cvmx_pow_nw_tim_s cn31xx;
- struct cvmx_pow_nw_tim_s cn38xx;
- struct cvmx_pow_nw_tim_s cn38xxp2;
- struct cvmx_pow_nw_tim_s cn50xx;
- struct cvmx_pow_nw_tim_s cn52xx;
- struct cvmx_pow_nw_tim_s cn52xxp1;
- struct cvmx_pow_nw_tim_s cn56xx;
- struct cvmx_pow_nw_tim_s cn56xxp1;
- struct cvmx_pow_nw_tim_s cn58xx;
- struct cvmx_pow_nw_tim_s cn58xxp1;
- struct cvmx_pow_nw_tim_s cn61xx;
- struct cvmx_pow_nw_tim_s cn63xx;
- struct cvmx_pow_nw_tim_s cn63xxp1;
- struct cvmx_pow_nw_tim_s cn66xx;
- struct cvmx_pow_nw_tim_s cnf71xx;
};
union cvmx_pow_pf_rst_msk {
@@ -663,18 +521,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_pow_pf_rst_msk_s cn50xx;
- struct cvmx_pow_pf_rst_msk_s cn52xx;
- struct cvmx_pow_pf_rst_msk_s cn52xxp1;
- struct cvmx_pow_pf_rst_msk_s cn56xx;
- struct cvmx_pow_pf_rst_msk_s cn56xxp1;
- struct cvmx_pow_pf_rst_msk_s cn58xx;
- struct cvmx_pow_pf_rst_msk_s cn58xxp1;
- struct cvmx_pow_pf_rst_msk_s cn61xx;
- struct cvmx_pow_pf_rst_msk_s cn63xx;
- struct cvmx_pow_pf_rst_msk_s cn63xxp1;
- struct cvmx_pow_pf_rst_msk_s cn66xx;
- struct cvmx_pow_pf_rst_msk_s cnf71xx;
};
union cvmx_pow_pp_grp_mskx {
@@ -713,21 +559,6 @@
uint64_t reserved_16_63:48;
#endif
} cn30xx;
- struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx;
- struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx;
- struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2;
- struct cvmx_pow_pp_grp_mskx_s cn50xx;
- struct cvmx_pow_pp_grp_mskx_s cn52xx;
- struct cvmx_pow_pp_grp_mskx_s cn52xxp1;
- struct cvmx_pow_pp_grp_mskx_s cn56xx;
- struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
- struct cvmx_pow_pp_grp_mskx_s cn58xx;
- struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
- struct cvmx_pow_pp_grp_mskx_s cn61xx;
- struct cvmx_pow_pp_grp_mskx_s cn63xx;
- struct cvmx_pow_pp_grp_mskx_s cn63xxp1;
- struct cvmx_pow_pp_grp_mskx_s cn66xx;
- struct cvmx_pow_pp_grp_mskx_s cnf71xx;
};
union cvmx_pow_qos_rndx {
@@ -747,22 +578,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pow_qos_rndx_s cn30xx;
- struct cvmx_pow_qos_rndx_s cn31xx;
- struct cvmx_pow_qos_rndx_s cn38xx;
- struct cvmx_pow_qos_rndx_s cn38xxp2;
- struct cvmx_pow_qos_rndx_s cn50xx;
- struct cvmx_pow_qos_rndx_s cn52xx;
- struct cvmx_pow_qos_rndx_s cn52xxp1;
- struct cvmx_pow_qos_rndx_s cn56xx;
- struct cvmx_pow_qos_rndx_s cn56xxp1;
- struct cvmx_pow_qos_rndx_s cn58xx;
- struct cvmx_pow_qos_rndx_s cn58xxp1;
- struct cvmx_pow_qos_rndx_s cn61xx;
- struct cvmx_pow_qos_rndx_s cn63xx;
- struct cvmx_pow_qos_rndx_s cn63xxp1;
- struct cvmx_pow_qos_rndx_s cn66xx;
- struct cvmx_pow_qos_rndx_s cnf71xx;
};
union cvmx_pow_qos_thrx {
@@ -838,9 +653,6 @@
uint64_t reserved_57_63:7;
#endif
} cn31xx;
- struct cvmx_pow_qos_thrx_s cn38xx;
- struct cvmx_pow_qos_thrx_s cn38xxp2;
- struct cvmx_pow_qos_thrx_cn31xx cn50xx;
struct cvmx_pow_qos_thrx_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_58_63:6;
@@ -866,12 +678,6 @@
uint64_t reserved_58_63:6;
#endif
} cn52xx;
- struct cvmx_pow_qos_thrx_cn52xx cn52xxp1;
- struct cvmx_pow_qos_thrx_s cn56xx;
- struct cvmx_pow_qos_thrx_s cn56xxp1;
- struct cvmx_pow_qos_thrx_s cn58xx;
- struct cvmx_pow_qos_thrx_s cn58xxp1;
- struct cvmx_pow_qos_thrx_cn52xx cn61xx;
struct cvmx_pow_qos_thrx_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_59_63:5;
@@ -897,9 +703,6 @@
uint64_t reserved_59_63:5;
#endif
} cn63xx;
- struct cvmx_pow_qos_thrx_cn63xx cn63xxp1;
- struct cvmx_pow_qos_thrx_cn63xx cn66xx;
- struct cvmx_pow_qos_thrx_cn52xx cnf71xx;
};
union cvmx_pow_ts_pc {
@@ -913,22 +716,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pow_ts_pc_s cn30xx;
- struct cvmx_pow_ts_pc_s cn31xx;
- struct cvmx_pow_ts_pc_s cn38xx;
- struct cvmx_pow_ts_pc_s cn38xxp2;
- struct cvmx_pow_ts_pc_s cn50xx;
- struct cvmx_pow_ts_pc_s cn52xx;
- struct cvmx_pow_ts_pc_s cn52xxp1;
- struct cvmx_pow_ts_pc_s cn56xx;
- struct cvmx_pow_ts_pc_s cn56xxp1;
- struct cvmx_pow_ts_pc_s cn58xx;
- struct cvmx_pow_ts_pc_s cn58xxp1;
- struct cvmx_pow_ts_pc_s cn61xx;
- struct cvmx_pow_ts_pc_s cn63xx;
- struct cvmx_pow_ts_pc_s cn63xxp1;
- struct cvmx_pow_ts_pc_s cn66xx;
- struct cvmx_pow_ts_pc_s cnf71xx;
};
union cvmx_pow_wa_com_pc {
@@ -942,22 +729,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pow_wa_com_pc_s cn30xx;
- struct cvmx_pow_wa_com_pc_s cn31xx;
- struct cvmx_pow_wa_com_pc_s cn38xx;
- struct cvmx_pow_wa_com_pc_s cn38xxp2;
- struct cvmx_pow_wa_com_pc_s cn50xx;
- struct cvmx_pow_wa_com_pc_s cn52xx;
- struct cvmx_pow_wa_com_pc_s cn52xxp1;
- struct cvmx_pow_wa_com_pc_s cn56xx;
- struct cvmx_pow_wa_com_pc_s cn56xxp1;
- struct cvmx_pow_wa_com_pc_s cn58xx;
- struct cvmx_pow_wa_com_pc_s cn58xxp1;
- struct cvmx_pow_wa_com_pc_s cn61xx;
- struct cvmx_pow_wa_com_pc_s cn63xx;
- struct cvmx_pow_wa_com_pc_s cn63xxp1;
- struct cvmx_pow_wa_com_pc_s cn66xx;
- struct cvmx_pow_wa_com_pc_s cnf71xx;
};
union cvmx_pow_wa_pcx {
@@ -971,22 +742,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pow_wa_pcx_s cn30xx;
- struct cvmx_pow_wa_pcx_s cn31xx;
- struct cvmx_pow_wa_pcx_s cn38xx;
- struct cvmx_pow_wa_pcx_s cn38xxp2;
- struct cvmx_pow_wa_pcx_s cn50xx;
- struct cvmx_pow_wa_pcx_s cn52xx;
- struct cvmx_pow_wa_pcx_s cn52xxp1;
- struct cvmx_pow_wa_pcx_s cn56xx;
- struct cvmx_pow_wa_pcx_s cn56xxp1;
- struct cvmx_pow_wa_pcx_s cn58xx;
- struct cvmx_pow_wa_pcx_s cn58xxp1;
- struct cvmx_pow_wa_pcx_s cn61xx;
- struct cvmx_pow_wa_pcx_s cn63xx;
- struct cvmx_pow_wa_pcx_s cn63xxp1;
- struct cvmx_pow_wa_pcx_s cn66xx;
- struct cvmx_pow_wa_pcx_s cnf71xx;
};
union cvmx_pow_wq_int {
@@ -1002,22 +757,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pow_wq_int_s cn30xx;
- struct cvmx_pow_wq_int_s cn31xx;
- struct cvmx_pow_wq_int_s cn38xx;
- struct cvmx_pow_wq_int_s cn38xxp2;
- struct cvmx_pow_wq_int_s cn50xx;
- struct cvmx_pow_wq_int_s cn52xx;
- struct cvmx_pow_wq_int_s cn52xxp1;
- struct cvmx_pow_wq_int_s cn56xx;
- struct cvmx_pow_wq_int_s cn56xxp1;
- struct cvmx_pow_wq_int_s cn58xx;
- struct cvmx_pow_wq_int_s cn58xxp1;
- struct cvmx_pow_wq_int_s cn61xx;
- struct cvmx_pow_wq_int_s cn63xx;
- struct cvmx_pow_wq_int_s cn63xxp1;
- struct cvmx_pow_wq_int_s cn66xx;
- struct cvmx_pow_wq_int_s cnf71xx;
};
union cvmx_pow_wq_int_cntx {
@@ -1069,9 +808,6 @@
uint64_t reserved_28_63:36;
#endif
} cn31xx;
- struct cvmx_pow_wq_int_cntx_s cn38xx;
- struct cvmx_pow_wq_int_cntx_s cn38xxp2;
- struct cvmx_pow_wq_int_cntx_cn31xx cn50xx;
struct cvmx_pow_wq_int_cntx_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
@@ -1089,12 +825,6 @@
uint64_t reserved_28_63:36;
#endif
} cn52xx;
- struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1;
- struct cvmx_pow_wq_int_cntx_s cn56xx;
- struct cvmx_pow_wq_int_cntx_s cn56xxp1;
- struct cvmx_pow_wq_int_cntx_s cn58xx;
- struct cvmx_pow_wq_int_cntx_s cn58xxp1;
- struct cvmx_pow_wq_int_cntx_cn52xx cn61xx;
struct cvmx_pow_wq_int_cntx_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_28_63:36;
@@ -1112,9 +842,6 @@
uint64_t reserved_28_63:36;
#endif
} cn63xx;
- struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;
- struct cvmx_pow_wq_int_cntx_cn63xx cn66xx;
- struct cvmx_pow_wq_int_cntx_cn52xx cnf71xx;
};
union cvmx_pow_wq_int_pc {
@@ -1134,22 +861,6 @@
uint64_t reserved_60_63:4;
#endif
} s;
- struct cvmx_pow_wq_int_pc_s cn30xx;
- struct cvmx_pow_wq_int_pc_s cn31xx;
- struct cvmx_pow_wq_int_pc_s cn38xx;
- struct cvmx_pow_wq_int_pc_s cn38xxp2;
- struct cvmx_pow_wq_int_pc_s cn50xx;
- struct cvmx_pow_wq_int_pc_s cn52xx;
- struct cvmx_pow_wq_int_pc_s cn52xxp1;
- struct cvmx_pow_wq_int_pc_s cn56xx;
- struct cvmx_pow_wq_int_pc_s cn56xxp1;
- struct cvmx_pow_wq_int_pc_s cn58xx;
- struct cvmx_pow_wq_int_pc_s cn58xxp1;
- struct cvmx_pow_wq_int_pc_s cn61xx;
- struct cvmx_pow_wq_int_pc_s cn63xx;
- struct cvmx_pow_wq_int_pc_s cn63xxp1;
- struct cvmx_pow_wq_int_pc_s cn66xx;
- struct cvmx_pow_wq_int_pc_s cnf71xx;
};
union cvmx_pow_wq_int_thrx {
@@ -1211,9 +922,6 @@
uint64_t reserved_29_63:35;
#endif
} cn31xx;
- struct cvmx_pow_wq_int_thrx_s cn38xx;
- struct cvmx_pow_wq_int_thrx_s cn38xxp2;
- struct cvmx_pow_wq_int_thrx_cn31xx cn50xx;
struct cvmx_pow_wq_int_thrx_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
@@ -1233,12 +941,6 @@
uint64_t reserved_29_63:35;
#endif
} cn52xx;
- struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1;
- struct cvmx_pow_wq_int_thrx_s cn56xx;
- struct cvmx_pow_wq_int_thrx_s cn56xxp1;
- struct cvmx_pow_wq_int_thrx_s cn58xx;
- struct cvmx_pow_wq_int_thrx_s cn58xxp1;
- struct cvmx_pow_wq_int_thrx_cn52xx cn61xx;
struct cvmx_pow_wq_int_thrx_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_29_63:35;
@@ -1258,9 +960,6 @@
uint64_t reserved_29_63:35;
#endif
} cn63xx;
- struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;
- struct cvmx_pow_wq_int_thrx_cn63xx cn66xx;
- struct cvmx_pow_wq_int_thrx_cn52xx cnf71xx;
};
union cvmx_pow_ws_pcx {
@@ -1274,22 +973,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_pow_ws_pcx_s cn30xx;
- struct cvmx_pow_ws_pcx_s cn31xx;
- struct cvmx_pow_ws_pcx_s cn38xx;
- struct cvmx_pow_ws_pcx_s cn38xxp2;
- struct cvmx_pow_ws_pcx_s cn50xx;
- struct cvmx_pow_ws_pcx_s cn52xx;
- struct cvmx_pow_ws_pcx_s cn52xxp1;
- struct cvmx_pow_ws_pcx_s cn56xx;
- struct cvmx_pow_ws_pcx_s cn56xxp1;
- struct cvmx_pow_ws_pcx_s cn58xx;
- struct cvmx_pow_ws_pcx_s cn58xxp1;
- struct cvmx_pow_ws_pcx_s cn61xx;
- struct cvmx_pow_ws_pcx_s cn63xx;
- struct cvmx_pow_ws_pcx_s cn63xxp1;
- struct cvmx_pow_ws_pcx_s cn66xx;
- struct cvmx_pow_ws_pcx_s cnf71xx;
};
union cvmx_sso_wq_int_thrx {
diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
index 87d6f92..94295d2 100644
--- a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
@@ -47,24 +47,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_rnm_bist_status_s cn30xx;
- struct cvmx_rnm_bist_status_s cn31xx;
- struct cvmx_rnm_bist_status_s cn38xx;
- struct cvmx_rnm_bist_status_s cn38xxp2;
- struct cvmx_rnm_bist_status_s cn50xx;
- struct cvmx_rnm_bist_status_s cn52xx;
- struct cvmx_rnm_bist_status_s cn52xxp1;
- struct cvmx_rnm_bist_status_s cn56xx;
- struct cvmx_rnm_bist_status_s cn56xxp1;
- struct cvmx_rnm_bist_status_s cn58xx;
- struct cvmx_rnm_bist_status_s cn58xxp1;
- struct cvmx_rnm_bist_status_s cn61xx;
- struct cvmx_rnm_bist_status_s cn63xx;
- struct cvmx_rnm_bist_status_s cn63xxp1;
- struct cvmx_rnm_bist_status_s cn66xx;
- struct cvmx_rnm_bist_status_s cn68xx;
- struct cvmx_rnm_bist_status_s cn68xxp1;
- struct cvmx_rnm_bist_status_s cnf71xx;
};
union cvmx_rnm_ctl_status {
@@ -109,9 +91,6 @@
uint64_t reserved_4_63:60;
#endif
} cn30xx;
- struct cvmx_rnm_ctl_status_cn30xx cn31xx;
- struct cvmx_rnm_ctl_status_cn30xx cn38xx;
- struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
struct cvmx_rnm_ctl_status_cn50xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_9_63:55;
@@ -131,13 +110,6 @@
uint64_t reserved_9_63:55;
#endif
} cn50xx;
- struct cvmx_rnm_ctl_status_cn50xx cn52xx;
- struct cvmx_rnm_ctl_status_cn50xx cn52xxp1;
- struct cvmx_rnm_ctl_status_cn50xx cn56xx;
- struct cvmx_rnm_ctl_status_cn50xx cn56xxp1;
- struct cvmx_rnm_ctl_status_cn50xx cn58xx;
- struct cvmx_rnm_ctl_status_cn50xx cn58xxp1;
- struct cvmx_rnm_ctl_status_s cn61xx;
struct cvmx_rnm_ctl_status_cn63xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_11_63:53;
@@ -161,11 +133,6 @@
uint64_t reserved_11_63:53;
#endif
} cn63xx;
- struct cvmx_rnm_ctl_status_cn63xx cn63xxp1;
- struct cvmx_rnm_ctl_status_s cn66xx;
- struct cvmx_rnm_ctl_status_cn63xx cn68xx;
- struct cvmx_rnm_ctl_status_cn63xx cn68xxp1;
- struct cvmx_rnm_ctl_status_s cnf71xx;
};
union cvmx_rnm_eer_dbg {
@@ -177,13 +144,6 @@
uint64_t dat:64;
#endif
} s;
- struct cvmx_rnm_eer_dbg_s cn61xx;
- struct cvmx_rnm_eer_dbg_s cn63xx;
- struct cvmx_rnm_eer_dbg_s cn63xxp1;
- struct cvmx_rnm_eer_dbg_s cn66xx;
- struct cvmx_rnm_eer_dbg_s cn68xx;
- struct cvmx_rnm_eer_dbg_s cn68xxp1;
- struct cvmx_rnm_eer_dbg_s cnf71xx;
};
union cvmx_rnm_eer_key {
@@ -195,13 +155,6 @@
uint64_t key:64;
#endif
} s;
- struct cvmx_rnm_eer_key_s cn61xx;
- struct cvmx_rnm_eer_key_s cn63xx;
- struct cvmx_rnm_eer_key_s cn63xxp1;
- struct cvmx_rnm_eer_key_s cn66xx;
- struct cvmx_rnm_eer_key_s cn68xx;
- struct cvmx_rnm_eer_key_s cn68xxp1;
- struct cvmx_rnm_eer_key_s cnf71xx;
};
union cvmx_rnm_serial_num {
@@ -213,12 +166,6 @@
uint64_t dat:64;
#endif
} s;
- struct cvmx_rnm_serial_num_s cn61xx;
- struct cvmx_rnm_serial_num_s cn63xx;
- struct cvmx_rnm_serial_num_s cn66xx;
- struct cvmx_rnm_serial_num_s cn68xx;
- struct cvmx_rnm_serial_num_s cn68xxp1;
- struct cvmx_rnm_serial_num_s cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-rst-defs.h b/arch/mips/include/asm/octeon/cvmx-rst-defs.h
index 0c9c3e7..accc997 100644
--- a/arch/mips/include/asm/octeon/cvmx-rst-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-rst-defs.h
@@ -80,9 +80,6 @@
uint64_t chipkill:1;
#endif
} s;
- struct cvmx_rst_boot_s cn70xx;
- struct cvmx_rst_boot_s cn70xxp1;
- struct cvmx_rst_boot_s cn78xx;
};
union cvmx_rst_cfg {
@@ -102,9 +99,6 @@
uint64_t bist_delay:58;
#endif
} s;
- struct cvmx_rst_cfg_s cn70xx;
- struct cvmx_rst_cfg_s cn70xxp1;
- struct cvmx_rst_cfg_s cn78xx;
};
union cvmx_rst_ckill {
@@ -118,9 +112,6 @@
uint64_t reserved_47_63:17;
#endif
} s;
- struct cvmx_rst_ckill_s cn70xx;
- struct cvmx_rst_ckill_s cn70xxp1;
- struct cvmx_rst_ckill_s cn78xx;
};
union cvmx_rst_ctlx {
@@ -150,9 +141,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_rst_ctlx_s cn70xx;
- struct cvmx_rst_ctlx_s cn70xxp1;
- struct cvmx_rst_ctlx_s cn78xx;
};
union cvmx_rst_delay {
@@ -168,9 +156,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_rst_delay_s cn70xx;
- struct cvmx_rst_delay_s cn70xxp1;
- struct cvmx_rst_delay_s cn78xx;
};
union cvmx_rst_eco {
@@ -184,7 +169,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_rst_eco_s cn78xx;
};
union cvmx_rst_int {
@@ -215,8 +199,6 @@
uint64_t reserved_11_63:53;
#endif
} cn70xx;
- struct cvmx_rst_int_cn70xx cn70xxp1;
- struct cvmx_rst_int_s cn78xx;
};
union cvmx_rst_ocx {
@@ -230,7 +212,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_rst_ocx_s cn78xx;
};
union cvmx_rst_power_dbg {
@@ -244,7 +225,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_rst_power_dbg_s cn78xx;
};
union cvmx_rst_pp_power {
@@ -267,8 +247,6 @@
uint64_t reserved_4_63:60;
#endif
} cn70xx;
- struct cvmx_rst_pp_power_cn70xx cn70xxp1;
- struct cvmx_rst_pp_power_s cn78xx;
};
union cvmx_rst_soft_prstx {
@@ -282,9 +260,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_rst_soft_prstx_s cn70xx;
- struct cvmx_rst_soft_prstx_s cn70xxp1;
- struct cvmx_rst_soft_prstx_s cn78xx;
};
union cvmx_rst_soft_rst {
@@ -298,9 +273,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_rst_soft_rst_s cn70xx;
- struct cvmx_rst_soft_rst_s cn70xxp1;
- struct cvmx_rst_soft_rst_s cn78xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
index 52cf96e..cbc7cda 100644
--- a/arch/mips/include/asm/octeon/cvmx-sli-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -46,6 +46,7 @@
case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
return 0x0000000000003CB0ull;
+ /* Else, fall through */
default:
return 0x0000000000023CB0ull;
}
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
deleted file mode 100644
index 8a278e6..0000000
--- a/arch/mips/include/asm/octeon/cvmx-smix-defs.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2012 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT. See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_SMIX_DEFS_H__
-#define __CVMX_SMIX_DEFS_H__
-
-static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128;
- }
- return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
-}
-
-static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128;
- }
- return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
-}
-
-static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128;
- }
- return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
-}
-
-static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128;
- }
- return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
-}
-
-static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
-{
- switch (cvmx_get_octeon_family()) {
- case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
- case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
- case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
- case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
- return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128;
- }
- return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
-}
-
-union cvmx_smix_clk {
- uint64_t u64;
- struct cvmx_smix_clk_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_25_63:39;
- uint64_t mode:1;
- uint64_t reserved_21_23:3;
- uint64_t sample_hi:5;
- uint64_t sample_mode:1;
- uint64_t reserved_14_14:1;
- uint64_t clk_idle:1;
- uint64_t preamble:1;
- uint64_t sample:4;
- uint64_t phase:8;
-#else
- uint64_t phase:8;
- uint64_t sample:4;
- uint64_t preamble:1;
- uint64_t clk_idle:1;
- uint64_t reserved_14_14:1;
- uint64_t sample_mode:1;
- uint64_t sample_hi:5;
- uint64_t reserved_21_23:3;
- uint64_t mode:1;
- uint64_t reserved_25_63:39;
-#endif
- } s;
- struct cvmx_smix_clk_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_21_63:43;
- uint64_t sample_hi:5;
- uint64_t sample_mode:1;
- uint64_t reserved_14_14:1;
- uint64_t clk_idle:1;
- uint64_t preamble:1;
- uint64_t sample:4;
- uint64_t phase:8;
-#else
- uint64_t phase:8;
- uint64_t sample:4;
- uint64_t preamble:1;
- uint64_t clk_idle:1;
- uint64_t reserved_14_14:1;
- uint64_t sample_mode:1;
- uint64_t sample_hi:5;
- uint64_t reserved_21_63:43;
-#endif
- } cn30xx;
- struct cvmx_smix_clk_cn30xx cn31xx;
- struct cvmx_smix_clk_cn30xx cn38xx;
- struct cvmx_smix_clk_cn30xx cn38xxp2;
- struct cvmx_smix_clk_s cn50xx;
- struct cvmx_smix_clk_s cn52xx;
- struct cvmx_smix_clk_s cn52xxp1;
- struct cvmx_smix_clk_s cn56xx;
- struct cvmx_smix_clk_s cn56xxp1;
- struct cvmx_smix_clk_cn30xx cn58xx;
- struct cvmx_smix_clk_cn30xx cn58xxp1;
- struct cvmx_smix_clk_s cn61xx;
- struct cvmx_smix_clk_s cn63xx;
- struct cvmx_smix_clk_s cn63xxp1;
- struct cvmx_smix_clk_s cn66xx;
- struct cvmx_smix_clk_s cn68xx;
- struct cvmx_smix_clk_s cn68xxp1;
- struct cvmx_smix_clk_s cnf71xx;
-};
-
-union cvmx_smix_cmd {
- uint64_t u64;
- struct cvmx_smix_cmd_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_18_63:46;
- uint64_t phy_op:2;
- uint64_t reserved_13_15:3;
- uint64_t phy_adr:5;
- uint64_t reserved_5_7:3;
- uint64_t reg_adr:5;
-#else
- uint64_t reg_adr:5;
- uint64_t reserved_5_7:3;
- uint64_t phy_adr:5;
- uint64_t reserved_13_15:3;
- uint64_t phy_op:2;
- uint64_t reserved_18_63:46;
-#endif
- } s;
- struct cvmx_smix_cmd_cn30xx {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_17_63:47;
- uint64_t phy_op:1;
- uint64_t reserved_13_15:3;
- uint64_t phy_adr:5;
- uint64_t reserved_5_7:3;
- uint64_t reg_adr:5;
-#else
- uint64_t reg_adr:5;
- uint64_t reserved_5_7:3;
- uint64_t phy_adr:5;
- uint64_t reserved_13_15:3;
- uint64_t phy_op:1;
- uint64_t reserved_17_63:47;
-#endif
- } cn30xx;
- struct cvmx_smix_cmd_cn30xx cn31xx;
- struct cvmx_smix_cmd_cn30xx cn38xx;
- struct cvmx_smix_cmd_cn30xx cn38xxp2;
- struct cvmx_smix_cmd_s cn50xx;
- struct cvmx_smix_cmd_s cn52xx;
- struct cvmx_smix_cmd_s cn52xxp1;
- struct cvmx_smix_cmd_s cn56xx;
- struct cvmx_smix_cmd_s cn56xxp1;
- struct cvmx_smix_cmd_cn30xx cn58xx;
- struct cvmx_smix_cmd_cn30xx cn58xxp1;
- struct cvmx_smix_cmd_s cn61xx;
- struct cvmx_smix_cmd_s cn63xx;
- struct cvmx_smix_cmd_s cn63xxp1;
- struct cvmx_smix_cmd_s cn66xx;
- struct cvmx_smix_cmd_s cn68xx;
- struct cvmx_smix_cmd_s cn68xxp1;
- struct cvmx_smix_cmd_s cnf71xx;
-};
-
-union cvmx_smix_en {
- uint64_t u64;
- struct cvmx_smix_en_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_1_63:63;
- uint64_t en:1;
-#else
- uint64_t en:1;
- uint64_t reserved_1_63:63;
-#endif
- } s;
- struct cvmx_smix_en_s cn30xx;
- struct cvmx_smix_en_s cn31xx;
- struct cvmx_smix_en_s cn38xx;
- struct cvmx_smix_en_s cn38xxp2;
- struct cvmx_smix_en_s cn50xx;
- struct cvmx_smix_en_s cn52xx;
- struct cvmx_smix_en_s cn52xxp1;
- struct cvmx_smix_en_s cn56xx;
- struct cvmx_smix_en_s cn56xxp1;
- struct cvmx_smix_en_s cn58xx;
- struct cvmx_smix_en_s cn58xxp1;
- struct cvmx_smix_en_s cn61xx;
- struct cvmx_smix_en_s cn63xx;
- struct cvmx_smix_en_s cn63xxp1;
- struct cvmx_smix_en_s cn66xx;
- struct cvmx_smix_en_s cn68xx;
- struct cvmx_smix_en_s cn68xxp1;
- struct cvmx_smix_en_s cnf71xx;
-};
-
-union cvmx_smix_rd_dat {
- uint64_t u64;
- struct cvmx_smix_rd_dat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_18_63:46;
- uint64_t pending:1;
- uint64_t val:1;
- uint64_t dat:16;
-#else
- uint64_t dat:16;
- uint64_t val:1;
- uint64_t pending:1;
- uint64_t reserved_18_63:46;
-#endif
- } s;
- struct cvmx_smix_rd_dat_s cn30xx;
- struct cvmx_smix_rd_dat_s cn31xx;
- struct cvmx_smix_rd_dat_s cn38xx;
- struct cvmx_smix_rd_dat_s cn38xxp2;
- struct cvmx_smix_rd_dat_s cn50xx;
- struct cvmx_smix_rd_dat_s cn52xx;
- struct cvmx_smix_rd_dat_s cn52xxp1;
- struct cvmx_smix_rd_dat_s cn56xx;
- struct cvmx_smix_rd_dat_s cn56xxp1;
- struct cvmx_smix_rd_dat_s cn58xx;
- struct cvmx_smix_rd_dat_s cn58xxp1;
- struct cvmx_smix_rd_dat_s cn61xx;
- struct cvmx_smix_rd_dat_s cn63xx;
- struct cvmx_smix_rd_dat_s cn63xxp1;
- struct cvmx_smix_rd_dat_s cn66xx;
- struct cvmx_smix_rd_dat_s cn68xx;
- struct cvmx_smix_rd_dat_s cn68xxp1;
- struct cvmx_smix_rd_dat_s cnf71xx;
-};
-
-union cvmx_smix_wr_dat {
- uint64_t u64;
- struct cvmx_smix_wr_dat_s {
-#ifdef __BIG_ENDIAN_BITFIELD
- uint64_t reserved_18_63:46;
- uint64_t pending:1;
- uint64_t val:1;
- uint64_t dat:16;
-#else
- uint64_t dat:16;
- uint64_t val:1;
- uint64_t pending:1;
- uint64_t reserved_18_63:46;
-#endif
- } s;
- struct cvmx_smix_wr_dat_s cn30xx;
- struct cvmx_smix_wr_dat_s cn31xx;
- struct cvmx_smix_wr_dat_s cn38xx;
- struct cvmx_smix_wr_dat_s cn38xxp2;
- struct cvmx_smix_wr_dat_s cn50xx;
- struct cvmx_smix_wr_dat_s cn52xx;
- struct cvmx_smix_wr_dat_s cn52xxp1;
- struct cvmx_smix_wr_dat_s cn56xx;
- struct cvmx_smix_wr_dat_s cn56xxp1;
- struct cvmx_smix_wr_dat_s cn58xx;
- struct cvmx_smix_wr_dat_s cn58xxp1;
- struct cvmx_smix_wr_dat_s cn61xx;
- struct cvmx_smix_wr_dat_s cn63xx;
- struct cvmx_smix_wr_dat_s cn63xxp1;
- struct cvmx_smix_wr_dat_s cn66xx;
- struct cvmx_smix_wr_dat_s cn68xx;
- struct cvmx_smix_wr_dat_s cn68xxp1;
- struct cvmx_smix_wr_dat_s cnf71xx;
-};
-
-#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
index f4c4e80..8471ed2 100644
--- a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
@@ -58,10 +58,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_spxx_bckprs_cnt_s cn38xx;
- struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
- struct cvmx_spxx_bckprs_cnt_s cn58xx;
- struct cvmx_spxx_bckprs_cnt_s cn58xxp1;
};
union cvmx_spxx_bist_stat {
@@ -79,10 +75,6 @@
uint64_t reserved_3_63:61;
#endif
} s;
- struct cvmx_spxx_bist_stat_s cn38xx;
- struct cvmx_spxx_bist_stat_s cn38xxp2;
- struct cvmx_spxx_bist_stat_s cn58xx;
- struct cvmx_spxx_bist_stat_s cn58xxp1;
};
union cvmx_spxx_clk_ctl {
@@ -114,10 +106,6 @@
uint64_t reserved_17_63:47;
#endif
} s;
- struct cvmx_spxx_clk_ctl_s cn38xx;
- struct cvmx_spxx_clk_ctl_s cn38xxp2;
- struct cvmx_spxx_clk_ctl_s cn58xx;
- struct cvmx_spxx_clk_ctl_s cn58xxp1;
};
union cvmx_spxx_clk_stat {
@@ -145,10 +133,6 @@
uint64_t reserved_11_63:53;
#endif
} s;
- struct cvmx_spxx_clk_stat_s cn38xx;
- struct cvmx_spxx_clk_stat_s cn38xxp2;
- struct cvmx_spxx_clk_stat_s cn58xx;
- struct cvmx_spxx_clk_stat_s cn58xxp1;
};
union cvmx_spxx_dbg_deskew_ctl {
@@ -190,10 +174,6 @@
uint64_t reserved_30_63:34;
#endif
} s;
- struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
- struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
- struct cvmx_spxx_dbg_deskew_ctl_s cn58xx;
- struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1;
};
union cvmx_spxx_dbg_deskew_state {
@@ -213,10 +193,6 @@
uint64_t reserved_9_63:55;
#endif
} s;
- struct cvmx_spxx_dbg_deskew_state_s cn38xx;
- struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
- struct cvmx_spxx_dbg_deskew_state_s cn58xx;
- struct cvmx_spxx_dbg_deskew_state_s cn58xxp1;
};
union cvmx_spxx_drv_ctl {
@@ -241,7 +217,6 @@
uint64_t reserved_16_63:48;
#endif
} cn38xx;
- struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
struct cvmx_spxx_drv_ctl_cn58xx {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_24_63:40;
@@ -257,7 +232,6 @@
uint64_t reserved_24_63:40;
#endif
} cn58xx;
- struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
};
union cvmx_spxx_err_ctl {
@@ -279,10 +253,6 @@
uint64_t reserved_9_63:55;
#endif
} s;
- struct cvmx_spxx_err_ctl_s cn38xx;
- struct cvmx_spxx_err_ctl_s cn38xxp2;
- struct cvmx_spxx_err_ctl_s cn58xx;
- struct cvmx_spxx_err_ctl_s cn58xxp1;
};
union cvmx_spxx_int_dat {
@@ -304,10 +274,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_spxx_int_dat_s cn38xx;
- struct cvmx_spxx_int_dat_s cn38xxp2;
- struct cvmx_spxx_int_dat_s cn58xx;
- struct cvmx_spxx_int_dat_s cn58xxp1;
};
union cvmx_spxx_int_msk {
@@ -341,10 +307,6 @@
uint64_t reserved_12_63:52;
#endif
} s;
- struct cvmx_spxx_int_msk_s cn38xx;
- struct cvmx_spxx_int_msk_s cn38xxp2;
- struct cvmx_spxx_int_msk_s cn58xx;
- struct cvmx_spxx_int_msk_s cn58xxp1;
};
union cvmx_spxx_int_reg {
@@ -382,10 +344,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_spxx_int_reg_s cn38xx;
- struct cvmx_spxx_int_reg_s cn38xxp2;
- struct cvmx_spxx_int_reg_s cn58xx;
- struct cvmx_spxx_int_reg_s cn58xxp1;
};
union cvmx_spxx_int_sync {
@@ -419,10 +377,6 @@
uint64_t reserved_12_63:52;
#endif
} s;
- struct cvmx_spxx_int_sync_s cn38xx;
- struct cvmx_spxx_int_sync_s cn38xxp2;
- struct cvmx_spxx_int_sync_s cn58xx;
- struct cvmx_spxx_int_sync_s cn58xxp1;
};
union cvmx_spxx_tpa_acc {
@@ -436,10 +390,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_spxx_tpa_acc_s cn38xx;
- struct cvmx_spxx_tpa_acc_s cn38xxp2;
- struct cvmx_spxx_tpa_acc_s cn58xx;
- struct cvmx_spxx_tpa_acc_s cn58xxp1;
};
union cvmx_spxx_tpa_max {
@@ -453,10 +403,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_spxx_tpa_max_s cn38xx;
- struct cvmx_spxx_tpa_max_s cn38xxp2;
- struct cvmx_spxx_tpa_max_s cn58xx;
- struct cvmx_spxx_tpa_max_s cn58xxp1;
};
union cvmx_spxx_tpa_sel {
@@ -470,10 +416,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_spxx_tpa_sel_s cn38xx;
- struct cvmx_spxx_tpa_sel_s cn38xxp2;
- struct cvmx_spxx_tpa_sel_s cn58xx;
- struct cvmx_spxx_tpa_sel_s cn58xxp1;
};
union cvmx_spxx_trn4_ctl {
@@ -499,10 +441,6 @@
uint64_t reserved_13_63:51;
#endif
} s;
- struct cvmx_spxx_trn4_ctl_s cn38xx;
- struct cvmx_spxx_trn4_ctl_s cn38xxp2;
- struct cvmx_spxx_trn4_ctl_s cn58xx;
- struct cvmx_spxx_trn4_ctl_s cn58xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
index 5140f2d..34d0fad 100644
--- a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
@@ -112,8 +112,6 @@
uint64_t reserved_3_63:61;
#endif
} cn63xx;
- struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
- struct cvmx_sriox_acc_ctrl_s cn66xx;
};
union cvmx_sriox_asmbly_id {
@@ -129,9 +127,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_sriox_asmbly_id_s cn63xx;
- struct cvmx_sriox_asmbly_id_s cn63xxp1;
- struct cvmx_sriox_asmbly_id_s cn66xx;
};
union cvmx_sriox_asmbly_info {
@@ -147,9 +142,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_sriox_asmbly_info_s cn63xx;
- struct cvmx_sriox_asmbly_info_s cn63xxp1;
- struct cvmx_sriox_asmbly_info_s cn66xx;
};
union cvmx_sriox_bell_resp_ctrl {
@@ -169,9 +161,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
- struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
- struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
};
union cvmx_sriox_bist_status {
@@ -305,7 +294,6 @@
uint64_t reserved_44_63:20;
#endif
} cn63xxp1;
- struct cvmx_sriox_bist_status_s cn66xx;
};
union cvmx_sriox_imsg_ctrl {
@@ -343,9 +331,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_sriox_imsg_ctrl_s cn63xx;
- struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
- struct cvmx_sriox_imsg_ctrl_s cn66xx;
};
union cvmx_sriox_imsg_inst_hdrx {
@@ -383,9 +368,6 @@
uint64_t r:1;
#endif
} s;
- struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
- struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
- struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
};
union cvmx_sriox_imsg_qos_grpx {
@@ -443,9 +425,6 @@
uint64_t reserved_63_63:1;
#endif
} s;
- struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
- struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
- struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
};
union cvmx_sriox_imsg_statusx {
@@ -503,9 +482,6 @@
uint64_t val1:1;
#endif
} s;
- struct cvmx_sriox_imsg_statusx_s cn63xx;
- struct cvmx_sriox_imsg_statusx_s cn63xxp1;
- struct cvmx_sriox_imsg_statusx_s cn66xx;
};
union cvmx_sriox_imsg_vport_thr {
@@ -541,9 +517,6 @@
uint64_t reserved_54_63:10;
#endif
} s;
- struct cvmx_sriox_imsg_vport_thr_s cn63xx;
- struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
- struct cvmx_sriox_imsg_vport_thr_s cn66xx;
};
union cvmx_sriox_imsg_vport_thr2 {
@@ -563,7 +536,6 @@
uint64_t reserved_46_63:18;
#endif
} s;
- struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
};
union cvmx_sriox_int2_enable {
@@ -577,8 +549,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_sriox_int2_enable_s cn63xx;
- struct cvmx_sriox_int2_enable_s cn66xx;
};
union cvmx_sriox_int2_reg {
@@ -596,8 +566,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_sriox_int2_reg_s cn63xx;
- struct cvmx_sriox_int2_reg_s cn66xx;
};
union cvmx_sriox_int_enable {
@@ -663,7 +631,6 @@
uint64_t reserved_27_63:37;
#endif
} s;
- struct cvmx_sriox_int_enable_s cn63xx;
struct cvmx_sriox_int_enable_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_22_63:42;
@@ -715,7 +682,6 @@
uint64_t reserved_22_63:42;
#endif
} cn63xxp1;
- struct cvmx_sriox_int_enable_s cn66xx;
};
union cvmx_sriox_int_info0 {
@@ -743,9 +709,6 @@
uint64_t cmd:4;
#endif
} s;
- struct cvmx_sriox_int_info0_s cn63xx;
- struct cvmx_sriox_int_info0_s cn63xxp1;
- struct cvmx_sriox_int_info0_s cn66xx;
};
union cvmx_sriox_int_info1 {
@@ -757,9 +720,6 @@
uint64_t info1:64;
#endif
} s;
- struct cvmx_sriox_int_info1_s cn63xx;
- struct cvmx_sriox_int_info1_s cn63xxp1;
- struct cvmx_sriox_int_info1_s cn66xx;
};
union cvmx_sriox_int_info2 {
@@ -791,9 +751,6 @@
uint64_t prio:2;
#endif
} s;
- struct cvmx_sriox_int_info2_s cn63xx;
- struct cvmx_sriox_int_info2_s cn63xxp1;
- struct cvmx_sriox_int_info2_s cn66xx;
};
union cvmx_sriox_int_info3 {
@@ -813,9 +770,6 @@
uint64_t prio:2;
#endif
} s;
- struct cvmx_sriox_int_info3_s cn63xx;
- struct cvmx_sriox_int_info3_s cn63xxp1;
- struct cvmx_sriox_int_info3_s cn66xx;
};
union cvmx_sriox_int_reg {
@@ -885,7 +839,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_sriox_int_reg_s cn63xx;
struct cvmx_sriox_int_reg_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t reserved_22_63:42;
@@ -937,7 +890,6 @@
uint64_t reserved_22_63:42;
#endif
} cn63xxp1;
- struct cvmx_sriox_int_reg_s cn66xx;
};
union cvmx_sriox_ip_feature {
@@ -990,8 +942,6 @@
uint64_t ops:32;
#endif
} cn63xx;
- struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
- struct cvmx_sriox_ip_feature_s cn66xx;
};
union cvmx_sriox_mac_buffers {
@@ -1021,8 +971,6 @@
uint64_t reserved_56_63:8;
#endif
} s;
- struct cvmx_sriox_mac_buffers_s cn63xx;
- struct cvmx_sriox_mac_buffers_s cn66xx;
};
union cvmx_sriox_maint_op {
@@ -1044,9 +992,6 @@
uint64_t wr_data:32;
#endif
} s;
- struct cvmx_sriox_maint_op_s cn63xx;
- struct cvmx_sriox_maint_op_s cn63xxp1;
- struct cvmx_sriox_maint_op_s cn66xx;
};
union cvmx_sriox_maint_rd_data {
@@ -1062,9 +1007,6 @@
uint64_t reserved_33_63:31;
#endif
} s;
- struct cvmx_sriox_maint_rd_data_s cn63xx;
- struct cvmx_sriox_maint_rd_data_s cn63xxp1;
- struct cvmx_sriox_maint_rd_data_s cn66xx;
};
union cvmx_sriox_mce_tx_ctl {
@@ -1078,9 +1020,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_sriox_mce_tx_ctl_s cn63xx;
- struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
- struct cvmx_sriox_mce_tx_ctl_s cn66xx;
};
union cvmx_sriox_mem_op_ctrl {
@@ -1106,9 +1045,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_sriox_mem_op_ctrl_s cn63xx;
- struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
- struct cvmx_sriox_mem_op_ctrl_s cn66xx;
};
union cvmx_sriox_omsg_ctrlx {
@@ -1140,7 +1076,6 @@
uint64_t testmode:1;
#endif
} s;
- struct cvmx_sriox_omsg_ctrlx_s cn63xx;
struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
uint64_t testmode:1;
@@ -1166,7 +1101,6 @@
uint64_t testmode:1;
#endif
} cn63xxp1;
- struct cvmx_sriox_omsg_ctrlx_s cn66xx;
};
union cvmx_sriox_omsg_done_countsx {
@@ -1182,8 +1116,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_sriox_omsg_done_countsx_s cn63xx;
- struct cvmx_sriox_omsg_done_countsx_s cn66xx;
};
union cvmx_sriox_omsg_fmp_mrx {
@@ -1225,9 +1157,6 @@
uint64_t reserved_15_63:49;
#endif
} s;
- struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
- struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
- struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
};
union cvmx_sriox_omsg_nmp_mrx {
@@ -1269,9 +1198,6 @@
uint64_t reserved_15_63:49;
#endif
} s;
- struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
- struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
- struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
};
union cvmx_sriox_omsg_portx {
@@ -1302,8 +1228,6 @@
uint64_t reserved_32_63:32;
#endif
} cn63xx;
- struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
- struct cvmx_sriox_omsg_portx_s cn66xx;
};
union cvmx_sriox_omsg_silo_thr {
@@ -1317,8 +1241,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_sriox_omsg_silo_thr_s cn63xx;
- struct cvmx_sriox_omsg_silo_thr_s cn66xx;
};
union cvmx_sriox_omsg_sp_mrx {
@@ -1362,9 +1284,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
- struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
- struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
};
union cvmx_sriox_priox_in_use {
@@ -1380,8 +1299,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_sriox_priox_in_use_s cn63xx;
- struct cvmx_sriox_priox_in_use_s cn66xx;
};
union cvmx_sriox_rx_bell {
@@ -1409,9 +1326,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_sriox_rx_bell_s cn63xx;
- struct cvmx_sriox_rx_bell_s cn63xxp1;
- struct cvmx_sriox_rx_bell_s cn66xx;
};
union cvmx_sriox_rx_bell_seq {
@@ -1427,9 +1341,6 @@
uint64_t reserved_40_63:24;
#endif
} s;
- struct cvmx_sriox_rx_bell_seq_s cn63xx;
- struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
- struct cvmx_sriox_rx_bell_seq_s cn66xx;
};
union cvmx_sriox_rx_status {
@@ -1457,9 +1368,6 @@
uint64_t rtn_pr3:8;
#endif
} s;
- struct cvmx_sriox_rx_status_s cn63xx;
- struct cvmx_sriox_rx_status_s cn63xxp1;
- struct cvmx_sriox_rx_status_s cn66xx;
};
union cvmx_sriox_s2m_typex {
@@ -1491,9 +1399,6 @@
uint64_t reserved_19_63:45;
#endif
} s;
- struct cvmx_sriox_s2m_typex_s cn63xx;
- struct cvmx_sriox_s2m_typex_s cn63xxp1;
- struct cvmx_sriox_s2m_typex_s cn66xx;
};
union cvmx_sriox_seq {
@@ -1507,9 +1412,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_sriox_seq_s cn63xx;
- struct cvmx_sriox_seq_s cn63xxp1;
- struct cvmx_sriox_seq_s cn66xx;
};
union cvmx_sriox_status_reg {
@@ -1525,9 +1427,6 @@
uint64_t reserved_2_63:62;
#endif
} s;
- struct cvmx_sriox_status_reg_s cn63xx;
- struct cvmx_sriox_status_reg_s cn63xxp1;
- struct cvmx_sriox_status_reg_s cn66xx;
};
union cvmx_sriox_tag_ctrl {
@@ -1549,9 +1448,6 @@
uint64_t reserved_17_63:47;
#endif
} s;
- struct cvmx_sriox_tag_ctrl_s cn63xx;
- struct cvmx_sriox_tag_ctrl_s cn63xxp1;
- struct cvmx_sriox_tag_ctrl_s cn66xx;
};
union cvmx_sriox_tlp_credits {
@@ -1573,9 +1469,6 @@
uint64_t reserved_28_63:36;
#endif
} s;
- struct cvmx_sriox_tlp_credits_s cn63xx;
- struct cvmx_sriox_tlp_credits_s cn63xxp1;
- struct cvmx_sriox_tlp_credits_s cn66xx;
};
union cvmx_sriox_tx_bell {
@@ -1605,9 +1498,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_sriox_tx_bell_s cn63xx;
- struct cvmx_sriox_tx_bell_s cn63xxp1;
- struct cvmx_sriox_tx_bell_s cn66xx;
};
union cvmx_sriox_tx_bell_info {
@@ -1639,9 +1529,6 @@
uint64_t reserved_48_63:16;
#endif
} s;
- struct cvmx_sriox_tx_bell_info_s cn63xx;
- struct cvmx_sriox_tx_bell_info_s cn63xxp1;
- struct cvmx_sriox_tx_bell_info_s cn66xx;
};
union cvmx_sriox_tx_ctrl {
@@ -1675,9 +1562,6 @@
uint64_t reserved_53_63:11;
#endif
} s;
- struct cvmx_sriox_tx_ctrl_s cn63xx;
- struct cvmx_sriox_tx_ctrl_s cn63xxp1;
- struct cvmx_sriox_tx_ctrl_s cn66xx;
};
union cvmx_sriox_tx_emphasis {
@@ -1691,8 +1575,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_sriox_tx_emphasis_s cn63xx;
- struct cvmx_sriox_tx_emphasis_s cn66xx;
};
union cvmx_sriox_tx_status {
@@ -1712,9 +1594,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_sriox_tx_status_s cn63xx;
- struct cvmx_sriox_tx_status_s cn63xxp1;
- struct cvmx_sriox_tx_status_s cn66xx;
};
union cvmx_sriox_wr_done_counts {
@@ -1730,8 +1609,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_sriox_wr_done_counts_s cn63xx;
- struct cvmx_sriox_wr_done_counts_s cn66xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
index c98e625..76b2a42 100644
--- a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
@@ -52,10 +52,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_srxx_com_ctl_s cn38xx;
- struct cvmx_srxx_com_ctl_s cn38xxp2;
- struct cvmx_srxx_com_ctl_s cn58xx;
- struct cvmx_srxx_com_ctl_s cn58xxp1;
};
union cvmx_srxx_ign_rx_full {
@@ -69,10 +65,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_srxx_ign_rx_full_s cn38xx;
- struct cvmx_srxx_ign_rx_full_s cn38xxp2;
- struct cvmx_srxx_ign_rx_full_s cn58xx;
- struct cvmx_srxx_ign_rx_full_s cn58xxp1;
};
union cvmx_srxx_spi4_calx {
@@ -94,10 +86,6 @@
uint64_t reserved_17_63:47;
#endif
} s;
- struct cvmx_srxx_spi4_calx_s cn38xx;
- struct cvmx_srxx_spi4_calx_s cn38xxp2;
- struct cvmx_srxx_spi4_calx_s cn58xx;
- struct cvmx_srxx_spi4_calx_s cn58xxp1;
};
union cvmx_srxx_spi4_stat {
@@ -115,10 +103,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_srxx_spi4_stat_s cn38xx;
- struct cvmx_srxx_spi4_stat_s cn38xxp2;
- struct cvmx_srxx_spi4_stat_s cn58xx;
- struct cvmx_srxx_spi4_stat_s cn58xxp1;
};
union cvmx_srxx_sw_tick_ctl {
@@ -140,9 +124,6 @@
uint64_t reserved_14_63:50;
#endif
} s;
- struct cvmx_srxx_sw_tick_ctl_s cn38xx;
- struct cvmx_srxx_sw_tick_ctl_s cn58xx;
- struct cvmx_srxx_sw_tick_ctl_s cn58xxp1;
};
union cvmx_srxx_sw_tick_dat {
@@ -154,9 +135,6 @@
uint64_t dat:64;
#endif
} s;
- struct cvmx_srxx_sw_tick_dat_s cn38xx;
- struct cvmx_srxx_sw_tick_dat_s cn58xx;
- struct cvmx_srxx_sw_tick_dat_s cn58xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
index 3c409a8..f49d821 100644
--- a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
@@ -64,10 +64,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_stxx_arb_ctl_s cn38xx;
- struct cvmx_stxx_arb_ctl_s cn38xxp2;
- struct cvmx_stxx_arb_ctl_s cn58xx;
- struct cvmx_stxx_arb_ctl_s cn58xxp1;
};
union cvmx_stxx_bckprs_cnt {
@@ -81,10 +77,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_stxx_bckprs_cnt_s cn38xx;
- struct cvmx_stxx_bckprs_cnt_s cn38xxp2;
- struct cvmx_stxx_bckprs_cnt_s cn58xx;
- struct cvmx_stxx_bckprs_cnt_s cn58xxp1;
};
union cvmx_stxx_com_ctl {
@@ -102,10 +94,6 @@
uint64_t reserved_4_63:60;
#endif
} s;
- struct cvmx_stxx_com_ctl_s cn38xx;
- struct cvmx_stxx_com_ctl_s cn38xxp2;
- struct cvmx_stxx_com_ctl_s cn58xx;
- struct cvmx_stxx_com_ctl_s cn58xxp1;
};
union cvmx_stxx_dip_cnt {
@@ -121,10 +109,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_stxx_dip_cnt_s cn38xx;
- struct cvmx_stxx_dip_cnt_s cn38xxp2;
- struct cvmx_stxx_dip_cnt_s cn58xx;
- struct cvmx_stxx_dip_cnt_s cn58xxp1;
};
union cvmx_stxx_ign_cal {
@@ -138,10 +122,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_stxx_ign_cal_s cn38xx;
- struct cvmx_stxx_ign_cal_s cn38xxp2;
- struct cvmx_stxx_ign_cal_s cn58xx;
- struct cvmx_stxx_ign_cal_s cn58xxp1;
};
union cvmx_stxx_int_msk {
@@ -169,10 +149,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_stxx_int_msk_s cn38xx;
- struct cvmx_stxx_int_msk_s cn38xxp2;
- struct cvmx_stxx_int_msk_s cn58xx;
- struct cvmx_stxx_int_msk_s cn58xxp1;
};
union cvmx_stxx_int_reg {
@@ -202,10 +178,6 @@
uint64_t reserved_9_63:55;
#endif
} s;
- struct cvmx_stxx_int_reg_s cn38xx;
- struct cvmx_stxx_int_reg_s cn38xxp2;
- struct cvmx_stxx_int_reg_s cn58xx;
- struct cvmx_stxx_int_reg_s cn58xxp1;
};
union cvmx_stxx_int_sync {
@@ -233,10 +205,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_stxx_int_sync_s cn38xx;
- struct cvmx_stxx_int_sync_s cn38xxp2;
- struct cvmx_stxx_int_sync_s cn58xx;
- struct cvmx_stxx_int_sync_s cn58xxp1;
};
union cvmx_stxx_min_bst {
@@ -250,10 +218,6 @@
uint64_t reserved_9_63:55;
#endif
} s;
- struct cvmx_stxx_min_bst_s cn38xx;
- struct cvmx_stxx_min_bst_s cn38xxp2;
- struct cvmx_stxx_min_bst_s cn58xx;
- struct cvmx_stxx_min_bst_s cn58xxp1;
};
union cvmx_stxx_spi4_calx {
@@ -275,10 +239,6 @@
uint64_t reserved_17_63:47;
#endif
} s;
- struct cvmx_stxx_spi4_calx_s cn38xx;
- struct cvmx_stxx_spi4_calx_s cn38xxp2;
- struct cvmx_stxx_spi4_calx_s cn58xx;
- struct cvmx_stxx_spi4_calx_s cn58xxp1;
};
union cvmx_stxx_spi4_dat {
@@ -294,10 +254,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_stxx_spi4_dat_s cn38xx;
- struct cvmx_stxx_spi4_dat_s cn38xxp2;
- struct cvmx_stxx_spi4_dat_s cn58xx;
- struct cvmx_stxx_spi4_dat_s cn58xxp1;
};
union cvmx_stxx_spi4_stat {
@@ -315,10 +271,6 @@
uint64_t reserved_16_63:48;
#endif
} s;
- struct cvmx_stxx_spi4_stat_s cn38xx;
- struct cvmx_stxx_spi4_stat_s cn38xxp2;
- struct cvmx_stxx_spi4_stat_s cn58xx;
- struct cvmx_stxx_spi4_stat_s cn58xxp1;
};
union cvmx_stxx_stat_bytes_hi {
@@ -332,10 +284,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_stxx_stat_bytes_hi_s cn38xx;
- struct cvmx_stxx_stat_bytes_hi_s cn38xxp2;
- struct cvmx_stxx_stat_bytes_hi_s cn58xx;
- struct cvmx_stxx_stat_bytes_hi_s cn58xxp1;
};
union cvmx_stxx_stat_bytes_lo {
@@ -349,10 +297,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_stxx_stat_bytes_lo_s cn38xx;
- struct cvmx_stxx_stat_bytes_lo_s cn38xxp2;
- struct cvmx_stxx_stat_bytes_lo_s cn58xx;
- struct cvmx_stxx_stat_bytes_lo_s cn58xxp1;
};
union cvmx_stxx_stat_ctl {
@@ -368,10 +312,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_stxx_stat_ctl_s cn38xx;
- struct cvmx_stxx_stat_ctl_s cn38xxp2;
- struct cvmx_stxx_stat_ctl_s cn58xx;
- struct cvmx_stxx_stat_ctl_s cn58xxp1;
};
union cvmx_stxx_stat_pkt_xmt {
@@ -385,10 +325,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_stxx_stat_pkt_xmt_s cn38xx;
- struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2;
- struct cvmx_stxx_stat_pkt_xmt_s cn58xx;
- struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
index bc5b80c..6cf2280 100644
--- a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
@@ -63,13 +63,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_uctlx_bist_status_s cn61xx;
- struct cvmx_uctlx_bist_status_s cn63xx;
- struct cvmx_uctlx_bist_status_s cn63xxp1;
- struct cvmx_uctlx_bist_status_s cn66xx;
- struct cvmx_uctlx_bist_status_s cn68xx;
- struct cvmx_uctlx_bist_status_s cn68xxp1;
- struct cvmx_uctlx_bist_status_s cnf71xx;
};
union cvmx_uctlx_clk_rst_ctl {
@@ -121,13 +114,6 @@
uint64_t reserved_25_63:39;
#endif
} s;
- struct cvmx_uctlx_clk_rst_ctl_s cn61xx;
- struct cvmx_uctlx_clk_rst_ctl_s cn63xx;
- struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1;
- struct cvmx_uctlx_clk_rst_ctl_s cn66xx;
- struct cvmx_uctlx_clk_rst_ctl_s cn68xx;
- struct cvmx_uctlx_clk_rst_ctl_s cn68xxp1;
- struct cvmx_uctlx_clk_rst_ctl_s cnf71xx;
};
union cvmx_uctlx_ehci_ctl {
@@ -161,13 +147,6 @@
uint64_t reserved_20_63:44;
#endif
} s;
- struct cvmx_uctlx_ehci_ctl_s cn61xx;
- struct cvmx_uctlx_ehci_ctl_s cn63xx;
- struct cvmx_uctlx_ehci_ctl_s cn63xxp1;
- struct cvmx_uctlx_ehci_ctl_s cn66xx;
- struct cvmx_uctlx_ehci_ctl_s cn68xx;
- struct cvmx_uctlx_ehci_ctl_s cn68xxp1;
- struct cvmx_uctlx_ehci_ctl_s cnf71xx;
};
union cvmx_uctlx_ehci_fla {
@@ -181,13 +160,6 @@
uint64_t reserved_6_63:58;
#endif
} s;
- struct cvmx_uctlx_ehci_fla_s cn61xx;
- struct cvmx_uctlx_ehci_fla_s cn63xx;
- struct cvmx_uctlx_ehci_fla_s cn63xxp1;
- struct cvmx_uctlx_ehci_fla_s cn66xx;
- struct cvmx_uctlx_ehci_fla_s cn68xx;
- struct cvmx_uctlx_ehci_fla_s cn68xxp1;
- struct cvmx_uctlx_ehci_fla_s cnf71xx;
};
union cvmx_uctlx_erto_ctl {
@@ -203,13 +175,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_uctlx_erto_ctl_s cn61xx;
- struct cvmx_uctlx_erto_ctl_s cn63xx;
- struct cvmx_uctlx_erto_ctl_s cn63xxp1;
- struct cvmx_uctlx_erto_ctl_s cn66xx;
- struct cvmx_uctlx_erto_ctl_s cn68xx;
- struct cvmx_uctlx_erto_ctl_s cn68xxp1;
- struct cvmx_uctlx_erto_ctl_s cnf71xx;
};
union cvmx_uctlx_if_ena {
@@ -223,13 +188,6 @@
uint64_t reserved_1_63:63;
#endif
} s;
- struct cvmx_uctlx_if_ena_s cn61xx;
- struct cvmx_uctlx_if_ena_s cn63xx;
- struct cvmx_uctlx_if_ena_s cn63xxp1;
- struct cvmx_uctlx_if_ena_s cn66xx;
- struct cvmx_uctlx_if_ena_s cn68xx;
- struct cvmx_uctlx_if_ena_s cn68xxp1;
- struct cvmx_uctlx_if_ena_s cnf71xx;
};
union cvmx_uctlx_int_ena {
@@ -257,13 +215,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_uctlx_int_ena_s cn61xx;
- struct cvmx_uctlx_int_ena_s cn63xx;
- struct cvmx_uctlx_int_ena_s cn63xxp1;
- struct cvmx_uctlx_int_ena_s cn66xx;
- struct cvmx_uctlx_int_ena_s cn68xx;
- struct cvmx_uctlx_int_ena_s cn68xxp1;
- struct cvmx_uctlx_int_ena_s cnf71xx;
};
union cvmx_uctlx_int_reg {
@@ -291,13 +242,6 @@
uint64_t reserved_8_63:56;
#endif
} s;
- struct cvmx_uctlx_int_reg_s cn61xx;
- struct cvmx_uctlx_int_reg_s cn63xx;
- struct cvmx_uctlx_int_reg_s cn63xxp1;
- struct cvmx_uctlx_int_reg_s cn66xx;
- struct cvmx_uctlx_int_reg_s cn68xx;
- struct cvmx_uctlx_int_reg_s cn68xxp1;
- struct cvmx_uctlx_int_reg_s cnf71xx;
};
union cvmx_uctlx_ohci_ctl {
@@ -329,13 +273,6 @@
uint64_t reserved_19_63:45;
#endif
} s;
- struct cvmx_uctlx_ohci_ctl_s cn61xx;
- struct cvmx_uctlx_ohci_ctl_s cn63xx;
- struct cvmx_uctlx_ohci_ctl_s cn63xxp1;
- struct cvmx_uctlx_ohci_ctl_s cn66xx;
- struct cvmx_uctlx_ohci_ctl_s cn68xx;
- struct cvmx_uctlx_ohci_ctl_s cn68xxp1;
- struct cvmx_uctlx_ohci_ctl_s cnf71xx;
};
union cvmx_uctlx_orto_ctl {
@@ -351,13 +288,6 @@
uint64_t reserved_32_63:32;
#endif
} s;
- struct cvmx_uctlx_orto_ctl_s cn61xx;
- struct cvmx_uctlx_orto_ctl_s cn63xx;
- struct cvmx_uctlx_orto_ctl_s cn63xxp1;
- struct cvmx_uctlx_orto_ctl_s cn66xx;
- struct cvmx_uctlx_orto_ctl_s cn68xx;
- struct cvmx_uctlx_orto_ctl_s cn68xxp1;
- struct cvmx_uctlx_orto_ctl_s cnf71xx;
};
union cvmx_uctlx_ppaf_wm {
@@ -371,11 +301,6 @@
uint64_t reserved_5_63:59;
#endif
} s;
- struct cvmx_uctlx_ppaf_wm_s cn61xx;
- struct cvmx_uctlx_ppaf_wm_s cn63xx;
- struct cvmx_uctlx_ppaf_wm_s cn63xxp1;
- struct cvmx_uctlx_ppaf_wm_s cn66xx;
- struct cvmx_uctlx_ppaf_wm_s cnf71xx;
};
union cvmx_uctlx_uphy_ctl_status {
@@ -407,13 +332,6 @@
uint64_t reserved_10_63:54;
#endif
} s;
- struct cvmx_uctlx_uphy_ctl_status_s cn61xx;
- struct cvmx_uctlx_uphy_ctl_status_s cn63xx;
- struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1;
- struct cvmx_uctlx_uphy_ctl_status_s cn66xx;
- struct cvmx_uctlx_uphy_ctl_status_s cn68xx;
- struct cvmx_uctlx_uphy_ctl_status_s cn68xxp1;
- struct cvmx_uctlx_uphy_ctl_status_s cnf71xx;
};
union cvmx_uctlx_uphy_portx_ctl_status {
@@ -463,13 +381,6 @@
uint64_t reserved_43_63:21;
#endif
} s;
- struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx;
- struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
- struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
- struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx;
- struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx;
- struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1;
- struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx;
};
#endif
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 6048150..a2e2876 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -51,7 +51,7 @@
extern void octeon_io_clk_delay(unsigned long);
#define OCTEON_ARGV_MAX_ARGS 64
-#define OCTOEN_SERIAL_LEN 20
+#define OCTEON_SERIAL_LEN 20
struct octeon_boot_descriptor {
#ifdef __BIG_ENDIAN_BITFIELD
@@ -102,7 +102,7 @@
uint16_t chip_type;
uint8_t chip_rev_major;
uint8_t chip_rev_minor;
- char board_serial_number[OCTOEN_SERIAL_LEN];
+ char board_serial_number[OCTEON_SERIAL_LEN];
uint8_t mac_addr_base[6];
uint8_t mac_addr_count;
uint64_t cvmx_desc_vaddr;
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index e8cc328..0ba4ce6 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -154,6 +154,7 @@
typedef struct { unsigned long pgprot; } pgprot_t;
#define pgprot_val(x) ((x).pgprot)
#define __pgprot(x) ((pgprot_t) { (x) } )
+#define pte_pgprot(x) __pgprot(pte_val(x) & ~_PFN_MASK)
/*
* On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
@@ -248,7 +249,7 @@
#define virt_to_pfn(kaddr) PFN_DOWN(virt_to_phys((void *)(kaddr)))
#define virt_to_page(kaddr) pfn_to_page(virt_to_pfn(kaddr))
-extern int __virt_addr_valid(const volatile void *kaddr);
+extern bool __virt_addr_valid(const volatile void *kaddr);
#define virt_addr_valid(kaddr) \
__virt_addr_valid((const volatile void *) (kaddr))
@@ -257,9 +258,6 @@
((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-#define UNCAC_ADDR(addr) (UNCAC_BASE + __pa(addr))
-#define CAC_ADDR(addr) ((unsigned long)__va((addr) - UNCAC_BASE))
-
#include <asm-generic/memory_model.h>
#include <asm-generic/getorder.h>
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 4360998..6f48649 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -108,7 +108,6 @@
#define HAVE_PCI_MMAP
#define ARCH_GENERIC_PCI_MMAP_RESOURCE
-#define HAVE_ARCH_PCI_RESOURCE_TO_USER
/*
* Dynamic DMA mapping stuff.
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index 3206245..a92cd30 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -45,18 +45,21 @@
#ifndef __ASSEMBLY__
-/*
- * All accesses to bridge hardware registers must be done
- * using 32-bit loads and stores.
- */
-typedef u32 bridgereg_t;
+#define ATE_V 0x01
+#define ATE_CO 0x02
+#define ATE_PREC 0x04
+#define ATE_PREF 0x08
+#define ATE_BAR 0x10
-typedef u64 bridge_ate_t;
+#define ATE_PFNSHIFT 12
+#define ATE_TIDSHIFT 8
+#define ATE_RMFSHIFT 48
-/* pointers to bridge ATEs
- * are always "pointer to volatile"
- */
-typedef volatile bridge_ate_t *bridge_ate_p;
+#define mkate(xaddr, xid, attr) (((xaddr) & 0x0000fffffffff000ULL) | \
+ ((xid)<<ATE_TIDSHIFT) | \
+ (attr))
+
+#define BRIDGE_INTERNAL_ATES 128
/*
* It is generally preferred that hardware registers on the bridge
@@ -65,7 +68,7 @@
* Generated from Bridge spec dated 04oct95
*/
-typedef volatile struct bridge_s {
+struct bridge_regs {
/* Local Registers 0x000000-0x00FFFF */
/* standard widget configuration 0x000000-0x000057 */
@@ -86,105 +89,105 @@
#define b_wid_tflush b_widget.w_tflush
/* bridge-specific widget configuration 0x000058-0x00007F */
- bridgereg_t _pad_000058;
- bridgereg_t b_wid_aux_err; /* 0x00005C */
- bridgereg_t _pad_000060;
- bridgereg_t b_wid_resp_upper; /* 0x000064 */
- bridgereg_t _pad_000068;
- bridgereg_t b_wid_resp_lower; /* 0x00006C */
- bridgereg_t _pad_000070;
- bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */
- bridgereg_t _pad_000078[2];
+ u32 _pad_000058;
+ u32 b_wid_aux_err; /* 0x00005C */
+ u32 _pad_000060;
+ u32 b_wid_resp_upper; /* 0x000064 */
+ u32 _pad_000068;
+ u32 b_wid_resp_lower; /* 0x00006C */
+ u32 _pad_000070;
+ u32 b_wid_tst_pin_ctrl; /* 0x000074 */
+ u32 _pad_000078[2];
/* PMU & Map 0x000080-0x00008F */
- bridgereg_t _pad_000080;
- bridgereg_t b_dir_map; /* 0x000084 */
- bridgereg_t _pad_000088[2];
+ u32 _pad_000080;
+ u32 b_dir_map; /* 0x000084 */
+ u32 _pad_000088[2];
/* SSRAM 0x000090-0x00009F */
- bridgereg_t _pad_000090;
- bridgereg_t b_ram_perr; /* 0x000094 */
- bridgereg_t _pad_000098[2];
+ u32 _pad_000090;
+ u32 b_ram_perr; /* 0x000094 */
+ u32 _pad_000098[2];
/* Arbitration 0x0000A0-0x0000AF */
- bridgereg_t _pad_0000A0;
- bridgereg_t b_arb; /* 0x0000A4 */
- bridgereg_t _pad_0000A8[2];
+ u32 _pad_0000A0;
+ u32 b_arb; /* 0x0000A4 */
+ u32 _pad_0000A8[2];
/* Number In A Can 0x0000B0-0x0000BF */
- bridgereg_t _pad_0000B0;
- bridgereg_t b_nic; /* 0x0000B4 */
- bridgereg_t _pad_0000B8[2];
+ u32 _pad_0000B0;
+ u32 b_nic; /* 0x0000B4 */
+ u32 _pad_0000B8[2];
/* PCI/GIO 0x0000C0-0x0000FF */
- bridgereg_t _pad_0000C0;
- bridgereg_t b_bus_timeout; /* 0x0000C4 */
+ u32 _pad_0000C0;
+ u32 b_bus_timeout; /* 0x0000C4 */
#define b_pci_bus_timeout b_bus_timeout
- bridgereg_t _pad_0000C8;
- bridgereg_t b_pci_cfg; /* 0x0000CC */
- bridgereg_t _pad_0000D0;
- bridgereg_t b_pci_err_upper; /* 0x0000D4 */
- bridgereg_t _pad_0000D8;
- bridgereg_t b_pci_err_lower; /* 0x0000DC */
- bridgereg_t _pad_0000E0[8];
+ u32 _pad_0000C8;
+ u32 b_pci_cfg; /* 0x0000CC */
+ u32 _pad_0000D0;
+ u32 b_pci_err_upper; /* 0x0000D4 */
+ u32 _pad_0000D8;
+ u32 b_pci_err_lower; /* 0x0000DC */
+ u32 _pad_0000E0[8];
#define b_gio_err_lower b_pci_err_lower
#define b_gio_err_upper b_pci_err_upper
/* Interrupt 0x000100-0x0001FF */
- bridgereg_t _pad_000100;
- bridgereg_t b_int_status; /* 0x000104 */
- bridgereg_t _pad_000108;
- bridgereg_t b_int_enable; /* 0x00010C */
- bridgereg_t _pad_000110;
- bridgereg_t b_int_rst_stat; /* 0x000114 */
- bridgereg_t _pad_000118;
- bridgereg_t b_int_mode; /* 0x00011C */
- bridgereg_t _pad_000120;
- bridgereg_t b_int_device; /* 0x000124 */
- bridgereg_t _pad_000128;
- bridgereg_t b_int_host_err; /* 0x00012C */
+ u32 _pad_000100;
+ u32 b_int_status; /* 0x000104 */
+ u32 _pad_000108;
+ u32 b_int_enable; /* 0x00010C */
+ u32 _pad_000110;
+ u32 b_int_rst_stat; /* 0x000114 */
+ u32 _pad_000118;
+ u32 b_int_mode; /* 0x00011C */
+ u32 _pad_000120;
+ u32 b_int_device; /* 0x000124 */
+ u32 _pad_000128;
+ u32 b_int_host_err; /* 0x00012C */
struct {
- bridgereg_t __pad; /* 0x0001{30,,,68} */
- bridgereg_t addr; /* 0x0001{34,,,6C} */
+ u32 __pad; /* 0x0001{30,,,68} */
+ u32 addr; /* 0x0001{34,,,6C} */
} b_int_addr[8]; /* 0x000130 */
- bridgereg_t _pad_000170[36];
+ u32 _pad_000170[36];
/* Device 0x000200-0x0003FF */
struct {
- bridgereg_t __pad; /* 0x0002{00,,,38} */
- bridgereg_t reg; /* 0x0002{04,,,3C} */
+ u32 __pad; /* 0x0002{00,,,38} */
+ u32 reg; /* 0x0002{04,,,3C} */
} b_device[8]; /* 0x000200 */
struct {
- bridgereg_t __pad; /* 0x0002{40,,,78} */
- bridgereg_t reg; /* 0x0002{44,,,7C} */
+ u32 __pad; /* 0x0002{40,,,78} */
+ u32 reg; /* 0x0002{44,,,7C} */
} b_wr_req_buf[8]; /* 0x000240 */
struct {
- bridgereg_t __pad; /* 0x0002{80,,,88} */
- bridgereg_t reg; /* 0x0002{84,,,8C} */
+ u32 __pad; /* 0x0002{80,,,88} */
+ u32 reg; /* 0x0002{84,,,8C} */
} b_rrb_map[2]; /* 0x000280 */
#define b_even_resp b_rrb_map[0].reg /* 0x000284 */
#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */
- bridgereg_t _pad_000290;
- bridgereg_t b_resp_status; /* 0x000294 */
- bridgereg_t _pad_000298;
- bridgereg_t b_resp_clear; /* 0x00029C */
+ u32 _pad_000290;
+ u32 b_resp_status; /* 0x000294 */
+ u32 _pad_000298;
+ u32 b_resp_clear; /* 0x00029C */
- bridgereg_t _pad_0002A0[24];
+ u32 _pad_0002A0[24];
char _pad_000300[0x10000 - 0x000300];
/* Internal Address Translation Entry RAM 0x010000-0x0103FF */
union {
- bridge_ate_t wr; /* write-only */
+ u64 wr; /* write-only */
struct {
- bridgereg_t _p_pad;
- bridgereg_t rd; /* read-only */
+ u32 _p_pad;
+ u32 rd; /* read-only */
} hi;
} b_int_ate_ram[128];
@@ -192,8 +195,8 @@
/* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
struct {
- bridgereg_t _p_pad;
- bridgereg_t rd; /* read-only */
+ u32 _p_pad;
+ u32 rd; /* read-only */
} b_int_ate_ram_lo[128];
char _pad_011400[0x20000 - 0x011400];
@@ -212,7 +215,7 @@
} f[8];
} b_type0_cfg_dev[8]; /* 0x020000 */
- /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
+ /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
union { /* make all access sizes available. */
u8 c[0x1000 / 1];
u16 s[0x1000 / 2];
@@ -233,7 +236,7 @@
u8 _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */
/* External Address Translation Entry RAM 0x080000-0x0FFFFF */
- bridge_ate_t b_ext_ate_ram[0x10000];
+ u64 b_ext_ate_ram[0x10000];
/* Reserved 0x100000-0x1FFFFF */
char _pad_100000[0x200000-0x100000];
@@ -259,13 +262,13 @@
u32 l[0x400000 / 4]; /* read-only */
u64 d[0x400000 / 8]; /* read-only */
} b_external_flash; /* 0xC00000 */
-} bridge_t;
+};
/*
* Field formats for Error Command Word and Auxiliary Error Command Word
* of bridge.
*/
-typedef struct bridge_err_cmdword_s {
+struct bridge_err_cmdword {
union {
u32 cmd_word;
struct {
@@ -282,7 +285,7 @@
rsvd:8;
} berr_st;
} berr_un;
-} bridge_err_cmdword_t;
+};
#define berr_field berr_un.berr_st
#endif /* !__ASSEMBLY__ */
@@ -290,7 +293,7 @@
/*
* The values of these macros can and should be crosschecked
* regularly against the offsets of the like-named fields
- * within the "bridge_t" structure above.
+ * within the bridge_regs structure above.
*/
/* Byte offset macros for Bridge internal registers */
@@ -797,59 +800,24 @@
#define PCI64_ATTR_RMF_MASK 0x00ff000000000000
#define PCI64_ATTR_RMF_SHFT 48
-#ifndef __ASSEMBLY__
-/* Address translation entry for mapped pci32 accesses */
-typedef union ate_u {
- u64 ent;
- struct ate_s {
- u64 rmf:16;
- u64 addr:36;
- u64 targ:4;
- u64 reserved:3;
- u64 barrier:1;
- u64 prefetch:1;
- u64 precise:1;
- u64 coherent:1;
- u64 valid:1;
- } field;
-} ate_t;
-#endif /* !__ASSEMBLY__ */
-
-#define ATE_V 0x01
-#define ATE_CO 0x02
-#define ATE_PREC 0x04
-#define ATE_PREF 0x08
-#define ATE_BAR 0x10
-
-#define ATE_PFNSHIFT 12
-#define ATE_TIDSHIFT 8
-#define ATE_RMFSHIFT 48
-
-#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
- ((xid)<<ATE_TIDSHIFT) | \
- (attr)
-
-#define BRIDGE_INTERNAL_ATES 128
-
struct bridge_controller {
- struct pci_controller pc;
- struct resource mem;
- struct resource io;
struct resource busn;
- bridge_t *base;
- nasid_t nasid;
- unsigned int widget_id;
- unsigned int irq_cpu;
- u64 baddr;
+ struct bridge_regs *base;
+ unsigned long baddr;
+ unsigned long intr_addr;
+ struct irq_domain *domain;
unsigned int pci_int[8];
+ nasid_t nasid;
};
#define BRIDGE_CONTROLLER(bus) \
((struct bridge_controller *)((bus)->sysdata))
-extern void register_bridge_irq(unsigned int irq);
-extern int request_bridge_irq(struct bridge_controller *bc);
-
-extern struct pci_ops bridge_pci_ops;
+#define bridge_read(bc, reg) __raw_readl(&bc->base->reg)
+#define bridge_write(bc, reg, val) __raw_writel(val, &bc->base->reg)
+#define bridge_set(bc, reg, val) \
+ __raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg)
+#define bridge_clr(bc, reg, val) \
+ __raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
#endif /* _ASM_PCI_BRIDGE_H */
diff --git a/arch/mips/include/asm/perf_event.h b/arch/mips/include/asm/perf_event.h
index d0c7749..0babf6b 100644
--- a/arch/mips/include/asm/perf_event.h
+++ b/arch/mips/include/asm/perf_event.h
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* linux/arch/mips/include/asm/perf_event.h
*
* Copyright (C) 2010 MIPS Technologies, Inc.
* Author: Deng-Cheng Zhu
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#ifndef __MIPS_PERF_EVENT_H__
diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h
index 39b9f31..1668423 100644
--- a/arch/mips/include/asm/pgalloc.h
+++ b/arch/mips/include/asm/pgalloc.h
@@ -13,6 +13,8 @@
#include <linux/mm.h>
#include <linux/sched.h>
+#include <asm-generic/pgalloc.h> /* for pte_{alloc,free}_one */
+
static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
pte_t *pte)
{
@@ -50,42 +52,9 @@
free_pages((unsigned long)pgd, PGD_ORDER);
}
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
- unsigned long address)
-{
- return (pte_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, PTE_ORDER);
-}
-
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
-{
- struct page *pte;
-
- pte = alloc_pages(GFP_KERNEL, PTE_ORDER);
- if (!pte)
- return NULL;
- clear_highpage(pte);
- if (!pgtable_page_ctor(pte)) {
- __free_page(pte);
- return NULL;
- }
- return pte;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_pages((unsigned long)pte, PTE_ORDER);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
- pgtable_page_dtor(pte);
- __free_pages(pte, PTE_ORDER);
-}
-
#define __pte_free_tlb(tlb,pte,address) \
do { \
- pgtable_page_dtor(pte); \
+ pgtable_pte_page_dtor(pte); \
tlb_remove_page((tlb), pte); \
} while (0)
@@ -136,8 +105,6 @@
#endif /* __PAGETABLE_PUD_FOLDED */
-#define check_pgt_cache() do { } while (0)
-
extern void pagetable_init(void);
#endif /* _ASM_PGALLOC_H */
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 74afe8c..ba96714 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -23,6 +23,24 @@
#include <asm/highmem.h>
#endif
+/*
+ * Regarding 32-bit MIPS huge page support (and the tradeoff it entails):
+ *
+ * We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size,
+ * our 2-level table layout would normally have a PGD entry cover a contiguous
+ * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t
+ * pointers, each pointing to a 4KB physical page). The problem is that 4MB,
+ * spanning both halves of a TLB EntryLo0,1 pair, requires 2MB hardware page
+ * support, not one of the standard supported sizes (1MB,4MB,16MB,...).
+ * To correct for this, when huge pages are enabled, we halve the number of
+ * pointers a PTE page holds, making its last half go to waste. Correspondingly,
+ * we double the number of PGD pages. Overall, page table memory overhead
+ * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly.
+ *
+ * NOTE: We don't yet support huge pages if extended-addressing is enabled
+ * (i.e. EVA, XPA, 36-bit Alchemy/Netlogic).
+ */
+
extern int temp_tlb_entry;
/*
@@ -44,7 +62,12 @@
*/
/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
+# define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2 - 1)
+#else
+# define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
+#endif
+
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE-1))
@@ -52,14 +75,23 @@
* Entries per page directory level: we use two-level, so
* we don't really have any PUD/PMD directory physically.
*/
-#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
+# define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1)
+#else
+# define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
+#endif
+
#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
#define PUD_ORDER aieeee_attempt_to_allocate_pud
-#define PMD_ORDER 1
+#define PMD_ORDER aieeee_attempt_to_allocate_pmd
#define PTE_ORDER 0
#define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
-#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
+# define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t) / 2)
+#else
+# define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+#endif
#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
#define FIRST_USER_ADDRESS 0UL
@@ -87,7 +119,7 @@
extern void load_pgd(unsigned long pg_dir);
-extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
+extern pte_t invalid_pte_table[PTRS_PER_PTE];
/*
* Empty pgd/pmd entries point to the invalid_pte_table.
@@ -97,7 +129,19 @@
return pmd_val(pmd) == (unsigned long) invalid_pte_table;
}
-#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
+static inline int pmd_bad(pmd_t pmd)
+{
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+ /* pmd_huge(pmd) but inline */
+ if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
+ return 0;
+#endif
+
+ if (unlikely(pmd_val(pmd) & ~PAGE_MASK))
+ return 1;
+
+ return 0;
+}
static inline int pmd_present(pmd_t pmd)
{
@@ -146,6 +190,7 @@
#else
#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot) __pmd(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
#endif
#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
@@ -159,6 +204,7 @@
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
/* to find an entry in a page-table-directory */
#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
@@ -175,7 +221,7 @@
((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_unmap(pte) ((void)(pte))
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3K_TLB)
/* Swap entries must have VALID bit cleared. */
#define __swp_type(x) (((x).val >> 10) & 0x1f)
@@ -220,6 +266,6 @@
#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
-#endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */
+#endif /* defined(CONFIG_CPU_R3K_TLB) */
#endif /* _ASM_PGTABLE_32_H */
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 0036ea0..93a9dce 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -265,6 +265,11 @@
static inline int pmd_present(pmd_t pmd)
{
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+ if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
+ return pmd_val(pmd) & _PAGE_PRESENT;
+#endif
+
return pmd_val(pmd) != (unsigned long) invalid_pte_table;
}
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index f88a48c..4da79b8 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -52,6 +52,9 @@
_PAGE_WRITE_SHIFT,
_PAGE_ACCESSED_SHIFT,
_PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+ _PAGE_SPECIAL_SHIFT,
+#endif
};
/*
@@ -78,9 +81,12 @@
_PAGE_WRITE_SHIFT,
_PAGE_ACCESSED_SHIFT,
_PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+ _PAGE_SPECIAL_SHIFT,
+#endif
};
-#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#elif defined(CONFIG_CPU_R3K_TLB)
/* Page table bits used for r3k systems */
enum pgtable_bits {
@@ -90,6 +96,9 @@
_PAGE_WRITE_SHIFT,
_PAGE_ACCESSED_SHIFT,
_PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+ _PAGE_SPECIAL_SHIFT,
+#endif
/* Used by TLB hardware (placed in EntryLo) */
_PAGE_GLOBAL_SHIFT = 8,
@@ -110,9 +119,12 @@
_PAGE_WRITE_SHIFT,
_PAGE_ACCESSED_SHIFT,
_PAGE_MODIFIED_SHIFT,
-#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
_PAGE_HUGE_SHIFT,
#endif
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+ _PAGE_SPECIAL_SHIFT,
+#endif
/* Used by TLB hardware (placed in EntryLo*) */
#if defined(CONFIG_CPU_HAS_RIXI)
@@ -132,9 +144,14 @@
#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
-#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
# define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
#endif
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+# define _PAGE_SPECIAL (1 << _PAGE_SPECIAL_SHIFT)
+#else
+# define _PAGE_SPECIAL 0
+#endif
/* Used by TLB hardware (placed in EntryLo*) */
#if defined(CONFIG_XPA)
@@ -146,7 +163,7 @@
#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3K_TLB)
# define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
# define _CACHE_MASK _CACHE_UNCACHED
# define _PFN_SHIFT PAGE_SHIFT
@@ -204,7 +221,7 @@
/*
* Cache attributes
*/
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+#if defined(CONFIG_CPU_R3K_TLB)
#define _CACHE_CACHABLE_NONCOHERENT 0
#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
@@ -216,13 +233,6 @@
#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
-#elif defined(CONFIG_CPU_LOONGSON3)
-
-/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
-
-#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
-#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
-
#elif defined(CONFIG_MACH_INGENIC)
/* Ingenic uses the WA bit to achieve write-combine memory writes */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 129e032..f85bd5b 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -17,8 +17,10 @@
#include <asm/pgtable-64.h>
#endif
+#include <asm/cmpxchg.h>
#include <asm/io.h>
#include <asm/pgtable-bits.h>
+#include <asm/cpu-features.h>
struct mm_struct;
struct vm_area_struct;
@@ -197,58 +199,18 @@
static inline void set_pte(pte_t *ptep, pte_t pteval)
{
*ptep = pteval;
-#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
+#if !defined(CONFIG_CPU_R3K_TLB)
if (pte_val(pteval) & _PAGE_GLOBAL) {
pte_t *buddy = ptep_buddy(ptep);
/*
* Make sure the buddy is global too (if it's !none,
* it better already be global)
*/
-#ifdef CONFIG_SMP
- /*
- * For SMP, multiple CPUs can race, so we need to do
- * this atomically.
- */
- unsigned long page_global = _PAGE_GLOBAL;
- unsigned long tmp;
-
- if (kernel_uses_llsc && R10000_LLSC_WAR) {
- __asm__ __volatile__ (
- " .set arch=r4000 \n"
- " .set push \n"
- " .set noreorder \n"
- "1:" __LL "%[tmp], %[buddy] \n"
- " bnez %[tmp], 2f \n"
- " or %[tmp], %[tmp], %[global] \n"
- __SC "%[tmp], %[buddy] \n"
- " beqzl %[tmp], 1b \n"
- " nop \n"
- "2: \n"
- " .set pop \n"
- " .set mips0 \n"
- : [buddy] "+m" (buddy->pte), [tmp] "=&r" (tmp)
- : [global] "r" (page_global));
- } else if (kernel_uses_llsc) {
- __asm__ __volatile__ (
- " .set "MIPS_ISA_ARCH_LEVEL" \n"
- " .set push \n"
- " .set noreorder \n"
- "1:" __LL "%[tmp], %[buddy] \n"
- " bnez %[tmp], 2f \n"
- " or %[tmp], %[tmp], %[global] \n"
- __SC "%[tmp], %[buddy] \n"
- " beqz %[tmp], 1b \n"
- " nop \n"
- "2: \n"
- " .set pop \n"
- " .set mips0 \n"
- : [buddy] "+m" (buddy->pte), [tmp] "=&r" (tmp)
- : [global] "r" (page_global));
- }
-#else /* !CONFIG_SMP */
- if (pte_none(*buddy))
- pte_val(*buddy) = pte_val(*buddy) | _PAGE_GLOBAL;
-#endif /* CONFIG_SMP */
+# if defined(CONFIG_PHYS_ADDR_T_64BIT) && !defined(CONFIG_CPU_MIPS32)
+ cmpxchg64(&buddy->pte, 0, _PAGE_GLOBAL);
+# else
+ cmpxchg(&buddy->pte, 0, _PAGE_GLOBAL);
+# endif
}
#endif
}
@@ -256,7 +218,7 @@
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
htw_stop();
-#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
+#if !defined(CONFIG_CPU_R3K_TLB)
/* Preserve global status for the pair */
if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
@@ -315,6 +277,7 @@
static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
+static inline int pte_special(pte_t pte) { return pte.pte_low & _PAGE_SPECIAL; }
static inline pte_t pte_wrprotect(pte_t pte)
{
@@ -375,10 +338,17 @@
}
return pte;
}
+
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+ pte.pte_low |= _PAGE_SPECIAL;
+ return pte;
+}
#else
static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
static inline pte_t pte_wrprotect(pte_t pte)
{
@@ -422,6 +392,12 @@
return pte;
}
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+ pte_val(pte) |= _PAGE_SPECIAL;
+ return pte;
+}
+
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; }
@@ -432,8 +408,6 @@
}
#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
#endif
-static inline int pte_special(pte_t pte) { return 0; }
-static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
/*
* Macro to make mark a page protection value as "uncacheable". Note
@@ -665,6 +639,8 @@
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+#define gup_fast_permitted(start, end) (!cpu_has_dc_aliases)
+
#include <asm-generic/pgtable.h>
/*
@@ -685,9 +661,4 @@
#define HAVE_ARCH_UNMAPPED_AREA
#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init() do { } while (0)
-
#endif /* _ASM_PGTABLE_H */
diff --git a/arch/mips/include/asm/pm-cps.h b/arch/mips/include/asm/pm-cps.h
index bb06169..efd96e9 100644
--- a/arch/mips/include/asm/pm-cps.h
+++ b/arch/mips/include/asm/pm-cps.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2014 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_PM_CPS_H__
diff --git a/arch/mips/include/asm/pm.h b/arch/mips/include/asm/pm.h
index 7c03469..10bb7b6 100644
--- a/arch/mips/include/asm/pm.h
+++ b/arch/mips/include/asm/pm.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2014 Imagination Technologies Ltd
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
* PM helper macros for CPU power off (e.g. Suspend-to-RAM).
*/
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index c373eb6..fba18d4 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -24,21 +24,11 @@
#include <asm/prefetch.h>
/*
- * Return current * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-/*
* System setup and hardware flags..
*/
extern unsigned int vced_count, vcei_count;
-/*
- * MIPS does have an arch_pick_mmap_layout()
- */
-#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
-
#ifdef CONFIG_32BIT
#ifdef CONFIG_KVM_GUEST
/* User space process size is limited to 1GB in KVM Guest Mode */
@@ -260,8 +250,10 @@
/* Saved cp0 stuff. */
unsigned long cp0_status;
+#ifdef CONFIG_MIPS_FP_SUPPORT
/* Saved fpu/fpu emulator stuff. */
struct mips_fpu_struct fpu FPU_ALIGN;
+#endif
/* Assigned branch delay slot 'emulation' frame */
atomic_t bd_emu_frame;
/* PC of the branch from a branch delay slot 'emulation' */
@@ -304,6 +296,17 @@
#define FPAFF_INIT
#endif /* CONFIG_MIPS_MT_FPAFF */
+#ifdef CONFIG_MIPS_FP_SUPPORT
+# define FPU_INIT \
+ .fpu = { \
+ .fpr = {{{0,},},}, \
+ .fcr31 = 0, \
+ .msacsr = 0, \
+ },
+#else
+# define FPU_INIT
+#endif
+
#define INIT_THREAD { \
/* \
* Saved main processor registers \
@@ -326,11 +329,7 @@
/* \
* Saved FPU/FPU emulator stuff \
*/ \
- .fpu = { \
- .fpr = {{{0,},},}, \
- .fcr31 = 0, \
- .msacsr = 0, \
- }, \
+ FPU_INIT \
/* \
* FPU affinity state (null if not FPAFF) \
*/ \
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index 0b4b668..c42e076 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* arch/mips/include/asm/prom.h
*
* Copyright (C) 2010 Cisco Systems Inc. <dediao@cisco.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
*/
#ifndef __ASM_PROM_H
#define __ASM_PROM_H
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index b657861..1e76774 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -56,11 +56,6 @@
return regs->regs[31];
}
-/*
- * Don't use asm-generic/ptrace.h it defines FP accessors that don't make
- * sense on MIPS. We rather want an error if they get invoked.
- */
-
static inline void instruction_pointer_set(struct pt_regs *regs,
unsigned long val)
{
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 7f12d7e..7f4a32d 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -20,6 +20,7 @@
#include <asm/cpu-features.h>
#include <asm/cpu-type.h>
#include <asm/mipsmtregs.h>
+#include <asm/mmzone.h>
#include <linux/uaccess.h> /* for uaccess_kernel() */
extern void (*r4k_blast_dcache)(void);
@@ -48,58 +49,14 @@
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
-#ifdef CONFIG_MIPS_MT
-
-#define __iflush_prologue \
- unsigned long redundance; \
- extern int mt_n_iflushes; \
- for (redundance = 0; redundance < mt_n_iflushes; redundance++) {
-
-#define __iflush_epilogue \
- }
-
-#define __dflush_prologue \
- unsigned long redundance; \
- extern int mt_n_dflushes; \
- for (redundance = 0; redundance < mt_n_dflushes; redundance++) {
-
-#define __dflush_epilogue \
- }
-
-#define __inv_dflush_prologue __dflush_prologue
-#define __inv_dflush_epilogue __dflush_epilogue
-#define __sflush_prologue {
-#define __sflush_epilogue }
-#define __inv_sflush_prologue __sflush_prologue
-#define __inv_sflush_epilogue __sflush_epilogue
-
-#else /* CONFIG_MIPS_MT */
-
-#define __iflush_prologue {
-#define __iflush_epilogue }
-#define __dflush_prologue {
-#define __dflush_epilogue }
-#define __inv_dflush_prologue {
-#define __inv_dflush_epilogue }
-#define __sflush_prologue {
-#define __sflush_epilogue }
-#define __inv_sflush_prologue {
-#define __inv_sflush_epilogue }
-
-#endif /* CONFIG_MIPS_MT */
-
static inline void flush_icache_line_indexed(unsigned long addr)
{
- __iflush_prologue
cache_op(Index_Invalidate_I, addr);
- __iflush_epilogue
}
static inline void flush_dcache_line_indexed(unsigned long addr)
{
- __dflush_prologue
cache_op(Index_Writeback_Inv_D, addr);
- __dflush_epilogue
}
static inline void flush_scache_line_indexed(unsigned long addr)
@@ -109,7 +66,6 @@
static inline void flush_icache_line(unsigned long addr)
{
- __iflush_prologue
switch (boot_cpu_type()) {
case CPU_LOONGSON2:
cache_op(Hit_Invalidate_I_Loongson2, addr);
@@ -119,21 +75,16 @@
cache_op(Hit_Invalidate_I, addr);
break;
}
- __iflush_epilogue
}
static inline void flush_dcache_line(unsigned long addr)
{
- __dflush_prologue
cache_op(Hit_Writeback_Inv_D, addr);
- __dflush_epilogue
}
static inline void invalidate_dcache_line(unsigned long addr)
{
- __dflush_prologue
cache_op(Hit_Invalidate_D, addr);
- __dflush_epilogue
}
static inline void invalidate_scache_line(unsigned long addr)
@@ -586,13 +537,9 @@
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
- __##pfx##flush_prologue \
- \
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
cache##lsize##_unroll32(addr|ws, indexop); \
- \
- __##pfx##flush_epilogue \
} \
\
static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
@@ -600,14 +547,10 @@
unsigned long start = page; \
unsigned long end = page + PAGE_SIZE; \
\
- __##pfx##flush_prologue \
- \
do { \
cache##lsize##_unroll32(start, hitop); \
start += lsize * 32; \
} while (start < end); \
- \
- __##pfx##flush_epilogue \
} \
\
static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
@@ -620,13 +563,9 @@
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
- __##pfx##flush_prologue \
- \
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
cache##lsize##_unroll32(addr|ws, indexop); \
- \
- __##pfx##flush_epilogue \
}
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
@@ -656,14 +595,10 @@
unsigned long start = page; \
unsigned long end = page + PAGE_SIZE; \
\
- __##pfx##flush_prologue \
- \
do { \
cache##lsize##_unroll32_user(start, hitop); \
start += lsize * 32; \
} while (start < end); \
- \
- __##pfx##flush_epilogue \
}
__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
@@ -685,16 +620,12 @@
unsigned long addr = start & ~(lsize - 1); \
unsigned long aend = (end - 1) & ~(lsize - 1); \
\
- __##pfx##flush_prologue \
- \
while (1) { \
prot##cache_op(hitop, addr); \
if (addr == aend) \
break; \
addr += lsize; \
} \
- \
- __##pfx##flush_epilogue \
}
#ifndef CONFIG_EVA
@@ -712,8 +643,6 @@
unsigned long addr = start & ~(lsize - 1); \
unsigned long aend = (end - 1) & ~(lsize - 1); \
\
- __##pfx##flush_prologue \
- \
if (!uaccess_kernel()) { \
while (1) { \
protected_cachee_op(hitop, addr); \
@@ -730,7 +659,6 @@
} \
\
} \
- __##pfx##flush_epilogue \
}
__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
@@ -747,4 +675,25 @@
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
+/* Currently, this is very specific to Loongson-3 */
+#define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \
+static inline void blast_##pfx##cache##lsize##_node(long node) \
+{ \
+ unsigned long start = CAC_BASE | nid_to_addrbase(node); \
+ unsigned long end = start + current_cpu_data.desc.waysize; \
+ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
+ unsigned long ws_end = current_cpu_data.desc.ways << \
+ current_cpu_data.desc.waybit; \
+ unsigned long ws, addr; \
+ \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+ for (addr = start; addr < end; addr += lsize * 32) \
+ cache##lsize##_unroll32(addr|ws, indexop); \
+}
+
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
+
#endif /* _ASM_R4KCACHE_H */
diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h
index 1d830c6..2777148 100644
--- a/arch/mips/include/asm/serial.h
+++ b/arch/mips/include/asm/serial.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2017 MIPS Tech, LLC
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM__SERIAL_H
#define __ASM__SERIAL_H
diff --git a/arch/mips/include/asm/sibyte/bcm1480_int.h b/arch/mips/include/asm/sibyte/bcm1480_int.h
index 6b82ed3..18cf4b1 100644
--- a/arch/mips/include/asm/sibyte/bcm1480_int.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_int.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* BCM1280/BCM1480 Board Support Package
*
@@ -14,20 +15,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_l2c.h b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
index 910e5c7..f6f3a19 100644
--- a/arch/mips/include/asm/sibyte/bcm1480_l2c.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* BCM1280/BCM1480 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_mc.h b/arch/mips/include/asm/sibyte/bcm1480_mc.h
index 86908fd..1d9b62d 100644
--- a/arch/mips/include/asm/sibyte/bcm1480_mc.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_mc.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* BCM1280/BCM1480 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/bcm1480_regs.h b/arch/mips/include/asm/sibyte/bcm1480_regs.h
index 32a8483..ef12ede 100644
--- a/arch/mips/include/asm/sibyte/bcm1480_regs.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_regs.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
#ifndef _BCM1480_REGS_H
diff --git a/arch/mips/include/asm/sibyte/bcm1480_scd.h b/arch/mips/include/asm/sibyte/bcm1480_scd.h
index 8a1e2b0..87f3708 100644
--- a/arch/mips/include/asm/sibyte/bcm1480_scd.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_scd.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* BCM1280/BCM1400 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003,2004,2005
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
#ifndef _BCM1480_SCD_H
diff --git a/arch/mips/include/asm/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h
index ae29dae..86c8761 100644
--- a/arch/mips/include/asm/sibyte/bigsur.h
+++ b/arch/mips/include/asm/sibyte/bigsur.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_SIBYTE_BIGSUR_H
#define __ASM_SIBYTE_BIGSUR_H
diff --git a/arch/mips/include/asm/sibyte/board.h b/arch/mips/include/asm/sibyte/board.h
index 25372ae..20fe2f1 100644
--- a/arch/mips/include/asm/sibyte/board.h
+++ b/arch/mips/include/asm/sibyte/board.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _SIBYTE_BOARD_H
diff --git a/arch/mips/include/asm/sibyte/carmel.h b/arch/mips/include/asm/sibyte/carmel.h
index 793edba..c6730d7 100644
--- a/arch/mips/include/asm/sibyte/carmel.h
+++ b/arch/mips/include/asm/sibyte/carmel.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2002 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_SIBYTE_CARMEL_H
#define __ASM_SIBYTE_CARMEL_H
diff --git a/arch/mips/include/asm/sibyte/sb1250.h b/arch/mips/include/asm/sibyte/sb1250.h
index d45dff9..dbde5f9 100644
--- a/arch/mips/include/asm/sibyte/sb1250.h
+++ b/arch/mips/include/asm/sibyte/sb1250.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _ASM_SIBYTE_SB1250_H
diff --git a/arch/mips/include/asm/sibyte/sb1250_defs.h b/arch/mips/include/asm/sibyte/sb1250_defs.h
index 4364eb8..68cd7c0 100644
--- a/arch/mips/include/asm/sibyte/sb1250_defs.h
+++ b/arch/mips/include/asm/sibyte/sb1250_defs.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_DEFS_H
diff --git a/arch/mips/include/asm/sibyte/sb1250_dma.h b/arch/mips/include/asm/sibyte/sb1250_dma.h
index ea81713..d9678b9 100644
--- a/arch/mips/include/asm/sibyte/sb1250_dma.h
+++ b/arch/mips/include/asm/sibyte/sb1250_dma.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -15,20 +16,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sb1250_genbus.h b/arch/mips/include/asm/sibyte/sb1250_genbus.h
index 04c009c..ddeb8ed 100644
--- a/arch/mips/include/asm/sibyte/sb1250_genbus.h
+++ b/arch/mips/include/asm/sibyte/sb1250_genbus.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -14,20 +15,6 @@
* Copyright 2000, 2001, 2002, 2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sb1250_int.h b/arch/mips/include/asm/sibyte/sb1250_int.h
index 36afcb2..2e0adb0 100644
--- a/arch/mips/include/asm/sibyte/sb1250_int.h
+++ b/arch/mips/include/asm/sibyte/sb1250_int.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000, 2001, 2002, 2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sb1250_l2c.h b/arch/mips/include/asm/sibyte/sb1250_l2c.h
index 30092d7..cd8de84 100644
--- a/arch/mips/include/asm/sibyte/sb1250_l2c.h
+++ b/arch/mips/include/asm/sibyte/sb1250_l2c.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h
index 2340c29..c22df8d 100644
--- a/arch/mips/include/asm/sibyte/sb1250_ldt.h
+++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000, 2001, 2002, 2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
index 3fa94fc..3ddbd4b 100644
--- a/arch/mips/include/asm/sibyte/sb1250_mac.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sb1250_mc.h b/arch/mips/include/asm/sibyte/sb1250_mc.h
index 8368e41..c02fe82 100644
--- a/arch/mips/include/asm/sibyte/sb1250_mc.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mc.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000, 2001, 2002, 2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sb1250_regs.h b/arch/mips/include/asm/sibyte/sb1250_regs.h
index ee86ca0..cdac018 100644
--- a/arch/mips/include/asm/sibyte/sb1250_regs.h
+++ b/arch/mips/include/asm/sibyte/sb1250_regs.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sb1250_scd.h b/arch/mips/include/asm/sibyte/sb1250_scd.h
index d725f2f..d099dcb 100644
--- a/arch/mips/include/asm/sibyte/sb1250_scd.h
+++ b/arch/mips/include/asm/sibyte/sb1250_scd.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003,2004,2005
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_SCD_H
diff --git a/arch/mips/include/asm/sibyte/sb1250_smbus.h b/arch/mips/include/asm/sibyte/sb1250_smbus.h
index 3cb73e8..e854f96 100644
--- a/arch/mips/include/asm/sibyte/sb1250_smbus.h
+++ b/arch/mips/include/asm/sibyte/sb1250_smbus.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -14,20 +15,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sb1250_syncser.h b/arch/mips/include/asm/sibyte/sb1250_syncser.h
index b3acc75..8b40e3f 100644
--- a/arch/mips/include/asm/sibyte/sb1250_syncser.h
+++ b/arch/mips/include/asm/sibyte/sb1250_syncser.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sb1250_uart.h b/arch/mips/include/asm/sibyte/sb1250_uart.h
index a43dc19..da782e6 100644
--- a/arch/mips/include/asm/sibyte/sb1250_uart.h
+++ b/arch/mips/include/asm/sibyte/sb1250_uart.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/* *********************************************************************
* SB1250 Board Support Package
*
@@ -13,20 +14,6 @@
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
********************************************************************* */
diff --git a/arch/mips/include/asm/sibyte/sentosa.h b/arch/mips/include/asm/sibyte/sentosa.h
index 0351a46..a27cda3 100644
--- a/arch/mips/include/asm/sibyte/sentosa.h
+++ b/arch/mips/include/asm/sibyte/sentosa.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2000, 2001 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_SIBYTE_SENTOSA_H
#define __ASM_SIBYTE_SENTOSA_H
diff --git a/arch/mips/include/asm/sibyte/swarm.h b/arch/mips/include/asm/sibyte/swarm.h
index 187cfb1..947122f 100644
--- a/arch/mips/include/asm/sibyte/swarm.h
+++ b/arch/mips/include/asm/sibyte/swarm.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_SIBYTE_SWARM_H
#define __ASM_SIBYTE_SWARM_H
diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h
index 16b4ee3..7e5b941 100644
--- a/arch/mips/include/asm/smp-cps.h
+++ b/arch/mips/include/asm/smp-cps.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2013 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_SMP_CPS_H__
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index 53b2cb8..65618ff 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -29,10 +29,14 @@
int (*boot_secondary)(int cpu, struct task_struct *idle);
void (*smp_setup)(void);
void (*prepare_cpus)(unsigned int max_cpus);
+ void (*prepare_boot_cpu)(void);
#ifdef CONFIG_HOTPLUG_CPU
int (*cpu_disable)(void);
void (*cpu_die)(unsigned int cpu);
#endif
+#ifdef CONFIG_KEXEC
+ void (*kexec_nonboot_cpu)(void);
+#endif
};
extern void register_smp_ops(const struct plat_smp_ops *ops);
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 056a6bf..7990c1c 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -91,6 +91,22 @@
extern void play_dead(void);
#endif
+#ifdef CONFIG_KEXEC
+static inline void kexec_nonboot_cpu(void)
+{
+ extern const struct plat_smp_ops *mp_ops; /* private */
+
+ return mp_ops->kexec_nonboot_cpu();
+}
+
+static inline void *kexec_nonboot_cpu_func(void)
+{
+ extern const struct plat_smp_ops *mp_ops; /* private */
+
+ return mp_ops->kexec_nonboot_cpu;
+}
+#endif
+
/*
* This function will set up the necessary IPIs for Linux to communicate
* with the CPUs in mask.
diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
index 66814f8..837d23e 100644
--- a/arch/mips/include/asm/sn/addrs.h
+++ b/arch/mips/include/asm/sn/addrs.h
@@ -27,16 +27,11 @@
#ifndef __ASSEMBLY__
-#define PS_UINT_CAST (unsigned long)
#define UINT64_CAST (unsigned long)
-#define HUBREG_CAST (volatile hubreg_t *)
-
#else /* __ASSEMBLY__ */
-#define PS_UINT_CAST
#define UINT64_CAST
-#define HUBREG_CAST
#endif /* __ASSEMBLY__ */
@@ -256,42 +251,23 @@
* Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
* They're always safe.
*/
-#define LOCAL_HUB_ADDR(_x) (HUBREG_CAST (IALIAS_BASE + (_x)))
-#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
- 0x800000 + (_x)))
-#ifdef CONFIG_SGI_IP27
-#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
- 0x800000 + (_x)))
-#endif /* CONFIG_SGI_IP27 */
+#define LOCAL_HUB_ADDR(_x) (IALIAS_BASE + (_x))
+#define REMOTE_HUB_ADDR(_n, _x) ((NODE_SWIN_BASE(_n, 1) + 0x800000 + (_x)))
#ifndef __ASSEMBLY__
-#define HUB_L(_a) *(_a)
-#define HUB_S(_a, _d) *(_a) = (_d)
+#define LOCAL_HUB_PTR(_x) ((u64 *)LOCAL_HUB_ADDR((_x)))
+#define REMOTE_HUB_PTR(_n, _x) ((u64 *)REMOTE_HUB_ADDR((_n), (_x)))
-#define LOCAL_HUB_L(_r) HUB_L(LOCAL_HUB_ADDR(_r))
-#define LOCAL_HUB_S(_r, _d) HUB_S(LOCAL_HUB_ADDR(_r), (_d))
-#define REMOTE_HUB_L(_n, _r) HUB_L(REMOTE_HUB_ADDR((_n), (_r)))
-#define REMOTE_HUB_S(_n, _r, _d) HUB_S(REMOTE_HUB_ADDR((_n), (_r)), (_d))
-#define REMOTE_HUB_PI_L(_n, _sn, _r) HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
-#define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
+#define LOCAL_HUB_L(_r) __raw_readq(LOCAL_HUB_PTR(_r))
+#define LOCAL_HUB_S(_r, _d) __raw_writeq((_d), LOCAL_HUB_PTR(_r))
+#define REMOTE_HUB_L(_n, _r) __raw_readq(REMOTE_HUB_PTR((_n), (_r)))
+#define REMOTE_HUB_S(_n, _r, _d) __raw_writeq((_d), \
+ REMOTE_HUB_PTR((_n), (_r)))
#endif /* !__ASSEMBLY__ */
/*
- * The following macros are used to get to a hub/bridge register, given
- * the base of the register space.
- */
-#define HUB_REG_PTR(_base, _off) \
- (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
-
-#define HUB_REG_PTR_L(_base, _off) \
- HUB_L(HUB_REG_PTR((_base), (_off)))
-
-#define HUB_REG_PTR_S(_base, _off, _data) \
- HUB_S(HUB_REG_PTR((_base), (_off)), (_data))
-
-/*
* Software structure locations -- permanently fixed
* See diagram in kldir.h
*/
@@ -387,44 +363,14 @@
#define SYMMON_STK_END(nasid) (SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
-/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
- * relocatable program
- */
-#define UNIX_DEBUG_LOADADDR 0x300000
-#define SYMMON_LOADADDR(nasid) \
- TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
-
-#define FREEMEM_OFFSET(nasid) KLD_FREEMEM(nasid)->offset
-#define FREEMEM_ADDR(nasid) SYMMON_STK_END(nasid)
-/*
- * XXX
- * Fix this. FREEMEM_ADDR should be aware of if symmon is loaded.
- * Also, it should take into account what prom thinks to be a safe
- * address
- PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid))
- */
-#define FREEMEM_SIZE(nasid) KLD_FREEMEM(nasid)->size
-
-#define PI_ERROR_OFFSET(nasid) KLD_PI_ERROR(nasid)->offset
-#define PI_ERROR_ADDR(nasid) \
- TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid))
-#define PI_ERROR_SIZE(nasid) KLD_PI_ERROR(nasid)->size
-
#define NODE_OFFSET_TO_K0(_nasid, _off) \
PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | CAC_BASE)
#define NODE_OFFSET_TO_K1(_nasid, _off) \
TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | UNCAC_BASE)
-#define K0_TO_NODE_OFFSET(_k0addr) \
- ((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK)
#define KERN_VARS_ADDR(nasid) KLD_KERN_VARS(nasid)->pointer
#define KERN_VARS_SIZE(nasid) KLD_KERN_VARS(nasid)->size
-#define KERN_XP_ADDR(nasid) KLD_KERN_XP(nasid)->pointer
-#define KERN_XP_SIZE(nasid) KLD_KERN_XP(nasid)->size
-
-#define GPDA_ADDR(nasid) TO_NODE_CAC(nasid, GPDA_OFFSET)
-
#endif /* !__ASSEMBLY__ */
diff --git a/arch/mips/include/asm/sn/arch.h b/arch/mips/include/asm/sn/arch.h
index 471e687..3f1fb14 100644
--- a/arch/mips/include/asm/sn/arch.h
+++ b/arch/mips/include/asm/sn/arch.h
@@ -17,8 +17,6 @@
#include <asm/sn/sn0/arch.h>
#endif
-typedef u64 hubreg_t;
-
#define cputonasid(cpu) (sn_cpu_info[(cpu)].p_nasid)
#define cputoslice(cpu) (sn_cpu_info[(cpu)].p_slice)
#define makespnum(_nasid, _slice) \
diff --git a/arch/mips/include/asm/sn/io.h b/arch/mips/include/asm/sn/io.h
index d5174d0..211f1e8 100644
--- a/arch/mips/include/asm/sn/io.h
+++ b/arch/mips/include/asm/sn/io.h
@@ -44,7 +44,7 @@
IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \
(bigwin), IIO_ITTE_INVALID_WIDGET, 0)
-#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin))
+#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_PTR((nasid), IIO_ITTE(bigwin))
/*
* Macro which takes the widget number, and returns the
diff --git a/arch/mips/include/asm/sn/ioc3.h b/arch/mips/include/asm/sn/ioc3.h
index 25c8dcc..a947eed 100644
--- a/arch/mips/include/asm/sn/ioc3.h
+++ b/arch/mips/include/asm/sn/ioc3.h
@@ -3,169 +3,161 @@
* Copyright (C) 1999, 2000 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
-#ifndef _IOC3_H
-#define _IOC3_H
+#ifndef MIPS_SN_IOC3_H
+#define MIPS_SN_IOC3_H
#include <linux/types.h>
-/* SUPERIO uart register map */
-typedef volatile struct ioc3_uartregs {
- union {
- volatile u8 rbr; /* read only, DLAB == 0 */
- volatile u8 thr; /* write only, DLAB == 0 */
- volatile u8 dll; /* DLAB == 1 */
- } u1;
- union {
- volatile u8 ier; /* DLAB == 0 */
- volatile u8 dlm; /* DLAB == 1 */
- } u2;
- union {
- volatile u8 iir; /* read only */
- volatile u8 fcr; /* write only */
- } u3;
- volatile u8 iu_lcr;
- volatile u8 iu_mcr;
- volatile u8 iu_lsr;
- volatile u8 iu_msr;
- volatile u8 iu_scr;
-} ioc3_uregs_t;
+/* serial port register map */
+struct ioc3_serialregs {
+ u32 sscr;
+ u32 stpir;
+ u32 stcir;
+ u32 srpir;
+ u32 srcir;
+ u32 srtr;
+ u32 shadow;
+};
-#define iu_rbr u1.rbr
-#define iu_thr u1.thr
-#define iu_dll u1.dll
-#define iu_ier u2.ier
-#define iu_dlm u2.dlm
-#define iu_iir u3.iir
-#define iu_fcr u3.fcr
+/* SUPERIO uart register map */
+struct ioc3_uartregs {
+ union {
+ u8 iu_rbr; /* read only, DLAB == 0 */
+ u8 iu_thr; /* write only, DLAB == 0 */
+ u8 iu_dll; /* DLAB == 1 */
+ };
+ union {
+ u8 iu_ier; /* DLAB == 0 */
+ u8 iu_dlm; /* DLAB == 1 */
+ };
+ union {
+ u8 iu_iir; /* read only */
+ u8 iu_fcr; /* write only */
+ };
+ u8 iu_lcr;
+ u8 iu_mcr;
+ u8 iu_lsr;
+ u8 iu_msr;
+ u8 iu_scr;
+};
struct ioc3_sioregs {
- volatile u8 fill[0x141]; /* starts at 0x141 */
+ u8 fill[0x141]; /* starts at 0x141 */
- volatile u8 uartc;
- volatile u8 kbdcg;
+ u8 uartc;
+ u8 kbdcg;
- volatile u8 fill0[0x150 - 0x142 - 1];
+ u8 fill0[0x150 - 0x142 - 1];
- volatile u8 pp_data;
- volatile u8 pp_dsr;
- volatile u8 pp_dcr;
+ u8 pp_data;
+ u8 pp_dsr;
+ u8 pp_dcr;
- volatile u8 fill1[0x158 - 0x152 - 1];
+ u8 fill1[0x158 - 0x152 - 1];
- volatile u8 pp_fifa;
- volatile u8 pp_cfgb;
- volatile u8 pp_ecr;
+ u8 pp_fifa;
+ u8 pp_cfgb;
+ u8 pp_ecr;
- volatile u8 fill2[0x168 - 0x15a - 1];
+ u8 fill2[0x168 - 0x15a - 1];
- volatile u8 rtcad;
- volatile u8 rtcdat;
+ u8 rtcad;
+ u8 rtcdat;
- volatile u8 fill3[0x170 - 0x169 - 1];
+ u8 fill3[0x170 - 0x169 - 1];
struct ioc3_uartregs uartb; /* 0x20170 */
struct ioc3_uartregs uarta; /* 0x20178 */
};
+struct ioc3_ethregs {
+ u32 emcr; /* 0x000f0 */
+ u32 eisr; /* 0x000f4 */
+ u32 eier; /* 0x000f8 */
+ u32 ercsr; /* 0x000fc */
+ u32 erbr_h; /* 0x00100 */
+ u32 erbr_l; /* 0x00104 */
+ u32 erbar; /* 0x00108 */
+ u32 ercir; /* 0x0010c */
+ u32 erpir; /* 0x00110 */
+ u32 ertr; /* 0x00114 */
+ u32 etcsr; /* 0x00118 */
+ u32 ersr; /* 0x0011c */
+ u32 etcdc; /* 0x00120 */
+ u32 ebir; /* 0x00124 */
+ u32 etbr_h; /* 0x00128 */
+ u32 etbr_l; /* 0x0012c */
+ u32 etcir; /* 0x00130 */
+ u32 etpir; /* 0x00134 */
+ u32 emar_h; /* 0x00138 */
+ u32 emar_l; /* 0x0013c */
+ u32 ehar_h; /* 0x00140 */
+ u32 ehar_l; /* 0x00144 */
+ u32 micr; /* 0x00148 */
+ u32 midr_r; /* 0x0014c */
+ u32 midr_w; /* 0x00150 */
+};
+
+struct ioc3_serioregs {
+ u32 km_csr; /* 0x0009c */
+ u32 k_rd; /* 0x000a0 */
+ u32 m_rd; /* 0x000a4 */
+ u32 k_wd; /* 0x000a8 */
+ u32 m_wd; /* 0x000ac */
+};
+
/* Register layout of IOC3 in configuration space. */
struct ioc3 {
- volatile u32 pad0[7]; /* 0x00000 */
- volatile u32 sio_ir; /* 0x0001c */
- volatile u32 sio_ies; /* 0x00020 */
- volatile u32 sio_iec; /* 0x00024 */
- volatile u32 sio_cr; /* 0x00028 */
- volatile u32 int_out; /* 0x0002c */
- volatile u32 mcr; /* 0x00030 */
+ /* PCI Config Space registers */
+ u32 pci_id; /* 0x00000 */
+ u32 pci_scr; /* 0x00004 */
+ u32 pci_rev; /* 0x00008 */
+ u32 pci_lat; /* 0x0000c */
+ u32 pci_addr; /* 0x00010 */
+ u32 pci_err_addr_l; /* 0x00014 */
+ u32 pci_err_addr_h; /* 0x00018 */
+
+ u32 sio_ir; /* 0x0001c */
+ u32 sio_ies; /* 0x00020 */
+ u32 sio_iec; /* 0x00024 */
+ u32 sio_cr; /* 0x00028 */
+ u32 int_out; /* 0x0002c */
+ u32 mcr; /* 0x00030 */
/* General Purpose I/O registers */
- volatile u32 gpcr_s; /* 0x00034 */
- volatile u32 gpcr_c; /* 0x00038 */
- volatile u32 gpdr; /* 0x0003c */
- volatile u32 gppr_0; /* 0x00040 */
- volatile u32 gppr_1; /* 0x00044 */
- volatile u32 gppr_2; /* 0x00048 */
- volatile u32 gppr_3; /* 0x0004c */
- volatile u32 gppr_4; /* 0x00050 */
- volatile u32 gppr_5; /* 0x00054 */
- volatile u32 gppr_6; /* 0x00058 */
- volatile u32 gppr_7; /* 0x0005c */
- volatile u32 gppr_8; /* 0x00060 */
- volatile u32 gppr_9; /* 0x00064 */
- volatile u32 gppr_10; /* 0x00068 */
- volatile u32 gppr_11; /* 0x0006c */
- volatile u32 gppr_12; /* 0x00070 */
- volatile u32 gppr_13; /* 0x00074 */
- volatile u32 gppr_14; /* 0x00078 */
- volatile u32 gppr_15; /* 0x0007c */
+ u32 gpcr_s; /* 0x00034 */
+ u32 gpcr_c; /* 0x00038 */
+ u32 gpdr; /* 0x0003c */
+ u32 gppr[16]; /* 0x00040 */
/* Parallel Port Registers */
- volatile u32 ppbr_h_a; /* 0x00080 */
- volatile u32 ppbr_l_a; /* 0x00084 */
- volatile u32 ppcr_a; /* 0x00088 */
- volatile u32 ppcr; /* 0x0008c */
- volatile u32 ppbr_h_b; /* 0x00090 */
- volatile u32 ppbr_l_b; /* 0x00094 */
- volatile u32 ppcr_b; /* 0x00098 */
+ u32 ppbr_h_a; /* 0x00080 */
+ u32 ppbr_l_a; /* 0x00084 */
+ u32 ppcr_a; /* 0x00088 */
+ u32 ppcr; /* 0x0008c */
+ u32 ppbr_h_b; /* 0x00090 */
+ u32 ppbr_l_b; /* 0x00094 */
+ u32 ppcr_b; /* 0x00098 */
/* Keyboard and Mouse Registers */
- volatile u32 km_csr; /* 0x0009c */
- volatile u32 k_rd; /* 0x000a0 */
- volatile u32 m_rd; /* 0x000a4 */
- volatile u32 k_wd; /* 0x000a8 */
- volatile u32 m_wd; /* 0x000ac */
+ struct ioc3_serioregs serio;
/* Serial Port Registers */
- volatile u32 sbbr_h; /* 0x000b0 */
- volatile u32 sbbr_l; /* 0x000b4 */
- volatile u32 sscr_a; /* 0x000b8 */
- volatile u32 stpir_a; /* 0x000bc */
- volatile u32 stcir_a; /* 0x000c0 */
- volatile u32 srpir_a; /* 0x000c4 */
- volatile u32 srcir_a; /* 0x000c8 */
- volatile u32 srtr_a; /* 0x000cc */
- volatile u32 shadow_a; /* 0x000d0 */
- volatile u32 sscr_b; /* 0x000d4 */
- volatile u32 stpir_b; /* 0x000d8 */
- volatile u32 stcir_b; /* 0x000dc */
- volatile u32 srpir_b; /* 0x000e0 */
- volatile u32 srcir_b; /* 0x000e4 */
- volatile u32 srtr_b; /* 0x000e8 */
- volatile u32 shadow_b; /* 0x000ec */
+ u32 sbbr_h; /* 0x000b0 */
+ u32 sbbr_l; /* 0x000b4 */
+ struct ioc3_serialregs port_a;
+ struct ioc3_serialregs port_b;
- /* Ethernet Registers */
- volatile u32 emcr; /* 0x000f0 */
- volatile u32 eisr; /* 0x000f4 */
- volatile u32 eier; /* 0x000f8 */
- volatile u32 ercsr; /* 0x000fc */
- volatile u32 erbr_h; /* 0x00100 */
- volatile u32 erbr_l; /* 0x00104 */
- volatile u32 erbar; /* 0x00108 */
- volatile u32 ercir; /* 0x0010c */
- volatile u32 erpir; /* 0x00110 */
- volatile u32 ertr; /* 0x00114 */
- volatile u32 etcsr; /* 0x00118 */
- volatile u32 ersr; /* 0x0011c */
- volatile u32 etcdc; /* 0x00120 */
- volatile u32 ebir; /* 0x00124 */
- volatile u32 etbr_h; /* 0x00128 */
- volatile u32 etbr_l; /* 0x0012c */
- volatile u32 etcir; /* 0x00130 */
- volatile u32 etpir; /* 0x00134 */
- volatile u32 emar_h; /* 0x00138 */
- volatile u32 emar_l; /* 0x0013c */
- volatile u32 ehar_h; /* 0x00140 */
- volatile u32 ehar_l; /* 0x00144 */
- volatile u32 micr; /* 0x00148 */
- volatile u32 midr_r; /* 0x0014c */
- volatile u32 midr_w; /* 0x00150 */
- volatile u32 pad1[(0x20000 - 0x00154) / 4];
+ /* Ethernet Registers */
+ struct ioc3_ethregs eth;
+ u32 pad1[(0x20000 - 0x00154) / 4];
/* SuperIO Registers XXX */
struct ioc3_sioregs sregs; /* 0x20000 */
- volatile u32 pad2[(0x40000 - 0x20180) / 4];
+ u32 pad2[(0x40000 - 0x20180) / 4];
/* SSRAM Diagnostic Access */
- volatile u32 ssram[(0x80000 - 0x40000) / 4];
+ u32 ssram[(0x80000 - 0x40000) / 4];
/* Bytebus device offsets
0x80000 - Access to the generic devices selected with DEV0
@@ -178,6 +170,20 @@
0xFFFFF bytebus DEV_SEL_3 */
};
+
+#define PCI_LAT 0xc /* Latency Timer */
+#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
+#define UARTA_BASE 0x178
+#define UARTB_BASE 0x170
+
+/*
+ * Bytebus device space
+ */
+#define IOC3_BYTEBUS_DEV0 0x80000L
+#define IOC3_BYTEBUS_DEV1 0xa0000L
+#define IOC3_BYTEBUS_DEV2 0xc0000L
+#define IOC3_BYTEBUS_DEV3 0xe0000L
+
/*
* Ethernet RX Buffer
*/
@@ -233,28 +239,20 @@
#define ETXD_B2CNT_MASK 0x7ff00000
#define ETXD_B2CNT_SHIFT 20
-/*
- * Bytebus device space
- */
-#define IOC3_BYTEBUS_DEV0 0x80000L
-#define IOC3_BYTEBUS_DEV1 0xa0000L
-#define IOC3_BYTEBUS_DEV2 0xc0000L
-#define IOC3_BYTEBUS_DEV3 0xe0000L
-
/* ------------------------------------------------------------------------- */
/* Superio Registers (PIO Access) */
#define IOC3_SIO_BASE 0x20000
#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */
#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */
-#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */
+#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */
#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */
#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */
#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */
/* SSRAM Diagnostic Access */
#define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */
-#define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */
+#define IOC3_SSRAM_LEN 0x40000 /* 256kb (addrspc sz, may not be populated) */
#define IOC3_SSRAM_DM 0x0000ffff /* data mask */
#define IOC3_SSRAM_PM 0x00010000 /* parity mask */
@@ -294,10 +292,10 @@
SIO_IR to assert */
#define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
SIO_IR to assert */
-#define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */
-#define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */
-#define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */
-#define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */
+#define KM_CSR_K_CLAMP_1 0x00100000 /* Pull K_CLK low aft recv 1 char */
+#define KM_CSR_M_CLAMP_1 0x00200000 /* Pull M_CLK low aft recv 1 char */
+#define KM_CSR_K_CLAMP_3 0x00400000 /* Pull K_CLK low aft recv 3 chars */
+#define KM_CSR_M_CLAMP_3 0x00800000 /* Pull M_CLK low aft recv 3 chars */
/* bitmasks for IOC3_K_RD and IOC3_M_RD */
#define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */
@@ -440,10 +438,6 @@
SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
-/* macro to load pending interrupts */
-#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
- PCI_INW(&((mem)->sio_ies_ro)))
-
/* bitmasks for SIO_CR */
#define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */
#define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */
@@ -500,10 +494,11 @@
#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
-#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
-#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */
-#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */
+#define GPPR_PHY_RESET_PIN 5 /* GIO pin cntrlling phy reset */
+#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrlling uart b mode sel */
+#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrlling uart a mode sel */
+/* ethernet */
#define EMCR_DUPLEX 0x00000001
#define EMCR_PROMISC 0x00000002
#define EMCR_PADEN 0x00000004
@@ -595,70 +590,4 @@
#define MIDR_DATA_MASK 0x0000ffff
-#define ERXBUF_IPCKSUM_MASK 0x0000ffff
-#define ERXBUF_BYTECNT_MASK 0x07ff0000
-#define ERXBUF_BYTECNT_SHIFT 16
-#define ERXBUF_V 0x80000000
-
-#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */
-#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */
-#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */
-#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */
-#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */
-#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */
-#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */
-#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */
-#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */
-#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */
-#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */
-#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */
-
-#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */
-#define ETXD_INTWHENDONE 0x00001000 /* intr when done */
-#define ETXD_D0V 0x00010000 /* data 0 valid */
-#define ETXD_B1V 0x00020000 /* buf 1 valid */
-#define ETXD_B2V 0x00040000 /* buf 2 valid */
-#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */
-#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */
-#define ETXD_CHKOFF_SHIFT 20
-
-#define ETXD_D0CNT_MASK 0x0000007f
-#define ETXD_B1CNT_MASK 0x0007ff00
-#define ETXD_B1CNT_SHIFT 8
-#define ETXD_B2CNT_MASK 0x7ff00000
-#define ETXD_B2CNT_SHIFT 20
-
-typedef enum ioc3_subdevs_e {
- ioc3_subdev_ether,
- ioc3_subdev_generic,
- ioc3_subdev_nic,
- ioc3_subdev_kbms,
- ioc3_subdev_ttya,
- ioc3_subdev_ttyb,
- ioc3_subdev_ecpp,
- ioc3_subdev_rt,
- ioc3_nsubdevs
-} ioc3_subdev_t;
-
-/* subdevice disable bits,
- * from the standard INFO_LBL_SUBDEVS
- */
-#define IOC3_SDB_ETHER (1<<ioc3_subdev_ether)
-#define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic)
-#define IOC3_SDB_NIC (1<<ioc3_subdev_nic)
-#define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms)
-#define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya)
-#define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb)
-#define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp)
-#define IOC3_SDB_RT (1<<ioc3_subdev_rt)
-
-#define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1)
-
-#define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB)
-
-#define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS
-
-#define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER
-#define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)
-
-#endif /* _IOC3_H */
+#endif /* MIPS_SN_IOC3_H */
diff --git a/arch/mips/include/asm/sn/irq_alloc.h b/arch/mips/include/asm/sn/irq_alloc.h
new file mode 100644
index 0000000..09b89ce
--- /dev/null
+++ b/arch/mips/include/asm/sn/irq_alloc.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_SN_IRQ_ALLOC_H
+#define __ASM_SN_IRQ_ALLOC_H
+
+struct irq_alloc_info {
+ void *ctrl;
+ nasid_t nasid;
+ int pin;
+};
+
+#endif /* __ASM_SN_IRQ_ALLOC_H */
diff --git a/arch/mips/include/asm/sn/sn0/addrs.h b/arch/mips/include/asm/sn/sn0/addrs.h
index 6b53070..f13df84 100644
--- a/arch/mips/include/asm/sn/sn0/addrs.h
+++ b/arch/mips/include/asm/sn/sn0/addrs.h
@@ -134,11 +134,6 @@
#define CALIAS_BASE CAC_BASE
-
-
-#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \
- ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
-
#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
/* Turn on sable logging for the processors whose bits are set. */
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index ee81297..8a88eb2 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -11,6 +11,21 @@
#include <asm/processor.h>
#include <asm/qrwlock.h>
+
+#include <asm-generic/qspinlock_types.h>
+
+#define queued_spin_unlock queued_spin_unlock
+/**
+ * queued_spin_unlock - release a queued spinlock
+ * @lock : Pointer to queued spinlock structure
+ */
+static inline void queued_spin_unlock(struct qspinlock *lock)
+{
+ /* This could be optimised with ARCH_HAS_MMIOWB */
+ mmiowb();
+ smp_store_release(&lock->locked, 0);
+}
+
#include <asm/qspinlock.h>
#endif /* _ASM_SPINLOCK_H */
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 2161357..4d6ad90 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -427,9 +427,10 @@
#ifdef CONFIG_CPU_MIPSR6
eretnc
#else
+ .set push
.set arch=r4000
eret
- .set mips0
+ .set pop
#endif
.endm
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index e610473..09cbe90 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -42,7 +42,7 @@
* inline to try to keep the overhead down. If we have been forced to run on
* a "CPU" with an FPU because of a previous high level of FP computation,
* but did not actually use the FPU during the most recent time-slice (CU1
- * isn't set), we undo the restriction on cpus_allowed.
+ * isn't set), we undo the restriction on cpus_mask.
*
* We're not calling set_cpus_allowed() here, because we have no need to
* force prompt migration - we're already switching the current CPU to a
@@ -57,7 +57,7 @@
test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
(!(KSTK_STATUS(prev) & ST0_CU1))) { \
clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
- prev->cpus_allowed = prev->thread.user_cpus_allowed; \
+ prev->cpus_mask = prev->thread.user_cpus_allowed; \
} \
next->thread.emulated_fp = 0; \
} while(0)
@@ -84,7 +84,8 @@
* Check FCSR for any unmasked exceptions pending set with `ptrace',
* clear them and send a signal.
*/
-#define __sanitize_fcr31(next) \
+#ifdef CONFIG_MIPS_FP_SUPPORT
+# define __sanitize_fcr31(next) \
do { \
unsigned long fcr31 = mask_fcr31_x(next->thread.fpu.fcr31); \
void __user *pc; \
@@ -95,6 +96,9 @@
force_fcr31_sig(fcr31, pc, next); \
} \
} while (0)
+#else
+# define __sanitize_fcr31(next)
+#endif
/*
* For newly created kernel threads switch_to() will return to
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index 6cf8ffb..25fa651 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -54,7 +54,7 @@
task_thread_info(task)->syscall = regs->regs[2];
}
-static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
+static inline void mips_get_syscall_arg(unsigned long *arg,
struct task_struct *task, struct pt_regs *regs, unsigned int n)
{
unsigned long usp __maybe_unused = regs->regs[29];
@@ -63,23 +63,24 @@
case 0: case 1: case 2: case 3:
*arg = regs->regs[4 + n];
- return 0;
+ return;
#ifdef CONFIG_32BIT
case 4: case 5: case 6: case 7:
- return get_user(*arg, (int *)usp + n);
+ get_user(*arg, (int *)usp + n);
+ return;
#endif
#ifdef CONFIG_64BIT
case 4: case 5: case 6: case 7:
#ifdef CONFIG_MIPS32_O32
if (test_tsk_thread_flag(task, TIF_32BIT_REGS))
- return get_user(*arg, (int *)usp + n);
+ get_user(*arg, (int *)usp + n);
else
#endif
*arg = regs->regs[4 + n];
- return 0;
+ return;
#endif
default:
@@ -89,6 +90,12 @@
unreachable();
}
+static inline long syscall_get_error(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ return regs->regs[7] ? -regs->regs[2] : 0;
+}
+
static inline long syscall_get_return_value(struct task_struct *task,
struct pt_regs *regs)
{
@@ -116,38 +123,31 @@
static inline void syscall_get_arguments(struct task_struct *task,
struct pt_regs *regs,
- unsigned int i, unsigned int n,
unsigned long *args)
{
- int ret;
+ unsigned int i = 0;
+ unsigned int n = 6;
/* O32 ABI syscall() */
if (mips_syscall_is_indirect(task, regs))
i++;
while (n--)
- ret |= mips_get_syscall_arg(args++, task, regs, i++);
-
- /*
- * No way to communicate an error because this is a void function.
- */
-#if 0
- return ret;
-#endif
+ mips_get_syscall_arg(args++, task, regs, i++);
}
extern const unsigned long sys_call_table[];
extern const unsigned long sys32_call_table[];
extern const unsigned long sysn32_call_table[];
-static inline int syscall_get_arch(void)
+static inline int syscall_get_arch(struct task_struct *task)
{
int arch = AUDIT_ARCH_MIPS;
#ifdef CONFIG_64BIT
- if (!test_thread_flag(TIF_32BIT_REGS)) {
+ if (!test_tsk_thread_flag(task, TIF_32BIT_REGS)) {
arch |= __AUDIT_ARCH_64BIT;
/* N32 sets only TIF_32BIT_ADDR */
- if (test_thread_flag(TIF_32BIT_ADDR))
+ if (test_tsk_thread_flag(task, TIF_32BIT_ADDR))
arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
}
#endif
diff --git a/arch/mips/include/asm/termios.h b/arch/mips/include/asm/termios.h
index ce2d72e..bc29eea 100644
--- a/arch/mips/include/asm/termios.h
+++ b/arch/mips/include/asm/termios.h
@@ -32,7 +32,7 @@
unsigned short iflag, oflag, cflag, lflag;
unsigned int err;
- if (!access_ok(VERIFY_READ, termio, sizeof(struct termio)))
+ if (!access_ok(termio, sizeof(struct termio)))
return -EFAULT;
err = __get_user(iflag, &termio->c_iflag);
@@ -61,7 +61,7 @@
{
int err;
- if (!access_ok(VERIFY_WRITE, termio, sizeof(struct termio)))
+ if (!access_ok(termio, sizeof(struct termio)))
return -EFAULT;
err = __put_user(termios->c_iflag, &termio->c_iflag);
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index b85ec64..e855a36 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2001, 2002, MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
@@ -5,11 +6,6 @@
*
* include/asm-mips/time.h
* header file for the new style time.c file and time services.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef _ASM_TIME_H
#define _ASM_TIME_H
diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
index b6823b9..90f3ad7 100644
--- a/arch/mips/include/asm/tlb.h
+++ b/arch/mips/include/asm/tlb.h
@@ -5,23 +5,6 @@
#include <asm/cpu-features.h>
#include <asm/mipsregs.h>
-/*
- * MIPS doesn't need any special per-pte or per-vma handling, except
- * we need to flush cache for area to be unmapped.
- */
-#define tlb_start_vma(tlb, vma) \
- do { \
- if (!tlb->fullmm) \
- flush_cache_range(vma, vma->vm_start, vma->vm_end); \
- } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it fills up.
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
#define _UNIQUE_ENTRYHI(base, idx) \
(((base) + ((idx) << (PAGE_SHIFT + 1))) | \
(cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
diff --git a/arch/mips/include/asm/tlbflush.h b/arch/mips/include/asm/tlbflush.h
index 40a3610..9789e7a 100644
--- a/arch/mips/include/asm/tlbflush.h
+++ b/arch/mips/include/asm/tlbflush.h
@@ -14,7 +14,6 @@
* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
*/
extern void local_flush_tlb_all(void);
-extern void local_flush_tlb_mm(struct mm_struct *mm);
extern void local_flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end);
extern void local_flush_tlb_kernel_range(unsigned long start,
@@ -23,6 +22,8 @@
unsigned long page);
extern void local_flush_tlb_one(unsigned long vaddr);
+#include <asm/mmu_context.h>
+
#ifdef CONFIG_SMP
extern void flush_tlb_all(void);
@@ -36,7 +37,7 @@
#else /* CONFIG_SMP */
#define flush_tlb_all() local_flush_tlb_all()
-#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
+#define flush_tlb_mm(mm) drop_mmu_context(mm)
#define flush_tlb_range(vma, vmaddr, end) local_flush_tlb_range(vma, vmaddr, end)
#define flush_tlb_kernel_range(vmaddr,end) \
local_flush_tlb_kernel_range(vmaddr, end)
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index f41cf3e..6a0864b 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Trap handling definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_TRAPS_H
#define _ASM_TRAPS_H
diff --git a/arch/mips/include/asm/txx9/dmac.h b/arch/mips/include/asm/txx9/dmac.h
index 5e9151f..b47ef5f 100644
--- a/arch/mips/include/asm/txx9/dmac.h
+++ b/arch/mips/include/asm/txx9/dmac.h
@@ -1,9 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* TXx9 SoC DMA Controller
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#ifndef __ASM_TXX9_DMAC_H
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index 0662901..62b298c 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -69,7 +69,6 @@
#define USER_DS ((mm_segment_t) { __UA_LIMIT })
#endif
-#define get_ds() (KERNEL_DS)
#define get_fs() (current_thread_info()->addr_limit)
#define set_fs(x) (current_thread_info()->addr_limit = (x))
@@ -109,9 +108,6 @@
/*
* access_ok: - Checks if a user space pointer is valid
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that
- * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
- * to write to a block, it is always safe to read from it.
* @addr: User space pointer to start of block to check
* @size: Size of block to check
*
@@ -134,7 +130,7 @@
return (get_fs().seg & (addr | (addr + size) | __ua_size(size))) == 0;
}
-#define access_ok(type, addr, size) \
+#define access_ok(addr, size) \
likely(__access_ok((addr), (size)))
/*
@@ -304,7 +300,7 @@
const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \
\
might_fault(); \
- if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) { \
+ if (likely(access_ok( __gu_ptr, size))) { \
if (eva_kernel_access()) \
__get_kernel_common((x), size, __gu_ptr); \
else \
@@ -446,7 +442,7 @@
int __pu_err = -EFAULT; \
\
might_fault(); \
- if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \
+ if (likely(access_ok( __pu_addr, size))) { \
if (eva_kernel_access()) \
__put_kernel_common(__pu_addr, size); \
else \
@@ -691,8 +687,7 @@
({ \
void __user * __cl_addr = (addr); \
unsigned long __cl_size = (n); \
- if (__cl_size && access_ok(VERIFY_WRITE, \
- __cl_addr, __cl_size)) \
+ if (__cl_size && access_ok(__cl_addr, __cl_size)) \
__cl_size = __clear_user(__cl_addr, __cl_size); \
__cl_size; \
})
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 59dae37..f7effca 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -86,14 +86,18 @@
Ip_u2u1s3(_daddiu);
Ip_u3u1u2(_daddu);
Ip_u1u2(_ddivu);
+Ip_u3u1u2(_ddivu_r6);
Ip_u1(_di);
Ip_u2u1msbu3(_dins);
Ip_u2u1msbu3(_dinsm);
Ip_u2u1msbu3(_dinsu);
Ip_u1u2(_divu);
+Ip_u3u1u2(_divu_r6);
Ip_u1u2u3(_dmfc0);
+Ip_u3u1u2(_dmodu);
Ip_u1u2u3(_dmtc0);
Ip_u1u2(_dmultu);
+Ip_u3u1u2(_dmulu);
Ip_u2u1u3(_drotr);
Ip_u2u1u3(_drotr32);
Ip_u2u1(_dsbh);
@@ -131,6 +135,7 @@
Ip_u1u2u3(_mfhc0);
Ip_u1(_mfhi);
Ip_u1(_mflo);
+Ip_u3u1u2(_modu);
Ip_u3u1u2(_movn);
Ip_u3u1u2(_movz);
Ip_u1u2u3(_mtc0);
@@ -139,6 +144,7 @@
Ip_u1(_mtlo);
Ip_u3u1u2(_mul);
Ip_u1u2(_multu);
+Ip_u3u1u2(_mulu);
Ip_u3u1u2(_nor);
Ip_u3u1u2(_or);
Ip_u2u1u3(_ori);
@@ -149,6 +155,8 @@
Ip_u2s3u1(_sc);
Ip_u2s3u1(_scd);
Ip_u2s3u1(_sd);
+Ip_u3u1u2(_seleqz);
+Ip_u3u1u2(_selnez);
Ip_u2s3u1(_sh);
Ip_u2u1u3(_sll);
Ip_u3u2u1(_sllv);
@@ -157,6 +165,7 @@
Ip_u2u1s3(_sltiu);
Ip_u3u1u2(_sltu);
Ip_u2u1u3(_sra);
+Ip_u3u2u1(_srav);
Ip_u2u1u3(_srl);
Ip_u3u2u1(_srlv);
Ip_u3u1u2(_subu);
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 3c09450..5d70bab 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -13,6 +13,9 @@
#define _ASM_UNISTD_H
#include <uapi/asm/unistd.h>
+#include <asm/unistd_nr_n32.h>
+#include <asm/unistd_nr_n64.h>
+#include <asm/unistd_nr_o32.h>
#ifdef CONFIG_MIPS32_N32
#define NR_syscalls (__NR_N32_Linux + __NR_N32_Linux_syscalls)
@@ -24,16 +27,17 @@
#ifndef __ASSEMBLY__
+#define __ARCH_WANT_NEW_STAT
#define __ARCH_WANT_OLD_READDIR
#define __ARCH_WANT_SYS_ALARM
#define __ARCH_WANT_SYS_GETHOSTNAME
#define __ARCH_WANT_SYS_IPC
#define __ARCH_WANT_SYS_PAUSE
#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_UTIME32
#define __ARCH_WANT_SYS_WAITPID
#define __ARCH_WANT_SYS_SOCKETCALL
#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
#define __ARCH_WANT_SYS_NICE
#define __ARCH_WANT_SYS_OLD_UNAME
#define __ARCH_WANT_SYS_OLDUMOUNT
@@ -41,29 +45,17 @@
#define __ARCH_WANT_SYS_SIGPROCMASK
# ifdef CONFIG_32BIT
# define __ARCH_WANT_STAT64
-# define __ARCH_WANT_SYS_TIME
+# define __ARCH_WANT_SYS_TIME32
# endif
# ifdef CONFIG_MIPS32_O32
-# define __ARCH_WANT_COMPAT_SYS_TIME
+# define __ARCH_WANT_SYS_TIME32
# endif
#define __ARCH_WANT_SYS_FORK
#define __ARCH_WANT_SYS_CLONE
+#define __ARCH_WANT_SYS_CLONE3
/* whitelists for checksyscalls */
-#define __IGNORE_select
-#define __IGNORE_vfork
-#define __IGNORE_time
-#define __IGNORE_uselib
#define __IGNORE_fadvise64_64
-#define __IGNORE_getdents64
-#if _MIPS_SIM == _MIPS_SIM_NABI32
-#define __IGNORE_truncate64
-#define __IGNORE_ftruncate64
-#define __IGNORE_stat64
-#define __IGNORE_lstat64
-#define __IGNORE_fstat64
-#define __IGNORE_fstatat64
-#endif
#endif /* !__ASSEMBLY__ */
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
index 91bf0c2..cc7b516 100644
--- a/arch/mips/include/asm/vdso.h
+++ b/arch/mips/include/asm/vdso.h
@@ -1,17 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2015 Imagination Technologies
* Author: Alex Smith <alex.smith@imgtec.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __ASM_VDSO_H
#define __ASM_VDSO_H
#include <linux/mm_types.h>
+#include <vdso/datapage.h>
#include <asm/barrier.h>
@@ -53,84 +50,9 @@
extern struct mips_vdso_image vdso_image_n32;
#endif
-/**
- * union mips_vdso_data - Data provided by the kernel for the VDSO.
- * @xtime_sec: Current real time (seconds part).
- * @xtime_nsec: Current real time (nanoseconds part, shifted).
- * @wall_to_mono_sec: Wall-to-monotonic offset (seconds part).
- * @wall_to_mono_nsec: Wall-to-monotonic offset (nanoseconds part).
- * @seq_count: Counter to synchronise updates (odd = updating).
- * @cs_shift: Clocksource shift value.
- * @clock_mode: Clocksource to use for time functions.
- * @cs_mult: Clocksource multiplier value.
- * @cs_cycle_last: Clock cycle value at last update.
- * @cs_mask: Clocksource mask value.
- * @tz_minuteswest: Minutes west of Greenwich (from timezone).
- * @tz_dsttime: Type of DST correction (from timezone).
- *
- * This structure contains data needed by functions within the VDSO. It is
- * populated by the kernel and mapped read-only into user memory. The time
- * fields are mirrors of internal data from the timekeeping infrastructure.
- *
- * Note: Care should be taken when modifying as the layout must remain the same
- * for both 64- and 32-bit (for 32-bit userland on 64-bit kernel).
- */
union mips_vdso_data {
- struct {
- u64 xtime_sec;
- u64 xtime_nsec;
- u64 wall_to_mono_sec;
- u64 wall_to_mono_nsec;
- u32 seq_count;
- u32 cs_shift;
- u8 clock_mode;
- u32 cs_mult;
- u64 cs_cycle_last;
- u64 cs_mask;
- s32 tz_minuteswest;
- s32 tz_dsttime;
- };
-
+ struct vdso_data data[CS_BASES];
u8 page[PAGE_SIZE];
};
-static inline u32 vdso_data_read_begin(const union mips_vdso_data *data)
-{
- u32 seq;
-
- while (true) {
- seq = READ_ONCE(data->seq_count);
- if (likely(!(seq & 1))) {
- /* Paired with smp_wmb() in vdso_data_write_*(). */
- smp_rmb();
- return seq;
- }
-
- cpu_relax();
- }
-}
-
-static inline bool vdso_data_read_retry(const union mips_vdso_data *data,
- u32 start_seq)
-{
- /* Paired with smp_wmb() in vdso_data_write_*(). */
- smp_rmb();
- return unlikely(data->seq_count != start_seq);
-}
-
-static inline void vdso_data_write_begin(union mips_vdso_data *data)
-{
- ++data->seq_count;
-
- /* Ensure sequence update is written before other data page values. */
- smp_wmb();
-}
-
-static inline void vdso_data_write_end(union mips_vdso_data *data)
-{
- /* Ensure data values are written before updating sequence again. */
- smp_wmb();
- ++data->seq_count;
-}
-
#endif /* __ASM_VDSO_H */
diff --git a/arch/mips/include/asm/vdso/gettimeofday.h b/arch/mips/include/asm/vdso/gettimeofday.h
new file mode 100644
index 0000000..b088255
--- /dev/null
+++ b/arch/mips/include/asm/vdso/gettimeofday.h
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2018 ARM Limited
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.smith@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __ASM_VDSO_GETTIMEOFDAY_H
+#define __ASM_VDSO_GETTIMEOFDAY_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+#include <linux/time.h>
+
+#include <asm/vdso/vdso.h>
+#include <asm/clocksource.h>
+#include <asm/io.h>
+#include <asm/unistd.h>
+#include <asm/vdso.h>
+
+#define VDSO_HAS_CLOCK_GETRES 1
+
+#define __VDSO_USE_SYSCALL ULLONG_MAX
+
+#ifdef CONFIG_MIPS_CLOCK_VSYSCALL
+
+static __always_inline long gettimeofday_fallback(
+ struct __kernel_old_timeval *_tv,
+ struct timezone *_tz)
+{
+ register struct timezone *tz asm("a1") = _tz;
+ register struct __kernel_old_timeval *tv asm("a0") = _tv;
+ register long ret asm("v0");
+ register long nr asm("v0") = __NR_gettimeofday;
+ register long error asm("a3");
+
+ asm volatile(
+ " syscall\n"
+ : "=r" (ret), "=r" (error)
+ : "r" (tv), "r" (tz), "r" (nr)
+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+ "$14", "$15", "$24", "$25", "hi", "lo", "memory");
+
+ return error ? -ret : ret;
+}
+
+#else
+
+static __always_inline long gettimeofday_fallback(
+ struct __kernel_old_timeval *_tv,
+ struct timezone *_tz)
+{
+ return -1;
+}
+
+#endif
+
+static __always_inline long clock_gettime_fallback(
+ clockid_t _clkid,
+ struct __kernel_timespec *_ts)
+{
+ register struct __kernel_timespec *ts asm("a1") = _ts;
+ register clockid_t clkid asm("a0") = _clkid;
+ register long ret asm("v0");
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+ register long nr asm("v0") = __NR_clock_gettime;
+#else
+ register long nr asm("v0") = __NR_clock_gettime64;
+#endif
+ register long error asm("a3");
+
+ asm volatile(
+ " syscall\n"
+ : "=r" (ret), "=r" (error)
+ : "r" (clkid), "r" (ts), "r" (nr)
+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+ "$14", "$15", "$24", "$25", "hi", "lo", "memory");
+
+ return error ? -ret : ret;
+}
+
+static __always_inline int clock_getres_fallback(
+ clockid_t _clkid,
+ struct __kernel_timespec *_ts)
+{
+ register struct __kernel_timespec *ts asm("a1") = _ts;
+ register clockid_t clkid asm("a0") = _clkid;
+ register long ret asm("v0");
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+ register long nr asm("v0") = __NR_clock_getres;
+#else
+ register long nr asm("v0") = __NR_clock_getres_time64;
+#endif
+ register long error asm("a3");
+
+ asm volatile(
+ " syscall\n"
+ : "=r" (ret), "=r" (error)
+ : "r" (clkid), "r" (ts), "r" (nr)
+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+ "$14", "$15", "$24", "$25", "hi", "lo", "memory");
+
+ return error ? -ret : ret;
+}
+
+#if _MIPS_SIM != _MIPS_SIM_ABI64
+
+#define VDSO_HAS_32BIT_FALLBACK 1
+
+static __always_inline long clock_gettime32_fallback(
+ clockid_t _clkid,
+ struct old_timespec32 *_ts)
+{
+ register struct old_timespec32 *ts asm("a1") = _ts;
+ register clockid_t clkid asm("a0") = _clkid;
+ register long ret asm("v0");
+ register long nr asm("v0") = __NR_clock_gettime;
+ register long error asm("a3");
+
+ asm volatile(
+ " syscall\n"
+ : "=r" (ret), "=r" (error)
+ : "r" (clkid), "r" (ts), "r" (nr)
+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+ "$14", "$15", "$24", "$25", "hi", "lo", "memory");
+
+ return error ? -ret : ret;
+}
+
+static __always_inline int clock_getres32_fallback(
+ clockid_t _clkid,
+ struct old_timespec32 *_ts)
+{
+ register struct old_timespec32 *ts asm("a1") = _ts;
+ register clockid_t clkid asm("a0") = _clkid;
+ register long ret asm("v0");
+ register long nr asm("v0") = __NR_clock_getres;
+ register long error asm("a3");
+
+ asm volatile(
+ " syscall\n"
+ : "=r" (ret), "=r" (error)
+ : "r" (clkid), "r" (ts), "r" (nr)
+ : "$1", "$3", "$8", "$9", "$10", "$11", "$12", "$13",
+ "$14", "$15", "$24", "$25", "hi", "lo", "memory");
+
+ return error ? -ret : ret;
+}
+#endif
+
+#ifdef CONFIG_CSRC_R4K
+
+static __always_inline u64 read_r4k_count(void)
+{
+ unsigned int count;
+
+ __asm__ __volatile__(
+ " .set push\n"
+ " .set mips32r2\n"
+ " rdhwr %0, $2\n"
+ " .set pop\n"
+ : "=r" (count));
+
+ return count;
+}
+
+#endif
+
+#ifdef CONFIG_CLKSRC_MIPS_GIC
+
+static __always_inline u64 read_gic_count(const struct vdso_data *data)
+{
+ void __iomem *gic = get_gic(data);
+ u32 hi, hi2, lo;
+
+ do {
+ hi = __raw_readl(gic + sizeof(lo));
+ lo = __raw_readl(gic);
+ hi2 = __raw_readl(gic + sizeof(lo));
+ } while (hi2 != hi);
+
+ return (((u64)hi) << 32) + lo;
+}
+
+#endif
+
+static __always_inline u64 __arch_get_hw_counter(s32 clock_mode)
+{
+#ifdef CONFIG_CLKSRC_MIPS_GIC
+ const struct vdso_data *data = get_vdso_data();
+#endif
+ u64 cycle_now;
+
+ switch (clock_mode) {
+#ifdef CONFIG_CSRC_R4K
+ case VDSO_CLOCK_R4K:
+ cycle_now = read_r4k_count();
+ break;
+#endif
+#ifdef CONFIG_CLKSRC_MIPS_GIC
+ case VDSO_CLOCK_GIC:
+ cycle_now = read_gic_count(data);
+ break;
+#endif
+ default:
+ cycle_now = __VDSO_USE_SYSCALL;
+ break;
+ }
+
+ return cycle_now;
+}
+
+static __always_inline const struct vdso_data *__arch_get_vdso_data(void)
+{
+ return get_vdso_data();
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_VDSO_GETTIMEOFDAY_H */
diff --git a/arch/mips/include/asm/vdso/vdso.h b/arch/mips/include/asm/vdso/vdso.h
new file mode 100644
index 0000000..737ddfc
--- /dev/null
+++ b/arch/mips/include/asm/vdso/vdso.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.smith@imgtec.com>
+ */
+
+#include <asm/sgidefs.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/asm.h>
+#include <asm/page.h>
+#include <asm/vdso.h>
+
+static inline unsigned long get_vdso_base(void)
+{
+ unsigned long addr;
+
+ /*
+ * We can't use cpu_has_mips_r6 since it needs the cpu_data[]
+ * kernel symbol.
+ */
+#ifdef CONFIG_CPU_MIPSR6
+ /*
+ * lapc <symbol> is an alias to addiupc reg, <symbol> - .
+ *
+ * We can't use addiupc because there is no label-label
+ * support for the addiupc reloc
+ */
+ __asm__("lapc %0, _start \n"
+ : "=r" (addr) : :);
+#else
+ /*
+ * Get the base load address of the VDSO. We have to avoid generating
+ * relocations and references to the GOT because ld.so does not peform
+ * relocations on the VDSO. We use the current offset from the VDSO base
+ * and perform a PC-relative branch which gives the absolute address in
+ * ra, and take the difference. The assembler chokes on
+ * "li %0, _start - .", so embed the offset as a word and branch over
+ * it.
+ *
+ */
+
+ __asm__(
+ " .set push \n"
+ " .set noreorder \n"
+ " bal 1f \n"
+ " nop \n"
+ " .word _start - . \n"
+ "1: lw %0, 0($31) \n"
+ " " STR(PTR_ADDU) " %0, $31, %0 \n"
+ " .set pop \n"
+ : "=r" (addr)
+ :
+ : "$31");
+#endif /* CONFIG_CPU_MIPSR6 */
+
+ return addr;
+}
+
+static inline const struct vdso_data *get_vdso_data(void)
+{
+ return (const struct vdso_data *)(get_vdso_base() - PAGE_SIZE);
+}
+
+#ifdef CONFIG_CLKSRC_MIPS_GIC
+
+static inline void __iomem *get_gic(const struct vdso_data *data)
+{
+ return (void __iomem *)data - PAGE_SIZE;
+}
+
+#endif /* CONFIG_CLKSRC_MIPS_GIC */
+
+#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/vdso/vsyscall.h b/arch/mips/include/asm/vdso/vsyscall.h
new file mode 100644
index 0000000..00d41b9
--- /dev/null
+++ b/arch/mips/include/asm/vdso/vsyscall.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_VDSO_VSYSCALL_H
+#define __ASM_VDSO_VSYSCALL_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/timekeeper_internal.h>
+#include <vdso/datapage.h>
+
+extern struct vdso_data *vdso_data;
+
+/*
+ * Update the vDSO data page to keep in sync with kernel timekeeping.
+ */
+static __always_inline
+struct vdso_data *__mips_get_k_vdso_data(void)
+{
+ return vdso_data;
+}
+#define __arch_get_k_vdso_data __mips_get_k_vdso_data
+
+static __always_inline
+int __mips_get_clock_mode(struct timekeeper *tk)
+{
+ u32 clock_mode = tk->tkr_mono.clock->archdata.vdso_clock_mode;
+
+ return clock_mode;
+}
+#define __arch_get_clock_mode __mips_get_clock_mode
+
+/* The asm-generic header needs to be included after the definitions above */
+#include <asm-generic/vdso/vsyscall.h>
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_VDSO_VSYSCALL_H */
diff --git a/arch/mips/include/asm/vr41xx/capcella.h b/arch/mips/include/asm/vr41xx/capcella.h
index fcc6569..d45a339 100644
--- a/arch/mips/include/asm/vr41xx/capcella.h
+++ b/arch/mips/include/asm/vr41xx/capcella.h
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* capcella.h, Include file for ZAO Networks Capcella.
*
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ZAO_CAPCELLA_H
#define __ZAO_CAPCELLA_H
diff --git a/arch/mips/include/asm/vr41xx/giu.h b/arch/mips/include/asm/vr41xx/giu.h
index 6a90bc1..0211fa8 100644
--- a/arch/mips/include/asm/vr41xx/giu.h
+++ b/arch/mips/include/asm/vr41xx/giu.h
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Include file for NEC VR4100 series General-purpose I/O Unit.
*
* Copyright (C) 2005-2009 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __NEC_VR41XX_GIU_H
#define __NEC_VR41XX_GIU_H
@@ -51,12 +38,4 @@
extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level);
-typedef enum {
- GPIO_PULL_DOWN,
- GPIO_PULL_UP,
- GPIO_PULL_DISABLE,
-} gpio_pull_t;
-
-extern int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull);
-
#endif /* __NEC_VR41XX_GIU_H */
diff --git a/arch/mips/include/asm/vr41xx/irq.h b/arch/mips/include/asm/vr41xx/irq.h
index b07f732..2f3d552 100644
--- a/arch/mips/include/asm/vr41xx/irq.h
+++ b/arch/mips/include/asm/vr41xx/irq.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/vr41xx/irq.h
*
@@ -8,11 +9,6 @@
* Copyright (C) 2002 MontaVista Software, Inc.
* Copyright (C) 2002 TimeSys Corp.
* Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __NEC_VR41XX_IRQ_H
#define __NEC_VR41XX_IRQ_H
diff --git a/arch/mips/include/asm/vr41xx/mpc30x.h b/arch/mips/include/asm/vr41xx/mpc30x.h
index 130d09d..9f977e1 100644
--- a/arch/mips/include/asm/vr41xx/mpc30x.h
+++ b/arch/mips/include/asm/vr41xx/mpc30x.h
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* mpc30x.h, Include file for Victor MP-C303/304.
*
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __VICTOR_MPC30X_H
#define __VICTOR_MPC30X_H
diff --git a/arch/mips/include/asm/vr41xx/pci.h b/arch/mips/include/asm/vr41xx/pci.h
index a866918..ad93b5e 100644
--- a/arch/mips/include/asm/vr41xx/pci.h
+++ b/arch/mips/include/asm/vr41xx/pci.h
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Include file for NEC VR4100 series PCI Control Unit.
*
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __NEC_VR41XX_PCI_H
#define __NEC_VR41XX_PCI_H
diff --git a/arch/mips/include/asm/vr41xx/siu.h b/arch/mips/include/asm/vr41xx/siu.h
index ca806bc..e920cd2 100644
--- a/arch/mips/include/asm/vr41xx/siu.h
+++ b/arch/mips/include/asm/vr41xx/siu.h
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Include file for NEC VR4100 series Serial Interface Unit.
*
* Copyright (C) 2005-2008 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __NEC_VR41XX_SIU_H
#define __NEC_VR41XX_SIU_H
diff --git a/arch/mips/include/asm/vr41xx/tb0219.h b/arch/mips/include/asm/vr41xx/tb0219.h
index c78e824..01e96d6 100644
--- a/arch/mips/include/asm/vr41xx/tb0219.h
+++ b/arch/mips/include/asm/vr41xx/tb0219.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* tb0219.h, Include file for TANBAC TB0219.
*
@@ -5,20 +6,6 @@
*
* Modified for TANBAC TB0219:
* Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __TANBAC_TB0219_H
#define __TANBAC_TB0219_H
diff --git a/arch/mips/include/asm/vr41xx/tb0226.h b/arch/mips/include/asm/vr41xx/tb0226.h
index 36f5f79..64993d1 100644
--- a/arch/mips/include/asm/vr41xx/tb0226.h
+++ b/arch/mips/include/asm/vr41xx/tb0226.h
@@ -1,21 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* tb0226.h, Include file for TANBAC TB0226.
*
* Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __TANBAC_TB0226_H
#define __TANBAC_TB0226_H
diff --git a/arch/mips/include/asm/vr41xx/tb0287.h b/arch/mips/include/asm/vr41xx/tb0287.h
index d58b567..3ddc913 100644
--- a/arch/mips/include/asm/vr41xx/tb0287.h
+++ b/arch/mips/include/asm/vr41xx/tb0287.h
@@ -1,23 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* tb0287.h, Include file for TANBAC TB0287 mini-ITX board.
*
* Copyright (C) 2005 Media Lab Inc. <ito@mlb.co.jp>
*
* This code is largely based on tb0219.h.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __TANBAC_TB0287_H
#define __TANBAC_TB0287_H
diff --git a/arch/mips/include/asm/vr41xx/vr41xx.h b/arch/mips/include/asm/vr41xx/vr41xx.h
index 7b96a43..9a4b36b 100644
--- a/arch/mips/include/asm/vr41xx/vr41xx.h
+++ b/arch/mips/include/asm/vr41xx/vr41xx.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/vr41xx/vr41xx.h
*
@@ -8,11 +9,6 @@
* Copyright (C) 2002 MontaVista Software, Inc.
* Copyright (C) 2002 TimeSys Corp.
* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __NEC_VR41XX_H
#define __NEC_VR41XX_H
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 9344e24..1eedd59 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -129,19 +129,6 @@
#endif
/*
- * When an interrupt happens on a CP0 register read instruction, CPU may
- * lock up or read corrupted values of CP0 registers after it enters
- * the exception handler.
- *
- * This workaround makes sure that we read a "safe" CP0 register as the
- * first thing in the exception handler, which breaks one of the
- * pre-conditions for this problem.
- */
-#ifndef R5432_CP0_INTERRUPT_WAR
-#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
-#endif
-
-/*
* Workaround for the Sibyte M3 errata the text of which can be found at
*
* http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h
index 26d2ed1..680e7ef 100644
--- a/arch/mips/include/asm/xtalk/xtalk.h
+++ b/arch/mips/include/asm/xtalk/xtalk.h
@@ -47,15 +47,6 @@
#define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
-#ifdef CONFIG_PCI
-extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
-#else
-static inline int bridge_probe(nasid_t nasid, int widget, int masterwid)
-{
- return 0;
-}
-#endif
-
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_XTALK_XTALK_H */
diff --git a/arch/mips/include/asm/yamon-dt.h b/arch/mips/include/asm/yamon-dt.h
index 10a073e..e204755 100644
--- a/arch/mips/include/asm/yamon-dt.h
+++ b/arch/mips/include/asm/yamon-dt.h
@@ -1,11 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2016 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#ifndef __MIPS_ASM_YAMON_DT_H__