Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * platform.c - DesignWare HS OTG Controller platform driver |
| 4 | * |
| 5 | * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl> |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions, and the following disclaimer, |
| 12 | * without modification. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * 3. The names of the above-listed copyright holders may not be used |
| 17 | * to endorse or promote products derived from this software without |
| 18 | * specific prior written permission. |
| 19 | * |
| 20 | * ALTERNATIVELY, this software may be distributed under the terms of the |
| 21 | * GNU General Public License ("GPL") as published by the Free Software |
| 22 | * Foundation; either version 2 of the License, or (at your option) any |
| 23 | * later version. |
| 24 | * |
| 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| 26 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 27 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 29 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 30 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 31 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 32 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 33 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 34 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 35 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 36 | */ |
| 37 | |
| 38 | #include <linux/kernel.h> |
| 39 | #include <linux/module.h> |
| 40 | #include <linux/slab.h> |
| 41 | #include <linux/clk.h> |
| 42 | #include <linux/device.h> |
| 43 | #include <linux/dma-mapping.h> |
| 44 | #include <linux/of_device.h> |
| 45 | #include <linux/mutex.h> |
| 46 | #include <linux/platform_device.h> |
| 47 | #include <linux/phy/phy.h> |
| 48 | #include <linux/platform_data/s3c-hsotg.h> |
| 49 | #include <linux/reset.h> |
| 50 | |
| 51 | #include <linux/usb/of.h> |
| 52 | |
| 53 | #include "core.h" |
| 54 | #include "hcd.h" |
| 55 | #include "debug.h" |
| 56 | |
| 57 | static const char dwc2_driver_name[] = "dwc2"; |
| 58 | |
| 59 | /* |
| 60 | * Check the dr_mode against the module configuration and hardware |
| 61 | * capabilities. |
| 62 | * |
| 63 | * The hardware, module, and dr_mode, can each be set to host, device, |
| 64 | * or otg. Check that all these values are compatible and adjust the |
| 65 | * value of dr_mode if possible. |
| 66 | * |
| 67 | * actual |
| 68 | * HW MOD dr_mode dr_mode |
| 69 | * ------------------------------ |
| 70 | * HST HST any : HST |
| 71 | * HST DEV any : --- |
| 72 | * HST OTG any : HST |
| 73 | * |
| 74 | * DEV HST any : --- |
| 75 | * DEV DEV any : DEV |
| 76 | * DEV OTG any : DEV |
| 77 | * |
| 78 | * OTG HST any : HST |
| 79 | * OTG DEV any : DEV |
| 80 | * OTG OTG any : dr_mode |
| 81 | */ |
| 82 | static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg) |
| 83 | { |
| 84 | enum usb_dr_mode mode; |
| 85 | |
| 86 | hsotg->dr_mode = usb_get_dr_mode(hsotg->dev); |
| 87 | if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN) |
| 88 | hsotg->dr_mode = USB_DR_MODE_OTG; |
| 89 | |
| 90 | mode = hsotg->dr_mode; |
| 91 | |
| 92 | if (dwc2_hw_is_device(hsotg)) { |
| 93 | if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) { |
| 94 | dev_err(hsotg->dev, |
| 95 | "Controller does not support host mode.\n"); |
| 96 | return -EINVAL; |
| 97 | } |
| 98 | mode = USB_DR_MODE_PERIPHERAL; |
| 99 | } else if (dwc2_hw_is_host(hsotg)) { |
| 100 | if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) { |
| 101 | dev_err(hsotg->dev, |
| 102 | "Controller does not support device mode.\n"); |
| 103 | return -EINVAL; |
| 104 | } |
| 105 | mode = USB_DR_MODE_HOST; |
| 106 | } else { |
| 107 | if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) |
| 108 | mode = USB_DR_MODE_HOST; |
| 109 | else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) |
| 110 | mode = USB_DR_MODE_PERIPHERAL; |
| 111 | } |
| 112 | |
| 113 | if (mode != hsotg->dr_mode) { |
| 114 | dev_warn(hsotg->dev, |
| 115 | "Configuration mismatch. dr_mode forced to %s\n", |
| 116 | mode == USB_DR_MODE_HOST ? "host" : "device"); |
| 117 | |
| 118 | hsotg->dr_mode = mode; |
| 119 | } |
| 120 | |
| 121 | return 0; |
| 122 | } |
| 123 | |
| 124 | static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) |
| 125 | { |
| 126 | struct platform_device *pdev = to_platform_device(hsotg->dev); |
| 127 | int ret; |
| 128 | |
| 129 | ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), |
| 130 | hsotg->supplies); |
| 131 | if (ret) |
| 132 | return ret; |
| 133 | |
| 134 | if (hsotg->clk) { |
| 135 | ret = clk_prepare_enable(hsotg->clk); |
| 136 | if (ret) |
| 137 | return ret; |
| 138 | } |
| 139 | |
| 140 | if (hsotg->uphy) { |
| 141 | ret = usb_phy_init(hsotg->uphy); |
| 142 | } else if (hsotg->plat && hsotg->plat->phy_init) { |
| 143 | ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); |
| 144 | } else { |
| 145 | ret = phy_power_on(hsotg->phy); |
| 146 | if (ret == 0) |
| 147 | ret = phy_init(hsotg->phy); |
| 148 | } |
| 149 | |
| 150 | return ret; |
| 151 | } |
| 152 | |
| 153 | /** |
| 154 | * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources |
| 155 | * @hsotg: The driver state |
| 156 | * |
| 157 | * A wrapper for platform code responsible for controlling |
| 158 | * low-level USB platform resources (phy, clock, regulators) |
| 159 | */ |
| 160 | int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) |
| 161 | { |
| 162 | int ret = __dwc2_lowlevel_hw_enable(hsotg); |
| 163 | |
| 164 | if (ret == 0) |
| 165 | hsotg->ll_hw_enabled = true; |
| 166 | return ret; |
| 167 | } |
| 168 | |
| 169 | static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) |
| 170 | { |
| 171 | struct platform_device *pdev = to_platform_device(hsotg->dev); |
| 172 | int ret = 0; |
| 173 | |
| 174 | if (hsotg->uphy) { |
| 175 | usb_phy_shutdown(hsotg->uphy); |
| 176 | } else if (hsotg->plat && hsotg->plat->phy_exit) { |
| 177 | ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); |
| 178 | } else { |
| 179 | ret = phy_exit(hsotg->phy); |
| 180 | if (ret == 0) |
| 181 | ret = phy_power_off(hsotg->phy); |
| 182 | } |
| 183 | if (ret) |
| 184 | return ret; |
| 185 | |
| 186 | if (hsotg->clk) |
| 187 | clk_disable_unprepare(hsotg->clk); |
| 188 | |
| 189 | ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), |
| 190 | hsotg->supplies); |
| 191 | |
| 192 | return ret; |
| 193 | } |
| 194 | |
| 195 | /** |
| 196 | * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources |
| 197 | * @hsotg: The driver state |
| 198 | * |
| 199 | * A wrapper for platform code responsible for controlling |
| 200 | * low-level USB platform resources (phy, clock, regulators) |
| 201 | */ |
| 202 | int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) |
| 203 | { |
| 204 | int ret = __dwc2_lowlevel_hw_disable(hsotg); |
| 205 | |
| 206 | if (ret == 0) |
| 207 | hsotg->ll_hw_enabled = false; |
| 208 | return ret; |
| 209 | } |
| 210 | |
| 211 | static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg) |
| 212 | { |
| 213 | int i, ret; |
| 214 | |
| 215 | hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2"); |
| 216 | if (IS_ERR(hsotg->reset)) { |
| 217 | ret = PTR_ERR(hsotg->reset); |
| 218 | dev_err(hsotg->dev, "error getting reset control %d\n", ret); |
| 219 | return ret; |
| 220 | } |
| 221 | |
| 222 | reset_control_deassert(hsotg->reset); |
| 223 | |
| 224 | hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc"); |
| 225 | if (IS_ERR(hsotg->reset_ecc)) { |
| 226 | ret = PTR_ERR(hsotg->reset_ecc); |
| 227 | dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret); |
| 228 | return ret; |
| 229 | } |
| 230 | |
| 231 | reset_control_deassert(hsotg->reset_ecc); |
| 232 | |
| 233 | /* Set default UTMI width */ |
| 234 | hsotg->phyif = GUSBCFG_PHYIF16; |
| 235 | |
| 236 | /* |
| 237 | * Attempt to find a generic PHY, then look for an old style |
| 238 | * USB PHY and then fall back to pdata |
| 239 | */ |
| 240 | hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy"); |
| 241 | if (IS_ERR(hsotg->phy)) { |
| 242 | ret = PTR_ERR(hsotg->phy); |
| 243 | switch (ret) { |
| 244 | case -ENODEV: |
| 245 | case -ENOSYS: |
| 246 | hsotg->phy = NULL; |
| 247 | break; |
| 248 | case -EPROBE_DEFER: |
| 249 | return ret; |
| 250 | default: |
| 251 | dev_err(hsotg->dev, "error getting phy %d\n", ret); |
| 252 | return ret; |
| 253 | } |
| 254 | } |
| 255 | |
| 256 | if (!hsotg->phy) { |
| 257 | hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2); |
| 258 | if (IS_ERR(hsotg->uphy)) { |
| 259 | ret = PTR_ERR(hsotg->uphy); |
| 260 | switch (ret) { |
| 261 | case -ENODEV: |
| 262 | case -ENXIO: |
| 263 | hsotg->uphy = NULL; |
| 264 | break; |
| 265 | case -EPROBE_DEFER: |
| 266 | return ret; |
| 267 | default: |
| 268 | dev_err(hsotg->dev, "error getting usb phy %d\n", |
| 269 | ret); |
| 270 | return ret; |
| 271 | } |
| 272 | } |
| 273 | } |
| 274 | |
| 275 | hsotg->plat = dev_get_platdata(hsotg->dev); |
| 276 | |
| 277 | if (hsotg->phy) { |
| 278 | /* |
| 279 | * If using the generic PHY framework, check if the PHY bus |
| 280 | * width is 8-bit and set the phyif appropriately. |
| 281 | */ |
| 282 | if (phy_get_bus_width(hsotg->phy) == 8) |
| 283 | hsotg->phyif = GUSBCFG_PHYIF8; |
| 284 | } |
| 285 | |
| 286 | /* Clock */ |
| 287 | hsotg->clk = devm_clk_get(hsotg->dev, "otg"); |
| 288 | if (IS_ERR(hsotg->clk)) { |
| 289 | hsotg->clk = NULL; |
| 290 | dev_dbg(hsotg->dev, "cannot get otg clock\n"); |
| 291 | } |
| 292 | |
| 293 | /* Regulators */ |
| 294 | for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) |
| 295 | hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i]; |
| 296 | |
| 297 | ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies), |
| 298 | hsotg->supplies); |
| 299 | if (ret) { |
| 300 | dev_err(hsotg->dev, "failed to request supplies: %d\n", ret); |
| 301 | return ret; |
| 302 | } |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | /** |
| 307 | * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the |
| 308 | * DWC_otg driver |
| 309 | * |
| 310 | * @dev: Platform device |
| 311 | * |
| 312 | * This routine is called, for example, when the rmmod command is executed. The |
| 313 | * device may or may not be electrically present. If it is present, the driver |
| 314 | * stops device processing. Any resources used on behalf of this device are |
| 315 | * freed. |
| 316 | */ |
| 317 | static int dwc2_driver_remove(struct platform_device *dev) |
| 318 | { |
| 319 | struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); |
| 320 | |
| 321 | dwc2_debugfs_exit(hsotg); |
| 322 | if (hsotg->hcd_enabled) |
| 323 | dwc2_hcd_remove(hsotg); |
| 324 | if (hsotg->gadget_enabled) |
| 325 | dwc2_hsotg_remove(hsotg); |
| 326 | |
| 327 | if (hsotg->ll_hw_enabled) |
| 328 | dwc2_lowlevel_hw_disable(hsotg); |
| 329 | |
| 330 | reset_control_assert(hsotg->reset); |
| 331 | reset_control_assert(hsotg->reset_ecc); |
| 332 | |
| 333 | return 0; |
| 334 | } |
| 335 | |
| 336 | /** |
| 337 | * dwc2_driver_shutdown() - Called on device shutdown |
| 338 | * |
| 339 | * @dev: Platform device |
| 340 | * |
| 341 | * In specific conditions (involving usb hubs) dwc2 devices can create a |
| 342 | * lot of interrupts, even to the point of overwhelming devices running |
| 343 | * at low frequencies. Some devices need to do special clock handling |
| 344 | * at shutdown-time which may bring the system clock below the threshold |
| 345 | * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs |
| 346 | * prevents reboots/poweroffs from getting stuck in such cases. |
| 347 | */ |
| 348 | static void dwc2_driver_shutdown(struct platform_device *dev) |
| 349 | { |
| 350 | struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); |
| 351 | |
| 352 | disable_irq(hsotg->irq); |
| 353 | } |
| 354 | |
| 355 | /** |
| 356 | * dwc2_check_core_endianness() - Returns true if core and AHB have |
| 357 | * opposite endianness. |
| 358 | * @hsotg: Programming view of the DWC_otg controller. |
| 359 | */ |
| 360 | static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg) |
| 361 | { |
| 362 | u32 snpsid; |
| 363 | |
| 364 | snpsid = ioread32(hsotg->regs + GSNPSID); |
| 365 | if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID || |
| 366 | (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID || |
| 367 | (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID) |
| 368 | return false; |
| 369 | return true; |
| 370 | } |
| 371 | |
| 372 | /** |
| 373 | * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg |
| 374 | * driver |
| 375 | * |
| 376 | * @dev: Platform device |
| 377 | * |
| 378 | * This routine creates the driver components required to control the device |
| 379 | * (core, HCD, and PCD) and initializes the device. The driver components are |
| 380 | * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved |
| 381 | * in the device private data. This allows the driver to access the dwc2_hsotg |
| 382 | * structure on subsequent calls to driver methods for this device. |
| 383 | */ |
| 384 | static int dwc2_driver_probe(struct platform_device *dev) |
| 385 | { |
| 386 | struct dwc2_hsotg *hsotg; |
| 387 | struct resource *res; |
| 388 | int retval; |
| 389 | |
| 390 | hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); |
| 391 | if (!hsotg) |
| 392 | return -ENOMEM; |
| 393 | |
| 394 | hsotg->dev = &dev->dev; |
| 395 | |
| 396 | /* |
| 397 | * Use reasonable defaults so platforms don't have to provide these. |
| 398 | */ |
| 399 | if (!dev->dev.dma_mask) |
| 400 | dev->dev.dma_mask = &dev->dev.coherent_dma_mask; |
| 401 | retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32)); |
| 402 | if (retval) { |
| 403 | dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval); |
| 404 | return retval; |
| 405 | } |
| 406 | |
| 407 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
| 408 | hsotg->regs = devm_ioremap_resource(&dev->dev, res); |
| 409 | if (IS_ERR(hsotg->regs)) |
| 410 | return PTR_ERR(hsotg->regs); |
| 411 | |
| 412 | dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n", |
| 413 | (unsigned long)res->start, hsotg->regs); |
| 414 | |
| 415 | retval = dwc2_lowlevel_hw_init(hsotg); |
| 416 | if (retval) |
| 417 | return retval; |
| 418 | |
| 419 | spin_lock_init(&hsotg->lock); |
| 420 | |
| 421 | hsotg->irq = platform_get_irq(dev, 0); |
| 422 | if (hsotg->irq < 0) { |
| 423 | dev_err(&dev->dev, "missing IRQ resource\n"); |
| 424 | return hsotg->irq; |
| 425 | } |
| 426 | |
| 427 | dev_dbg(hsotg->dev, "registering common handler for irq%d\n", |
| 428 | hsotg->irq); |
| 429 | retval = devm_request_irq(hsotg->dev, hsotg->irq, |
| 430 | dwc2_handle_common_intr, IRQF_SHARED, |
| 431 | dev_name(hsotg->dev), hsotg); |
| 432 | if (retval) |
| 433 | return retval; |
| 434 | |
| 435 | retval = dwc2_lowlevel_hw_enable(hsotg); |
| 436 | if (retval) |
| 437 | return retval; |
| 438 | |
| 439 | hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg); |
| 440 | |
| 441 | retval = dwc2_get_dr_mode(hsotg); |
| 442 | if (retval) |
| 443 | goto error; |
| 444 | |
| 445 | /* |
| 446 | * Reset before dwc2_get_hwparams() then it could get power-on real |
| 447 | * reset value form registers. |
| 448 | */ |
| 449 | retval = dwc2_core_reset(hsotg, false); |
| 450 | if (retval) |
| 451 | goto error; |
| 452 | |
| 453 | /* Detect config values from hardware */ |
| 454 | retval = dwc2_get_hwparams(hsotg); |
| 455 | if (retval) |
| 456 | goto error; |
| 457 | |
| 458 | /* |
| 459 | * For OTG cores, set the force mode bits to reflect the value |
| 460 | * of dr_mode. Force mode bits should not be touched at any |
| 461 | * other time after this. |
| 462 | */ |
| 463 | dwc2_force_dr_mode(hsotg); |
| 464 | |
| 465 | retval = dwc2_init_params(hsotg); |
| 466 | if (retval) |
| 467 | goto error; |
| 468 | |
| 469 | if (hsotg->dr_mode != USB_DR_MODE_HOST) { |
| 470 | retval = dwc2_gadget_init(hsotg); |
| 471 | if (retval) |
| 472 | goto error; |
| 473 | hsotg->gadget_enabled = 1; |
| 474 | } |
| 475 | |
| 476 | if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { |
| 477 | retval = dwc2_hcd_init(hsotg); |
| 478 | if (retval) { |
| 479 | if (hsotg->gadget_enabled) |
| 480 | dwc2_hsotg_remove(hsotg); |
| 481 | goto error; |
| 482 | } |
| 483 | hsotg->hcd_enabled = 1; |
| 484 | } |
| 485 | |
| 486 | platform_set_drvdata(dev, hsotg); |
| 487 | hsotg->hibernated = 0; |
| 488 | |
| 489 | dwc2_debugfs_init(hsotg); |
| 490 | |
| 491 | /* Gadget code manages lowlevel hw on its own */ |
| 492 | if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
| 493 | dwc2_lowlevel_hw_disable(hsotg); |
| 494 | |
| 495 | return 0; |
| 496 | |
| 497 | error: |
| 498 | dwc2_lowlevel_hw_disable(hsotg); |
| 499 | return retval; |
| 500 | } |
| 501 | |
| 502 | static int __maybe_unused dwc2_suspend(struct device *dev) |
| 503 | { |
| 504 | struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); |
| 505 | int ret = 0; |
| 506 | |
| 507 | if (dwc2_is_device_mode(dwc2)) |
| 508 | dwc2_hsotg_suspend(dwc2); |
| 509 | |
| 510 | if (dwc2->ll_hw_enabled) |
| 511 | ret = __dwc2_lowlevel_hw_disable(dwc2); |
| 512 | |
| 513 | return ret; |
| 514 | } |
| 515 | |
| 516 | static int __maybe_unused dwc2_resume(struct device *dev) |
| 517 | { |
| 518 | struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); |
| 519 | int ret = 0; |
| 520 | |
| 521 | if (dwc2->ll_hw_enabled) { |
| 522 | ret = __dwc2_lowlevel_hw_enable(dwc2); |
| 523 | if (ret) |
| 524 | return ret; |
| 525 | } |
| 526 | |
| 527 | if (dwc2_is_device_mode(dwc2)) |
| 528 | ret = dwc2_hsotg_resume(dwc2); |
| 529 | |
| 530 | return ret; |
| 531 | } |
| 532 | |
| 533 | static const struct dev_pm_ops dwc2_dev_pm_ops = { |
| 534 | SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume) |
| 535 | }; |
| 536 | |
| 537 | static struct platform_driver dwc2_platform_driver = { |
| 538 | .driver = { |
| 539 | .name = dwc2_driver_name, |
| 540 | .of_match_table = dwc2_of_match_table, |
| 541 | .pm = &dwc2_dev_pm_ops, |
| 542 | }, |
| 543 | .probe = dwc2_driver_probe, |
| 544 | .remove = dwc2_driver_remove, |
| 545 | .shutdown = dwc2_driver_shutdown, |
| 546 | }; |
| 547 | |
| 548 | module_platform_driver(dwc2_platform_driver); |
| 549 | |
| 550 | MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue"); |
| 551 | MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>"); |
| 552 | MODULE_LICENSE("Dual BSD/GPL"); |