| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef _ASM_POWERPC_TIMEX_H |
| 3 | #define _ASM_POWERPC_TIMEX_H |
| 4 | |
| 5 | #ifdef __KERNEL__ |
| 6 | |
| 7 | /* |
| 8 | * PowerPC architecture timex specifications |
| 9 | */ |
| 10 | |
| 11 | #include <asm/cputable.h> |
| 12 | #include <asm/reg.h> |
| 13 | |
| 14 | #define CLOCK_TICK_RATE 1024000 /* Underlying HZ */ |
| 15 | |
| 16 | typedef unsigned long cycles_t; |
| 17 | |
| 18 | static inline cycles_t get_cycles(void) |
| 19 | { |
| 20 | #ifdef __powerpc64__ |
| 21 | return mftb(); |
| 22 | #else |
| 23 | cycles_t ret; |
| 24 | |
| 25 | /* |
| 26 | * For the "cycle" counter we use the timebase lower half. |
| 27 | * Currently only used on SMP. |
| 28 | */ |
| 29 | |
| 30 | ret = 0; |
| 31 | |
| 32 | __asm__ __volatile__( |
| 33 | #ifdef CONFIG_PPC_8xx |
| 34 | "97: mftb %0\n" |
| 35 | #else |
| 36 | "97: mfspr %0, %2\n" |
| 37 | #endif |
| 38 | "99:\n" |
| 39 | ".section __ftr_fixup,\"a\"\n" |
| 40 | ".align 2\n" |
| 41 | "98:\n" |
| 42 | " .long %1\n" |
| 43 | " .long 0\n" |
| 44 | " .long 97b-98b\n" |
| 45 | " .long 99b-98b\n" |
| 46 | " .long 0\n" |
| 47 | " .long 0\n" |
| 48 | ".previous" |
| 49 | : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL)); |
| 50 | return ret; |
| 51 | #endif |
| 52 | } |
| 53 | |
| 54 | #endif /* __KERNEL__ */ |
| 55 | #endif /* _ASM_POWERPC_TIMEX_H */ |