| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Header for the new SH dmaengine driver |
| 4 | * |
| 5 | * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 6 | */ |
| 7 | #ifndef SH_DMA_H |
| 8 | #define SH_DMA_H |
| 9 | |
| 10 | #include <linux/dmaengine.h> |
| 11 | #include <linux/list.h> |
| 12 | #include <linux/shdma-base.h> |
| 13 | #include <linux/types.h> |
| 14 | |
| 15 | struct device; |
| 16 | |
| 17 | /* Used by slave DMA clients to request DMA to/from a specific peripheral */ |
| 18 | struct sh_dmae_slave { |
| 19 | struct shdma_slave shdma_slave; /* Set by the platform */ |
| 20 | }; |
| 21 | |
| 22 | /* |
| 23 | * Supplied by platforms to specify, how a DMA channel has to be configured for |
| 24 | * a certain peripheral |
| 25 | */ |
| 26 | struct sh_dmae_slave_config { |
| 27 | int slave_id; |
| 28 | dma_addr_t addr; |
| 29 | u32 chcr; |
| 30 | char mid_rid; |
| 31 | }; |
| 32 | |
| 33 | /** |
| 34 | * struct sh_dmae_channel - DMAC channel platform data |
| 35 | * @offset: register offset within the main IOMEM resource |
| 36 | * @dmars: channel DMARS register offset |
| 37 | * @chclr_offset: channel CHCLR register offset |
| 38 | * @dmars_bit: channel DMARS field offset within the register |
| 39 | * @chclr_bit: bit position, to be set to reset the channel |
| 40 | */ |
| 41 | struct sh_dmae_channel { |
| 42 | unsigned int offset; |
| 43 | unsigned int dmars; |
| 44 | unsigned int chclr_offset; |
| 45 | unsigned char dmars_bit; |
| 46 | unsigned char chclr_bit; |
| 47 | }; |
| 48 | |
| 49 | /** |
| 50 | * struct sh_dmae_pdata - DMAC platform data |
| 51 | * @slave: array of slaves |
| 52 | * @slave_num: number of slaves in the above array |
| 53 | * @channel: array of DMA channels |
| 54 | * @channel_num: number of channels in the above array |
| 55 | * @ts_low_shift: shift of the low part of the TS field |
| 56 | * @ts_low_mask: low TS field mask |
| 57 | * @ts_high_shift: additional shift of the high part of the TS field |
| 58 | * @ts_high_mask: high TS field mask |
| 59 | * @ts_shift: array of Transfer Size shifts, indexed by TS value |
| 60 | * @ts_shift_num: number of shifts in the above array |
| 61 | * @dmaor_init: DMAOR initialisation value |
| 62 | * @chcr_offset: CHCR address offset |
| 63 | * @chcr_ie_bit: CHCR Interrupt Enable bit |
| 64 | * @dmaor_is_32bit: DMAOR is a 32-bit register |
| 65 | * @needs_tend_set: the TEND register has to be set |
| 66 | * @no_dmars: DMAC has no DMARS registers |
| 67 | * @chclr_present: DMAC has one or several CHCLR registers |
| 68 | * @chclr_bitwise: channel CHCLR registers are bitwise |
| 69 | * @slave_only: DMAC cannot be used for MEMCPY |
| 70 | */ |
| 71 | struct sh_dmae_pdata { |
| 72 | const struct sh_dmae_slave_config *slave; |
| 73 | int slave_num; |
| 74 | const struct sh_dmae_channel *channel; |
| 75 | int channel_num; |
| 76 | unsigned int ts_low_shift; |
| 77 | unsigned int ts_low_mask; |
| 78 | unsigned int ts_high_shift; |
| 79 | unsigned int ts_high_mask; |
| 80 | const unsigned int *ts_shift; |
| 81 | int ts_shift_num; |
| 82 | u16 dmaor_init; |
| 83 | unsigned int chcr_offset; |
| 84 | u32 chcr_ie_bit; |
| 85 | |
| 86 | unsigned int dmaor_is_32bit:1; |
| 87 | unsigned int needs_tend_set:1; |
| 88 | unsigned int no_dmars:1; |
| 89 | unsigned int chclr_present:1; |
| 90 | unsigned int chclr_bitwise:1; |
| 91 | unsigned int slave_only:1; |
| 92 | }; |
| 93 | |
| 94 | /* DMAOR definitions */ |
| 95 | #define DMAOR_AE 0x00000004 /* Address Error Flag */ |
| 96 | #define DMAOR_NMIF 0x00000002 |
| 97 | #define DMAOR_DME 0x00000001 /* DMA Master Enable */ |
| 98 | |
| 99 | /* Definitions for the SuperH DMAC */ |
| 100 | #define DM_INC 0x00004000 /* Destination addresses are incremented */ |
| 101 | #define DM_DEC 0x00008000 /* Destination addresses are decremented */ |
| 102 | #define DM_FIX 0x0000c000 /* Destination address is fixed */ |
| 103 | #define SM_INC 0x00001000 /* Source addresses are incremented */ |
| 104 | #define SM_DEC 0x00002000 /* Source addresses are decremented */ |
| 105 | #define SM_FIX 0x00003000 /* Source address is fixed */ |
| 106 | #define RS_AUTO 0x00000400 /* Auto Request */ |
| 107 | #define RS_ERS 0x00000800 /* DMA extended resource selector */ |
| 108 | #define CHCR_DE 0x00000001 /* DMA Enable */ |
| 109 | #define CHCR_TE 0x00000002 /* Transfer End Flag */ |
| 110 | #define CHCR_IE 0x00000004 /* Interrupt Enable */ |
| 111 | |
| 112 | #endif |