David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Hardware monitoring driver for PMBus devices |
| 4 | * |
| 5 | * Copyright (c) 2010, 2011 Ericsson AB. |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _PMBUS_H_ |
| 9 | #define _PMBUS_H_ |
| 10 | |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 11 | #include <linux/bits.h> |
| 12 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 13 | /* flags */ |
| 14 | |
| 15 | /* |
| 16 | * PMBUS_SKIP_STATUS_CHECK |
| 17 | * |
| 18 | * During register detection, skip checking the status register for |
| 19 | * communication or command errors. |
| 20 | * |
| 21 | * Some PMBus chips respond with valid data when trying to read an unsupported |
| 22 | * register. For such chips, checking the status register is mandatory when |
| 23 | * trying to determine if a chip register exists or not. |
| 24 | * Other PMBus chips don't support the STATUS_CML register, or report |
| 25 | * communication errors for no explicable reason. For such chips, checking |
| 26 | * the status register must be disabled. |
| 27 | */ |
Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame] | 28 | #define PMBUS_SKIP_STATUS_CHECK BIT(0) |
| 29 | |
| 30 | /* |
| 31 | * PMBUS_WRITE_PROTECTED |
| 32 | * Set if the chip is write protected and write protection is not determined |
| 33 | * by the standard WRITE_PROTECT command. |
| 34 | */ |
| 35 | #define PMBUS_WRITE_PROTECTED BIT(1) |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 36 | |
| 37 | struct pmbus_platform_data { |
| 38 | u32 flags; /* Device specific flags */ |
| 39 | |
| 40 | /* regulator support */ |
| 41 | int num_regulators; |
| 42 | struct regulator_init_data *reg_init_data; |
| 43 | }; |
| 44 | |
| 45 | #endif /* _PMBUS_H_ */ |