blob: 24ff23e27c8ab117f23d7d00c93d16535ef0a663 [file] [log] [blame]
Andrew Scullb4b6d4a2019-01-02 15:54:55 +00001/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_SRQ_H
34#define MLX5_SRQ_H
35
36#include <linux/mlx5/driver.h>
37
38enum {
39 MLX5_SRQ_FLAG_ERR = (1 << 0),
40 MLX5_SRQ_FLAG_WQ_SIG = (1 << 1),
41 MLX5_SRQ_FLAG_RNDV = (1 << 2),
42};
43
44struct mlx5_srq_attr {
45 u32 type;
46 u32 flags;
47 u32 log_size;
48 u32 wqe_shift;
49 u32 log_page_size;
50 u32 wqe_cnt;
51 u32 srqn;
52 u32 xrcd;
53 u32 page_offset;
54 u32 cqn;
55 u32 pd;
56 u32 lwm;
57 u32 user_index;
58 u64 db_record;
59 __be64 *pas;
60 u32 tm_log_list_size;
61 u32 tm_next_tag;
62 u32 tm_hw_phase_cnt;
63 u32 tm_sw_phase_cnt;
64};
65
66struct mlx5_core_dev;
67
68void mlx5_init_srq_table(struct mlx5_core_dev *dev);
69void mlx5_cleanup_srq_table(struct mlx5_core_dev *dev);
70
71#endif /* MLX5_SRQ_H */