| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Simple pci display device. |
| 4 | * |
| 5 | * Framebuffer memory is pci bar 0. |
| 6 | * Configuration (read-only) is in pci config space. |
| 7 | * Format field uses drm fourcc codes. |
| 8 | * ATM only DRM_FORMAT_XRGB8888 is supported. |
| 9 | */ |
| 10 | |
| 11 | /* pci ids */ |
| Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 12 | #define MDPY_PCI_VENDOR_ID PCI_VENDOR_ID_REDHAT |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 13 | #define MDPY_PCI_DEVICE_ID 0x000f |
| 14 | #define MDPY_PCI_SUBVENDOR_ID PCI_SUBVENDOR_ID_REDHAT_QUMRANET |
| 15 | #define MDPY_PCI_SUBDEVICE_ID PCI_SUBDEVICE_ID_QEMU |
| 16 | |
| 17 | /* pci cfg space offsets for fb config (dword) */ |
| 18 | #define MDPY_VENDORCAP_OFFSET 0x40 |
| 19 | #define MDPY_VENDORCAP_SIZE 0x10 |
| 20 | #define MDPY_FORMAT_OFFSET (MDPY_VENDORCAP_OFFSET + 0x04) |
| 21 | #define MDPY_WIDTH_OFFSET (MDPY_VENDORCAP_OFFSET + 0x08) |
| 22 | #define MDPY_HEIGHT_OFFSET (MDPY_VENDORCAP_OFFSET + 0x0c) |