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Andrew Scullb4b6d4a2019-01-02 15:54:55 +00001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) STMicroelectronics 2016
4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
5 */
6
7#ifndef _LINUX_STM32_GPTIMER_H_
8#define _LINUX_STM32_GPTIMER_H_
9
10#include <linux/clk.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/regmap.h>
14
15#define TIM_CR1 0x00 /* Control Register 1 */
16#define TIM_CR2 0x04 /* Control Register 2 */
17#define TIM_SMCR 0x08 /* Slave mode control reg */
18#define TIM_DIER 0x0C /* DMA/interrupt register */
19#define TIM_SR 0x10 /* Status register */
20#define TIM_EGR 0x14 /* Event Generation Reg */
21#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
22#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
23#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
24#define TIM_CNT 0x24 /* Counter */
25#define TIM_PSC 0x28 /* Prescaler */
26#define TIM_ARR 0x2c /* Auto-Reload Register */
27#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
28#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
29#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
30#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
31#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
32#define TIM_DCR 0x48 /* DMA control register */
33#define TIM_DMAR 0x4C /* DMA register for transfer */
34
35#define TIM_CR1_CEN BIT(0) /* Counter Enable */
36#define TIM_CR1_DIR BIT(4) /* Counter Direction */
37#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
38#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
39#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */
40#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
41#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
42#define TIM_DIER_UIE BIT(0) /* Update interrupt */
43#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
44#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */
45#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */
46#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */
47#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */
48#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */
49#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */
50#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
51#define TIM_EGR_UG BIT(0) /* Update Generation */
52#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
53#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
54#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
55#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */
56#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
57#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */
58#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */
59#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */
60#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */
61#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */
62#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
63#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
64#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
65#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
66#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
67#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
68#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
69#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
70#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
71#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
72#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
Olivier Deprez157378f2022-04-04 15:47:50 +020073#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
74#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000075#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
76#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
Olivier Deprez157378f2022-04-04 15:47:50 +020077#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4))
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000078#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */
79#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */
80
81#define MAX_TIM_PSC 0xFFFF
82#define MAX_TIM_ICPSC 0x3
83#define TIM_CR2_MMS_SHIFT 4
84#define TIM_CR2_MMS2_SHIFT 20
85#define TIM_SMCR_TS_SHIFT 4
86#define TIM_BDTR_BKF_MASK 0xF
Olivier Deprez157378f2022-04-04 15:47:50 +020087#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4)
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000088
89enum stm32_timers_dmas {
90 STM32_TIMERS_DMA_CH1,
91 STM32_TIMERS_DMA_CH2,
92 STM32_TIMERS_DMA_CH3,
93 STM32_TIMERS_DMA_CH4,
94 STM32_TIMERS_DMA_UP,
95 STM32_TIMERS_DMA_TRIG,
96 STM32_TIMERS_DMA_COM,
97 STM32_TIMERS_MAX_DMAS,
98};
99
100/**
101 * struct stm32_timers_dma - STM32 timer DMA handling.
102 * @completion: end of DMA transfer completion
103 * @phys_base: control registers physical base address
104 * @lock: protect DMA access
105 * @chan: DMA channel in use
106 * @chans: DMA channels available for this timer instance
107 */
108struct stm32_timers_dma {
109 struct completion completion;
110 phys_addr_t phys_base;
111 struct mutex lock;
112 struct dma_chan *chan;
113 struct dma_chan *chans[STM32_TIMERS_MAX_DMAS];
114};
115
116struct stm32_timers {
117 struct clk *clk;
118 struct regmap *regmap;
119 u32 max_arr;
120 struct stm32_timers_dma dma; /* Only to be used by the parent */
121};
122
123#if IS_REACHABLE(CONFIG_MFD_STM32_TIMERS)
124int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
125 enum stm32_timers_dmas id, u32 reg,
126 unsigned int num_reg, unsigned int bursts,
127 unsigned long tmo_ms);
128#else
129static inline int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
130 enum stm32_timers_dmas id,
131 u32 reg,
132 unsigned int num_reg,
133 unsigned int bursts,
134 unsigned long tmo_ms)
135{
136 return -ENODEV;
137}
138#endif
139#endif