| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * TI Syscon Reset definitions |
| 4 | * |
| Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 5 | * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ |
| 9 | #define __DT_BINDINGS_RESET_TI_SYSCON_H__ |
| 10 | |
| 11 | /* |
| 12 | * The reset does not support the feature and corresponding |
| 13 | * values are not valid |
| 14 | */ |
| 15 | #define ASSERT_NONE (1 << 0) |
| 16 | #define DEASSERT_NONE (1 << 1) |
| 17 | #define STATUS_NONE (1 << 2) |
| 18 | |
| 19 | /* When set this function is activated by setting(vs clearing) this bit */ |
| 20 | #define ASSERT_SET (1 << 3) |
| 21 | #define DEASSERT_SET (1 << 4) |
| 22 | #define STATUS_SET (1 << 5) |
| 23 | |
| 24 | /* The following are the inverse of the above and are added for consistency */ |
| 25 | #define ASSERT_CLEAR (0 << 3) |
| 26 | #define DEASSERT_CLEAR (0 << 4) |
| 27 | #define STATUS_CLEAR (0 << 5) |
| 28 | |
| 29 | #endif |