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review.trustedfirmware.org / hafnium / third_party / linux.git / 157378f43faad830e4aa3815bde5fa9f9a9f5be6 / . / drivers / soc / renesas / rcar-sysc.h
blob: 8d861c1cfdf78b6f03b43922ec644a2a45d2577c [file] [log] [blame]
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]3 * Renesas R-Car System Controller
4 *
5 * Copyright (C) 2016 Glider bvba
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]6 */
7#ifndef __SOC_RENESAS_RCAR_SYSC_H__
8#define __SOC_RENESAS_RCAR_SYSC_H__
9
10#include <linux/types.h>
11
12
13/*
14 * Power Domain flags
15 */
16#define PD_CPU BIT(0) /* Area contains main CPU core */
17#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
18#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */
19
20#define PD_CPU_CR PD_CPU /* CPU area has CR (R-Car H1) */
21#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
22#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
23
24
25/*
26 * Description of a Power Area
27 */
28
29struct rcar_sysc_area {
30 const char *name;
31 u16 chan_offs; /* Offset of PWRSR register for this area */
32 u8 chan_bit; /* Bit in PWR* (except for PWRUP in PWRSR) */
33 u8 isr_bit; /* Bit in SYSCI*R */
34 int parent; /* -1 if none */
35 unsigned int flags; /* See PD_* */
36};
37
38
39/*
40 * SoC-specific Power Area Description
41 */
42
43struct rcar_sysc_info {
44 int (*init)(void); /* Optional */
45 const struct rcar_sysc_area *areas;
46 unsigned int num_areas;
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]47 /* Optional External Request Mask Register */
48 u32 extmask_offs; /* SYSCEXTMASK register offset */
49 u32 extmask_val; /* SYSCEXTMASK register mask value */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]50};
51
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]52extern const struct rcar_sysc_info r8a7742_sysc_info;
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]53extern const struct rcar_sysc_info r8a7743_sysc_info;
54extern const struct rcar_sysc_info r8a7745_sysc_info;
55extern const struct rcar_sysc_info r8a77470_sysc_info;
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]56extern const struct rcar_sysc_info r8a774a1_sysc_info;
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]57extern const struct rcar_sysc_info r8a774b1_sysc_info;
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]58extern const struct rcar_sysc_info r8a774c0_sysc_info;
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]59extern const struct rcar_sysc_info r8a774e1_sysc_info;
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]60extern const struct rcar_sysc_info r8a7779_sysc_info;
61extern const struct rcar_sysc_info r8a7790_sysc_info;
62extern const struct rcar_sysc_info r8a7791_sysc_info;
63extern const struct rcar_sysc_info r8a7792_sysc_info;
64extern const struct rcar_sysc_info r8a7794_sysc_info;
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]65extern struct rcar_sysc_info r8a7795_sysc_info;
66extern const struct rcar_sysc_info r8a77960_sysc_info;
67extern const struct rcar_sysc_info r8a77961_sysc_info;
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]68extern const struct rcar_sysc_info r8a77965_sysc_info;
69extern const struct rcar_sysc_info r8a77970_sysc_info;
70extern const struct rcar_sysc_info r8a77980_sysc_info;
71extern const struct rcar_sysc_info r8a77990_sysc_info;
72extern const struct rcar_sysc_info r8a77995_sysc_info;
73
74
75 /*
76 * Helpers for fixing up power area tables depending on SoC revision
77 */
78
79extern void rcar_sysc_nullify(struct rcar_sysc_area *areas,
80 unsigned int num_areas, u8 id);
81
82#endif /* __SOC_RENESAS_RCAR_SYSC_H__ */