| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2013 NVIDIA Corporation |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef TEGRA_GR2D_H |
| 7 | #define TEGRA_GR2D_H |
| 8 | |
| 9 | #define GR2D_UA_BASE_ADDR 0x1a |
| 10 | #define GR2D_VA_BASE_ADDR 0x1b |
| 11 | #define GR2D_PAT_BASE_ADDR 0x26 |
| 12 | #define GR2D_DSTA_BASE_ADDR 0x2b |
| 13 | #define GR2D_DSTB_BASE_ADDR 0x2c |
| 14 | #define GR2D_DSTC_BASE_ADDR 0x2d |
| 15 | #define GR2D_SRCA_BASE_ADDR 0x31 |
| 16 | #define GR2D_SRCB_BASE_ADDR 0x32 |
| Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 17 | #define GR2D_PATBASE_ADDR 0x47 |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 18 | #define GR2D_SRC_BASE_ADDR_SB 0x48 |
| 19 | #define GR2D_DSTA_BASE_ADDR_SB 0x49 |
| 20 | #define GR2D_DSTB_BASE_ADDR_SB 0x4a |
| 21 | #define GR2D_UA_BASE_ADDR_SB 0x4b |
| 22 | #define GR2D_VA_BASE_ADDR_SB 0x4c |
| 23 | |
| 24 | #define GR2D_NUM_REGS 0x4d |
| 25 | |
| 26 | #endif |