| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Chen Liqin <liqin.chen@sunplusct.com> |
| 4 | * Copyright (C) 2012 Regents of the University of California |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_RISCV_CACHE_H |
| 8 | #define _ASM_RISCV_CACHE_H |
| 9 | |
| 10 | #define L1_CACHE_SHIFT 6 |
| 11 | |
| 12 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
| 13 | |
| Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 14 | /* |
| 15 | * RISC-V requires the stack pointer to be 16-byte aligned, so ensure that |
| 16 | * the flat loader aligns it accordingly. |
| 17 | */ |
| 18 | #ifndef CONFIG_MMU |
| 19 | #define ARCH_SLAB_MINALIGN 16 |
| 20 | #endif |
| 21 | |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 22 | #endif /* _ASM_RISCV_CACHE_H */ |