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Andrew Scullb4b6d4a2019-01-02 15:54:55 +00001// SPDX-License-Identifier: GPL-2.0
2/**
3 * ulpi.c - DesignWare USB3 Controller's ULPI PHY interface
4 *
5 * Copyright (C) 2015 Intel Corporation
6 *
7 * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
8 */
9
Olivier Deprez0e641232021-09-23 10:07:05 +020010#include <linux/delay.h>
11#include <linux/time64.h>
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000012#include <linux/ulpi/regs.h>
13
14#include "core.h"
15#include "io.h"
16
17#define DWC3_ULPI_ADDR(a) \
18 ((a >= ULPI_EXT_VENDOR_SPECIFIC) ? \
19 DWC3_GUSB2PHYACC_ADDR(ULPI_ACCESS_EXTENDED) | \
20 DWC3_GUSB2PHYACC_EXTEND_ADDR(a) : DWC3_GUSB2PHYACC_ADDR(a))
21
Olivier Deprez0e641232021-09-23 10:07:05 +020022#define DWC3_ULPI_BASE_DELAY DIV_ROUND_UP(NSEC_PER_SEC, 60000000L)
23
24static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read)
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000025{
Olivier Deprez0e641232021-09-23 10:07:05 +020026 unsigned long ns = 5L * DWC3_ULPI_BASE_DELAY;
27 unsigned int count = 1000;
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000028 u32 reg;
29
Olivier Deprez0e641232021-09-23 10:07:05 +020030 if (addr >= ULPI_EXT_VENDOR_SPECIFIC)
31 ns += DWC3_ULPI_BASE_DELAY;
32
33 if (read)
34 ns += DWC3_ULPI_BASE_DELAY;
35
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000036 while (count--) {
Olivier Deprez0e641232021-09-23 10:07:05 +020037 ndelay(ns);
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000038 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
Olivier Deprez0e641232021-09-23 10:07:05 +020039 if (reg & DWC3_GUSB2PHYACC_DONE)
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000040 return 0;
41 cpu_relax();
42 }
43
44 return -ETIMEDOUT;
45}
46
47static int dwc3_ulpi_read(struct device *dev, u8 addr)
48{
49 struct dwc3 *dwc = dev_get_drvdata(dev);
50 u32 reg;
51 int ret;
52
53 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
54 if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
55 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
56 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
57 }
58
59 reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
60 dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
61
Olivier Deprez0e641232021-09-23 10:07:05 +020062 ret = dwc3_ulpi_busyloop(dwc, addr, true);
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000063 if (ret)
64 return ret;
65
66 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
67
68 return DWC3_GUSB2PHYACC_DATA(reg);
69}
70
71static int dwc3_ulpi_write(struct device *dev, u8 addr, u8 val)
72{
73 struct dwc3 *dwc = dev_get_drvdata(dev);
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
77 if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
78 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
79 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
80 }
81
82 reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
83 reg |= DWC3_GUSB2PHYACC_WRITE | val;
84 dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
85
Olivier Deprez0e641232021-09-23 10:07:05 +020086 return dwc3_ulpi_busyloop(dwc, addr, false);
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000087}
88
89static const struct ulpi_ops dwc3_ulpi_ops = {
90 .read = dwc3_ulpi_read,
91 .write = dwc3_ulpi_write,
92};
93
94int dwc3_ulpi_init(struct dwc3 *dwc)
95{
96 /* Register the interface */
97 dwc->ulpi = ulpi_register_interface(dwc->dev, &dwc3_ulpi_ops);
98 if (IS_ERR(dwc->ulpi)) {
99 dev_err(dwc->dev, "failed to register ULPI interface");
100 return PTR_ERR(dwc->ulpi);
101 }
102
103 return 0;
104}
105
106void dwc3_ulpi_exit(struct dwc3 *dwc)
107{
108 if (dwc->ulpi) {
109 ulpi_unregister_interface(dwc->ulpi);
110 dwc->ulpi = NULL;
111 }
112}