David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * intel_pt_decoder.h: Intel Processor Trace support |
| 4 | * Copyright (c) 2013-2014, Intel Corporation. |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef INCLUDE__INTEL_PT_DECODER_H__ |
| 8 | #define INCLUDE__INTEL_PT_DECODER_H__ |
| 9 | |
| 10 | #include <stdint.h> |
| 11 | #include <stddef.h> |
| 12 | #include <stdbool.h> |
| 13 | |
| 14 | #include "intel-pt-insn-decoder.h" |
| 15 | |
| 16 | #define INTEL_PT_IN_TX (1 << 0) |
| 17 | #define INTEL_PT_ABORT_TX (1 << 1) |
| 18 | #define INTEL_PT_ASYNC (1 << 2) |
| 19 | #define INTEL_PT_FUP_IP (1 << 3) |
| 20 | |
| 21 | enum intel_pt_sample_type { |
| 22 | INTEL_PT_BRANCH = 1 << 0, |
| 23 | INTEL_PT_INSTRUCTION = 1 << 1, |
| 24 | INTEL_PT_TRANSACTION = 1 << 2, |
| 25 | INTEL_PT_PTW = 1 << 3, |
| 26 | INTEL_PT_MWAIT_OP = 1 << 4, |
| 27 | INTEL_PT_PWR_ENTRY = 1 << 5, |
| 28 | INTEL_PT_EX_STOP = 1 << 6, |
| 29 | INTEL_PT_PWR_EXIT = 1 << 7, |
| 30 | INTEL_PT_CBR_CHG = 1 << 8, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 31 | INTEL_PT_TRACE_BEGIN = 1 << 9, |
| 32 | INTEL_PT_TRACE_END = 1 << 10, |
| 33 | INTEL_PT_BLK_ITEMS = 1 << 11, |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 34 | }; |
| 35 | |
| 36 | enum intel_pt_period_type { |
| 37 | INTEL_PT_PERIOD_NONE, |
| 38 | INTEL_PT_PERIOD_INSTRUCTIONS, |
| 39 | INTEL_PT_PERIOD_TICKS, |
| 40 | INTEL_PT_PERIOD_MTC, |
| 41 | }; |
| 42 | |
| 43 | enum { |
| 44 | INTEL_PT_ERR_NOMEM = 1, |
| 45 | INTEL_PT_ERR_INTERN, |
| 46 | INTEL_PT_ERR_BADPKT, |
| 47 | INTEL_PT_ERR_NODATA, |
| 48 | INTEL_PT_ERR_NOINSN, |
| 49 | INTEL_PT_ERR_MISMAT, |
| 50 | INTEL_PT_ERR_OVR, |
| 51 | INTEL_PT_ERR_LOST, |
| 52 | INTEL_PT_ERR_UNK, |
| 53 | INTEL_PT_ERR_NELOOP, |
| 54 | INTEL_PT_ERR_MAX, |
| 55 | }; |
| 56 | |
| 57 | enum intel_pt_param_flags { |
| 58 | /* |
| 59 | * FUP packet can contain next linear instruction pointer instead of |
| 60 | * current linear instruction pointer. |
| 61 | */ |
| 62 | INTEL_PT_FUP_WITH_NLIP = 1 << 0, |
| 63 | }; |
| 64 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 65 | enum intel_pt_blk_type { |
| 66 | INTEL_PT_GP_REGS = 1, |
| 67 | INTEL_PT_PEBS_BASIC = 4, |
| 68 | INTEL_PT_PEBS_MEM = 5, |
| 69 | INTEL_PT_LBR_0 = 8, |
| 70 | INTEL_PT_LBR_1 = 9, |
| 71 | INTEL_PT_LBR_2 = 10, |
| 72 | INTEL_PT_XMM = 16, |
| 73 | INTEL_PT_BLK_TYPE_MAX |
| 74 | }; |
| 75 | |
| 76 | /* |
| 77 | * The block type numbers are not sequential but here they are given sequential |
| 78 | * positions to avoid wasting space for array placement. |
| 79 | */ |
| 80 | enum intel_pt_blk_type_pos { |
| 81 | INTEL_PT_GP_REGS_POS, |
| 82 | INTEL_PT_PEBS_BASIC_POS, |
| 83 | INTEL_PT_PEBS_MEM_POS, |
| 84 | INTEL_PT_LBR_0_POS, |
| 85 | INTEL_PT_LBR_1_POS, |
| 86 | INTEL_PT_LBR_2_POS, |
| 87 | INTEL_PT_XMM_POS, |
| 88 | INTEL_PT_BLK_TYPE_CNT |
| 89 | }; |
| 90 | |
| 91 | /* Get the array position for a block type */ |
| 92 | static inline int intel_pt_blk_type_pos(enum intel_pt_blk_type blk_type) |
| 93 | { |
| 94 | #define BLK_TYPE(bt) [INTEL_PT_##bt] = INTEL_PT_##bt##_POS + 1 |
| 95 | const int map[INTEL_PT_BLK_TYPE_MAX] = { |
| 96 | BLK_TYPE(GP_REGS), |
| 97 | BLK_TYPE(PEBS_BASIC), |
| 98 | BLK_TYPE(PEBS_MEM), |
| 99 | BLK_TYPE(LBR_0), |
| 100 | BLK_TYPE(LBR_1), |
| 101 | BLK_TYPE(LBR_2), |
| 102 | BLK_TYPE(XMM), |
| 103 | }; |
| 104 | #undef BLK_TYPE |
| 105 | |
| 106 | return blk_type < INTEL_PT_BLK_TYPE_MAX ? map[blk_type] - 1 : -1; |
| 107 | } |
| 108 | |
| 109 | #define INTEL_PT_BLK_ITEM_ID_CNT 32 |
| 110 | |
| 111 | /* |
| 112 | * Use unions so that the block items can be accessed by name or by array index. |
| 113 | * There is an array of 32-bit masks for each block type, which indicate which |
| 114 | * values are present. Then arrays of 32 64-bit values for each block type. |
| 115 | */ |
| 116 | struct intel_pt_blk_items { |
| 117 | union { |
| 118 | uint32_t mask[INTEL_PT_BLK_TYPE_CNT]; |
| 119 | struct { |
| 120 | uint32_t has_rflags:1; |
| 121 | uint32_t has_rip:1; |
| 122 | uint32_t has_rax:1; |
| 123 | uint32_t has_rcx:1; |
| 124 | uint32_t has_rdx:1; |
| 125 | uint32_t has_rbx:1; |
| 126 | uint32_t has_rsp:1; |
| 127 | uint32_t has_rbp:1; |
| 128 | uint32_t has_rsi:1; |
| 129 | uint32_t has_rdi:1; |
| 130 | uint32_t has_r8:1; |
| 131 | uint32_t has_r9:1; |
| 132 | uint32_t has_r10:1; |
| 133 | uint32_t has_r11:1; |
| 134 | uint32_t has_r12:1; |
| 135 | uint32_t has_r13:1; |
| 136 | uint32_t has_r14:1; |
| 137 | uint32_t has_r15:1; |
| 138 | uint32_t has_unused_0:14; |
| 139 | uint32_t has_ip:1; |
| 140 | uint32_t has_applicable_counters:1; |
| 141 | uint32_t has_timestamp:1; |
| 142 | uint32_t has_unused_1:29; |
| 143 | uint32_t has_mem_access_address:1; |
| 144 | uint32_t has_mem_aux_info:1; |
| 145 | uint32_t has_mem_access_latency:1; |
| 146 | uint32_t has_tsx_aux_info:1; |
| 147 | uint32_t has_unused_2:28; |
| 148 | uint32_t has_lbr_0; |
| 149 | uint32_t has_lbr_1; |
| 150 | uint32_t has_lbr_2; |
| 151 | uint32_t has_xmm; |
| 152 | }; |
| 153 | }; |
| 154 | union { |
| 155 | uint64_t val[INTEL_PT_BLK_TYPE_CNT][INTEL_PT_BLK_ITEM_ID_CNT]; |
| 156 | struct { |
| 157 | struct { |
| 158 | uint64_t rflags; |
| 159 | uint64_t rip; |
| 160 | uint64_t rax; |
| 161 | uint64_t rcx; |
| 162 | uint64_t rdx; |
| 163 | uint64_t rbx; |
| 164 | uint64_t rsp; |
| 165 | uint64_t rbp; |
| 166 | uint64_t rsi; |
| 167 | uint64_t rdi; |
| 168 | uint64_t r8; |
| 169 | uint64_t r9; |
| 170 | uint64_t r10; |
| 171 | uint64_t r11; |
| 172 | uint64_t r12; |
| 173 | uint64_t r13; |
| 174 | uint64_t r14; |
| 175 | uint64_t r15; |
| 176 | uint64_t unused_0[INTEL_PT_BLK_ITEM_ID_CNT - 18]; |
| 177 | }; |
| 178 | struct { |
| 179 | uint64_t ip; |
| 180 | uint64_t applicable_counters; |
| 181 | uint64_t timestamp; |
| 182 | uint64_t unused_1[INTEL_PT_BLK_ITEM_ID_CNT - 3]; |
| 183 | }; |
| 184 | struct { |
| 185 | uint64_t mem_access_address; |
| 186 | uint64_t mem_aux_info; |
| 187 | uint64_t mem_access_latency; |
| 188 | uint64_t tsx_aux_info; |
| 189 | uint64_t unused_2[INTEL_PT_BLK_ITEM_ID_CNT - 4]; |
| 190 | }; |
| 191 | uint64_t lbr_0[INTEL_PT_BLK_ITEM_ID_CNT]; |
| 192 | uint64_t lbr_1[INTEL_PT_BLK_ITEM_ID_CNT]; |
| 193 | uint64_t lbr_2[INTEL_PT_BLK_ITEM_ID_CNT]; |
| 194 | uint64_t xmm[INTEL_PT_BLK_ITEM_ID_CNT]; |
| 195 | }; |
| 196 | }; |
| 197 | bool is_32_bit; |
| 198 | }; |
| 199 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 200 | struct intel_pt_state { |
| 201 | enum intel_pt_sample_type type; |
| 202 | int err; |
| 203 | uint64_t from_ip; |
| 204 | uint64_t to_ip; |
| 205 | uint64_t cr3; |
| 206 | uint64_t tot_insn_cnt; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 207 | uint64_t tot_cyc_cnt; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 208 | uint64_t timestamp; |
| 209 | uint64_t est_timestamp; |
| 210 | uint64_t trace_nr; |
| 211 | uint64_t ptw_payload; |
| 212 | uint64_t mwait_payload; |
| 213 | uint64_t pwre_payload; |
| 214 | uint64_t pwrx_payload; |
| 215 | uint64_t cbr_payload; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 216 | uint32_t cbr; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 217 | uint32_t flags; |
| 218 | enum intel_pt_insn_op insn_op; |
| 219 | int insn_len; |
| 220 | char insn[INTEL_PT_INSN_BUF_SZ]; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 221 | struct intel_pt_blk_items items; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 222 | }; |
| 223 | |
| 224 | struct intel_pt_insn; |
| 225 | |
| 226 | struct intel_pt_buffer { |
| 227 | const unsigned char *buf; |
| 228 | size_t len; |
| 229 | bool consecutive; |
| 230 | uint64_t ref_timestamp; |
| 231 | uint64_t trace_nr; |
| 232 | }; |
| 233 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 234 | typedef int (*intel_pt_lookahead_cb_t)(struct intel_pt_buffer *, void *); |
| 235 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 236 | struct intel_pt_params { |
| 237 | int (*get_trace)(struct intel_pt_buffer *buffer, void *data); |
| 238 | int (*walk_insn)(struct intel_pt_insn *intel_pt_insn, |
| 239 | uint64_t *insn_cnt_ptr, uint64_t *ip, uint64_t to_ip, |
| 240 | uint64_t max_insn_cnt, void *data); |
| 241 | bool (*pgd_ip)(uint64_t ip, void *data); |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 242 | int (*lookahead)(void *data, intel_pt_lookahead_cb_t cb, void *cb_data); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 243 | void *data; |
| 244 | bool return_compression; |
| 245 | bool branch_enable; |
| 246 | uint64_t period; |
| 247 | enum intel_pt_period_type period_type; |
| 248 | unsigned max_non_turbo_ratio; |
| 249 | unsigned int mtc_period; |
| 250 | uint32_t tsc_ctc_ratio_n; |
| 251 | uint32_t tsc_ctc_ratio_d; |
| 252 | enum intel_pt_param_flags flags; |
| 253 | }; |
| 254 | |
| 255 | struct intel_pt_decoder; |
| 256 | |
| 257 | struct intel_pt_decoder *intel_pt_decoder_new(struct intel_pt_params *params); |
| 258 | void intel_pt_decoder_free(struct intel_pt_decoder *decoder); |
| 259 | |
| 260 | const struct intel_pt_state *intel_pt_decode(struct intel_pt_decoder *decoder); |
| 261 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 262 | int intel_pt_fast_forward(struct intel_pt_decoder *decoder, uint64_t timestamp); |
| 263 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 264 | unsigned char *intel_pt_find_overlap(unsigned char *buf_a, size_t len_a, |
| 265 | unsigned char *buf_b, size_t len_b, |
| 266 | bool have_tsc, bool *consecutive); |
| 267 | |
| 268 | int intel_pt__strerror(int code, char *buf, size_t buflen); |
| 269 | |
| 270 | #endif |