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review.trustedfirmware.org / hafnium / third_party / linux.git / 0f672f6c0b52b7b0700b0915c72b540721af4465 / . / include / linux / qcom_scm.h
blob: 2d5eff506e13b08924dd127ed7e8a13499780bae [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]3 * Copyright (C) 2015 Linaro Ltd.
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]4 */
5#ifndef __QCOM_SCM_H
6#define __QCOM_SCM_H
7
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]8#include <linux/err.h>
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]9#include <linux/types.h>
10#include <linux/cpumask.h>
11
12#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
13#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
14#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
15#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
16
17struct qcom_scm_hdcp_req {
18 u32 addr;
19 u32 val;
20};
21
22struct qcom_scm_vmperm {
23 int vmid;
24 int perm;
25};
26
27#define QCOM_SCM_VMID_HLOS 0x3
28#define QCOM_SCM_VMID_MSS_MSA 0xF
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]29#define QCOM_SCM_VMID_WLAN 0x18
30#define QCOM_SCM_VMID_WLAN_CE 0x19
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]31#define QCOM_SCM_PERM_READ 0x4
32#define QCOM_SCM_PERM_WRITE 0x2
33#define QCOM_SCM_PERM_EXEC 0x1
34#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
35#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
36
37#if IS_ENABLED(CONFIG_QCOM_SCM)
38extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
39extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
40extern bool qcom_scm_is_available(void);
41extern bool qcom_scm_hdcp_available(void);
42extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
43 u32 *resp);
44extern bool qcom_scm_pas_supported(u32 peripheral);
45extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
46 size_t size);
47extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
48 phys_addr_t size);
49extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
50extern int qcom_scm_pas_shutdown(u32 peripheral);
51extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]52 unsigned int *src,
53 const struct qcom_scm_vmperm *newvm,
54 unsigned int dest_cnt);
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]55extern void qcom_scm_cpu_power_down(u32 flags);
56extern u32 qcom_scm_get_version(void);
57extern int qcom_scm_set_remote_state(u32 state, u32 id);
58extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
59extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
60extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
61extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
62extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
63#else
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]64
65#include <linux/errno.h>
66
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]67static inline
68int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
69{
70 return -ENODEV;
71}
72static inline
73int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
74{
75 return -ENODEV;
76}
77static inline bool qcom_scm_is_available(void) { return false; }
78static inline bool qcom_scm_hdcp_available(void) { return false; }
79static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
80 u32 *resp) { return -ENODEV; }
81static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
82static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
83 size_t size) { return -ENODEV; }
84static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
85 phys_addr_t size) { return -ENODEV; }
86static inline int
87qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
88static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
89static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
90 unsigned int *src,
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]91 const struct qcom_scm_vmperm *newvm,
92 unsigned int dest_cnt) { return -ENODEV; }
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]93static inline void qcom_scm_cpu_power_down(u32 flags) {}
94static inline u32 qcom_scm_get_version(void) { return 0; }
95static inline u32
96qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
97static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
98static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
99static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
100static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
101static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
102#endif
103#endif