| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H |
| 7 | #define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H |
| 8 | |
| 9 | #define TEGRA186_POWER_DOMAIN_AUD 0 |
| 10 | #define TEGRA186_POWER_DOMAIN_DFD 1 |
| 11 | #define TEGRA186_POWER_DOMAIN_DISP 2 |
| 12 | #define TEGRA186_POWER_DOMAIN_DISPB 3 |
| 13 | #define TEGRA186_POWER_DOMAIN_DISPC 4 |
| 14 | #define TEGRA186_POWER_DOMAIN_ISPA 5 |
| 15 | #define TEGRA186_POWER_DOMAIN_NVDEC 6 |
| 16 | #define TEGRA186_POWER_DOMAIN_NVJPG 7 |
| 17 | #define TEGRA186_POWER_DOMAIN_MPE 8 |
| 18 | #define TEGRA186_POWER_DOMAIN_PCX 9 |
| 19 | #define TEGRA186_POWER_DOMAIN_SAX 10 |
| 20 | #define TEGRA186_POWER_DOMAIN_VE 11 |
| 21 | #define TEGRA186_POWER_DOMAIN_VIC 12 |
| 22 | #define TEGRA186_POWER_DOMAIN_XUSBA 13 |
| 23 | #define TEGRA186_POWER_DOMAIN_XUSBB 14 |
| 24 | #define TEGRA186_POWER_DOMAIN_XUSBC 15 |
| 25 | #define TEGRA186_POWER_DOMAIN_GPU 43 |
| 26 | #define TEGRA186_POWER_DOMAIN_MAX 44 |
| 27 | |
| 28 | #endif |