David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 ARM Ltd. |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 4 | */ |
| 5 | #ifndef __CLKSOURCE_ARM_ARCH_TIMER_H |
| 6 | #define __CLKSOURCE_ARM_ARCH_TIMER_H |
| 7 | |
| 8 | #include <linux/bitops.h> |
| 9 | #include <linux/timecounter.h> |
| 10 | #include <linux/types.h> |
| 11 | |
| 12 | #define ARCH_TIMER_TYPE_CP15 BIT(0) |
| 13 | #define ARCH_TIMER_TYPE_MEM BIT(1) |
| 14 | |
| 15 | #define ARCH_TIMER_CTRL_ENABLE (1 << 0) |
| 16 | #define ARCH_TIMER_CTRL_IT_MASK (1 << 1) |
| 17 | #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) |
| 18 | |
| 19 | #define CNTHCTL_EL1PCTEN (1 << 0) |
| 20 | #define CNTHCTL_EL1PCEN (1 << 1) |
| 21 | #define CNTHCTL_EVNTEN (1 << 2) |
| 22 | #define CNTHCTL_EVNTDIR (1 << 3) |
| 23 | #define CNTHCTL_EVNTI (0xF << 4) |
| 24 | |
| 25 | enum arch_timer_reg { |
| 26 | ARCH_TIMER_REG_CTRL, |
| 27 | ARCH_TIMER_REG_TVAL, |
| 28 | }; |
| 29 | |
| 30 | enum arch_timer_ppi_nr { |
| 31 | ARCH_TIMER_PHYS_SECURE_PPI, |
| 32 | ARCH_TIMER_PHYS_NONSECURE_PPI, |
| 33 | ARCH_TIMER_VIRT_PPI, |
| 34 | ARCH_TIMER_HYP_PPI, |
| 35 | ARCH_TIMER_MAX_TIMER_PPI |
| 36 | }; |
| 37 | |
| 38 | enum arch_timer_spi_nr { |
| 39 | ARCH_TIMER_PHYS_SPI, |
| 40 | ARCH_TIMER_VIRT_SPI, |
| 41 | ARCH_TIMER_MAX_TIMER_SPI |
| 42 | }; |
| 43 | |
| 44 | #define ARCH_TIMER_PHYS_ACCESS 0 |
| 45 | #define ARCH_TIMER_VIRT_ACCESS 1 |
| 46 | #define ARCH_TIMER_MEM_PHYS_ACCESS 2 |
| 47 | #define ARCH_TIMER_MEM_VIRT_ACCESS 3 |
| 48 | |
| 49 | #define ARCH_TIMER_MEM_MAX_FRAMES 8 |
| 50 | |
| 51 | #define ARCH_TIMER_USR_PCT_ACCESS_EN (1 << 0) /* physical counter */ |
| 52 | #define ARCH_TIMER_USR_VCT_ACCESS_EN (1 << 1) /* virtual counter */ |
| 53 | #define ARCH_TIMER_VIRT_EVT_EN (1 << 2) |
| 54 | #define ARCH_TIMER_EVT_TRIGGER_SHIFT (4) |
| 55 | #define ARCH_TIMER_EVT_TRIGGER_MASK (0xF << ARCH_TIMER_EVT_TRIGGER_SHIFT) |
| 56 | #define ARCH_TIMER_USR_VT_ACCESS_EN (1 << 8) /* virtual timer registers */ |
| 57 | #define ARCH_TIMER_USR_PT_ACCESS_EN (1 << 9) /* physical timer registers */ |
| 58 | |
| 59 | #define ARCH_TIMER_EVT_STREAM_PERIOD_US 100 |
| 60 | #define ARCH_TIMER_EVT_STREAM_FREQ \ |
| 61 | (USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US) |
| 62 | |
| 63 | struct arch_timer_kvm_info { |
| 64 | struct timecounter timecounter; |
| 65 | int virtual_irq; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 66 | int physical_irq; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | struct arch_timer_mem_frame { |
| 70 | bool valid; |
| 71 | phys_addr_t cntbase; |
| 72 | size_t size; |
| 73 | int phys_irq; |
| 74 | int virt_irq; |
| 75 | }; |
| 76 | |
| 77 | struct arch_timer_mem { |
| 78 | phys_addr_t cntctlbase; |
| 79 | size_t size; |
| 80 | struct arch_timer_mem_frame frame[ARCH_TIMER_MEM_MAX_FRAMES]; |
| 81 | }; |
| 82 | |
| 83 | #ifdef CONFIG_ARM_ARCH_TIMER |
| 84 | |
| 85 | extern u32 arch_timer_get_rate(void); |
| 86 | extern u64 (*arch_timer_read_counter)(void); |
| 87 | extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void); |
| 88 | extern bool arch_timer_evtstrm_available(void); |
| 89 | |
| 90 | #else |
| 91 | |
| 92 | static inline u32 arch_timer_get_rate(void) |
| 93 | { |
| 94 | return 0; |
| 95 | } |
| 96 | |
| 97 | static inline u64 arch_timer_read_counter(void) |
| 98 | { |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | static inline bool arch_timer_evtstrm_available(void) |
| 103 | { |
| 104 | return false; |
| 105 | } |
| 106 | |
| 107 | #endif |
| 108 | |
| 109 | #endif |