David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 3 | config CLK_RENESAS |
| 4 | bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS |
| 5 | default y if ARCH_RENESAS |
| 6 | select CLK_EMEV2 if ARCH_EMEV2 |
| 7 | select CLK_RZA1 if ARCH_R7S72100 |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 8 | select CLK_R7S9210 if ARCH_R7S9210 |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 9 | select CLK_R8A73A4 if ARCH_R8A73A4 |
| 10 | select CLK_R8A7740 if ARCH_R8A7740 |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 11 | select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744 |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 12 | select CLK_R8A7745 if ARCH_R8A7745 |
| 13 | select CLK_R8A77470 if ARCH_R8A77470 |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 14 | select CLK_R8A774A1 if ARCH_R8A774A1 |
| 15 | select CLK_R8A774C0 if ARCH_R8A774C0 |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 16 | select CLK_R8A7778 if ARCH_R8A7778 |
| 17 | select CLK_R8A7779 if ARCH_R8A7779 |
| 18 | select CLK_R8A7790 if ARCH_R8A7790 |
| 19 | select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793 |
| 20 | select CLK_R8A7792 if ARCH_R8A7792 |
| 21 | select CLK_R8A7794 if ARCH_R8A7794 |
| 22 | select CLK_R8A7795 if ARCH_R8A7795 |
| 23 | select CLK_R8A7796 if ARCH_R8A7796 |
| 24 | select CLK_R8A77965 if ARCH_R8A77965 |
| 25 | select CLK_R8A77970 if ARCH_R8A77970 |
| 26 | select CLK_R8A77980 if ARCH_R8A77980 |
| 27 | select CLK_R8A77990 if ARCH_R8A77990 |
| 28 | select CLK_R8A77995 if ARCH_R8A77995 |
| 29 | select CLK_R9A06G032 if ARCH_R9A06G032 |
| 30 | select CLK_SH73A0 if ARCH_SH73A0 |
| 31 | |
| 32 | if CLK_RENESAS |
| 33 | |
| 34 | config CLK_RENESAS_LEGACY |
| 35 | bool "Legacy DT clock support" |
| 36 | depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794 |
| 37 | help |
| 38 | Enable backward compatibility with old device trees describing a |
| 39 | hierarchical representation of the various CPG and MSTP clocks. |
| 40 | |
| 41 | Say Y if you want your kernel to work with old DTBs. |
| 42 | It is safe to say N if you use the DTS that is supplied with the |
| 43 | current kernel source tree. |
| 44 | |
| 45 | # SoC |
| 46 | config CLK_EMEV2 |
| 47 | bool "Emma Mobile EV2 clock support" if COMPILE_TEST |
| 48 | |
| 49 | config CLK_RZA1 |
| 50 | bool "RZ/A1H clock support" if COMPILE_TEST |
| 51 | select CLK_RENESAS_CPG_MSTP |
| 52 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 53 | config CLK_R7S9210 |
| 54 | bool "RZ/A2 clock support" if COMPILE_TEST |
| 55 | select CLK_RENESAS_CPG_MSSR |
| 56 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 57 | config CLK_R8A73A4 |
| 58 | bool "R-Mobile APE6 clock support" if COMPILE_TEST |
| 59 | select CLK_RENESAS_CPG_MSTP |
| 60 | select CLK_RENESAS_DIV6 |
| 61 | |
| 62 | config CLK_R8A7740 |
| 63 | bool "R-Mobile A1 clock support" if COMPILE_TEST |
| 64 | select CLK_RENESAS_CPG_MSTP |
| 65 | select CLK_RENESAS_DIV6 |
| 66 | |
| 67 | config CLK_R8A7743 |
| 68 | bool "RZ/G1M clock support" if COMPILE_TEST |
| 69 | select CLK_RCAR_GEN2_CPG |
| 70 | |
| 71 | config CLK_R8A7745 |
| 72 | bool "RZ/G1E clock support" if COMPILE_TEST |
| 73 | select CLK_RCAR_GEN2_CPG |
| 74 | |
| 75 | config CLK_R8A77470 |
| 76 | bool "RZ/G1C clock support" if COMPILE_TEST |
| 77 | select CLK_RCAR_GEN2_CPG |
| 78 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 79 | config CLK_R8A774A1 |
| 80 | bool "RZ/G2M clock support" if COMPILE_TEST |
| 81 | select CLK_RCAR_GEN3_CPG |
| 82 | |
| 83 | config CLK_R8A774C0 |
| 84 | bool "RZ/G2E clock support" if COMPILE_TEST |
| 85 | select CLK_RCAR_GEN3_CPG |
| 86 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 87 | config CLK_R8A7778 |
| 88 | bool "R-Car M1A clock support" if COMPILE_TEST |
| 89 | select CLK_RENESAS_CPG_MSTP |
| 90 | |
| 91 | config CLK_R8A7779 |
| 92 | bool "R-Car H1 clock support" if COMPILE_TEST |
| 93 | select CLK_RENESAS_CPG_MSTP |
| 94 | |
| 95 | config CLK_R8A7790 |
| 96 | bool "R-Car H2 clock support" if COMPILE_TEST |
| 97 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
| 98 | select CLK_RCAR_GEN2_CPG |
| 99 | select CLK_RENESAS_DIV6 |
| 100 | |
| 101 | config CLK_R8A7791 |
| 102 | bool "R-Car M2-W/N clock support" if COMPILE_TEST |
| 103 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
| 104 | select CLK_RCAR_GEN2_CPG |
| 105 | select CLK_RENESAS_DIV6 |
| 106 | |
| 107 | config CLK_R8A7792 |
| 108 | bool "R-Car V2H clock support" if COMPILE_TEST |
| 109 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
| 110 | select CLK_RCAR_GEN2_CPG |
| 111 | |
| 112 | config CLK_R8A7794 |
| 113 | bool "R-Car E2 clock support" if COMPILE_TEST |
| 114 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
| 115 | select CLK_RCAR_GEN2_CPG |
| 116 | select CLK_RENESAS_DIV6 |
| 117 | |
| 118 | config CLK_R8A7795 |
| 119 | bool "R-Car H3 clock support" if COMPILE_TEST |
| 120 | select CLK_RCAR_GEN3_CPG |
| 121 | |
| 122 | config CLK_R8A7796 |
| 123 | bool "R-Car M3-W clock support" if COMPILE_TEST |
| 124 | select CLK_RCAR_GEN3_CPG |
| 125 | |
| 126 | config CLK_R8A77965 |
| 127 | bool "R-Car M3-N clock support" if COMPILE_TEST |
| 128 | select CLK_RCAR_GEN3_CPG |
| 129 | |
| 130 | config CLK_R8A77970 |
| 131 | bool "R-Car V3M clock support" if COMPILE_TEST |
| 132 | select CLK_RCAR_GEN3_CPG |
| 133 | |
| 134 | config CLK_R8A77980 |
| 135 | bool "R-Car V3H clock support" if COMPILE_TEST |
| 136 | select CLK_RCAR_GEN3_CPG |
| 137 | |
| 138 | config CLK_R8A77990 |
| 139 | bool "R-Car E3 clock support" if COMPILE_TEST |
| 140 | select CLK_RCAR_GEN3_CPG |
| 141 | |
| 142 | config CLK_R8A77995 |
| 143 | bool "R-Car D3 clock support" if COMPILE_TEST |
| 144 | select CLK_RCAR_GEN3_CPG |
| 145 | |
| 146 | config CLK_R9A06G032 |
| 147 | bool "Renesas R9A06G032 clock driver" |
| 148 | help |
| 149 | This is a driver for R9A06G032 clocks |
| 150 | |
| 151 | config CLK_SH73A0 |
| 152 | bool "SH-Mobile AG5 clock support" if COMPILE_TEST |
| 153 | select CLK_RENESAS_CPG_MSTP |
| 154 | select CLK_RENESAS_DIV6 |
| 155 | |
| 156 | |
| 157 | # Family |
| 158 | config CLK_RCAR_GEN2 |
| 159 | bool "R-Car Gen2 legacy clock support" if COMPILE_TEST |
| 160 | select CLK_RENESAS_CPG_MSTP |
| 161 | select CLK_RENESAS_DIV6 |
| 162 | |
| 163 | config CLK_RCAR_GEN2_CPG |
| 164 | bool "R-Car Gen2 CPG clock support" if COMPILE_TEST |
| 165 | select CLK_RENESAS_CPG_MSSR |
| 166 | |
| 167 | config CLK_RCAR_GEN3_CPG |
| 168 | bool "R-Car Gen3 CPG clock support" if COMPILE_TEST |
| 169 | select CLK_RENESAS_CPG_MSSR |
| 170 | |
| 171 | config CLK_RCAR_USB2_CLOCK_SEL |
| 172 | bool "Renesas R-Car USB2 clock selector support" |
| 173 | depends on ARCH_RENESAS || COMPILE_TEST |
| 174 | help |
| 175 | This is a driver for R-Car USB2 clock selector |
| 176 | |
| 177 | # Generic |
| 178 | config CLK_RENESAS_CPG_MSSR |
| 179 | bool "CPG/MSSR clock support" if COMPILE_TEST |
| 180 | select CLK_RENESAS_DIV6 |
| 181 | |
| 182 | config CLK_RENESAS_CPG_MSTP |
| 183 | bool "MSTP clock support" if COMPILE_TEST |
| 184 | |
| 185 | config CLK_RENESAS_DIV6 |
| 186 | bool "DIV6 clock support" if COMPILE_TEST |
| 187 | |
| 188 | endif # CLK_RENESAS |