Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Generate definitions needed by assembly language modules. |
| 4 | * This code generates raw asm output which is post-processed to extract |
| 5 | * and format the required data. |
| 6 | */ |
| 7 | #define COMPILE_OFFSETS |
| 8 | |
| 9 | #include <linux/crypto.h> |
| 10 | #include <linux/sched.h> |
| 11 | #include <linux/stddef.h> |
| 12 | #include <linux/hardirq.h> |
| 13 | #include <linux/suspend.h> |
| 14 | #include <linux/kbuild.h> |
| 15 | #include <asm/processor.h> |
| 16 | #include <asm/thread_info.h> |
| 17 | #include <asm/sigframe.h> |
| 18 | #include <asm/bootparam.h> |
| 19 | #include <asm/suspend.h> |
| 20 | #include <asm/tlbflush.h> |
| 21 | |
| 22 | #ifdef CONFIG_XEN |
| 23 | #include <xen/interface/xen.h> |
| 24 | #endif |
| 25 | |
| 26 | #ifdef CONFIG_X86_32 |
| 27 | # include "asm-offsets_32.c" |
| 28 | #else |
| 29 | # include "asm-offsets_64.c" |
| 30 | #endif |
| 31 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 32 | static void __used common(void) |
| 33 | { |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 34 | BLANK(); |
| 35 | OFFSET(TASK_threadsp, task_struct, thread.sp); |
| 36 | #ifdef CONFIG_STACKPROTECTOR |
| 37 | OFFSET(TASK_stack_canary, task_struct, stack_canary); |
| 38 | #endif |
| 39 | |
| 40 | BLANK(); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 41 | OFFSET(TASK_addr_limit, task_struct, thread.addr_limit); |
| 42 | |
| 43 | BLANK(); |
| 44 | OFFSET(crypto_tfm_ctx_offset, crypto_tfm, __crt_ctx); |
| 45 | |
| 46 | BLANK(); |
| 47 | OFFSET(pbe_address, pbe, address); |
| 48 | OFFSET(pbe_orig_address, pbe, orig_address); |
| 49 | OFFSET(pbe_next, pbe, next); |
| 50 | |
| 51 | #if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION) |
| 52 | BLANK(); |
| 53 | OFFSET(IA32_SIGCONTEXT_ax, sigcontext_32, ax); |
| 54 | OFFSET(IA32_SIGCONTEXT_bx, sigcontext_32, bx); |
| 55 | OFFSET(IA32_SIGCONTEXT_cx, sigcontext_32, cx); |
| 56 | OFFSET(IA32_SIGCONTEXT_dx, sigcontext_32, dx); |
| 57 | OFFSET(IA32_SIGCONTEXT_si, sigcontext_32, si); |
| 58 | OFFSET(IA32_SIGCONTEXT_di, sigcontext_32, di); |
| 59 | OFFSET(IA32_SIGCONTEXT_bp, sigcontext_32, bp); |
| 60 | OFFSET(IA32_SIGCONTEXT_sp, sigcontext_32, sp); |
| 61 | OFFSET(IA32_SIGCONTEXT_ip, sigcontext_32, ip); |
| 62 | |
| 63 | BLANK(); |
| 64 | OFFSET(IA32_RT_SIGFRAME_sigcontext, rt_sigframe_ia32, uc.uc_mcontext); |
| 65 | #endif |
| 66 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 67 | #ifdef CONFIG_PARAVIRT_XXL |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 68 | BLANK(); |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 69 | OFFSET(PV_IRQ_irq_disable, paravirt_patch_template, irq.irq_disable); |
| 70 | OFFSET(PV_IRQ_irq_enable, paravirt_patch_template, irq.irq_enable); |
| 71 | OFFSET(PV_CPU_iret, paravirt_patch_template, cpu.iret); |
| 72 | OFFSET(PV_MMU_read_cr2, paravirt_patch_template, mmu.read_cr2); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 73 | #endif |
| 74 | |
| 75 | #ifdef CONFIG_XEN |
| 76 | BLANK(); |
| 77 | OFFSET(XEN_vcpu_info_mask, vcpu_info, evtchn_upcall_mask); |
| 78 | OFFSET(XEN_vcpu_info_pending, vcpu_info, evtchn_upcall_pending); |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 79 | OFFSET(XEN_vcpu_info_arch_cr2, vcpu_info, arch.cr2); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 80 | #endif |
| 81 | |
| 82 | BLANK(); |
| 83 | OFFSET(BP_scratch, boot_params, scratch); |
| 84 | OFFSET(BP_secure_boot, boot_params, secure_boot); |
| 85 | OFFSET(BP_loadflags, boot_params, hdr.loadflags); |
| 86 | OFFSET(BP_hardware_subarch, boot_params, hdr.hardware_subarch); |
| 87 | OFFSET(BP_version, boot_params, hdr.version); |
| 88 | OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment); |
| 89 | OFFSET(BP_init_size, boot_params, hdr.init_size); |
| 90 | OFFSET(BP_pref_address, boot_params, hdr.pref_address); |
| 91 | OFFSET(BP_code32_start, boot_params, hdr.code32_start); |
| 92 | |
| 93 | BLANK(); |
| 94 | DEFINE(PTREGS_SIZE, sizeof(struct pt_regs)); |
| 95 | |
| 96 | /* TLB state for the entry code */ |
| 97 | OFFSET(TLB_STATE_user_pcid_flush_mask, tlb_state, user_pcid_flush_mask); |
| 98 | |
| 99 | /* Layout info for cpu_entry_area */ |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 100 | OFFSET(CPU_ENTRY_AREA_entry_stack, cpu_entry_area, entry_stack_page); |
| 101 | DEFINE(SIZEOF_entry_stack, sizeof(struct entry_stack)); |
| 102 | DEFINE(MASK_entry_stack, (~(sizeof(struct entry_stack) - 1))); |
| 103 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 104 | /* Offset for fields in tss_struct */ |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 105 | OFFSET(TSS_sp0, tss_struct, x86_tss.sp0); |
| 106 | OFFSET(TSS_sp1, tss_struct, x86_tss.sp1); |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 107 | OFFSET(TSS_sp2, tss_struct, x86_tss.sp2); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 108 | } |