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review.trustedfirmware.org / hafnium / third_party / linux.git / 0f672f6c0b52b7b0700b0915c72b540721af4465 / . / arch / x86 / include / asm / vmx.h
blob: 1835767aa3356bf87f3b2d7ec4db2112223c8c09 [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]2/*
3 * vmx.h: VMX Architecture related definitions
4 * Copyright (c) 2004, Intel Corporation.
5 *
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]6 * A few random additions are:
7 * Copyright (C) 2006 Qumranet
8 * Avi Kivity <avi@qumranet.com>
9 * Yaniv Kamay <yaniv@qumranet.com>
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]10 */
11#ifndef VMX_H
12#define VMX_H
13
14
15#include <linux/bitops.h>
16#include <linux/types.h>
17#include <uapi/asm/vmx.h>
18
19/*
20 * Definitions of Primary Processor-Based VM-Execution Controls.
21 */
22#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
23#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
24#define CPU_BASED_HLT_EXITING 0x00000080
25#define CPU_BASED_INVLPG_EXITING 0x00000200
26#define CPU_BASED_MWAIT_EXITING 0x00000400
27#define CPU_BASED_RDPMC_EXITING 0x00000800
28#define CPU_BASED_RDTSC_EXITING 0x00001000
29#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
30#define CPU_BASED_CR3_STORE_EXITING 0x00010000
31#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
32#define CPU_BASED_CR8_STORE_EXITING 0x00100000
33#define CPU_BASED_TPR_SHADOW 0x00200000
34#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
35#define CPU_BASED_MOV_DR_EXITING 0x00800000
36#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
37#define CPU_BASED_USE_IO_BITMAPS 0x02000000
38#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
39#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
40#define CPU_BASED_MONITOR_EXITING 0x20000000
41#define CPU_BASED_PAUSE_EXITING 0x40000000
42#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
43
44#define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
45
46/*
47 * Definitions of Secondary Processor-Based VM-Execution Controls.
48 */
49#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
50#define SECONDARY_EXEC_ENABLE_EPT 0x00000002
51#define SECONDARY_EXEC_DESC 0x00000004
52#define SECONDARY_EXEC_RDTSCP 0x00000008
53#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
54#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
55#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
56#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
57#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
58#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
59#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
60#define SECONDARY_EXEC_RDRAND_EXITING 0x00000800
61#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
62#define SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
63#define SECONDARY_EXEC_SHADOW_VMCS 0x00004000
64#define SECONDARY_EXEC_ENCLS_EXITING 0x00008000
65#define SECONDARY_EXEC_RDSEED_EXITING 0x00010000
66#define SECONDARY_EXEC_ENABLE_PML 0x00020000
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]67#define SECONDARY_EXEC_PT_CONCEAL_VMX 0x00080000
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]68#define SECONDARY_EXEC_XSAVES 0x00100000
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]69#define SECONDARY_EXEC_PT_USE_GPA 0x01000000
70#define SECONDARY_EXEC_MODE_BASED_EPT_EXEC 0x00400000
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]71#define SECONDARY_EXEC_TSC_SCALING 0x02000000
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]72#define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE 0x04000000
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]73
74#define PIN_BASED_EXT_INTR_MASK 0x00000001
75#define PIN_BASED_NMI_EXITING 0x00000008
76#define PIN_BASED_VIRTUAL_NMIS 0x00000020
77#define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
78#define PIN_BASED_POSTED_INTR 0x00000080
79
80#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
81
82#define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
83#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
84#define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
85#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
86#define VM_EXIT_SAVE_IA32_PAT 0x00040000
87#define VM_EXIT_LOAD_IA32_PAT 0x00080000
88#define VM_EXIT_SAVE_IA32_EFER 0x00100000
89#define VM_EXIT_LOAD_IA32_EFER 0x00200000
90#define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
91#define VM_EXIT_CLEAR_BNDCFGS 0x00800000
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]92#define VM_EXIT_PT_CONCEAL_PIP 0x01000000
93#define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]94
95#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
96
97#define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
98#define VM_ENTRY_IA32E_MODE 0x00000200
99#define VM_ENTRY_SMM 0x00000400
100#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
101#define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
102#define VM_ENTRY_LOAD_IA32_PAT 0x00004000
103#define VM_ENTRY_LOAD_IA32_EFER 0x00008000
104#define VM_ENTRY_LOAD_BNDCFGS 0x00010000
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]105#define VM_ENTRY_PT_CONCEAL_PIP 0x00020000
106#define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]107
108#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
109
110#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
111#define VMX_MISC_SAVE_EFER_LMA 0x00000020
112#define VMX_MISC_ACTIVITY_HLT 0x00000040
113#define VMX_MISC_ZERO_LEN_INS 0x40000000
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]114#define VMX_MISC_MSR_LIST_MULTIPLIER 512
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]115
116/* VMFUNC functions */
117#define VMX_VMFUNC_EPTP_SWITCHING 0x00000001
118#define VMFUNC_EPTP_ENTRIES 512
119
120static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
121{
122 return vmx_basic & GENMASK_ULL(30, 0);
123}
124
125static inline u32 vmx_basic_vmcs_size(u64 vmx_basic)
126{
127 return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;
128}
129
130static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
131{
132 return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
133}
134
135static inline int vmx_misc_cr3_count(u64 vmx_misc)
136{
137 return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;
138}
139
140static inline int vmx_misc_max_msr(u64 vmx_misc)
141{
142 return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;
143}
144
145static inline int vmx_misc_mseg_revid(u64 vmx_misc)
146{
147 return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;
148}
149
150/* VMCS Encodings */
151enum vmcs_field {
152 VIRTUAL_PROCESSOR_ID = 0x00000000,
153 POSTED_INTR_NV = 0x00000002,
154 GUEST_ES_SELECTOR = 0x00000800,
155 GUEST_CS_SELECTOR = 0x00000802,
156 GUEST_SS_SELECTOR = 0x00000804,
157 GUEST_DS_SELECTOR = 0x00000806,
158 GUEST_FS_SELECTOR = 0x00000808,
159 GUEST_GS_SELECTOR = 0x0000080a,
160 GUEST_LDTR_SELECTOR = 0x0000080c,
161 GUEST_TR_SELECTOR = 0x0000080e,
162 GUEST_INTR_STATUS = 0x00000810,
163 GUEST_PML_INDEX = 0x00000812,
164 HOST_ES_SELECTOR = 0x00000c00,
165 HOST_CS_SELECTOR = 0x00000c02,
166 HOST_SS_SELECTOR = 0x00000c04,
167 HOST_DS_SELECTOR = 0x00000c06,
168 HOST_FS_SELECTOR = 0x00000c08,
169 HOST_GS_SELECTOR = 0x00000c0a,
170 HOST_TR_SELECTOR = 0x00000c0c,
171 IO_BITMAP_A = 0x00002000,
172 IO_BITMAP_A_HIGH = 0x00002001,
173 IO_BITMAP_B = 0x00002002,
174 IO_BITMAP_B_HIGH = 0x00002003,
175 MSR_BITMAP = 0x00002004,
176 MSR_BITMAP_HIGH = 0x00002005,
177 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
178 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
179 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
180 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
181 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
182 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
183 PML_ADDRESS = 0x0000200e,
184 PML_ADDRESS_HIGH = 0x0000200f,
185 TSC_OFFSET = 0x00002010,
186 TSC_OFFSET_HIGH = 0x00002011,
187 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
188 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
189 APIC_ACCESS_ADDR = 0x00002014,
190 APIC_ACCESS_ADDR_HIGH = 0x00002015,
191 POSTED_INTR_DESC_ADDR = 0x00002016,
192 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
193 VM_FUNCTION_CONTROL = 0x00002018,
194 VM_FUNCTION_CONTROL_HIGH = 0x00002019,
195 EPT_POINTER = 0x0000201a,
196 EPT_POINTER_HIGH = 0x0000201b,
197 EOI_EXIT_BITMAP0 = 0x0000201c,
198 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
199 EOI_EXIT_BITMAP1 = 0x0000201e,
200 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
201 EOI_EXIT_BITMAP2 = 0x00002020,
202 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
203 EOI_EXIT_BITMAP3 = 0x00002022,
204 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
205 EPTP_LIST_ADDRESS = 0x00002024,
206 EPTP_LIST_ADDRESS_HIGH = 0x00002025,
207 VMREAD_BITMAP = 0x00002026,
208 VMREAD_BITMAP_HIGH = 0x00002027,
209 VMWRITE_BITMAP = 0x00002028,
210 VMWRITE_BITMAP_HIGH = 0x00002029,
211 XSS_EXIT_BITMAP = 0x0000202C,
212 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
213 ENCLS_EXITING_BITMAP = 0x0000202E,
214 ENCLS_EXITING_BITMAP_HIGH = 0x0000202F,
215 TSC_MULTIPLIER = 0x00002032,
216 TSC_MULTIPLIER_HIGH = 0x00002033,
217 GUEST_PHYSICAL_ADDRESS = 0x00002400,
218 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
219 VMCS_LINK_POINTER = 0x00002800,
220 VMCS_LINK_POINTER_HIGH = 0x00002801,
221 GUEST_IA32_DEBUGCTL = 0x00002802,
222 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
223 GUEST_IA32_PAT = 0x00002804,
224 GUEST_IA32_PAT_HIGH = 0x00002805,
225 GUEST_IA32_EFER = 0x00002806,
226 GUEST_IA32_EFER_HIGH = 0x00002807,
227 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
228 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
229 GUEST_PDPTR0 = 0x0000280a,
230 GUEST_PDPTR0_HIGH = 0x0000280b,
231 GUEST_PDPTR1 = 0x0000280c,
232 GUEST_PDPTR1_HIGH = 0x0000280d,
233 GUEST_PDPTR2 = 0x0000280e,
234 GUEST_PDPTR2_HIGH = 0x0000280f,
235 GUEST_PDPTR3 = 0x00002810,
236 GUEST_PDPTR3_HIGH = 0x00002811,
237 GUEST_BNDCFGS = 0x00002812,
238 GUEST_BNDCFGS_HIGH = 0x00002813,
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]239 GUEST_IA32_RTIT_CTL = 0x00002814,
240 GUEST_IA32_RTIT_CTL_HIGH = 0x00002815,
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]241 HOST_IA32_PAT = 0x00002c00,
242 HOST_IA32_PAT_HIGH = 0x00002c01,
243 HOST_IA32_EFER = 0x00002c02,
244 HOST_IA32_EFER_HIGH = 0x00002c03,
245 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
246 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
247 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
248 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
249 EXCEPTION_BITMAP = 0x00004004,
250 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
251 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
252 CR3_TARGET_COUNT = 0x0000400a,
253 VM_EXIT_CONTROLS = 0x0000400c,
254 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
255 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
256 VM_ENTRY_CONTROLS = 0x00004012,
257 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
258 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
259 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
260 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
261 TPR_THRESHOLD = 0x0000401c,
262 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
263 PLE_GAP = 0x00004020,
264 PLE_WINDOW = 0x00004022,
265 VM_INSTRUCTION_ERROR = 0x00004400,
266 VM_EXIT_REASON = 0x00004402,
267 VM_EXIT_INTR_INFO = 0x00004404,
268 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
269 IDT_VECTORING_INFO_FIELD = 0x00004408,
270 IDT_VECTORING_ERROR_CODE = 0x0000440a,
271 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
272 VMX_INSTRUCTION_INFO = 0x0000440e,
273 GUEST_ES_LIMIT = 0x00004800,
274 GUEST_CS_LIMIT = 0x00004802,
275 GUEST_SS_LIMIT = 0x00004804,
276 GUEST_DS_LIMIT = 0x00004806,
277 GUEST_FS_LIMIT = 0x00004808,
278 GUEST_GS_LIMIT = 0x0000480a,
279 GUEST_LDTR_LIMIT = 0x0000480c,
280 GUEST_TR_LIMIT = 0x0000480e,
281 GUEST_GDTR_LIMIT = 0x00004810,
282 GUEST_IDTR_LIMIT = 0x00004812,
283 GUEST_ES_AR_BYTES = 0x00004814,
284 GUEST_CS_AR_BYTES = 0x00004816,
285 GUEST_SS_AR_BYTES = 0x00004818,
286 GUEST_DS_AR_BYTES = 0x0000481a,
287 GUEST_FS_AR_BYTES = 0x0000481c,
288 GUEST_GS_AR_BYTES = 0x0000481e,
289 GUEST_LDTR_AR_BYTES = 0x00004820,
290 GUEST_TR_AR_BYTES = 0x00004822,
291 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
292 GUEST_ACTIVITY_STATE = 0X00004826,
293 GUEST_SYSENTER_CS = 0x0000482A,
294 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
295 HOST_IA32_SYSENTER_CS = 0x00004c00,
296 CR0_GUEST_HOST_MASK = 0x00006000,
297 CR4_GUEST_HOST_MASK = 0x00006002,
298 CR0_READ_SHADOW = 0x00006004,
299 CR4_READ_SHADOW = 0x00006006,
300 CR3_TARGET_VALUE0 = 0x00006008,
301 CR3_TARGET_VALUE1 = 0x0000600a,
302 CR3_TARGET_VALUE2 = 0x0000600c,
303 CR3_TARGET_VALUE3 = 0x0000600e,
304 EXIT_QUALIFICATION = 0x00006400,
305 GUEST_LINEAR_ADDRESS = 0x0000640a,
306 GUEST_CR0 = 0x00006800,
307 GUEST_CR3 = 0x00006802,
308 GUEST_CR4 = 0x00006804,
309 GUEST_ES_BASE = 0x00006806,
310 GUEST_CS_BASE = 0x00006808,
311 GUEST_SS_BASE = 0x0000680a,
312 GUEST_DS_BASE = 0x0000680c,
313 GUEST_FS_BASE = 0x0000680e,
314 GUEST_GS_BASE = 0x00006810,
315 GUEST_LDTR_BASE = 0x00006812,
316 GUEST_TR_BASE = 0x00006814,
317 GUEST_GDTR_BASE = 0x00006816,
318 GUEST_IDTR_BASE = 0x00006818,
319 GUEST_DR7 = 0x0000681a,
320 GUEST_RSP = 0x0000681c,
321 GUEST_RIP = 0x0000681e,
322 GUEST_RFLAGS = 0x00006820,
323 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
324 GUEST_SYSENTER_ESP = 0x00006824,
325 GUEST_SYSENTER_EIP = 0x00006826,
326 HOST_CR0 = 0x00006c00,
327 HOST_CR3 = 0x00006c02,
328 HOST_CR4 = 0x00006c04,
329 HOST_FS_BASE = 0x00006c06,
330 HOST_GS_BASE = 0x00006c08,
331 HOST_TR_BASE = 0x00006c0a,
332 HOST_GDTR_BASE = 0x00006c0c,
333 HOST_IDTR_BASE = 0x00006c0e,
334 HOST_IA32_SYSENTER_ESP = 0x00006c10,
335 HOST_IA32_SYSENTER_EIP = 0x00006c12,
336 HOST_RSP = 0x00006c14,
337 HOST_RIP = 0x00006c16,
338};
339
340/*
341 * Interruption-information format
342 */
343#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
344#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
345#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
346#define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
347#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
348#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
349
350#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
351#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
352#define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
353#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
354
355#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
356#define INTR_TYPE_RESERVED (1 << 8) /* reserved */
357#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
358#define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
359#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
360#define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */
361#define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
362#define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */
363
364/* GUEST_INTERRUPTIBILITY_INFO flags. */
365#define GUEST_INTR_STATE_STI 0x00000001
366#define GUEST_INTR_STATE_MOV_SS 0x00000002
367#define GUEST_INTR_STATE_SMI 0x00000004
368#define GUEST_INTR_STATE_NMI 0x00000008
369
370/* GUEST_ACTIVITY_STATE flags */
371#define GUEST_ACTIVITY_ACTIVE 0
372#define GUEST_ACTIVITY_HLT 1
373#define GUEST_ACTIVITY_SHUTDOWN 2
374#define GUEST_ACTIVITY_WAIT_SIPI 3
375
376/*
377 * Exit Qualifications for MOV for Control Register Access
378 */
379#define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
380#define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
381#define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
382#define LMSW_SOURCE_DATA_SHIFT 16
383#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
384#define REG_EAX (0 << 8)
385#define REG_ECX (1 << 8)
386#define REG_EDX (2 << 8)
387#define REG_EBX (3 << 8)
388#define REG_ESP (4 << 8)
389#define REG_EBP (5 << 8)
390#define REG_ESI (6 << 8)
391#define REG_EDI (7 << 8)
392#define REG_R8 (8 << 8)
393#define REG_R9 (9 << 8)
394#define REG_R10 (10 << 8)
395#define REG_R11 (11 << 8)
396#define REG_R12 (12 << 8)
397#define REG_R13 (13 << 8)
398#define REG_R14 (14 << 8)
399#define REG_R15 (15 << 8)
400
401/*
402 * Exit Qualifications for MOV for Debug Register Access
403 */
404#define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
405#define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
406#define TYPE_MOV_TO_DR (0 << 4)
407#define TYPE_MOV_FROM_DR (1 << 4)
408#define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
409
410
411/*
412 * Exit Qualifications for APIC-Access
413 */
414#define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
415#define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
416#define TYPE_LINEAR_APIC_INST_READ (0 << 12)
417#define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
418#define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
419#define TYPE_LINEAR_APIC_EVENT (3 << 12)
420#define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
421#define TYPE_PHYSICAL_APIC_INST (15 << 12)
422
423/* segment AR in VMCS -- these are different from what LAR reports */
424#define VMX_SEGMENT_AR_L_MASK (1 << 13)
425
426#define VMX_AR_TYPE_ACCESSES_MASK 1
427#define VMX_AR_TYPE_READABLE_MASK (1 << 1)
428#define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
429#define VMX_AR_TYPE_CODE_MASK (1 << 3)
430#define VMX_AR_TYPE_MASK 0x0f
431#define VMX_AR_TYPE_BUSY_64_TSS 11
432#define VMX_AR_TYPE_BUSY_32_TSS 11
433#define VMX_AR_TYPE_BUSY_16_TSS 3
434#define VMX_AR_TYPE_LDT 2
435
436#define VMX_AR_UNUSABLE_MASK (1 << 16)
437#define VMX_AR_S_MASK (1 << 4)
438#define VMX_AR_P_MASK (1 << 7)
439#define VMX_AR_L_MASK (1 << 13)
440#define VMX_AR_DB_MASK (1 << 14)
441#define VMX_AR_G_MASK (1 << 15)
442#define VMX_AR_DPL_SHIFT 5
443#define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
444
445#define VMX_AR_RESERVD_MASK 0xfffe0f00
446
447#define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
448#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
449#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
450
451#define VMX_NR_VPIDS (1 << 16)
452#define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
453#define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
454#define VMX_VPID_EXTENT_ALL_CONTEXT 2
455#define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3
456
457#define VMX_EPT_EXTENT_CONTEXT 1
458#define VMX_EPT_EXTENT_GLOBAL 2
459#define VMX_EPT_EXTENT_SHIFT 24
460
461#define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
462#define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
463#define VMX_EPT_PAGE_WALK_5_BIT (1ull << 7)
464#define VMX_EPTP_UC_BIT (1ull << 8)
465#define VMX_EPTP_WB_BIT (1ull << 14)
466#define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
467#define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
468#define VMX_EPT_INVEPT_BIT (1ull << 20)
469#define VMX_EPT_AD_BIT (1ull << 21)
470#define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
471#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
472
473#define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */
474#define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8) /* (40 - 32) */
475#define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */
476#define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */
477#define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11) /* (43 - 32) */
478
479#define VMX_EPT_MT_EPTE_SHIFT 3
480#define VMX_EPTP_PWL_MASK 0x38ull
481#define VMX_EPTP_PWL_4 0x18ull
482#define VMX_EPTP_PWL_5 0x20ull
483#define VMX_EPTP_AD_ENABLE_BIT (1ull << 6)
484#define VMX_EPTP_MT_MASK 0x7ull
485#define VMX_EPTP_MT_WB 0x6ull
486#define VMX_EPTP_MT_UC 0x0ull
487#define VMX_EPT_READABLE_MASK 0x1ull
488#define VMX_EPT_WRITABLE_MASK 0x2ull
489#define VMX_EPT_EXECUTABLE_MASK 0x4ull
490#define VMX_EPT_IPAT_BIT (1ull << 6)
491#define VMX_EPT_ACCESS_BIT (1ull << 8)
492#define VMX_EPT_DIRTY_BIT (1ull << 9)
493#define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \
494 VMX_EPT_WRITABLE_MASK | \
495 VMX_EPT_EXECUTABLE_MASK)
496#define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT)
497
498/* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */
499#define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \
500 VMX_EPT_EXECUTABLE_MASK)
501
502#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
503
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]504struct vmx_msr_entry {
505 u32 index;
506 u32 reserved;
507 u64 value;
508} __aligned(16);
509
510/*
511 * Exit Qualifications for entry failure during or after loading guest state
512 */
513#define ENTRY_FAIL_DEFAULT 0
514#define ENTRY_FAIL_PDPTE 2
515#define ENTRY_FAIL_NMI 3
516#define ENTRY_FAIL_VMCS_LINK_PTR 4
517
518/*
519 * Exit Qualifications for EPT Violations
520 */
521#define EPT_VIOLATION_ACC_READ_BIT 0
522#define EPT_VIOLATION_ACC_WRITE_BIT 1
523#define EPT_VIOLATION_ACC_INSTR_BIT 2
524#define EPT_VIOLATION_READABLE_BIT 3
525#define EPT_VIOLATION_WRITABLE_BIT 4
526#define EPT_VIOLATION_EXECUTABLE_BIT 5
527#define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
528#define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT)
529#define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT)
530#define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT)
531#define EPT_VIOLATION_READABLE (1 << EPT_VIOLATION_READABLE_BIT)
532#define EPT_VIOLATION_WRITABLE (1 << EPT_VIOLATION_WRITABLE_BIT)
533#define EPT_VIOLATION_EXECUTABLE (1 << EPT_VIOLATION_EXECUTABLE_BIT)
534#define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT)
535
536/*
537 * VM-instruction error numbers
538 */
539enum vm_instruction_error_number {
540 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
541 VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
542 VMXERR_VMCLEAR_VMXON_POINTER = 3,
543 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
544 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
545 VMXERR_VMRESUME_AFTER_VMXOFF = 6,
546 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
547 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
548 VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
549 VMXERR_VMPTRLD_VMXON_POINTER = 10,
550 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
551 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
552 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
553 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
554 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
555 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
556 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
557 VMXERR_VMCALL_NONCLEAR_VMCS = 19,
558 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
559 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
560 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
561 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
562 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
563 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
564 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
565};
566
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]567/*
568 * VM-instruction errors that can be encountered on VM-Enter, used to trace
569 * nested VM-Enter failures reported by hardware. Errors unique to VM-Enter
570 * from a SMI Transfer Monitor are not included as things have gone seriously
571 * sideways if we get one of those...
572 */
573#define VMX_VMENTER_INSTRUCTION_ERRORS \
574 { VMXERR_VMLAUNCH_NONCLEAR_VMCS, "VMLAUNCH_NONCLEAR_VMCS" }, \
575 { VMXERR_VMRESUME_NONLAUNCHED_VMCS, "VMRESUME_NONLAUNCHED_VMCS" }, \
576 { VMXERR_VMRESUME_AFTER_VMXOFF, "VMRESUME_AFTER_VMXOFF" }, \
577 { VMXERR_ENTRY_INVALID_CONTROL_FIELD, "VMENTRY_INVALID_CONTROL_FIELD" }, \
578 { VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, "VMENTRY_INVALID_HOST_STATE_FIELD" }, \
579 { VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, "VMENTRY_EVENTS_BLOCKED_BY_MOV_SS" }
580
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]581enum vmx_l1d_flush_state {
582 VMENTER_L1D_FLUSH_AUTO,
583 VMENTER_L1D_FLUSH_NEVER,
584 VMENTER_L1D_FLUSH_COND,
585 VMENTER_L1D_FLUSH_ALWAYS,
586 VMENTER_L1D_FLUSH_EPT_DISABLED,
587 VMENTER_L1D_FLUSH_NOT_REQUIRED,
588};
589
590extern enum vmx_l1d_flush_state l1tf_vmx_mitigation;
591
592#endif