| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
| 4 | * Rewrite, cleanup: |
| 5 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _ASM_POWERPC_TCE_H |
| 9 | #define _ASM_POWERPC_TCE_H |
| 10 | #ifdef __KERNEL__ |
| 11 | |
| 12 | #include <asm/iommu.h> |
| 13 | |
| 14 | /* |
| 15 | * Tces come in two formats, one for the virtual bus and a different |
| 16 | * format for PCI. PCI TCEs can have hardware or software maintianed |
| 17 | * coherency. |
| 18 | */ |
| 19 | #define TCE_VB 0 |
| 20 | #define TCE_PCI 1 |
| 21 | |
| 22 | /* TCE page size is 4096 bytes (1 << 12) */ |
| 23 | |
| 24 | #define TCE_SHIFT 12 |
| 25 | #define TCE_PAGE_SIZE (1 << TCE_SHIFT) |
| 26 | |
| 27 | #define TCE_ENTRY_SIZE 8 /* each TCE is 64 bits */ |
| 28 | |
| 29 | #define TCE_RPN_MASK 0xfffffffffful /* 40-bit RPN (4K pages) */ |
| 30 | #define TCE_RPN_SHIFT 12 |
| 31 | #define TCE_VALID 0x800 /* TCE valid */ |
| 32 | #define TCE_ALLIO 0x400 /* TCE valid for all lpars */ |
| 33 | #define TCE_PCI_WRITE 0x2 /* write from PCI allowed */ |
| 34 | #define TCE_PCI_READ 0x1 /* read from PCI allowed */ |
| 35 | #define TCE_VB_WRITE 0x1 /* write from VB allowed */ |
| 36 | |
| 37 | #endif /* __KERNEL__ */ |
| 38 | #endif /* _ASM_POWERPC_TCE_H */ |