| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch> |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _ASM_NIOS2_CPUINFO_H |
| 7 | #define _ASM_NIOS2_CPUINFO_H |
| 8 | |
| 9 | #include <linux/types.h> |
| 10 | |
| 11 | struct cpuinfo { |
| 12 | /* Core CPU configuration */ |
| 13 | char cpu_impl[12]; |
| 14 | u32 cpu_clock_freq; |
| 15 | bool mmu; |
| 16 | bool has_div; |
| 17 | bool has_mul; |
| 18 | bool has_mulx; |
| 19 | bool has_bmx; |
| 20 | bool has_cdx; |
| 21 | |
| 22 | /* CPU caches */ |
| 23 | u32 icache_line_size; |
| 24 | u32 icache_size; |
| 25 | u32 dcache_line_size; |
| 26 | u32 dcache_size; |
| 27 | |
| 28 | /* TLB */ |
| 29 | u32 tlb_pid_num_bits; /* number of bits used for the PID in TLBMISC */ |
| 30 | u32 tlb_num_ways; |
| 31 | u32 tlb_num_ways_log2; |
| 32 | u32 tlb_num_entries; |
| 33 | u32 tlb_num_lines; |
| 34 | u32 tlb_ptr_sz; |
| 35 | |
| 36 | /* Addresses */ |
| 37 | u32 reset_addr; |
| 38 | u32 exception_addr; |
| 39 | u32 fast_tlb_miss_exc_addr; |
| 40 | }; |
| 41 | |
| 42 | extern struct cpuinfo cpuinfo; |
| 43 | |
| 44 | extern void setup_cpuinfo(void); |
| 45 | |
| 46 | #endif /* _ASM_NIOS2_CPUINFO_H */ |