| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __MACH_TEGRA_IRAMMAP_H |
| 7 | #define __MACH_TEGRA_IRAMMAP_H |
| 8 | |
| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 9 | #include <linux/sizes.h> |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 10 | |
| 11 | /* The first 1K of IRAM is permanently reserved for the CPU reset handler */ |
| 12 | #define TEGRA_IRAM_RESET_HANDLER_OFFSET 0 |
| 13 | #define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K |
| 14 | |
| 15 | /* |
| 16 | * This area is used for LPx resume vector, only while LPx power state is |
| 17 | * active. At other times, the AVP may use this area for arbitrary purposes |
| 18 | */ |
| 19 | #define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K) |
| 20 | |
| 21 | #endif |