TrustedFirmware Git Browser
Code Review Sign In
review.trustedfirmware.org / hafnium / third_party / linux.git / 0f672f6c0b52b7b0700b0915c72b540721af4465 / . / arch / arm / mach-omap2 / clockdomains43xx_data.c
blob: 751708d727af97e9deee36eefdb6985ce7c8de1b [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]2/*
3 * AM43xx Clock domains framework
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]6 */
7
8#include <linux/kernel.h>
9#include <linux/io.h>
10
11#include "clockdomain.h"
12#include "prcm44xx.h"
13#include "prcm43xx.h"
14
15static struct clockdomain l4_cefuse_43xx_clkdm = {
16 .name = "l4_cefuse_clkdm",
17 .pwrdm = { .name = "cefuse_pwrdm" },
18 .prcm_partition = AM43XX_CM_PARTITION,
19 .cm_inst = AM43XX_CM_CEFUSE_INST,
20 .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
21 .flags = CLKDM_CAN_SWSUP,
22};
23
24static struct clockdomain mpu_43xx_clkdm = {
25 .name = "mpu_clkdm",
26 .pwrdm = { .name = "mpu_pwrdm" },
27 .prcm_partition = AM43XX_CM_PARTITION,
28 .cm_inst = AM43XX_CM_MPU_INST,
29 .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS,
30 .flags = CLKDM_CAN_HWSUP_SWSUP,
31};
32
33static struct clockdomain l4ls_43xx_clkdm = {
34 .name = "l4ls_clkdm",
35 .pwrdm = { .name = "per_pwrdm" },
36 .prcm_partition = AM43XX_CM_PARTITION,
37 .cm_inst = AM43XX_CM_PER_INST,
38 .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS,
39 .flags = CLKDM_CAN_SWSUP,
40};
41
42static struct clockdomain tamper_43xx_clkdm = {
43 .name = "tamper_clkdm",
44 .pwrdm = { .name = "tamper_pwrdm" },
45 .prcm_partition = AM43XX_CM_PARTITION,
46 .cm_inst = AM43XX_CM_TAMPER_INST,
47 .clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
48 .flags = CLKDM_CAN_SWSUP,
49};
50
51static struct clockdomain l4_rtc_43xx_clkdm = {
52 .name = "l4_rtc_clkdm",
53 .pwrdm = { .name = "rtc_pwrdm" },
54 .prcm_partition = AM43XX_CM_PARTITION,
55 .cm_inst = AM43XX_CM_RTC_INST,
56 .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS,
57 .flags = CLKDM_CAN_SWSUP,
58};
59
60static struct clockdomain pruss_ocp_43xx_clkdm = {
61 .name = "pruss_ocp_clkdm",
62 .pwrdm = { .name = "per_pwrdm" },
63 .prcm_partition = AM43XX_CM_PARTITION,
64 .cm_inst = AM43XX_CM_PER_INST,
65 .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS,
66 .flags = CLKDM_CAN_SWSUP,
67};
68
69static struct clockdomain ocpwp_l3_43xx_clkdm = {
70 .name = "ocpwp_l3_clkdm",
71 .pwrdm = { .name = "per_pwrdm" },
72 .prcm_partition = AM43XX_CM_PARTITION,
73 .cm_inst = AM43XX_CM_PER_INST,
74 .clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
75 .flags = CLKDM_CAN_SWSUP,
76};
77
78static struct clockdomain l3s_tsc_43xx_clkdm = {
79 .name = "l3s_tsc_clkdm",
80 .pwrdm = { .name = "wkup_pwrdm" },
81 .prcm_partition = AM43XX_CM_PARTITION,
82 .cm_inst = AM43XX_CM_WKUP_INST,
83 .clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
84 .flags = CLKDM_CAN_SWSUP,
85};
86
87static struct clockdomain dss_43xx_clkdm = {
88 .name = "dss_clkdm",
89 .pwrdm = { .name = "per_pwrdm" },
90 .prcm_partition = AM43XX_CM_PARTITION,
91 .cm_inst = AM43XX_CM_PER_INST,
92 .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS,
93 .flags = CLKDM_CAN_SWSUP,
94};
95
96static struct clockdomain l3_aon_43xx_clkdm = {
97 .name = "l3_aon_clkdm",
98 .pwrdm = { .name = "wkup_pwrdm" },
99 .prcm_partition = AM43XX_CM_PARTITION,
100 .cm_inst = AM43XX_CM_WKUP_INST,
101 .clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS,
102 .flags = CLKDM_CAN_SWSUP,
103};
104
105static struct clockdomain emif_43xx_clkdm = {
106 .name = "emif_clkdm",
107 .pwrdm = { .name = "per_pwrdm" },
108 .prcm_partition = AM43XX_CM_PARTITION,
109 .cm_inst = AM43XX_CM_PER_INST,
110 .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS,
111 .flags = CLKDM_CAN_SWSUP,
112};
113
114static struct clockdomain l4_wkup_aon_43xx_clkdm = {
115 .name = "l4_wkup_aon_clkdm",
116 .pwrdm = { .name = "wkup_pwrdm" },
117 .prcm_partition = AM43XX_CM_PARTITION,
118 .cm_inst = AM43XX_CM_WKUP_INST,
119 .clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
120};
121
122static struct clockdomain l3_43xx_clkdm = {
123 .name = "l3_clkdm",
124 .pwrdm = { .name = "per_pwrdm" },
125 .prcm_partition = AM43XX_CM_PARTITION,
126 .cm_inst = AM43XX_CM_PER_INST,
127 .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS,
128 .flags = CLKDM_CAN_SWSUP,
129};
130
131static struct clockdomain l4_wkup_43xx_clkdm = {
132 .name = "l4_wkup_clkdm",
133 .pwrdm = { .name = "wkup_pwrdm" },
134 .prcm_partition = AM43XX_CM_PARTITION,
135 .cm_inst = AM43XX_CM_WKUP_INST,
136 .clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS,
137 .flags = CLKDM_CAN_SWSUP,
138};
139
140static struct clockdomain cpsw_125mhz_43xx_clkdm = {
141 .name = "cpsw_125mhz_clkdm",
142 .pwrdm = { .name = "per_pwrdm" },
143 .prcm_partition = AM43XX_CM_PARTITION,
144 .cm_inst = AM43XX_CM_PER_INST,
145 .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS,
146 .flags = CLKDM_CAN_SWSUP,
147};
148
149static struct clockdomain gfx_l3_43xx_clkdm = {
150 .name = "gfx_l3_clkdm",
151 .pwrdm = { .name = "gfx_pwrdm" },
152 .prcm_partition = AM43XX_CM_PARTITION,
153 .cm_inst = AM43XX_CM_GFX_INST,
154 .clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS,
155 .flags = CLKDM_CAN_SWSUP,
156};
157
158static struct clockdomain l3s_43xx_clkdm = {
159 .name = "l3s_clkdm",
160 .pwrdm = { .name = "per_pwrdm" },
161 .prcm_partition = AM43XX_CM_PARTITION,
162 .cm_inst = AM43XX_CM_PER_INST,
163 .clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS,
164 .flags = CLKDM_CAN_SWSUP,
165};
166
167static struct clockdomain *clockdomains_am43xx[] __initdata = {
168 &l4_cefuse_43xx_clkdm,
169 &mpu_43xx_clkdm,
170 &l4ls_43xx_clkdm,
171 &tamper_43xx_clkdm,
172 &l4_rtc_43xx_clkdm,
173 &pruss_ocp_43xx_clkdm,
174 &ocpwp_l3_43xx_clkdm,
175 &l3s_tsc_43xx_clkdm,
176 &dss_43xx_clkdm,
177 &l3_aon_43xx_clkdm,
178 &emif_43xx_clkdm,
179 &l4_wkup_aon_43xx_clkdm,
180 &l3_43xx_clkdm,
181 &l4_wkup_43xx_clkdm,
182 &cpsw_125mhz_43xx_clkdm,
183 &gfx_l3_43xx_clkdm,
184 &l3s_43xx_clkdm,
185 NULL
186};
187
188void __init am43xx_clockdomains_init(void)
189{
190 clkdm_register_platform_funcs(&am43xx_clkdm_operations);
191 clkdm_register_clkdms(clockdomains_am43xx);
192 clkdm_complete_init();
193}