David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University |
| 4 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <linux/compiler.h> |
| 7 | #include <linux/errno.h> |
| 8 | #include <linux/sched.h> |
| 9 | #include <linux/kvm_host.h> |
| 10 | #include <linux/kvm.h> |
| 11 | |
| 12 | #include <asm/unified.h> |
| 13 | #include <asm/ptrace.h> |
| 14 | #include <asm/cputype.h> |
| 15 | #include <asm/kvm_arm.h> |
| 16 | #include <asm/kvm_coproc.h> |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 17 | #include <asm/kvm_emulate.h> |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 18 | |
| 19 | #include <kvm/arm_arch_timer.h> |
| 20 | |
| 21 | /****************************************************************************** |
| 22 | * Cortex-A15 and Cortex-A7 Reset Values |
| 23 | */ |
| 24 | |
| 25 | static struct kvm_regs cortexa_regs_reset = { |
| 26 | .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT, |
| 27 | }; |
| 28 | |
| 29 | |
| 30 | /******************************************************************************* |
| 31 | * Exported reset function |
| 32 | */ |
| 33 | |
| 34 | /** |
| 35 | * kvm_reset_vcpu - sets core registers and cp15 registers to reset value |
| 36 | * @vcpu: The VCPU pointer |
| 37 | * |
| 38 | * This function finds the right table above and sets the registers on the |
| 39 | * virtual CPU struct to their architecturally defined reset values. |
| 40 | */ |
| 41 | int kvm_reset_vcpu(struct kvm_vcpu *vcpu) |
| 42 | { |
| 43 | struct kvm_regs *reset_regs; |
| 44 | |
| 45 | switch (vcpu->arch.target) { |
| 46 | case KVM_ARM_TARGET_CORTEX_A7: |
| 47 | case KVM_ARM_TARGET_CORTEX_A15: |
| 48 | reset_regs = &cortexa_regs_reset; |
| 49 | vcpu->arch.midr = read_cpuid_id(); |
| 50 | break; |
| 51 | default: |
| 52 | return -ENODEV; |
| 53 | } |
| 54 | |
| 55 | /* Reset core registers */ |
| 56 | memcpy(&vcpu->arch.ctxt.gp_regs, reset_regs, sizeof(vcpu->arch.ctxt.gp_regs)); |
| 57 | |
| 58 | /* Reset CP15 registers */ |
| 59 | kvm_reset_coprocs(vcpu); |
| 60 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 61 | /* |
| 62 | * Additional reset state handling that PSCI may have imposed on us. |
| 63 | * Must be done after all the sys_reg reset. |
| 64 | */ |
| 65 | if (READ_ONCE(vcpu->arch.reset_state.reset)) { |
| 66 | unsigned long target_pc = vcpu->arch.reset_state.pc; |
| 67 | |
| 68 | /* Gracefully handle Thumb2 entry point */ |
| 69 | if (target_pc & 1) { |
| 70 | target_pc &= ~1UL; |
| 71 | vcpu_set_thumb(vcpu); |
| 72 | } |
| 73 | |
| 74 | /* Propagate caller endianness */ |
| 75 | if (vcpu->arch.reset_state.be) |
| 76 | kvm_vcpu_set_be(vcpu); |
| 77 | |
| 78 | *vcpu_pc(vcpu) = target_pc; |
| 79 | vcpu_set_reg(vcpu, 0, vcpu->arch.reset_state.r0); |
| 80 | |
| 81 | vcpu->arch.reset_state.reset = false; |
| 82 | } |
| 83 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 84 | /* Reset arch_timer context */ |
| 85 | return kvm_timer_vcpu_reset(vcpu); |
| 86 | } |