Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Marvell 88e6xxx Ethernet switch PHY and PPU support |
| 3 | * |
| 4 | * Copyright (c) 2008 Marvell Semiconductor |
| 5 | * |
| 6 | * Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/mdio.h> |
| 15 | #include <linux/module.h> |
| 16 | |
| 17 | #include "chip.h" |
| 18 | #include "phy.h" |
| 19 | |
| 20 | int mv88e6165_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus, |
| 21 | int addr, int reg, u16 *val) |
| 22 | { |
| 23 | return mv88e6xxx_read(chip, addr, reg, val); |
| 24 | } |
| 25 | |
| 26 | int mv88e6165_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus, |
| 27 | int addr, int reg, u16 val) |
| 28 | { |
| 29 | return mv88e6xxx_write(chip, addr, reg, val); |
| 30 | } |
| 31 | |
| 32 | int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, int reg, u16 *val) |
| 33 | { |
| 34 | int addr = phy; /* PHY devices addresses start at 0x0 */ |
| 35 | struct mii_bus *bus; |
| 36 | |
| 37 | bus = mv88e6xxx_default_mdio_bus(chip); |
| 38 | if (!bus) |
| 39 | return -EOPNOTSUPP; |
| 40 | |
| 41 | if (!chip->info->ops->phy_read) |
| 42 | return -EOPNOTSUPP; |
| 43 | |
| 44 | return chip->info->ops->phy_read(chip, bus, addr, reg, val); |
| 45 | } |
| 46 | |
| 47 | int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, int reg, u16 val) |
| 48 | { |
| 49 | int addr = phy; /* PHY devices addresses start at 0x0 */ |
| 50 | struct mii_bus *bus; |
| 51 | |
| 52 | bus = mv88e6xxx_default_mdio_bus(chip); |
| 53 | if (!bus) |
| 54 | return -EOPNOTSUPP; |
| 55 | |
| 56 | if (!chip->info->ops->phy_write) |
| 57 | return -EOPNOTSUPP; |
| 58 | |
| 59 | return chip->info->ops->phy_write(chip, bus, addr, reg, val); |
| 60 | } |
| 61 | |
| 62 | static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) |
| 63 | { |
| 64 | return mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE, page); |
| 65 | } |
| 66 | |
| 67 | static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) |
| 68 | { |
| 69 | int err; |
| 70 | |
| 71 | /* Restore PHY page Copper 0x0 for access via the registered |
| 72 | * MDIO bus |
| 73 | */ |
| 74 | err = mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE, |
| 75 | MV88E6XXX_PHY_PAGE_COPPER); |
| 76 | if (unlikely(err)) { |
| 77 | dev_err(chip->dev, |
| 78 | "failed to restore PHY %d page Copper (%d)\n", |
| 79 | phy, err); |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, |
| 84 | u8 page, int reg, u16 *val) |
| 85 | { |
| 86 | int err; |
| 87 | |
| 88 | /* There is no paging for registers 22 */ |
| 89 | if (reg == MV88E6XXX_PHY_PAGE) |
| 90 | return -EINVAL; |
| 91 | |
| 92 | err = mv88e6xxx_phy_page_get(chip, phy, page); |
| 93 | if (!err) { |
| 94 | err = mv88e6xxx_phy_read(chip, phy, reg, val); |
| 95 | mv88e6xxx_phy_page_put(chip, phy); |
| 96 | } |
| 97 | |
| 98 | return err; |
| 99 | } |
| 100 | |
| 101 | int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, |
| 102 | u8 page, int reg, u16 val) |
| 103 | { |
| 104 | int err; |
| 105 | |
| 106 | /* There is no paging for registers 22 */ |
| 107 | if (reg == MV88E6XXX_PHY_PAGE) |
| 108 | return -EINVAL; |
| 109 | |
| 110 | err = mv88e6xxx_phy_page_get(chip, phy, page); |
| 111 | if (!err) { |
| 112 | err = mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE, page); |
| 113 | if (!err) |
| 114 | err = mv88e6xxx_phy_write(chip, phy, reg, val); |
| 115 | |
| 116 | mv88e6xxx_phy_page_put(chip, phy); |
| 117 | } |
| 118 | |
| 119 | return err; |
| 120 | } |
| 121 | |
| 122 | static int mv88e6xxx_phy_ppu_disable(struct mv88e6xxx_chip *chip) |
| 123 | { |
| 124 | if (!chip->info->ops->ppu_disable) |
| 125 | return 0; |
| 126 | |
| 127 | return chip->info->ops->ppu_disable(chip); |
| 128 | } |
| 129 | |
| 130 | static int mv88e6xxx_phy_ppu_enable(struct mv88e6xxx_chip *chip) |
| 131 | { |
| 132 | if (!chip->info->ops->ppu_enable) |
| 133 | return 0; |
| 134 | |
| 135 | return chip->info->ops->ppu_enable(chip); |
| 136 | } |
| 137 | |
| 138 | static void mv88e6xxx_phy_ppu_reenable_work(struct work_struct *ugly) |
| 139 | { |
| 140 | struct mv88e6xxx_chip *chip; |
| 141 | |
| 142 | chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); |
| 143 | |
| 144 | mutex_lock(&chip->reg_lock); |
| 145 | |
| 146 | if (mutex_trylock(&chip->ppu_mutex)) { |
| 147 | if (mv88e6xxx_phy_ppu_enable(chip) == 0) |
| 148 | chip->ppu_disabled = 0; |
| 149 | mutex_unlock(&chip->ppu_mutex); |
| 150 | } |
| 151 | |
| 152 | mutex_unlock(&chip->reg_lock); |
| 153 | } |
| 154 | |
| 155 | static void mv88e6xxx_phy_ppu_reenable_timer(struct timer_list *t) |
| 156 | { |
| 157 | struct mv88e6xxx_chip *chip = from_timer(chip, t, ppu_timer); |
| 158 | |
| 159 | schedule_work(&chip->ppu_work); |
| 160 | } |
| 161 | |
| 162 | static int mv88e6xxx_phy_ppu_access_get(struct mv88e6xxx_chip *chip) |
| 163 | { |
| 164 | int ret; |
| 165 | |
| 166 | mutex_lock(&chip->ppu_mutex); |
| 167 | |
| 168 | /* If the PHY polling unit is enabled, disable it so that |
| 169 | * we can access the PHY registers. If it was already |
| 170 | * disabled, cancel the timer that is going to re-enable |
| 171 | * it. |
| 172 | */ |
| 173 | if (!chip->ppu_disabled) { |
| 174 | ret = mv88e6xxx_phy_ppu_disable(chip); |
| 175 | if (ret < 0) { |
| 176 | mutex_unlock(&chip->ppu_mutex); |
| 177 | return ret; |
| 178 | } |
| 179 | chip->ppu_disabled = 1; |
| 180 | } else { |
| 181 | del_timer(&chip->ppu_timer); |
| 182 | ret = 0; |
| 183 | } |
| 184 | |
| 185 | return ret; |
| 186 | } |
| 187 | |
| 188 | static void mv88e6xxx_phy_ppu_access_put(struct mv88e6xxx_chip *chip) |
| 189 | { |
| 190 | /* Schedule a timer to re-enable the PHY polling unit. */ |
| 191 | mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); |
| 192 | mutex_unlock(&chip->ppu_mutex); |
| 193 | } |
| 194 | |
| 195 | static void mv88e6xxx_phy_ppu_state_init(struct mv88e6xxx_chip *chip) |
| 196 | { |
| 197 | mutex_init(&chip->ppu_mutex); |
| 198 | INIT_WORK(&chip->ppu_work, mv88e6xxx_phy_ppu_reenable_work); |
| 199 | timer_setup(&chip->ppu_timer, mv88e6xxx_phy_ppu_reenable_timer, 0); |
| 200 | } |
| 201 | |
| 202 | static void mv88e6xxx_phy_ppu_state_destroy(struct mv88e6xxx_chip *chip) |
| 203 | { |
| 204 | del_timer_sync(&chip->ppu_timer); |
| 205 | } |
| 206 | |
| 207 | int mv88e6185_phy_ppu_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus, |
| 208 | int addr, int reg, u16 *val) |
| 209 | { |
| 210 | int err; |
| 211 | |
| 212 | err = mv88e6xxx_phy_ppu_access_get(chip); |
| 213 | if (!err) { |
| 214 | err = mv88e6xxx_read(chip, addr, reg, val); |
| 215 | mv88e6xxx_phy_ppu_access_put(chip); |
| 216 | } |
| 217 | |
| 218 | return err; |
| 219 | } |
| 220 | |
| 221 | int mv88e6185_phy_ppu_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus, |
| 222 | int addr, int reg, u16 val) |
| 223 | { |
| 224 | int err; |
| 225 | |
| 226 | err = mv88e6xxx_phy_ppu_access_get(chip); |
| 227 | if (!err) { |
| 228 | err = mv88e6xxx_write(chip, addr, reg, val); |
| 229 | mv88e6xxx_phy_ppu_access_put(chip); |
| 230 | } |
| 231 | |
| 232 | return err; |
| 233 | } |
| 234 | |
| 235 | void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) |
| 236 | { |
| 237 | if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable) |
| 238 | mv88e6xxx_phy_ppu_state_init(chip); |
| 239 | } |
| 240 | |
| 241 | void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip) |
| 242 | { |
| 243 | if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable) |
| 244 | mv88e6xxx_phy_ppu_state_destroy(chip); |
| 245 | } |
| 246 | |
| 247 | int mv88e6xxx_phy_setup(struct mv88e6xxx_chip *chip) |
| 248 | { |
| 249 | return mv88e6xxx_phy_ppu_enable(chip); |
| 250 | } |