| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | menuconfig MTD_SPI_NOR |
| 2 | tristate "SPI-NOR device support" |
| 3 | depends on MTD |
| 4 | help |
| 5 | This is the framework for the SPI NOR which can be used by the SPI |
| 6 | device drivers and the SPI-NOR device driver. |
| 7 | |
| 8 | if MTD_SPI_NOR |
| 9 | |
| 10 | config MTD_MT81xx_NOR |
| 11 | tristate "Mediatek MT81xx SPI NOR flash controller" |
| 12 | depends on HAS_IOMEM |
| 13 | help |
| 14 | This enables access to SPI NOR flash, using MT81xx SPI NOR flash |
| 15 | controller. This controller does not support generic SPI BUS, it only |
| 16 | supports SPI NOR Flash. |
| 17 | |
| 18 | config MTD_SPI_NOR_USE_4K_SECTORS |
| 19 | bool "Use small 4096 B erase sectors" |
| 20 | default y |
| 21 | help |
| 22 | Many flash memories support erasing small (4096 B) sectors. Depending |
| 23 | on the usage this feature may provide performance gain in comparison |
| 24 | to erasing whole blocks (32/64 KiB). |
| 25 | Changing a small part of the flash's contents is usually faster with |
| 26 | small sectors. On the other hand erasing should be faster when using |
| 27 | 64 KiB block instead of 16 × 4 KiB sectors. |
| 28 | |
| 29 | Please note that some tools/drivers/filesystems may not work with |
| 30 | 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum). |
| 31 | |
| 32 | config SPI_ASPEED_SMC |
| 33 | tristate "Aspeed flash controllers in SPI mode" |
| 34 | depends on ARCH_ASPEED || COMPILE_TEST |
| 35 | depends on HAS_IOMEM && OF |
| 36 | help |
| 37 | This enables support for the Firmware Memory controller (FMC) |
| 38 | in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips, |
| 39 | and support for the SPI flash memory controller (SPI) for |
| 40 | the host firmware. The implementation only supports SPI NOR. |
| 41 | |
| 42 | config SPI_ATMEL_QUADSPI |
| 43 | tristate "Atmel Quad SPI Controller" |
| 44 | depends on ARCH_AT91 || (ARM && COMPILE_TEST) |
| 45 | depends on OF && HAS_IOMEM |
| 46 | help |
| 47 | This enables support for the Quad SPI controller in master mode. |
| 48 | This driver does not support generic SPI. The implementation only |
| 49 | supports SPI NOR. |
| 50 | |
| 51 | config SPI_CADENCE_QUADSPI |
| 52 | tristate "Cadence Quad SPI controller" |
| 53 | depends on OF && (ARM || ARM64 || COMPILE_TEST) |
| 54 | help |
| 55 | Enable support for the Cadence Quad SPI Flash controller. |
| 56 | |
| 57 | Cadence QSPI is a specialized controller for connecting an SPI |
| 58 | Flash over 1/2/4-bit wide bus. Enable this option if you have a |
| 59 | device with a Cadence QSPI controller and want to access the |
| 60 | Flash as an MTD device. |
| 61 | |
| 62 | config SPI_FSL_QUADSPI |
| 63 | tristate "Freescale Quad SPI controller" |
| 64 | depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST |
| 65 | depends on HAS_IOMEM |
| 66 | help |
| 67 | This enables support for the Quad SPI controller in master mode. |
| 68 | This controller does not support generic SPI. It only supports |
| 69 | SPI NOR. |
| 70 | |
| 71 | config SPI_HISI_SFC |
| 72 | tristate "Hisilicon SPI-NOR Flash Controller(SFC)" |
| 73 | depends on ARCH_HISI || COMPILE_TEST |
| 74 | depends on HAS_IOMEM |
| 75 | help |
| 76 | This enables support for hisilicon SPI-NOR flash controller. |
| 77 | |
| 78 | config SPI_NXP_SPIFI |
| 79 | tristate "NXP SPI Flash Interface (SPIFI)" |
| 80 | depends on OF && (ARCH_LPC18XX || COMPILE_TEST) |
| 81 | depends on HAS_IOMEM |
| 82 | help |
| 83 | Enable support for the NXP LPC SPI Flash Interface controller. |
| 84 | |
| 85 | SPIFI is a specialized controller for connecting serial SPI |
| 86 | Flash. Enable this option if you have a device with a SPIFI |
| 87 | controller and want to access the Flash as a mtd device. |
| 88 | |
| 89 | config SPI_INTEL_SPI |
| 90 | tristate |
| 91 | |
| 92 | config SPI_INTEL_SPI_PCI |
| 93 | tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)" |
| 94 | depends on X86 && PCI |
| 95 | select SPI_INTEL_SPI |
| 96 | help |
| 97 | This enables PCI support for the Intel PCH/PCU SPI controller in |
| 98 | master mode. This controller is present in modern Intel hardware |
| 99 | and is used to hold BIOS and other persistent settings. Using |
| 100 | this driver it is possible to upgrade BIOS directly from Linux. |
| 101 | |
| 102 | Say N here unless you know what you are doing. Overwriting the |
| 103 | SPI flash may render the system unbootable. |
| 104 | |
| 105 | To compile this driver as a module, choose M here: the module |
| 106 | will be called intel-spi-pci. |
| 107 | |
| 108 | config SPI_INTEL_SPI_PLATFORM |
| 109 | tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)" |
| 110 | depends on X86 |
| 111 | select SPI_INTEL_SPI |
| 112 | help |
| 113 | This enables platform support for the Intel PCH/PCU SPI |
| 114 | controller in master mode. This controller is present in modern |
| 115 | Intel hardware and is used to hold BIOS and other persistent |
| 116 | settings. Using this driver it is possible to upgrade BIOS |
| 117 | directly from Linux. |
| 118 | |
| 119 | Say N here unless you know what you are doing. Overwriting the |
| 120 | SPI flash may render the system unbootable. |
| 121 | |
| 122 | To compile this driver as a module, choose M here: the module |
| 123 | will be called intel-spi-platform. |
| 124 | |
| 125 | config SPI_STM32_QUADSPI |
| 126 | tristate "STM32 Quad SPI controller" |
| 127 | depends on ARCH_STM32 || COMPILE_TEST |
| 128 | help |
| 129 | This enables support for the STM32 Quad SPI controller. |
| 130 | We only connect the NOR to this controller. |
| 131 | |
| 132 | endif # MTD_SPI_NOR |