| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * H/W layer of ISHTP provider device (ISH) |
| 3 | * |
| 4 | * Copyright (c) 2014-2016, Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | */ |
| 15 | |
| 16 | #ifndef _ISHTP_HW_ISH_H_ |
| 17 | #define _ISHTP_HW_ISH_H_ |
| 18 | |
| 19 | #include <linux/pci.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include "hw-ish-regs.h" |
| 22 | #include "ishtp-dev.h" |
| 23 | |
| 24 | #define CHV_DEVICE_ID 0x22D8 |
| 25 | #define BXT_Ax_DEVICE_ID 0x0AA2 |
| 26 | #define BXT_Bx_DEVICE_ID 0x1AA2 |
| 27 | #define APL_Ax_DEVICE_ID 0x5AA2 |
| 28 | #define SPT_Ax_DEVICE_ID 0x9D35 |
| 29 | #define CNL_Ax_DEVICE_ID 0x9DFC |
| 30 | #define GLK_Ax_DEVICE_ID 0x31A2 |
| 31 | #define CNL_H_DEVICE_ID 0xA37C |
| 32 | #define ICL_MOBILE_DEVICE_ID 0x34FC |
| 33 | #define SPT_H_DEVICE_ID 0xA135 |
| 34 | |
| 35 | #define REVISION_ID_CHT_A0 0x6 |
| 36 | #define REVISION_ID_CHT_Ax_SI 0x0 |
| 37 | #define REVISION_ID_CHT_Bx_SI 0x10 |
| 38 | #define REVISION_ID_CHT_Kx_SI 0x20 |
| 39 | #define REVISION_ID_CHT_Dx_SI 0x30 |
| 40 | #define REVISION_ID_CHT_B0 0xB0 |
| 41 | #define REVISION_ID_SI_MASK 0x70 |
| 42 | |
| 43 | struct ipc_rst_payload_type { |
| 44 | uint16_t reset_id; |
| 45 | uint16_t reserved; |
| 46 | }; |
| 47 | |
| 48 | struct time_sync_format { |
| 49 | uint8_t ts1_source; |
| 50 | uint8_t ts2_source; |
| 51 | uint16_t reserved; |
| 52 | } __packed; |
| 53 | |
| 54 | struct ipc_time_update_msg { |
| 55 | uint64_t primary_host_time; |
| 56 | struct time_sync_format sync_info; |
| 57 | uint64_t secondary_host_time; |
| 58 | } __packed; |
| 59 | |
| 60 | enum { |
| 61 | HOST_UTC_TIME_USEC = 0, |
| 62 | HOST_SYSTEM_TIME_USEC = 1 |
| 63 | }; |
| 64 | |
| 65 | struct ish_hw { |
| 66 | void __iomem *mem_addr; |
| 67 | }; |
| 68 | |
| 69 | /* |
| 70 | * ISH FW status type |
| 71 | */ |
| 72 | enum { |
| 73 | FWSTS_AFTER_RESET = 0, |
| 74 | FWSTS_WAIT_FOR_HOST = 4, |
| 75 | FWSTS_START_KERNEL_DMA = 5, |
| 76 | FWSTS_FW_IS_RUNNING = 7, |
| 77 | FWSTS_SENSOR_APP_LOADED = 8, |
| 78 | FWSTS_SENSOR_APP_RUNNING = 15 |
| 79 | }; |
| 80 | |
| 81 | #define to_ish_hw(dev) (struct ish_hw *)((dev)->hw) |
| 82 | |
| 83 | irqreturn_t ish_irq_handler(int irq, void *dev_id); |
| 84 | struct ishtp_device *ish_dev_init(struct pci_dev *pdev); |
| 85 | int ish_hw_start(struct ishtp_device *dev); |
| 86 | void ish_device_disable(struct ishtp_device *dev); |
| 87 | |
| 88 | #endif /* _ISHTP_HW_ISH_H_ */ |