| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | menuconfig ARCH_SIRF |
| 2 | bool "CSR SiRF" |
| 3 | depends on ARCH_MULTI_V7 |
| 4 | select ARCH_HAS_RESET_CONTROLLER |
| 5 | select RESET_CONTROLLER |
| 6 | select GENERIC_IRQ_CHIP |
| 7 | select GPIOLIB |
| 8 | select NO_IOPORT_MAP |
| 9 | select REGMAP |
| 10 | select PINCTRL |
| 11 | select PINCTRL_SIRF |
| 12 | help |
| 13 | Support for CSR SiRFprimaII/Marco/Polo platforms |
| 14 | |
| 15 | if ARCH_SIRF |
| 16 | |
| 17 | comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features" |
| 18 | |
| 19 | config ARCH_ATLAS6 |
| 20 | bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" |
| 21 | default y |
| 22 | select SIRF_IRQ |
| 23 | help |
| 24 | Support for CSR SiRFSoC ARM Cortex A9 Platform |
| 25 | |
| 26 | config ARCH_ATLAS7 |
| 27 | bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform" |
| 28 | default y |
| 29 | select ARM_GIC |
| 30 | select ATLAS7_TIMER |
| 31 | select HAVE_ARM_SCU if SMP |
| 32 | select HAVE_SMP |
| 33 | help |
| 34 | Support for CSR SiRFSoC ARM Cortex A7 Platform |
| 35 | |
| 36 | config ARCH_PRIMA2 |
| 37 | bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" |
| 38 | default y |
| 39 | select SIRF_IRQ |
| 40 | select ZONE_DMA |
| 41 | select PRIMA2_TIMER |
| 42 | help |
| 43 | Support for CSR SiRFSoC ARM Cortex A9 Platform |
| 44 | |
| 45 | config SIRF_IRQ |
| 46 | bool |
| 47 | |
| 48 | endif |