| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | */ |
| 4 | |
| 5 | /* |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ASM_ARCH_MXC_COMMON_H__ |
| 12 | #define __ASM_ARCH_MXC_COMMON_H__ |
| 13 | |
| 14 | #include <linux/reboot.h> |
| 15 | |
| 16 | struct irq_data; |
| 17 | struct platform_device; |
| 18 | struct pt_regs; |
| 19 | struct clk; |
| 20 | struct device_node; |
| 21 | enum mxc_cpu_pwr_mode; |
| 22 | struct of_device_id; |
| 23 | |
| 24 | void mx21_map_io(void); |
| 25 | void mx27_map_io(void); |
| 26 | void mx31_map_io(void); |
| 27 | void mx35_map_io(void); |
| 28 | void imx21_init_early(void); |
| 29 | void imx27_init_early(void); |
| 30 | void imx31_init_early(void); |
| 31 | void imx35_init_early(void); |
| 32 | void mxc_init_irq(void __iomem *); |
| 33 | void mx21_init_irq(void); |
| 34 | void mx27_init_irq(void); |
| 35 | void mx31_init_irq(void); |
| 36 | void mx35_init_irq(void); |
| 37 | void imx21_soc_init(void); |
| 38 | void imx27_soc_init(void); |
| 39 | void imx31_soc_init(void); |
| 40 | void imx35_soc_init(void); |
| 41 | int mx21_clocks_init(unsigned long lref, unsigned long fref); |
| 42 | int mx27_clocks_init(unsigned long fref); |
| 43 | int mx31_clocks_init(unsigned long fref); |
| 44 | int mx35_clocks_init(void); |
| 45 | struct platform_device *mxc_register_gpio(char *name, int id, |
| 46 | resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); |
| 47 | void mxc_set_cpu_type(unsigned int type); |
| 48 | void mxc_restart(enum reboot_mode, const char *); |
| 49 | void mxc_arch_reset_init(void __iomem *); |
| 50 | void imx1_reset_init(void __iomem *); |
| 51 | void imx_set_aips(void __iomem *); |
| 52 | void imx_aips_allow_unprivileged_access(const char *compat); |
| 53 | int mxc_device_init(void); |
| 54 | void imx_set_soc_revision(unsigned int rev); |
| 55 | void imx_init_revision_from_anatop(void); |
| 56 | struct device *imx_soc_device_init(void); |
| 57 | void imx6_enable_rbc(bool enable); |
| 58 | void imx_gpc_check_dt(void); |
| 59 | void imx_gpc_set_arm_power_in_lpm(bool power_off); |
| 60 | void imx_gpc_set_l2_mem_power_in_lpm(bool power_off); |
| 61 | void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); |
| 62 | void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); |
| 63 | void imx25_pm_init(void); |
| 64 | void imx27_pm_init(void); |
| 65 | void imx5_pmu_init(void); |
| 66 | |
| 67 | enum mxc_cpu_pwr_mode { |
| 68 | WAIT_CLOCKED, /* wfi only */ |
| 69 | WAIT_UNCLOCKED, /* WAIT */ |
| 70 | WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ |
| 71 | STOP_POWER_ON, /* just STOP */ |
| 72 | STOP_POWER_OFF, /* STOP + SRPG */ |
| 73 | }; |
| 74 | |
| 75 | void imx_enable_cpu(int cpu, bool enable); |
| 76 | void imx_set_cpu_jump(int cpu, void *jump_addr); |
| 77 | u32 imx_get_cpu_arg(int cpu); |
| 78 | void imx_set_cpu_arg(int cpu, u32 arg); |
| 79 | #ifdef CONFIG_SMP |
| 80 | void v7_secondary_startup(void); |
| 81 | void imx_scu_map_io(void); |
| 82 | void imx_smp_prepare(void); |
| 83 | #else |
| 84 | static inline void imx_scu_map_io(void) {} |
| 85 | static inline void imx_smp_prepare(void) {} |
| 86 | #endif |
| 87 | void imx_src_init(void); |
| 88 | void imx_gpc_pre_suspend(bool arm_power_off); |
| 89 | void imx_gpc_post_resume(void); |
| 90 | void imx_gpc_mask_all(void); |
| 91 | void imx_gpc_restore_all(void); |
| 92 | void imx_gpc_hwirq_mask(unsigned int hwirq); |
| 93 | void imx_gpc_hwirq_unmask(unsigned int hwirq); |
| 94 | void imx_anatop_init(void); |
| 95 | void imx_anatop_pre_suspend(void); |
| 96 | void imx_anatop_post_resume(void); |
| 97 | int imx6_set_lpm(enum mxc_cpu_pwr_mode mode); |
| 98 | void imx6_set_int_mem_clk_lpm(bool enable); |
| 99 | void imx6sl_set_wait_clk(bool enter); |
| 100 | int imx_mmdc_get_ddr_type(void); |
| 101 | |
| 102 | void imx_cpu_die(unsigned int cpu); |
| 103 | int imx_cpu_kill(unsigned int cpu); |
| 104 | |
| 105 | #ifdef CONFIG_SUSPEND |
| 106 | void v7_cpu_resume(void); |
| 107 | void imx53_suspend(void __iomem *ocram_vbase); |
| 108 | extern const u32 imx53_suspend_sz; |
| 109 | void imx6_suspend(void __iomem *ocram_vbase); |
| 110 | #else |
| 111 | static inline void v7_cpu_resume(void) {} |
| 112 | static inline void imx53_suspend(void __iomem *ocram_vbase) {} |
| 113 | static const u32 imx53_suspend_sz; |
| 114 | static inline void imx6_suspend(void __iomem *ocram_vbase) {} |
| 115 | #endif |
| 116 | |
| 117 | void imx6_pm_ccm_init(const char *ccm_compat); |
| 118 | void imx6q_pm_init(void); |
| 119 | void imx6dl_pm_init(void); |
| 120 | void imx6sl_pm_init(void); |
| 121 | void imx6sx_pm_init(void); |
| 122 | void imx6ul_pm_init(void); |
| 123 | |
| 124 | #ifdef CONFIG_PM |
| 125 | void imx51_pm_init(void); |
| 126 | void imx53_pm_init(void); |
| 127 | #else |
| 128 | static inline void imx51_pm_init(void) {} |
| 129 | static inline void imx53_pm_init(void) {} |
| 130 | #endif |
| 131 | |
| 132 | #ifdef CONFIG_NEON |
| 133 | int mx51_neon_fixup(void); |
| 134 | #else |
| 135 | static inline int mx51_neon_fixup(void) { return 0; } |
| 136 | #endif |
| 137 | |
| 138 | #ifdef CONFIG_CACHE_L2X0 |
| 139 | void imx_init_l2cache(void); |
| 140 | #else |
| 141 | static inline void imx_init_l2cache(void) {} |
| 142 | #endif |
| 143 | |
| 144 | extern const struct smp_operations imx_smp_ops; |
| 145 | extern const struct smp_operations ls1021a_smp_ops; |
| 146 | |
| 147 | #endif |