| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright(c) 2015 EZchip Technologies. |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <linux/init.h> |
| 7 | #include <linux/io.h> |
| 8 | #include <asm/mach_desc.h> |
| 9 | #include <plat/mtm.h> |
| 10 | |
| 11 | static void __init eznps_configure_msu(void) |
| 12 | { |
| 13 | int cpu; |
| 14 | struct nps_host_reg_msu_en_cfg msu_en_cfg = {.value = 0}; |
| 15 | |
| 16 | msu_en_cfg.msu_en = 1; |
| 17 | msu_en_cfg.ipi_en = 1; |
| 18 | msu_en_cfg.gim_0_en = 1; |
| 19 | msu_en_cfg.gim_1_en = 1; |
| 20 | |
| 21 | /* enable IPI and GIM messages on all clusters */ |
| 22 | for (cpu = 0 ; cpu < eznps_max_cpus; cpu += eznps_cpus_per_cluster) |
| 23 | iowrite32be(msu_en_cfg.value, |
| 24 | nps_host_reg(cpu, NPS_MSU_BLKID, NPS_MSU_EN_CFG)); |
| 25 | } |
| 26 | |
| 27 | static void __init eznps_configure_gim(void) |
| 28 | { |
| 29 | u32 reg_value; |
| 30 | u32 gim_int_lines; |
| 31 | struct nps_host_reg_gim_p_int_dst gim_p_int_dst = {.value = 0}; |
| 32 | |
| 33 | gim_int_lines = NPS_GIM_UART_LINE; |
| 34 | gim_int_lines |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE; |
| 35 | gim_int_lines |= NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE; |
| 36 | gim_int_lines |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE; |
| 37 | gim_int_lines |= NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE; |
| 38 | |
| 39 | /* |
| 40 | * IRQ polarity |
| 41 | * low or high level |
| 42 | * negative or positive edge |
| 43 | */ |
| 44 | reg_value = ioread32be(REG_GIM_P_INT_POL_0); |
| 45 | reg_value &= ~gim_int_lines; |
| 46 | iowrite32be(reg_value, REG_GIM_P_INT_POL_0); |
| 47 | |
| 48 | /* IRQ type level or edge */ |
| 49 | reg_value = ioread32be(REG_GIM_P_INT_SENS_0); |
| 50 | reg_value |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE; |
| 51 | reg_value |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE; |
| 52 | iowrite32be(reg_value, REG_GIM_P_INT_SENS_0); |
| 53 | |
| 54 | /* |
| 55 | * GIM interrupt select type for |
| 56 | * dbg_lan TX and RX interrupts |
| 57 | * should be type 1 |
| 58 | * type 0 = IRQ line 6 |
| 59 | * type 1 = IRQ line 7 |
| 60 | */ |
| 61 | gim_p_int_dst.is = 1; |
| 62 | iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_10); |
| 63 | iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_11); |
| 64 | iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_25); |
| 65 | iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_26); |
| 66 | |
| 67 | /* |
| 68 | * CTOP IRQ lines should be defined |
| 69 | * as blocking in GIM |
| 70 | */ |
| 71 | iowrite32be(gim_int_lines, REG_GIM_P_INT_BLK_0); |
| 72 | |
| 73 | /* enable CTOP IRQ lines in GIM */ |
| 74 | iowrite32be(gim_int_lines, REG_GIM_P_INT_EN_0); |
| 75 | } |
| 76 | |
| 77 | static void __init eznps_early_init(void) |
| 78 | { |
| 79 | eznps_configure_msu(); |
| 80 | eznps_configure_gim(); |
| 81 | } |
| 82 | |
| 83 | static const char *eznps_compat[] __initconst = { |
| 84 | "ezchip,arc-nps", |
| 85 | NULL, |
| 86 | }; |
| 87 | |
| 88 | MACHINE_START(NPS, "nps") |
| 89 | .dt_compat = eznps_compat, |
| 90 | .init_early = eznps_early_init, |
| 91 | MACHINE_END |