v4.19.13 snapshot.
diff --git a/drivers/video/fbdev/geode/Kconfig b/drivers/video/fbdev/geode/Kconfig
new file mode 100644
index 0000000..1e85552
--- /dev/null
+++ b/drivers/video/fbdev/geode/Kconfig
@@ -0,0 +1,54 @@
+#
+# Geode family framebuffer configuration
+#
+config FB_GEODE
+ bool "AMD Geode family framebuffer support"
+ depends on FB && PCI && (X86_32 || (X86 && COMPILE_TEST))
+ ---help---
+ Say 'Y' here to allow you to select framebuffer drivers for
+ the AMD Geode family of processors.
+
+config FB_GEODE_LX
+ tristate "AMD Geode LX framebuffer support"
+ depends on FB && FB_GEODE
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ ---help---
+ Framebuffer driver for the display controller integrated into the
+ AMD Geode LX processors.
+
+ To compile this driver as a module, choose M here: the module will
+ be called lxfb.
+
+ If unsure, say N.
+
+config FB_GEODE_GX
+ tristate "AMD Geode GX framebuffer support"
+ depends on FB && FB_GEODE
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ ---help---
+ Framebuffer driver for the display controller integrated into the
+ AMD Geode GX processors.
+
+ To compile this driver as a module, choose M here: the module will be
+ called gxfb.
+
+ If unsure, say N.
+
+config FB_GEODE_GX1
+ tristate "AMD Geode GX1 framebuffer support"
+ depends on FB && FB_GEODE
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ ---help---
+ Framebuffer driver for the display controller integrated into the
+ AMD Geode GX1 processor.
+
+ To compile this driver as a module, choose M here: the module will be
+ called gx1fb.
+
+ If unsure, say N.
diff --git a/drivers/video/fbdev/geode/Makefile b/drivers/video/fbdev/geode/Makefile
new file mode 100644
index 0000000..16ba8a7
--- /dev/null
+++ b/drivers/video/fbdev/geode/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+# Makefile for the Geode family framebuffer drivers
+
+obj-$(CONFIG_FB_GEODE_GX1) += gx1fb.o
+obj-$(CONFIG_FB_GEODE_GX) += gxfb.o
+obj-$(CONFIG_FB_GEODE_LX) += lxfb.o
+
+gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o
+gxfb-objs := gxfb_core.o display_gx.o video_gx.o suspend_gx.o
+lxfb-objs := lxfb_core.o lxfb_ops.o
diff --git a/drivers/video/fbdev/geode/display_gx.c b/drivers/video/fbdev/geode/display_gx.c
new file mode 100644
index 0000000..f0af911
--- /dev/null
+++ b/drivers/video/fbdev/geode/display_gx.c
@@ -0,0 +1,184 @@
+/*
+ * Geode GX display controller.
+ *
+ * Copyright (C) 2005 Arcom Control Systems Ltd.
+ *
+ * Portions from AMD's original 2.4 driver:
+ * Copyright (C) 2004 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by * the
+ * Free Software Foundation; either version 2 of the License, or * (at your
+ * option) any later version.
+ */
+#include <linux/spinlock.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/div64.h>
+#include <asm/delay.h>
+#include <linux/cs5535.h>
+
+#include "gxfb.h"
+
+unsigned int gx_frame_buffer_size(void)
+{
+ unsigned int val;
+
+ if (!cs5535_has_vsa2()) {
+ uint32_t hi, lo;
+
+ /* The number of pages is (PMAX - PMIN)+1 */
+ rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
+
+ /* PMAX */
+ val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
+ /* PMIN */
+ val -= (lo & 0x000fffff);
+ val += 1;
+
+ /* The page size is 4k */
+ return (val << 12);
+ }
+
+ /* FB size can be obtained from the VSA II */
+ /* Virtual register class = 0x02 */
+ /* VG_MEM_SIZE(512Kb units) = 0x00 */
+
+ outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
+ outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
+
+ val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFFl;
+ return (val << 19);
+}
+
+int gx_line_delta(int xres, int bpp)
+{
+ /* Must be a multiple of 8 bytes. */
+ return (xres * (bpp >> 3) + 7) & ~0x7;
+}
+
+void gx_set_mode(struct fb_info *info)
+{
+ struct gxfb_par *par = info->par;
+ u32 gcfg, dcfg;
+ int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
+ int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
+
+ /* Unlock the display controller registers. */
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
+
+ gcfg = read_dc(par, DC_GENERAL_CFG);
+ dcfg = read_dc(par, DC_DISPLAY_CFG);
+
+ /* Disable the timing generator. */
+ dcfg &= ~DC_DISPLAY_CFG_TGEN;
+ write_dc(par, DC_DISPLAY_CFG, dcfg);
+
+ /* Wait for pending memory requests before disabling the FIFO load. */
+ udelay(100);
+
+ /* Disable FIFO load and compression. */
+ gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
+ DC_GENERAL_CFG_DECE);
+ write_dc(par, DC_GENERAL_CFG, gcfg);
+
+ /* Setup DCLK and its divisor. */
+ gx_set_dclk_frequency(info);
+
+ /*
+ * Setup new mode.
+ */
+
+ /* Clear all unused feature bits. */
+ gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
+ dcfg = 0;
+
+ /* Set FIFO priority (default 6/5) and enable. */
+ /* FIXME: increase fifo priority for 1280x1024 and higher modes? */
+ gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
+ (5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;
+
+ /* Framebuffer start offset. */
+ write_dc(par, DC_FB_ST_OFFSET, 0);
+
+ /* Line delta and line buffer length. */
+ write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
+ write_dc(par, DC_LINE_SIZE,
+ ((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2);
+
+
+ /* Enable graphics and video data and unmask address lines. */
+ dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
+ DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;
+
+ /* Set pixel format. */
+ switch (info->var.bits_per_pixel) {
+ case 8:
+ dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
+ break;
+ case 16:
+ dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
+ break;
+ case 32:
+ dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
+ dcfg |= DC_DISPLAY_CFG_PALB;
+ break;
+ }
+
+ /* Enable timing generator. */
+ dcfg |= DC_DISPLAY_CFG_TGEN;
+
+ /* Horizontal and vertical timings. */
+ hactive = info->var.xres;
+ hblankstart = hactive;
+ hsyncstart = hblankstart + info->var.right_margin;
+ hsyncend = hsyncstart + info->var.hsync_len;
+ hblankend = hsyncend + info->var.left_margin;
+ htotal = hblankend;
+
+ vactive = info->var.yres;
+ vblankstart = vactive;
+ vsyncstart = vblankstart + info->var.lower_margin;
+ vsyncend = vsyncstart + info->var.vsync_len;
+ vblankend = vsyncend + info->var.upper_margin;
+ vtotal = vblankend;
+
+ write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) |
+ ((htotal - 1) << 16));
+ write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) |
+ ((hblankend - 1) << 16));
+ write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1) |
+ ((hsyncend - 1) << 16));
+
+ write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) |
+ ((vtotal - 1) << 16));
+ write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) |
+ ((vblankend - 1) << 16));
+ write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1) |
+ ((vsyncend - 1) << 16));
+
+ /* Write final register values. */
+ write_dc(par, DC_DISPLAY_CFG, dcfg);
+ write_dc(par, DC_GENERAL_CFG, gcfg);
+
+ gx_configure_display(info);
+
+ /* Relock display controller registers */
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
+}
+
+void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
+ unsigned red, unsigned green, unsigned blue)
+{
+ struct gxfb_par *par = info->par;
+ int val;
+
+ /* Hardware palette is in RGB 8-8-8 format. */
+ val = (red << 8) & 0xff0000;
+ val |= (green) & 0x00ff00;
+ val |= (blue >> 8) & 0x0000ff;
+
+ write_dc(par, DC_PAL_ADDRESS, regno);
+ write_dc(par, DC_PAL_DATA, val);
+}
diff --git a/drivers/video/fbdev/geode/display_gx1.c b/drivers/video/fbdev/geode/display_gx1.c
new file mode 100644
index 0000000..b383eb9
--- /dev/null
+++ b/drivers/video/fbdev/geode/display_gx1.c
@@ -0,0 +1,214 @@
+/*
+ * drivers/video/geode/display_gx1.c
+ * -- Geode GX1 display controller
+ *
+ * Copyright (C) 2005 Arcom Control Systems Ltd.
+ *
+ * Based on AMD's original 2.4 driver:
+ * Copyright (C) 2004 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/spinlock.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/div64.h>
+#include <asm/delay.h>
+
+#include "geodefb.h"
+#include "display_gx1.h"
+
+static DEFINE_SPINLOCK(gx1_conf_reg_lock);
+
+static u8 gx1_read_conf_reg(u8 reg)
+{
+ u8 val, ccr3;
+ unsigned long flags;
+
+ spin_lock_irqsave(&gx1_conf_reg_lock, flags);
+
+ outb(CONFIG_CCR3, 0x22);
+ ccr3 = inb(0x23);
+ outb(CONFIG_CCR3, 0x22);
+ outb(ccr3 | CONFIG_CCR3_MAPEN, 0x23);
+ outb(reg, 0x22);
+ val = inb(0x23);
+ outb(CONFIG_CCR3, 0x22);
+ outb(ccr3, 0x23);
+
+ spin_unlock_irqrestore(&gx1_conf_reg_lock, flags);
+
+ return val;
+}
+
+unsigned gx1_gx_base(void)
+{
+ return (gx1_read_conf_reg(CONFIG_GCR) & 0x03) << 30;
+}
+
+int gx1_frame_buffer_size(void)
+{
+ void __iomem *mc_regs;
+ u32 bank_cfg;
+ int d;
+ unsigned dram_size = 0, fb_base;
+
+ mc_regs = ioremap(gx1_gx_base() + 0x8400, 0x100);
+ if (!mc_regs)
+ return -ENOMEM;
+
+
+ /* Calculate the total size of both DIMM0 and DIMM1. */
+ bank_cfg = readl(mc_regs + MC_BANK_CFG);
+
+ for (d = 0; d < 2; d++) {
+ if ((bank_cfg & MC_BCFG_DIMM0_PG_SZ_MASK) != MC_BCFG_DIMM0_PG_SZ_NO_DIMM)
+ dram_size += 0x400000 << ((bank_cfg & MC_BCFG_DIMM0_SZ_MASK) >> 8);
+ bank_cfg >>= 16; /* look at DIMM1 next */
+ }
+
+ fb_base = (readl(mc_regs + MC_GBASE_ADD) & MC_GADD_GBADD_MASK) << 19;
+
+ iounmap(mc_regs);
+
+ return dram_size - fb_base;
+}
+
+static void gx1_set_mode(struct fb_info *info)
+{
+ struct geodefb_par *par = info->par;
+ u32 gcfg, tcfg, ocfg, dclk_div, val;
+ int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
+ int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
+
+ /* Unlock the display controller registers. */
+ readl(par->dc_regs + DC_UNLOCK);
+ writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
+
+ gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
+ tcfg = readl(par->dc_regs + DC_TIMING_CFG);
+
+ /* Blank the display and disable the timing generator. */
+ tcfg &= ~(DC_TCFG_BLKE | DC_TCFG_TGEN);
+ writel(tcfg, par->dc_regs + DC_TIMING_CFG);
+
+ /* Wait for pending memory requests before disabling the FIFO load. */
+ udelay(100);
+
+ /* Disable FIFO load and compression. */
+ gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
+ writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
+
+ /* Setup DCLK and its divisor. */
+ gcfg &= ~DC_GCFG_DCLK_MASK;
+ writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
+
+ par->vid_ops->set_dclk(info);
+
+ dclk_div = DC_GCFG_DCLK_DIV_1; /* FIXME: may need to divide DCLK by 2 sometimes? */
+ gcfg |= dclk_div;
+ writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
+
+ /* Wait for the clock generatation to settle. This is needed since
+ * some of the register writes that follow require that clock to be
+ * present. */
+ udelay(1000); /* FIXME: seems a little long */
+
+ /*
+ * Setup new mode.
+ */
+
+ /* Clear all unused feature bits. */
+ gcfg = DC_GCFG_VRDY | dclk_div;
+
+ /* Set FIFO priority (default 6/5) and enable. */
+ /* FIXME: increase fifo priority for 1280x1024 modes? */
+ gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
+
+ /* FIXME: Set pixel and line double bits if necessary. */
+
+ /* Framebuffer start offset. */
+ writel(0, par->dc_regs + DC_FB_ST_OFFSET);
+
+ /* Line delta and line buffer length. */
+ writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);
+ writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
+ par->dc_regs + DC_BUF_SIZE);
+
+ /* Output configuration. Enable panel data, set pixel format. */
+ ocfg = DC_OCFG_PCKE | DC_OCFG_PDEL | DC_OCFG_PDEH;
+ if (info->var.bits_per_pixel == 8) ocfg |= DC_OCFG_8BPP;
+
+ /* Enable timing generator, sync and FP data. */
+ tcfg = DC_TCFG_FPPE | DC_TCFG_HSYE | DC_TCFG_VSYE | DC_TCFG_BLKE
+ | DC_TCFG_TGEN;
+
+ /* Horizontal and vertical timings. */
+ hactive = info->var.xres;
+ hblankstart = hactive;
+ hsyncstart = hblankstart + info->var.right_margin;
+ hsyncend = hsyncstart + info->var.hsync_len;
+ hblankend = hsyncend + info->var.left_margin;
+ htotal = hblankend;
+
+ vactive = info->var.yres;
+ vblankstart = vactive;
+ vsyncstart = vblankstart + info->var.lower_margin;
+ vsyncend = vsyncstart + info->var.vsync_len;
+ vblankend = vsyncend + info->var.upper_margin;
+ vtotal = vblankend;
+
+ val = (hactive - 1) | ((htotal - 1) << 16);
+ writel(val, par->dc_regs + DC_H_TIMING_1);
+ val = (hblankstart - 1) | ((hblankend - 1) << 16);
+ writel(val, par->dc_regs + DC_H_TIMING_2);
+ val = (hsyncstart - 1) | ((hsyncend - 1) << 16);
+ writel(val, par->dc_regs + DC_H_TIMING_3);
+ writel(val, par->dc_regs + DC_FP_H_TIMING);
+ val = (vactive - 1) | ((vtotal - 1) << 16);
+ writel(val, par->dc_regs + DC_V_TIMING_1);
+ val = (vblankstart - 1) | ((vblankend - 1) << 16);
+ writel(val, par->dc_regs + DC_V_TIMING_2);
+ val = (vsyncstart - 1) | ((vsyncend - 1) << 16);
+ writel(val, par->dc_regs + DC_V_TIMING_3);
+ val = (vsyncstart - 2) | ((vsyncend - 2) << 16);
+ writel(val, par->dc_regs + DC_FP_V_TIMING);
+
+ /* Write final register values. */
+ writel(ocfg, par->dc_regs + DC_OUTPUT_CFG);
+ writel(tcfg, par->dc_regs + DC_TIMING_CFG);
+ udelay(1000); /* delay after TIMING_CFG. FIXME: perhaps a little long */
+ writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
+
+ par->vid_ops->configure_display(info);
+
+ /* Relock display controller registers */
+ writel(0, par->dc_regs + DC_UNLOCK);
+
+ /* FIXME: write line_length and bpp to Graphics Pipeline GP_BLT_STATUS
+ * register. */
+}
+
+static void gx1_set_hw_palette_reg(struct fb_info *info, unsigned regno,
+ unsigned red, unsigned green, unsigned blue)
+{
+ struct geodefb_par *par = info->par;
+ int val;
+
+ /* Hardware palette is in RGB 6-6-6 format. */
+ val = (red << 2) & 0x3f000;
+ val |= (green >> 4) & 0x00fc0;
+ val |= (blue >> 10) & 0x0003f;
+
+ writel(regno, par->dc_regs + DC_PAL_ADDRESS);
+ writel(val, par->dc_regs + DC_PAL_DATA);
+}
+
+const struct geode_dc_ops gx1_dc_ops = {
+ .set_mode = gx1_set_mode,
+ .set_palette_reg = gx1_set_hw_palette_reg,
+};
diff --git a/drivers/video/fbdev/geode/display_gx1.h b/drivers/video/fbdev/geode/display_gx1.h
new file mode 100644
index 0000000..e1cc41b
--- /dev/null
+++ b/drivers/video/fbdev/geode/display_gx1.h
@@ -0,0 +1,154 @@
+/*
+ * drivers/video/geode/display_gx1.h
+ * -- Geode GX1 display controller
+ *
+ * Copyright (C) 2005 Arcom Control Systems Ltd.
+ *
+ * Based on AMD's original 2.4 driver:
+ * Copyright (C) 2004 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DISPLAY_GX1_H__
+#define __DISPLAY_GX1_H__
+
+unsigned gx1_gx_base(void);
+int gx1_frame_buffer_size(void);
+
+extern const struct geode_dc_ops gx1_dc_ops;
+
+/* GX1 configuration I/O registers */
+
+#define CONFIG_CCR3 0xc3
+# define CONFIG_CCR3_MAPEN 0x10
+#define CONFIG_GCR 0xb8
+
+/* Memory controller registers */
+
+#define MC_BANK_CFG 0x08
+# define MC_BCFG_DIMM0_SZ_MASK 0x00000700
+# define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070
+# define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070
+
+#define MC_GBASE_ADD 0x14
+# define MC_GADD_GBADD_MASK 0x000003ff
+
+/* Display controller registers */
+
+#define DC_PAL_ADDRESS 0x70
+#define DC_PAL_DATA 0x74
+
+#define DC_UNLOCK 0x00
+# define DC_UNLOCK_CODE 0x00004758
+
+#define DC_GENERAL_CFG 0x04
+# define DC_GCFG_DFLE 0x00000001
+# define DC_GCFG_CURE 0x00000002
+# define DC_GCFG_VCLK_DIV 0x00000004
+# define DC_GCFG_PLNO 0x00000004
+# define DC_GCFG_PPC 0x00000008
+# define DC_GCFG_CMPE 0x00000010
+# define DC_GCFG_DECE 0x00000020
+# define DC_GCFG_DCLK_MASK 0x000000C0
+# define DC_GCFG_DCLK_DIV_1 0x00000080
+# define DC_GCFG_DFHPSL_MASK 0x00000F00
+# define DC_GCFG_DFHPSL_POS 8
+# define DC_GCFG_DFHPEL_MASK 0x0000F000
+# define DC_GCFG_DFHPEL_POS 12
+# define DC_GCFG_CIM_MASK 0x00030000
+# define DC_GCFG_CIM_POS 16
+# define DC_GCFG_FDTY 0x00040000
+# define DC_GCFG_RTPM 0x00080000
+# define DC_GCFG_DAC_RS_MASK 0x00700000
+# define DC_GCFG_DAC_RS_POS 20
+# define DC_GCFG_CKWR 0x00800000
+# define DC_GCFG_LDBL 0x01000000
+# define DC_GCFG_DIAG 0x02000000
+# define DC_GCFG_CH4S 0x04000000
+# define DC_GCFG_SSLC 0x08000000
+# define DC_GCFG_VIDE 0x10000000
+# define DC_GCFG_VRDY 0x20000000
+# define DC_GCFG_DPCK 0x40000000
+# define DC_GCFG_DDCK 0x80000000
+
+#define DC_TIMING_CFG 0x08
+# define DC_TCFG_FPPE 0x00000001
+# define DC_TCFG_HSYE 0x00000002
+# define DC_TCFG_VSYE 0x00000004
+# define DC_TCFG_BLKE 0x00000008
+# define DC_TCFG_DDCK 0x00000010
+# define DC_TCFG_TGEN 0x00000020
+# define DC_TCFG_VIEN 0x00000040
+# define DC_TCFG_BLNK 0x00000080
+# define DC_TCFG_CHSP 0x00000100
+# define DC_TCFG_CVSP 0x00000200
+# define DC_TCFG_FHSP 0x00000400
+# define DC_TCFG_FVSP 0x00000800
+# define DC_TCFG_FCEN 0x00001000
+# define DC_TCFG_CDCE 0x00002000
+# define DC_TCFG_PLNR 0x00002000
+# define DC_TCFG_INTL 0x00004000
+# define DC_TCFG_PXDB 0x00008000
+# define DC_TCFG_BKRT 0x00010000
+# define DC_TCFG_PSD_MASK 0x000E0000
+# define DC_TCFG_PSD_POS 17
+# define DC_TCFG_DDCI 0x08000000
+# define DC_TCFG_SENS 0x10000000
+# define DC_TCFG_DNA 0x20000000
+# define DC_TCFG_VNA 0x40000000
+# define DC_TCFG_VINT 0x80000000
+
+#define DC_OUTPUT_CFG 0x0C
+# define DC_OCFG_8BPP 0x00000001
+# define DC_OCFG_555 0x00000002
+# define DC_OCFG_PCKE 0x00000004
+# define DC_OCFG_FRME 0x00000008
+# define DC_OCFG_DITE 0x00000010
+# define DC_OCFG_2PXE 0x00000020
+# define DC_OCFG_2XCK 0x00000040
+# define DC_OCFG_2IND 0x00000080
+# define DC_OCFG_34ADD 0x00000100
+# define DC_OCFG_FRMS 0x00000200
+# define DC_OCFG_CKSL 0x00000400
+# define DC_OCFG_PRMP 0x00000800
+# define DC_OCFG_PDEL 0x00001000
+# define DC_OCFG_PDEH 0x00002000
+# define DC_OCFG_CFRW 0x00004000
+# define DC_OCFG_DIAG 0x00008000
+
+#define DC_FB_ST_OFFSET 0x10
+#define DC_CB_ST_OFFSET 0x14
+#define DC_CURS_ST_OFFSET 0x18
+#define DC_ICON_ST_OFFSET 0x1C
+#define DC_VID_ST_OFFSET 0x20
+#define DC_LINE_DELTA 0x24
+#define DC_BUF_SIZE 0x28
+
+#define DC_H_TIMING_1 0x30
+#define DC_H_TIMING_2 0x34
+#define DC_H_TIMING_3 0x38
+#define DC_FP_H_TIMING 0x3C
+
+#define DC_V_TIMING_1 0x40
+#define DC_V_TIMING_2 0x44
+#define DC_V_TIMING_3 0x48
+#define DC_FP_V_TIMING 0x4C
+
+#define DC_CURSOR_X 0x50
+#define DC_ICON_X 0x54
+#define DC_V_LINE_CNT 0x54
+#define DC_CURSOR_Y 0x58
+#define DC_ICON_Y 0x5C
+#define DC_SS_LINE_CMP 0x5C
+#define DC_CURSOR_COLOR 0x60
+#define DC_ICON_COLOR 0x64
+#define DC_BORDER_COLOR 0x68
+#define DC_PAL_ADDRESS 0x70
+#define DC_PAL_DATA 0x74
+#define DC_DFIFO_DIAG 0x78
+#define DC_CFIFO_DIAG 0x7C
+
+#endif /* !__DISPLAY_GX1_H__ */
diff --git a/drivers/video/fbdev/geode/geodefb.h b/drivers/video/fbdev/geode/geodefb.h
new file mode 100644
index 0000000..e2e0793
--- /dev/null
+++ b/drivers/video/fbdev/geode/geodefb.h
@@ -0,0 +1,38 @@
+/*
+ * drivers/video/geode/geodefb.h
+ * -- Geode framebuffer driver
+ *
+ * Copyright (C) 2005 Arcom Control Systems Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __GEODEFB_H__
+#define __GEODEFB_H__
+
+struct geodefb_info;
+
+struct geode_dc_ops {
+ void (*set_mode)(struct fb_info *);
+ void (*set_palette_reg)(struct fb_info *, unsigned, unsigned, unsigned, unsigned);
+};
+
+struct geode_vid_ops {
+ void (*set_dclk)(struct fb_info *);
+ void (*configure_display)(struct fb_info *);
+ int (*blank_display)(struct fb_info *, int blank_mode);
+};
+
+struct geodefb_par {
+ int enable_crt;
+ int panel_x; /* dimensions of an attached flat panel, non-zero => enable panel */
+ int panel_y;
+ void __iomem *dc_regs;
+ void __iomem *vid_regs;
+ const struct geode_dc_ops *dc_ops;
+ const struct geode_vid_ops *vid_ops;
+};
+
+#endif /* !__GEODEFB_H__ */
diff --git a/drivers/video/fbdev/geode/gx1fb_core.c b/drivers/video/fbdev/geode/gx1fb_core.c
new file mode 100644
index 0000000..9bee874
--- /dev/null
+++ b/drivers/video/fbdev/geode/gx1fb_core.c
@@ -0,0 +1,474 @@
+/*
+ * drivers/video/geode/gx1fb_core.c
+ * -- Geode GX1 framebuffer driver
+ *
+ * Copyright (C) 2005 Arcom Control Systems Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#include "geodefb.h"
+#include "display_gx1.h"
+#include "video_cs5530.h"
+
+static char mode_option[32] = "640x480-16@60";
+static int crt_option = 1;
+static char panel_option[32] = "";
+
+/* Modes relevant to the GX1 (taken from modedb.c) */
+static const struct fb_videomode gx1_modedb[] = {
+ /* 640x480-60 VESA */
+ { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 640x480-75 VESA */
+ { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 640x480-85 VESA */
+ { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 800x600-60 VESA */
+ { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 800x600-75 VESA */
+ { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 800x600-85 VESA */
+ { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1024x768-60 VESA */
+ { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1024x768-75 VESA */
+ { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1024x768-85 VESA */
+ { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1280x960-60 VESA */
+ { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1280x960-85 VESA */
+ { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1280x1024-60 VESA */
+ { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1280x1024-75 VESA */
+ { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1280x1024-85 VESA */
+ { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+};
+
+static int gx1_line_delta(int xres, int bpp)
+{
+ int line_delta = xres * (bpp >> 3);
+
+ if (line_delta > 2048)
+ line_delta = 4096;
+ else if (line_delta > 1024)
+ line_delta = 2048;
+ else
+ line_delta = 1024;
+ return line_delta;
+}
+
+static int gx1fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ struct geodefb_par *par = info->par;
+
+ /* Maximum resolution is 1280x1024. */
+ if (var->xres > 1280 || var->yres > 1024)
+ return -EINVAL;
+
+ if (par->panel_x && (var->xres > par->panel_x || var->yres > par->panel_y))
+ return -EINVAL;
+
+ /* Only 16 bpp and 8 bpp is supported by the hardware. */
+ if (var->bits_per_pixel == 16) {
+ var->red.offset = 11; var->red.length = 5;
+ var->green.offset = 5; var->green.length = 6;
+ var->blue.offset = 0; var->blue.length = 5;
+ var->transp.offset = 0; var->transp.length = 0;
+ } else if (var->bits_per_pixel == 8) {
+ var->red.offset = 0; var->red.length = 8;
+ var->green.offset = 0; var->green.length = 8;
+ var->blue.offset = 0; var->blue.length = 8;
+ var->transp.offset = 0; var->transp.length = 0;
+ } else
+ return -EINVAL;
+
+ /* Enough video memory? */
+ if (gx1_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
+ return -EINVAL;
+
+ /* FIXME: Check timing parameters here? */
+
+ return 0;
+}
+
+static int gx1fb_set_par(struct fb_info *info)
+{
+ struct geodefb_par *par = info->par;
+
+ if (info->var.bits_per_pixel == 16)
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ else
+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+
+ info->fix.line_length = gx1_line_delta(info->var.xres, info->var.bits_per_pixel);
+
+ par->dc_ops->set_mode(info);
+
+ return 0;
+}
+
+static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+ chan &= 0xffff;
+ chan >>= 16 - bf->length;
+ return chan << bf->offset;
+}
+
+static int gx1fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info)
+{
+ struct geodefb_par *par = info->par;
+
+ if (info->var.grayscale) {
+ /* grayscale = 0.30*R + 0.59*G + 0.11*B */
+ red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+ }
+
+ /* Truecolor has hardware independent palette */
+ if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+ u32 *pal = info->pseudo_palette;
+ u32 v;
+
+ if (regno >= 16)
+ return -EINVAL;
+
+ v = chan_to_field(red, &info->var.red);
+ v |= chan_to_field(green, &info->var.green);
+ v |= chan_to_field(blue, &info->var.blue);
+
+ pal[regno] = v;
+ } else {
+ if (regno >= 256)
+ return -EINVAL;
+
+ par->dc_ops->set_palette_reg(info, regno, red, green, blue);
+ }
+
+ return 0;
+}
+
+static int gx1fb_blank(int blank_mode, struct fb_info *info)
+{
+ struct geodefb_par *par = info->par;
+
+ return par->vid_ops->blank_display(info, blank_mode);
+}
+
+static int gx1fb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
+{
+ struct geodefb_par *par = info->par;
+ unsigned gx_base;
+ int fb_len;
+ int ret;
+
+ gx_base = gx1_gx_base();
+ if (!gx_base)
+ return -ENODEV;
+
+ ret = pci_enable_device(dev);
+ if (ret < 0)
+ return ret;
+
+ ret = pci_request_region(dev, 0, "gx1fb (video)");
+ if (ret < 0)
+ return ret;
+ par->vid_regs = pci_ioremap_bar(dev, 0);
+ if (!par->vid_regs)
+ return -ENOMEM;
+
+ if (!request_mem_region(gx_base + 0x8300, 0x100, "gx1fb (display controller)"))
+ return -EBUSY;
+ par->dc_regs = ioremap(gx_base + 0x8300, 0x100);
+ if (!par->dc_regs)
+ return -ENOMEM;
+
+ if ((fb_len = gx1_frame_buffer_size()) < 0)
+ return -ENOMEM;
+ info->fix.smem_start = gx_base + 0x800000;
+ info->fix.smem_len = fb_len;
+ info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
+ if (!info->screen_base)
+ return -ENOMEM;
+
+ dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
+ info->fix.smem_len / 1024, info->fix.smem_start);
+
+ return 0;
+}
+
+static int parse_panel_option(struct fb_info *info)
+{
+ struct geodefb_par *par = info->par;
+
+ if (strcmp(panel_option, "") != 0) {
+ int x, y;
+ char *s;
+ x = simple_strtol(panel_option, &s, 10);
+ if (!x)
+ return -EINVAL;
+ y = simple_strtol(s + 1, NULL, 10);
+ if (!y)
+ return -EINVAL;
+ par->panel_x = x;
+ par->panel_y = y;
+ }
+ return 0;
+}
+
+static struct fb_ops gx1fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = gx1fb_check_var,
+ .fb_set_par = gx1fb_set_par,
+ .fb_setcolreg = gx1fb_setcolreg,
+ .fb_blank = gx1fb_blank,
+ /* No HW acceleration for now. */
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+};
+
+static struct fb_info *gx1fb_init_fbinfo(struct device *dev)
+{
+ struct geodefb_par *par;
+ struct fb_info *info;
+
+ /* Alloc enough space for the pseudo palette. */
+ info = framebuffer_alloc(sizeof(struct geodefb_par) + sizeof(u32) * 16, dev);
+ if (!info)
+ return NULL;
+
+ par = info->par;
+
+ strcpy(info->fix.id, "GX1");
+
+ info->fix.type = FB_TYPE_PACKED_PIXELS;
+ info->fix.type_aux = 0;
+ info->fix.xpanstep = 0;
+ info->fix.ypanstep = 0;
+ info->fix.ywrapstep = 0;
+ info->fix.accel = FB_ACCEL_NONE;
+
+ info->var.nonstd = 0;
+ info->var.activate = FB_ACTIVATE_NOW;
+ info->var.height = -1;
+ info->var.width = -1;
+ info->var.accel_flags = 0;
+ info->var.vmode = FB_VMODE_NONINTERLACED;
+
+ info->fbops = &gx1fb_ops;
+ info->flags = FBINFO_DEFAULT;
+ info->node = -1;
+
+ info->pseudo_palette = (void *)par + sizeof(struct geodefb_par);
+
+ info->var.grayscale = 0;
+
+ /* CRT and panel options */
+ par->enable_crt = crt_option;
+ if (parse_panel_option(info) < 0)
+ printk(KERN_WARNING "gx1fb: invalid 'panel' option -- disabling flat panel\n");
+ if (!par->panel_x)
+ par->enable_crt = 1; /* fall back to CRT if no panel is specified */
+
+ if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
+ framebuffer_release(info);
+ return NULL;
+ }
+ return info;
+}
+
+static int gx1fb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct geodefb_par *par;
+ struct fb_info *info;
+ int ret;
+
+ info = gx1fb_init_fbinfo(&pdev->dev);
+ if (!info)
+ return -ENOMEM;
+ par = info->par;
+
+ /* GX1 display controller and CS5530 video device */
+ par->dc_ops = &gx1_dc_ops;
+ par->vid_ops = &cs5530_vid_ops;
+
+ if ((ret = gx1fb_map_video_memory(info, pdev)) < 0) {
+ dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
+ goto err;
+ }
+
+ ret = fb_find_mode(&info->var, info, mode_option,
+ gx1_modedb, ARRAY_SIZE(gx1_modedb), NULL, 16);
+ if (ret == 0 || ret == 4) {
+ dev_err(&pdev->dev, "could not find valid video mode\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Clear the frame buffer of garbage. */
+ memset_io(info->screen_base, 0, info->fix.smem_len);
+
+ gx1fb_check_var(&info->var, info);
+ gx1fb_set_par(info);
+
+ if (register_framebuffer(info) < 0) {
+ ret = -EINVAL;
+ goto err;
+ }
+ pci_set_drvdata(pdev, info);
+ fb_info(info, "%s frame buffer device\n", info->fix.id);
+ return 0;
+
+ err:
+ if (info->screen_base) {
+ iounmap(info->screen_base);
+ pci_release_region(pdev, 0);
+ }
+ if (par->vid_regs) {
+ iounmap(par->vid_regs);
+ pci_release_region(pdev, 1);
+ }
+ if (par->dc_regs) {
+ iounmap(par->dc_regs);
+ release_mem_region(gx1_gx_base() + 0x8300, 0x100);
+ }
+
+ fb_dealloc_cmap(&info->cmap);
+ framebuffer_release(info);
+
+ return ret;
+}
+
+static void gx1fb_remove(struct pci_dev *pdev)
+{
+ struct fb_info *info = pci_get_drvdata(pdev);
+ struct geodefb_par *par = info->par;
+
+ unregister_framebuffer(info);
+
+ iounmap((void __iomem *)info->screen_base);
+ pci_release_region(pdev, 0);
+
+ iounmap(par->vid_regs);
+ pci_release_region(pdev, 1);
+
+ iounmap(par->dc_regs);
+ release_mem_region(gx1_gx_base() + 0x8300, 0x100);
+
+ fb_dealloc_cmap(&info->cmap);
+
+ framebuffer_release(info);
+}
+
+#ifndef MODULE
+static void __init gx1fb_setup(char *options)
+{
+ char *this_opt;
+
+ if (!options || !*options)
+ return;
+
+ while ((this_opt = strsep(&options, ","))) {
+ if (!*this_opt)
+ continue;
+
+ if (!strncmp(this_opt, "mode:", 5))
+ strlcpy(mode_option, this_opt + 5, sizeof(mode_option));
+ else if (!strncmp(this_opt, "crt:", 4))
+ crt_option = !!simple_strtoul(this_opt + 4, NULL, 0);
+ else if (!strncmp(this_opt, "panel:", 6))
+ strlcpy(panel_option, this_opt + 6, sizeof(panel_option));
+ else
+ strlcpy(mode_option, this_opt, sizeof(mode_option));
+ }
+}
+#endif
+
+static struct pci_device_id gx1fb_id_table[] = {
+ { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_VIDEO,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
+ 0xff0000, 0 },
+ { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, gx1fb_id_table);
+
+static struct pci_driver gx1fb_driver = {
+ .name = "gx1fb",
+ .id_table = gx1fb_id_table,
+ .probe = gx1fb_probe,
+ .remove = gx1fb_remove,
+};
+
+static int __init gx1fb_init(void)
+{
+#ifndef MODULE
+ char *option = NULL;
+
+ if (fb_get_options("gx1fb", &option))
+ return -ENODEV;
+ gx1fb_setup(option);
+#endif
+ return pci_register_driver(&gx1fb_driver);
+}
+
+static void gx1fb_cleanup(void)
+{
+ pci_unregister_driver(&gx1fb_driver);
+}
+
+module_init(gx1fb_init);
+module_exit(gx1fb_cleanup);
+
+module_param_string(mode, mode_option, sizeof(mode_option), 0444);
+MODULE_PARM_DESC(mode, "video mode (<x>x<y>[-<bpp>][@<refr>])");
+
+module_param_named(crt, crt_option, int, 0444);
+MODULE_PARM_DESC(crt, "enable CRT output. 0 = off, 1 = on (default)");
+
+module_param_string(panel, panel_option, sizeof(panel_option), 0444);
+MODULE_PARM_DESC(panel, "size of attached flat panel (<x>x<y>)");
+
+MODULE_DESCRIPTION("framebuffer driver for the AMD Geode GX1");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/geode/gxfb.h b/drivers/video/fbdev/geode/gxfb.h
new file mode 100644
index 0000000..d19e937
--- /dev/null
+++ b/drivers/video/fbdev/geode/gxfb.h
@@ -0,0 +1,358 @@
+/*
+ * Copyright (C) 2008 Andres Salomon <dilinger@debian.org>
+ *
+ * Geode GX2 header information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef _GXFB_H_
+#define _GXFB_H_
+
+#include <linux/io.h>
+
+#define GP_REG_COUNT (0x50 / 4)
+#define DC_REG_COUNT (0x90 / 4)
+#define VP_REG_COUNT (0x138 / 8)
+#define FP_REG_COUNT (0x68 / 8)
+
+#define DC_PAL_COUNT 0x104
+
+struct gxfb_par {
+ int enable_crt;
+ void __iomem *dc_regs;
+ void __iomem *vid_regs;
+ void __iomem *gp_regs;
+#ifdef CONFIG_PM
+ int powered_down;
+
+ /* register state, for power management functionality */
+ struct {
+ uint64_t padsel;
+ uint64_t dotpll;
+ } msr;
+
+ uint32_t gp[GP_REG_COUNT];
+ uint32_t dc[DC_REG_COUNT];
+ uint64_t vp[VP_REG_COUNT];
+ uint64_t fp[FP_REG_COUNT];
+
+ uint32_t pal[DC_PAL_COUNT];
+#endif
+};
+
+unsigned int gx_frame_buffer_size(void);
+int gx_line_delta(int xres, int bpp);
+void gx_set_mode(struct fb_info *info);
+void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
+ unsigned red, unsigned green, unsigned blue);
+
+void gx_set_dclk_frequency(struct fb_info *info);
+void gx_configure_display(struct fb_info *info);
+int gx_blank_display(struct fb_info *info, int blank_mode);
+
+#ifdef CONFIG_PM
+int gx_powerdown(struct fb_info *info);
+int gx_powerup(struct fb_info *info);
+#endif
+
+
+/* Graphics Processor registers (table 6-23 from the data book) */
+enum gp_registers {
+ GP_DST_OFFSET = 0,
+ GP_SRC_OFFSET,
+ GP_STRIDE,
+ GP_WID_HEIGHT,
+
+ GP_SRC_COLOR_FG,
+ GP_SRC_COLOR_BG,
+ GP_PAT_COLOR_0,
+ GP_PAT_COLOR_1,
+
+ GP_PAT_COLOR_2,
+ GP_PAT_COLOR_3,
+ GP_PAT_COLOR_4,
+ GP_PAT_COLOR_5,
+
+ GP_PAT_DATA_0,
+ GP_PAT_DATA_1,
+ GP_RASTER_MODE,
+ GP_VECTOR_MODE,
+
+ GP_BLT_MODE,
+ GP_BLT_STATUS,
+ GP_HST_SRC,
+ GP_BASE_OFFSET, /* 0x4c */
+};
+
+#define GP_BLT_STATUS_BLT_PENDING (1 << 2)
+#define GP_BLT_STATUS_BLT_BUSY (1 << 0)
+
+
+/* Display Controller registers (table 6-38 from the data book) */
+enum dc_registers {
+ DC_UNLOCK = 0,
+ DC_GENERAL_CFG,
+ DC_DISPLAY_CFG,
+ DC_RSVD_0,
+
+ DC_FB_ST_OFFSET,
+ DC_CB_ST_OFFSET,
+ DC_CURS_ST_OFFSET,
+ DC_ICON_ST_OFFSET,
+
+ DC_VID_Y_ST_OFFSET,
+ DC_VID_U_ST_OFFSET,
+ DC_VID_V_ST_OFFSET,
+ DC_RSVD_1,
+
+ DC_LINE_SIZE,
+ DC_GFX_PITCH,
+ DC_VID_YUV_PITCH,
+ DC_RSVD_2,
+
+ DC_H_ACTIVE_TIMING,
+ DC_H_BLANK_TIMING,
+ DC_H_SYNC_TIMING,
+ DC_RSVD_3,
+
+ DC_V_ACTIVE_TIMING,
+ DC_V_BLANK_TIMING,
+ DC_V_SYNC_TIMING,
+ DC_RSVD_4,
+
+ DC_CURSOR_X,
+ DC_CURSOR_Y,
+ DC_ICON_X,
+ DC_LINE_CNT,
+
+ DC_PAL_ADDRESS,
+ DC_PAL_DATA,
+ DC_DFIFO_DIAG,
+ DC_CFIFO_DIAG,
+
+ DC_VID_DS_DELTA,
+ DC_GLIU0_MEM_OFFSET,
+ DC_RSVD_5,
+ DC_DV_ACC, /* 0x8c */
+};
+
+#define DC_UNLOCK_LOCK 0x00000000
+#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
+
+#define DC_GENERAL_CFG_YUVM (1 << 20)
+#define DC_GENERAL_CFG_VDSE (1 << 19)
+#define DC_GENERAL_CFG_DFHPEL_SHIFT 12
+#define DC_GENERAL_CFG_DFHPSL_SHIFT 8
+#define DC_GENERAL_CFG_DECE (1 << 6)
+#define DC_GENERAL_CFG_CMPE (1 << 5)
+#define DC_GENERAL_CFG_VIDE (1 << 3)
+#define DC_GENERAL_CFG_ICNE (1 << 2)
+#define DC_GENERAL_CFG_CURE (1 << 1)
+#define DC_GENERAL_CFG_DFLE (1 << 0)
+
+#define DC_DISPLAY_CFG_A20M (1 << 31)
+#define DC_DISPLAY_CFG_A18M (1 << 30)
+#define DC_DISPLAY_CFG_PALB (1 << 25)
+#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
+#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
+#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
+#define DC_DISPLAY_CFG_VDEN (1 << 4)
+#define DC_DISPLAY_CFG_GDEN (1 << 3)
+#define DC_DISPLAY_CFG_TGEN (1 << 0)
+
+
+/*
+ * Video Processor registers (table 6-54).
+ * There is space for 64 bit values, but we never use more than the
+ * lower 32 bits. The actual register save/restore code only bothers
+ * to restore those 32 bits.
+ */
+enum vp_registers {
+ VP_VCFG = 0,
+ VP_DCFG,
+
+ VP_VX,
+ VP_VY,
+
+ VP_VS,
+ VP_VCK,
+
+ VP_VCM,
+ VP_GAR,
+
+ VP_GDR,
+ VP_RSVD_0,
+
+ VP_MISC,
+ VP_CCS,
+
+ VP_RSVD_1,
+ VP_RSVD_2,
+
+ VP_RSVD_3,
+ VP_VDC,
+
+ VP_VCO,
+ VP_CRC,
+
+ VP_CRC32,
+ VP_VDE,
+
+ VP_CCK,
+ VP_CCM,
+
+ VP_CC1,
+ VP_CC2,
+
+ VP_A1X,
+ VP_A1Y,
+
+ VP_A1C,
+ VP_A1T,
+
+ VP_A2X,
+ VP_A2Y,
+
+ VP_A2C,
+ VP_A2T,
+
+ VP_A3X,
+ VP_A3Y,
+
+ VP_A3C,
+ VP_A3T,
+
+ VP_VRR,
+ VP_AWT,
+
+ VP_VTM, /* 0x130 */
+};
+
+#define VP_VCFG_VID_EN (1 << 0)
+
+#define VP_DCFG_DAC_VREF (1 << 26)
+#define VP_DCFG_GV_GAM (1 << 21)
+#define VP_DCFG_VG_CK (1 << 20)
+#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
+#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
+#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
+#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
+#define VP_DCFG_FP_DATA_EN (1 << 7) /* undocumented */
+#define VP_DCFG_FP_PWR_EN (1 << 6) /* undocumented */
+#define VP_DCFG_DAC_BL_EN (1 << 3)
+#define VP_DCFG_VSYNC_EN (1 << 2)
+#define VP_DCFG_HSYNC_EN (1 << 1)
+#define VP_DCFG_CRT_EN (1 << 0)
+
+#define VP_MISC_GAM_EN (1 << 0)
+#define VP_MISC_DACPWRDN (1 << 10)
+#define VP_MISC_APWRDN (1 << 11)
+
+
+/*
+ * Flat Panel registers (table 6-55).
+ * Also 64 bit registers; see above note about 32-bit handling.
+ */
+
+/* we're actually in the VP register space, starting at address 0x400 */
+#define VP_FP_START 0x400
+
+enum fp_registers {
+ FP_PT1 = 0,
+ FP_PT2,
+
+ FP_PM,
+ FP_DFC,
+
+ FP_BLFSR,
+ FP_RLFSR,
+
+ FP_FMI,
+ FP_FMD,
+
+ FP_RSVD_0,
+ FP_DCA,
+
+ FP_DMD,
+ FP_CRC,
+
+ FP_FBB, /* 0x460 */
+};
+
+#define FP_PT1_VSIZE_SHIFT 16 /* undocumented? */
+#define FP_PT1_VSIZE_MASK 0x7FF0000 /* undocumented? */
+
+#define FP_PT2_HSP (1 << 22)
+#define FP_PT2_VSP (1 << 23)
+
+#define FP_PM_P (1 << 24) /* panel power on */
+#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
+#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
+#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
+#define FP_PM_PANEL_ON (1 << 0) /* r/o */
+
+#define FP_DFC_NFI ((1 << 4) | (1 << 5) | (1 << 6))
+
+
+/* register access functions */
+
+static inline uint32_t read_gp(struct gxfb_par *par, int reg)
+{
+ return readl(par->gp_regs + 4*reg);
+}
+
+static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val)
+{
+ writel(val, par->gp_regs + 4*reg);
+}
+
+static inline uint32_t read_dc(struct gxfb_par *par, int reg)
+{
+ return readl(par->dc_regs + 4*reg);
+}
+
+static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val)
+{
+ writel(val, par->dc_regs + 4*reg);
+}
+
+static inline uint32_t read_vp(struct gxfb_par *par, int reg)
+{
+ return readl(par->vid_regs + 8*reg);
+}
+
+static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val)
+{
+ writel(val, par->vid_regs + 8*reg);
+}
+
+static inline uint32_t read_fp(struct gxfb_par *par, int reg)
+{
+ return readl(par->vid_regs + 8*reg + VP_FP_START);
+}
+
+static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val)
+{
+ writel(val, par->vid_regs + 8*reg + VP_FP_START);
+}
+
+
+/* MSRs are defined in linux/cs5535.h; their bitfields are here */
+
+#define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (1 << 3)
+#define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (1 << 2)
+#define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (1 << 1)
+
+#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
+#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
+#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
+
+#define MSR_GX_MSR_PADSEL_MASK 0x3FFFFFFF /* undocumented? */
+#define MSR_GX_MSR_PADSEL_TFT 0x1FFFFFFF /* undocumented? */
+
+#define MSR_GX_GLD_MSR_CONFIG_FP (1 << 3)
+
+#endif
diff --git a/drivers/video/fbdev/geode/gxfb_core.c b/drivers/video/fbdev/geode/gxfb_core.c
new file mode 100644
index 0000000..f4f7637
--- /dev/null
+++ b/drivers/video/fbdev/geode/gxfb_core.c
@@ -0,0 +1,546 @@
+/*
+ * Geode GX framebuffer driver.
+ *
+ * Copyright (C) 2006 Arcom Control Systems Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ *
+ * This driver assumes that the BIOS has created a virtual PCI device header
+ * for the video device. The PCI header is assumed to contain the following
+ * BARs:
+ *
+ * BAR0 - framebuffer memory
+ * BAR1 - graphics processor registers
+ * BAR2 - display controller registers
+ * BAR3 - video processor and flat panel control registers.
+ *
+ * 16 MiB of framebuffer memory is assumed to be available.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/console.h>
+#include <linux/suspend.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/cs5535.h>
+
+#include "gxfb.h"
+
+static char *mode_option;
+static int vram;
+static int vt_switch;
+
+/* Modes relevant to the GX (taken from modedb.c) */
+static struct fb_videomode gx_modedb[] = {
+ /* 640x480-60 VESA */
+ { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 640x480-75 VESA */
+ { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 640x480-85 VESA */
+ { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 800x600-60 VESA */
+ { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 800x600-75 VESA */
+ { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 800x600-85 VESA */
+ { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1024x768-60 VESA */
+ { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1024x768-75 VESA */
+ { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1024x768-85 VESA */
+ { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1280x960-60 VESA */
+ { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1280x960-85 VESA */
+ { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1280x1024-60 VESA */
+ { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1280x1024-75 VESA */
+ { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1280x1024-85 VESA */
+ { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1600x1200-60 VESA */
+ { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1600x1200-75 VESA */
+ { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1600x1200-85 VESA */
+ { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+};
+
+#ifdef CONFIG_OLPC
+#include <asm/olpc.h>
+
+static struct fb_videomode gx_dcon_modedb[] = {
+ /* The only mode the DCON has is 1200x900 */
+ { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 }
+};
+
+static void get_modedb(struct fb_videomode **modedb, unsigned int *size)
+{
+ if (olpc_has_dcon()) {
+ *modedb = (struct fb_videomode *) gx_dcon_modedb;
+ *size = ARRAY_SIZE(gx_dcon_modedb);
+ } else {
+ *modedb = (struct fb_videomode *) gx_modedb;
+ *size = ARRAY_SIZE(gx_modedb);
+ }
+}
+
+#else
+static void get_modedb(struct fb_videomode **modedb, unsigned int *size)
+{
+ *modedb = (struct fb_videomode *) gx_modedb;
+ *size = ARRAY_SIZE(gx_modedb);
+}
+#endif
+
+static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ if (var->xres > 1600 || var->yres > 1200)
+ return -EINVAL;
+ if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16)
+ return -EINVAL;
+
+ if (var->bits_per_pixel == 32) {
+ var->red.offset = 16; var->red.length = 8;
+ var->green.offset = 8; var->green.length = 8;
+ var->blue.offset = 0; var->blue.length = 8;
+ } else if (var->bits_per_pixel == 16) {
+ var->red.offset = 11; var->red.length = 5;
+ var->green.offset = 5; var->green.length = 6;
+ var->blue.offset = 0; var->blue.length = 5;
+ } else if (var->bits_per_pixel == 8) {
+ var->red.offset = 0; var->red.length = 8;
+ var->green.offset = 0; var->green.length = 8;
+ var->blue.offset = 0; var->blue.length = 8;
+ } else
+ return -EINVAL;
+ var->transp.offset = 0; var->transp.length = 0;
+
+ /* Enough video memory? */
+ if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
+ return -EINVAL;
+
+ /* FIXME: Check timing parameters here? */
+
+ return 0;
+}
+
+static int gxfb_set_par(struct fb_info *info)
+{
+ if (info->var.bits_per_pixel > 8)
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ else
+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+
+ info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);
+
+ gx_set_mode(info);
+
+ return 0;
+}
+
+static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+ chan &= 0xffff;
+ chan >>= 16 - bf->length;
+ return chan << bf->offset;
+}
+
+static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info)
+{
+ if (info->var.grayscale) {
+ /* grayscale = 0.30*R + 0.59*G + 0.11*B */
+ red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+ }
+
+ /* Truecolor has hardware independent palette */
+ if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+ u32 *pal = info->pseudo_palette;
+ u32 v;
+
+ if (regno >= 16)
+ return -EINVAL;
+
+ v = chan_to_field(red, &info->var.red);
+ v |= chan_to_field(green, &info->var.green);
+ v |= chan_to_field(blue, &info->var.blue);
+
+ pal[regno] = v;
+ } else {
+ if (regno >= 256)
+ return -EINVAL;
+
+ gx_set_hw_palette_reg(info, regno, red, green, blue);
+ }
+
+ return 0;
+}
+
+static int gxfb_blank(int blank_mode, struct fb_info *info)
+{
+ return gx_blank_display(info, blank_mode);
+}
+
+static int gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
+{
+ struct gxfb_par *par = info->par;
+ int ret;
+
+ ret = pci_enable_device(dev);
+ if (ret < 0)
+ return ret;
+
+ ret = pci_request_region(dev, 3, "gxfb (video processor)");
+ if (ret < 0)
+ return ret;
+ par->vid_regs = pci_ioremap_bar(dev, 3);
+ if (!par->vid_regs)
+ return -ENOMEM;
+
+ ret = pci_request_region(dev, 2, "gxfb (display controller)");
+ if (ret < 0)
+ return ret;
+ par->dc_regs = pci_ioremap_bar(dev, 2);
+ if (!par->dc_regs)
+ return -ENOMEM;
+
+ ret = pci_request_region(dev, 1, "gxfb (graphics processor)");
+ if (ret < 0)
+ return ret;
+ par->gp_regs = pci_ioremap_bar(dev, 1);
+
+ if (!par->gp_regs)
+ return -ENOMEM;
+
+ ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
+ if (ret < 0)
+ return ret;
+
+ info->fix.smem_start = pci_resource_start(dev, 0);
+ info->fix.smem_len = vram ? vram : gx_frame_buffer_size();
+ info->screen_base = ioremap_wc(info->fix.smem_start,
+ info->fix.smem_len);
+ if (!info->screen_base)
+ return -ENOMEM;
+
+ /* Set the 16MiB aligned base address of the graphics memory region
+ * in the display controller */
+
+ write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
+
+ dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n",
+ info->fix.smem_len / 1024, info->fix.smem_start);
+
+ return 0;
+}
+
+static struct fb_ops gxfb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = gxfb_check_var,
+ .fb_set_par = gxfb_set_par,
+ .fb_setcolreg = gxfb_setcolreg,
+ .fb_blank = gxfb_blank,
+ /* No HW acceleration for now. */
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+};
+
+static struct fb_info *gxfb_init_fbinfo(struct device *dev)
+{
+ struct gxfb_par *par;
+ struct fb_info *info;
+
+ /* Alloc enough space for the pseudo palette. */
+ info = framebuffer_alloc(sizeof(struct gxfb_par) + sizeof(u32) * 16,
+ dev);
+ if (!info)
+ return NULL;
+
+ par = info->par;
+
+ strcpy(info->fix.id, "Geode GX");
+
+ info->fix.type = FB_TYPE_PACKED_PIXELS;
+ info->fix.type_aux = 0;
+ info->fix.xpanstep = 0;
+ info->fix.ypanstep = 0;
+ info->fix.ywrapstep = 0;
+ info->fix.accel = FB_ACCEL_NONE;
+
+ info->var.nonstd = 0;
+ info->var.activate = FB_ACTIVATE_NOW;
+ info->var.height = -1;
+ info->var.width = -1;
+ info->var.accel_flags = 0;
+ info->var.vmode = FB_VMODE_NONINTERLACED;
+
+ info->fbops = &gxfb_ops;
+ info->flags = FBINFO_DEFAULT;
+ info->node = -1;
+
+ info->pseudo_palette = (void *)par + sizeof(struct gxfb_par);
+
+ info->var.grayscale = 0;
+
+ if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
+ framebuffer_release(info);
+ return NULL;
+ }
+
+ return info;
+}
+
+#ifdef CONFIG_PM
+static int gxfb_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct fb_info *info = pci_get_drvdata(pdev);
+
+ if (state.event == PM_EVENT_SUSPEND) {
+ console_lock();
+ gx_powerdown(info);
+ fb_set_suspend(info, 1);
+ console_unlock();
+ }
+
+ /* there's no point in setting PCI states; we emulate PCI, so
+ * we don't end up getting power savings anyways */
+
+ return 0;
+}
+
+static int gxfb_resume(struct pci_dev *pdev)
+{
+ struct fb_info *info = pci_get_drvdata(pdev);
+ int ret;
+
+ console_lock();
+ ret = gx_powerup(info);
+ if (ret) {
+ printk(KERN_ERR "gxfb: power up failed!\n");
+ return ret;
+ }
+
+ fb_set_suspend(info, 0);
+ console_unlock();
+ return 0;
+}
+#endif
+
+static int gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct gxfb_par *par;
+ struct fb_info *info;
+ int ret;
+ unsigned long val;
+
+ struct fb_videomode *modedb_ptr;
+ unsigned int modedb_size;
+
+ info = gxfb_init_fbinfo(&pdev->dev);
+ if (!info)
+ return -ENOMEM;
+ par = info->par;
+
+ if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
+ dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
+ goto err;
+ }
+
+ /* Figure out if this is a TFT or CRT part */
+
+ rdmsrl(MSR_GX_GLD_MSR_CONFIG, val);
+
+ if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP)
+ par->enable_crt = 0;
+ else
+ par->enable_crt = 1;
+
+ get_modedb(&modedb_ptr, &modedb_size);
+ ret = fb_find_mode(&info->var, info, mode_option,
+ modedb_ptr, modedb_size, NULL, 16);
+ if (ret == 0 || ret == 4) {
+ dev_err(&pdev->dev, "could not find valid video mode\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+
+ /* Clear the frame buffer of garbage. */
+ memset_io(info->screen_base, 0, info->fix.smem_len);
+
+ gxfb_check_var(&info->var, info);
+ gxfb_set_par(info);
+
+ pm_set_vt_switch(vt_switch);
+
+ if (register_framebuffer(info) < 0) {
+ ret = -EINVAL;
+ goto err;
+ }
+ pci_set_drvdata(pdev, info);
+ fb_info(info, "%s frame buffer device\n", info->fix.id);
+ return 0;
+
+ err:
+ if (info->screen_base) {
+ iounmap(info->screen_base);
+ pci_release_region(pdev, 0);
+ }
+ if (par->vid_regs) {
+ iounmap(par->vid_regs);
+ pci_release_region(pdev, 3);
+ }
+ if (par->dc_regs) {
+ iounmap(par->dc_regs);
+ pci_release_region(pdev, 2);
+ }
+ if (par->gp_regs) {
+ iounmap(par->gp_regs);
+ pci_release_region(pdev, 1);
+ }
+
+ fb_dealloc_cmap(&info->cmap);
+ framebuffer_release(info);
+ return ret;
+}
+
+static void gxfb_remove(struct pci_dev *pdev)
+{
+ struct fb_info *info = pci_get_drvdata(pdev);
+ struct gxfb_par *par = info->par;
+
+ unregister_framebuffer(info);
+
+ iounmap((void __iomem *)info->screen_base);
+ pci_release_region(pdev, 0);
+
+ iounmap(par->vid_regs);
+ pci_release_region(pdev, 3);
+
+ iounmap(par->dc_regs);
+ pci_release_region(pdev, 2);
+
+ iounmap(par->gp_regs);
+ pci_release_region(pdev, 1);
+
+ fb_dealloc_cmap(&info->cmap);
+
+ framebuffer_release(info);
+}
+
+static const struct pci_device_id gxfb_id_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) },
+ { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, gxfb_id_table);
+
+static struct pci_driver gxfb_driver = {
+ .name = "gxfb",
+ .id_table = gxfb_id_table,
+ .probe = gxfb_probe,
+ .remove = gxfb_remove,
+#ifdef CONFIG_PM
+ .suspend = gxfb_suspend,
+ .resume = gxfb_resume,
+#endif
+};
+
+#ifndef MODULE
+static int __init gxfb_setup(char *options)
+{
+
+ char *opt;
+
+ if (!options || !*options)
+ return 0;
+
+ while ((opt = strsep(&options, ",")) != NULL) {
+ if (!*opt)
+ continue;
+
+ mode_option = opt;
+ }
+
+ return 0;
+}
+#endif
+
+static int __init gxfb_init(void)
+{
+#ifndef MODULE
+ char *option = NULL;
+
+ if (fb_get_options("gxfb", &option))
+ return -ENODEV;
+
+ gxfb_setup(option);
+#endif
+ return pci_register_driver(&gxfb_driver);
+}
+
+static void __exit gxfb_cleanup(void)
+{
+ pci_unregister_driver(&gxfb_driver);
+}
+
+module_init(gxfb_init);
+module_exit(gxfb_cleanup);
+
+module_param(mode_option, charp, 0);
+MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
+
+module_param(vram, int, 0);
+MODULE_PARM_DESC(vram, "video memory size");
+
+module_param(vt_switch, int, 0);
+MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume");
+
+MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/geode/lxfb.h b/drivers/video/fbdev/geode/lxfb.h
new file mode 100644
index 0000000..cfcd809
--- /dev/null
+++ b/drivers/video/fbdev/geode/lxfb.h
@@ -0,0 +1,452 @@
+/* Geode LX framebuffer driver
+ *
+ * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
+ * Copyright (c) 2008 Andres Salomon <dilinger@debian.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _LXFB_H_
+#define _LXFB_H_
+
+#include <linux/fb.h>
+
+#define GP_REG_COUNT (0x7c / 4)
+#define DC_REG_COUNT (0xf0 / 4)
+#define VP_REG_COUNT (0x158 / 8)
+#define FP_REG_COUNT (0x60 / 8)
+
+#define DC_PAL_COUNT 0x104
+#define DC_HFILT_COUNT 0x100
+#define DC_VFILT_COUNT 0x100
+#define VP_COEFF_SIZE 0x1000
+#define VP_PAL_COUNT 0x100
+
+#define OUTPUT_CRT 0x01
+#define OUTPUT_PANEL 0x02
+
+struct lxfb_par {
+ int output;
+
+ void __iomem *gp_regs;
+ void __iomem *dc_regs;
+ void __iomem *vp_regs;
+#ifdef CONFIG_PM
+ int powered_down;
+
+ /* register state, for power mgmt functionality */
+ struct {
+ uint64_t padsel;
+ uint64_t dotpll;
+ uint64_t dfglcfg;
+ uint64_t dcspare;
+ } msr;
+
+ uint32_t gp[GP_REG_COUNT];
+ uint32_t dc[DC_REG_COUNT];
+ uint64_t vp[VP_REG_COUNT];
+ uint64_t fp[FP_REG_COUNT];
+
+ uint32_t dc_pal[DC_PAL_COUNT];
+ uint32_t vp_pal[VP_PAL_COUNT];
+ uint32_t hcoeff[DC_HFILT_COUNT * 2];
+ uint32_t vcoeff[DC_VFILT_COUNT];
+ uint32_t vp_coeff[VP_COEFF_SIZE / 4];
+#endif
+};
+
+static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
+{
+ return (((xres * (bpp >> 3)) + 7) & ~7);
+}
+
+void lx_set_mode(struct fb_info *);
+unsigned int lx_framebuffer_size(void);
+int lx_blank_display(struct fb_info *, int);
+void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
+ unsigned int, unsigned int);
+
+#ifdef CONFIG_PM
+int lx_powerdown(struct fb_info *info);
+int lx_powerup(struct fb_info *info);
+#endif
+
+
+/* Graphics Processor registers (table 6-29 from the data book) */
+enum gp_registers {
+ GP_DST_OFFSET = 0,
+ GP_SRC_OFFSET,
+ GP_STRIDE,
+ GP_WID_HEIGHT,
+
+ GP_SRC_COLOR_FG,
+ GP_SRC_COLOR_BG,
+ GP_PAT_COLOR_0,
+ GP_PAT_COLOR_1,
+
+ GP_PAT_COLOR_2,
+ GP_PAT_COLOR_3,
+ GP_PAT_COLOR_4,
+ GP_PAT_COLOR_5,
+
+ GP_PAT_DATA_0,
+ GP_PAT_DATA_1,
+ GP_RASTER_MODE,
+ GP_VECTOR_MODE,
+
+ GP_BLT_MODE,
+ GP_BLT_STATUS,
+ GP_HST_SRC,
+ GP_BASE_OFFSET,
+
+ GP_CMD_TOP,
+ GP_CMD_BOT,
+ GP_CMD_READ,
+ GP_CMD_WRITE,
+
+ GP_CH3_OFFSET,
+ GP_CH3_MODE_STR,
+ GP_CH3_WIDHI,
+ GP_CH3_HSRC,
+
+ GP_LUT_INDEX,
+ GP_LUT_DATA,
+ GP_INT_CNTRL, /* 0x78 */
+};
+
+#define GP_BLT_STATUS_CE (1 << 4) /* cmd buf empty */
+#define GP_BLT_STATUS_PB (1 << 0) /* primitive busy */
+
+
+/* Display Controller registers (table 6-47 from the data book) */
+enum dc_registers {
+ DC_UNLOCK = 0,
+ DC_GENERAL_CFG,
+ DC_DISPLAY_CFG,
+ DC_ARB_CFG,
+
+ DC_FB_ST_OFFSET,
+ DC_CB_ST_OFFSET,
+ DC_CURS_ST_OFFSET,
+ DC_RSVD_0,
+
+ DC_VID_Y_ST_OFFSET,
+ DC_VID_U_ST_OFFSET,
+ DC_VID_V_ST_OFFSET,
+ DC_DV_TOP,
+
+ DC_LINE_SIZE,
+ DC_GFX_PITCH,
+ DC_VID_YUV_PITCH,
+ DC_RSVD_1,
+
+ DC_H_ACTIVE_TIMING,
+ DC_H_BLANK_TIMING,
+ DC_H_SYNC_TIMING,
+ DC_RSVD_2,
+
+ DC_V_ACTIVE_TIMING,
+ DC_V_BLANK_TIMING,
+ DC_V_SYNC_TIMING,
+ DC_FB_ACTIVE,
+
+ DC_CURSOR_X,
+ DC_CURSOR_Y,
+ DC_RSVD_3,
+ DC_LINE_CNT,
+
+ DC_PAL_ADDRESS,
+ DC_PAL_DATA,
+ DC_DFIFO_DIAG,
+ DC_CFIFO_DIAG,
+
+ DC_VID_DS_DELTA,
+ DC_GLIU0_MEM_OFFSET,
+ DC_DV_CTL,
+ DC_DV_ACCESS,
+
+ DC_GFX_SCALE,
+ DC_IRQ_FILT_CTL,
+ DC_FILT_COEFF1,
+ DC_FILT_COEFF2,
+
+ DC_VBI_EVEN_CTL,
+ DC_VBI_ODD_CTL,
+ DC_VBI_HOR,
+ DC_VBI_LN_ODD,
+
+ DC_VBI_LN_EVEN,
+ DC_VBI_PITCH,
+ DC_CLR_KEY,
+ DC_CLR_KEY_MASK,
+
+ DC_CLR_KEY_X,
+ DC_CLR_KEY_Y,
+ DC_IRQ,
+ DC_RSVD_4,
+
+ DC_RSVD_5,
+ DC_GENLK_CTL,
+ DC_VID_EVEN_Y_ST_OFFSET,
+ DC_VID_EVEN_U_ST_OFFSET,
+
+ DC_VID_EVEN_V_ST_OFFSET,
+ DC_V_ACTIVE_EVEN_TIMING,
+ DC_V_BLANK_EVEN_TIMING,
+ DC_V_SYNC_EVEN_TIMING, /* 0xec */
+};
+
+#define DC_UNLOCK_LOCK 0x00000000
+#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
+
+#define DC_GENERAL_CFG_FDTY (1 << 17)
+#define DC_GENERAL_CFG_DFHPEL_SHIFT (12)
+#define DC_GENERAL_CFG_DFHPSL_SHIFT (8)
+#define DC_GENERAL_CFG_VGAE (1 << 7)
+#define DC_GENERAL_CFG_DECE (1 << 6)
+#define DC_GENERAL_CFG_CMPE (1 << 5)
+#define DC_GENERAL_CFG_VIDE (1 << 3)
+#define DC_GENERAL_CFG_DFLE (1 << 0)
+
+#define DC_DISPLAY_CFG_VISL (1 << 27)
+#define DC_DISPLAY_CFG_PALB (1 << 25)
+#define DC_DISPLAY_CFG_DCEN (1 << 24)
+#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
+#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
+#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
+#define DC_DISPLAY_CFG_TRUP (1 << 6)
+#define DC_DISPLAY_CFG_VDEN (1 << 4)
+#define DC_DISPLAY_CFG_GDEN (1 << 3)
+#define DC_DISPLAY_CFG_TGEN (1 << 0)
+
+#define DC_DV_TOP_DV_TOP_EN (1 << 0)
+
+#define DC_DV_CTL_DV_LINE_SIZE ((1 << 10) | (1 << 11))
+#define DC_DV_CTL_DV_LINE_SIZE_1K (0)
+#define DC_DV_CTL_DV_LINE_SIZE_2K (1 << 10)
+#define DC_DV_CTL_DV_LINE_SIZE_4K (1 << 11)
+#define DC_DV_CTL_DV_LINE_SIZE_8K ((1 << 10) | (1 << 11))
+#define DC_DV_CTL_CLEAR_DV_RAM (1 << 0)
+
+#define DC_IRQ_FILT_CTL_H_FILT_SEL (1 << 10)
+
+#define DC_CLR_KEY_CLR_KEY_EN (1 << 24)
+
+#define DC_IRQ_VIP_VSYNC_IRQ_STATUS (1 << 21) /* undocumented? */
+#define DC_IRQ_STATUS (1 << 20) /* undocumented? */
+#define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK (1 << 1)
+#define DC_IRQ_MASK (1 << 0)
+
+#define DC_GENLK_CTL_FLICK_SEL_MASK (0x0F << 28)
+#define DC_GENLK_CTL_ALPHA_FLICK_EN (1 << 25)
+#define DC_GENLK_CTL_FLICK_EN (1 << 24)
+#define DC_GENLK_CTL_GENLK_EN (1 << 18)
+
+
+/*
+ * Video Processor registers (table 6-71).
+ * There is space for 64 bit values, but we never use more than the
+ * lower 32 bits. The actual register save/restore code only bothers
+ * to restore those 32 bits.
+ */
+enum vp_registers {
+ VP_VCFG = 0,
+ VP_DCFG,
+
+ VP_VX,
+ VP_VY,
+
+ VP_SCL,
+ VP_VCK,
+
+ VP_VCM,
+ VP_PAR,
+
+ VP_PDR,
+ VP_SLR,
+
+ VP_MISC,
+ VP_CCS,
+
+ VP_VYS,
+ VP_VXS,
+
+ VP_RSVD_0,
+ VP_VDC,
+
+ VP_RSVD_1,
+ VP_CRC,
+
+ VP_CRC32,
+ VP_VDE,
+
+ VP_CCK,
+ VP_CCM,
+
+ VP_CC1,
+ VP_CC2,
+
+ VP_A1X,
+ VP_A1Y,
+
+ VP_A1C,
+ VP_A1T,
+
+ VP_A2X,
+ VP_A2Y,
+
+ VP_A2C,
+ VP_A2T,
+
+ VP_A3X,
+ VP_A3Y,
+
+ VP_A3C,
+ VP_A3T,
+
+ VP_VRR,
+ VP_AWT,
+
+ VP_VTM,
+ VP_VYE,
+
+ VP_A1YE,
+ VP_A2YE,
+
+ VP_A3YE, /* 0x150 */
+
+ VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
+};
+
+#define VP_VCFG_VID_EN (1 << 0)
+
+#define VP_DCFG_GV_GAM (1 << 21)
+#define VP_DCFG_PWR_SEQ_DELAY ((1 << 17) | (1 << 18) | (1 << 19))
+#define VP_DCFG_PWR_SEQ_DELAY_DEFAULT (1 << 19) /* undocumented */
+#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
+#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
+#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
+#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
+#define VP_DCFG_DAC_BL_EN (1 << 3)
+#define VP_DCFG_VSYNC_EN (1 << 2)
+#define VP_DCFG_HSYNC_EN (1 << 1)
+#define VP_DCFG_CRT_EN (1 << 0)
+
+#define VP_MISC_APWRDN (1 << 11)
+#define VP_MISC_DACPWRDN (1 << 10)
+#define VP_MISC_BYP_BOTH (1 << 0)
+
+
+/*
+ * Flat Panel registers (table 6-71).
+ * Also 64 bit registers; see above note about 32-bit handling.
+ */
+
+/* we're actually in the VP register space, starting at address 0x400 */
+#define VP_FP_START 0x400
+
+enum fp_registers {
+ FP_PT1 = 0,
+ FP_PT2,
+
+ FP_PM,
+ FP_DFC,
+
+ FP_RSVD_0,
+ FP_RSVD_1,
+
+ FP_RSVD_2,
+ FP_RSVD_3,
+
+ FP_RSVD_4,
+ FP_DCA,
+
+ FP_DMD,
+ FP_CRC, /* 0x458 */
+};
+
+#define FP_PT2_HSP (1 << 22)
+#define FP_PT2_VSP (1 << 23)
+#define FP_PT2_SCRC (1 << 27) /* shfclk free */
+
+#define FP_PM_P (1 << 24) /* panel power ctl */
+#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
+#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
+#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
+#define FP_PM_PANEL_ON (1 << 0) /* r/o */
+
+#define FP_DFC_BC ((1 << 4) | (1 << 5) | (1 << 6))
+
+
+/* register access functions */
+
+static inline uint32_t read_gp(struct lxfb_par *par, int reg)
+{
+ return readl(par->gp_regs + 4*reg);
+}
+
+static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
+{
+ writel(val, par->gp_regs + 4*reg);
+}
+
+static inline uint32_t read_dc(struct lxfb_par *par, int reg)
+{
+ return readl(par->dc_regs + 4*reg);
+}
+
+static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
+{
+ writel(val, par->dc_regs + 4*reg);
+}
+
+static inline uint32_t read_vp(struct lxfb_par *par, int reg)
+{
+ return readl(par->vp_regs + 8*reg);
+}
+
+static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
+{
+ writel(val, par->vp_regs + 8*reg);
+}
+
+static inline uint32_t read_fp(struct lxfb_par *par, int reg)
+{
+ return readl(par->vp_regs + 8*reg + VP_FP_START);
+}
+
+static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
+{
+ writel(val, par->vp_regs + 8*reg + VP_FP_START);
+}
+
+
+/* MSRs are defined in linux/cs5535.h; their bitfields are here */
+
+#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
+#define MSR_GLCP_DOTPLL_HALFPIX (1 << 24)
+#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
+#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
+
+/* note: this is actually the VP's GLD_MSR_CONFIG */
+#define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5))
+#define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3)
+#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0)
+#define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) /* FP *and* CRT */
+
+#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */
+#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */
+
+#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */
+#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */
+#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */
+#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */
+#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */
+#define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6)
+#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */
+#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */
+#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */
+
+#endif
diff --git a/drivers/video/fbdev/geode/lxfb_core.c b/drivers/video/fbdev/geode/lxfb_core.c
new file mode 100644
index 0000000..138da6c
--- /dev/null
+++ b/drivers/video/fbdev/geode/lxfb_core.c
@@ -0,0 +1,681 @@
+/*
+ * Geode LX framebuffer driver.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Built from gxfb (which is Copyright (C) 2006 Arcom Control Systems Ltd.)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/console.h>
+#include <linux/mm.h>
+#include <linux/suspend.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/uaccess.h>
+
+#include "lxfb.h"
+
+static char *mode_option;
+static int noclear, nopanel, nocrt;
+static int vram;
+static int vt_switch;
+
+/* Most of these modes are sorted in ascending order, but
+ * since the first entry in this table is the "default" mode,
+ * we try to make it something sane - 640x480-60 is sane
+ */
+
+static struct fb_videomode geode_modedb[] = {
+ /* 640x480-60 */
+ { NULL, 60, 640, 480, 39682, 48, 8, 25, 2, 88, 2,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 640x400-70 */
+ { NULL, 70, 640, 400, 39770, 40, 8, 28, 5, 96, 2,
+ FB_SYNC_HOR_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 640x480-70 */
+ { NULL, 70, 640, 480, 35014, 88, 24, 15, 2, 64, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 640x480-72 */
+ { NULL, 72, 640, 480, 32102, 120, 16, 20, 1, 40, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 640x480-75 */
+ { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 640x480-85 */
+ { NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 640x480-90 */
+ { NULL, 90, 640, 480, 26392, 96, 32, 22, 1, 64, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 640x480-100 */
+ { NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 640x480-60 */
+ { NULL, 60, 640, 480, 39682, 48, 16, 25, 10, 88, 2,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 800x600-56 */
+ { NULL, 56, 800, 600, 27901, 128, 24, 22, 1, 72, 2,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 800x600-60 */
+ { NULL, 60, 800, 600, 25131, 72, 32, 23, 1, 136, 4,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 800x600-70 */
+ { NULL, 70, 800, 600, 21873, 120, 40, 21, 4, 80, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 800x600-72 */
+ { NULL, 72, 800, 600, 20052, 64, 56, 23, 37, 120, 6,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 800x600-75 */
+ { NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 800x600-85 */
+ { NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 800x600-90 */
+ { NULL, 90, 800, 600, 16648, 128, 40, 28, 1, 88, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 800x600-100 */
+ { NULL, 100, 800, 600, 14667, 136, 48, 27, 1, 88, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 800x600-60 */
+ { NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 1024x768-60 */
+ { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 1024x768-70 */
+ { NULL, 70, 1024, 768, 13346, 144, 24, 29, 3, 136, 6,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 1024x768-72 */
+ { NULL, 72, 1024, 768, 12702, 168, 56, 29, 4, 112, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1024x768-75 */
+ { NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1024x768-85 */
+ { NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1024x768-90 */
+ { NULL, 90, 1024, 768, 9981, 176, 64, 37, 1, 112, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1024x768-100 */
+ { NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1024x768-60 */
+ { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 1152x864-60 */
+ { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1152x864-70 */
+ { NULL, 70, 1152, 864, 10254, 192, 72, 32, 8, 120, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1152x864-72 */
+ { NULL, 72, 1152, 864, 9866, 200, 72, 33, 7, 128, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1152x864-75 */
+ { NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1152x864-85 */
+ { NULL, 85, 1152, 864, 8357, 200, 72, 37, 3, 128, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1152x864-90 */
+ { NULL, 90, 1152, 864, 7719, 208, 80, 42, 9, 128, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1152x864-100 */
+ { NULL, 100, 1152, 864, 6947, 208, 80, 48, 3, 128, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1152x864-60 */
+ { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 1280x1024-60 */
+ { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1280x1024-70 */
+ { NULL, 70, 1280, 1024, 7719, 224, 88, 38, 6, 136, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1280x1024-72 */
+ { NULL, 72, 1280, 1024, 7490, 224, 88, 39, 7, 136, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1280x1024-75 */
+ { NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1280x1024-85 */
+ { NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1280x1024-90 */
+ { NULL, 90, 1280, 1024, 5791, 240, 96, 51, 12, 144, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1280x1024-100 */
+ { NULL, 100, 1280, 1024, 5212, 240, 96, 57, 6, 144, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1280x1024-60 */
+ { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 1600x1200-60 */
+ { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1600x1200-70 */
+ { NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1600x1200-72 */
+ { NULL, 72, 1600, 1200, 5053, 288, 112, 47, 13, 176, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1600x1200-75 */
+ { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1600x1200-85 */
+ { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1600x1200-90 */
+ { NULL, 90, 1600, 1200, 3981, 304, 128, 60, 1, 176, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1600x1200-100 */
+ { NULL, 100, 1600, 1200, 3563, 304, 128, 67, 1, 176, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1600x1200-60 */
+ { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+ /* 1920x1440-60 */
+ { NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1920x1440-70 */
+ { NULL, 70, 1920, 1440, 3593, 360, 152, 55, 8, 208, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1920x1440-72 */
+ { NULL, 72, 1920, 1440, 3472, 360, 152, 68, 4, 208, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1920x1440-75 */
+ { NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+ /* 1920x1440-85 */
+ { NULL, 85, 1920, 1440, 2929, 368, 152, 68, 1, 216, 3,
+ 0, FB_VMODE_NONINTERLACED, 0 },
+};
+
+#ifdef CONFIG_OLPC
+#include <asm/olpc.h>
+
+static struct fb_videomode olpc_dcon_modedb[] = {
+ /* The only mode the DCON has is 1200x900 */
+ { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ FB_VMODE_NONINTERLACED, 0 }
+};
+
+static void get_modedb(struct fb_videomode **modedb, unsigned int *size)
+{
+ if (olpc_has_dcon()) {
+ *modedb = (struct fb_videomode *) olpc_dcon_modedb;
+ *size = ARRAY_SIZE(olpc_dcon_modedb);
+ } else {
+ *modedb = (struct fb_videomode *) geode_modedb;
+ *size = ARRAY_SIZE(geode_modedb);
+ }
+}
+
+#else
+static void get_modedb(struct fb_videomode **modedb, unsigned int *size)
+{
+ *modedb = (struct fb_videomode *) geode_modedb;
+ *size = ARRAY_SIZE(geode_modedb);
+}
+#endif
+
+static int lxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ if (var->xres > 1920 || var->yres > 1440)
+ return -EINVAL;
+
+ if (var->bits_per_pixel == 32) {
+ var->red.offset = 16; var->red.length = 8;
+ var->green.offset = 8; var->green.length = 8;
+ var->blue.offset = 0; var->blue.length = 8;
+ } else if (var->bits_per_pixel == 16) {
+ var->red.offset = 11; var->red.length = 5;
+ var->green.offset = 5; var->green.length = 6;
+ var->blue.offset = 0; var->blue.length = 5;
+ } else if (var->bits_per_pixel == 8) {
+ var->red.offset = 0; var->red.length = 8;
+ var->green.offset = 0; var->green.length = 8;
+ var->blue.offset = 0; var->blue.length = 8;
+ } else
+ return -EINVAL;
+
+ var->transp.offset = 0; var->transp.length = 0;
+
+ /* Enough video memory? */
+ if ((lx_get_pitch(var->xres, var->bits_per_pixel) * var->yres)
+ > info->fix.smem_len)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int lxfb_set_par(struct fb_info *info)
+{
+ if (info->var.bits_per_pixel > 8)
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ else
+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+
+ info->fix.line_length = lx_get_pitch(info->var.xres,
+ info->var.bits_per_pixel);
+
+ lx_set_mode(info);
+ return 0;
+}
+
+static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
+{
+ chan &= 0xffff;
+ chan >>= 16 - bf->length;
+ return chan << bf->offset;
+}
+
+static int lxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp,
+ struct fb_info *info)
+{
+ if (info->var.grayscale) {
+ /* grayscale = 0.30*R + 0.59*G + 0.11*B */
+ red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+ }
+
+ /* Truecolor has hardware independent palette */
+ if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+ u32 *pal = info->pseudo_palette;
+ u32 v;
+
+ if (regno >= 16)
+ return -EINVAL;
+
+ v = chan_to_field(red, &info->var.red);
+ v |= chan_to_field(green, &info->var.green);
+ v |= chan_to_field(blue, &info->var.blue);
+
+ pal[regno] = v;
+ } else {
+ if (regno >= 256)
+ return -EINVAL;
+
+ lx_set_palette_reg(info, regno, red, green, blue);
+ }
+
+ return 0;
+}
+
+static int lxfb_blank(int blank_mode, struct fb_info *info)
+{
+ return lx_blank_display(info, blank_mode);
+}
+
+
+static int lxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
+{
+ struct lxfb_par *par = info->par;
+ int ret;
+
+ ret = pci_enable_device(dev);
+
+ if (ret)
+ return ret;
+
+ ret = pci_request_region(dev, 0, "lxfb-framebuffer");
+
+ if (ret)
+ return ret;
+
+ ret = pci_request_region(dev, 1, "lxfb-gp");
+
+ if (ret)
+ return ret;
+
+ ret = pci_request_region(dev, 2, "lxfb-vg");
+
+ if (ret)
+ return ret;
+
+ ret = pci_request_region(dev, 3, "lxfb-vp");
+
+ if (ret)
+ return ret;
+
+ info->fix.smem_start = pci_resource_start(dev, 0);
+ info->fix.smem_len = vram ? vram : lx_framebuffer_size();
+
+ info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
+
+ ret = -ENOMEM;
+
+ if (info->screen_base == NULL)
+ return ret;
+
+ par->gp_regs = pci_ioremap_bar(dev, 1);
+
+ if (par->gp_regs == NULL)
+ return ret;
+
+ par->dc_regs = pci_ioremap_bar(dev, 2);
+
+ if (par->dc_regs == NULL)
+ return ret;
+
+ par->vp_regs = pci_ioremap_bar(dev, 3);
+
+ if (par->vp_regs == NULL)
+ return ret;
+
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
+ write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
+
+ dev_info(&dev->dev, "%d KB of video memory at 0x%lx\n",
+ info->fix.smem_len / 1024, info->fix.smem_start);
+
+ return 0;
+}
+
+static struct fb_ops lxfb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = lxfb_check_var,
+ .fb_set_par = lxfb_set_par,
+ .fb_setcolreg = lxfb_setcolreg,
+ .fb_blank = lxfb_blank,
+ /* No HW acceleration for now. */
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+};
+
+static struct fb_info *lxfb_init_fbinfo(struct device *dev)
+{
+ struct lxfb_par *par;
+ struct fb_info *info;
+
+ /* Alloc enough space for the pseudo palette. */
+ info = framebuffer_alloc(sizeof(struct lxfb_par) + sizeof(u32) * 16,
+ dev);
+ if (!info)
+ return NULL;
+
+ par = info->par;
+
+ strcpy(info->fix.id, "Geode LX");
+
+ info->fix.type = FB_TYPE_PACKED_PIXELS;
+ info->fix.type_aux = 0;
+ info->fix.xpanstep = 0;
+ info->fix.ypanstep = 0;
+ info->fix.ywrapstep = 0;
+ info->fix.accel = FB_ACCEL_NONE;
+
+ info->var.nonstd = 0;
+ info->var.activate = FB_ACTIVATE_NOW;
+ info->var.height = -1;
+ info->var.width = -1;
+ info->var.accel_flags = 0;
+ info->var.vmode = FB_VMODE_NONINTERLACED;
+
+ info->fbops = &lxfb_ops;
+ info->flags = FBINFO_DEFAULT;
+ info->node = -1;
+
+ info->pseudo_palette = (void *)par + sizeof(struct lxfb_par);
+
+ if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
+ framebuffer_release(info);
+ return NULL;
+ }
+
+ info->var.grayscale = 0;
+
+ return info;
+}
+
+#ifdef CONFIG_PM
+static int lxfb_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct fb_info *info = pci_get_drvdata(pdev);
+
+ if (state.event == PM_EVENT_SUSPEND) {
+ console_lock();
+ lx_powerdown(info);
+ fb_set_suspend(info, 1);
+ console_unlock();
+ }
+
+ /* there's no point in setting PCI states; we emulate PCI, so
+ * we don't end up getting power savings anyways */
+
+ return 0;
+}
+
+static int lxfb_resume(struct pci_dev *pdev)
+{
+ struct fb_info *info = pci_get_drvdata(pdev);
+ int ret;
+
+ console_lock();
+ ret = lx_powerup(info);
+ if (ret) {
+ printk(KERN_ERR "lxfb: power up failed!\n");
+ return ret;
+ }
+
+ fb_set_suspend(info, 0);
+ console_unlock();
+ return 0;
+}
+#else
+#define lxfb_suspend NULL
+#define lxfb_resume NULL
+#endif
+
+static int lxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+ struct lxfb_par *par;
+ struct fb_info *info;
+ int ret;
+
+ struct fb_videomode *modedb_ptr;
+ unsigned int modedb_size;
+
+ info = lxfb_init_fbinfo(&pdev->dev);
+
+ if (info == NULL)
+ return -ENOMEM;
+
+ par = info->par;
+
+ ret = lxfb_map_video_memory(info, pdev);
+
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "failed to map frame buffer or controller registers\n");
+ goto err;
+ }
+
+ /* Set up the desired outputs */
+
+ par->output = 0;
+ par->output |= (nopanel) ? 0 : OUTPUT_PANEL;
+ par->output |= (nocrt) ? 0 : OUTPUT_CRT;
+
+ /* Set up the mode database */
+
+ get_modedb(&modedb_ptr, &modedb_size);
+ ret = fb_find_mode(&info->var, info, mode_option,
+ modedb_ptr, modedb_size, NULL, 16);
+
+ if (ret == 0 || ret == 4) {
+ dev_err(&pdev->dev, "could not find valid video mode\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Clear the screen of garbage, unless noclear was specified,
+ * in which case we assume the user knows what he is doing */
+
+ if (!noclear)
+ memset_io(info->screen_base, 0, info->fix.smem_len);
+
+ /* Set the mode */
+
+ lxfb_check_var(&info->var, info);
+ lxfb_set_par(info);
+
+ pm_set_vt_switch(vt_switch);
+
+ if (register_framebuffer(info) < 0) {
+ ret = -EINVAL;
+ goto err;
+ }
+ pci_set_drvdata(pdev, info);
+ fb_info(info, "%s frame buffer device\n", info->fix.id);
+
+ return 0;
+
+err:
+ if (info->screen_base) {
+ iounmap(info->screen_base);
+ pci_release_region(pdev, 0);
+ }
+ if (par->gp_regs) {
+ iounmap(par->gp_regs);
+ pci_release_region(pdev, 1);
+ }
+ if (par->dc_regs) {
+ iounmap(par->dc_regs);
+ pci_release_region(pdev, 2);
+ }
+ if (par->vp_regs) {
+ iounmap(par->vp_regs);
+ pci_release_region(pdev, 3);
+ }
+
+ fb_dealloc_cmap(&info->cmap);
+ framebuffer_release(info);
+
+ return ret;
+}
+
+static void lxfb_remove(struct pci_dev *pdev)
+{
+ struct fb_info *info = pci_get_drvdata(pdev);
+ struct lxfb_par *par = info->par;
+
+ unregister_framebuffer(info);
+
+ iounmap(info->screen_base);
+ pci_release_region(pdev, 0);
+
+ iounmap(par->gp_regs);
+ pci_release_region(pdev, 1);
+
+ iounmap(par->dc_regs);
+ pci_release_region(pdev, 2);
+
+ iounmap(par->vp_regs);
+ pci_release_region(pdev, 3);
+
+ fb_dealloc_cmap(&info->cmap);
+ framebuffer_release(info);
+}
+
+static struct pci_device_id lxfb_id_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LX_VIDEO) },
+ { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, lxfb_id_table);
+
+static struct pci_driver lxfb_driver = {
+ .name = "lxfb",
+ .id_table = lxfb_id_table,
+ .probe = lxfb_probe,
+ .remove = lxfb_remove,
+ .suspend = lxfb_suspend,
+ .resume = lxfb_resume,
+};
+
+#ifndef MODULE
+static int __init lxfb_setup(char *options)
+{
+ char *opt;
+
+ if (!options || !*options)
+ return 0;
+
+ while ((opt = strsep(&options, ",")) != NULL) {
+ if (!*opt)
+ continue;
+
+ if (!strcmp(opt, "noclear"))
+ noclear = 1;
+ else if (!strcmp(opt, "nopanel"))
+ nopanel = 1;
+ else if (!strcmp(opt, "nocrt"))
+ nocrt = 1;
+ else
+ mode_option = opt;
+ }
+
+ return 0;
+}
+#endif
+
+static int __init lxfb_init(void)
+{
+#ifndef MODULE
+ char *option = NULL;
+
+ if (fb_get_options("lxfb", &option))
+ return -ENODEV;
+
+ lxfb_setup(option);
+#endif
+ return pci_register_driver(&lxfb_driver);
+}
+static void __exit lxfb_cleanup(void)
+{
+ pci_unregister_driver(&lxfb_driver);
+}
+
+module_init(lxfb_init);
+module_exit(lxfb_cleanup);
+
+module_param(mode_option, charp, 0);
+MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
+
+module_param(vram, int, 0);
+MODULE_PARM_DESC(vram, "video memory size");
+
+module_param(vt_switch, int, 0);
+MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume");
+
+MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode LX");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/geode/lxfb_ops.c b/drivers/video/fbdev/geode/lxfb_ops.c
new file mode 100644
index 0000000..79e9abc
--- /dev/null
+++ b/drivers/video/fbdev/geode/lxfb_ops.c
@@ -0,0 +1,845 @@
+/* Geode LX framebuffer driver
+ *
+ * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/fb.h>
+#include <linux/uaccess.h>
+#include <linux/delay.h>
+#include <linux/cs5535.h>
+
+#include "lxfb.h"
+
+/* TODO
+ * Support panel scaling
+ * Add acceleration
+ * Add support for interlacing (TV out)
+ * Support compression
+ */
+
+/* This is the complete list of PLL frequencies that we can set -
+ * we will choose the closest match to the incoming clock.
+ * freq is the frequency of the dotclock * 1000 (for example,
+ * 24823 = 24.983 Mhz).
+ * pllval is the corresponding PLL value
+*/
+
+static const struct {
+ unsigned int pllval;
+ unsigned int freq;
+} pll_table[] = {
+ { 0x000131AC, 6231 },
+ { 0x0001215D, 6294 },
+ { 0x00011087, 6750 },
+ { 0x0001216C, 7081 },
+ { 0x0001218D, 7140 },
+ { 0x000110C9, 7800 },
+ { 0x00013147, 7875 },
+ { 0x000110A7, 8258 },
+ { 0x00012159, 8778 },
+ { 0x00014249, 8875 },
+ { 0x00010057, 9000 },
+ { 0x0001219A, 9472 },
+ { 0x00012158, 9792 },
+ { 0x00010045, 10000 },
+ { 0x00010089, 10791 },
+ { 0x000110E7, 11225 },
+ { 0x00012136, 11430 },
+ { 0x00013207, 12375 },
+ { 0x00012187, 12500 },
+ { 0x00014286, 14063 },
+ { 0x000110E5, 15016 },
+ { 0x00014214, 16250 },
+ { 0x00011105, 17045 },
+ { 0x000131E4, 18563 },
+ { 0x00013183, 18750 },
+ { 0x00014284, 19688 },
+ { 0x00011104, 20400 },
+ { 0x00016363, 23625 },
+ { 0x000031AC, 24923 },
+ { 0x0000215D, 25175 },
+ { 0x00001087, 27000 },
+ { 0x0000216C, 28322 },
+ { 0x0000218D, 28560 },
+ { 0x000010C9, 31200 },
+ { 0x00003147, 31500 },
+ { 0x000010A7, 33032 },
+ { 0x00002159, 35112 },
+ { 0x00004249, 35500 },
+ { 0x00000057, 36000 },
+ { 0x0000219A, 37889 },
+ { 0x00002158, 39168 },
+ { 0x00000045, 40000 },
+ { 0x00000089, 43163 },
+ { 0x000010E7, 44900 },
+ { 0x00002136, 45720 },
+ { 0x00003207, 49500 },
+ { 0x00002187, 50000 },
+ { 0x00004286, 56250 },
+ { 0x000010E5, 60065 },
+ { 0x00004214, 65000 },
+ { 0x00001105, 68179 },
+ { 0x000031E4, 74250 },
+ { 0x00003183, 75000 },
+ { 0x00004284, 78750 },
+ { 0x00001104, 81600 },
+ { 0x00006363, 94500 },
+ { 0x00005303, 97520 },
+ { 0x00002183, 100187 },
+ { 0x00002122, 101420 },
+ { 0x00001081, 108000 },
+ { 0x00006201, 113310 },
+ { 0x00000041, 119650 },
+ { 0x000041A1, 129600 },
+ { 0x00002182, 133500 },
+ { 0x000041B1, 135000 },
+ { 0x00000051, 144000 },
+ { 0x000041E1, 148500 },
+ { 0x000062D1, 157500 },
+ { 0x000031A1, 162000 },
+ { 0x00000061, 169203 },
+ { 0x00004231, 172800 },
+ { 0x00002151, 175500 },
+ { 0x000052E1, 189000 },
+ { 0x00000071, 192000 },
+ { 0x00003201, 198000 },
+ { 0x00004291, 202500 },
+ { 0x00001101, 204750 },
+ { 0x00007481, 218250 },
+ { 0x00004170, 229500 },
+ { 0x00006210, 234000 },
+ { 0x00003140, 251182 },
+ { 0x00006250, 261000 },
+ { 0x000041C0, 278400 },
+ { 0x00005220, 280640 },
+ { 0x00000050, 288000 },
+ { 0x000041E0, 297000 },
+ { 0x00002130, 320207 }
+};
+
+
+static void lx_set_dotpll(u32 pllval)
+{
+ u32 dotpll_lo, dotpll_hi;
+ int i;
+
+ rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+
+ if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
+ return;
+
+ dotpll_hi = pllval;
+ dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX);
+ dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
+
+ wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+
+ /* Wait 100us for the PLL to lock */
+
+ udelay(100);
+
+ /* Now, loop for the lock bit */
+
+ for (i = 0; i < 1000; i++) {
+ rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+ if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
+ break;
+ }
+
+ /* Clear the reset bit */
+
+ dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
+ wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+}
+
+/* Set the clock based on the frequency specified by the current mode */
+
+static void lx_set_clock(struct fb_info *info)
+{
+ unsigned int diff, min, best = 0;
+ unsigned int freq, i;
+
+ freq = (unsigned int) (1000000000 / info->var.pixclock);
+
+ min = abs(pll_table[0].freq - freq);
+
+ for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
+ diff = abs(pll_table[i].freq - freq);
+ if (diff < min) {
+ min = diff;
+ best = i;
+ }
+ }
+
+ lx_set_dotpll(pll_table[best].pllval & 0x00017FFF);
+}
+
+static void lx_graphics_disable(struct fb_info *info)
+{
+ struct lxfb_par *par = info->par;
+ unsigned int val, gcfg;
+
+ /* Note: This assumes that the video is in a quitet state */
+
+ write_vp(par, VP_A1T, 0);
+ write_vp(par, VP_A2T, 0);
+ write_vp(par, VP_A3T, 0);
+
+ /* Turn off the VGA and video enable */
+ val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE |
+ DC_GENERAL_CFG_VIDE);
+
+ write_dc(par, DC_GENERAL_CFG, val);
+
+ val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN;
+ write_vp(par, VP_VCFG, val);
+
+ write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK |
+ DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS);
+
+ val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN;
+ write_dc(par, DC_GENLK_CTL, val);
+
+ val = read_dc(par, DC_CLR_KEY);
+ write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN);
+
+ /* turn off the panel */
+ write_fp(par, FP_PM, read_fp(par, FP_PM) & ~FP_PM_P);
+
+ val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN;
+ write_vp(par, VP_MISC, val);
+
+ /* Turn off the display */
+
+ val = read_vp(par, VP_DCFG);
+ write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
+ VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN));
+
+ gcfg = read_dc(par, DC_GENERAL_CFG);
+ gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE);
+ write_dc(par, DC_GENERAL_CFG, gcfg);
+
+ /* Turn off the TGEN */
+ val = read_dc(par, DC_DISPLAY_CFG);
+ val &= ~DC_DISPLAY_CFG_TGEN;
+ write_dc(par, DC_DISPLAY_CFG, val);
+
+ /* Wait 1000 usecs to ensure that the TGEN is clear */
+ udelay(1000);
+
+ /* Turn off the FIFO loader */
+
+ gcfg &= ~DC_GENERAL_CFG_DFLE;
+ write_dc(par, DC_GENERAL_CFG, gcfg);
+
+ /* Lastly, wait for the GP to go idle */
+
+ do {
+ val = read_gp(par, GP_BLT_STATUS);
+ } while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE));
+}
+
+static void lx_graphics_enable(struct fb_info *info)
+{
+ struct lxfb_par *par = info->par;
+ u32 temp, config;
+
+ /* Set the video request register */
+ write_vp(par, VP_VRR, 0);
+
+ /* Set up the polarities */
+
+ config = read_vp(par, VP_DCFG);
+
+ config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY |
+ VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL);
+
+ config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT
+ | VP_DCFG_GV_GAM);
+
+ if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
+ config |= VP_DCFG_CRT_HSYNC_POL;
+
+ if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
+ config |= VP_DCFG_CRT_VSYNC_POL;
+
+ if (par->output & OUTPUT_PANEL) {
+ u32 msrlo, msrhi;
+
+ write_fp(par, FP_PT1, 0);
+ temp = FP_PT2_SCRC;
+
+ if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
+ temp |= FP_PT2_HSP;
+
+ if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
+ temp |= FP_PT2_VSP;
+
+ write_fp(par, FP_PT2, temp);
+ write_fp(par, FP_DFC, FP_DFC_BC);
+
+ msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW;
+ msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH;
+
+ wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
+ }
+
+ if (par->output & OUTPUT_CRT) {
+ config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
+ VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN;
+ }
+
+ write_vp(par, VP_DCFG, config);
+
+ /* Turn the CRT dacs back on */
+
+ if (par->output & OUTPUT_CRT) {
+ temp = read_vp(par, VP_MISC);
+ temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN);
+ write_vp(par, VP_MISC, temp);
+ }
+
+ /* Turn the panel on (if it isn't already) */
+ if (par->output & OUTPUT_PANEL)
+ write_fp(par, FP_PM, read_fp(par, FP_PM) | FP_PM_P);
+}
+
+unsigned int lx_framebuffer_size(void)
+{
+ unsigned int val;
+
+ if (!cs5535_has_vsa2()) {
+ uint32_t hi, lo;
+
+ /* The number of pages is (PMAX - PMIN)+1 */
+ rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
+
+ /* PMAX */
+ val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
+ /* PMIN */
+ val -= (lo & 0x000fffff);
+ val += 1;
+
+ /* The page size is 4k */
+ return (val << 12);
+ }
+
+ /* The frame buffer size is reported by a VSM in VSA II */
+ /* Virtual Register Class = 0x02 */
+ /* VG_MEM_SIZE (1MB units) = 0x00 */
+
+ outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
+ outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
+
+ val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFE;
+ return (val << 20);
+}
+
+void lx_set_mode(struct fb_info *info)
+{
+ struct lxfb_par *par = info->par;
+ u64 msrval;
+
+ unsigned int max, dv, val, size;
+
+ unsigned int gcfg, dcfg;
+ int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
+ int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
+
+ /* Unlock the DC registers */
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
+
+ lx_graphics_disable(info);
+
+ lx_set_clock(info);
+
+ /* Set output mode */
+
+ rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
+ msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT;
+
+ if (par->output & OUTPUT_PANEL) {
+ msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_FP;
+
+ if (par->output & OUTPUT_CRT)
+ msrval |= MSR_LX_GLD_MSR_CONFIG_FPC;
+ else
+ msrval &= ~MSR_LX_GLD_MSR_CONFIG_FPC;
+ } else
+ msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT;
+
+ wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
+
+ /* Clear the various buffers */
+ /* FIXME: Adjust for panning here */
+
+ write_dc(par, DC_FB_ST_OFFSET, 0);
+ write_dc(par, DC_CB_ST_OFFSET, 0);
+ write_dc(par, DC_CURS_ST_OFFSET, 0);
+
+ /* FIXME: Add support for interlacing */
+ /* FIXME: Add support for scaling */
+
+ val = read_dc(par, DC_GENLK_CTL);
+ val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN |
+ DC_GENLK_CTL_FLICK_SEL_MASK);
+
+ /* Default scaling params */
+
+ write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000);
+ write_dc(par, DC_IRQ_FILT_CTL, 0);
+ write_dc(par, DC_GENLK_CTL, val);
+
+ /* FIXME: Support compression */
+
+ if (info->fix.line_length > 4096)
+ dv = DC_DV_CTL_DV_LINE_SIZE_8K;
+ else if (info->fix.line_length > 2048)
+ dv = DC_DV_CTL_DV_LINE_SIZE_4K;
+ else if (info->fix.line_length > 1024)
+ dv = DC_DV_CTL_DV_LINE_SIZE_2K;
+ else
+ dv = DC_DV_CTL_DV_LINE_SIZE_1K;
+
+ max = info->fix.line_length * info->var.yres;
+ max = (max + 0x3FF) & 0xFFFFFC00;
+
+ write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN);
+
+ val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE;
+ write_dc(par, DC_DV_CTL, val | dv);
+
+ size = info->var.xres * (info->var.bits_per_pixel >> 3);
+
+ write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
+ write_dc(par, DC_LINE_SIZE, (size + 7) >> 3);
+
+ /* Set default watermark values */
+
+ rdmsrl(MSR_LX_SPARE_MSR, msrval);
+
+ msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO
+ | MSR_LX_SPARE_MSR_VFIFO_ARB_SEL
+ | MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M
+ | MSR_LX_SPARE_MSR_WM_LPEN_OVRD);
+ msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM |
+ MSR_LX_SPARE_MSR_DIS_INIT_V_PRI;
+ wrmsrl(MSR_LX_SPARE_MSR, msrval);
+
+ gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */
+ gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */
+ (0xb << DC_GENERAL_CFG_DFHPEL_SHIFT);
+ gcfg |= DC_GENERAL_CFG_FDTY; /* Set the frame dirty mode */
+
+ dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */
+ dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */
+ dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */
+ dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */
+ dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */
+ dcfg |= DC_DISPLAY_CFG_VISL;
+ dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */
+
+ /* Set the current BPP mode */
+
+ switch (info->var.bits_per_pixel) {
+ case 8:
+ dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
+ break;
+
+ case 16:
+ dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
+ break;
+
+ case 32:
+ case 24:
+ dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
+ break;
+ }
+
+ /* Now - set up the timings */
+
+ hactive = info->var.xres;
+ hblankstart = hactive;
+ hsyncstart = hblankstart + info->var.right_margin;
+ hsyncend = hsyncstart + info->var.hsync_len;
+ hblankend = hsyncend + info->var.left_margin;
+ htotal = hblankend;
+
+ vactive = info->var.yres;
+ vblankstart = vactive;
+ vsyncstart = vblankstart + info->var.lower_margin;
+ vsyncend = vsyncstart + info->var.vsync_len;
+ vblankend = vsyncend + info->var.upper_margin;
+ vtotal = vblankend;
+
+ write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16));
+ write_dc(par, DC_H_BLANK_TIMING,
+ (hblankstart - 1) | ((hblankend - 1) << 16));
+ write_dc(par, DC_H_SYNC_TIMING,
+ (hsyncstart - 1) | ((hsyncend - 1) << 16));
+
+ write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16));
+ write_dc(par, DC_V_BLANK_TIMING,
+ (vblankstart - 1) | ((vblankend - 1) << 16));
+ write_dc(par, DC_V_SYNC_TIMING,
+ (vsyncstart - 1) | ((vsyncend - 1) << 16));
+
+ write_dc(par, DC_FB_ACTIVE,
+ (info->var.xres - 1) << 16 | (info->var.yres - 1));
+
+ /* And re-enable the graphics output */
+ lx_graphics_enable(info);
+
+ /* Write the two main configuration registers */
+ write_dc(par, DC_DISPLAY_CFG, dcfg);
+ write_dc(par, DC_ARB_CFG, 0);
+ write_dc(par, DC_GENERAL_CFG, gcfg);
+
+ /* Lock the DC registers */
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
+}
+
+void lx_set_palette_reg(struct fb_info *info, unsigned regno,
+ unsigned red, unsigned green, unsigned blue)
+{
+ struct lxfb_par *par = info->par;
+ int val;
+
+ /* Hardware palette is in RGB 8-8-8 format. */
+
+ val = (red << 8) & 0xff0000;
+ val |= (green) & 0x00ff00;
+ val |= (blue >> 8) & 0x0000ff;
+
+ write_dc(par, DC_PAL_ADDRESS, regno);
+ write_dc(par, DC_PAL_DATA, val);
+}
+
+int lx_blank_display(struct fb_info *info, int blank_mode)
+{
+ struct lxfb_par *par = info->par;
+ u32 dcfg, misc, fp_pm;
+ int blank, hsync, vsync;
+
+ /* CRT power saving modes. */
+ switch (blank_mode) {
+ case FB_BLANK_UNBLANK:
+ blank = 0; hsync = 1; vsync = 1;
+ break;
+ case FB_BLANK_NORMAL:
+ blank = 1; hsync = 1; vsync = 1;
+ break;
+ case FB_BLANK_VSYNC_SUSPEND:
+ blank = 1; hsync = 1; vsync = 0;
+ break;
+ case FB_BLANK_HSYNC_SUSPEND:
+ blank = 1; hsync = 0; vsync = 1;
+ break;
+ case FB_BLANK_POWERDOWN:
+ blank = 1; hsync = 0; vsync = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dcfg = read_vp(par, VP_DCFG);
+ dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
+ VP_DCFG_CRT_EN);
+ if (!blank)
+ dcfg |= VP_DCFG_DAC_BL_EN | VP_DCFG_CRT_EN;
+ if (hsync)
+ dcfg |= VP_DCFG_HSYNC_EN;
+ if (vsync)
+ dcfg |= VP_DCFG_VSYNC_EN;
+
+ write_vp(par, VP_DCFG, dcfg);
+
+ misc = read_vp(par, VP_MISC);
+
+ if (vsync && hsync)
+ misc &= ~VP_MISC_DACPWRDN;
+ else
+ misc |= VP_MISC_DACPWRDN;
+
+ write_vp(par, VP_MISC, misc);
+
+ /* Power on/off flat panel */
+
+ if (par->output & OUTPUT_PANEL) {
+ fp_pm = read_fp(par, FP_PM);
+ if (blank_mode == FB_BLANK_POWERDOWN)
+ fp_pm &= ~FP_PM_P;
+ else
+ fp_pm |= FP_PM_P;
+ write_fp(par, FP_PM, fp_pm);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static void lx_save_regs(struct lxfb_par *par)
+{
+ uint32_t filt;
+ int i;
+
+ /* wait for the BLT engine to stop being busy */
+ do {
+ i = read_gp(par, GP_BLT_STATUS);
+ } while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE));
+
+ /* save MSRs */
+ rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
+ rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll);
+ rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
+ rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
+
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
+
+ /* save registers */
+ memcpy(par->gp, par->gp_regs, sizeof(par->gp));
+ memcpy(par->dc, par->dc_regs, sizeof(par->dc));
+ memcpy(par->vp, par->vp_regs, sizeof(par->vp));
+ memcpy(par->fp, par->vp_regs + VP_FP_START, sizeof(par->fp));
+
+ /* save the display controller palette */
+ write_dc(par, DC_PAL_ADDRESS, 0);
+ for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++)
+ par->dc_pal[i] = read_dc(par, DC_PAL_DATA);
+
+ /* save the video processor palette */
+ write_vp(par, VP_PAR, 0);
+ for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++)
+ par->vp_pal[i] = read_vp(par, VP_PDR);
+
+ /* save the horizontal filter coefficients */
+ filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
+ for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
+ write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
+ par->hcoeff[i] = read_dc(par, DC_FILT_COEFF1);
+ par->hcoeff[i + 1] = read_dc(par, DC_FILT_COEFF2);
+ }
+
+ /* save the vertical filter coefficients */
+ filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
+ for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
+ write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
+ par->vcoeff[i] = read_dc(par, DC_FILT_COEFF1);
+ }
+
+ /* save video coeff ram */
+ memcpy(par->vp_coeff, par->vp_regs + VP_VCR, sizeof(par->vp_coeff));
+}
+
+static void lx_restore_gfx_proc(struct lxfb_par *par)
+{
+ int i;
+
+ /* a bunch of registers require GP_RASTER_MODE to be set first */
+ write_gp(par, GP_RASTER_MODE, par->gp[GP_RASTER_MODE]);
+
+ for (i = 0; i < ARRAY_SIZE(par->gp); i++) {
+ switch (i) {
+ case GP_RASTER_MODE:
+ case GP_VECTOR_MODE:
+ case GP_BLT_MODE:
+ case GP_BLT_STATUS:
+ case GP_HST_SRC:
+ /* FIXME: restore LUT data */
+ case GP_LUT_INDEX:
+ case GP_LUT_DATA:
+ /* don't restore these registers */
+ break;
+
+ default:
+ write_gp(par, i, par->gp[i]);
+ }
+ }
+}
+
+static void lx_restore_display_ctlr(struct lxfb_par *par)
+{
+ uint32_t filt;
+ int i;
+
+ wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
+
+ for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
+ switch (i) {
+ case DC_UNLOCK:
+ /* unlock the DC; runs first */
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
+ break;
+
+ case DC_GENERAL_CFG:
+ case DC_DISPLAY_CFG:
+ /* disable all while restoring */
+ write_dc(par, i, 0);
+ break;
+
+ case DC_DV_CTL:
+ /* set all ram to dirty */
+ write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM);
+
+ case DC_RSVD_1:
+ case DC_RSVD_2:
+ case DC_RSVD_3:
+ case DC_LINE_CNT:
+ case DC_PAL_ADDRESS:
+ case DC_PAL_DATA:
+ case DC_DFIFO_DIAG:
+ case DC_CFIFO_DIAG:
+ case DC_FILT_COEFF1:
+ case DC_FILT_COEFF2:
+ case DC_RSVD_4:
+ case DC_RSVD_5:
+ /* don't restore these registers */
+ break;
+
+ default:
+ write_dc(par, i, par->dc[i]);
+ }
+ }
+
+ /* restore the palette */
+ write_dc(par, DC_PAL_ADDRESS, 0);
+ for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++)
+ write_dc(par, DC_PAL_DATA, par->dc_pal[i]);
+
+ /* restore the horizontal filter coefficients */
+ filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
+ for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
+ write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
+ write_dc(par, DC_FILT_COEFF1, par->hcoeff[i]);
+ write_dc(par, DC_FILT_COEFF2, par->hcoeff[i + 1]);
+ }
+
+ /* restore the vertical filter coefficients */
+ filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
+ for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
+ write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
+ write_dc(par, DC_FILT_COEFF1, par->vcoeff[i]);
+ }
+}
+
+static void lx_restore_video_proc(struct lxfb_par *par)
+{
+ int i;
+
+ wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
+ wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
+
+ for (i = 0; i < ARRAY_SIZE(par->vp); i++) {
+ switch (i) {
+ case VP_VCFG:
+ case VP_DCFG:
+ case VP_PAR:
+ case VP_PDR:
+ case VP_CCS:
+ case VP_RSVD_0:
+ /* case VP_VDC: */ /* why should this not be restored? */
+ case VP_RSVD_1:
+ case VP_CRC32:
+ /* don't restore these registers */
+ break;
+
+ default:
+ write_vp(par, i, par->vp[i]);
+ }
+ }
+
+ /* restore video processor palette */
+ write_vp(par, VP_PAR, 0);
+ for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++)
+ write_vp(par, VP_PDR, par->vp_pal[i]);
+
+ /* restore video coeff ram */
+ memcpy(par->vp_regs + VP_VCR, par->vp_coeff, sizeof(par->vp_coeff));
+}
+
+static void lx_restore_regs(struct lxfb_par *par)
+{
+ int i;
+
+ lx_set_dotpll((u32) (par->msr.dotpll >> 32));
+ lx_restore_gfx_proc(par);
+ lx_restore_display_ctlr(par);
+ lx_restore_video_proc(par);
+
+ /* Flat Panel */
+ for (i = 0; i < ARRAY_SIZE(par->fp); i++) {
+ switch (i) {
+ case FP_PM:
+ case FP_RSVD_0:
+ case FP_RSVD_1:
+ case FP_RSVD_2:
+ case FP_RSVD_3:
+ case FP_RSVD_4:
+ /* don't restore these registers */
+ break;
+
+ default:
+ write_fp(par, i, par->fp[i]);
+ }
+ }
+
+ /* control the panel */
+ if (par->fp[FP_PM] & FP_PM_P) {
+ /* power on the panel if not already power{ed,ing} on */
+ if (!(read_fp(par, FP_PM) &
+ (FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP)))
+ write_fp(par, FP_PM, par->fp[FP_PM]);
+ } else {
+ /* power down the panel if not already power{ed,ing} down */
+ if (!(read_fp(par, FP_PM) &
+ (FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN)))
+ write_fp(par, FP_PM, par->fp[FP_PM]);
+ }
+
+ /* turn everything on */
+ write_vp(par, VP_VCFG, par->vp[VP_VCFG]);
+ write_vp(par, VP_DCFG, par->vp[VP_DCFG]);
+ write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
+ /* do this last; it will enable the FIFO load */
+ write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
+
+ /* lock the door behind us */
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
+}
+
+int lx_powerdown(struct fb_info *info)
+{
+ struct lxfb_par *par = info->par;
+
+ if (par->powered_down)
+ return 0;
+
+ lx_save_regs(par);
+ lx_graphics_disable(info);
+
+ par->powered_down = 1;
+ return 0;
+}
+
+int lx_powerup(struct fb_info *info)
+{
+ struct lxfb_par *par = info->par;
+
+ if (!par->powered_down)
+ return 0;
+
+ lx_restore_regs(par);
+
+ par->powered_down = 0;
+ return 0;
+}
+
+#endif
diff --git a/drivers/video/fbdev/geode/suspend_gx.c b/drivers/video/fbdev/geode/suspend_gx.c
new file mode 100644
index 0000000..1bb043d
--- /dev/null
+++ b/drivers/video/fbdev/geode/suspend_gx.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Andres Salomon <dilinger@debian.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/fb.h>
+#include <asm/io.h>
+#include <asm/msr.h>
+#include <linux/cs5535.h>
+#include <asm/delay.h>
+
+#include "gxfb.h"
+
+#ifdef CONFIG_PM
+
+static void gx_save_regs(struct gxfb_par *par)
+{
+ int i;
+
+ /* wait for the BLT engine to stop being busy */
+ do {
+ i = read_gp(par, GP_BLT_STATUS);
+ } while (i & (GP_BLT_STATUS_BLT_PENDING | GP_BLT_STATUS_BLT_BUSY));
+
+ /* save MSRs */
+ rdmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel);
+ rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll);
+
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
+
+ /* save registers */
+ memcpy(par->gp, par->gp_regs, sizeof(par->gp));
+ memcpy(par->dc, par->dc_regs, sizeof(par->dc));
+ memcpy(par->vp, par->vid_regs, sizeof(par->vp));
+ memcpy(par->fp, par->vid_regs + VP_FP_START, sizeof(par->fp));
+
+ /* save the palette */
+ write_dc(par, DC_PAL_ADDRESS, 0);
+ for (i = 0; i < ARRAY_SIZE(par->pal); i++)
+ par->pal[i] = read_dc(par, DC_PAL_DATA);
+}
+
+static void gx_set_dotpll(uint32_t dotpll_hi)
+{
+ uint32_t dotpll_lo;
+ int i;
+
+ rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo);
+ dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
+ dotpll_lo &= ~MSR_GLCP_DOTPLL_BYPASS;
+ wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+
+ /* wait for the PLL to lock */
+ for (i = 0; i < 200; i++) {
+ rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo);
+ if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
+ break;
+ udelay(1);
+ }
+
+ /* PLL set, unlock */
+ dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
+ wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
+}
+
+static void gx_restore_gfx_proc(struct gxfb_par *par)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(par->gp); i++) {
+ switch (i) {
+ case GP_VECTOR_MODE:
+ case GP_BLT_MODE:
+ case GP_BLT_STATUS:
+ case GP_HST_SRC:
+ /* don't restore these registers */
+ break;
+ default:
+ write_gp(par, i, par->gp[i]);
+ }
+ }
+}
+
+static void gx_restore_display_ctlr(struct gxfb_par *par)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
+ switch (i) {
+ case DC_UNLOCK:
+ /* unlock the DC; runs first */
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
+ break;
+
+ case DC_GENERAL_CFG:
+ /* write without the enables */
+ write_dc(par, i, par->dc[i] & ~(DC_GENERAL_CFG_VIDE |
+ DC_GENERAL_CFG_ICNE |
+ DC_GENERAL_CFG_CURE |
+ DC_GENERAL_CFG_DFLE));
+ break;
+
+ case DC_DISPLAY_CFG:
+ /* write without the enables */
+ write_dc(par, i, par->dc[i] & ~(DC_DISPLAY_CFG_VDEN |
+ DC_DISPLAY_CFG_GDEN |
+ DC_DISPLAY_CFG_TGEN));
+ break;
+
+ case DC_RSVD_0:
+ case DC_RSVD_1:
+ case DC_RSVD_2:
+ case DC_RSVD_3:
+ case DC_RSVD_4:
+ case DC_LINE_CNT:
+ case DC_PAL_ADDRESS:
+ case DC_PAL_DATA:
+ case DC_DFIFO_DIAG:
+ case DC_CFIFO_DIAG:
+ case DC_RSVD_5:
+ /* don't restore these registers */
+ break;
+ default:
+ write_dc(par, i, par->dc[i]);
+ }
+ }
+
+ /* restore the palette */
+ write_dc(par, DC_PAL_ADDRESS, 0);
+ for (i = 0; i < ARRAY_SIZE(par->pal); i++)
+ write_dc(par, DC_PAL_DATA, par->pal[i]);
+}
+
+static void gx_restore_video_proc(struct gxfb_par *par)
+{
+ int i;
+
+ wrmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel);
+
+ for (i = 0; i < ARRAY_SIZE(par->vp); i++) {
+ switch (i) {
+ case VP_VCFG:
+ /* don't enable video yet */
+ write_vp(par, i, par->vp[i] & ~VP_VCFG_VID_EN);
+ break;
+
+ case VP_DCFG:
+ /* don't enable CRT yet */
+ write_vp(par, i, par->vp[i] &
+ ~(VP_DCFG_DAC_BL_EN | VP_DCFG_VSYNC_EN |
+ VP_DCFG_HSYNC_EN | VP_DCFG_CRT_EN));
+ break;
+
+ case VP_GAR:
+ case VP_GDR:
+ case VP_RSVD_0:
+ case VP_RSVD_1:
+ case VP_RSVD_2:
+ case VP_RSVD_3:
+ case VP_CRC32:
+ case VP_AWT:
+ case VP_VTM:
+ /* don't restore these registers */
+ break;
+ default:
+ write_vp(par, i, par->vp[i]);
+ }
+ }
+}
+
+static void gx_restore_regs(struct gxfb_par *par)
+{
+ int i;
+
+ gx_set_dotpll((uint32_t) (par->msr.dotpll >> 32));
+ gx_restore_gfx_proc(par);
+ gx_restore_display_ctlr(par);
+ gx_restore_video_proc(par);
+
+ /* Flat Panel */
+ for (i = 0; i < ARRAY_SIZE(par->fp); i++) {
+ if (i != FP_PM && i != FP_RSVD_0)
+ write_fp(par, i, par->fp[i]);
+ }
+}
+
+static void gx_disable_graphics(struct gxfb_par *par)
+{
+ /* shut down the engine */
+ write_vp(par, VP_VCFG, par->vp[VP_VCFG] & ~VP_VCFG_VID_EN);
+ write_vp(par, VP_DCFG, par->vp[VP_DCFG] & ~(VP_DCFG_DAC_BL_EN |
+ VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN | VP_DCFG_CRT_EN));
+
+ /* turn off the flat panel */
+ write_fp(par, FP_PM, par->fp[FP_PM] & ~FP_PM_P);
+
+
+ /* turn off display */
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
+ write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG] &
+ ~(DC_GENERAL_CFG_VIDE | DC_GENERAL_CFG_ICNE |
+ DC_GENERAL_CFG_CURE | DC_GENERAL_CFG_DFLE));
+ write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG] &
+ ~(DC_DISPLAY_CFG_VDEN | DC_DISPLAY_CFG_GDEN |
+ DC_DISPLAY_CFG_TGEN));
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
+}
+
+static void gx_enable_graphics(struct gxfb_par *par)
+{
+ uint32_t fp;
+
+ fp = read_fp(par, FP_PM);
+ if (par->fp[FP_PM] & FP_PM_P) {
+ /* power on the panel if not already power{ed,ing} on */
+ if (!(fp & (FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP)))
+ write_fp(par, FP_PM, par->fp[FP_PM]);
+ } else {
+ /* power down the panel if not already power{ed,ing} down */
+ if (!(fp & (FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN)))
+ write_fp(par, FP_PM, par->fp[FP_PM]);
+ }
+
+ /* turn everything on */
+ write_vp(par, VP_VCFG, par->vp[VP_VCFG]);
+ write_vp(par, VP_DCFG, par->vp[VP_DCFG]);
+ write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
+ /* do this last; it will enable the FIFO load */
+ write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
+
+ /* lock the door behind us */
+ write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
+}
+
+int gx_powerdown(struct fb_info *info)
+{
+ struct gxfb_par *par = info->par;
+
+ if (par->powered_down)
+ return 0;
+
+ gx_save_regs(par);
+ gx_disable_graphics(par);
+
+ par->powered_down = 1;
+ return 0;
+}
+
+int gx_powerup(struct fb_info *info)
+{
+ struct gxfb_par *par = info->par;
+
+ if (!par->powered_down)
+ return 0;
+
+ gx_restore_regs(par);
+ gx_enable_graphics(par);
+
+ par->powered_down = 0;
+ return 0;
+}
+
+#endif
diff --git a/drivers/video/fbdev/geode/video_cs5530.c b/drivers/video/fbdev/geode/video_cs5530.c
new file mode 100644
index 0000000..8806132
--- /dev/null
+++ b/drivers/video/fbdev/geode/video_cs5530.c
@@ -0,0 +1,193 @@
+/*
+ * drivers/video/geode/video_cs5530.c
+ * -- CS5530 video device
+ *
+ * Copyright (C) 2005 Arcom Control Systems Ltd.
+ *
+ * Based on AMD's original 2.4 driver:
+ * Copyright (C) 2004 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/delay.h>
+
+#include "geodefb.h"
+#include "video_cs5530.h"
+
+/*
+ * CS5530 PLL table. This maps pixclocks to the appropriate PLL register
+ * value.
+ */
+struct cs5530_pll_entry {
+ long pixclock; /* ps */
+ u32 pll_value;
+};
+
+static const struct cs5530_pll_entry cs5530_pll_table[] = {
+ { 39721, 0x31C45801, }, /* 25.1750 MHz */
+ { 35308, 0x20E36802, }, /* 28.3220 */
+ { 31746, 0x33915801, }, /* 31.5000 */
+ { 27777, 0x31EC4801, }, /* 36.0000 */
+ { 26666, 0x21E22801, }, /* 37.5000 */
+ { 25000, 0x33088801, }, /* 40.0000 */
+ { 22271, 0x33E22801, }, /* 44.9000 */
+ { 20202, 0x336C4801, }, /* 49.5000 */
+ { 20000, 0x23088801, }, /* 50.0000 */
+ { 19860, 0x23088801, }, /* 50.3500 */
+ { 18518, 0x3708A801, }, /* 54.0000 */
+ { 17777, 0x23E36802, }, /* 56.2500 */
+ { 17733, 0x23E36802, }, /* 56.3916 */
+ { 17653, 0x23E36802, }, /* 56.6444 */
+ { 16949, 0x37C45801, }, /* 59.0000 */
+ { 15873, 0x23EC4801, }, /* 63.0000 */
+ { 15384, 0x37911801, }, /* 65.0000 */
+ { 14814, 0x37963803, }, /* 67.5000 */
+ { 14124, 0x37058803, }, /* 70.8000 */
+ { 13888, 0x3710C805, }, /* 72.0000 */
+ { 13333, 0x37E22801, }, /* 75.0000 */
+ { 12698, 0x27915801, }, /* 78.7500 */
+ { 12500, 0x37D8D802, }, /* 80.0000 */
+ { 11135, 0x27588802, }, /* 89.8000 */
+ { 10582, 0x27EC4802, }, /* 94.5000 */
+ { 10101, 0x27AC6803, }, /* 99.0000 */
+ { 10000, 0x27088801, }, /* 100.0000 */
+ { 9259, 0x2710C805, }, /* 108.0000 */
+ { 8888, 0x27E36802, }, /* 112.5000 */
+ { 7692, 0x27C58803, }, /* 130.0000 */
+ { 7407, 0x27316803, }, /* 135.0000 */
+ { 6349, 0x2F915801, }, /* 157.5000 */
+ { 6172, 0x2F08A801, }, /* 162.0000 */
+ { 5714, 0x2FB11802, }, /* 175.0000 */
+ { 5291, 0x2FEC4802, }, /* 189.0000 */
+ { 4950, 0x2F963803, }, /* 202.0000 */
+ { 4310, 0x2FB1B802, }, /* 232.0000 */
+};
+
+static void cs5530_set_dclk_frequency(struct fb_info *info)
+{
+ struct geodefb_par *par = info->par;
+ int i;
+ u32 value;
+ long min, diff;
+
+ /* Search the table for the closest pixclock. */
+ value = cs5530_pll_table[0].pll_value;
+ min = cs5530_pll_table[0].pixclock - info->var.pixclock;
+ if (min < 0) min = -min;
+ for (i = 1; i < ARRAY_SIZE(cs5530_pll_table); i++) {
+ diff = cs5530_pll_table[i].pixclock - info->var.pixclock;
+ if (diff < 0L) diff = -diff;
+ if (diff < min) {
+ min = diff;
+ value = cs5530_pll_table[i].pll_value;
+ }
+ }
+
+ writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG);
+ writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */
+ udelay(500); /* wait for PLL to settle */
+ writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */
+ writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */
+}
+
+static void cs5530_configure_display(struct fb_info *info)
+{
+ struct geodefb_par *par = info->par;
+ u32 dcfg;
+
+ dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
+
+ /* Clear bits from existing mode. */
+ dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK
+ | CS5530_DCFG_CRT_HSYNC_POL | CS5530_DCFG_CRT_VSYNC_POL
+ | CS5530_DCFG_FP_PWR_EN | CS5530_DCFG_FP_DATA_EN
+ | CS5530_DCFG_DAC_PWR_EN | CS5530_DCFG_VSYNC_EN
+ | CS5530_DCFG_HSYNC_EN);
+
+ /* Set default sync skew and power sequence delays. */
+ dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT
+ | CS5530_DCFG_GV_PAL_BYP);
+
+ /* Enable DACs, hsync and vsync for CRTs */
+ if (par->enable_crt) {
+ dcfg |= CS5530_DCFG_DAC_PWR_EN;
+ dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN;
+ }
+ /* Enable panel power and data if using a flat panel. */
+ if (par->panel_x > 0) {
+ dcfg |= CS5530_DCFG_FP_PWR_EN;
+ dcfg |= CS5530_DCFG_FP_DATA_EN;
+ }
+
+ /* Sync polarities. */
+ if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
+ dcfg |= CS5530_DCFG_CRT_HSYNC_POL;
+ if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
+ dcfg |= CS5530_DCFG_CRT_VSYNC_POL;
+
+ writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
+}
+
+static int cs5530_blank_display(struct fb_info *info, int blank_mode)
+{
+ struct geodefb_par *par = info->par;
+ u32 dcfg;
+ int blank, hsync, vsync;
+
+ switch (blank_mode) {
+ case FB_BLANK_UNBLANK:
+ blank = 0; hsync = 1; vsync = 1;
+ break;
+ case FB_BLANK_NORMAL:
+ blank = 1; hsync = 1; vsync = 1;
+ break;
+ case FB_BLANK_VSYNC_SUSPEND:
+ blank = 1; hsync = 1; vsync = 0;
+ break;
+ case FB_BLANK_HSYNC_SUSPEND:
+ blank = 1; hsync = 0; vsync = 1;
+ break;
+ case FB_BLANK_POWERDOWN:
+ blank = 1; hsync = 0; vsync = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
+
+ dcfg &= ~(CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN
+ | CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN
+ | CS5530_DCFG_FP_DATA_EN | CS5530_DCFG_FP_PWR_EN);
+
+ if (par->enable_crt) {
+ if (!blank)
+ dcfg |= CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN;
+ if (hsync)
+ dcfg |= CS5530_DCFG_HSYNC_EN;
+ if (vsync)
+ dcfg |= CS5530_DCFG_VSYNC_EN;
+ }
+ if (par->panel_x > 0) {
+ if (!blank)
+ dcfg |= CS5530_DCFG_FP_DATA_EN;
+ if (hsync && vsync)
+ dcfg |= CS5530_DCFG_FP_PWR_EN;
+ }
+
+ writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
+
+ return 0;
+}
+
+const struct geode_vid_ops cs5530_vid_ops = {
+ .set_dclk = cs5530_set_dclk_frequency,
+ .configure_display = cs5530_configure_display,
+ .blank_display = cs5530_blank_display,
+};
diff --git a/drivers/video/fbdev/geode/video_cs5530.h b/drivers/video/fbdev/geode/video_cs5530.h
new file mode 100644
index 0000000..c843348
--- /dev/null
+++ b/drivers/video/fbdev/geode/video_cs5530.h
@@ -0,0 +1,75 @@
+/*
+ * drivers/video/geode/video_cs5530.h
+ * -- CS5530 video device
+ *
+ * Copyright (C) 2005 Arcom Control Systems Ltd.
+ *
+ * Based on AMD's original 2.4 driver:
+ * Copyright (C) 2004 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __VIDEO_CS5530_H__
+#define __VIDEO_CS5530_H__
+
+extern const struct geode_vid_ops cs5530_vid_ops;
+
+/* CS5530 Video device registers */
+
+#define CS5530_VIDEO_CONFIG 0x0000
+# define CS5530_VCFG_VID_EN 0x00000001
+# define CS5530_VCFG_VID_REG_UPDATE 0x00000002
+# define CS5530_VCFG_VID_INP_FORMAT 0x0000000C
+# define CS5530_VCFG_8_BIT_4_2_0 0x00000004
+# define CS5530_VCFG_16_BIT_4_2_0 0x00000008
+# define CS5530_VCFG_GV_SEL 0x00000010
+# define CS5530_VCFG_CSC_BYPASS 0x00000020
+# define CS5530_VCFG_X_FILTER_EN 0x00000040
+# define CS5530_VCFG_Y_FILTER_EN 0x00000080
+# define CS5530_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00
+# define CS5530_VCFG_INIT_READ_MASK 0x01FF0000
+# define CS5530_VCFG_EARLY_VID_RDY 0x02000000
+# define CS5530_VCFG_LINE_SIZE_UPPER 0x08000000
+# define CS5530_VCFG_4_2_0_MODE 0x10000000
+# define CS5530_VCFG_16_BIT_EN 0x20000000
+# define CS5530_VCFG_HIGH_SPD_INT 0x40000000
+
+#define CS5530_DISPLAY_CONFIG 0x0004
+# define CS5530_DCFG_DIS_EN 0x00000001
+# define CS5530_DCFG_HSYNC_EN 0x00000002
+# define CS5530_DCFG_VSYNC_EN 0x00000004
+# define CS5530_DCFG_DAC_BL_EN 0x00000008
+# define CS5530_DCFG_DAC_PWR_EN 0x00000020
+# define CS5530_DCFG_FP_PWR_EN 0x00000040
+# define CS5530_DCFG_FP_DATA_EN 0x00000080
+# define CS5530_DCFG_CRT_HSYNC_POL 0x00000100
+# define CS5530_DCFG_CRT_VSYNC_POL 0x00000200
+# define CS5530_DCFG_FP_HSYNC_POL 0x00000400
+# define CS5530_DCFG_FP_VSYNC_POL 0x00000800
+# define CS5530_DCFG_XGA_FP 0x00001000
+# define CS5530_DCFG_FP_DITH_EN 0x00002000
+# define CS5530_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
+# define CS5530_DCFG_CRT_SYNC_SKW_INIT 0x00010000
+# define CS5530_DCFG_PWR_SEQ_DLY_MASK 0x000E0000
+# define CS5530_DCFG_PWR_SEQ_DLY_INIT 0x00080000
+# define CS5530_DCFG_VG_CK 0x00100000
+# define CS5530_DCFG_GV_PAL_BYP 0x00200000
+# define CS5530_DCFG_DDC_SCL 0x00400000
+# define CS5530_DCFG_DDC_SDA 0x00800000
+# define CS5530_DCFG_DDC_OE 0x01000000
+# define CS5530_DCFG_16_BIT_EN 0x02000000
+
+#define CS5530_VIDEO_X_POS 0x0008
+#define CS5530_VIDEO_Y_POS 0x000C
+#define CS5530_VIDEO_SCALE 0x0010
+#define CS5530_VIDEO_COLOR_KEY 0x0014
+#define CS5530_VIDEO_COLOR_MASK 0x0018
+#define CS5530_PALETTE_ADDRESS 0x001C
+#define CS5530_PALETTE_DATA 0x0020
+#define CS5530_DOT_CLK_CONFIG 0x0024
+#define CS5530_CRCSIG_TFT_TV 0x0028
+
+#endif /* !__VIDEO_CS5530_H__ */
diff --git a/drivers/video/fbdev/geode/video_gx.c b/drivers/video/fbdev/geode/video_gx.c
new file mode 100644
index 0000000..67773e8
--- /dev/null
+++ b/drivers/video/fbdev/geode/video_gx.c
@@ -0,0 +1,349 @@
+/*
+ * Geode GX video processor device.
+ *
+ * Copyright (C) 2006 Arcom Control Systems Ltd.
+ *
+ * Portions from AMD's original 2.4 driver:
+ * Copyright (C) 2004 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/delay.h>
+#include <asm/msr.h>
+#include <linux/cs5535.h>
+
+#include "gxfb.h"
+
+
+/*
+ * Tables of register settings for various DOTCLKs.
+ */
+struct gx_pll_entry {
+ long pixclock; /* ps */
+ u32 sys_rstpll_bits;
+ u32 dotpll_value;
+};
+
+#define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
+#define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
+#define PREDIV2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
+
+static const struct gx_pll_entry gx_pll_table_48MHz[] = {
+ { 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
+ { 39721, 0, 0x00000037 }, /* 25.1750 */
+ { 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
+ { 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
+ { 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
+ { 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
+ { 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
+ { 22271, 0, 0x00000063 }, /* 44.9000 */
+ { 20202, 0, 0x0000054B }, /* 49.5000 */
+ { 20000, 0, 0x0000026E }, /* 50.0000 */
+ { 19860, PREMULT2, 0x00000037 }, /* 50.3500 */
+ { 18518, POSTDIV3|PREMULT2, 0x00000B0D }, /* 54.0000 */
+ { 17777, 0, 0x00000577 }, /* 56.2500 */
+ { 17733, 0, 0x000007F7 }, /* 56.3916 */
+ { 17653, 0, 0x0000057B }, /* 56.6444 */
+ { 16949, PREMULT2, 0x00000707 }, /* 59.0000 */
+ { 15873, POSTDIV3|PREMULT2, 0x00000B39 }, /* 63.0000 */
+ { 15384, POSTDIV3|PREMULT2, 0x00000B45 }, /* 65.0000 */
+ { 14814, POSTDIV3|PREMULT2, 0x00000FC1 }, /* 67.5000 */
+ { 14124, POSTDIV3, 0x00000561 }, /* 70.8000 */
+ { 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */
+ { 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */
+ { 13333, 0, 0x00000052 }, /* 75.0000 */
+ { 12698, 0, 0x00000056 }, /* 78.7500 */
+ { 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */
+ { 11135, PREMULT2, 0x00000262 }, /* 89.8000 */
+ { 10582, 0, 0x000002D2 }, /* 94.5000 */
+ { 10101, PREMULT2, 0x00000B4A }, /* 99.0000 */
+ { 10000, PREMULT2, 0x00000036 }, /* 100.0000 */
+ { 9259, 0, 0x000007E2 }, /* 108.0000 */
+ { 8888, 0, 0x000007F6 }, /* 112.5000 */
+ { 7692, POSTDIV3|PREMULT2, 0x00000FB0 }, /* 130.0000 */
+ { 7407, POSTDIV3|PREMULT2, 0x00000B50 }, /* 135.0000 */
+ { 6349, 0, 0x00000055 }, /* 157.5000 */
+ { 6172, 0, 0x000009C1 }, /* 162.0000 */
+ { 5787, PREMULT2, 0x0000002D }, /* 172.798 */
+ { 5698, 0, 0x000002C1 }, /* 175.5000 */
+ { 5291, 0, 0x000002D1 }, /* 189.0000 */
+ { 4938, 0, 0x00000551 }, /* 202.5000 */
+ { 4357, 0, 0x0000057D }, /* 229.5000 */
+};
+
+static const struct gx_pll_entry gx_pll_table_14MHz[] = {
+ { 39721, 0, 0x00000037 }, /* 25.1750 */
+ { 35308, 0, 0x00000B7B }, /* 28.3220 */
+ { 31746, 0, 0x000004D3 }, /* 31.5000 */
+ { 27777, 0, 0x00000BE3 }, /* 36.0000 */
+ { 26666, 0, 0x0000074F }, /* 37.5000 */
+ { 25000, 0, 0x0000050B }, /* 40.0000 */
+ { 22271, 0, 0x00000063 }, /* 44.9000 */
+ { 20202, 0, 0x0000054B }, /* 49.5000 */
+ { 20000, 0, 0x0000026E }, /* 50.0000 */
+ { 19860, 0, 0x000007C3 }, /* 50.3500 */
+ { 18518, 0, 0x000007E3 }, /* 54.0000 */
+ { 17777, 0, 0x00000577 }, /* 56.2500 */
+ { 17733, 0, 0x000002FB }, /* 56.3916 */
+ { 17653, 0, 0x0000057B }, /* 56.6444 */
+ { 16949, 0, 0x0000058B }, /* 59.0000 */
+ { 15873, 0, 0x0000095E }, /* 63.0000 */
+ { 15384, 0, 0x0000096A }, /* 65.0000 */
+ { 14814, 0, 0x00000BC2 }, /* 67.5000 */
+ { 14124, 0, 0x0000098A }, /* 70.8000 */
+ { 13888, 0, 0x00000BE2 }, /* 72.0000 */
+ { 13333, 0, 0x00000052 }, /* 75.0000 */
+ { 12698, 0, 0x00000056 }, /* 78.7500 */
+ { 12500, 0, 0x0000050A }, /* 80.0000 */
+ { 11135, 0, 0x0000078E }, /* 89.8000 */
+ { 10582, 0, 0x000002D2 }, /* 94.5000 */
+ { 10101, 0, 0x000011F6 }, /* 99.0000 */
+ { 10000, 0, 0x0000054E }, /* 100.0000 */
+ { 9259, 0, 0x000007E2 }, /* 108.0000 */
+ { 8888, 0, 0x000002FA }, /* 112.5000 */
+ { 7692, 0, 0x00000BB1 }, /* 130.0000 */
+ { 7407, 0, 0x00000975 }, /* 135.0000 */
+ { 6349, 0, 0x00000055 }, /* 157.5000 */
+ { 6172, 0, 0x000009C1 }, /* 162.0000 */
+ { 5698, 0, 0x000002C1 }, /* 175.5000 */
+ { 5291, 0, 0x00000539 }, /* 189.0000 */
+ { 4938, 0, 0x00000551 }, /* 202.5000 */
+ { 4357, 0, 0x0000057D }, /* 229.5000 */
+};
+
+void gx_set_dclk_frequency(struct fb_info *info)
+{
+ const struct gx_pll_entry *pll_table;
+ int pll_table_len;
+ int i, best_i;
+ long min, diff;
+ u64 dotpll, sys_rstpll;
+ int timeout = 1000;
+
+ /* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
+ if (cpu_data(0).x86_stepping == 1) {
+ pll_table = gx_pll_table_14MHz;
+ pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
+ } else {
+ pll_table = gx_pll_table_48MHz;
+ pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
+ }
+
+ /* Search the table for the closest pixclock. */
+ best_i = 0;
+ min = abs(pll_table[0].pixclock - info->var.pixclock);
+ for (i = 1; i < pll_table_len; i++) {
+ diff = abs(pll_table[i].pixclock - info->var.pixclock);
+ if (diff < min) {
+ min = diff;
+ best_i = i;
+ }
+ }
+
+ rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ /* Program new M, N and P. */
+ dotpll &= 0x00000000ffffffffull;
+ dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
+ dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
+ dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
+
+ wrmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ /* Program dividers. */
+ sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
+ | MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
+ | MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
+ sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
+
+ wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
+
+ /* Clear reset bit to start PLL. */
+ dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
+ wrmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ /* Wait for LOCK bit. */
+ do {
+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
+ } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
+}
+
+static void
+gx_configure_tft(struct fb_info *info)
+{
+ struct gxfb_par *par = info->par;
+ unsigned long val;
+ unsigned long fp;
+
+ /* Set up the DF pad select MSR */
+
+ rdmsrl(MSR_GX_MSR_PADSEL, val);
+ val &= ~MSR_GX_MSR_PADSEL_MASK;
+ val |= MSR_GX_MSR_PADSEL_TFT;
+ wrmsrl(MSR_GX_MSR_PADSEL, val);
+
+ /* Turn off the panel */
+
+ fp = read_fp(par, FP_PM);
+ fp &= ~FP_PM_P;
+ write_fp(par, FP_PM, fp);
+
+ /* Set timing 1 */
+
+ fp = read_fp(par, FP_PT1);
+ fp &= FP_PT1_VSIZE_MASK;
+ fp |= info->var.yres << FP_PT1_VSIZE_SHIFT;
+ write_fp(par, FP_PT1, fp);
+
+ /* Timing 2 */
+ /* Set bits that are always on for TFT */
+
+ fp = 0x0F100000;
+
+ /* Configure sync polarity */
+
+ if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
+ fp |= FP_PT2_VSP;
+
+ if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
+ fp |= FP_PT2_HSP;
+
+ write_fp(par, FP_PT2, fp);
+
+ /* Set the dither control */
+ write_fp(par, FP_DFC, FP_DFC_NFI);
+
+ /* Enable the FP data and power (in case the BIOS didn't) */
+
+ fp = read_vp(par, VP_DCFG);
+ fp |= VP_DCFG_FP_PWR_EN | VP_DCFG_FP_DATA_EN;
+ write_vp(par, VP_DCFG, fp);
+
+ /* Unblank the panel */
+
+ fp = read_fp(par, FP_PM);
+ fp |= FP_PM_P;
+ write_fp(par, FP_PM, fp);
+}
+
+void gx_configure_display(struct fb_info *info)
+{
+ struct gxfb_par *par = info->par;
+ u32 dcfg, misc;
+
+ /* Write the display configuration */
+ dcfg = read_vp(par, VP_DCFG);
+
+ /* Disable hsync and vsync */
+ dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
+ write_vp(par, VP_DCFG, dcfg);
+
+ /* Clear bits from existing mode. */
+ dcfg &= ~(VP_DCFG_CRT_SYNC_SKW
+ | VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL
+ | VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
+
+ /* Set default sync skew. */
+ dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT;
+
+ /* Enable hsync and vsync. */
+ dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN;
+
+ misc = read_vp(par, VP_MISC);
+
+ /* Disable gamma correction */
+ misc |= VP_MISC_GAM_EN;
+
+ if (par->enable_crt) {
+
+ /* Power up the CRT DACs */
+ misc &= ~(VP_MISC_APWRDN | VP_MISC_DACPWRDN);
+ write_vp(par, VP_MISC, misc);
+
+ /* Only change the sync polarities if we are running
+ * in CRT mode. The FP polarities will be handled in
+ * gxfb_configure_tft */
+ if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
+ dcfg |= VP_DCFG_CRT_HSYNC_POL;
+ if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
+ dcfg |= VP_DCFG_CRT_VSYNC_POL;
+ } else {
+ /* Power down the CRT DACs if in FP mode */
+ misc |= (VP_MISC_APWRDN | VP_MISC_DACPWRDN);
+ write_vp(par, VP_MISC, misc);
+ }
+
+ /* Enable the display logic */
+ /* Set up the DACS to blank normally */
+
+ dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN;
+
+ /* Enable the external DAC VREF? */
+
+ write_vp(par, VP_DCFG, dcfg);
+
+ /* Set up the flat panel (if it is enabled) */
+
+ if (par->enable_crt == 0)
+ gx_configure_tft(info);
+}
+
+int gx_blank_display(struct fb_info *info, int blank_mode)
+{
+ struct gxfb_par *par = info->par;
+ u32 dcfg, fp_pm;
+ int blank, hsync, vsync, crt;
+
+ /* CRT power saving modes. */
+ switch (blank_mode) {
+ case FB_BLANK_UNBLANK:
+ blank = 0; hsync = 1; vsync = 1; crt = 1;
+ break;
+ case FB_BLANK_NORMAL:
+ blank = 1; hsync = 1; vsync = 1; crt = 1;
+ break;
+ case FB_BLANK_VSYNC_SUSPEND:
+ blank = 1; hsync = 1; vsync = 0; crt = 1;
+ break;
+ case FB_BLANK_HSYNC_SUSPEND:
+ blank = 1; hsync = 0; vsync = 1; crt = 1;
+ break;
+ case FB_BLANK_POWERDOWN:
+ blank = 1; hsync = 0; vsync = 0; crt = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ dcfg = read_vp(par, VP_DCFG);
+ dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
+ VP_DCFG_CRT_EN);
+ if (!blank)
+ dcfg |= VP_DCFG_DAC_BL_EN;
+ if (hsync)
+ dcfg |= VP_DCFG_HSYNC_EN;
+ if (vsync)
+ dcfg |= VP_DCFG_VSYNC_EN;
+ if (crt)
+ dcfg |= VP_DCFG_CRT_EN;
+ write_vp(par, VP_DCFG, dcfg);
+
+ /* Power on/off flat panel. */
+
+ if (par->enable_crt == 0) {
+ fp_pm = read_fp(par, FP_PM);
+ if (blank_mode == FB_BLANK_POWERDOWN)
+ fp_pm &= ~FP_PM_P;
+ else
+ fp_pm |= FP_PM_P;
+ write_fp(par, FP_PM, fp_pm);
+ }
+
+ return 0;
+}