v4.19.13 snapshot.
diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild
new file mode 100644
index 0000000..a4b8d33
--- /dev/null
+++ b/arch/m68k/include/asm/Kbuild
@@ -0,0 +1,26 @@
+generic-y += barrier.h
+generic-y += compat.h
+generic-y += device.h
+generic-y += dma-mapping.h
+generic-y += emergency-restart.h
+generic-y += exec.h
+generic-y += extable.h
+generic-y += futex.h
+generic-y += hw_irq.h
+generic-y += irq_regs.h
+generic-y += irq_work.h
+generic-y += kdebug.h
+generic-y += kmap_types.h
+generic-y += kprobes.h
+generic-y += local.h
+generic-y += local64.h
+generic-y += mcs_spinlock.h
+generic-y += mm-arch-hooks.h
+generic-y += percpu.h
+generic-y += preempt.h
+generic-y += sections.h
+generic-y += spinlock.h
+generic-y += topology.h
+generic-y += trace_clock.h
+generic-y += word-at-a-time.h
+generic-y += xor.h
diff --git a/arch/m68k/include/asm/MC68328.h b/arch/m68k/include/asm/MC68328.h
new file mode 100644
index 0000000..6e14e92
--- /dev/null
+++ b/arch/m68k/include/asm/MC68328.h
@@ -0,0 +1,1268 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* include/asm-m68knommu/MC68328.h: '328 control registers
+ *
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ * Bear & Hare Software, Inc.
+ *
+ * Based on include/asm-m68knommu/MC68332.h
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
+ *
+ */
+#include <linux/compiler.h>
+
+#ifndef _MC68328_H_
+#define _MC68328_H_
+
+#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
+#define WORD_REF(addr) (*((volatile unsigned short*)addr))
+#define LONG_REF(addr) (*((volatile unsigned long*)addr))
+
+#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
+#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
+
+/**********
+ *
+ * 0xFFFFF0xx -- System Control
+ *
+ **********/
+
+/*
+ * System Control Register (SCR)
+ */
+#define SCR_ADDR 0xfffff000
+#define SCR BYTE_REF(SCR_ADDR)
+
+#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
+#define SCR_DMAP 0x04 /* Double Map */
+#define SCR_SO 0x08 /* Supervisor Only */
+#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
+#define SCR_PRV 0x20 /* Privilege Violation */
+#define SCR_WPV 0x40 /* Write Protect Violation */
+#define SCR_BETO 0x80 /* Bus-Error TimeOut */
+
+/*
+ * Mask Revision Register
+ */
+#define MRR_ADDR 0xfffff004
+#define MRR LONG_REF(MRR_ADDR)
+
+/**********
+ *
+ * 0xFFFFF1xx -- Chip-Select logic
+ *
+ **********/
+
+/**********
+ *
+ * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
+ *
+ **********/
+
+/*
+ * Group Base Address Registers
+ */
+#define GRPBASEA_ADDR 0xfffff100
+#define GRPBASEB_ADDR 0xfffff102
+#define GRPBASEC_ADDR 0xfffff104
+#define GRPBASED_ADDR 0xfffff106
+
+#define GRPBASEA WORD_REF(GRPBASEA_ADDR)
+#define GRPBASEB WORD_REF(GRPBASEB_ADDR)
+#define GRPBASEC WORD_REF(GRPBASEC_ADDR)
+#define GRPBASED WORD_REF(GRPBASED_ADDR)
+
+#define GRPBASE_V 0x0001 /* Valid */
+#define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
+
+/*
+ * Group Base Address Mask Registers
+ */
+#define GRPMASKA_ADDR 0xfffff108
+#define GRPMASKB_ADDR 0xfffff10a
+#define GRPMASKC_ADDR 0xfffff10c
+#define GRPMASKD_ADDR 0xfffff10e
+
+#define GRPMASKA WORD_REF(GRPMASKA_ADDR)
+#define GRPMASKB WORD_REF(GRPMASKB_ADDR)
+#define GRPMASKC WORD_REF(GRPMASKC_ADDR)
+#define GRPMASKD WORD_REF(GRPMASKD_ADDR)
+
+#define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */
+
+/*
+ * Chip-Select Option Registers (group A)
+ */
+#define CSA0_ADDR 0xfffff110
+#define CSA1_ADDR 0xfffff114
+#define CSA2_ADDR 0xfffff118
+#define CSA3_ADDR 0xfffff11c
+
+#define CSA0 LONG_REF(CSA0_ADDR)
+#define CSA1 LONG_REF(CSA1_ADDR)
+#define CSA2 LONG_REF(CSA2_ADDR)
+#define CSA3 LONG_REF(CSA3_ADDR)
+
+#define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */
+#define CSA_WAIT_SHIFT 0
+#define CSA_RO 0x00000008 /* Read-Only */
+#define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
+#define CSA_AM_SHIFT 8
+#define CSA_BUSW 0x00010000 /* Bus Width Select */
+#define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
+#define CSA_AC_SHIFT 24
+
+/*
+ * Chip-Select Option Registers (group B)
+ */
+#define CSB0_ADDR 0xfffff120
+#define CSB1_ADDR 0xfffff124
+#define CSB2_ADDR 0xfffff128
+#define CSB3_ADDR 0xfffff12c
+
+#define CSB0 LONG_REF(CSB0_ADDR)
+#define CSB1 LONG_REF(CSB1_ADDR)
+#define CSB2 LONG_REF(CSB2_ADDR)
+#define CSB3 LONG_REF(CSB3_ADDR)
+
+#define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */
+#define CSB_WAIT_SHIFT 0
+#define CSB_RO 0x00000008 /* Read-Only */
+#define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
+#define CSB_AM_SHIFT 8
+#define CSB_BUSW 0x00010000 /* Bus Width Select */
+#define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
+#define CSB_AC_SHIFT 24
+
+/*
+ * Chip-Select Option Registers (group C)
+ */
+#define CSC0_ADDR 0xfffff130
+#define CSC1_ADDR 0xfffff134
+#define CSC2_ADDR 0xfffff138
+#define CSC3_ADDR 0xfffff13c
+
+#define CSC0 LONG_REF(CSC0_ADDR)
+#define CSC1 LONG_REF(CSC1_ADDR)
+#define CSC2 LONG_REF(CSC2_ADDR)
+#define CSC3 LONG_REF(CSC3_ADDR)
+
+#define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */
+#define CSC_WAIT_SHIFT 0
+#define CSC_RO 0x00000008 /* Read-Only */
+#define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
+#define CSC_AM_SHIFT 4
+#define CSC_BUSW 0x00010000 /* Bus Width Select */
+#define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
+#define CSC_AC_SHIFT 20
+
+/*
+ * Chip-Select Option Registers (group D)
+ */
+#define CSD0_ADDR 0xfffff140
+#define CSD1_ADDR 0xfffff144
+#define CSD2_ADDR 0xfffff148
+#define CSD3_ADDR 0xfffff14c
+
+#define CSD0 LONG_REF(CSD0_ADDR)
+#define CSD1 LONG_REF(CSD1_ADDR)
+#define CSD2 LONG_REF(CSD2_ADDR)
+#define CSD3 LONG_REF(CSD3_ADDR)
+
+#define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */
+#define CSD_WAIT_SHIFT 0
+#define CSD_RO 0x00000008 /* Read-Only */
+#define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
+#define CSD_AM_SHIFT 4
+#define CSD_BUSW 0x00010000 /* Bus Width Select */
+#define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
+#define CSD_AC_SHIFT 20
+
+/**********
+ *
+ * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
+ *
+ **********/
+
+/*
+ * PLL Control Register
+ */
+#define PLLCR_ADDR 0xfffff200
+#define PLLCR WORD_REF(PLLCR_ADDR)
+
+#define PLLCR_DISPLL 0x0008 /* Disable PLL */
+#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
+#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
+#define PLLCR_SYSCLK_SEL_SHIFT 8
+#define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
+#define PLLCR_PIXCLK_SEL_SHIFT 11
+
+/* 'EZ328-compatible definitions */
+#define PLLCR_LCDCLK_SEL_MASK PLLCR_PIXCLK_SEL_MASK
+#define PLLCR_LCDCLK_SEL_SHIFT PLLCR_PIXCLK_SEL_SHIFT
+
+/*
+ * PLL Frequency Select Register
+ */
+#define PLLFSR_ADDR 0xfffff202
+#define PLLFSR WORD_REF(PLLFSR_ADDR)
+
+#define PLLFSR_PC_MASK 0x00ff /* P Count */
+#define PLLFSR_PC_SHIFT 0
+#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
+#define PLLFSR_QC_SHIFT 8
+#define PLLFSR_PROT 0x4000 /* Protect P & Q */
+#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
+
+/*
+ * Power Control Register
+ */
+#define PCTRL_ADDR 0xfffff207
+#define PCTRL BYTE_REF(PCTRL_ADDR)
+
+#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
+#define PCTRL_WIDTH_SHIFT 0
+#define PCTRL_STOP 0x40 /* Enter power-save mode immediately */
+#define PCTRL_PCEN 0x80 /* Power Control Enable */
+
+/**********
+ *
+ * 0xFFFFF3xx -- Interrupt Controller
+ *
+ **********/
+
+/*
+ * Interrupt Vector Register
+ */
+#define IVR_ADDR 0xfffff300
+#define IVR BYTE_REF(IVR_ADDR)
+
+#define IVR_VECTOR_MASK 0xF8
+
+/*
+ * Interrupt control Register
+ */
+#define ICR_ADRR 0xfffff302
+#define ICR WORD_REF(ICR_ADDR)
+
+#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
+#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
+#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
+#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
+#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
+#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
+#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
+#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
+
+/*
+ * Interrupt Mask Register
+ */
+#define IMR_ADDR 0xfffff304
+#define IMR LONG_REF(IMR_ADDR)
+
+/*
+ * Define the names for bit positions first. This is useful for
+ * request_irq
+ */
+#define SPIM_IRQ_NUM 0 /* SPI Master interrupt */
+#define TMR2_IRQ_NUM 1 /* Timer 2 interrupt */
+#define UART_IRQ_NUM 2 /* UART interrupt */
+#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
+#define RTC_IRQ_NUM 4 /* RTC interrupt */
+#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
+#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
+#define INT0_IRQ_NUM 8 /* External INT0 */
+#define INT1_IRQ_NUM 9 /* External INT1 */
+#define INT2_IRQ_NUM 10 /* External INT2 */
+#define INT3_IRQ_NUM 11 /* External INT3 */
+#define INT4_IRQ_NUM 12 /* External INT4 */
+#define INT5_IRQ_NUM 13 /* External INT5 */
+#define INT6_IRQ_NUM 14 /* External INT6 */
+#define INT7_IRQ_NUM 15 /* External INT7 */
+#define IRQ1_IRQ_NUM 16 /* IRQ1 */
+#define IRQ2_IRQ_NUM 17 /* IRQ2 */
+#define IRQ3_IRQ_NUM 18 /* IRQ3 */
+#define IRQ6_IRQ_NUM 19 /* IRQ6 */
+#define PEN_IRQ_NUM 20 /* Pen Interrupt */
+#define SPIS_IRQ_NUM 21 /* SPI Slave Interrupt */
+#define TMR1_IRQ_NUM 22 /* Timer 1 interrupt */
+#define IRQ7_IRQ_NUM 23 /* IRQ7 */
+
+/* '328-compatible definitions */
+#define SPI_IRQ_NUM SPIM_IRQ_NUM
+#define TMR_IRQ_NUM TMR1_IRQ_NUM
+
+/*
+ * Here go the bitmasks themselves
+ */
+#define IMR_MSPIM (1 << SPIM_IRQ_NUM) /* Mask SPI Master interrupt */
+#define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */
+#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
+#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
+#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
+#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
+#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
+#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
+#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
+#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
+#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
+#define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */
+#define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */
+#define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */
+#define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */
+#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
+#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
+#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
+#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
+#define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */
+#define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */
+#define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */
+#define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */
+
+/* 'EZ328-compatible definitions */
+#define IMR_MSPI IMR_MSPIM
+#define IMR_MTMR IMR_MTMR1
+
+/*
+ * Interrupt Wake-Up Enable Register
+ */
+#define IWR_ADDR 0xfffff308
+#define IWR LONG_REF(IWR_ADDR)
+
+#define IWR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */
+#define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
+#define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define IWR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define IWR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
+#define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define IWR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define IWR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define IWR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define IWR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
+#define IWR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
+#define IWR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
+#define IWR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
+#define IWR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define IWR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define IWR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define IWR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define IWR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
+#define IWR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
+#define IWR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
+#define IWR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
+
+/*
+ * Interrupt Status Register
+ */
+#define ISR_ADDR 0xfffff30c
+#define ISR LONG_REF(ISR_ADDR)
+
+#define ISR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */
+#define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
+#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
+#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define ISR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
+#define ISR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
+#define ISR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
+#define ISR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
+#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define ISR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
+#define ISR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
+#define ISR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
+#define ISR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
+
+/* 'EZ328-compatible definitions */
+#define ISR_SPI ISR_SPIM
+#define ISR_TMR ISR_TMR1
+
+/*
+ * Interrupt Pending Register
+ */
+#define IPR_ADDR 0xfffff310
+#define IPR LONG_REF(IPR_ADDR)
+
+#define IPR_SPIM (1 << SPIM_IRQ_NUM) /* SPI Master interrupt */
+#define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
+#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
+#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define IPR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
+#define IPR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
+#define IPR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
+#define IPR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
+#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define IPR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
+#define IPR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
+#define IPR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
+#define IPR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
+
+/* 'EZ328-compatible definitions */
+#define IPR_SPI IPR_SPIM
+#define IPR_TMR IPR_TMR1
+
+/**********
+ *
+ * 0xFFFFF4xx -- Parallel Ports
+ *
+ **********/
+
+/*
+ * Port A
+ */
+#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
+#define PADATA_ADDR 0xfffff401 /* Port A data register */
+#define PASEL_ADDR 0xfffff403 /* Port A Select register */
+
+#define PADIR BYTE_REF(PADIR_ADDR)
+#define PADATA BYTE_REF(PADATA_ADDR)
+#define PASEL BYTE_REF(PASEL_ADDR)
+
+#define PA(x) (1 << (x))
+#define PA_A(x) PA((x) - 16) /* This is specific to PA only! */
+
+#define PA_A16 PA(0) /* Use A16 as PA(0) */
+#define PA_A17 PA(1) /* Use A17 as PA(1) */
+#define PA_A18 PA(2) /* Use A18 as PA(2) */
+#define PA_A19 PA(3) /* Use A19 as PA(3) */
+#define PA_A20 PA(4) /* Use A20 as PA(4) */
+#define PA_A21 PA(5) /* Use A21 as PA(5) */
+#define PA_A22 PA(6) /* Use A22 as PA(6) */
+#define PA_A23 PA(7) /* Use A23 as PA(7) */
+
+/*
+ * Port B
+ */
+#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
+#define PBDATA_ADDR 0xfffff409 /* Port B data register */
+#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
+
+#define PBDIR BYTE_REF(PBDIR_ADDR)
+#define PBDATA BYTE_REF(PBDATA_ADDR)
+#define PBSEL BYTE_REF(PBSEL_ADDR)
+
+#define PB(x) (1 << (x))
+#define PB_D(x) PB(x) /* This is specific to port B only */
+
+#define PB_D0 PB(0) /* Use D0 as PB(0) */
+#define PB_D1 PB(1) /* Use D1 as PB(1) */
+#define PB_D2 PB(2) /* Use D2 as PB(2) */
+#define PB_D3 PB(3) /* Use D3 as PB(3) */
+#define PB_D4 PB(4) /* Use D4 as PB(4) */
+#define PB_D5 PB(5) /* Use D5 as PB(5) */
+#define PB_D6 PB(6) /* Use D6 as PB(6) */
+#define PB_D7 PB(7) /* Use D7 as PB(7) */
+
+/*
+ * Port C
+ */
+#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
+#define PCDATA_ADDR 0xfffff411 /* Port C data register */
+#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
+
+#define PCDIR BYTE_REF(PCDIR_ADDR)
+#define PCDATA BYTE_REF(PCDATA_ADDR)
+#define PCSEL BYTE_REF(PCSEL_ADDR)
+
+#define PC(x) (1 << (x))
+
+#define PC_WE PC(6) /* Use WE as PC(6) */
+#define PC_DTACK PC(5) /* Use DTACK as PC(5) */
+#define PC_IRQ7 PC(4) /* Use IRQ7 as PC(4) */
+#define PC_LDS PC(2) /* Use LDS as PC(2) */
+#define PC_UDS PC(1) /* Use UDS as PC(1) */
+#define PC_MOCLK PC(0) /* Use MOCLK as PC(0) */
+
+/*
+ * Port D
+ */
+#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
+#define PDDATA_ADDR 0xfffff419 /* Port D data register */
+#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
+#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
+#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
+#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
+
+#define PDDIR BYTE_REF(PDDIR_ADDR)
+#define PDDATA BYTE_REF(PDDATA_ADDR)
+#define PDPUEN BYTE_REF(PDPUEN_ADDR)
+#define PDPOL BYTE_REF(PDPOL_ADDR)
+#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
+#define PDIQEG BYTE_REF(PDIQEG_ADDR)
+
+#define PD(x) (1 << (x))
+#define PD_KB(x) PD(x) /* This is specific for Port D only */
+
+#define PD_KB0 PD(0) /* Use KB0 as PD(0) */
+#define PD_KB1 PD(1) /* Use KB1 as PD(1) */
+#define PD_KB2 PD(2) /* Use KB2 as PD(2) */
+#define PD_KB3 PD(3) /* Use KB3 as PD(3) */
+#define PD_KB4 PD(4) /* Use KB4 as PD(4) */
+#define PD_KB5 PD(5) /* Use KB5 as PD(5) */
+#define PD_KB6 PD(6) /* Use KB6 as PD(6) */
+#define PD_KB7 PD(7) /* Use KB7 as PD(7) */
+
+/*
+ * Port E
+ */
+#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
+#define PEDATA_ADDR 0xfffff421 /* Port E data register */
+#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
+#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
+
+#define PEDIR BYTE_REF(PEDIR_ADDR)
+#define PEDATA BYTE_REF(PEDATA_ADDR)
+#define PEPUEN BYTE_REF(PEPUEN_ADDR)
+#define PESEL BYTE_REF(PESEL_ADDR)
+
+#define PE(x) (1 << (x))
+
+#define PE_CSA1 PE(1) /* Use CSA1 as PE(1) */
+#define PE_CSA2 PE(2) /* Use CSA2 as PE(2) */
+#define PE_CSA3 PE(3) /* Use CSA3 as PE(3) */
+#define PE_CSB0 PE(4) /* Use CSB0 as PE(4) */
+#define PE_CSB1 PE(5) /* Use CSB1 as PE(5) */
+#define PE_CSB2 PE(6) /* Use CSB2 as PE(6) */
+#define PE_CSB3 PE(7) /* Use CSB3 as PE(7) */
+
+/*
+ * Port F
+ */
+#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
+#define PFDATA_ADDR 0xfffff429 /* Port F data register */
+#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
+#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
+
+#define PFDIR BYTE_REF(PFDIR_ADDR)
+#define PFDATA BYTE_REF(PFDATA_ADDR)
+#define PFPUEN BYTE_REF(PFPUEN_ADDR)
+#define PFSEL BYTE_REF(PFSEL_ADDR)
+
+#define PF(x) (1 << (x))
+#define PF_A(x) PF((x) - 24) /* This is Port F specific only */
+
+#define PF_A24 PF(0) /* Use A24 as PF(0) */
+#define PF_A25 PF(1) /* Use A25 as PF(1) */
+#define PF_A26 PF(2) /* Use A26 as PF(2) */
+#define PF_A27 PF(3) /* Use A27 as PF(3) */
+#define PF_A28 PF(4) /* Use A28 as PF(4) */
+#define PF_A29 PF(5) /* Use A29 as PF(5) */
+#define PF_A30 PF(6) /* Use A30 as PF(6) */
+#define PF_A31 PF(7) /* Use A31 as PF(7) */
+
+/*
+ * Port G
+ */
+#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
+#define PGDATA_ADDR 0xfffff431 /* Port G data register */
+#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
+#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
+
+#define PGDIR BYTE_REF(PGDIR_ADDR)
+#define PGDATA BYTE_REF(PGDATA_ADDR)
+#define PGPUEN BYTE_REF(PGPUEN_ADDR)
+#define PGSEL BYTE_REF(PGSEL_ADDR)
+
+#define PG(x) (1 << (x))
+
+#define PG_UART_TXD PG(0) /* Use UART_TXD as PG(0) */
+#define PG_UART_RXD PG(1) /* Use UART_RXD as PG(1) */
+#define PG_PWMOUT PG(2) /* Use PWMOUT as PG(2) */
+#define PG_TOUT2 PG(3) /* Use TOUT2 as PG(3) */
+#define PG_TIN2 PG(4) /* Use TIN2 as PG(4) */
+#define PG_TOUT1 PG(5) /* Use TOUT1 as PG(5) */
+#define PG_TIN1 PG(6) /* Use TIN1 as PG(6) */
+#define PG_RTCOUT PG(7) /* Use RTCOUT as PG(7) */
+
+/*
+ * Port J
+ */
+#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
+#define PJDATA_ADDR 0xfffff439 /* Port J data register */
+#define PJSEL_ADDR 0xfffff43b /* Port J Select Register */
+
+#define PJDIR BYTE_REF(PJDIR_ADDR)
+#define PJDATA BYTE_REF(PJDATA_ADDR)
+#define PJSEL BYTE_REF(PJSEL_ADDR)
+
+#define PJ(x) (1 << (x))
+
+#define PJ_CSD3 PJ(7) /* Use CSD3 as PJ(7) */
+
+/*
+ * Port K
+ */
+#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
+#define PKDATA_ADDR 0xfffff441 /* Port K data register */
+#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */
+#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
+
+#define PKDIR BYTE_REF(PKDIR_ADDR)
+#define PKDATA BYTE_REF(PKDATA_ADDR)
+#define PKPUEN BYTE_REF(PKPUEN_ADDR)
+#define PKSEL BYTE_REF(PKSEL_ADDR)
+
+#define PK(x) (1 << (x))
+
+/*
+ * Port M
+ */
+#define PMDIR_ADDR 0xfffff438 /* Port M direction reg */
+#define PMDATA_ADDR 0xfffff439 /* Port M data register */
+#define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */
+#define PMSEL_ADDR 0xfffff43b /* Port M Select Register */
+
+#define PMDIR BYTE_REF(PMDIR_ADDR)
+#define PMDATA BYTE_REF(PMDATA_ADDR)
+#define PMPUEN BYTE_REF(PMPUEN_ADDR)
+#define PMSEL BYTE_REF(PMSEL_ADDR)
+
+#define PM(x) (1 << (x))
+
+/**********
+ *
+ * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
+ *
+ **********/
+
+/*
+ * PWM Control Register
+ */
+#define PWMC_ADDR 0xfffff500
+#define PWMC WORD_REF(PWMC_ADDR)
+
+#define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */
+#define PWMC_CLKSEL_SHIFT 0
+#define PWMC_PWMEN 0x0010 /* Enable PWM */
+#define PMNC_POL 0x0020 /* PWM Output Bit Polarity */
+#define PWMC_PIN 0x0080 /* Current PWM output pin status */
+#define PWMC_LOAD 0x0100 /* Force a new period */
+#define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */
+#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
+
+/* 'EZ328-compatible definitions */
+#define PWMC_EN PWMC_PWMEN
+
+/*
+ * PWM Period Register
+ */
+#define PWMP_ADDR 0xfffff502
+#define PWMP WORD_REF(PWMP_ADDR)
+
+/*
+ * PWM Width Register
+ */
+#define PWMW_ADDR 0xfffff504
+#define PWMW WORD_REF(PWMW_ADDR)
+
+/*
+ * PWM Counter Register
+ */
+#define PWMCNT_ADDR 0xfffff506
+#define PWMCNT WORD_REF(PWMCNT_ADDR)
+
+/**********
+ *
+ * 0xFFFFF6xx -- General-Purpose Timers
+ *
+ **********/
+
+/*
+ * Timer Unit 1 and 2 Control Registers
+ */
+#define TCTL1_ADDR 0xfffff600
+#define TCTL1 WORD_REF(TCTL1_ADDR)
+#define TCTL2_ADDR 0xfffff60c
+#define TCTL2 WORD_REF(TCTL2_ADDR)
+
+#define TCTL_TEN 0x0001 /* Timer Enable */
+#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
+#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
+#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
+#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
+#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
+#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
+#define TCTL_IRQEN 0x0010 /* IRQ Enable */
+#define TCTL_OM 0x0020 /* Output Mode */
+#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
+#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
+#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
+#define TCTL_FRR 0x0010 /* Free-Run Mode */
+
+/* 'EZ328-compatible definitions */
+#define TCTL_ADDR TCTL1_ADDR
+#define TCTL TCTL1
+
+/*
+ * Timer Unit 1 and 2 Prescaler Registers
+ */
+#define TPRER1_ADDR 0xfffff602
+#define TPRER1 WORD_REF(TPRER1_ADDR)
+#define TPRER2_ADDR 0xfffff60e
+#define TPRER2 WORD_REF(TPRER2_ADDR)
+
+/* 'EZ328-compatible definitions */
+#define TPRER_ADDR TPRER1_ADDR
+#define TPRER TPRER1
+
+/*
+ * Timer Unit 1 and 2 Compare Registers
+ */
+#define TCMP1_ADDR 0xfffff604
+#define TCMP1 WORD_REF(TCMP1_ADDR)
+#define TCMP2_ADDR 0xfffff610
+#define TCMP2 WORD_REF(TCMP2_ADDR)
+
+/* 'EZ328-compatible definitions */
+#define TCMP_ADDR TCMP1_ADDR
+#define TCMP TCMP1
+
+/*
+ * Timer Unit 1 and 2 Capture Registers
+ */
+#define TCR1_ADDR 0xfffff606
+#define TCR1 WORD_REF(TCR1_ADDR)
+#define TCR2_ADDR 0xfffff612
+#define TCR2 WORD_REF(TCR2_ADDR)
+
+/* 'EZ328-compatible definitions */
+#define TCR_ADDR TCR1_ADDR
+#define TCR TCR1
+
+/*
+ * Timer Unit 1 and 2 Counter Registers
+ */
+#define TCN1_ADDR 0xfffff608
+#define TCN1 WORD_REF(TCN1_ADDR)
+#define TCN2_ADDR 0xfffff614
+#define TCN2 WORD_REF(TCN2_ADDR)
+
+/* 'EZ328-compatible definitions */
+#define TCN_ADDR TCN1_ADDR
+#define TCN TCN1
+
+/*
+ * Timer Unit 1 and 2 Status Registers
+ */
+#define TSTAT1_ADDR 0xfffff60a
+#define TSTAT1 WORD_REF(TSTAT1_ADDR)
+#define TSTAT2_ADDR 0xfffff616
+#define TSTAT2 WORD_REF(TSTAT2_ADDR)
+
+#define TSTAT_COMP 0x0001 /* Compare Event occurred */
+#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
+
+/* 'EZ328-compatible definitions */
+#define TSTAT_ADDR TSTAT1_ADDR
+#define TSTAT TSTAT1
+
+/*
+ * Watchdog Compare Register
+ */
+#define WRR_ADDR 0xfffff61a
+#define WRR WORD_REF(WRR_ADDR)
+
+/*
+ * Watchdog Counter Register
+ */
+#define WCN_ADDR 0xfffff61c
+#define WCN WORD_REF(WCN_ADDR)
+
+/*
+ * Watchdog Control and Status Register
+ */
+#define WCSR_ADDR 0xfffff618
+#define WCSR WORD_REF(WCSR_ADDR)
+
+#define WCSR_WDEN 0x0001 /* Watchdog Enable */
+#define WCSR_FI 0x0002 /* Forced Interrupt (instead of SW reset)*/
+#define WCSR_WRST 0x0004 /* Watchdog Reset */
+
+/**********
+ *
+ * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
+ *
+ **********/
+
+/*
+ * SPI Slave Register
+ */
+#define SPISR_ADDR 0xfffff700
+#define SPISR WORD_REF(SPISR_ADDR)
+
+#define SPISR_DATA_ADDR 0xfffff701
+#define SPISR_DATA BYTE_REF(SPISR_DATA_ADDR)
+
+#define SPISR_DATA_MASK 0x00ff /* Shifted data from the external device */
+#define SPISR_DATA_SHIFT 0
+#define SPISR_SPISEN 0x0100 /* SPIS module enable */
+#define SPISR_POL 0x0200 /* SPSCLK polarity control */
+#define SPISR_PHA 0x0400 /* Phase relationship between SPSCLK & SPSRxD */
+#define SPISR_OVWR 0x0800 /* Data buffer has been overwritten */
+#define SPISR_DATARDY 0x1000 /* Data ready */
+#define SPISR_ENPOL 0x2000 /* Enable Polarity */
+#define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */
+#define SPISR_SPISIRQ 0x8000 /* SPIS IRQ posted */
+
+/**********
+ *
+ * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
+ *
+ **********/
+
+/*
+ * SPIM Data Register
+ */
+#define SPIMDATA_ADDR 0xfffff800
+#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
+
+/*
+ * SPIM Control/Status Register
+ */
+#define SPIMCONT_ADDR 0xfffff802
+#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
+
+#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
+#define SPIMCONT_BIT_COUNT_SHIFT 0
+#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
+#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
+#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
+#define SPIMCONT_SPIMIRQ 0x0080 /* Interrupt Request */
+#define SPIMCONT_XCH 0x0100 /* Exchange */
+#define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */
+#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
+#define SPIMCONT_DATA_RATE_SHIFT 13
+
+/* 'EZ328-compatible definitions */
+#define SPIMCONT_IRQ SPIMCONT_SPIMIRQ
+#define SPIMCONT_ENABLE SPIMCONT_SPIMEN
+/**********
+ *
+ * 0xFFFFF9xx -- UART
+ *
+ **********/
+
+/*
+ * UART Status/Control Register
+ */
+#define USTCNT_ADDR 0xfffff900
+#define USTCNT WORD_REF(USTCNT_ADDR)
+
+#define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */
+#define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */
+#define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */
+#define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */
+#define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */
+#define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */
+#define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */
+#define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */
+#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
+#define USTCNT_STOP 0x0200 /* Stop bit transmission */
+#define USTCNT_ODD_EVEN 0x0400 /* Odd Parity */
+#define USTCNT_PARITYEN 0x0800 /* Parity Enable */
+#define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */
+#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
+#define USTCNT_RXEN 0x4000 /* Receiver Enable */
+#define USTCNT_UARTEN 0x8000 /* UART Enable */
+
+/* 'EZ328-compatible definitions */
+#define USTCNT_TXAE USTCNT_TXAVAILEN
+#define USTCNT_TXHE USTCNT_TXHALFEN
+#define USTCNT_TXEE USTCNT_TXEMPTYEN
+#define USTCNT_RXRE USTCNT_RXREADYEN
+#define USTCNT_RXHE USTCNT_RXHALFEN
+#define USTCNT_RXFE USTCNT_RXFULLEN
+#define USTCNT_CTSD USTCNT_CTSDELTAEN
+#define USTCNT_ODD USTCNT_ODD_EVEN
+#define USTCNT_PEN USTCNT_PARITYEN
+#define USTCNT_CLKM USTCNT_CLKMODE
+#define USTCNT_UEN USTCNT_UARTEN
+
+/*
+ * UART Baud Control Register
+ */
+#define UBAUD_ADDR 0xfffff902
+#define UBAUD WORD_REF(UBAUD_ADDR)
+
+#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
+#define UBAUD_PRESCALER_SHIFT 0
+#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
+#define UBAUD_DIVIDE_SHIFT 8
+#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
+#define UBAUD_GPIOSRC 0x1000 /* GPIO source */
+#define UBAUD_GPIODIR 0x2000 /* GPIO Direction */
+#define UBAUD_GPIO 0x4000 /* Current GPIO pin status */
+#define UBAUD_GPIODELTA 0x8000 /* GPIO pin value changed */
+
+/*
+ * UART Receiver Register
+ */
+#define URX_ADDR 0xfffff904
+#define URX WORD_REF(URX_ADDR)
+
+#define URX_RXDATA_ADDR 0xfffff905
+#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
+
+#define URX_RXDATA_MASK 0x00ff /* Received data */
+#define URX_RXDATA_SHIFT 0
+#define URX_PARITY_ERROR 0x0100 /* Parity Error */
+#define URX_BREAK 0x0200 /* Break Detected */
+#define URX_FRAME_ERROR 0x0400 /* Framing Error */
+#define URX_OVRUN 0x0800 /* Serial Overrun */
+#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
+#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
+#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
+
+/*
+ * UART Transmitter Register
+ */
+#define UTX_ADDR 0xfffff906
+#define UTX WORD_REF(UTX_ADDR)
+
+#define UTX_TXDATA_ADDR 0xfffff907
+#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
+
+#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
+#define UTX_TXDATA_SHIFT 0
+#define UTX_CTS_DELTA 0x0100 /* CTS changed */
+#define UTX_CTS_STATUS 0x0200 /* CTS State */
+#define UTX_IGNORE_CTS 0x0800 /* Ignore CTS */
+#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
+#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
+#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
+#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
+
+/* 'EZ328-compatible definitions */
+#define UTX_CTS_STAT UTX_CTS_STATUS
+#define UTX_NOCTS UTX_IGNORE_CTS
+
+/*
+ * UART Miscellaneous Register
+ */
+#define UMISC_ADDR 0xfffff908
+#define UMISC WORD_REF(UMISC_ADDR)
+
+#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
+#define UMISC_RX_POL 0x0008 /* Receive Polarity */
+#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
+#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
+#define UMISC_RTS 0x0040 /* Set RTS status */
+#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
+#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
+#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
+#define UMISC_CLKSRC 0x4000 /* Clock Source */
+
+
+/* generalization of uart control registers to support multiple ports: */
+typedef volatile struct {
+ volatile unsigned short int ustcnt;
+ volatile unsigned short int ubaud;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char rxdata;
+ } b;
+ } urx;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char txdata;
+ } b;
+ } utx;
+ volatile unsigned short int umisc;
+ volatile unsigned short int pad1;
+ volatile unsigned short int pad2;
+ volatile unsigned short int pad3;
+} __packed m68328_uart;
+
+
+/**********
+ *
+ * 0xFFFFFAxx -- LCD Controller
+ *
+ **********/
+
+/*
+ * LCD Screen Starting Address Register
+ */
+#define LSSA_ADDR 0xfffffa00
+#define LSSA LONG_REF(LSSA_ADDR)
+
+#define LSSA_SSA_MASK 0xfffffffe /* Bit 0 is reserved */
+
+/*
+ * LCD Virtual Page Width Register
+ */
+#define LVPW_ADDR 0xfffffa05
+#define LVPW BYTE_REF(LVPW_ADDR)
+
+/*
+ * LCD Screen Width Register (not compatible with 'EZ328 !!!)
+ */
+#define LXMAX_ADDR 0xfffffa08
+#define LXMAX WORD_REF(LXMAX_ADDR)
+
+#define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */
+
+/*
+ * LCD Screen Height Register
+ */
+#define LYMAX_ADDR 0xfffffa0a
+#define LYMAX WORD_REF(LYMAX_ADDR)
+
+#define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */
+
+/*
+ * LCD Cursor X Position Register
+ */
+#define LCXP_ADDR 0xfffffa18
+#define LCXP WORD_REF(LCXP_ADDR)
+
+#define LCXP_CC_MASK 0xc000 /* Cursor Control */
+#define LCXP_CC_TRAMSPARENT 0x0000
+#define LCXP_CC_BLACK 0x4000
+#define LCXP_CC_REVERSED 0x8000
+#define LCXP_CC_WHITE 0xc000
+#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
+
+/*
+ * LCD Cursor Y Position Register
+ */
+#define LCYP_ADDR 0xfffffa1a
+#define LCYP WORD_REF(LCYP_ADDR)
+
+#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
+
+/*
+ * LCD Cursor Width and Heigth Register
+ */
+#define LCWCH_ADDR 0xfffffa1c
+#define LCWCH WORD_REF(LCWCH_ADDR)
+
+#define LCWCH_CH_MASK 0x001f /* Cursor Height */
+#define LCWCH_CH_SHIFT 0
+#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
+#define LCWCH_CW_SHIFT 8
+
+/*
+ * LCD Blink Control Register
+ */
+#define LBLKC_ADDR 0xfffffa1f
+#define LBLKC BYTE_REF(LBLKC_ADDR)
+
+#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
+#define LBLKC_BD_SHIFT 0
+#define LBLKC_BKEN 0x80 /* Blink Enabled */
+
+/*
+ * LCD Panel Interface Configuration Register
+ */
+#define LPICF_ADDR 0xfffffa20
+#define LPICF BYTE_REF(LPICF_ADDR)
+
+#define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */
+#define LPICF_GS_BW 0x00
+#define LPICF_GS_GRAY_4 0x01
+#define LPICF_PBSIZ_MASK 0x06 /* Panel Bus Width */
+#define LPICF_PBSIZ_1 0x00
+#define LPICF_PBSIZ_2 0x02
+#define LPICF_PBSIZ_4 0x04
+
+/*
+ * LCD Polarity Configuration Register
+ */
+#define LPOLCF_ADDR 0xfffffa21
+#define LPOLCF BYTE_REF(LPOLCF_ADDR)
+
+#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
+#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
+#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
+#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
+
+/*
+ * LACD (LCD Alternate Crystal Direction) Rate Control Register
+ */
+#define LACDRC_ADDR 0xfffffa23
+#define LACDRC BYTE_REF(LACDRC_ADDR)
+
+#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
+#define LACDRC_ACD_SHIFT 0
+
+/*
+ * LCD Pixel Clock Divider Register
+ */
+#define LPXCD_ADDR 0xfffffa25
+#define LPXCD BYTE_REF(LPXCD_ADDR)
+
+#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
+#define LPXCD_PCD_SHIFT 0
+
+/*
+ * LCD Clocking Control Register
+ */
+#define LCKCON_ADDR 0xfffffa27
+#define LCKCON BYTE_REF(LCKCON_ADDR)
+
+#define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */
+#define LCKCON_DWIDTH 0x02 /* Display Memory Width */
+#define LCKCON_DWS_MASK 0x3c /* Display Wait-State */
+#define LCKCON_DWS_SHIFT 2
+#define LCKCON_DMA16 0x40 /* DMA burst length */
+#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
+
+/* 'EZ328-compatible definitions */
+#define LCKCON_DW_MASK LCKCON_DWS_MASK
+#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
+
+/*
+ * LCD Last Buffer Address Register
+ */
+#define LLBAR_ADDR 0xfffffa29
+#define LLBAR BYTE_REF(LLBAR_ADDR)
+
+#define LLBAR_LBAR_MASK 0x7f /* Number of memory words to fill 1 line */
+#define LLBAR_LBAR_SHIFT 0
+
+/*
+ * LCD Octet Terminal Count Register
+ */
+#define LOTCR_ADDR 0xfffffa2b
+#define LOTCR BYTE_REF(LOTCR_ADDR)
+
+/*
+ * LCD Panning Offset Register
+ */
+#define LPOSR_ADDR 0xfffffa2d
+#define LPOSR BYTE_REF(LPOSR_ADDR)
+
+#define LPOSR_BOS 0x08 /* Byte offset (for B/W mode only */
+#define LPOSR_POS_MASK 0x07 /* Pixel Offset Code */
+#define LPOSR_POS_SHIFT 0
+
+/*
+ * LCD Frame Rate Control Modulation Register
+ */
+#define LFRCM_ADDR 0xfffffa31
+#define LFRCM BYTE_REF(LFRCM_ADDR)
+
+#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
+#define LFRCM_YMOD_SHIFT 0
+#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
+#define LFRCM_XMOD_SHIFT 4
+
+/*
+ * LCD Gray Palette Mapping Register
+ */
+#define LGPMR_ADDR 0xfffffa32
+#define LGPMR WORD_REF(LGPMR_ADDR)
+
+#define LGPMR_GLEVEL3_MASK 0x000f
+#define LGPMR_GLEVEL3_SHIFT 0
+#define LGPMR_GLEVEL2_MASK 0x00f0
+#define LGPMR_GLEVEL2_SHIFT 4
+#define LGPMR_GLEVEL0_MASK 0x0f00
+#define LGPMR_GLEVEL0_SHIFT 8
+#define LGPMR_GLEVEL1_MASK 0xf000
+#define LGPMR_GLEVEL1_SHIFT 12
+
+/**********
+ *
+ * 0xFFFFFBxx -- Real-Time Clock (RTC)
+ *
+ **********/
+
+/*
+ * RTC Hours Minutes and Seconds Register
+ */
+#define RTCTIME_ADDR 0xfffffb00
+#define RTCTIME LONG_REF(RTCTIME_ADDR)
+
+#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCTIME_SECONDS_SHIFT 0
+#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCTIME_MINUTES_SHIFT 16
+#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCTIME_HOURS_SHIFT 24
+
+/*
+ * RTC Alarm Register
+ */
+#define RTCALRM_ADDR 0xfffffb04
+#define RTCALRM LONG_REF(RTCALRM_ADDR)
+
+#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCALRM_SECONDS_SHIFT 0
+#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCALRM_MINUTES_SHIFT 16
+#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCALRM_HOURS_SHIFT 24
+
+/*
+ * RTC Control Register
+ */
+#define RTCCTL_ADDR 0xfffffb0c
+#define RTCCTL WORD_REF(RTCCTL_ADDR)
+
+#define RTCCTL_384 0x0020 /* Crystal Selection */
+#define RTCCTL_ENABLE 0x0080 /* RTC Enable */
+
+/* 'EZ328-compatible definitions */
+#define RTCCTL_XTL RTCCTL_384
+#define RTCCTL_EN RTCCTL_ENABLE
+
+/*
+ * RTC Interrupt Status Register
+ */
+#define RTCISR_ADDR 0xfffffb0e
+#define RTCISR WORD_REF(RTCISR_ADDR)
+
+#define RTCISR_SW 0x0001 /* Stopwatch timed out */
+#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
+#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
+#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
+#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
+
+/*
+ * RTC Interrupt Enable Register
+ */
+#define RTCIENR_ADDR 0xfffffb10
+#define RTCIENR WORD_REF(RTCIENR_ADDR)
+
+#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
+#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
+#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
+#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
+#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
+
+/*
+ * Stopwatch Minutes Register
+ */
+#define STPWCH_ADDR 0xfffffb12
+#define STPWCH WORD_REF(STPWCH)
+
+#define STPWCH_CNT_MASK 0x00ff /* Stopwatch countdown value */
+#define SPTWCH_CNT_SHIFT 0
+
+#endif /* _MC68328_H_ */
diff --git a/arch/m68k/include/asm/MC68EZ328.h b/arch/m68k/include/asm/MC68EZ328.h
new file mode 100644
index 0000000..c50b9f6
--- /dev/null
+++ b/arch/m68k/include/asm/MC68EZ328.h
@@ -0,0 +1,1255 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
+ *
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ * Bear & Hare Software, Inc.
+ *
+ * Based on include/asm-m68knommu/MC68332.h
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
+ * The Silver Hammer Group, Ltd.
+ *
+ */
+#include <linux/compiler.h>
+
+#ifndef _MC68EZ328_H_
+#define _MC68EZ328_H_
+
+#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
+#define WORD_REF(addr) (*((volatile unsigned short*)addr))
+#define LONG_REF(addr) (*((volatile unsigned long*)addr))
+
+#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
+#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
+
+/**********
+ *
+ * 0xFFFFF0xx -- System Control
+ *
+ **********/
+
+/*
+ * System Control Register (SCR)
+ */
+#define SCR_ADDR 0xfffff000
+#define SCR BYTE_REF(SCR_ADDR)
+
+#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
+#define SCR_DMAP 0x04 /* Double Map */
+#define SCR_SO 0x08 /* Supervisor Only */
+#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
+#define SCR_PRV 0x20 /* Privilege Violation */
+#define SCR_WPV 0x40 /* Write Protect Violation */
+#define SCR_BETO 0x80 /* Bus-Error TimeOut */
+
+/*
+ * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
+ */
+#define MRR_ADDR 0xfffff004
+#define MRR LONG_REF(MRR_ADDR)
+
+/**********
+ *
+ * 0xFFFFF1xx -- Chip-Select logic
+ *
+ **********/
+
+/*
+ * Chip Select Group Base Registers
+ */
+#define CSGBA_ADDR 0xfffff100
+#define CSGBB_ADDR 0xfffff102
+
+#define CSGBC_ADDR 0xfffff104
+#define CSGBD_ADDR 0xfffff106
+
+#define CSGBA WORD_REF(CSGBA_ADDR)
+#define CSGBB WORD_REF(CSGBB_ADDR)
+#define CSGBC WORD_REF(CSGBC_ADDR)
+#define CSGBD WORD_REF(CSGBD_ADDR)
+
+/*
+ * Chip Select Registers
+ */
+#define CSA_ADDR 0xfffff110
+#define CSB_ADDR 0xfffff112
+#define CSC_ADDR 0xfffff114
+#define CSD_ADDR 0xfffff116
+
+#define CSA WORD_REF(CSA_ADDR)
+#define CSB WORD_REF(CSB_ADDR)
+#define CSC WORD_REF(CSC_ADDR)
+#define CSD WORD_REF(CSD_ADDR)
+
+#define CSA_EN 0x0001 /* Chip-Select Enable */
+#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSA_SIZ_SHIFT 1
+#define CSA_WS_MASK 0x0070 /* Wait State */
+#define CSA_WS_SHIFT 4
+#define CSA_BSW 0x0080 /* Data Bus Width */
+#define CSA_FLASH 0x0100 /* FLASH Memory Support */
+#define CSA_RO 0x8000 /* Read-Only */
+
+#define CSB_EN 0x0001 /* Chip-Select Enable */
+#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSB_SIZ_SHIFT 1
+#define CSB_WS_MASK 0x0070 /* Wait State */
+#define CSB_WS_SHIFT 4
+#define CSB_BSW 0x0080 /* Data Bus Width */
+#define CSB_FLASH 0x0100 /* FLASH Memory Support */
+#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSB_UPSIZ_SHIFT 11
+#define CSB_ROP 0x2000 /* Readonly if protected */
+#define CSB_SOP 0x4000 /* Supervisor only if protected */
+#define CSB_RO 0x8000 /* Read-Only */
+
+#define CSC_EN 0x0001 /* Chip-Select Enable */
+#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSC_SIZ_SHIFT 1
+#define CSC_WS_MASK 0x0070 /* Wait State */
+#define CSC_WS_SHIFT 4
+#define CSC_BSW 0x0080 /* Data Bus Width */
+#define CSC_FLASH 0x0100 /* FLASH Memory Support */
+#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSC_UPSIZ_SHIFT 11
+#define CSC_ROP 0x2000 /* Readonly if protected */
+#define CSC_SOP 0x4000 /* Supervisor only if protected */
+#define CSC_RO 0x8000 /* Read-Only */
+
+#define CSD_EN 0x0001 /* Chip-Select Enable */
+#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSD_SIZ_SHIFT 1
+#define CSD_WS_MASK 0x0070 /* Wait State */
+#define CSD_WS_SHIFT 4
+#define CSD_BSW 0x0080 /* Data Bus Width */
+#define CSD_FLASH 0x0100 /* FLASH Memory Support */
+#define CSD_DRAM 0x0200 /* Dram Selection */
+#define CSD_COMB 0x0400 /* Combining */
+#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSD_UPSIZ_SHIFT 11
+#define CSD_ROP 0x2000 /* Readonly if protected */
+#define CSD_SOP 0x4000 /* Supervisor only if protected */
+#define CSD_RO 0x8000 /* Read-Only */
+
+/*
+ * Emulation Chip-Select Register
+ */
+#define EMUCS_ADDR 0xfffff118
+#define EMUCS WORD_REF(EMUCS_ADDR)
+
+#define EMUCS_WS_MASK 0x0070
+#define EMUCS_WS_SHIFT 4
+
+/**********
+ *
+ * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
+ *
+ **********/
+
+/*
+ * PLL Control Register
+ */
+#define PLLCR_ADDR 0xfffff200
+#define PLLCR WORD_REF(PLLCR_ADDR)
+
+#define PLLCR_DISPLL 0x0008 /* Disable PLL */
+#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
+#define PLLCR_PRESC 0x0020 /* VCO prescaler */
+#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
+#define PLLCR_SYSCLK_SEL_SHIFT 8
+#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
+#define PLLCR_LCDCLK_SEL_SHIFT 11
+
+/* '328-compatible definitions */
+#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
+#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
+
+/*
+ * PLL Frequency Select Register
+ */
+#define PLLFSR_ADDR 0xfffff202
+#define PLLFSR WORD_REF(PLLFSR_ADDR)
+
+#define PLLFSR_PC_MASK 0x00ff /* P Count */
+#define PLLFSR_PC_SHIFT 0
+#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
+#define PLLFSR_QC_SHIFT 8
+#define PLLFSR_PROT 0x4000 /* Protect P & Q */
+#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
+
+/*
+ * Power Control Register
+ */
+#define PCTRL_ADDR 0xfffff207
+#define PCTRL BYTE_REF(PCTRL_ADDR)
+
+#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
+#define PCTRL_WIDTH_SHIFT 0
+#define PCTRL_PCEN 0x80 /* Power Control Enable */
+
+/**********
+ *
+ * 0xFFFFF3xx -- Interrupt Controller
+ *
+ **********/
+
+/*
+ * Interrupt Vector Register
+ */
+#define IVR_ADDR 0xfffff300
+#define IVR BYTE_REF(IVR_ADDR)
+
+#define IVR_VECTOR_MASK 0xF8
+
+/*
+ * Interrupt control Register
+ */
+#define ICR_ADDR 0xfffff302
+#define ICR WORD_REF(ICR_ADDR)
+
+#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
+#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
+#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
+#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
+#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
+#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
+#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
+#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
+#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
+
+/*
+ * Interrupt Mask Register
+ */
+#define IMR_ADDR 0xfffff304
+#define IMR LONG_REF(IMR_ADDR)
+
+/*
+ * Define the names for bit positions first. This is useful for
+ * request_irq
+ */
+#define SPI_IRQ_NUM 0 /* SPI interrupt */
+#define TMR_IRQ_NUM 1 /* Timer interrupt */
+#define UART_IRQ_NUM 2 /* UART interrupt */
+#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
+#define RTC_IRQ_NUM 4 /* RTC interrupt */
+#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
+#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
+#define INT0_IRQ_NUM 8 /* External INT0 */
+#define INT1_IRQ_NUM 9 /* External INT1 */
+#define INT2_IRQ_NUM 10 /* External INT2 */
+#define INT3_IRQ_NUM 11 /* External INT3 */
+#define IRQ1_IRQ_NUM 16 /* IRQ1 */
+#define IRQ2_IRQ_NUM 17 /* IRQ2 */
+#define IRQ3_IRQ_NUM 18 /* IRQ3 */
+#define IRQ6_IRQ_NUM 19 /* IRQ6 */
+#define IRQ5_IRQ_NUM 20 /* IRQ5 */
+#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
+#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define SPIM_IRQ_NUM SPI_IRQ_NUM
+#define TMR1_IRQ_NUM TMR_IRQ_NUM
+
+/*
+ * Here go the bitmasks themselves
+ */
+#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
+#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
+#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
+#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
+#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
+#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
+#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
+#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
+#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
+#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
+#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
+#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
+#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
+#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
+#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
+#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
+#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
+#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define IMR_MSPIM IMR_MSPI
+#define IMR_MTMR1 IMR_MTMR
+
+/*
+ * Interrupt Status Register
+ */
+#define ISR_ADDR 0xfffff30c
+#define ISR LONG_REF(ISR_ADDR)
+
+#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
+#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
+#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
+#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
+#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
+#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define ISR_SPIM ISR_SPI
+#define ISR_TMR1 ISR_TMR
+
+/*
+ * Interrupt Pending Register
+ */
+#define IPR_ADDR 0xfffff30c
+#define IPR LONG_REF(IPR_ADDR)
+
+#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
+#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
+#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
+#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
+#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
+#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define IPR_SPIM IPR_SPI
+#define IPR_TMR1 IPR_TMR
+
+/**********
+ *
+ * 0xFFFFF4xx -- Parallel Ports
+ *
+ **********/
+
+/*
+ * Port A
+ */
+#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
+#define PADATA_ADDR 0xfffff401 /* Port A data register */
+#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
+
+#define PADIR BYTE_REF(PADIR_ADDR)
+#define PADATA BYTE_REF(PADATA_ADDR)
+#define PAPUEN BYTE_REF(PAPUEN_ADDR)
+
+#define PA(x) (1 << (x))
+
+/*
+ * Port B
+ */
+#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
+#define PBDATA_ADDR 0xfffff409 /* Port B data register */
+#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
+#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
+
+#define PBDIR BYTE_REF(PBDIR_ADDR)
+#define PBDATA BYTE_REF(PBDATA_ADDR)
+#define PBPUEN BYTE_REF(PBPUEN_ADDR)
+#define PBSEL BYTE_REF(PBSEL_ADDR)
+
+#define PB(x) (1 << (x))
+
+#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
+#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
+#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
+#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
+#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
+#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
+#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
+#define PB_PWMO 0x80 /* Use PWMO as PB[7] */
+
+/*
+ * Port C
+ */
+#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
+#define PCDATA_ADDR 0xfffff411 /* Port C data register */
+#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
+#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
+
+#define PCDIR BYTE_REF(PCDIR_ADDR)
+#define PCDATA BYTE_REF(PCDATA_ADDR)
+#define PCPDEN BYTE_REF(PCPDEN_ADDR)
+#define PCSEL BYTE_REF(PCSEL_ADDR)
+
+#define PC(x) (1 << (x))
+
+#define PC_LD0 0x01 /* Use LD0 as PC[0] */
+#define PC_LD1 0x02 /* Use LD1 as PC[1] */
+#define PC_LD2 0x04 /* Use LD2 as PC[2] */
+#define PC_LD3 0x08 /* Use LD3 as PC[3] */
+#define PC_LFLM 0x10 /* Use LFLM as PC[4] */
+#define PC_LLP 0x20 /* Use LLP as PC[5] */
+#define PC_LCLK 0x40 /* Use LCLK as PC[6] */
+#define PC_LACD 0x80 /* Use LACD as PC[7] */
+
+/*
+ * Port D
+ */
+#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
+#define PDDATA_ADDR 0xfffff419 /* Port D data register */
+#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
+#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
+#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
+#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
+#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
+#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
+
+#define PDDIR BYTE_REF(PDDIR_ADDR)
+#define PDDATA BYTE_REF(PDDATA_ADDR)
+#define PDPUEN BYTE_REF(PDPUEN_ADDR)
+#define PDSEL BYTE_REF(PDSEL_ADDR)
+#define PDPOL BYTE_REF(PDPOL_ADDR)
+#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
+#define PDKBEN BYTE_REF(PDKBEN_ADDR)
+#define PDIQEG BYTE_REF(PDIQEG_ADDR)
+
+#define PD(x) (1 << (x))
+
+#define PD_INT0 0x01 /* Use INT0 as PD[0] */
+#define PD_INT1 0x02 /* Use INT1 as PD[1] */
+#define PD_INT2 0x04 /* Use INT2 as PD[2] */
+#define PD_INT3 0x08 /* Use INT3 as PD[3] */
+#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
+#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
+#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
+#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
+
+/*
+ * Port E
+ */
+#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
+#define PEDATA_ADDR 0xfffff421 /* Port E data register */
+#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
+#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
+
+#define PEDIR BYTE_REF(PEDIR_ADDR)
+#define PEDATA BYTE_REF(PEDATA_ADDR)
+#define PEPUEN BYTE_REF(PEPUEN_ADDR)
+#define PESEL BYTE_REF(PESEL_ADDR)
+
+#define PE(x) (1 << (x))
+
+#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
+#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
+#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
+#define PE_DWE 0x08 /* Use DWE as PE[3] */
+#define PE_RXD 0x10 /* Use RXD as PE[4] */
+#define PE_TXD 0x20 /* Use TXD as PE[5] */
+#define PE_RTS 0x40 /* Use RTS as PE[6] */
+#define PE_CTS 0x80 /* Use CTS as PE[7] */
+
+/*
+ * Port F
+ */
+#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
+#define PFDATA_ADDR 0xfffff429 /* Port F data register */
+#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
+#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
+
+#define PFDIR BYTE_REF(PFDIR_ADDR)
+#define PFDATA BYTE_REF(PFDATA_ADDR)
+#define PFPUEN BYTE_REF(PFPUEN_ADDR)
+#define PFSEL BYTE_REF(PFSEL_ADDR)
+
+#define PF(x) (1 << (x))
+
+#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
+#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
+#define PF_CLKO 0x04 /* Use CLKO as PF[2] */
+#define PF_A20 0x08 /* Use A20 as PF[3] */
+#define PF_A21 0x10 /* Use A21 as PF[4] */
+#define PF_A22 0x20 /* Use A22 as PF[5] */
+#define PF_A23 0x40 /* Use A23 as PF[6] */
+#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
+
+/*
+ * Port G
+ */
+#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
+#define PGDATA_ADDR 0xfffff431 /* Port G data register */
+#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
+#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
+
+#define PGDIR BYTE_REF(PGDIR_ADDR)
+#define PGDATA BYTE_REF(PGDATA_ADDR)
+#define PGPUEN BYTE_REF(PGPUEN_ADDR)
+#define PGSEL BYTE_REF(PGSEL_ADDR)
+
+#define PG(x) (1 << (x))
+
+#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
+#define PG_A0 0x02 /* Use A0 as PG[1] */
+#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
+#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
+#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
+#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
+
+/**********
+ *
+ * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
+ *
+ **********/
+
+/*
+ * PWM Control Register
+ */
+#define PWMC_ADDR 0xfffff500
+#define PWMC WORD_REF(PWMC_ADDR)
+
+#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
+#define PWMC_CLKSEL_SHIFT 0
+#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
+#define PWMC_REPEAT_SHIFT 2
+#define PWMC_EN 0x0010 /* Enable PWM */
+#define PMNC_FIFOAV 0x0020 /* FIFO Available */
+#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
+#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
+#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
+#define PWMC_PRESCALER_SHIFT 8
+#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
+
+/* '328-compatible definitions */
+#define PWMC_PWMEN PWMC_EN
+
+/*
+ * PWM Sample Register
+ */
+#define PWMS_ADDR 0xfffff502
+#define PWMS WORD_REF(PWMS_ADDR)
+
+/*
+ * PWM Period Register
+ */
+#define PWMP_ADDR 0xfffff504
+#define PWMP BYTE_REF(PWMP_ADDR)
+
+/*
+ * PWM Counter Register
+ */
+#define PWMCNT_ADDR 0xfffff505
+#define PWMCNT BYTE_REF(PWMCNT_ADDR)
+
+/**********
+ *
+ * 0xFFFFF6xx -- General-Purpose Timer
+ *
+ **********/
+
+/*
+ * Timer Control register
+ */
+#define TCTL_ADDR 0xfffff600
+#define TCTL WORD_REF(TCTL_ADDR)
+
+#define TCTL_TEN 0x0001 /* Timer Enable */
+#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
+#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
+#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
+#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
+#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
+#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
+#define TCTL_IRQEN 0x0010 /* IRQ Enable */
+#define TCTL_OM 0x0020 /* Output Mode */
+#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
+#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
+#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
+#define TCTL_FRR 0x0010 /* Free-Run Mode */
+
+/* '328-compatible definitions */
+#define TCTL1_ADDR TCTL_ADDR
+#define TCTL1 TCTL
+
+/*
+ * Timer Prescaler Register
+ */
+#define TPRER_ADDR 0xfffff602
+#define TPRER WORD_REF(TPRER_ADDR)
+
+/* '328-compatible definitions */
+#define TPRER1_ADDR TPRER_ADDR
+#define TPRER1 TPRER
+
+/*
+ * Timer Compare Register
+ */
+#define TCMP_ADDR 0xfffff604
+#define TCMP WORD_REF(TCMP_ADDR)
+
+/* '328-compatible definitions */
+#define TCMP1_ADDR TCMP_ADDR
+#define TCMP1 TCMP
+
+/*
+ * Timer Capture register
+ */
+#define TCR_ADDR 0xfffff606
+#define TCR WORD_REF(TCR_ADDR)
+
+/* '328-compatible definitions */
+#define TCR1_ADDR TCR_ADDR
+#define TCR1 TCR
+
+/*
+ * Timer Counter Register
+ */
+#define TCN_ADDR 0xfffff608
+#define TCN WORD_REF(TCN_ADDR)
+
+/* '328-compatible definitions */
+#define TCN1_ADDR TCN_ADDR
+#define TCN1 TCN
+
+/*
+ * Timer Status Register
+ */
+#define TSTAT_ADDR 0xfffff60a
+#define TSTAT WORD_REF(TSTAT_ADDR)
+
+#define TSTAT_COMP 0x0001 /* Compare Event occurred */
+#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
+
+/* '328-compatible definitions */
+#define TSTAT1_ADDR TSTAT_ADDR
+#define TSTAT1 TSTAT
+
+/**********
+ *
+ * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
+ *
+ **********/
+
+/*
+ * SPIM Data Register
+ */
+#define SPIMDATA_ADDR 0xfffff800
+#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
+
+/*
+ * SPIM Control/Status Register
+ */
+#define SPIMCONT_ADDR 0xfffff802
+#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
+
+#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
+#define SPIMCONT_BIT_COUNT_SHIFT 0
+#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
+#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
+#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
+#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
+#define SPIMCONT_XCH 0x0100 /* Exchange */
+#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
+#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
+#define SPIMCONT_DATA_RATE_SHIFT 13
+
+/* '328-compatible definitions */
+#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
+#define SPIMCONT_SPIMEN SPIMCONT_ENABLE
+
+/**********
+ *
+ * 0xFFFFF9xx -- UART
+ *
+ **********/
+
+/*
+ * UART Status/Control Register
+ */
+#define USTCNT_ADDR 0xfffff900
+#define USTCNT WORD_REF(USTCNT_ADDR)
+
+#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
+#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
+#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
+#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
+#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
+#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
+#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
+#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
+#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
+#define USTCNT_STOP 0x0200 /* Stop bit transmission */
+#define USTCNT_ODD 0x0400 /* Odd Parity */
+#define USTCNT_PEN 0x0800 /* Parity Enable */
+#define USTCNT_CLKM 0x1000 /* Clock Mode Select */
+#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
+#define USTCNT_RXEN 0x4000 /* Receiver Enable */
+#define USTCNT_UEN 0x8000 /* UART Enable */
+
+/* '328-compatible definitions */
+#define USTCNT_TXAVAILEN USTCNT_TXAE
+#define USTCNT_TXHALFEN USTCNT_TXHE
+#define USTCNT_TXEMPTYEN USTCNT_TXEE
+#define USTCNT_RXREADYEN USTCNT_RXRE
+#define USTCNT_RXHALFEN USTCNT_RXHE
+#define USTCNT_RXFULLEN USTCNT_RXFE
+#define USTCNT_CTSDELTAEN USTCNT_CTSD
+#define USTCNT_ODD_EVEN USTCNT_ODD
+#define USTCNT_PARITYEN USTCNT_PEN
+#define USTCNT_CLKMODE USTCNT_CLKM
+#define USTCNT_UARTEN USTCNT_UEN
+
+/*
+ * UART Baud Control Register
+ */
+#define UBAUD_ADDR 0xfffff902
+#define UBAUD WORD_REF(UBAUD_ADDR)
+
+#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
+#define UBAUD_PRESCALER_SHIFT 0
+#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
+#define UBAUD_DIVIDE_SHIFT 8
+#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
+#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
+
+/*
+ * UART Receiver Register
+ */
+#define URX_ADDR 0xfffff904
+#define URX WORD_REF(URX_ADDR)
+
+#define URX_RXDATA_ADDR 0xfffff905
+#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
+
+#define URX_RXDATA_MASK 0x00ff /* Received data */
+#define URX_RXDATA_SHIFT 0
+#define URX_PARITY_ERROR 0x0100 /* Parity Error */
+#define URX_BREAK 0x0200 /* Break Detected */
+#define URX_FRAME_ERROR 0x0400 /* Framing Error */
+#define URX_OVRUN 0x0800 /* Serial Overrun */
+#define URX_OLD_DATA 0x1000 /* Old data in FIFO */
+#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
+#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
+#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
+
+/*
+ * UART Transmitter Register
+ */
+#define UTX_ADDR 0xfffff906
+#define UTX WORD_REF(UTX_ADDR)
+
+#define UTX_TXDATA_ADDR 0xfffff907
+#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
+
+#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
+#define UTX_TXDATA_SHIFT 0
+#define UTX_CTS_DELTA 0x0100 /* CTS changed */
+#define UTX_CTS_STAT 0x0200 /* CTS State */
+#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
+#define UTX_NOCTS 0x0800 /* Ignore CTS */
+#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
+#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
+#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
+#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
+
+/* '328-compatible definitions */
+#define UTX_CTS_STATUS UTX_CTS_STAT
+#define UTX_IGNORE_CTS UTX_NOCTS
+
+/*
+ * UART Miscellaneous Register
+ */
+#define UMISC_ADDR 0xfffff908
+#define UMISC WORD_REF(UMISC_ADDR)
+
+#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
+#define UMISC_RX_POL 0x0008 /* Receive Polarity */
+#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
+#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
+#define UMISC_RTS 0x0040 /* Set RTS status */
+#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
+#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
+#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
+#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
+#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
+#define UMISC_CLKSRC 0x4000 /* Clock Source */
+#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
+
+/*
+ * UART Non-integer Prescaler Register
+ */
+#define NIPR_ADDR 0xfffff90a
+#define NIPR WORD_REF(NIPR_ADDR)
+
+#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
+#define NIPR_STEP_VALUE_SHIFT 0
+#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
+#define NIPR_SELECT_SHIFT 8
+#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
+
+
+/* generalization of uart control registers to support multiple ports: */
+typedef volatile struct {
+ volatile unsigned short int ustcnt;
+ volatile unsigned short int ubaud;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char rxdata;
+ } b;
+ } urx;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char txdata;
+ } b;
+ } utx;
+ volatile unsigned short int umisc;
+ volatile unsigned short int nipr;
+ volatile unsigned short int pad1;
+ volatile unsigned short int pad2;
+} __packed m68328_uart;
+
+
+/**********
+ *
+ * 0xFFFFFAxx -- LCD Controller
+ *
+ **********/
+
+/*
+ * LCD Screen Starting Address Register
+ */
+#define LSSA_ADDR 0xfffffa00
+#define LSSA LONG_REF(LSSA_ADDR)
+
+#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
+
+/*
+ * LCD Virtual Page Width Register
+ */
+#define LVPW_ADDR 0xfffffa05
+#define LVPW BYTE_REF(LVPW_ADDR)
+
+/*
+ * LCD Screen Width Register (not compatible with '328 !!!)
+ */
+#define LXMAX_ADDR 0xfffffa08
+#define LXMAX WORD_REF(LXMAX_ADDR)
+
+#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
+
+/*
+ * LCD Screen Height Register
+ */
+#define LYMAX_ADDR 0xfffffa0a
+#define LYMAX WORD_REF(LYMAX_ADDR)
+
+#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
+
+/*
+ * LCD Cursor X Position Register
+ */
+#define LCXP_ADDR 0xfffffa18
+#define LCXP WORD_REF(LCXP_ADDR)
+
+#define LCXP_CC_MASK 0xc000 /* Cursor Control */
+#define LCXP_CC_TRAMSPARENT 0x0000
+#define LCXP_CC_BLACK 0x4000
+#define LCXP_CC_REVERSED 0x8000
+#define LCXP_CC_WHITE 0xc000
+#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
+
+/*
+ * LCD Cursor Y Position Register
+ */
+#define LCYP_ADDR 0xfffffa1a
+#define LCYP WORD_REF(LCYP_ADDR)
+
+#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
+
+/*
+ * LCD Cursor Width and Heigth Register
+ */
+#define LCWCH_ADDR 0xfffffa1c
+#define LCWCH WORD_REF(LCWCH_ADDR)
+
+#define LCWCH_CH_MASK 0x001f /* Cursor Height */
+#define LCWCH_CH_SHIFT 0
+#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
+#define LCWCH_CW_SHIFT 8
+
+/*
+ * LCD Blink Control Register
+ */
+#define LBLKC_ADDR 0xfffffa1f
+#define LBLKC BYTE_REF(LBLKC_ADDR)
+
+#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
+#define LBLKC_BD_SHIFT 0
+#define LBLKC_BKEN 0x80 /* Blink Enabled */
+
+/*
+ * LCD Panel Interface Configuration Register
+ */
+#define LPICF_ADDR 0xfffffa20
+#define LPICF BYTE_REF(LPICF_ADDR)
+
+#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
+#define LPICF_GS_BW 0x00
+#define LPICF_GS_GRAY_4 0x01
+#define LPICF_GS_GRAY_16 0x02
+#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
+#define LPICF_PBSIZ_1 0x00
+#define LPICF_PBSIZ_2 0x04
+#define LPICF_PBSIZ_4 0x08
+
+/*
+ * LCD Polarity Configuration Register
+ */
+#define LPOLCF_ADDR 0xfffffa21
+#define LPOLCF BYTE_REF(LPOLCF_ADDR)
+
+#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
+#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
+#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
+#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
+
+/*
+ * LACD (LCD Alternate Crystal Direction) Rate Control Register
+ */
+#define LACDRC_ADDR 0xfffffa23
+#define LACDRC BYTE_REF(LACDRC_ADDR)
+
+#define LACDRC_ACDSLT 0x80 /* Signal Source Select */
+#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
+#define LACDRC_ACD_SHIFT 0
+
+/*
+ * LCD Pixel Clock Divider Register
+ */
+#define LPXCD_ADDR 0xfffffa25
+#define LPXCD BYTE_REF(LPXCD_ADDR)
+
+#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
+#define LPXCD_PCD_SHIFT 0
+
+/*
+ * LCD Clocking Control Register
+ */
+#define LCKCON_ADDR 0xfffffa27
+#define LCKCON BYTE_REF(LCKCON_ADDR)
+
+#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
+#define LCKCON_DWS_SHIFT 0
+#define LCKCON_DWIDTH 0x40 /* Display Memory Width */
+#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
+
+/* '328-compatible definitions */
+#define LCKCON_DW_MASK LCKCON_DWS_MASK
+#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
+
+/*
+ * LCD Refresh Rate Adjustment Register
+ */
+#define LRRA_ADDR 0xfffffa29
+#define LRRA BYTE_REF(LRRA_ADDR)
+
+/*
+ * LCD Panning Offset Register
+ */
+#define LPOSR_ADDR 0xfffffa2d
+#define LPOSR BYTE_REF(LPOSR_ADDR)
+
+#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
+#define LPOSR_POS_SHIFT 0
+
+/*
+ * LCD Frame Rate Control Modulation Register
+ */
+#define LFRCM_ADDR 0xfffffa31
+#define LFRCM BYTE_REF(LFRCM_ADDR)
+
+#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
+#define LFRCM_YMOD_SHIFT 0
+#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
+#define LFRCM_XMOD_SHIFT 4
+
+/*
+ * LCD Gray Palette Mapping Register
+ */
+#define LGPMR_ADDR 0xfffffa33
+#define LGPMR BYTE_REF(LGPMR_ADDR)
+
+#define LGPMR_G1_MASK 0x0f
+#define LGPMR_G1_SHIFT 0
+#define LGPMR_G2_MASK 0xf0
+#define LGPMR_G2_SHIFT 4
+
+/*
+ * PWM Contrast Control Register
+ */
+#define PWMR_ADDR 0xfffffa36
+#define PWMR WORD_REF(PWMR_ADDR)
+
+#define PWMR_PW_MASK 0x00ff /* Pulse Width */
+#define PWMR_PW_SHIFT 0
+#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
+#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
+#define PWMR_SRC_LINE 0x0000 /* Line Pulse */
+#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
+#define PWMR_SRC_LCD 0x4000 /* LCD clock */
+
+/**********
+ *
+ * 0xFFFFFBxx -- Real-Time Clock (RTC)
+ *
+ **********/
+
+/*
+ * RTC Hours Minutes and Seconds Register
+ */
+#define RTCTIME_ADDR 0xfffffb00
+#define RTCTIME LONG_REF(RTCTIME_ADDR)
+
+#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCTIME_SECONDS_SHIFT 0
+#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCTIME_MINUTES_SHIFT 16
+#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCTIME_HOURS_SHIFT 24
+
+/*
+ * RTC Alarm Register
+ */
+#define RTCALRM_ADDR 0xfffffb04
+#define RTCALRM LONG_REF(RTCALRM_ADDR)
+
+#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCALRM_SECONDS_SHIFT 0
+#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCALRM_MINUTES_SHIFT 16
+#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCALRM_HOURS_SHIFT 24
+
+/*
+ * Watchdog Timer Register
+ */
+#define WATCHDOG_ADDR 0xfffffb0a
+#define WATCHDOG WORD_REF(WATCHDOG_ADDR)
+
+#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
+#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
+#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */
+#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
+#define WATCHDOG_CNT_SHIFT 8
+
+/*
+ * RTC Control Register
+ */
+#define RTCCTL_ADDR 0xfffffb0c
+#define RTCCTL WORD_REF(RTCCTL_ADDR)
+
+#define RTCCTL_XTL 0x0020 /* Crystal Selection */
+#define RTCCTL_EN 0x0080 /* RTC Enable */
+
+/* '328-compatible definitions */
+#define RTCCTL_384 RTCCTL_XTL
+#define RTCCTL_ENABLE RTCCTL_EN
+
+/*
+ * RTC Interrupt Status Register
+ */
+#define RTCISR_ADDR 0xfffffb0e
+#define RTCISR WORD_REF(RTCISR_ADDR)
+
+#define RTCISR_SW 0x0001 /* Stopwatch timed out */
+#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
+#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
+#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
+#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
+#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
+#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
+#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
+#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
+#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
+#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
+#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
+#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
+#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
+
+/*
+ * RTC Interrupt Enable Register
+ */
+#define RTCIENR_ADDR 0xfffffb10
+#define RTCIENR WORD_REF(RTCIENR_ADDR)
+
+#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
+#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
+#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
+#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
+#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
+#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
+#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
+#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
+#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
+#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
+#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
+#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
+#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
+#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
+
+/*
+ * Stopwatch Minutes Register
+ */
+#define STPWCH_ADDR 0xfffffb12
+#define STPWCH WORD_REF(STPWCH)
+
+#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
+#define SPTWCH_CNT_SHIFT 0
+
+/*
+ * RTC Day Count Register
+ */
+#define DAYR_ADDR 0xfffffb1a
+#define DAYR WORD_REF(DAYR_ADDR)
+
+#define DAYR_DAYS_MASK 0x1ff /* Day Setting */
+#define DAYR_DAYS_SHIFT 0
+
+/*
+ * RTC Day Alarm Register
+ */
+#define DAYALARM_ADDR 0xfffffb1c
+#define DAYALARM WORD_REF(DAYALARM_ADDR)
+
+#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
+#define DAYALARM_DAYSAL_SHIFT 0
+
+/**********
+ *
+ * 0xFFFFFCxx -- DRAM Controller
+ *
+ **********/
+
+/*
+ * DRAM Memory Configuration Register
+ */
+#define DRAMMC_ADDR 0xfffffc00
+#define DRAMMC WORD_REF(DRAMMC_ADDR)
+
+#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
+#define DRAMMC_ROW12_PA10 0x0000
+#define DRAMMC_ROW12_PA21 0x4000
+#define DRAMMC_ROW12_PA23 0x8000
+#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
+#define DRAMMC_ROW0_PA11 0x0000
+#define DRAMMC_ROW0_PA22 0x1000
+#define DRAMMC_ROW0_PA23 0x2000
+#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
+#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
+#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
+#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
+#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
+#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
+#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
+#define DRAMMC_REF_MASK 0x001f /* Refresh Cycle */
+#define DRAMMC_REF_SHIFT 0
+
+/*
+ * DRAM Control Register
+ */
+#define DRAMC_ADDR 0xfffffc02
+#define DRAMC WORD_REF(DRAMC_ADDR)
+
+#define DRAMC_DWE 0x0001 /* DRAM Write Enable */
+#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
+#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
+#define DRAMC_SLW 0x0008 /* Slow RAM */
+#define DRAMC_LSP 0x0010 /* Light Sleep */
+#define DRAMC_MSW 0x0020 /* Slow Multiplexing */
+#define DRAMC_WS_MASK 0x00c0 /* Wait-states */
+#define DRAMC_WS_SHIFT 6
+#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
+#define DRAMC_PGSZ_SHIFT 8
+#define DRAMC_PGSZ_256K 0x0000
+#define DRAMC_PGSZ_512K 0x0100
+#define DRAMC_PGSZ_1024K 0x0200
+#define DRAMC_PGSZ_2048K 0x0300
+#define DRAMC_EDO 0x0400 /* EDO DRAM */
+#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
+#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
+#define DRAMC_BC_SHIFT 12
+#define DRAMC_RM 0x4000 /* Refresh Mode */
+#define DRAMC_EN 0x8000 /* DRAM Controller enable */
+
+
+/**********
+ *
+ * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
+ *
+ **********/
+
+/*
+ * ICE Module Address Compare Register
+ */
+#define ICEMACR_ADDR 0xfffffd00
+#define ICEMACR LONG_REF(ICEMACR_ADDR)
+
+/*
+ * ICE Module Address Mask Register
+ */
+#define ICEMAMR_ADDR 0xfffffd04
+#define ICEMAMR LONG_REF(ICEMAMR_ADDR)
+
+/*
+ * ICE Module Control Compare Register
+ */
+#define ICEMCCR_ADDR 0xfffffd08
+#define ICEMCCR WORD_REF(ICEMCCR_ADDR)
+
+#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
+#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
+
+/*
+ * ICE Module Control Mask Register
+ */
+#define ICEMCMR_ADDR 0xfffffd0a
+#define ICEMCMR WORD_REF(ICEMCMR_ADDR)
+
+#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
+#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
+
+/*
+ * ICE Module Control Register
+ */
+#define ICEMCR_ADDR 0xfffffd0c
+#define ICEMCR WORD_REF(ICEMCR_ADDR)
+
+#define ICEMCR_CEN 0x0001 /* Compare Enable */
+#define ICEMCR_PBEN 0x0002 /* Program Break Enable */
+#define ICEMCR_SB 0x0004 /* Single Breakpoint */
+#define ICEMCR_HMDIS 0x0008 /* HardMap disable */
+#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
+
+/*
+ * ICE Module Status Register
+ */
+#define ICEMSR_ADDR 0xfffffd0e
+#define ICEMSR WORD_REF(ICEMSR_ADDR)
+
+#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
+#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
+#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
+#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */
+
+#endif /* _MC68EZ328_H_ */
diff --git a/arch/m68k/include/asm/MC68VZ328.h b/arch/m68k/include/asm/MC68VZ328.h
new file mode 100644
index 0000000..dc894cf
--- /dev/null
+++ b/arch/m68k/include/asm/MC68VZ328.h
@@ -0,0 +1,1350 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
+ *
+ * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
+ * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
+ * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
+ * Bare & Hare Software, Inc.
+ * Based on include/asm-m68knommu/MC68332.h
+ * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
+ * The Silver Hammer Group, Ltd.
+ *
+ * M68VZ328 fixes by Evan Stawnyczy <evan@lineo.com>
+ * vz multiport fixes by Michael Leslie <mleslie@lineo.com>
+ */
+
+#ifndef _MC68VZ328_H_
+#define _MC68VZ328_H_
+
+#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
+#define WORD_REF(addr) (*((volatile unsigned short*)addr))
+#define LONG_REF(addr) (*((volatile unsigned long*)addr))
+
+#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
+#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
+
+/**********
+ *
+ * 0xFFFFF0xx -- System Control
+ *
+ **********/
+
+/*
+ * System Control Register (SCR)
+ */
+#define SCR_ADDR 0xfffff000
+#define SCR BYTE_REF(SCR_ADDR)
+
+#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
+#define SCR_DMAP 0x04 /* Double Map */
+#define SCR_SO 0x08 /* Supervisor Only */
+#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
+#define SCR_PRV 0x20 /* Privilege Violation */
+#define SCR_WPV 0x40 /* Write Protect Violation */
+#define SCR_BETO 0x80 /* Bus-Error TimeOut */
+
+/*
+ * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
+ */
+#define MRR_ADDR 0xfffff004
+#define MRR LONG_REF(MRR_ADDR)
+
+/**********
+ *
+ * 0xFFFFF1xx -- Chip-Select logic
+ *
+ **********/
+
+/*
+ * Chip Select Group Base Registers
+ */
+#define CSGBA_ADDR 0xfffff100
+#define CSGBB_ADDR 0xfffff102
+
+#define CSGBC_ADDR 0xfffff104
+#define CSGBD_ADDR 0xfffff106
+
+#define CSGBA WORD_REF(CSGBA_ADDR)
+#define CSGBB WORD_REF(CSGBB_ADDR)
+#define CSGBC WORD_REF(CSGBC_ADDR)
+#define CSGBD WORD_REF(CSGBD_ADDR)
+
+/*
+ * Chip Select Registers
+ */
+#define CSA_ADDR 0xfffff110
+#define CSB_ADDR 0xfffff112
+#define CSC_ADDR 0xfffff114
+#define CSD_ADDR 0xfffff116
+
+#define CSA WORD_REF(CSA_ADDR)
+#define CSB WORD_REF(CSB_ADDR)
+#define CSC WORD_REF(CSC_ADDR)
+#define CSD WORD_REF(CSD_ADDR)
+
+#define CSA_EN 0x0001 /* Chip-Select Enable */
+#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSA_SIZ_SHIFT 1
+#define CSA_WS_MASK 0x0070 /* Wait State */
+#define CSA_WS_SHIFT 4
+#define CSA_BSW 0x0080 /* Data Bus Width */
+#define CSA_FLASH 0x0100 /* FLASH Memory Support */
+#define CSA_RO 0x8000 /* Read-Only */
+
+#define CSB_EN 0x0001 /* Chip-Select Enable */
+#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSB_SIZ_SHIFT 1
+#define CSB_WS_MASK 0x0070 /* Wait State */
+#define CSB_WS_SHIFT 4
+#define CSB_BSW 0x0080 /* Data Bus Width */
+#define CSB_FLASH 0x0100 /* FLASH Memory Support */
+#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSB_UPSIZ_SHIFT 11
+#define CSB_ROP 0x2000 /* Readonly if protected */
+#define CSB_SOP 0x4000 /* Supervisor only if protected */
+#define CSB_RO 0x8000 /* Read-Only */
+
+#define CSC_EN 0x0001 /* Chip-Select Enable */
+#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSC_SIZ_SHIFT 1
+#define CSC_WS_MASK 0x0070 /* Wait State */
+#define CSC_WS_SHIFT 4
+#define CSC_BSW 0x0080 /* Data Bus Width */
+#define CSC_FLASH 0x0100 /* FLASH Memory Support */
+#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSC_UPSIZ_SHIFT 11
+#define CSC_ROP 0x2000 /* Readonly if protected */
+#define CSC_SOP 0x4000 /* Supervisor only if protected */
+#define CSC_RO 0x8000 /* Read-Only */
+
+#define CSD_EN 0x0001 /* Chip-Select Enable */
+#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
+#define CSD_SIZ_SHIFT 1
+#define CSD_WS_MASK 0x0070 /* Wait State */
+#define CSD_WS_SHIFT 4
+#define CSD_BSW 0x0080 /* Data Bus Width */
+#define CSD_FLASH 0x0100 /* FLASH Memory Support */
+#define CSD_DRAM 0x0200 /* Dram Selection */
+#define CSD_COMB 0x0400 /* Combining */
+#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
+#define CSD_UPSIZ_SHIFT 11
+#define CSD_ROP 0x2000 /* Readonly if protected */
+#define CSD_SOP 0x4000 /* Supervisor only if protected */
+#define CSD_RO 0x8000 /* Read-Only */
+
+/*
+ * Emulation Chip-Select Register
+ */
+#define EMUCS_ADDR 0xfffff118
+#define EMUCS WORD_REF(EMUCS_ADDR)
+
+#define EMUCS_WS_MASK 0x0070
+#define EMUCS_WS_SHIFT 4
+
+/**********
+ *
+ * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
+ *
+ **********/
+
+/*
+ * PLL Control Register
+ */
+#define PLLCR_ADDR 0xfffff200
+#define PLLCR WORD_REF(PLLCR_ADDR)
+
+#define PLLCR_DISPLL 0x0008 /* Disable PLL */
+#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
+#define PLLCR_PRESC 0x0020 /* VCO prescaler */
+#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
+#define PLLCR_SYSCLK_SEL_SHIFT 8
+#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
+#define PLLCR_LCDCLK_SEL_SHIFT 11
+
+/* '328-compatible definitions */
+#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
+#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
+
+/*
+ * PLL Frequency Select Register
+ */
+#define PLLFSR_ADDR 0xfffff202
+#define PLLFSR WORD_REF(PLLFSR_ADDR)
+
+#define PLLFSR_PC_MASK 0x00ff /* P Count */
+#define PLLFSR_PC_SHIFT 0
+#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
+#define PLLFSR_QC_SHIFT 8
+#define PLLFSR_PROT 0x4000 /* Protect P & Q */
+#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
+
+/*
+ * Power Control Register
+ */
+#define PCTRL_ADDR 0xfffff207
+#define PCTRL BYTE_REF(PCTRL_ADDR)
+
+#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
+#define PCTRL_WIDTH_SHIFT 0
+#define PCTRL_PCEN 0x80 /* Power Control Enable */
+
+/**********
+ *
+ * 0xFFFFF3xx -- Interrupt Controller
+ *
+ **********/
+
+/*
+ * Interrupt Vector Register
+ */
+#define IVR_ADDR 0xfffff300
+#define IVR BYTE_REF(IVR_ADDR)
+
+#define IVR_VECTOR_MASK 0xF8
+
+/*
+ * Interrupt control Register
+ */
+#define ICR_ADDR 0xfffff302
+#define ICR WORD_REF(ICR_ADDR)
+
+#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
+#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
+#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
+#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
+#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
+#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
+#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
+#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
+#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
+
+/*
+ * Interrupt Mask Register
+ */
+#define IMR_ADDR 0xfffff304
+#define IMR LONG_REF(IMR_ADDR)
+
+/*
+ * Define the names for bit positions first. This is useful for
+ * request_irq
+ */
+#define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */
+#define TMR_IRQ_NUM 1 /* Timer 1 interrupt */
+#define UART1_IRQ_NUM 2 /* UART 1 interrupt */
+#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
+#define RTC_IRQ_NUM 4 /* RTC interrupt */
+#define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */
+#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
+#define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */
+#define INT0_IRQ_NUM 8 /* External INT0 */
+#define INT1_IRQ_NUM 9 /* External INT1 */
+#define INT2_IRQ_NUM 10 /* External INT2 */
+#define INT3_IRQ_NUM 11 /* External INT3 */
+#define UART2_IRQ_NUM 12 /* UART 2 interrupt */
+#define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */
+#define IRQ1_IRQ_NUM 16 /* IRQ1 */
+#define IRQ2_IRQ_NUM 17 /* IRQ2 */
+#define IRQ3_IRQ_NUM 18 /* IRQ3 */
+#define IRQ6_IRQ_NUM 19 /* IRQ6 */
+#define IRQ5_IRQ_NUM 20 /* IRQ5 */
+#define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */
+#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
+#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
+
+#define SPI_IRQ_NUM SPI2_IRQ_NUM
+
+/* '328-compatible definitions */
+#define SPIM_IRQ_NUM SPI_IRQ_NUM
+#define TMR1_IRQ_NUM TMR_IRQ_NUM
+#define UART_IRQ_NUM UART1_IRQ_NUM
+
+/*
+ * Here go the bitmasks themselves
+ */
+#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
+#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
+#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
+#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
+#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
+#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
+#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
+#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
+#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
+#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
+#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
+#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
+#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
+#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
+#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
+#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
+#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
+#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define IMR_MSPIM IMR_MSPI
+#define IMR_MTMR1 IMR_MTMR
+
+/*
+ * Interrupt Status Register
+ */
+#define ISR_ADDR 0xfffff30c
+#define ISR LONG_REF(ISR_ADDR)
+
+#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
+#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
+#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
+#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
+#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
+#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define ISR_SPIM ISR_SPI
+#define ISR_TMR1 ISR_TMR
+
+/*
+ * Interrupt Pending Register
+ */
+#define IPR_ADDR 0xfffff30c
+#define IPR LONG_REF(IPR_ADDR)
+
+#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
+#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
+#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
+#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
+#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
+#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
+#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
+#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
+#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
+#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
+#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
+#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
+#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
+#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
+#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
+#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
+#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
+#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
+
+/* '328-compatible definitions */
+#define IPR_SPIM IPR_SPI
+#define IPR_TMR1 IPR_TMR
+
+/**********
+ *
+ * 0xFFFFF4xx -- Parallel Ports
+ *
+ **********/
+
+/*
+ * Port A
+ */
+#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
+#define PADATA_ADDR 0xfffff401 /* Port A data register */
+#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
+
+#define PADIR BYTE_REF(PADIR_ADDR)
+#define PADATA BYTE_REF(PADATA_ADDR)
+#define PAPUEN BYTE_REF(PAPUEN_ADDR)
+
+#define PA(x) (1 << (x))
+
+/*
+ * Port B
+ */
+#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
+#define PBDATA_ADDR 0xfffff409 /* Port B data register */
+#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
+#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
+
+#define PBDIR BYTE_REF(PBDIR_ADDR)
+#define PBDATA BYTE_REF(PBDATA_ADDR)
+#define PBPUEN BYTE_REF(PBPUEN_ADDR)
+#define PBSEL BYTE_REF(PBSEL_ADDR)
+
+#define PB(x) (1 << (x))
+
+#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
+#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
+#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
+#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
+#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
+#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
+#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
+#define PB_PWMO 0x80 /* Use PWMO as PB[7] */
+
+/*
+ * Port C
+ */
+#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
+#define PCDATA_ADDR 0xfffff411 /* Port C data register */
+#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
+#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
+
+#define PCDIR BYTE_REF(PCDIR_ADDR)
+#define PCDATA BYTE_REF(PCDATA_ADDR)
+#define PCPDEN BYTE_REF(PCPDEN_ADDR)
+#define PCSEL BYTE_REF(PCSEL_ADDR)
+
+#define PC(x) (1 << (x))
+
+#define PC_LD0 0x01 /* Use LD0 as PC[0] */
+#define PC_LD1 0x02 /* Use LD1 as PC[1] */
+#define PC_LD2 0x04 /* Use LD2 as PC[2] */
+#define PC_LD3 0x08 /* Use LD3 as PC[3] */
+#define PC_LFLM 0x10 /* Use LFLM as PC[4] */
+#define PC_LLP 0x20 /* Use LLP as PC[5] */
+#define PC_LCLK 0x40 /* Use LCLK as PC[6] */
+#define PC_LACD 0x80 /* Use LACD as PC[7] */
+
+/*
+ * Port D
+ */
+#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
+#define PDDATA_ADDR 0xfffff419 /* Port D data register */
+#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
+#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
+#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
+#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
+#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
+#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
+
+#define PDDIR BYTE_REF(PDDIR_ADDR)
+#define PDDATA BYTE_REF(PDDATA_ADDR)
+#define PDPUEN BYTE_REF(PDPUEN_ADDR)
+#define PDSEL BYTE_REF(PDSEL_ADDR)
+#define PDPOL BYTE_REF(PDPOL_ADDR)
+#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
+#define PDKBEN BYTE_REF(PDKBEN_ADDR)
+#define PDIQEG BYTE_REF(PDIQEG_ADDR)
+
+#define PD(x) (1 << (x))
+
+#define PD_INT0 0x01 /* Use INT0 as PD[0] */
+#define PD_INT1 0x02 /* Use INT1 as PD[1] */
+#define PD_INT2 0x04 /* Use INT2 as PD[2] */
+#define PD_INT3 0x08 /* Use INT3 as PD[3] */
+#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
+#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
+#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
+#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
+
+/*
+ * Port E
+ */
+#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
+#define PEDATA_ADDR 0xfffff421 /* Port E data register */
+#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
+#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
+
+#define PEDIR BYTE_REF(PEDIR_ADDR)
+#define PEDATA BYTE_REF(PEDATA_ADDR)
+#define PEPUEN BYTE_REF(PEPUEN_ADDR)
+#define PESEL BYTE_REF(PESEL_ADDR)
+
+#define PE(x) (1 << (x))
+
+#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
+#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
+#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
+#define PE_DWE 0x08 /* Use DWE as PE[3] */
+#define PE_RXD 0x10 /* Use RXD as PE[4] */
+#define PE_TXD 0x20 /* Use TXD as PE[5] */
+#define PE_RTS 0x40 /* Use RTS as PE[6] */
+#define PE_CTS 0x80 /* Use CTS as PE[7] */
+
+/*
+ * Port F
+ */
+#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
+#define PFDATA_ADDR 0xfffff429 /* Port F data register */
+#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
+#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
+
+#define PFDIR BYTE_REF(PFDIR_ADDR)
+#define PFDATA BYTE_REF(PFDATA_ADDR)
+#define PFPUEN BYTE_REF(PFPUEN_ADDR)
+#define PFSEL BYTE_REF(PFSEL_ADDR)
+
+#define PF(x) (1 << (x))
+
+#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
+#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
+#define PF_CLKO 0x04 /* Use CLKO as PF[2] */
+#define PF_A20 0x08 /* Use A20 as PF[3] */
+#define PF_A21 0x10 /* Use A21 as PF[4] */
+#define PF_A22 0x20 /* Use A22 as PF[5] */
+#define PF_A23 0x40 /* Use A23 as PF[6] */
+#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
+
+/*
+ * Port G
+ */
+#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
+#define PGDATA_ADDR 0xfffff431 /* Port G data register */
+#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
+#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
+
+#define PGDIR BYTE_REF(PGDIR_ADDR)
+#define PGDATA BYTE_REF(PGDATA_ADDR)
+#define PGPUEN BYTE_REF(PGPUEN_ADDR)
+#define PGSEL BYTE_REF(PGSEL_ADDR)
+
+#define PG(x) (1 << (x))
+
+#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
+#define PG_A0 0x02 /* Use A0 as PG[1] */
+#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
+#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
+#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
+#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
+
+/*
+ * Port J
+ */
+#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
+#define PJDATA_ADDR 0xfffff439 /* Port J data register */
+#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */
+#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
+
+#define PJDIR BYTE_REF(PJDIR_ADDR)
+#define PJDATA BYTE_REF(PJDATA_ADDR)
+#define PJPUEN BYTE_REF(PJPUEN_ADDR)
+#define PJSEL BYTE_REF(PJSEL_ADDR)
+
+#define PJ(x) (1 << (x))
+
+/*
+ * Port K
+ */
+#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
+#define PKDATA_ADDR 0xfffff441 /* Port K data register */
+#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */
+#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
+
+#define PKDIR BYTE_REF(PKDIR_ADDR)
+#define PKDATA BYTE_REF(PKDATA_ADDR)
+#define PKPUEN BYTE_REF(PKPUEN_ADDR)
+#define PKSEL BYTE_REF(PKSEL_ADDR)
+
+#define PK(x) (1 << (x))
+
+#define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */
+#define PK_PWM2 0x01 /* Use PWM2 as PK[0] */
+#define PK_R_W 0x02 /* Use R/W as PK[1] */
+#define PK_LDS 0x04 /* Use /LDS as PK[2] */
+#define PK_UDS 0x08 /* Use /UDS as PK[3] */
+#define PK_LD4 0x10 /* Use LD4 as PK[4] */
+#define PK_LD5 0x20 /* Use LD5 as PK[5] */
+#define PK_LD6 0x40 /* Use LD6 as PK[6] */
+#define PK_LD7 0x80 /* Use LD7 as PK[7] */
+
+#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
+#define PJDATA_ADDR 0xfffff439 /* Port J data register */
+#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */
+#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */
+
+#define PJDIR BYTE_REF(PJDIR_ADDR)
+#define PJDATA BYTE_REF(PJDATA_ADDR)
+#define PJPUEN BYTE_REF(PJPUEN_ADDR)
+#define PJSEL BYTE_REF(PJSEL_ADDR)
+
+#define PJ(x) (1 << (x))
+
+#define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */
+#define PJ_MISO 0x02 /* Use MISO as PJ[1] */
+#define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */
+#define PJ_SS 0x08 /* Use SS as PJ[3] */
+#define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */
+#define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */
+#define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */
+#define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */
+
+/*
+ * Port M
+ */
+#define PMDIR_ADDR 0xfffff448 /* Port M direction reg */
+#define PMDATA_ADDR 0xfffff449 /* Port M data register */
+#define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */
+#define PMSEL_ADDR 0xfffff44b /* Port M Select Register */
+
+#define PMDIR BYTE_REF(PMDIR_ADDR)
+#define PMDATA BYTE_REF(PMDATA_ADDR)
+#define PMPUEN BYTE_REF(PMPUEN_ADDR)
+#define PMSEL BYTE_REF(PMSEL_ADDR)
+
+#define PM(x) (1 << (x))
+
+#define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
+#define PM_SDCE 0x02 /* Use SDCE as PM[1] */
+#define PM_DQMH 0x04 /* Use DQMH as PM[2] */
+#define PM_DQML 0x08 /* Use DQML as PM[3] */
+#define PM_SDA10 0x10 /* Use SDA10 as PM[4] */
+#define PM_DMOE 0x20 /* Use DMOE as PM[5] */
+
+/**********
+ *
+ * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
+ *
+ **********/
+
+/*
+ * PWM Control Register
+ */
+#define PWMC_ADDR 0xfffff500
+#define PWMC WORD_REF(PWMC_ADDR)
+
+#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
+#define PWMC_CLKSEL_SHIFT 0
+#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
+#define PWMC_REPEAT_SHIFT 2
+#define PWMC_EN 0x0010 /* Enable PWM */
+#define PMNC_FIFOAV 0x0020 /* FIFO Available */
+#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
+#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
+#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
+#define PWMC_PRESCALER_SHIFT 8
+#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
+
+/* '328-compatible definitions */
+#define PWMC_PWMEN PWMC_EN
+
+/*
+ * PWM Sample Register
+ */
+#define PWMS_ADDR 0xfffff502
+#define PWMS WORD_REF(PWMS_ADDR)
+
+/*
+ * PWM Period Register
+ */
+#define PWMP_ADDR 0xfffff504
+#define PWMP BYTE_REF(PWMP_ADDR)
+
+/*
+ * PWM Counter Register
+ */
+#define PWMCNT_ADDR 0xfffff505
+#define PWMCNT BYTE_REF(PWMCNT_ADDR)
+
+/**********
+ *
+ * 0xFFFFF6xx -- General-Purpose Timer
+ *
+ **********/
+
+/*
+ * Timer Control register
+ */
+#define TCTL_ADDR 0xfffff600
+#define TCTL WORD_REF(TCTL_ADDR)
+
+#define TCTL_TEN 0x0001 /* Timer Enable */
+#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
+#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
+#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
+#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
+#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
+#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
+#define TCTL_IRQEN 0x0010 /* IRQ Enable */
+#define TCTL_OM 0x0020 /* Output Mode */
+#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
+#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
+#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
+#define TCTL_FRR 0x0010 /* Free-Run Mode */
+
+/* '328-compatible definitions */
+#define TCTL1_ADDR TCTL_ADDR
+#define TCTL1 TCTL
+
+/*
+ * Timer Prescaler Register
+ */
+#define TPRER_ADDR 0xfffff602
+#define TPRER WORD_REF(TPRER_ADDR)
+
+/* '328-compatible definitions */
+#define TPRER1_ADDR TPRER_ADDR
+#define TPRER1 TPRER
+
+/*
+ * Timer Compare Register
+ */
+#define TCMP_ADDR 0xfffff604
+#define TCMP WORD_REF(TCMP_ADDR)
+
+/* '328-compatible definitions */
+#define TCMP1_ADDR TCMP_ADDR
+#define TCMP1 TCMP
+
+/*
+ * Timer Capture register
+ */
+#define TCR_ADDR 0xfffff606
+#define TCR WORD_REF(TCR_ADDR)
+
+/* '328-compatible definitions */
+#define TCR1_ADDR TCR_ADDR
+#define TCR1 TCR
+
+/*
+ * Timer Counter Register
+ */
+#define TCN_ADDR 0xfffff608
+#define TCN WORD_REF(TCN_ADDR)
+
+/* '328-compatible definitions */
+#define TCN1_ADDR TCN_ADDR
+#define TCN1 TCN
+
+/*
+ * Timer Status Register
+ */
+#define TSTAT_ADDR 0xfffff60a
+#define TSTAT WORD_REF(TSTAT_ADDR)
+
+#define TSTAT_COMP 0x0001 /* Compare Event occurred */
+#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
+
+/* '328-compatible definitions */
+#define TSTAT1_ADDR TSTAT_ADDR
+#define TSTAT1 TSTAT
+
+/**********
+ *
+ * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
+ *
+ **********/
+
+/*
+ * SPIM Data Register
+ */
+#define SPIMDATA_ADDR 0xfffff800
+#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
+
+/*
+ * SPIM Control/Status Register
+ */
+#define SPIMCONT_ADDR 0xfffff802
+#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
+
+#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
+#define SPIMCONT_BIT_COUNT_SHIFT 0
+#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
+#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
+#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
+#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
+#define SPIMCONT_XCH 0x0100 /* Exchange */
+#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
+#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
+#define SPIMCONT_DATA_RATE_SHIFT 13
+
+/* '328-compatible definitions */
+#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
+#define SPIMCONT_SPIMEN SPIMCONT_ENABLE
+
+/**********
+ *
+ * 0xFFFFF9xx -- UART
+ *
+ **********/
+
+/*
+ * UART Status/Control Register
+ */
+
+#define USTCNT_ADDR 0xfffff900
+#define USTCNT WORD_REF(USTCNT_ADDR)
+
+#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
+#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
+#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
+#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
+#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
+#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
+#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
+#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
+#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
+#define USTCNT_STOP 0x0200 /* Stop bit transmission */
+#define USTCNT_ODD 0x0400 /* Odd Parity */
+#define USTCNT_PEN 0x0800 /* Parity Enable */
+#define USTCNT_CLKM 0x1000 /* Clock Mode Select */
+#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
+#define USTCNT_RXEN 0x4000 /* Receiver Enable */
+#define USTCNT_UEN 0x8000 /* UART Enable */
+
+/* '328-compatible definitions */
+#define USTCNT_TXAVAILEN USTCNT_TXAE
+#define USTCNT_TXHALFEN USTCNT_TXHE
+#define USTCNT_TXEMPTYEN USTCNT_TXEE
+#define USTCNT_RXREADYEN USTCNT_RXRE
+#define USTCNT_RXHALFEN USTCNT_RXHE
+#define USTCNT_RXFULLEN USTCNT_RXFE
+#define USTCNT_CTSDELTAEN USTCNT_CTSD
+#define USTCNT_ODD_EVEN USTCNT_ODD
+#define USTCNT_PARITYEN USTCNT_PEN
+#define USTCNT_CLKMODE USTCNT_CLKM
+#define USTCNT_UARTEN USTCNT_UEN
+
+/*
+ * UART Baud Control Register
+ */
+#define UBAUD_ADDR 0xfffff902
+#define UBAUD WORD_REF(UBAUD_ADDR)
+
+#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
+#define UBAUD_PRESCALER_SHIFT 0
+#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
+#define UBAUD_DIVIDE_SHIFT 8
+#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
+#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
+
+/*
+ * UART Receiver Register
+ */
+#define URX_ADDR 0xfffff904
+#define URX WORD_REF(URX_ADDR)
+
+#define URX_RXDATA_ADDR 0xfffff905
+#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
+
+#define URX_RXDATA_MASK 0x00ff /* Received data */
+#define URX_RXDATA_SHIFT 0
+#define URX_PARITY_ERROR 0x0100 /* Parity Error */
+#define URX_BREAK 0x0200 /* Break Detected */
+#define URX_FRAME_ERROR 0x0400 /* Framing Error */
+#define URX_OVRUN 0x0800 /* Serial Overrun */
+#define URX_OLD_DATA 0x1000 /* Old data in FIFO */
+#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
+#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
+#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
+
+/*
+ * UART Transmitter Register
+ */
+#define UTX_ADDR 0xfffff906
+#define UTX WORD_REF(UTX_ADDR)
+
+#define UTX_TXDATA_ADDR 0xfffff907
+#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
+
+#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
+#define UTX_TXDATA_SHIFT 0
+#define UTX_CTS_DELTA 0x0100 /* CTS changed */
+#define UTX_CTS_STAT 0x0200 /* CTS State */
+#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
+#define UTX_NOCTS 0x0800 /* Ignore CTS */
+#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
+#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
+#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
+#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
+
+/* '328-compatible definitions */
+#define UTX_CTS_STATUS UTX_CTS_STAT
+#define UTX_IGNORE_CTS UTX_NOCTS
+
+/*
+ * UART Miscellaneous Register
+ */
+#define UMISC_ADDR 0xfffff908
+#define UMISC WORD_REF(UMISC_ADDR)
+
+#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
+#define UMISC_RX_POL 0x0008 /* Receive Polarity */
+#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
+#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
+#define UMISC_RTS 0x0040 /* Set RTS status */
+#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
+#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
+#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
+#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
+#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
+#define UMISC_CLKSRC 0x4000 /* Clock Source */
+#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
+
+/*
+ * UART Non-integer Prescaler Register
+ */
+#define NIPR_ADDR 0xfffff90a
+#define NIPR WORD_REF(NIPR_ADDR)
+
+#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
+#define NIPR_STEP_VALUE_SHIFT 0
+#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
+#define NIPR_SELECT_SHIFT 8
+#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
+
+
+/* generalization of uart control registers to support multiple ports: */
+typedef struct {
+ volatile unsigned short int ustcnt;
+ volatile unsigned short int ubaud;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char rxdata;
+ } b;
+ } urx;
+ union {
+ volatile unsigned short int w;
+ struct {
+ volatile unsigned char status;
+ volatile unsigned char txdata;
+ } b;
+ } utx;
+ volatile unsigned short int umisc;
+ volatile unsigned short int nipr;
+ volatile unsigned short int hmark;
+ volatile unsigned short int unused;
+} __packed m68328_uart;
+
+
+
+
+/**********
+ *
+ * 0xFFFFFAxx -- LCD Controller
+ *
+ **********/
+
+/*
+ * LCD Screen Starting Address Register
+ */
+#define LSSA_ADDR 0xfffffa00
+#define LSSA LONG_REF(LSSA_ADDR)
+
+#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
+
+/*
+ * LCD Virtual Page Width Register
+ */
+#define LVPW_ADDR 0xfffffa05
+#define LVPW BYTE_REF(LVPW_ADDR)
+
+/*
+ * LCD Screen Width Register (not compatible with '328 !!!)
+ */
+#define LXMAX_ADDR 0xfffffa08
+#define LXMAX WORD_REF(LXMAX_ADDR)
+
+#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
+
+/*
+ * LCD Screen Height Register
+ */
+#define LYMAX_ADDR 0xfffffa0a
+#define LYMAX WORD_REF(LYMAX_ADDR)
+
+#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
+
+/*
+ * LCD Cursor X Position Register
+ */
+#define LCXP_ADDR 0xfffffa18
+#define LCXP WORD_REF(LCXP_ADDR)
+
+#define LCXP_CC_MASK 0xc000 /* Cursor Control */
+#define LCXP_CC_TRAMSPARENT 0x0000
+#define LCXP_CC_BLACK 0x4000
+#define LCXP_CC_REVERSED 0x8000
+#define LCXP_CC_WHITE 0xc000
+#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
+
+/*
+ * LCD Cursor Y Position Register
+ */
+#define LCYP_ADDR 0xfffffa1a
+#define LCYP WORD_REF(LCYP_ADDR)
+
+#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
+
+/*
+ * LCD Cursor Width and Heigth Register
+ */
+#define LCWCH_ADDR 0xfffffa1c
+#define LCWCH WORD_REF(LCWCH_ADDR)
+
+#define LCWCH_CH_MASK 0x001f /* Cursor Height */
+#define LCWCH_CH_SHIFT 0
+#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
+#define LCWCH_CW_SHIFT 8
+
+/*
+ * LCD Blink Control Register
+ */
+#define LBLKC_ADDR 0xfffffa1f
+#define LBLKC BYTE_REF(LBLKC_ADDR)
+
+#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
+#define LBLKC_BD_SHIFT 0
+#define LBLKC_BKEN 0x80 /* Blink Enabled */
+
+/*
+ * LCD Panel Interface Configuration Register
+ */
+#define LPICF_ADDR 0xfffffa20
+#define LPICF BYTE_REF(LPICF_ADDR)
+
+#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
+#define LPICF_GS_BW 0x00
+#define LPICF_GS_GRAY_4 0x01
+#define LPICF_GS_GRAY_16 0x02
+#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
+#define LPICF_PBSIZ_1 0x00
+#define LPICF_PBSIZ_2 0x04
+#define LPICF_PBSIZ_4 0x08
+
+/*
+ * LCD Polarity Configuration Register
+ */
+#define LPOLCF_ADDR 0xfffffa21
+#define LPOLCF BYTE_REF(LPOLCF_ADDR)
+
+#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
+#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
+#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
+#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
+
+/*
+ * LACD (LCD Alternate Crystal Direction) Rate Control Register
+ */
+#define LACDRC_ADDR 0xfffffa23
+#define LACDRC BYTE_REF(LACDRC_ADDR)
+
+#define LACDRC_ACDSLT 0x80 /* Signal Source Select */
+#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
+#define LACDRC_ACD_SHIFT 0
+
+/*
+ * LCD Pixel Clock Divider Register
+ */
+#define LPXCD_ADDR 0xfffffa25
+#define LPXCD BYTE_REF(LPXCD_ADDR)
+
+#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
+#define LPXCD_PCD_SHIFT 0
+
+/*
+ * LCD Clocking Control Register
+ */
+#define LCKCON_ADDR 0xfffffa27
+#define LCKCON BYTE_REF(LCKCON_ADDR)
+
+#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
+#define LCKCON_DWS_SHIFT 0
+#define LCKCON_DWIDTH 0x40 /* Display Memory Width */
+#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
+
+/* '328-compatible definitions */
+#define LCKCON_DW_MASK LCKCON_DWS_MASK
+#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
+
+/*
+ * LCD Refresh Rate Adjustment Register
+ */
+#define LRRA_ADDR 0xfffffa29
+#define LRRA BYTE_REF(LRRA_ADDR)
+
+/*
+ * LCD Panning Offset Register
+ */
+#define LPOSR_ADDR 0xfffffa2d
+#define LPOSR BYTE_REF(LPOSR_ADDR)
+
+#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
+#define LPOSR_POS_SHIFT 0
+
+/*
+ * LCD Frame Rate Control Modulation Register
+ */
+#define LFRCM_ADDR 0xfffffa31
+#define LFRCM BYTE_REF(LFRCM_ADDR)
+
+#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
+#define LFRCM_YMOD_SHIFT 0
+#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
+#define LFRCM_XMOD_SHIFT 4
+
+/*
+ * LCD Gray Palette Mapping Register
+ */
+#define LGPMR_ADDR 0xfffffa33
+#define LGPMR BYTE_REF(LGPMR_ADDR)
+
+#define LGPMR_G1_MASK 0x0f
+#define LGPMR_G1_SHIFT 0
+#define LGPMR_G2_MASK 0xf0
+#define LGPMR_G2_SHIFT 4
+
+/*
+ * PWM Contrast Control Register
+ */
+#define PWMR_ADDR 0xfffffa36
+#define PWMR WORD_REF(PWMR_ADDR)
+
+#define PWMR_PW_MASK 0x00ff /* Pulse Width */
+#define PWMR_PW_SHIFT 0
+#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
+#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
+#define PWMR_SRC_LINE 0x0000 /* Line Pulse */
+#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
+#define PWMR_SRC_LCD 0x4000 /* LCD clock */
+
+/**********
+ *
+ * 0xFFFFFBxx -- Real-Time Clock (RTC)
+ *
+ **********/
+
+/*
+ * RTC Hours Minutes and Seconds Register
+ */
+#define RTCTIME_ADDR 0xfffffb00
+#define RTCTIME LONG_REF(RTCTIME_ADDR)
+
+#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCTIME_SECONDS_SHIFT 0
+#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCTIME_MINUTES_SHIFT 16
+#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCTIME_HOURS_SHIFT 24
+
+/*
+ * RTC Alarm Register
+ */
+#define RTCALRM_ADDR 0xfffffb04
+#define RTCALRM LONG_REF(RTCALRM_ADDR)
+
+#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
+#define RTCALRM_SECONDS_SHIFT 0
+#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
+#define RTCALRM_MINUTES_SHIFT 16
+#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
+#define RTCALRM_HOURS_SHIFT 24
+
+/*
+ * Watchdog Timer Register
+ */
+#define WATCHDOG_ADDR 0xfffffb0a
+#define WATCHDOG WORD_REF(WATCHDOG_ADDR)
+
+#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
+#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
+#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */
+#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
+#define WATCHDOG_CNT_SHIFT 8
+
+/*
+ * RTC Control Register
+ */
+#define RTCCTL_ADDR 0xfffffb0c
+#define RTCCTL WORD_REF(RTCCTL_ADDR)
+
+#define RTCCTL_XTL 0x0020 /* Crystal Selection */
+#define RTCCTL_EN 0x0080 /* RTC Enable */
+
+/* '328-compatible definitions */
+#define RTCCTL_384 RTCCTL_XTL
+#define RTCCTL_ENABLE RTCCTL_EN
+
+/*
+ * RTC Interrupt Status Register
+ */
+#define RTCISR_ADDR 0xfffffb0e
+#define RTCISR WORD_REF(RTCISR_ADDR)
+
+#define RTCISR_SW 0x0001 /* Stopwatch timed out */
+#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
+#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
+#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
+#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
+#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
+#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
+#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
+#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
+#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
+#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
+#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
+#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
+#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
+
+/*
+ * RTC Interrupt Enable Register
+ */
+#define RTCIENR_ADDR 0xfffffb10
+#define RTCIENR WORD_REF(RTCIENR_ADDR)
+
+#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
+#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
+#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
+#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
+#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
+#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
+#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
+#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
+#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
+#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
+#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
+#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
+#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
+#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
+
+/*
+ * Stopwatch Minutes Register
+ */
+#define STPWCH_ADDR 0xfffffb12
+#define STPWCH WORD_REF(STPWCH_ADDR)
+
+#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
+#define SPTWCH_CNT_SHIFT 0
+
+/*
+ * RTC Day Count Register
+ */
+#define DAYR_ADDR 0xfffffb1a
+#define DAYR WORD_REF(DAYR_ADDR)
+
+#define DAYR_DAYS_MASK 0x1ff /* Day Setting */
+#define DAYR_DAYS_SHIFT 0
+
+/*
+ * RTC Day Alarm Register
+ */
+#define DAYALARM_ADDR 0xfffffb1c
+#define DAYALARM WORD_REF(DAYALARM_ADDR)
+
+#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
+#define DAYALARM_DAYSAL_SHIFT 0
+
+/**********
+ *
+ * 0xFFFFFCxx -- DRAM Controller
+ *
+ **********/
+
+/*
+ * DRAM Memory Configuration Register
+ */
+#define DRAMMC_ADDR 0xfffffc00
+#define DRAMMC WORD_REF(DRAMMC_ADDR)
+
+#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
+#define DRAMMC_ROW12_PA10 0x0000
+#define DRAMMC_ROW12_PA21 0x4000
+#define DRAMMC_ROW12_PA23 0x8000
+#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
+#define DRAMMC_ROW0_PA11 0x0000
+#define DRAMMC_ROW0_PA22 0x1000
+#define DRAMMC_ROW0_PA23 0x2000
+#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
+#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
+#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
+#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
+#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
+#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
+#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
+#define DRAMMC_REF_MASK 0x001f /* Refresh Cycle */
+#define DRAMMC_REF_SHIFT 0
+
+/*
+ * DRAM Control Register
+ */
+#define DRAMC_ADDR 0xfffffc02
+#define DRAMC WORD_REF(DRAMC_ADDR)
+
+#define DRAMC_DWE 0x0001 /* DRAM Write Enable */
+#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
+#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
+#define DRAMC_SLW 0x0008 /* Slow RAM */
+#define DRAMC_LSP 0x0010 /* Light Sleep */
+#define DRAMC_MSW 0x0020 /* Slow Multiplexing */
+#define DRAMC_WS_MASK 0x00c0 /* Wait-states */
+#define DRAMC_WS_SHIFT 6
+#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
+#define DRAMC_PGSZ_SHIFT 8
+#define DRAMC_PGSZ_256K 0x0000
+#define DRAMC_PGSZ_512K 0x0100
+#define DRAMC_PGSZ_1024K 0x0200
+#define DRAMC_PGSZ_2048K 0x0300
+#define DRAMC_EDO 0x0400 /* EDO DRAM */
+#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
+#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
+#define DRAMC_BC_SHIFT 12
+#define DRAMC_RM 0x4000 /* Refresh Mode */
+#define DRAMC_EN 0x8000 /* DRAM Controller enable */
+
+
+/**********
+ *
+ * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
+ *
+ **********/
+
+/*
+ * ICE Module Address Compare Register
+ */
+#define ICEMACR_ADDR 0xfffffd00
+#define ICEMACR LONG_REF(ICEMACR_ADDR)
+
+/*
+ * ICE Module Address Mask Register
+ */
+#define ICEMAMR_ADDR 0xfffffd04
+#define ICEMAMR LONG_REF(ICEMAMR_ADDR)
+
+/*
+ * ICE Module Control Compare Register
+ */
+#define ICEMCCR_ADDR 0xfffffd08
+#define ICEMCCR WORD_REF(ICEMCCR_ADDR)
+
+#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
+#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
+
+/*
+ * ICE Module Control Mask Register
+ */
+#define ICEMCMR_ADDR 0xfffffd0a
+#define ICEMCMR WORD_REF(ICEMCMR_ADDR)
+
+#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
+#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
+
+/*
+ * ICE Module Control Register
+ */
+#define ICEMCR_ADDR 0xfffffd0c
+#define ICEMCR WORD_REF(ICEMCR_ADDR)
+
+#define ICEMCR_CEN 0x0001 /* Compare Enable */
+#define ICEMCR_PBEN 0x0002 /* Program Break Enable */
+#define ICEMCR_SB 0x0004 /* Single Breakpoint */
+#define ICEMCR_HMDIS 0x0008 /* HardMap disable */
+#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
+
+/*
+ * ICE Module Status Register
+ */
+#define ICEMSR_ADDR 0xfffffd0e
+#define ICEMSR WORD_REF(ICEMSR_ADDR)
+
+#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
+#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
+#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
+#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */
+
+#endif /* _MC68VZ328_H_ */
diff --git a/arch/m68k/include/asm/a.out-core.h b/arch/m68k/include/asm/a.out-core.h
new file mode 100644
index 0000000..ae91ea6
--- /dev/null
+++ b/arch/m68k/include/asm/a.out-core.h
@@ -0,0 +1,68 @@
+/* a.out coredump register dumper
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_A_OUT_CORE_H
+#define _ASM_A_OUT_CORE_H
+
+#ifdef __KERNEL__
+
+#include <linux/user.h>
+#include <linux/elfcore.h>
+#include <linux/mm_types.h>
+
+/*
+ * fill in the user structure for an a.out core dump
+ */
+static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
+{
+ struct switch_stack *sw;
+
+/* changed the size calculations - should hopefully work better. lbt */
+ dump->magic = CMAGIC;
+ dump->start_code = 0;
+ dump->start_stack = rdusp() & ~(PAGE_SIZE - 1);
+ dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
+ dump->u_dsize = ((unsigned long) (current->mm->brk +
+ (PAGE_SIZE-1))) >> PAGE_SHIFT;
+ dump->u_dsize -= dump->u_tsize;
+ dump->u_ssize = 0;
+
+ if (dump->start_stack < TASK_SIZE)
+ dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
+
+ dump->u_ar0 = offsetof(struct user, regs);
+ sw = ((struct switch_stack *)regs) - 1;
+ dump->regs.d1 = regs->d1;
+ dump->regs.d2 = regs->d2;
+ dump->regs.d3 = regs->d3;
+ dump->regs.d4 = regs->d4;
+ dump->regs.d5 = regs->d5;
+ dump->regs.d6 = sw->d6;
+ dump->regs.d7 = sw->d7;
+ dump->regs.a0 = regs->a0;
+ dump->regs.a1 = regs->a1;
+ dump->regs.a2 = regs->a2;
+ dump->regs.a3 = sw->a3;
+ dump->regs.a4 = sw->a4;
+ dump->regs.a5 = sw->a5;
+ dump->regs.a6 = sw->a6;
+ dump->regs.d0 = regs->d0;
+ dump->regs.orig_d0 = regs->orig_d0;
+ dump->regs.stkadj = regs->stkadj;
+ dump->regs.sr = regs->sr;
+ dump->regs.pc = regs->pc;
+ dump->regs.fmtvec = (regs->format << 12) | regs->vector;
+ /* dump floating point stuff */
+ dump->u_fpvalid = dump_fpu (regs, &dump->m68kfp);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_A_OUT_CORE_H */
diff --git a/arch/m68k/include/asm/adb_iop.h b/arch/m68k/include/asm/adb_iop.h
new file mode 100644
index 0000000..195d7fb
--- /dev/null
+++ b/arch/m68k/include/asm/adb_iop.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ADB through the IOP
+ * Written by Joshua M. Thompson
+ */
+
+/* IOP number and channel number for ADB */
+
+#define ADB_IOP IOP_NUM_ISM
+#define ADB_CHAN 2
+
+/* From the A/UX headers...maybe important, maybe not */
+
+#define ADB_IOP_LISTEN 0x01
+#define ADB_IOP_TALK 0x02
+#define ADB_IOP_EXISTS 0x04
+#define ADB_IOP_FLUSH 0x08
+#define ADB_IOP_RESET 0x10
+#define ADB_IOP_INT 0x20
+#define ADB_IOP_POLL 0x40
+#define ADB_IOP_UNINT 0x80
+
+#define AIF_RESET 0x00
+#define AIF_FLUSH 0x01
+#define AIF_LISTEN 0x08
+#define AIF_TALK 0x0C
+
+/* Flag bits in struct adb_iopmsg */
+
+#define ADB_IOP_EXPLICIT 0x80 /* nonzero if explicit command */
+#define ADB_IOP_AUTOPOLL 0x40 /* auto/SRQ polling enabled */
+#define ADB_IOP_SRQ 0x04 /* SRQ detected */
+#define ADB_IOP_TIMEOUT 0x02 /* nonzero if timeout */
+
+#ifndef __ASSEMBLY__
+
+struct adb_iopmsg {
+ __u8 flags; /* ADB flags */
+ __u8 count; /* no. of data bytes */
+ __u8 cmd; /* ADB command */
+ __u8 data[8]; /* ADB data */
+ __u8 spare[21]; /* spare */
+};
+
+#endif /* __ASSEMBLY__ */
diff --git a/arch/m68k/include/asm/amigahw.h b/arch/m68k/include/asm/amigahw.h
new file mode 100644
index 0000000..5ad5681
--- /dev/null
+++ b/arch/m68k/include/asm/amigahw.h
@@ -0,0 +1,325 @@
+/*
+** asm-m68k/amigahw.h -- This header defines some macros and pointers for
+** the various Amiga custom hardware registers.
+** The naming conventions used here conform to those
+** used in the Amiga Hardware Reference Manual, 3rd Edition
+**
+** Copyright 1992 by Greg Harp
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 9/24/92 by Greg Harp
+*/
+
+#ifndef _M68K_AMIGAHW_H
+#define _M68K_AMIGAHW_H
+
+#include <linux/ioport.h>
+
+#include <asm/bootinfo-amiga.h>
+
+
+ /*
+ * Chipsets
+ */
+
+extern unsigned long amiga_chipset;
+
+
+ /*
+ * Miscellaneous
+ */
+
+extern unsigned long amiga_eclock; /* 700 kHz E Peripheral Clock */
+extern unsigned long amiga_colorclock; /* 3.5 MHz Color Clock */
+extern unsigned long amiga_chip_size; /* Chip RAM Size (bytes) */
+extern unsigned char amiga_vblank; /* VBLANK Frequency */
+
+
+#define AMIGAHW_DECLARE(name) unsigned name : 1
+#define AMIGAHW_SET(name) (amiga_hw_present.name = 1)
+#define AMIGAHW_PRESENT(name) (amiga_hw_present.name)
+
+struct amiga_hw_present {
+ /* video hardware */
+ AMIGAHW_DECLARE(AMI_VIDEO); /* Amiga Video */
+ AMIGAHW_DECLARE(AMI_BLITTER); /* Amiga Blitter */
+ AMIGAHW_DECLARE(AMBER_FF); /* Amber Flicker Fixer */
+ /* sound hardware */
+ AMIGAHW_DECLARE(AMI_AUDIO); /* Amiga Audio */
+ /* disk storage interfaces */
+ AMIGAHW_DECLARE(AMI_FLOPPY); /* Amiga Floppy */
+ AMIGAHW_DECLARE(A3000_SCSI); /* SCSI (wd33c93, A3000 alike) */
+ AMIGAHW_DECLARE(A4000_SCSI); /* SCSI (ncr53c710, A4000T alike) */
+ AMIGAHW_DECLARE(A1200_IDE); /* IDE (A1200 alike) */
+ AMIGAHW_DECLARE(A4000_IDE); /* IDE (A4000 alike) */
+ AMIGAHW_DECLARE(CD_ROM); /* CD ROM drive */
+ /* other I/O hardware */
+ AMIGAHW_DECLARE(AMI_KEYBOARD); /* Amiga Keyboard */
+ AMIGAHW_DECLARE(AMI_MOUSE); /* Amiga Mouse */
+ AMIGAHW_DECLARE(AMI_SERIAL); /* Amiga Serial */
+ AMIGAHW_DECLARE(AMI_PARALLEL); /* Amiga Parallel */
+ /* real time clocks */
+ AMIGAHW_DECLARE(A2000_CLK); /* Hardware Clock (A2000 alike) */
+ AMIGAHW_DECLARE(A3000_CLK); /* Hardware Clock (A3000 alike) */
+ /* supporting hardware */
+ AMIGAHW_DECLARE(CHIP_RAM); /* Chip RAM */
+ AMIGAHW_DECLARE(PAULA); /* Paula (8364) */
+ AMIGAHW_DECLARE(DENISE); /* Denise (8362) */
+ AMIGAHW_DECLARE(DENISE_HR); /* Denise (8373) */
+ AMIGAHW_DECLARE(LISA); /* Lisa (8375) */
+ AMIGAHW_DECLARE(AGNUS_PAL); /* Normal/Fat PAL Agnus (8367/8371) */
+ AMIGAHW_DECLARE(AGNUS_NTSC); /* Normal/Fat NTSC Agnus (8361/8370) */
+ AMIGAHW_DECLARE(AGNUS_HR_PAL); /* Fat Hires PAL Agnus (8372) */
+ AMIGAHW_DECLARE(AGNUS_HR_NTSC); /* Fat Hires NTSC Agnus (8372) */
+ AMIGAHW_DECLARE(ALICE_PAL); /* PAL Alice (8374) */
+ AMIGAHW_DECLARE(ALICE_NTSC); /* NTSC Alice (8374) */
+ AMIGAHW_DECLARE(MAGIC_REKICK); /* A3000 Magic Hard Rekick */
+ AMIGAHW_DECLARE(PCMCIA); /* PCMCIA Slot */
+ AMIGAHW_DECLARE(ZORRO); /* Zorro AutoConfig */
+ AMIGAHW_DECLARE(ZORRO3); /* Zorro III */
+};
+
+extern struct amiga_hw_present amiga_hw_present;
+
+struct CUSTOM {
+ unsigned short bltddat;
+ unsigned short dmaconr;
+ unsigned short vposr;
+ unsigned short vhposr;
+ unsigned short dskdatr;
+ unsigned short joy0dat;
+ unsigned short joy1dat;
+ unsigned short clxdat;
+ unsigned short adkconr;
+ unsigned short pot0dat;
+ unsigned short pot1dat;
+ unsigned short potgor;
+ unsigned short serdatr;
+ unsigned short dskbytr;
+ unsigned short intenar;
+ unsigned short intreqr;
+ unsigned char *dskptr;
+ unsigned short dsklen;
+ unsigned short dskdat;
+ unsigned short refptr;
+ unsigned short vposw;
+ unsigned short vhposw;
+ unsigned short copcon;
+ unsigned short serdat;
+ unsigned short serper;
+ unsigned short potgo;
+ unsigned short joytest;
+ unsigned short strequ;
+ unsigned short strvbl;
+ unsigned short strhor;
+ unsigned short strlong;
+ unsigned short bltcon0;
+ unsigned short bltcon1;
+ unsigned short bltafwm;
+ unsigned short bltalwm;
+ unsigned char *bltcpt;
+ unsigned char *bltbpt;
+ unsigned char *bltapt;
+ unsigned char *bltdpt;
+ unsigned short bltsize;
+ unsigned char pad2d;
+ unsigned char bltcon0l;
+ unsigned short bltsizv;
+ unsigned short bltsizh;
+ unsigned short bltcmod;
+ unsigned short bltbmod;
+ unsigned short bltamod;
+ unsigned short bltdmod;
+ unsigned short spare2[4];
+ unsigned short bltcdat;
+ unsigned short bltbdat;
+ unsigned short bltadat;
+ unsigned short spare3[3];
+ unsigned short deniseid;
+ unsigned short dsksync;
+ unsigned short *cop1lc;
+ unsigned short *cop2lc;
+ unsigned short copjmp1;
+ unsigned short copjmp2;
+ unsigned short copins;
+ unsigned short diwstrt;
+ unsigned short diwstop;
+ unsigned short ddfstrt;
+ unsigned short ddfstop;
+ unsigned short dmacon;
+ unsigned short clxcon;
+ unsigned short intena;
+ unsigned short intreq;
+ unsigned short adkcon;
+ struct {
+ unsigned short *audlc;
+ unsigned short audlen;
+ unsigned short audper;
+ unsigned short audvol;
+ unsigned short auddat;
+ unsigned short audspare[2];
+ } aud[4];
+ unsigned char *bplpt[8];
+ unsigned short bplcon0;
+ unsigned short bplcon1;
+ unsigned short bplcon2;
+ unsigned short bplcon3;
+ unsigned short bpl1mod;
+ unsigned short bpl2mod;
+ unsigned short bplcon4;
+ unsigned short clxcon2;
+ unsigned short bpldat[8];
+ unsigned char *sprpt[8];
+ struct {
+ unsigned short pos;
+ unsigned short ctl;
+ unsigned short dataa;
+ unsigned short datab;
+ } spr[8];
+ unsigned short color[32];
+ unsigned short htotal;
+ unsigned short hsstop;
+ unsigned short hbstrt;
+ unsigned short hbstop;
+ unsigned short vtotal;
+ unsigned short vsstop;
+ unsigned short vbstrt;
+ unsigned short vbstop;
+ unsigned short sprhstrt;
+ unsigned short sprhstop;
+ unsigned short bplhstrt;
+ unsigned short bplhstop;
+ unsigned short hhposw;
+ unsigned short hhposr;
+ unsigned short beamcon0;
+ unsigned short hsstrt;
+ unsigned short vsstrt;
+ unsigned short hcenter;
+ unsigned short diwhigh;
+ unsigned short spare4[11];
+ unsigned short fmode;
+};
+
+/*
+ * DMA register bits
+ */
+#define DMAF_SETCLR (0x8000)
+#define DMAF_AUD0 (0x0001)
+#define DMAF_AUD1 (0x0002)
+#define DMAF_AUD2 (0x0004)
+#define DMAF_AUD3 (0x0008)
+#define DMAF_DISK (0x0010)
+#define DMAF_SPRITE (0x0020)
+#define DMAF_BLITTER (0x0040)
+#define DMAF_COPPER (0x0080)
+#define DMAF_RASTER (0x0100)
+#define DMAF_MASTER (0x0200)
+#define DMAF_BLITHOG (0x0400)
+#define DMAF_BLTNZERO (0x2000)
+#define DMAF_BLTDONE (0x4000)
+#define DMAF_ALL (0x01FF)
+
+struct CIA {
+ unsigned char pra; char pad0[0xff];
+ unsigned char prb; char pad1[0xff];
+ unsigned char ddra; char pad2[0xff];
+ unsigned char ddrb; char pad3[0xff];
+ unsigned char talo; char pad4[0xff];
+ unsigned char tahi; char pad5[0xff];
+ unsigned char tblo; char pad6[0xff];
+ unsigned char tbhi; char pad7[0xff];
+ unsigned char todlo; char pad8[0xff];
+ unsigned char todmid; char pad9[0xff];
+ unsigned char todhi; char pada[0x1ff];
+ unsigned char sdr; char padb[0xff];
+ unsigned char icr; char padc[0xff];
+ unsigned char cra; char padd[0xff];
+ unsigned char crb; char pade[0xff];
+};
+
+#define zTwoBase (0x80000000)
+#define ZTWO_PADDR(x) (((unsigned long)(x))-zTwoBase)
+#define ZTWO_VADDR(x) ((void __iomem *)(((unsigned long)(x))+zTwoBase))
+
+#define CUSTOM_PHYSADDR (0xdff000)
+#define amiga_custom ((*(volatile struct CUSTOM *)(zTwoBase+CUSTOM_PHYSADDR)))
+
+#define CIAA_PHYSADDR (0xbfe001)
+#define CIAB_PHYSADDR (0xbfd000)
+#define ciaa ((*(volatile struct CIA *)(zTwoBase + CIAA_PHYSADDR)))
+#define ciab ((*(volatile struct CIA *)(zTwoBase + CIAB_PHYSADDR)))
+
+#define CHIP_PHYSADDR (0x000000)
+
+void amiga_chip_init (void);
+void *amiga_chip_alloc(unsigned long size, const char *name);
+void *amiga_chip_alloc_res(unsigned long size, struct resource *res);
+void amiga_chip_free(void *ptr);
+unsigned long amiga_chip_avail( void ); /*MILAN*/
+extern volatile unsigned short amiga_audio_min_period;
+
+static inline void amifb_video_off(void)
+{
+ if (amiga_chipset == CS_ECS || amiga_chipset == CS_AGA) {
+ /* program Denise/Lisa for a higher maximum play rate */
+ amiga_custom.htotal = 113; /* 31 kHz */
+ amiga_custom.vtotal = 223; /* 70 Hz */
+ amiga_custom.beamcon0 = 0x4390; /* HARDDIS, VAR{BEAM,VSY,HSY,CSY}EN */
+ /* suspend the monitor */
+ amiga_custom.hsstrt = amiga_custom.hsstop = 116;
+ amiga_custom.vsstrt = amiga_custom.vsstop = 226;
+ amiga_audio_min_period = 57;
+ }
+}
+
+struct tod3000 {
+ unsigned int :28, second2:4; /* lower digit */
+ unsigned int :28, second1:4; /* upper digit */
+ unsigned int :28, minute2:4; /* lower digit */
+ unsigned int :28, minute1:4; /* upper digit */
+ unsigned int :28, hour2:4; /* lower digit */
+ unsigned int :28, hour1:4; /* upper digit */
+ unsigned int :28, weekday:4;
+ unsigned int :28, day2:4; /* lower digit */
+ unsigned int :28, day1:4; /* upper digit */
+ unsigned int :28, month2:4; /* lower digit */
+ unsigned int :28, month1:4; /* upper digit */
+ unsigned int :28, year2:4; /* lower digit */
+ unsigned int :28, year1:4; /* upper digit */
+ unsigned int :28, cntrl1:4; /* control-byte 1 */
+ unsigned int :28, cntrl2:4; /* control-byte 2 */
+ unsigned int :28, cntrl3:4; /* control-byte 3 */
+};
+#define TOD3000_CNTRL1_HOLD 0
+#define TOD3000_CNTRL1_FREE 9
+#define tod_3000 ((*(volatile struct tod3000 *)(zTwoBase+0xDC0000)))
+
+struct tod2000 {
+ unsigned int :28, second2:4; /* lower digit */
+ unsigned int :28, second1:4; /* upper digit */
+ unsigned int :28, minute2:4; /* lower digit */
+ unsigned int :28, minute1:4; /* upper digit */
+ unsigned int :28, hour2:4; /* lower digit */
+ unsigned int :28, hour1:4; /* upper digit */
+ unsigned int :28, day2:4; /* lower digit */
+ unsigned int :28, day1:4; /* upper digit */
+ unsigned int :28, month2:4; /* lower digit */
+ unsigned int :28, month1:4; /* upper digit */
+ unsigned int :28, year2:4; /* lower digit */
+ unsigned int :28, year1:4; /* upper digit */
+ unsigned int :28, weekday:4;
+ unsigned int :28, cntrl1:4; /* control-byte 1 */
+ unsigned int :28, cntrl2:4; /* control-byte 2 */
+ unsigned int :28, cntrl3:4; /* control-byte 3 */
+};
+
+#define TOD2000_CNTRL1_HOLD (1<<0)
+#define TOD2000_CNTRL1_BUSY (1<<1)
+#define TOD2000_CNTRL3_24HMODE (1<<2)
+#define TOD2000_HOUR1_PM (1<<2)
+#define tod_2000 ((*(volatile struct tod2000 *)(zTwoBase+0xDC0000)))
+
+#endif /* _M68K_AMIGAHW_H */
diff --git a/arch/m68k/include/asm/amigaints.h b/arch/m68k/include/asm/amigaints.h
new file mode 100644
index 0000000..b1bcdb8
--- /dev/null
+++ b/arch/m68k/include/asm/amigaints.h
@@ -0,0 +1,113 @@
+/*
+** amigaints.h -- Amiga Linux interrupt handling structs and prototypes
+**
+** Copyright 1992 by Greg Harp
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created 10/2/92 by Greg Harp
+*/
+
+#ifndef _ASMm68k_AMIGAINTS_H_
+#define _ASMm68k_AMIGAINTS_H_
+
+#include <asm/irq.h>
+
+/*
+** Amiga Interrupt sources.
+**
+*/
+
+#define AUTO_IRQS (8)
+#define AMI_STD_IRQS (14)
+#define CIA_IRQS (5)
+#define AMI_IRQS (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */
+
+/* builtin serial port interrupts */
+#define IRQ_AMIGA_TBE (IRQ_USER+0)
+#define IRQ_AMIGA_RBF (IRQ_USER+11)
+
+/* floppy disk interrupts */
+#define IRQ_AMIGA_DSKBLK (IRQ_USER+1)
+#define IRQ_AMIGA_DSKSYN (IRQ_USER+12)
+
+/* software interrupts */
+#define IRQ_AMIGA_SOFT (IRQ_USER+2)
+
+/* interrupts from external hardware */
+#define IRQ_AMIGA_PORTS IRQ_AUTO_2
+#define IRQ_AMIGA_EXTER IRQ_AUTO_6
+
+/* copper interrupt */
+#define IRQ_AMIGA_COPPER (IRQ_USER+4)
+
+/* vertical blanking interrupt */
+#define IRQ_AMIGA_VERTB (IRQ_USER+5)
+
+/* Blitter done interrupt */
+#define IRQ_AMIGA_BLIT (IRQ_USER+6)
+
+/* Audio interrupts */
+#define IRQ_AMIGA_AUD0 (IRQ_USER+7)
+#define IRQ_AMIGA_AUD1 (IRQ_USER+8)
+#define IRQ_AMIGA_AUD2 (IRQ_USER+9)
+#define IRQ_AMIGA_AUD3 (IRQ_USER+10)
+
+/* CIA interrupt sources */
+#define IRQ_AMIGA_CIAA (IRQ_USER+14)
+#define IRQ_AMIGA_CIAA_TA (IRQ_USER+14)
+#define IRQ_AMIGA_CIAA_TB (IRQ_USER+15)
+#define IRQ_AMIGA_CIAA_ALRM (IRQ_USER+16)
+#define IRQ_AMIGA_CIAA_SP (IRQ_USER+17)
+#define IRQ_AMIGA_CIAA_FLG (IRQ_USER+18)
+#define IRQ_AMIGA_CIAB (IRQ_USER+19)
+#define IRQ_AMIGA_CIAB_TA (IRQ_USER+19)
+#define IRQ_AMIGA_CIAB_TB (IRQ_USER+20)
+#define IRQ_AMIGA_CIAB_ALRM (IRQ_USER+21)
+#define IRQ_AMIGA_CIAB_SP (IRQ_USER+22)
+#define IRQ_AMIGA_CIAB_FLG (IRQ_USER+23)
+
+
+/* INTREQR masks */
+#define IF_SETCLR 0x8000 /* set/clr bit */
+#define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */
+#define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */
+#define IF_DSKSYN 0x1000 /* disk sync interrupt */
+#define IF_RBF 0x0800 /* serial receive buffer full interrupt */
+#define IF_AUD3 0x0400 /* audio channel 3 done interrupt */
+#define IF_AUD2 0x0200 /* audio channel 2 done interrupt */
+#define IF_AUD1 0x0100 /* audio channel 1 done interrupt */
+#define IF_AUD0 0x0080 /* audio channel 0 done interrupt */
+#define IF_BLIT 0x0040 /* blitter done interrupt */
+#define IF_VERTB 0x0020 /* vertical blanking interrupt */
+#define IF_COPER 0x0010 /* copper interrupt */
+#define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */
+#define IF_SOFT 0x0004 /* software initiated interrupt */
+#define IF_DSKBLK 0x0002 /* diskblock DMA finished */
+#define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */
+
+/* CIA interrupt control register bits */
+
+#define CIA_ICR_TA 0x01
+#define CIA_ICR_TB 0x02
+#define CIA_ICR_ALRM 0x04
+#define CIA_ICR_SP 0x08
+#define CIA_ICR_FLG 0x10
+#define CIA_ICR_ALL 0x1f
+#define CIA_ICR_SETCLR 0x80
+
+extern void amiga_init_IRQ(void);
+
+/* to access the interrupt control registers of CIA's use only
+** these functions, they behave exactly like the amiga os routines
+*/
+
+extern struct ciabase ciaa_base, ciab_base;
+
+extern void cia_init_IRQ(struct ciabase *base);
+extern unsigned char cia_set_irq(struct ciabase *base, unsigned char mask);
+extern unsigned char cia_able_irq(struct ciabase *base, unsigned char mask);
+
+#endif /* asm-m68k/amigaints.h */
diff --git a/arch/m68k/include/asm/amigayle.h b/arch/m68k/include/asm/amigayle.h
new file mode 100644
index 0000000..a01453d
--- /dev/null
+++ b/arch/m68k/include/asm/amigayle.h
@@ -0,0 +1,113 @@
+/*
+** asm-m68k/amigayle.h -- This header defines the registers of the gayle chip
+** found on the Amiga 1200
+** This information was found by disassembling card.resource,
+** so the definitions may not be 100% correct
+** anyone has an official doc ?
+**
+** Copyright 1997 by Alain Malek
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 11/28/97 by Alain Malek
+*/
+
+#ifndef _M68K_AMIGAYLE_H_
+#define _M68K_AMIGAYLE_H_
+
+#include <linux/types.h>
+#include <asm/amigahw.h>
+
+/* memory layout */
+
+#define GAYLE_RAM (0x600000+zTwoBase)
+#define GAYLE_RAMSIZE (0x400000)
+#define GAYLE_ATTRIBUTE (0xa00000+zTwoBase)
+#define GAYLE_ATTRIBUTESIZE (0x020000)
+#define GAYLE_IO (0xa20000+zTwoBase) /* 16bit and even 8bit registers */
+#define GAYLE_IOSIZE (0x010000)
+#define GAYLE_IO_8BITODD (0xa30000+zTwoBase) /* odd 8bit registers */
+
+/* offset for accessing odd IO registers */
+#define GAYLE_ODD (GAYLE_IO_8BITODD-GAYLE_IO-1)
+
+/* GAYLE registers */
+
+struct GAYLE {
+ u_char cardstatus;
+ u_char pad0[0x1000-1];
+
+ u_char intreq;
+ u_char pad1[0x1000-1];
+
+ u_char inten;
+ u_char pad2[0x1000-1];
+
+ u_char config;
+ u_char pad3[0x1000-1];
+};
+
+#define GAYLE_ADDRESS (0xda8000) /* gayle main registers base address */
+
+#define GAYLE_RESET (0xa40000) /* write 0x00 to start reset,
+ read 1 byte to stop reset */
+
+#define gayle (*(volatile struct GAYLE *)(zTwoBase+GAYLE_ADDRESS))
+#define gayle_reset (*(volatile u_char *)(zTwoBase+GAYLE_RESET))
+
+#define gayle_attribute ((volatile u_char *)(GAYLE_ATTRIBUTE))
+
+#if 0
+#define gayle_inb(a) readb( GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
+#define gayle_outb(v,a) writeb( v, GAYLE_IO+(a)+(((a)&1)*GAYLE_ODD) )
+
+#define gayle_inw(a) readw( GAYLE_IO+(a) )
+#define gayle_outw(v,a) writew( v, GAYLE_IO+(a) )
+#endif
+
+/* GAYLE_CARDSTATUS bit def */
+
+#define GAYLE_CS_CCDET 0x40 /* credit card detect */
+#define GAYLE_CS_BVD1 0x20 /* battery voltage detect 1 */
+#define GAYLE_CS_SC 0x20 /* credit card status change */
+#define GAYLE_CS_BVD2 0x10 /* battery voltage detect 2 */
+#define GAYLE_CS_DA 0x10 /* digital audio */
+#define GAYLE_CS_WR 0x08 /* write enable (1 == enabled) */
+#define GAYLE_CS_BSY 0x04 /* credit card busy */
+#define GAYLE_CS_IRQ 0x04 /* interrupt request */
+
+/* GAYLE_IRQ bit def */
+
+#define GAYLE_IRQ_IDE 0x80
+#define GAYLE_IRQ_CCDET 0x40
+#define GAYLE_IRQ_BVD1 0x20
+#define GAYLE_IRQ_SC 0x20
+#define GAYLE_IRQ_BVD2 0x10
+#define GAYLE_IRQ_DA 0x10
+#define GAYLE_IRQ_WR 0x08
+#define GAYLE_IRQ_BSY 0x04
+#define GAYLE_IRQ_IRQ 0x04
+#define GAYLE_IRQ_IDEACK1 0x02
+#define GAYLE_IRQ_IDEACK0 0x01
+
+/* GAYLE_CONFIG bit def
+ (bit 0-1 for program voltage, bit 2-3 for access speed */
+
+#define GAYLE_CFG_0V 0x00
+#define GAYLE_CFG_5V 0x01
+#define GAYLE_CFG_12V 0x02
+
+#define GAYLE_CFG_100NS 0x08
+#define GAYLE_CFG_150NS 0x04
+#define GAYLE_CFG_250NS 0x00
+#define GAYLE_CFG_720NS 0x0c
+
+struct gayle_ide_platform_data {
+ unsigned long base;
+ unsigned long irqport;
+ int explicit_ack; /* A1200 IDE needs explicit ack */
+};
+
+#endif /* asm-m68k/amigayle.h */
diff --git a/arch/m68k/include/asm/amipcmcia.h b/arch/m68k/include/asm/amipcmcia.h
new file mode 100644
index 0000000..6f1ec18
--- /dev/null
+++ b/arch/m68k/include/asm/amipcmcia.h
@@ -0,0 +1,110 @@
+/*
+** asm-m68k/pcmcia.h -- Amiga Linux PCMCIA Definitions
+**
+** Copyright 1997 by Alain Malek
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 12/10/97 by Alain Malek
+*/
+
+#ifndef __AMIGA_PCMCIA_H__
+#define __AMIGA_PCMCIA_H__
+
+#include <asm/amigayle.h>
+
+/* prototypes */
+
+void pcmcia_reset(void);
+int pcmcia_copy_tuple(unsigned char tuple_id, void *tuple, int max_len);
+void pcmcia_program_voltage(int voltage);
+void pcmcia_access_speed(int speed);
+void pcmcia_write_enable(void);
+void pcmcia_write_disable(void);
+
+static inline u_char pcmcia_read_status(void)
+{
+ return (gayle.cardstatus & 0x7c);
+}
+
+static inline u_char pcmcia_get_intreq(void)
+{
+ return (gayle.intreq);
+}
+
+static inline void pcmcia_ack_int(u_char intreq)
+{
+ gayle.intreq = 0xf8;
+}
+
+static inline void pcmcia_enable_irq(void)
+{
+ gayle.inten |= GAYLE_IRQ_IRQ;
+}
+
+static inline void pcmcia_disable_irq(void)
+{
+ gayle.inten &= ~GAYLE_IRQ_IRQ;
+}
+
+#define PCMCIA_INSERTED (gayle.cardstatus & GAYLE_CS_CCDET)
+
+/* valid voltages for pcmcia_ProgramVoltage */
+
+#define PCMCIA_0V 0
+#define PCMCIA_5V 5
+#define PCMCIA_12V 12
+
+/* valid speeds for pcmcia_AccessSpeed */
+
+#define PCMCIA_SPEED_100NS 100
+#define PCMCIA_SPEED_150NS 150
+#define PCMCIA_SPEED_250NS 250
+#define PCMCIA_SPEED_720NS 720
+
+/* PCMCIA Tuple codes */
+
+#define CISTPL_NULL 0x00
+#define CISTPL_DEVICE 0x01
+#define CISTPL_LONGLINK_CB 0x02
+#define CISTPL_CONFIG_CB 0x04
+#define CISTPL_CFTABLE_ENTRY_CB 0x05
+#define CISTPL_LONGLINK_MFC 0x06
+#define CISTPL_BAR 0x07
+#define CISTPL_CHECKSUM 0x10
+#define CISTPL_LONGLINK_A 0x11
+#define CISTPL_LONGLINK_C 0x12
+#define CISTPL_LINKTARGET 0x13
+#define CISTPL_NO_LINK 0x14
+#define CISTPL_VERS_1 0x15
+#define CISTPL_ALTSTR 0x16
+#define CISTPL_DEVICE_A 0x17
+#define CISTPL_JEDEC_C 0x18
+#define CISTPL_JEDEC_A 0x19
+#define CISTPL_CONFIG 0x1a
+#define CISTPL_CFTABLE_ENTRY 0x1b
+#define CISTPL_DEVICE_OC 0x1c
+#define CISTPL_DEVICE_OA 0x1d
+#define CISTPL_DEVICE_GEO 0x1e
+#define CISTPL_DEVICE_GEO_A 0x1f
+#define CISTPL_MANFID 0x20
+#define CISTPL_FUNCID 0x21
+#define CISTPL_FUNCE 0x22
+#define CISTPL_SWIL 0x23
+#define CISTPL_END 0xff
+
+/* FUNCID */
+
+#define CISTPL_FUNCID_MULTI 0x00
+#define CISTPL_FUNCID_MEMORY 0x01
+#define CISTPL_FUNCID_SERIAL 0x02
+#define CISTPL_FUNCID_PARALLEL 0x03
+#define CISTPL_FUNCID_FIXED 0x04
+#define CISTPL_FUNCID_VIDEO 0x05
+#define CISTPL_FUNCID_NETWORK 0x06
+#define CISTPL_FUNCID_AIMS 0x07
+#define CISTPL_FUNCID_SCSI 0x08
+
+#endif
diff --git a/arch/m68k/include/asm/apollohw.h b/arch/m68k/include/asm/apollohw.h
new file mode 100644
index 0000000..52066f3
--- /dev/null
+++ b/arch/m68k/include/asm/apollohw.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* apollohw.h : some structures to access apollo HW */
+
+#ifndef _ASMm68k_APOLLOHW_H_
+#define _ASMm68k_APOLLOHW_H_
+
+#include <linux/types.h>
+
+#include <asm/bootinfo-apollo.h>
+
+
+extern u_long apollo_model;
+
+
+/*
+ see scn2681 data sheet for more info.
+ member names are read_write.
+*/
+
+#define DECLARE_2681_FIELD(x) unsigned char x; unsigned char dummy##x
+
+struct SCN2681 {
+
+ DECLARE_2681_FIELD(mra);
+ DECLARE_2681_FIELD(sra_csra);
+ DECLARE_2681_FIELD(BRGtest_cra);
+ DECLARE_2681_FIELD(rhra_thra);
+ DECLARE_2681_FIELD(ipcr_acr);
+ DECLARE_2681_FIELD(isr_imr);
+ DECLARE_2681_FIELD(ctu_ctur);
+ DECLARE_2681_FIELD(ctl_ctlr);
+ DECLARE_2681_FIELD(mrb);
+ DECLARE_2681_FIELD(srb_csrb);
+ DECLARE_2681_FIELD(tst_crb);
+ DECLARE_2681_FIELD(rhrb_thrb);
+ DECLARE_2681_FIELD(reserved);
+ DECLARE_2681_FIELD(ip_opcr);
+ DECLARE_2681_FIELD(startCnt_setOutBit);
+ DECLARE_2681_FIELD(stopCnt_resetOutBit);
+
+};
+
+struct mc146818 {
+ unsigned char second, alarm_second;
+ unsigned char minute, alarm_minute;
+ unsigned char hours, alarm_hours;
+ unsigned char day_of_week, day_of_month;
+ unsigned char month, year;
+};
+
+
+#define IO_BASE 0x80000000
+
+extern u_long sio01_physaddr;
+extern u_long sio23_physaddr;
+extern u_long rtc_physaddr;
+extern u_long pica_physaddr;
+extern u_long picb_physaddr;
+extern u_long cpuctrl_physaddr;
+extern u_long timer_physaddr;
+
+#define SAU7_SIO01_PHYSADDR 0x10400
+#define SAU7_SIO23_PHYSADDR 0x10500
+#define SAU7_RTC_PHYSADDR 0x10900
+#define SAU7_PICA 0x11000
+#define SAU7_PICB 0x11100
+#define SAU7_CPUCTRL 0x10100
+#define SAU7_TIMER 0x010800
+
+#define SAU8_SIO01_PHYSADDR 0x8400
+#define SAU8_RTC_PHYSADDR 0x8900
+#define SAU8_PICA 0x9400
+#define SAU8_PICB 0x9500
+#define SAU8_CPUCTRL 0x8100
+#define SAU8_TIMER 0x8800
+
+#define sio01 ((*(volatile struct SCN2681 *)(IO_BASE + sio01_physaddr)))
+#define sio23 ((*(volatile struct SCN2681 *)(IO_BASE + sio23_physaddr)))
+#define rtc (((volatile struct mc146818 *)(IO_BASE + rtc_physaddr)))
+#define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr))
+#define pica (IO_BASE + pica_physaddr)
+#define picb (IO_BASE + picb_physaddr)
+#define apollo_timer (IO_BASE + timer_physaddr)
+#define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000))
+
+#define isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE)
+
+#define IRQ_APOLLO IRQ_USER
+
+#endif
diff --git a/arch/m68k/include/asm/asm-offsets.h b/arch/m68k/include/asm/asm-offsets.h
new file mode 100644
index 0000000..d370ee3
--- /dev/null
+++ b/arch/m68k/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/m68k/include/asm/asm-prototypes.h b/arch/m68k/include/asm/asm-prototypes.h
new file mode 100644
index 0000000..22ccb9c
--- /dev/null
+++ b/arch/m68k/include/asm/asm-prototypes.h
@@ -0,0 +1,5 @@
+extern int __divsi3(int, int);
+extern int __modsi3(int, int);
+extern int __mulsi3(int, int);
+extern unsigned int __udivsi3(unsigned int, unsigned int);
+extern unsigned int __umodsi3(unsigned int, unsigned int);
diff --git a/arch/m68k/include/asm/atafd.h b/arch/m68k/include/asm/atafd.h
new file mode 100644
index 0000000..ad7014c
--- /dev/null
+++ b/arch/m68k/include/asm/atafd.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_FD_H
+#define _ASM_M68K_FD_H
+
+/* Definitions for the Atari Floppy driver */
+
+struct atari_format_descr {
+ int track; /* to be formatted */
+ int head; /* "" "" */
+ int sect_offset; /* offset of first sector */
+};
+
+#endif
diff --git a/arch/m68k/include/asm/atafdreg.h b/arch/m68k/include/asm/atafdreg.h
new file mode 100644
index 0000000..c31b491
--- /dev/null
+++ b/arch/m68k/include/asm/atafdreg.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _LINUX_FDREG_H
+#define _LINUX_FDREG_H
+
+/*
+** WD1772 stuff
+ */
+
+/* register codes */
+
+#define FDCSELREG_STP (0x80) /* command/status register */
+#define FDCSELREG_TRA (0x82) /* track register */
+#define FDCSELREG_SEC (0x84) /* sector register */
+#define FDCSELREG_DTA (0x86) /* data register */
+
+/* register names for FDC_READ/WRITE macros */
+
+#define FDCREG_CMD 0
+#define FDCREG_STATUS 0
+#define FDCREG_TRACK 2
+#define FDCREG_SECTOR 4
+#define FDCREG_DATA 6
+
+/* command opcodes */
+
+#define FDCCMD_RESTORE (0x00) /* - */
+#define FDCCMD_SEEK (0x10) /* | */
+#define FDCCMD_STEP (0x20) /* | TYP 1 Commands */
+#define FDCCMD_STIN (0x40) /* | */
+#define FDCCMD_STOT (0x60) /* - */
+#define FDCCMD_RDSEC (0x80) /* - TYP 2 Commands */
+#define FDCCMD_WRSEC (0xa0) /* - " */
+#define FDCCMD_RDADR (0xc0) /* - */
+#define FDCCMD_RDTRA (0xe0) /* | TYP 3 Commands */
+#define FDCCMD_WRTRA (0xf0) /* - */
+#define FDCCMD_FORCI (0xd0) /* - TYP 4 Command */
+
+/* command modifier bits */
+
+#define FDCCMDADD_SR6 (0x00) /* step rate settings */
+#define FDCCMDADD_SR12 (0x01)
+#define FDCCMDADD_SR2 (0x02)
+#define FDCCMDADD_SR3 (0x03)
+#define FDCCMDADD_V (0x04) /* verify */
+#define FDCCMDADD_H (0x08) /* wait for spin-up */
+#define FDCCMDADD_U (0x10) /* update track register */
+#define FDCCMDADD_M (0x10) /* multiple sector access */
+#define FDCCMDADD_E (0x04) /* head settling flag */
+#define FDCCMDADD_P (0x02) /* precompensation off */
+#define FDCCMDADD_A0 (0x01) /* DAM flag */
+
+/* status register bits */
+
+#define FDCSTAT_MOTORON (0x80) /* motor on */
+#define FDCSTAT_WPROT (0x40) /* write protected (FDCCMD_WR*) */
+#define FDCSTAT_SPINUP (0x20) /* motor speed stable (Type I) */
+#define FDCSTAT_DELDAM (0x20) /* sector has deleted DAM (Type II+III) */
+#define FDCSTAT_RECNF (0x10) /* record not found */
+#define FDCSTAT_CRC (0x08) /* CRC error */
+#define FDCSTAT_TR00 (0x04) /* Track 00 flag (Type I) */
+#define FDCSTAT_LOST (0x04) /* Lost Data (Type II+III) */
+#define FDCSTAT_IDX (0x02) /* Index status (Type I) */
+#define FDCSTAT_DRQ (0x02) /* DRQ status (Type II+III) */
+#define FDCSTAT_BUSY (0x01) /* FDC is busy */
+
+
+/* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1 1 -> Side 2 */
+#define DSKSIDE (0x01)
+
+#define DSKDRVNONE (0x06)
+#define DSKDRV0 (0x02)
+#define DSKDRV1 (0x04)
+
+/* step rates */
+#define FDCSTEP_6 0x00
+#define FDCSTEP_12 0x01
+#define FDCSTEP_2 0x02
+#define FDCSTEP_3 0x03
+
+#endif
diff --git a/arch/m68k/include/asm/atari_joystick.h b/arch/m68k/include/asm/atari_joystick.h
new file mode 100644
index 0000000..c4a6a06
--- /dev/null
+++ b/arch/m68k/include/asm/atari_joystick.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _LINUX_ATARI_JOYSTICK_H
+#define _LINUX_ATARI_JOYSTICK_H
+
+/*
+ * linux/include/linux/atari_joystick.h
+ * header file for Atari Joystick driver
+ * by Robert de Vries (robert@and.nl) on 19Jul93
+ */
+
+void atari_joystick_interrupt(char*);
+int atari_joystick_init(void);
+extern int atari_mouse_buttons;
+
+struct joystick_status {
+ char fire;
+ char dir;
+ int ready;
+ int active;
+ wait_queue_head_t wait;
+};
+
+#endif
diff --git a/arch/m68k/include/asm/atari_stdma.h b/arch/m68k/include/asm/atari_stdma.h
new file mode 100644
index 0000000..70de9b1
--- /dev/null
+++ b/arch/m68k/include/asm/atari_stdma.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _atari_stdma_h
+#define _atari_stdma_h
+
+
+#include <linux/interrupt.h>
+
+
+/***************************** Prototypes *****************************/
+
+int stdma_try_lock(irq_handler_t, void *);
+void stdma_lock(irq_handler_t handler, void *data);
+void stdma_release( void );
+int stdma_islocked( void );
+int stdma_is_locked_by(irq_handler_t);
+void stdma_init( void );
+
+/************************* End of Prototypes **************************/
+
+
+
+#endif /* _atari_stdma_h */
diff --git a/arch/m68k/include/asm/atari_stram.h b/arch/m68k/include/asm/atari_stram.h
new file mode 100644
index 0000000..1fc1910
--- /dev/null
+++ b/arch/m68k/include/asm/atari_stram.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_ATARI_STRAM_H
+#define _M68K_ATARI_STRAM_H
+
+/*
+ * Functions for Atari ST-RAM management
+ */
+
+/* public interface */
+void *atari_stram_alloc(unsigned long size, const char *owner);
+void atari_stram_free(void *);
+void *atari_stram_to_virt(unsigned long phys);
+unsigned long atari_stram_to_phys(void *);
+
+/* functions called internally by other parts of the kernel */
+void atari_stram_init(void);
+void atari_stram_reserve_pages(void *start_mem);
+
+#endif /*_M68K_ATARI_STRAM_H */
diff --git a/arch/m68k/include/asm/atarihw.h b/arch/m68k/include/asm/atarihw.h
new file mode 100644
index 0000000..9000b24
--- /dev/null
+++ b/arch/m68k/include/asm/atarihw.h
@@ -0,0 +1,816 @@
+/*
+** linux/atarihw.h -- This header defines some macros and pointers for
+** the various Atari custom hardware registers.
+**
+** Copyright 1994 by Björn Brauel
+**
+** 5/1/94 Roman Hodek:
+** Added definitions for TT specific chips.
+**
+** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>:
+** Finally added definitions for the matrix/codec and the DSP56001 host
+** interface.
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+*/
+
+#ifndef _LINUX_ATARIHW_H_
+#define _LINUX_ATARIHW_H_
+
+#include <linux/types.h>
+#include <asm/bootinfo-atari.h>
+#include <asm/raw_io.h>
+#include <asm/kmap.h>
+
+extern u_long atari_mch_cookie;
+extern u_long atari_mch_type;
+extern u_long atari_switches;
+extern int atari_rtc_year_offset;
+extern int atari_dont_touch_floppy_select;
+
+extern int atari_SCC_reset_done;
+
+/* convenience macros for testing machine type */
+#define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST)
+#define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
+ (atari_mch_cookie & 0xffff) == 0)
+#define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \
+ (atari_mch_cookie & 0xffff) == 0x10)
+#define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT)
+#define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON)
+#define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA)
+#define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40)
+
+/* values for atari_switches */
+#define ATARI_SWITCH_IKBD 0x01
+#define ATARI_SWITCH_MIDI 0x02
+#define ATARI_SWITCH_SND6 0x04
+#define ATARI_SWITCH_SND7 0x08
+#define ATARI_SWITCH_OVSC_SHIFT 16
+#define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT)
+#define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT)
+#define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT)
+#define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT)
+#define ATARI_SWITCH_OVSC_MASK 0xffff0000
+
+/*
+ * Define several Hardware-Chips for indication so that for the ATARI we do
+ * no longer decide whether it is a Falcon or other machine . It's just
+ * important what hardware the machine uses
+ */
+
+/* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */
+
+#define ATARIHW_DECLARE(name) unsigned name : 1
+#define ATARIHW_SET(name) (atari_hw_present.name = 1)
+#define ATARIHW_PRESENT(name) (atari_hw_present.name)
+
+struct atari_hw_present {
+ /* video hardware */
+ ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */
+ ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */
+ ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */
+ ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */
+ /* sound hardware */
+ ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */
+ ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */
+ ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */
+ /* disk storage interfaces */
+ ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */
+ ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */
+ ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */
+ ATARIHW_DECLARE(IDE); /* IDE Interface */
+ ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */
+ /* other I/O hardware */
+ ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari
+ without it... but who knows?) */
+ ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */
+ ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */
+ ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */
+ ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe
+ and Falcon */
+ ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */
+ /* DMA */
+ ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */
+ ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */
+ ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */
+ ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */
+ /* real time clocks */
+ ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */
+ ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */
+ /* supporting hardware */
+ ATARIHW_DECLARE(SCU); /* System Control Unit */
+ ATARIHW_DECLARE(BLITTER); /* Blitter */
+ ATARIHW_DECLARE(VME); /* VME Bus */
+ ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */
+};
+
+extern struct atari_hw_present atari_hw_present;
+
+
+/* Reading the MFP port register gives a machine independent delay, since the
+ * MFP always has a 8 MHz clock. This avoids problems with the varying length
+ * of nops on various machines. Somebody claimed that the tstb takes 600 ns.
+ */
+#define MFPDELAY() \
+ __asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" );
+
+/* Do cache push/invalidate for DMA read/write. This function obeys the
+ * snooping on some machines (Medusa) and processors: The Medusa itself can
+ * snoop, but only the '040 can source data from its cache to DMA writes i.e.,
+ * reads from memory). Both '040 and '060 invalidate cache entries on snooped
+ * DMA reads (i.e., writes to memory).
+ */
+
+
+#define atari_readb raw_inb
+#define atari_writeb raw_outb
+
+#define atari_inb_p raw_inb
+#define atari_outb_p raw_outb
+
+
+
+#include <linux/mm.h>
+#include <asm/cacheflush.h>
+
+static inline void dma_cache_maintenance( unsigned long paddr,
+ unsigned long len,
+ int writeflag )
+
+{
+ if (writeflag) {
+ if (!MACH_IS_MEDUSA || CPU_IS_060)
+ cache_push( paddr, len );
+ }
+ else {
+ if (!MACH_IS_MEDUSA)
+ cache_clear( paddr, len );
+ }
+}
+
+
+/*
+** Shifter
+ */
+#define ST_LOW 0
+#define ST_MID 1
+#define ST_HIGH 2
+#define TT_LOW 7
+#define TT_MID 4
+#define TT_HIGH 6
+
+#define SHF_BAS (0xffff8200)
+struct SHIFTER
+ {
+ u_char pad1;
+ u_char bas_hi;
+ u_char pad2;
+ u_char bas_md;
+ u_char pad3;
+ u_char volatile vcounthi;
+ u_char pad4;
+ u_char volatile vcountmid;
+ u_char pad5;
+ u_char volatile vcountlow;
+ u_char volatile syncmode;
+ u_char pad6;
+ u_char pad7;
+ u_char bas_lo;
+ };
+# define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
+
+#define SHF_FBAS (0xffff820e)
+struct SHIFTER_F030
+ {
+ u_short off_next;
+ u_short scn_width;
+ };
+# define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS))
+
+
+#define SHF_TBAS (0xffff8200)
+struct SHIFTER_TT {
+ u_char char_dummy0;
+ u_char bas_hi; /* video mem base addr, high and mid byte */
+ u_char char_dummy1;
+ u_char bas_md;
+ u_char char_dummy2;
+ u_char vcount_hi; /* pointer to currently displayed byte */
+ u_char char_dummy3;
+ u_char vcount_md;
+ u_char char_dummy4;
+ u_char vcount_lo;
+ u_short st_sync; /* ST compatible sync mode register, unused */
+ u_char char_dummy5;
+ u_char bas_lo; /* video mem addr, low byte */
+ u_char char_dummy6[2+3*16];
+ /* $ffff8240: */
+ u_short color_reg[16]; /* 16 color registers */
+ u_char st_shiftmode; /* ST compatible shift mode register, unused */
+ u_char char_dummy7;
+ u_short tt_shiftmode; /* TT shift mode register */
+
+
+};
+#define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS))
+
+/* values for shifter_tt->tt_shiftmode */
+#define TT_SHIFTER_STLOW 0x0000
+#define TT_SHIFTER_STMID 0x0100
+#define TT_SHIFTER_STHIGH 0x0200
+#define TT_SHIFTER_TTLOW 0x0700
+#define TT_SHIFTER_TTMID 0x0400
+#define TT_SHIFTER_TTHIGH 0x0600
+#define TT_SHIFTER_MODEMASK 0x0700
+#define TT_SHIFTER_NUMMODE 0x0008
+#define TT_SHIFTER_PALETTE_MASK 0x000f
+#define TT_SHIFTER_GRAYMODE 0x1000
+
+/* 256 TT palette registers */
+#define TT_PALETTE_BASE (0xffff8400)
+#define tt_palette ((volatile u_short *)TT_PALETTE_BASE)
+
+#define TT_PALETTE_RED_MASK 0x0f00
+#define TT_PALETTE_GREEN_MASK 0x00f0
+#define TT_PALETTE_BLUE_MASK 0x000f
+
+/*
+** Falcon030 VIDEL Video Controller
+** for description see File 'linux\tools\atari\hardware.txt
+ */
+#define f030_col ((u_long *) 0xffff9800)
+#define f030_xreg ((u_short*) 0xffff8282)
+#define f030_yreg ((u_short*) 0xffff82a2)
+#define f030_creg ((u_short*) 0xffff82c0)
+#define f030_sreg ((u_short*) 0xffff8260)
+#define f030_mreg ((u_short*) 0xffff820a)
+#define f030_linewidth ((u_short*) 0xffff820e)
+#define f030_hscroll ((u_char*) 0xffff8265)
+
+#define VIDEL_BAS (0xffff8260)
+struct VIDEL {
+ u_short st_shift;
+ u_short pad1;
+ u_char xoffset_s;
+ u_char xoffset;
+ u_short f_shift;
+ u_char pad2[0x1a];
+ u_short hht;
+ u_short hbb;
+ u_short hbe;
+ u_short hdb;
+ u_short hde;
+ u_short hss;
+ u_char pad3[0x14];
+ u_short vft;
+ u_short vbb;
+ u_short vbe;
+ u_short vdb;
+ u_short vde;
+ u_short vss;
+ u_char pad4[0x12];
+ u_short control;
+ u_short mode;
+};
+#define videl ((*(volatile struct VIDEL *)VIDEL_BAS))
+
+/*
+** DMA/WD1772 Disk Controller
+ */
+
+#define FWD_BAS (0xffff8604)
+struct DMA_WD
+ {
+ u_short fdc_acces_seccount;
+ u_short dma_mode_status;
+ u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */
+ u_char dma_hi;
+ u_char char_dummy2;
+ u_char dma_md;
+ u_char char_dummy3;
+ u_char dma_lo;
+ u_short fdc_speed;
+ };
+# define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS))
+/* alias */
+#define st_dma dma_wd
+/* The two highest bytes of an extended DMA as a short; this is a must
+ * for the Medusa.
+ */
+#define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608))
+
+/*
+** YM2149 Sound Chip
+** access in bytes
+ */
+
+#define YM_BAS (0xffff8800)
+struct SOUND_YM
+ {
+ u_char rd_data_reg_sel;
+ u_char char_dummy1;
+ u_char wd_data;
+ };
+#define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS))
+
+/* TT SCSI DMA */
+
+#define TT_SCSI_DMA_BAS (0xffff8700)
+struct TT_DMA {
+ u_char char_dummy0;
+ u_char dma_addr_hi;
+ u_char char_dummy1;
+ u_char dma_addr_hmd;
+ u_char char_dummy2;
+ u_char dma_addr_lmd;
+ u_char char_dummy3;
+ u_char dma_addr_lo;
+ u_char char_dummy4;
+ u_char dma_cnt_hi;
+ u_char char_dummy5;
+ u_char dma_cnt_hmd;
+ u_char char_dummy6;
+ u_char dma_cnt_lmd;
+ u_char char_dummy7;
+ u_char dma_cnt_lo;
+ u_long dma_restdata;
+ u_short dma_ctrl;
+};
+#define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS))
+
+/* TT SCSI Controller 5380 */
+
+#define TT_5380_BAS (0xffff8781)
+struct TT_5380 {
+ u_char scsi_data;
+ u_char char_dummy1;
+ u_char scsi_icr;
+ u_char char_dummy2;
+ u_char scsi_mode;
+ u_char char_dummy3;
+ u_char scsi_tcr;
+ u_char char_dummy4;
+ u_char scsi_idstat;
+ u_char char_dummy5;
+ u_char scsi_dmastat;
+ u_char char_dummy6;
+ u_char scsi_targrcv;
+ u_char char_dummy7;
+ u_char scsi_inircv;
+};
+#define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS))
+#define tt_scsi_regp ((volatile char *)TT_5380_BAS)
+
+
+/*
+** Falcon DMA Sound Subsystem
+ */
+
+#define MATRIX_BASE (0xffff8930)
+struct MATRIX
+{
+ u_short source;
+ u_short destination;
+ u_char external_frequency_divider;
+ u_char internal_frequency_divider;
+};
+#define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE)
+
+#define CODEC_BASE (0xffff8936)
+struct CODEC
+{
+ u_char tracks;
+ u_char input_source;
+#define CODEC_SOURCE_ADC 1
+#define CODEC_SOURCE_MATRIX 2
+ u_char adc_source;
+#define ADC_SOURCE_RIGHT_PSG 1
+#define ADC_SOURCE_LEFT_PSG 2
+ u_char gain;
+#define CODEC_GAIN_RIGHT 0x0f
+#define CODEC_GAIN_LEFT 0xf0
+ u_char attenuation;
+#define CODEC_ATTENUATION_RIGHT 0x0f
+#define CODEC_ATTENUATION_LEFT 0xf0
+ u_char unused1;
+ u_char status;
+#define CODEC_OVERFLOW_RIGHT 1
+#define CODEC_OVERFLOW_LEFT 2
+ u_char unused2, unused3, unused4, unused5;
+ u_char gpio_directions;
+#define CODEC_GPIO_IN 0
+#define CODEC_GPIO_OUT 1
+ u_char unused6;
+ u_char gpio_data;
+};
+#define falcon_codec (*(volatile struct CODEC *)CODEC_BASE)
+
+/*
+** Falcon Blitter
+*/
+
+#define BLT_BAS (0xffff8a00)
+
+struct BLITTER
+ {
+ u_short halftone[16];
+ u_short src_x_inc;
+ u_short src_y_inc;
+ u_long src_address;
+ u_short endmask1;
+ u_short endmask2;
+ u_short endmask3;
+ u_short dst_x_inc;
+ u_short dst_y_inc;
+ u_long dst_address;
+ u_short wd_per_line;
+ u_short ln_per_bb;
+ u_short hlf_op_reg;
+ u_short log_op_reg;
+ u_short lin_nm_reg;
+ u_short skew_reg;
+ };
+# define blitter ((*(volatile struct BLITTER *)BLT_BAS))
+
+
+/*
+** SCC Z8530
+ */
+
+#define SCC_BAS (0xffff8c81)
+struct SCC
+ {
+ u_char cha_a_ctrl;
+ u_char char_dummy1;
+ u_char cha_a_data;
+ u_char char_dummy2;
+ u_char cha_b_ctrl;
+ u_char char_dummy3;
+ u_char cha_b_data;
+ };
+# define atari_scc ((*(volatile struct SCC*)SCC_BAS))
+
+/* The ESCC (Z85230) in an Atari ST. The channels are reversed! */
+# define st_escc ((*(volatile struct SCC*)0xfffffa31))
+# define st_escc_dsr ((*(volatile char *)0xfffffa39))
+
+/* TT SCC DMA Controller (same chip as SCSI DMA) */
+
+#define TT_SCC_DMA_BAS (0xffff8c00)
+#define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS))
+
+/*
+** VIDEL Palette Register
+ */
+
+#define FPL_BAS (0xffff9800)
+struct VIDEL_PALETTE
+ {
+ u_long reg[256];
+ };
+# define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS))
+
+
+/*
+** Falcon DSP Host Interface
+ */
+
+#define DSP56K_HOST_INTERFACE_BASE (0xffffa200)
+struct DSP56K_HOST_INTERFACE {
+ u_char icr;
+#define DSP56K_ICR_RREQ 0x01
+#define DSP56K_ICR_TREQ 0x02
+#define DSP56K_ICR_HF0 0x08
+#define DSP56K_ICR_HF1 0x10
+#define DSP56K_ICR_HM0 0x20
+#define DSP56K_ICR_HM1 0x40
+#define DSP56K_ICR_INIT 0x80
+
+ u_char cvr;
+#define DSP56K_CVR_HV_MASK 0x1f
+#define DSP56K_CVR_HC 0x80
+
+ u_char isr;
+#define DSP56K_ISR_RXDF 0x01
+#define DSP56K_ISR_TXDE 0x02
+#define DSP56K_ISR_TRDY 0x04
+#define DSP56K_ISR_HF2 0x08
+#define DSP56K_ISR_HF3 0x10
+#define DSP56K_ISR_DMA 0x40
+#define DSP56K_ISR_HREQ 0x80
+
+ u_char ivr;
+
+ union {
+ u_char b[4];
+ u_short w[2];
+ u_long l;
+ } data;
+};
+#define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE))
+
+/*
+** MFP 68901
+ */
+
+#define MFP_BAS (0xfffffa01)
+struct MFP
+ {
+ u_char par_dt_reg;
+ u_char char_dummy1;
+ u_char active_edge;
+ u_char char_dummy2;
+ u_char data_dir;
+ u_char char_dummy3;
+ u_char int_en_a;
+ u_char char_dummy4;
+ u_char int_en_b;
+ u_char char_dummy5;
+ u_char int_pn_a;
+ u_char char_dummy6;
+ u_char int_pn_b;
+ u_char char_dummy7;
+ u_char int_sv_a;
+ u_char char_dummy8;
+ u_char int_sv_b;
+ u_char char_dummy9;
+ u_char int_mk_a;
+ u_char char_dummy10;
+ u_char int_mk_b;
+ u_char char_dummy11;
+ u_char vec_adr;
+ u_char char_dummy12;
+ u_char tim_ct_a;
+ u_char char_dummy13;
+ u_char tim_ct_b;
+ u_char char_dummy14;
+ u_char tim_ct_cd;
+ u_char char_dummy15;
+ u_char tim_dt_a;
+ u_char char_dummy16;
+ u_char tim_dt_b;
+ u_char char_dummy17;
+ u_char tim_dt_c;
+ u_char char_dummy18;
+ u_char tim_dt_d;
+ u_char char_dummy19;
+ u_char sync_char;
+ u_char char_dummy20;
+ u_char usart_ctr;
+ u_char char_dummy21;
+ u_char rcv_stat;
+ u_char char_dummy22;
+ u_char trn_stat;
+ u_char char_dummy23;
+ u_char usart_dta;
+ };
+# define st_mfp ((*(volatile struct MFP*)MFP_BAS))
+
+/* TT's second MFP */
+
+#define TT_MFP_BAS (0xfffffa81)
+# define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS))
+
+
+/* TT System Control Unit */
+
+#define TT_SCU_BAS (0xffff8e01)
+struct TT_SCU {
+ u_char sys_mask;
+ u_char char_dummy1;
+ u_char sys_stat;
+ u_char char_dummy2;
+ u_char softint;
+ u_char char_dummy3;
+ u_char vmeint;
+ u_char char_dummy4;
+ u_char gp_reg1;
+ u_char char_dummy5;
+ u_char gp_reg2;
+ u_char char_dummy6;
+ u_char vme_mask;
+ u_char char_dummy7;
+ u_char vme_stat;
+};
+#define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS))
+
+/* TT real time clock */
+
+#define TT_RTC_BAS (0xffff8961)
+struct TT_RTC {
+ u_char regsel;
+ u_char dummy;
+ u_char data;
+};
+#define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS))
+
+
+/*
+** ACIA 6850
+ */
+/* constants for the ACIA registers */
+
+/* baudrate selection and reset (Baudrate = clock/factor) */
+#define ACIA_DIV1 0
+#define ACIA_DIV16 1
+#define ACIA_DIV64 2
+#define ACIA_RESET 3
+
+/* character format */
+#define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */
+#define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */
+#define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */
+#define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */
+#define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */
+#define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */
+#define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */
+#define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */
+
+/* transmit control */
+#define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */
+#define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */
+#define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */
+#define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */
+
+/* receive control */
+#define ACIA_RID (0<<7) /* RxINT disabled */
+#define ACIA_RIE (1<<7) /* RxINT enabled */
+
+/* status fields of the ACIA */
+#define ACIA_RDRF 1 /* Receive Data Register Full */
+#define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */
+#define ACIA_DCD (1<<2) /* Data Carrier Detect */
+#define ACIA_CTS (1<<3) /* Clear To Send */
+#define ACIA_FE (1<<4) /* Framing Error */
+#define ACIA_OVRN (1<<5) /* Receiver Overrun */
+#define ACIA_PE (1<<6) /* Parity Error */
+#define ACIA_IRQ (1<<7) /* Interrupt Request */
+
+#define ACIA_BAS (0xfffffc00)
+struct ACIA
+ {
+ u_char key_ctrl;
+ u_char char_dummy1;
+ u_char key_data;
+ u_char char_dummy2;
+ u_char mid_ctrl;
+ u_char char_dummy3;
+ u_char mid_data;
+ };
+# define acia ((*(volatile struct ACIA*)ACIA_BAS))
+
+#define TT_DMASND_BAS (0xffff8900)
+struct TT_DMASND {
+ u_char int_ctrl; /* Falcon: Interrupt control */
+ u_char ctrl;
+ u_char pad2;
+ u_char bas_hi;
+ u_char pad3;
+ u_char bas_mid;
+ u_char pad4;
+ u_char bas_low;
+ u_char pad5;
+ u_char addr_hi;
+ u_char pad6;
+ u_char addr_mid;
+ u_char pad7;
+ u_char addr_low;
+ u_char pad8;
+ u_char end_hi;
+ u_char pad9;
+ u_char end_mid;
+ u_char pad10;
+ u_char end_low;
+ u_char pad11[12];
+ u_char track_select; /* Falcon */
+ u_char mode;
+ u_char pad12[14];
+ /* Falcon only: */
+ u_short cbar_src;
+ u_short cbar_dst;
+ u_char ext_div;
+ u_char int_div;
+ u_char rec_track_select;
+ u_char dac_src;
+ u_char adc_src;
+ u_char input_gain;
+ u_short output_atten;
+};
+# define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS))
+
+#define DMASND_MFP_INT_REPLAY 0x01
+#define DMASND_MFP_INT_RECORD 0x02
+#define DMASND_TIMERA_INT_REPLAY 0x04
+#define DMASND_TIMERA_INT_RECORD 0x08
+
+#define DMASND_CTRL_OFF 0x00
+#define DMASND_CTRL_ON 0x01
+#define DMASND_CTRL_REPEAT 0x02
+#define DMASND_CTRL_RECORD_ON 0x10
+#define DMASND_CTRL_RECORD_OFF 0x00
+#define DMASND_CTRL_RECORD_REPEAT 0x20
+#define DMASND_CTRL_SELECT_REPLAY 0x00
+#define DMASND_CTRL_SELECT_RECORD 0x80
+#define DMASND_MODE_MONO 0x80
+#define DMASND_MODE_STEREO 0x00
+#define DMASND_MODE_8BIT 0x00
+#define DMASND_MODE_16BIT 0x40 /* Falcon only */
+#define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */
+#define DMASND_MODE_12KHZ 0x01
+#define DMASND_MODE_25KHZ 0x02
+#define DMASND_MODE_50KHZ 0x03
+
+
+#define DMASNDSetBase(bufstart) \
+ do { \
+ tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \
+ tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \
+ tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \
+ } while( 0 )
+
+#define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \
+ (tt_dmasnd.addr_mid << 8) + \
+ (tt_dmasnd.addr_low))
+
+#define DMASNDSetEnd(bufend) \
+ do { \
+ tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \
+ tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \
+ tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \
+ } while( 0 )
+
+
+#define TT_MICROWIRE_BAS (0xffff8922)
+struct TT_MICROWIRE {
+ u_short data;
+ u_short mask;
+};
+# define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS))
+
+#define MW_LM1992_ADDR 0x0400
+
+#define MW_LM1992_VOLUME(dB) \
+ (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2)))
+#define MW_LM1992_BALLEFT(dB) \
+ (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
+#define MW_LM1992_BALRIGHT(dB) \
+ (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2)))
+#define MW_LM1992_TREBLE(dB) \
+ (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
+#define MW_LM1992_BASS(dB) \
+ (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6)))
+
+#define MW_LM1992_PSG_LOW 0x000
+#define MW_LM1992_PSG_HIGH 0x001
+#define MW_LM1992_PSG_OFF 0x002
+
+#define MSTE_RTC_BAS (0xfffffc21)
+
+struct MSTE_RTC {
+ u_char sec_ones;
+ u_char dummy1;
+ u_char sec_tens;
+ u_char dummy2;
+ u_char min_ones;
+ u_char dummy3;
+ u_char min_tens;
+ u_char dummy4;
+ u_char hr_ones;
+ u_char dummy5;
+ u_char hr_tens;
+ u_char dummy6;
+ u_char weekday;
+ u_char dummy7;
+ u_char day_ones;
+ u_char dummy8;
+ u_char day_tens;
+ u_char dummy9;
+ u_char mon_ones;
+ u_char dummy10;
+ u_char mon_tens;
+ u_char dummy11;
+ u_char year_ones;
+ u_char dummy12;
+ u_char year_tens;
+ u_char dummy13;
+ u_char mode;
+ u_char dummy14;
+ u_char test;
+ u_char dummy15;
+ u_char reset;
+};
+
+#define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS))
+
+/*
+** EtherNAT add-on card for Falcon - combined ethernet and USB adapter
+*/
+
+#define ATARI_ETHERNAT_PHYS_ADDR 0x80000000
+
+#endif /* linux/atarihw.h */
+
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h
new file mode 100644
index 0000000..6321c44
--- /dev/null
+++ b/arch/m68k/include/asm/atariints.h
@@ -0,0 +1,208 @@
+/*
+** atariints.h -- Atari Linux interrupt handling structs and prototypes
+**
+** Copyright 1994 by Björn Brauel
+**
+** 5/2/94 Roman Hodek:
+** TT interrupt definitions added.
+**
+** 12/02/96: (Roman)
+** Adapted to new int handling scheme (see ataints.c); revised numbering
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+*/
+
+#ifndef _LINUX_ATARIINTS_H_
+#define _LINUX_ATARIINTS_H_
+
+#include <asm/irq.h>
+#include <asm/atarihw.h>
+
+/*
+** Atari Interrupt sources.
+**
+*/
+
+#define STMFP_SOURCE_BASE 8
+#define TTMFP_SOURCE_BASE 24
+#define SCC_SOURCE_BASE 40
+#define VME_SOURCE_BASE 56
+#define VME_MAX_SOURCES 16
+
+#define NUM_ATARI_SOURCES 141
+
+/* convert vector number to int source number */
+#define IRQ_VECTOR_TO_SOURCE(v) ((v) - ((v) < 0x20 ? 0x18 : (0x40-8)))
+
+/* convert irq_handler index to vector number */
+#define IRQ_SOURCE_TO_VECTOR(i) ((i) + ((i) < 8 ? 0x18 : (0x40-8)))
+
+/* ST-MFP interrupts */
+#define IRQ_MFP_BUSY (8)
+#define IRQ_MFP_DCD (9)
+#define IRQ_MFP_CTS (10)
+#define IRQ_MFP_GPU (11)
+#define IRQ_MFP_TIMD (12)
+#define IRQ_MFP_TIMC (13)
+#define IRQ_MFP_ACIA (14)
+#define IRQ_MFP_FDC (15)
+#define IRQ_MFP_ACSI IRQ_MFP_FDC
+#define IRQ_MFP_FSCSI IRQ_MFP_FDC
+#define IRQ_MFP_IDE IRQ_MFP_FDC
+#define IRQ_MFP_TIMB (16)
+#define IRQ_MFP_SERERR (17)
+#define IRQ_MFP_SEREMPT (18)
+#define IRQ_MFP_RECERR (19)
+#define IRQ_MFP_RECFULL (20)
+#define IRQ_MFP_TIMA (21)
+#define IRQ_MFP_RI (22)
+#define IRQ_MFP_MMD (23)
+
+/* TT-MFP interrupts */
+#define IRQ_TT_MFP_IO0 (24)
+#define IRQ_TT_MFP_IO1 (25)
+#define IRQ_TT_MFP_SCC (26)
+#define IRQ_TT_MFP_RI (27)
+#define IRQ_TT_MFP_TIMD (28)
+#define IRQ_TT_MFP_TIMC (29)
+#define IRQ_TT_MFP_DRVRDY (30)
+#define IRQ_TT_MFP_SCSIDMA (31)
+#define IRQ_TT_MFP_TIMB (32)
+#define IRQ_TT_MFP_SERERR (33)
+#define IRQ_TT_MFP_SEREMPT (34)
+#define IRQ_TT_MFP_RECERR (35)
+#define IRQ_TT_MFP_RECFULL (36)
+#define IRQ_TT_MFP_TIMA (37)
+#define IRQ_TT_MFP_RTC (38)
+#define IRQ_TT_MFP_SCSI (39)
+
+/* SCC interrupts */
+#define IRQ_SCCB_TX (40)
+#define IRQ_SCCB_STAT (42)
+#define IRQ_SCCB_RX (44)
+#define IRQ_SCCB_SPCOND (46)
+#define IRQ_SCCA_TX (48)
+#define IRQ_SCCA_STAT (50)
+#define IRQ_SCCA_RX (52)
+#define IRQ_SCCA_SPCOND (54)
+
+/* shared MFP timer D interrupts - hires timer for EtherNEC et al. */
+#define IRQ_MFP_TIMER1 (64)
+#define IRQ_MFP_TIMER2 (65)
+#define IRQ_MFP_TIMER3 (66)
+#define IRQ_MFP_TIMER4 (67)
+#define IRQ_MFP_TIMER5 (68)
+#define IRQ_MFP_TIMER6 (69)
+#define IRQ_MFP_TIMER7 (70)
+#define IRQ_MFP_TIMER8 (71)
+
+#define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */
+#define INT_TICKS 246 /* to make sched_time = 99.902... HZ */
+
+
+#define MFP_ENABLE 0
+#define MFP_PENDING 1
+#define MFP_SERVICE 2
+#define MFP_MASK 3
+
+/* Utility functions for setting/clearing bits in the interrupt registers of
+ * the MFP. 'type' should be constant, if 'irq' is constant, too, code size is
+ * reduced. set_mfp_bit() is nonsense for PENDING and SERVICE registers. */
+
+static inline int get_mfp_bit( unsigned irq, int type )
+
+{ unsigned char mask, *reg;
+
+ mask = 1 << (irq & 7);
+ reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
+ ((irq & 8) >> 2) + (((irq-8) & 16) << 3);
+ return( *reg & mask );
+}
+
+static inline void set_mfp_bit( unsigned irq, int type )
+
+{ unsigned char mask, *reg;
+
+ mask = 1 << (irq & 7);
+ reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
+ ((irq & 8) >> 2) + (((irq-8) & 16) << 3);
+ __asm__ __volatile__ ( "orb %0,%1"
+ : : "di" (mask), "m" (*reg) : "memory" );
+}
+
+static inline void clear_mfp_bit( unsigned irq, int type )
+
+{ unsigned char mask, *reg;
+
+ mask = ~(1 << (irq & 7));
+ reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
+ ((irq & 8) >> 2) + (((irq-8) & 16) << 3);
+ if (type == MFP_PENDING || type == MFP_SERVICE)
+ __asm__ __volatile__ ( "moveb %0,%1"
+ : : "di" (mask), "m" (*reg) : "memory" );
+ else
+ __asm__ __volatile__ ( "andb %0,%1"
+ : : "di" (mask), "m" (*reg) : "memory" );
+}
+
+/*
+ * {en,dis}able_irq have the usual semantics of temporary blocking the
+ * interrupt, but not losing requests that happen between disabling and
+ * enabling. This is done with the MFP mask registers.
+ */
+
+static inline void atari_enable_irq( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
+ set_mfp_bit( irq, MFP_MASK );
+}
+
+static inline void atari_disable_irq( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
+ clear_mfp_bit( irq, MFP_MASK );
+}
+
+/*
+ * In opposite to {en,dis}able_irq, requests between turn{off,on}_irq are not
+ * "stored"
+ */
+
+static inline void atari_turnon_irq( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
+ set_mfp_bit( irq, MFP_ENABLE );
+}
+
+static inline void atari_turnoff_irq( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
+ clear_mfp_bit( irq, MFP_ENABLE );
+ clear_mfp_bit( irq, MFP_PENDING );
+}
+
+static inline void atari_clear_pending_irq( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return;
+ clear_mfp_bit( irq, MFP_PENDING );
+}
+
+static inline int atari_irq_pending( unsigned irq )
+
+{
+ if (irq < STMFP_SOURCE_BASE || irq >= SCC_SOURCE_BASE) return( 0 );
+ return( get_mfp_bit( irq, MFP_PENDING ) );
+}
+
+unsigned int atari_register_vme_int(void);
+void atari_unregister_vme_int(unsigned int);
+
+#endif /* linux/atariints.h */
diff --git a/arch/m68k/include/asm/atarikb.h b/arch/m68k/include/asm/atarikb.h
new file mode 100644
index 0000000..68f3622
--- /dev/null
+++ b/arch/m68k/include/asm/atarikb.h
@@ -0,0 +1,44 @@
+/*
+** atarikb.h -- This header contains the prototypes of functions of
+** the intelligent keyboard of the Atari needed by the
+** mouse and joystick drivers.
+**
+** Copyright 1994 by Robert de Vries
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created: 20 Feb 1994 by Robert de Vries
+*/
+
+#ifndef _LINUX_ATARIKB_H
+#define _LINUX_ATARIKB_H
+
+void ikbd_write(const char *, int);
+void ikbd_mouse_button_action(int mode);
+void ikbd_mouse_rel_pos(void);
+void ikbd_mouse_abs_pos(int xmax, int ymax);
+void ikbd_mouse_kbd_mode(int dx, int dy);
+void ikbd_mouse_thresh(int x, int y);
+void ikbd_mouse_scale(int x, int y);
+void ikbd_mouse_pos_get(int *x, int *y);
+void ikbd_mouse_pos_set(int x, int y);
+void ikbd_mouse_y0_bot(void);
+void ikbd_mouse_y0_top(void);
+void ikbd_mouse_disable(void);
+void ikbd_joystick_event_on(void);
+void ikbd_joystick_event_off(void);
+void ikbd_joystick_get_state(void);
+void ikbd_joystick_disable(void);
+
+/* Hook for MIDI serial driver */
+extern void (*atari_MIDI_interrupt_hook) (void);
+/* Hook for keyboard inputdev driver */
+extern void (*atari_input_keyboard_interrupt_hook) (unsigned char, char);
+/* Hook for mouse inputdev driver */
+extern void (*atari_input_mouse_interrupt_hook) (char *);
+
+int atari_keyb_init(void);
+
+#endif /* _LINUX_ATARIKB_H */
diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h
new file mode 100644
index 0000000..47228b0
--- /dev/null
+++ b/arch/m68k/include/asm/atomic.h
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ARCH_M68K_ATOMIC__
+#define __ARCH_M68K_ATOMIC__
+
+#include <linux/types.h>
+#include <linux/irqflags.h>
+#include <asm/cmpxchg.h>
+#include <asm/barrier.h>
+
+/*
+ * Atomic operations that C can't guarantee us. Useful for
+ * resource counting etc..
+ */
+
+/*
+ * We do not have SMP m68k systems, so we don't have to deal with that.
+ */
+
+#define ATOMIC_INIT(i) { (i) }
+
+#define atomic_read(v) READ_ONCE((v)->counter)
+#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
+
+/*
+ * The ColdFire parts cannot do some immediate to memory operations,
+ * so for them we do not specify the "i" asm constraint.
+ */
+#ifdef CONFIG_COLDFIRE
+#define ASM_DI "d"
+#else
+#define ASM_DI "di"
+#endif
+
+#define ATOMIC_OP(op, c_op, asm_op) \
+static inline void atomic_##op(int i, atomic_t *v) \
+{ \
+ __asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\
+} \
+
+#ifdef CONFIG_RMW_INSNS
+
+#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
+static inline int atomic_##op##_return(int i, atomic_t *v) \
+{ \
+ int t, tmp; \
+ \
+ __asm__ __volatile__( \
+ "1: movel %2,%1\n" \
+ " " #asm_op "l %3,%1\n" \
+ " casl %2,%1,%0\n" \
+ " jne 1b" \
+ : "+m" (*v), "=&d" (t), "=&d" (tmp) \
+ : "g" (i), "2" (atomic_read(v))); \
+ return t; \
+}
+
+#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
+static inline int atomic_fetch_##op(int i, atomic_t *v) \
+{ \
+ int t, tmp; \
+ \
+ __asm__ __volatile__( \
+ "1: movel %2,%1\n" \
+ " " #asm_op "l %3,%1\n" \
+ " casl %2,%1,%0\n" \
+ " jne 1b" \
+ : "+m" (*v), "=&d" (t), "=&d" (tmp) \
+ : "g" (i), "2" (atomic_read(v))); \
+ return tmp; \
+}
+
+#else
+
+#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
+static inline int atomic_##op##_return(int i, atomic_t * v) \
+{ \
+ unsigned long flags; \
+ int t; \
+ \
+ local_irq_save(flags); \
+ t = (v->counter c_op i); \
+ local_irq_restore(flags); \
+ \
+ return t; \
+}
+
+#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
+static inline int atomic_fetch_##op(int i, atomic_t * v) \
+{ \
+ unsigned long flags; \
+ int t; \
+ \
+ local_irq_save(flags); \
+ t = v->counter; \
+ v->counter c_op i; \
+ local_irq_restore(flags); \
+ \
+ return t; \
+}
+
+#endif /* CONFIG_RMW_INSNS */
+
+#define ATOMIC_OPS(op, c_op, asm_op) \
+ ATOMIC_OP(op, c_op, asm_op) \
+ ATOMIC_OP_RETURN(op, c_op, asm_op) \
+ ATOMIC_FETCH_OP(op, c_op, asm_op)
+
+ATOMIC_OPS(add, +=, add)
+ATOMIC_OPS(sub, -=, sub)
+
+#undef ATOMIC_OPS
+#define ATOMIC_OPS(op, c_op, asm_op) \
+ ATOMIC_OP(op, c_op, asm_op) \
+ ATOMIC_FETCH_OP(op, c_op, asm_op)
+
+ATOMIC_OPS(and, &=, and)
+ATOMIC_OPS(or, |=, or)
+ATOMIC_OPS(xor, ^=, eor)
+
+#undef ATOMIC_OPS
+#undef ATOMIC_FETCH_OP
+#undef ATOMIC_OP_RETURN
+#undef ATOMIC_OP
+
+static inline void atomic_inc(atomic_t *v)
+{
+ __asm__ __volatile__("addql #1,%0" : "+m" (*v));
+}
+#define atomic_inc atomic_inc
+
+static inline void atomic_dec(atomic_t *v)
+{
+ __asm__ __volatile__("subql #1,%0" : "+m" (*v));
+}
+#define atomic_dec atomic_dec
+
+static inline int atomic_dec_and_test(atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
+ return c != 0;
+}
+#define atomic_dec_and_test atomic_dec_and_test
+
+static inline int atomic_dec_and_test_lt(atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__(
+ "subql #1,%1; slt %0"
+ : "=d" (c), "=m" (*v)
+ : "m" (*v));
+ return c != 0;
+}
+
+static inline int atomic_inc_and_test(atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
+ return c != 0;
+}
+#define atomic_inc_and_test atomic_inc_and_test
+
+#ifdef CONFIG_RMW_INSNS
+
+#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+
+#else /* !CONFIG_RMW_INSNS */
+
+static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
+{
+ unsigned long flags;
+ int prev;
+
+ local_irq_save(flags);
+ prev = atomic_read(v);
+ if (prev == old)
+ atomic_set(v, new);
+ local_irq_restore(flags);
+ return prev;
+}
+
+static inline int atomic_xchg(atomic_t *v, int new)
+{
+ unsigned long flags;
+ int prev;
+
+ local_irq_save(flags);
+ prev = atomic_read(v);
+ atomic_set(v, new);
+ local_irq_restore(flags);
+ return prev;
+}
+
+#endif /* !CONFIG_RMW_INSNS */
+
+static inline int atomic_sub_and_test(int i, atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__("subl %2,%1; seq %0"
+ : "=d" (c), "+m" (*v)
+ : ASM_DI (i));
+ return c != 0;
+}
+#define atomic_sub_and_test atomic_sub_and_test
+
+static inline int atomic_add_negative(int i, atomic_t *v)
+{
+ char c;
+ __asm__ __volatile__("addl %2,%1; smi %0"
+ : "=d" (c), "+m" (*v)
+ : ASM_DI (i));
+ return c != 0;
+}
+#define atomic_add_negative atomic_add_negative
+
+#endif /* __ARCH_M68K_ATOMIC __ */
diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h
new file mode 100644
index 0000000..d979f38
--- /dev/null
+++ b/arch/m68k/include/asm/bitops.h
@@ -0,0 +1,534 @@
+#ifndef _M68K_BITOPS_H
+#define _M68K_BITOPS_H
+/*
+ * Copyright 1992, Linus Torvalds.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _LINUX_BITOPS_H
+#error only <linux/bitops.h> can be included directly
+#endif
+
+#include <linux/compiler.h>
+#include <asm/barrier.h>
+
+/*
+ * Bit access functions vary across the ColdFire and 68k families.
+ * So we will break them out here, and then macro in the ones we want.
+ *
+ * ColdFire - supports standard bset/bclr/bchg with register operand only
+ * 68000 - supports standard bset/bclr/bchg with memory operand
+ * >= 68020 - also supports the bfset/bfclr/bfchg instructions
+ *
+ * Although it is possible to use only the bset/bclr/bchg with register
+ * operands on all platforms you end up with larger generated code.
+ * So we use the best form possible on a given platform.
+ */
+
+static inline void bset_reg_set_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bset %1,(%0)"
+ :
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+}
+
+static inline void bset_mem_set_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bset %1,%0"
+ : "+m" (*p)
+ : "di" (nr & 7));
+}
+
+static inline void bfset_mem_set_bit(int nr, volatile unsigned long *vaddr)
+{
+ __asm__ __volatile__ ("bfset %1{%0:#1}"
+ :
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define set_bit(nr, vaddr) bset_reg_set_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define set_bit(nr, vaddr) bset_mem_set_bit(nr, vaddr)
+#else
+#define set_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bset_mem_set_bit(nr, vaddr) : \
+ bfset_mem_set_bit(nr, vaddr))
+#endif
+
+#define __set_bit(nr, vaddr) set_bit(nr, vaddr)
+
+
+static inline void bclr_reg_clear_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bclr %1,(%0)"
+ :
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+}
+
+static inline void bclr_mem_clear_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bclr %1,%0"
+ : "+m" (*p)
+ : "di" (nr & 7));
+}
+
+static inline void bfclr_mem_clear_bit(int nr, volatile unsigned long *vaddr)
+{
+ __asm__ __volatile__ ("bfclr %1{%0:#1}"
+ :
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define clear_bit(nr, vaddr) bclr_reg_clear_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define clear_bit(nr, vaddr) bclr_mem_clear_bit(nr, vaddr)
+#else
+#define clear_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bclr_mem_clear_bit(nr, vaddr) : \
+ bfclr_mem_clear_bit(nr, vaddr))
+#endif
+
+#define __clear_bit(nr, vaddr) clear_bit(nr, vaddr)
+
+
+static inline void bchg_reg_change_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bchg %1,(%0)"
+ :
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+}
+
+static inline void bchg_mem_change_bit(int nr, volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+
+ __asm__ __volatile__ ("bchg %1,%0"
+ : "+m" (*p)
+ : "di" (nr & 7));
+}
+
+static inline void bfchg_mem_change_bit(int nr, volatile unsigned long *vaddr)
+{
+ __asm__ __volatile__ ("bfchg %1{%0:#1}"
+ :
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define change_bit(nr, vaddr) bchg_reg_change_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define change_bit(nr, vaddr) bchg_mem_change_bit(nr, vaddr)
+#else
+#define change_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bchg_mem_change_bit(nr, vaddr) : \
+ bfchg_mem_change_bit(nr, vaddr))
+#endif
+
+#define __change_bit(nr, vaddr) change_bit(nr, vaddr)
+
+
+static inline int test_bit(int nr, const volatile unsigned long *vaddr)
+{
+ return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
+}
+
+
+static inline int bset_reg_test_and_set_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bset %2,(%1); sne %0"
+ : "=d" (retval)
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+ return retval;
+}
+
+static inline int bset_mem_test_and_set_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bset %2,%1; sne %0"
+ : "=d" (retval), "+m" (*p)
+ : "di" (nr & 7));
+ return retval;
+}
+
+static inline int bfset_mem_test_and_set_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char retval;
+
+ __asm__ __volatile__ ("bfset %2{%1:#1}; sne %0"
+ : "=d" (retval)
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+ return retval;
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define test_and_set_bit(nr, vaddr) bset_reg_test_and_set_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define test_and_set_bit(nr, vaddr) bset_mem_test_and_set_bit(nr, vaddr)
+#else
+#define test_and_set_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bset_mem_test_and_set_bit(nr, vaddr) : \
+ bfset_mem_test_and_set_bit(nr, vaddr))
+#endif
+
+#define __test_and_set_bit(nr, vaddr) test_and_set_bit(nr, vaddr)
+
+
+static inline int bclr_reg_test_and_clear_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bclr %2,(%1); sne %0"
+ : "=d" (retval)
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+ return retval;
+}
+
+static inline int bclr_mem_test_and_clear_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bclr %2,%1; sne %0"
+ : "=d" (retval), "+m" (*p)
+ : "di" (nr & 7));
+ return retval;
+}
+
+static inline int bfclr_mem_test_and_clear_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char retval;
+
+ __asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0"
+ : "=d" (retval)
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+ return retval;
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define test_and_clear_bit(nr, vaddr) bclr_reg_test_and_clear_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define test_and_clear_bit(nr, vaddr) bclr_mem_test_and_clear_bit(nr, vaddr)
+#else
+#define test_and_clear_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bclr_mem_test_and_clear_bit(nr, vaddr) : \
+ bfclr_mem_test_and_clear_bit(nr, vaddr))
+#endif
+
+#define __test_and_clear_bit(nr, vaddr) test_and_clear_bit(nr, vaddr)
+
+
+static inline int bchg_reg_test_and_change_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bchg %2,(%1); sne %0"
+ : "=d" (retval)
+ : "a" (p), "di" (nr & 7)
+ : "memory");
+ return retval;
+}
+
+static inline int bchg_mem_test_and_change_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char *p = (char *)vaddr + (nr ^ 31) / 8;
+ char retval;
+
+ __asm__ __volatile__ ("bchg %2,%1; sne %0"
+ : "=d" (retval), "+m" (*p)
+ : "di" (nr & 7));
+ return retval;
+}
+
+static inline int bfchg_mem_test_and_change_bit(int nr,
+ volatile unsigned long *vaddr)
+{
+ char retval;
+
+ __asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0"
+ : "=d" (retval)
+ : "d" (nr ^ 31), "o" (*vaddr)
+ : "memory");
+ return retval;
+}
+
+#if defined(CONFIG_COLDFIRE)
+#define test_and_change_bit(nr, vaddr) bchg_reg_test_and_change_bit(nr, vaddr)
+#elif defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#define test_and_change_bit(nr, vaddr) bchg_mem_test_and_change_bit(nr, vaddr)
+#else
+#define test_and_change_bit(nr, vaddr) (__builtin_constant_p(nr) ? \
+ bchg_mem_test_and_change_bit(nr, vaddr) : \
+ bfchg_mem_test_and_change_bit(nr, vaddr))
+#endif
+
+#define __test_and_change_bit(nr, vaddr) test_and_change_bit(nr, vaddr)
+
+
+/*
+ * The true 68020 and more advanced processors support the "bfffo"
+ * instruction for finding bits. ColdFire and simple 68000 parts
+ * (including CPU32) do not support this. They simply use the generic
+ * functions.
+ */
+#if defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+#include <asm-generic/bitops/ffz.h>
+#else
+
+static inline int find_first_zero_bit(const unsigned long *vaddr,
+ unsigned size)
+{
+ const unsigned long *p = vaddr;
+ int res = 32;
+ unsigned int words;
+ unsigned long num;
+
+ if (!size)
+ return 0;
+
+ words = (size + 31) >> 5;
+ while (!(num = ~*p++)) {
+ if (!--words)
+ goto out;
+ }
+
+ __asm__ __volatile__ ("bfffo %1{#0,#0},%0"
+ : "=d" (res) : "d" (num & -num));
+ res ^= 31;
+out:
+ res += ((long)p - (long)vaddr - 4) * 8;
+ return res < size ? res : size;
+}
+#define find_first_zero_bit find_first_zero_bit
+
+static inline int find_next_zero_bit(const unsigned long *vaddr, int size,
+ int offset)
+{
+ const unsigned long *p = vaddr + (offset >> 5);
+ int bit = offset & 31UL, res;
+
+ if (offset >= size)
+ return size;
+
+ if (bit) {
+ unsigned long num = ~*p++ & (~0UL << bit);
+ offset -= bit;
+
+ /* Look for zero in first longword */
+ __asm__ __volatile__ ("bfffo %1{#0,#0},%0"
+ : "=d" (res) : "d" (num & -num));
+ if (res < 32) {
+ offset += res ^ 31;
+ return offset < size ? offset : size;
+ }
+ offset += 32;
+
+ if (offset >= size)
+ return size;
+ }
+ /* No zero yet, search remaining full bytes for a zero */
+ return offset + find_first_zero_bit(p, size - offset);
+}
+#define find_next_zero_bit find_next_zero_bit
+
+static inline int find_first_bit(const unsigned long *vaddr, unsigned size)
+{
+ const unsigned long *p = vaddr;
+ int res = 32;
+ unsigned int words;
+ unsigned long num;
+
+ if (!size)
+ return 0;
+
+ words = (size + 31) >> 5;
+ while (!(num = *p++)) {
+ if (!--words)
+ goto out;
+ }
+
+ __asm__ __volatile__ ("bfffo %1{#0,#0},%0"
+ : "=d" (res) : "d" (num & -num));
+ res ^= 31;
+out:
+ res += ((long)p - (long)vaddr - 4) * 8;
+ return res < size ? res : size;
+}
+#define find_first_bit find_first_bit
+
+static inline int find_next_bit(const unsigned long *vaddr, int size,
+ int offset)
+{
+ const unsigned long *p = vaddr + (offset >> 5);
+ int bit = offset & 31UL, res;
+
+ if (offset >= size)
+ return size;
+
+ if (bit) {
+ unsigned long num = *p++ & (~0UL << bit);
+ offset -= bit;
+
+ /* Look for one in first longword */
+ __asm__ __volatile__ ("bfffo %1{#0,#0},%0"
+ : "=d" (res) : "d" (num & -num));
+ if (res < 32) {
+ offset += res ^ 31;
+ return offset < size ? offset : size;
+ }
+ offset += 32;
+
+ if (offset >= size)
+ return size;
+ }
+ /* No one yet, search remaining full bytes for a one */
+ return offset + find_first_bit(p, size - offset);
+}
+#define find_next_bit find_next_bit
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+ int res;
+
+ __asm__ __volatile__ ("bfffo %1{#0,#0},%0"
+ : "=d" (res) : "d" (~word & -~word));
+ return res ^ 31;
+}
+
+#endif
+
+#include <asm-generic/bitops/find.h>
+
+#ifdef __KERNEL__
+
+#if defined(CONFIG_CPU_HAS_NO_BITFIELDS)
+
+/*
+ * The newer ColdFire family members support a "bitrev" instruction
+ * and we can use that to implement a fast ffs. Older Coldfire parts,
+ * and normal 68000 parts don't have anything special, so we use the
+ * generic functions for those.
+ */
+#if (defined(__mcfisaaplus__) || defined(__mcfisac__)) && \
+ !defined(CONFIG_M68000) && !defined(CONFIG_MCPU32)
+static inline unsigned long __ffs(unsigned long x)
+{
+ __asm__ __volatile__ ("bitrev %0; ff1 %0"
+ : "=d" (x)
+ : "0" (x));
+ return x;
+}
+
+static inline int ffs(int x)
+{
+ if (!x)
+ return 0;
+ return __ffs(x) + 1;
+}
+
+#else
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/__ffs.h>
+#endif
+
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+
+#else
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static inline int ffs(int x)
+{
+ int cnt;
+
+ __asm__ ("bfffo %1{#0:#0},%0"
+ : "=d" (cnt)
+ : "dm" (x & -x));
+ return 32 - cnt;
+}
+
+static inline unsigned long __ffs(unsigned long x)
+{
+ return ffs(x) - 1;
+}
+
+/*
+ * fls: find last bit set.
+ */
+static inline int fls(int x)
+{
+ int cnt;
+
+ __asm__ ("bfffo %1{#0,#0},%0"
+ : "=d" (cnt)
+ : "dm" (x));
+ return 32 - cnt;
+}
+
+static inline int __fls(int x)
+{
+ return fls(x) - 1;
+}
+
+#endif
+
+/* Simple test-and-set bit locks */
+#define test_and_set_bit_lock test_and_set_bit
+#define clear_bit_unlock clear_bit
+#define __clear_bit_unlock clear_bit_unlock
+
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/le.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/hweight.h>
+#endif /* __KERNEL__ */
+
+#endif /* _M68K_BITOPS_H */
diff --git a/arch/m68k/include/asm/blinken.h b/arch/m68k/include/asm/blinken.h
new file mode 100644
index 0000000..0626582
--- /dev/null
+++ b/arch/m68k/include/asm/blinken.h
@@ -0,0 +1,32 @@
+/*
+** asm/blinken.h -- m68k blinkenlights support (currently hp300 only)
+**
+** (c) 1998 Phil Blundell <philb@gnu.org>
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+*/
+
+#ifndef _M68K_BLINKEN_H
+#define _M68K_BLINKEN_H
+
+#include <asm/setup.h>
+#include <asm/io.h>
+
+#define HP300_LEDS 0xf001ffff
+
+extern unsigned char hp300_ledstate;
+
+static __inline__ void blinken_leds(int on, int off)
+{
+ if (MACH_IS_HP300)
+ {
+ hp300_ledstate |= on;
+ hp300_ledstate &= ~off;
+ out_8(HP300_LEDS, ~hp300_ledstate);
+ }
+}
+
+#endif
diff --git a/arch/m68k/include/asm/bootinfo.h b/arch/m68k/include/asm/bootinfo.h
new file mode 100644
index 0000000..81c91af
--- /dev/null
+++ b/arch/m68k/include/asm/bootinfo.h
@@ -0,0 +1,34 @@
+/*
+** asm/bootinfo.h -- Definition of the Linux/m68k boot information structure
+**
+** Copyright 1992 by Greg Harp
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+*/
+
+#ifndef _M68K_BOOTINFO_H
+#define _M68K_BOOTINFO_H
+
+#include <uapi/asm/bootinfo.h>
+
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_BOOTINFO_PROC
+extern void save_bootinfo(const struct bi_record *bi);
+#else
+static inline void save_bootinfo(const struct bi_record *bi) {}
+#endif
+
+#ifdef CONFIG_UBOOT
+void process_uboot_commandline(char *commandp, int size);
+#else
+static inline void process_uboot_commandline(char *commandp, int size) {}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+
+#endif /* _M68K_BOOTINFO_H */
diff --git a/arch/m68k/include/asm/bootstd.h b/arch/m68k/include/asm/bootstd.h
new file mode 100644
index 0000000..1dab93d
--- /dev/null
+++ b/arch/m68k/include/asm/bootstd.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* bootstd.h: Bootloader system call interface
+ *
+ * (c) 1999, Rt-Control, Inc.
+ */
+
+#ifndef __BOOTSTD_H__
+#define __BOOTSTD_H__
+
+#define NR_BSC 21 /* last used bootloader system call */
+
+#define __BN_reset 0 /* reset and start the bootloader */
+#define __BN_test 1 /* tests the system call interface */
+#define __BN_exec 2 /* executes a bootloader image */
+#define __BN_exit 3 /* terminates a bootloader image */
+#define __BN_program 4 /* program FLASH from a chain */
+#define __BN_erase 5 /* erase sector(s) of FLASH */
+#define __BN_open 6
+#define __BN_write 7
+#define __BN_read 8
+#define __BN_close 9
+#define __BN_mmap 10 /* map a file descriptor into memory */
+#define __BN_munmap 11 /* remove a file to memory mapping */
+#define __BN_gethwaddr 12 /* get the hardware address of my interfaces */
+#define __BN_getserialnum 13 /* get the serial number of this board */
+#define __BN_getbenv 14 /* get a bootloader envvar */
+#define __BN_setbenv 15 /* get a bootloader envvar */
+#define __BN_setpmask 16 /* set the protection mask */
+#define __BN_readenv 17 /* read environment variables */
+#define __BN_flash_chattr_range 18
+#define __BN_flash_erase_range 19
+#define __BN_flash_write_range 20
+
+/* Calling conventions compatible to (uC)linux/68k
+ * We use similar macros to call into the bootloader as for uClinux
+ */
+
+#define __bsc_return(type, res) \
+do { \
+ if ((unsigned long)(res) >= (unsigned long)(-64)) { \
+ /* let errno be a function, preserve res in %d0 */ \
+ int __err = -(res); \
+ errno = __err; \
+ res = -1; \
+ } \
+ return (type)(res); \
+} while (0)
+
+#define _bsc0(type,name) \
+type name(void) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#define _bsc1(type,name,atype,a) \
+type name(atype a) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ register long __a __asm__ ("%d1") = (long)a; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res), "d" (__a) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#define _bsc2(type,name,atype,a,btype,b) \
+type name(atype a, btype b) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ register long __a __asm__ ("%d1") = (long)a; \
+ register long __b __asm__ ("%d2") = (long)b; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res), "d" (__a), "d" (__b) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#define _bsc3(type,name,atype,a,btype,b,ctype,c) \
+type name(atype a, btype b, ctype c) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ register long __a __asm__ ("%d1") = (long)a; \
+ register long __b __asm__ ("%d2") = (long)b; \
+ register long __c __asm__ ("%d3") = (long)c; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res), "d" (__a), "d" (__b), \
+ "d" (__c) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#define _bsc4(type,name,atype,a,btype,b,ctype,c,dtype,d) \
+type name(atype a, btype b, ctype c, dtype d) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ register long __a __asm__ ("%d1") = (long)a; \
+ register long __b __asm__ ("%d2") = (long)b; \
+ register long __c __asm__ ("%d3") = (long)c; \
+ register long __d __asm__ ("%d4") = (long)d; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res), "d" (__a), "d" (__b), \
+ "d" (__c), "d" (__d) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#define _bsc5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
+type name(atype a, btype b, ctype c, dtype d, etype e) \
+{ \
+ register long __res __asm__ ("%d0") = __BN_##name; \
+ register long __a __asm__ ("%d1") = (long)a; \
+ register long __b __asm__ ("%d2") = (long)b; \
+ register long __c __asm__ ("%d3") = (long)c; \
+ register long __d __asm__ ("%d4") = (long)d; \
+ register long __e __asm__ ("%d5") = (long)e; \
+ __asm__ __volatile__ ("trap #2" \
+ : "=g" (__res) \
+ : "0" (__res), "d" (__a), "d" (__b), \
+ "d" (__c), "d" (__d), "d" (__e) \
+ ); \
+ __bsc_return(type,__res); \
+}
+
+#endif /* __BOOTSTD_H__ */
diff --git a/arch/m68k/include/asm/bug.h b/arch/m68k/include/asm/bug.h
new file mode 100644
index 0000000..275dca1
--- /dev/null
+++ b/arch/m68k/include/asm/bug.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_BUG_H
+#define _M68K_BUG_H
+
+#ifdef CONFIG_MMU
+#ifdef CONFIG_BUG
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+#ifndef CONFIG_SUN3
+#define BUG() do { \
+ pr_crit("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
+ barrier_before_unreachable(); \
+ __builtin_trap(); \
+} while (0)
+#else
+#define BUG() do { \
+ pr_crit("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
+ barrier_before_unreachable(); \
+ panic("BUG!"); \
+} while (0)
+#endif
+#else
+#define BUG() do { \
+ barrier_before_unreachable(); \
+ __builtin_trap(); \
+} while (0)
+#endif
+
+#define HAVE_ARCH_BUG
+#endif
+#endif /* CONFIG_MMU */
+
+#include <asm-generic/bug.h>
+
+#endif
diff --git a/arch/m68k/include/asm/bugs.h b/arch/m68k/include/asm/bugs.h
new file mode 100644
index 0000000..7455306
--- /dev/null
+++ b/arch/m68k/include/asm/bugs.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/asm-m68k/bugs.h
+ *
+ * Copyright (C) 1994 Linus Torvalds
+ */
+
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Needs:
+ * void check_bugs(void);
+ */
+
+#ifdef CONFIG_MMU
+extern void check_bugs(void); /* in arch/m68k/kernel/setup.c */
+#else
+static void check_bugs(void)
+{
+}
+#endif
diff --git a/arch/m68k/include/asm/bvme6000hw.h b/arch/m68k/include/asm/bvme6000hw.h
new file mode 100644
index 0000000..7b1309b
--- /dev/null
+++ b/arch/m68k/include/asm/bvme6000hw.h
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_BVME6000HW_H_
+#define _M68K_BVME6000HW_H_
+
+#include <asm/irq.h>
+
+/*
+ * PIT structure
+ */
+
+#define BVME_PIT_BASE 0xffa00000
+
+typedef struct {
+ unsigned char
+ pad_a[3], pgcr,
+ pad_b[3], psrr,
+ pad_c[3], paddr,
+ pad_d[3], pbddr,
+ pad_e[3], pcddr,
+ pad_f[3], pivr,
+ pad_g[3], pacr,
+ pad_h[3], pbcr,
+ pad_i[3], padr,
+ pad_j[3], pbdr,
+ pad_k[3], paar,
+ pad_l[3], pbar,
+ pad_m[3], pcdr,
+ pad_n[3], psr,
+ pad_o[3], res1,
+ pad_p[3], res2,
+ pad_q[3], tcr,
+ pad_r[3], tivr,
+ pad_s[3], res3,
+ pad_t[3], cprh,
+ pad_u[3], cprm,
+ pad_v[3], cprl,
+ pad_w[3], res4,
+ pad_x[3], crh,
+ pad_y[3], crm,
+ pad_z[3], crl,
+ pad_A[3], tsr,
+ pad_B[3], res5;
+} PitRegs_t, *PitRegsPtr;
+
+#define bvmepit ((*(volatile PitRegsPtr)(BVME_PIT_BASE)))
+
+#define BVME_RTC_BASE 0xff900000
+
+typedef struct {
+ unsigned char
+ pad_a[3], msr,
+ pad_b[3], t0cr_rtmr,
+ pad_c[3], t1cr_omr,
+ pad_d[3], pfr_icr0,
+ pad_e[3], irr_icr1,
+ pad_f[3], bcd_tenms,
+ pad_g[3], bcd_sec,
+ pad_h[3], bcd_min,
+ pad_i[3], bcd_hr,
+ pad_j[3], bcd_dom,
+ pad_k[3], bcd_mth,
+ pad_l[3], bcd_year,
+ pad_m[3], bcd_ujcc,
+ pad_n[3], bcd_hjcc,
+ pad_o[3], bcd_dow,
+ pad_p[3], t0lsb,
+ pad_q[3], t0msb,
+ pad_r[3], t1lsb,
+ pad_s[3], t1msb,
+ pad_t[3], cmp_sec,
+ pad_u[3], cmp_min,
+ pad_v[3], cmp_hr,
+ pad_w[3], cmp_dom,
+ pad_x[3], cmp_mth,
+ pad_y[3], cmp_dow,
+ pad_z[3], sav_sec,
+ pad_A[3], sav_min,
+ pad_B[3], sav_hr,
+ pad_C[3], sav_dom,
+ pad_D[3], sav_mth,
+ pad_E[3], ram,
+ pad_F[3], test;
+} RtcRegs_t, *RtcPtr_t;
+
+
+#define BVME_I596_BASE 0xff100000
+
+#define BVME_ETHIRQ_REG 0xff20000b
+
+#define BVME_LOCAL_IRQ_STAT 0xff20000f
+
+#define BVME_ETHERR 0x02
+#define BVME_ABORT_STATUS 0x08
+
+#define BVME_NCR53C710_BASE 0xff000000
+
+#define BVME_SCC_A_ADDR 0xffb0000b
+#define BVME_SCC_B_ADDR 0xffb00003
+#define BVME_SCC_RTxC 7372800
+
+#define BVME_CONFIG_REG 0xff500003
+
+#define config_reg_ptr (volatile unsigned char *)BVME_CONFIG_REG
+
+#define BVME_CONFIG_SW1 0x08
+#define BVME_CONFIG_SW2 0x04
+#define BVME_CONFIG_SW3 0x02
+#define BVME_CONFIG_SW4 0x01
+
+
+#define BVME_IRQ_TYPE_PRIO 0
+
+#define BVME_IRQ_PRN (IRQ_USER+20)
+#define BVME_IRQ_TIMER (IRQ_USER+25)
+#define BVME_IRQ_I596 IRQ_AUTO_2
+#define BVME_IRQ_SCSI IRQ_AUTO_3
+#define BVME_IRQ_RTC IRQ_AUTO_6
+#define BVME_IRQ_ABORT IRQ_AUTO_7
+
+/* SCC interrupts */
+#define BVME_IRQ_SCC_BASE IRQ_USER
+#define BVME_IRQ_SCCB_TX IRQ_USER
+#define BVME_IRQ_SCCB_STAT (IRQ_USER+2)
+#define BVME_IRQ_SCCB_RX (IRQ_USER+4)
+#define BVME_IRQ_SCCB_SPCOND (IRQ_USER+6)
+#define BVME_IRQ_SCCA_TX (IRQ_USER+8)
+#define BVME_IRQ_SCCA_STAT (IRQ_USER+10)
+#define BVME_IRQ_SCCA_RX (IRQ_USER+12)
+#define BVME_IRQ_SCCA_SPCOND (IRQ_USER+14)
+
+/* Address control registers */
+
+#define BVME_ACR_A32VBA 0xff400003
+#define BVME_ACR_A32MSK 0xff410003
+#define BVME_ACR_A24VBA 0xff420003
+#define BVME_ACR_A24MSK 0xff430003
+#define BVME_ACR_A16VBA 0xff440003
+#define BVME_ACR_A32LBA 0xff450003
+#define BVME_ACR_A24LBA 0xff460003
+#define BVME_ACR_ADDRCTL 0xff470003
+
+#define bvme_acr_a32vba *(volatile unsigned char *)BVME_ACR_A32VBA
+#define bvme_acr_a32msk *(volatile unsigned char *)BVME_ACR_A32MSK
+#define bvme_acr_a24vba *(volatile unsigned char *)BVME_ACR_A24VBA
+#define bvme_acr_a24msk *(volatile unsigned char *)BVME_ACR_A24MSK
+#define bvme_acr_a16vba *(volatile unsigned char *)BVME_ACR_A16VBA
+#define bvme_acr_a32lba *(volatile unsigned char *)BVME_ACR_A32LBA
+#define bvme_acr_a24lba *(volatile unsigned char *)BVME_ACR_A24LBA
+#define bvme_acr_addrctl *(volatile unsigned char *)BVME_ACR_ADDRCTL
+
+#endif
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
new file mode 100644
index 0000000..9c06458
--- /dev/null
+++ b/arch/m68k/include/asm/cache.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/asm-m68k/cache.h
+ */
+#ifndef __ARCH_M68K_CACHE_H
+#define __ARCH_M68K_CACHE_H
+
+/* bytes per L1 cache line */
+#define L1_CACHE_SHIFT 4
+#define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT)
+
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+
+#endif
diff --git a/arch/m68k/include/asm/cacheflush.h b/arch/m68k/include/asm/cacheflush.h
new file mode 100644
index 0000000..29b8e63
--- /dev/null
+++ b/arch/m68k/include/asm/cacheflush.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifdef __uClinux__
+#include <asm/cacheflush_no.h>
+#else
+#include <asm/cacheflush_mm.h>
+#endif
diff --git a/arch/m68k/include/asm/cacheflush_mm.h b/arch/m68k/include/asm/cacheflush_mm.h
new file mode 100644
index 0000000..1e2544e
--- /dev/null
+++ b/arch/m68k/include/asm/cacheflush_mm.h
@@ -0,0 +1,277 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_CACHEFLUSH_H
+#define _M68K_CACHEFLUSH_H
+
+#include <linux/mm.h>
+#ifdef CONFIG_COLDFIRE
+#include <asm/mcfsim.h>
+#endif
+
+/* cache code */
+#define FLUSH_I_AND_D (0x00000808)
+#define FLUSH_I (0x00000008)
+
+#ifndef ICACHE_MAX_ADDR
+#define ICACHE_MAX_ADDR 0
+#define ICACHE_SET_MASK 0
+#define DCACHE_MAX_ADDR 0
+#define DCACHE_SETMASK 0
+#endif
+#ifndef CACHE_MODE
+#define CACHE_MODE 0
+#define CACR_ICINVA 0
+#define CACR_DCINVA 0
+#define CACR_BCINVA 0
+#endif
+
+/*
+ * ColdFire architecture has no way to clear individual cache lines, so we
+ * are stuck invalidating all the cache entries when we want a clear operation.
+ */
+static inline void clear_cf_icache(unsigned long start, unsigned long end)
+{
+ __asm__ __volatile__ (
+ "movec %0,%%cacr\n\t"
+ "nop"
+ :
+ : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA));
+}
+
+static inline void clear_cf_dcache(unsigned long start, unsigned long end)
+{
+ __asm__ __volatile__ (
+ "movec %0,%%cacr\n\t"
+ "nop"
+ :
+ : "r" (CACHE_MODE | CACR_DCINVA));
+}
+
+static inline void clear_cf_bcache(unsigned long start, unsigned long end)
+{
+ __asm__ __volatile__ (
+ "movec %0,%%cacr\n\t"
+ "nop"
+ :
+ : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA | CACR_DCINVA));
+}
+
+/*
+ * Use the ColdFire cpushl instruction to push (and invalidate) cache lines.
+ * The start and end addresses are cache line numbers not memory addresses.
+ */
+static inline void flush_cf_icache(unsigned long start, unsigned long end)
+{
+ unsigned long set;
+
+ for (set = start; set <= end; set += (0x10 - 3)) {
+ __asm__ __volatile__ (
+ "cpushl %%ic,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%ic,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%ic,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%ic,(%0)"
+ : "=a" (set)
+ : "a" (set));
+ }
+}
+
+static inline void flush_cf_dcache(unsigned long start, unsigned long end)
+{
+ unsigned long set;
+
+ for (set = start; set <= end; set += (0x10 - 3)) {
+ __asm__ __volatile__ (
+ "cpushl %%dc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%dc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%dc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%dc,(%0)"
+ : "=a" (set)
+ : "a" (set));
+ }
+}
+
+static inline void flush_cf_bcache(unsigned long start, unsigned long end)
+{
+ unsigned long set;
+
+ for (set = start; set <= end; set += (0x10 - 3)) {
+ __asm__ __volatile__ (
+ "cpushl %%bc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%bc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%bc,(%0)\n\t"
+ "addq%.l #1,%0\n\t"
+ "cpushl %%bc,(%0)"
+ : "=a" (set)
+ : "a" (set));
+ }
+}
+
+/*
+ * Cache handling functions
+ */
+
+static inline void flush_icache(void)
+{
+ if (CPU_IS_COLDFIRE) {
+ flush_cf_icache(0, ICACHE_MAX_ADDR);
+ } else if (CPU_IS_040_OR_060) {
+ asm volatile ( "nop\n"
+ " .chip 68040\n"
+ " cpusha %bc\n"
+ " .chip 68k");
+ } else {
+ unsigned long tmp;
+ asm volatile ( "movec %%cacr,%0\n"
+ " or.w %1,%0\n"
+ " movec %0,%%cacr"
+ : "=&d" (tmp)
+ : "id" (FLUSH_I));
+ }
+}
+
+/*
+ * invalidate the cache for the specified memory range.
+ * It starts at the physical address specified for
+ * the given number of bytes.
+ */
+extern void cache_clear(unsigned long paddr, int len);
+/*
+ * push any dirty cache in the specified memory range.
+ * It starts at the physical address specified for
+ * the given number of bytes.
+ */
+extern void cache_push(unsigned long paddr, int len);
+
+/*
+ * push and invalidate pages in the specified user virtual
+ * memory range.
+ */
+extern void cache_push_v(unsigned long vaddr, int len);
+
+/* This is needed whenever the virtual mapping of the current
+ process changes. */
+#define __flush_cache_all() \
+({ \
+ if (CPU_IS_COLDFIRE) { \
+ flush_cf_dcache(0, DCACHE_MAX_ADDR); \
+ } else if (CPU_IS_040_OR_060) { \
+ __asm__ __volatile__("nop\n\t" \
+ ".chip 68040\n\t" \
+ "cpusha %dc\n\t" \
+ ".chip 68k"); \
+ } else { \
+ unsigned long _tmp; \
+ __asm__ __volatile__("movec %%cacr,%0\n\t" \
+ "orw %1,%0\n\t" \
+ "movec %0,%%cacr" \
+ : "=&d" (_tmp) \
+ : "di" (FLUSH_I_AND_D)); \
+ } \
+})
+
+#define __flush_cache_030() \
+({ \
+ if (CPU_IS_020_OR_030) { \
+ unsigned long _tmp; \
+ __asm__ __volatile__("movec %%cacr,%0\n\t" \
+ "orw %1,%0\n\t" \
+ "movec %0,%%cacr" \
+ : "=&d" (_tmp) \
+ : "di" (FLUSH_I_AND_D)); \
+ } \
+})
+
+#define flush_cache_all() __flush_cache_all()
+
+#define flush_cache_vmap(start, end) flush_cache_all()
+#define flush_cache_vunmap(start, end) flush_cache_all()
+
+static inline void flush_cache_mm(struct mm_struct *mm)
+{
+ if (mm == current->mm)
+ __flush_cache_030();
+}
+
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+
+/* flush_cache_range/flush_cache_page must be macros to avoid
+ a dependency on linux/mm.h, which includes this file... */
+static inline void flush_cache_range(struct vm_area_struct *vma,
+ unsigned long start,
+ unsigned long end)
+{
+ if (vma->vm_mm == current->mm)
+ __flush_cache_030();
+}
+
+static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
+{
+ if (vma->vm_mm == current->mm)
+ __flush_cache_030();
+}
+
+
+/* Push the page at kernel virtual address and clear the icache */
+/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
+static inline void __flush_page_to_ram(void *vaddr)
+{
+ if (CPU_IS_COLDFIRE) {
+ unsigned long addr, start, end;
+ addr = ((unsigned long) vaddr) & ~(PAGE_SIZE - 1);
+ start = addr & ICACHE_SET_MASK;
+ end = (addr + PAGE_SIZE - 1) & ICACHE_SET_MASK;
+ if (start > end) {
+ flush_cf_bcache(0, end);
+ end = ICACHE_MAX_ADDR;
+ }
+ flush_cf_bcache(start, end);
+ } else if (CPU_IS_040_OR_060) {
+ __asm__ __volatile__("nop\n\t"
+ ".chip 68040\n\t"
+ "cpushp %%bc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (__pa(vaddr)));
+ } else {
+ unsigned long _tmp;
+ __asm__ __volatile__("movec %%cacr,%0\n\t"
+ "orw %1,%0\n\t"
+ "movec %0,%%cacr"
+ : "=&d" (_tmp)
+ : "di" (FLUSH_I));
+ }
+}
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
+
+extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
+ unsigned long addr, int len);
+extern void flush_icache_range(unsigned long address, unsigned long endaddr);
+
+static inline void copy_to_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr,
+ void *dst, void *src, int len)
+{
+ flush_cache_page(vma, vaddr, page_to_pfn(page));
+ memcpy(dst, src, len);
+ flush_icache_user_range(vma, page, vaddr, len);
+}
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr,
+ void *dst, void *src, int len)
+{
+ flush_cache_page(vma, vaddr, page_to_pfn(page));
+ memcpy(dst, src, len);
+}
+
+#endif /* _M68K_CACHEFLUSH_H */
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
new file mode 100644
index 0000000..11e9a9d
--- /dev/null
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68KNOMMU_CACHEFLUSH_H
+#define _M68KNOMMU_CACHEFLUSH_H
+
+/*
+ * (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com>
+ */
+#include <linux/mm.h>
+#include <asm/mcfsim.h>
+
+#define flush_cache_all() __flush_cache_all()
+#define flush_cache_mm(mm) do { } while (0)
+#define flush_cache_dup_mm(mm) do { } while (0)
+#define flush_cache_range(vma, start, end) do { } while (0)
+#define flush_cache_page(vma, vmaddr) do { } while (0)
+#define flush_dcache_range(start, len) __flush_dcache_all()
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
+#define flush_dcache_page(page) do { } while (0)
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+#define flush_icache_range(start, len) __flush_icache_all()
+#define flush_icache_page(vma,pg) do { } while (0)
+#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
+#define flush_cache_vmap(start, end) do { } while (0)
+#define flush_cache_vunmap(start, end) do { } while (0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+ memcpy(dst, src, len)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+ memcpy(dst, src, len)
+
+void mcf_cache_push(void);
+
+static inline void __clear_cache_all(void)
+{
+#ifdef CACHE_INVALIDATE
+ __asm__ __volatile__ (
+ "movec %0, %%CACR\n\t"
+ "nop\n\t"
+ : : "r" (CACHE_INVALIDATE) );
+#endif
+}
+
+static inline void __flush_cache_all(void)
+{
+#ifdef CACHE_PUSH
+ mcf_cache_push();
+#endif
+ __clear_cache_all();
+}
+
+/*
+ * Some ColdFire parts implement separate instruction and data caches,
+ * on those we should just flush the appropriate cache. If we don't need
+ * to do any specific flushing then this will be optimized away.
+ */
+static inline void __flush_icache_all(void)
+{
+#ifdef CACHE_INVALIDATEI
+ __asm__ __volatile__ (
+ "movec %0, %%CACR\n\t"
+ "nop\n\t"
+ : : "r" (CACHE_INVALIDATEI) );
+#endif
+}
+
+static inline void __flush_dcache_all(void)
+{
+#ifdef CACHE_PUSH
+ mcf_cache_push();
+#endif
+#ifdef CACHE_INVALIDATED
+ __asm__ __volatile__ (
+ "movec %0, %%CACR\n\t"
+ "nop\n\t"
+ : : "r" (CACHE_INVALIDATED) );
+#else
+ /* Flush the write buffer */
+ __asm__ __volatile__ ( "nop" );
+#endif
+}
+
+/*
+ * Push cache entries at supplied address. We want to write back any dirty
+ * data and then invalidate the cache lines associated with this address.
+ */
+static inline void cache_push(unsigned long paddr, int len)
+{
+ __flush_cache_all();
+}
+
+/*
+ * Clear cache entries at supplied address (that is don't write back any
+ * dirty data).
+ */
+static inline void cache_clear(unsigned long paddr, int len)
+{
+ __clear_cache_all();
+}
+
+#endif /* _M68KNOMMU_CACHEFLUSH_H */
diff --git a/arch/m68k/include/asm/checksum.h b/arch/m68k/include/asm/checksum.h
new file mode 100644
index 0000000..f9b94e4
--- /dev/null
+++ b/arch/m68k/include/asm/checksum.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_CHECKSUM_H
+#define _M68K_CHECKSUM_H
+
+#include <linux/in6.h>
+
+#ifdef CONFIG_GENERIC_CSUM
+#include <asm-generic/checksum.h>
+#else
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+__wsum csum_partial(const void *buff, int len, __wsum sum);
+
+/*
+ * the same as csum_partial, but copies from src while it
+ * checksums
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+
+extern __wsum csum_partial_copy_from_user(const void __user *src,
+ void *dst,
+ int len, __wsum sum,
+ int *csum_err);
+
+extern __wsum csum_partial_copy_nocheck(const void *src,
+ void *dst, int len,
+ __wsum sum);
+
+/*
+ * This is a version of ip_fast_csum() optimized for IP headers,
+ * which always checksum on 4 octet boundaries.
+ */
+static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+ unsigned int sum = 0;
+ unsigned long tmp;
+
+ __asm__ ("subqw #1,%2\n"
+ "1:\t"
+ "movel %1@+,%3\n\t"
+ "addxl %3,%0\n\t"
+ "dbra %2,1b\n\t"
+ "movel %0,%3\n\t"
+ "swap %3\n\t"
+ "addxw %3,%0\n\t"
+ "clrw %3\n\t"
+ "addxw %3,%0\n\t"
+ : "=d" (sum), "=&a" (iph), "=&d" (ihl), "=&d" (tmp)
+ : "0" (sum), "1" (iph), "2" (ihl)
+ : "memory");
+ return (__force __sum16)~sum;
+}
+
+static inline __sum16 csum_fold(__wsum sum)
+{
+ unsigned int tmp = (__force u32)sum;
+
+ __asm__("swap %1\n\t"
+ "addw %1, %0\n\t"
+ "clrw %1\n\t"
+ "addxw %1, %0"
+ : "=&d" (sum), "=&d" (tmp)
+ : "0" (sum), "1" (tmp));
+
+ return (__force __sum16)~sum;
+}
+
+static inline __wsum
+csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
+ unsigned short proto, __wsum sum)
+{
+ __asm__ ("addl %2,%0\n\t"
+ "addxl %3,%0\n\t"
+ "addxl %4,%0\n\t"
+ "clrl %1\n\t"
+ "addxl %1,%0"
+ : "=&d" (sum), "=d" (saddr)
+ : "g" (daddr), "1" (saddr), "d" (len + proto),
+ "0" (sum));
+ return sum;
+}
+
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16
+csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
+ unsigned short proto, __wsum sum)
+{
+ return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+
+static inline __sum16 ip_compute_csum(const void *buff, int len)
+{
+ return csum_fold (csum_partial(buff, len, 0));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+static __inline__ __sum16
+csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
+ __u32 len, __u8 proto, __wsum sum)
+{
+ register unsigned long tmp;
+ __asm__("addl %2@,%0\n\t"
+ "movel %2@(4),%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %2@(8),%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %2@(12),%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %3@,%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %3@(4),%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %3@(8),%1\n\t"
+ "addxl %1,%0\n\t"
+ "movel %3@(12),%1\n\t"
+ "addxl %1,%0\n\t"
+ "addxl %4,%0\n\t"
+ "clrl %1\n\t"
+ "addxl %1,%0"
+ : "=&d" (sum), "=&d" (tmp)
+ : "a" (saddr), "a" (daddr), "d" (len + proto),
+ "0" (sum));
+
+ return csum_fold(sum);
+}
+
+#endif /* CONFIG_GENERIC_CSUM */
+#endif /* _M68K_CHECKSUM_H */
diff --git a/arch/m68k/include/asm/cmpxchg.h b/arch/m68k/include/asm/cmpxchg.h
new file mode 100644
index 0000000..38e1d7a
--- /dev/null
+++ b/arch/m68k/include/asm/cmpxchg.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ARCH_M68K_CMPXCHG__
+#define __ARCH_M68K_CMPXCHG__
+
+#include <linux/irqflags.h>
+
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((volatile struct __xchg_dummy *)(x))
+
+extern unsigned long __invalid_xchg_size(unsigned long, volatile void *, int);
+
+#ifndef CONFIG_RMW_INSNS
+static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+{
+ unsigned long flags, tmp;
+
+ local_irq_save(flags);
+
+ switch (size) {
+ case 1:
+ tmp = *(u8 *)ptr;
+ *(u8 *)ptr = x;
+ x = tmp;
+ break;
+ case 2:
+ tmp = *(u16 *)ptr;
+ *(u16 *)ptr = x;
+ x = tmp;
+ break;
+ case 4:
+ tmp = *(u32 *)ptr;
+ *(u32 *)ptr = x;
+ x = tmp;
+ break;
+ default:
+ tmp = __invalid_xchg_size(x, ptr, size);
+ break;
+ }
+
+ local_irq_restore(flags);
+ return x;
+}
+#else
+static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+{
+ switch (size) {
+ case 1:
+ __asm__ __volatile__
+ ("moveb %2,%0\n\t"
+ "1:\n\t"
+ "casb %0,%1,%2\n\t"
+ "jne 1b"
+ : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
+ break;
+ case 2:
+ __asm__ __volatile__
+ ("movew %2,%0\n\t"
+ "1:\n\t"
+ "casw %0,%1,%2\n\t"
+ "jne 1b"
+ : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
+ break;
+ case 4:
+ __asm__ __volatile__
+ ("movel %2,%0\n\t"
+ "1:\n\t"
+ "casl %0,%1,%2\n\t"
+ "jne 1b"
+ : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
+ break;
+ default:
+ x = __invalid_xchg_size(x, ptr, size);
+ break;
+ }
+ return x;
+}
+#endif
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+#include <asm-generic/cmpxchg-local.h>
+
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+extern unsigned long __invalid_cmpxchg_size(volatile void *,
+ unsigned long, unsigned long, int);
+
+/*
+ * Atomic compare and exchange. Compare OLD with MEM, if identical,
+ * store NEW in MEM. Return the initial value in MEM. Success is
+ * indicated by comparing RETURN with OLD.
+ */
+#ifdef CONFIG_RMW_INSNS
+
+static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
+ unsigned long new, int size)
+{
+ switch (size) {
+ case 1:
+ __asm__ __volatile__ ("casb %0,%2,%1"
+ : "=d" (old), "=m" (*(char *)p)
+ : "d" (new), "0" (old), "m" (*(char *)p));
+ break;
+ case 2:
+ __asm__ __volatile__ ("casw %0,%2,%1"
+ : "=d" (old), "=m" (*(short *)p)
+ : "d" (new), "0" (old), "m" (*(short *)p));
+ break;
+ case 4:
+ __asm__ __volatile__ ("casl %0,%2,%1"
+ : "=d" (old), "=m" (*(int *)p)
+ : "d" (new), "0" (old), "m" (*(int *)p));
+ break;
+ default:
+ old = __invalid_cmpxchg_size(p, old, new, size);
+ break;
+ }
+ return old;
+}
+
+#define cmpxchg(ptr, o, n) \
+ ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
+ (unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg_local(ptr, o, n) \
+ ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
+ (unsigned long)(n), sizeof(*(ptr))))
+
+#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
+
+#else
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+#define cmpxchg_local(ptr, o, n) \
+ ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
+ (unsigned long)(n), sizeof(*(ptr))))
+
+#include <asm-generic/cmpxchg.h>
+
+#endif
+
+#endif /* __ARCH_M68K_CMPXCHG__ */
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
new file mode 100644
index 0000000..d9cb26f
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * coldfire.h -- Motorola ColdFire CPU sepecific defines
+ *
+ * (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo (www.lineo.com)
+ */
+
+/****************************************************************************/
+#ifndef coldfire_h
+#define coldfire_h
+/****************************************************************************/
+
+
+/*
+ * Define master clock frequency. This is done at config time now.
+ * No point enumerating dozens of possible clock options here. And
+ * in any case new boards come along from time to time that have yet
+ * another different clocking frequency.
+ */
+#ifdef CONFIG_CLOCK_FREQ
+#define MCF_CLK CONFIG_CLOCK_FREQ
+#else
+#error "Don't know what your ColdFire CPU clock frequency is??"
+#endif
+
+/*
+ * Define the processor internal peripherals base address.
+ *
+ * The majority of ColdFire parts use an MBAR register to set
+ * the base address. Some have an IPSBAR register instead, and it
+ * has slightly different rules on its size and alignment. Some
+ * parts have fixed addresses and the internal peripherals cannot
+ * be relocated in the CPU address space.
+ *
+ * The value of MBAR or IPSBAR is config time selectable, we no
+ * longer hard define it here. No MBAR or IPSBAR will be defined if
+ * this part has a fixed peripheral address map.
+ */
+#ifdef CONFIG_MBAR
+#define MCF_MBAR CONFIG_MBAR
+#endif
+#ifdef CONFIG_IPSBAR
+#define MCF_IPSBAR CONFIG_IPSBAR
+#endif
+
+/****************************************************************************/
+#endif /* coldfire_h */
diff --git a/arch/m68k/include/asm/contregs.h b/arch/m68k/include/asm/contregs.h
new file mode 100644
index 0000000..f82ca0a
--- /dev/null
+++ b/arch/m68k/include/asm/contregs.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_CONTREGS_H
+#define _M68K_CONTREGS_H
+
+/* contregs.h: Addresses of registers in the ASI_CONTROL alternate address
+ * space. These are for the mmu's context register, etc.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+/* 3=sun3
+ 4=sun4 (as in sun4 sysmaint student book)
+ c=sun4c (according to davem) */
+
+#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
+#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
+#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
+#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
+#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
+#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
+#define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
+#define AC_SYNC_ERR 0x60000000 /* c fault type */
+#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
+#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
+#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
+#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
+#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
+#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
+#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
+#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
+#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
+
+/* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress */
+#define AC_M_PCR 0x0000 /* shv Processor Control Reg */
+#define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
+#define AC_M_CXR 0x0200 /* shv Context Register */
+#define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
+#define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
+#define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
+#define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
+#define AC_M_RESET 0x0700 /* hv Reset Reg */
+#define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
+#define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
+#define AC_M_IAPTP 0x1100 /* hv Instruction Access PTP */
+#define AC_M_DAPTP 0x1200 /* hv Data Access PTP */
+#define AC_M_ITR 0x1300 /* hv Index Tag Register */
+#define AC_M_TRCR 0x1400 /* hv TLB Replacement Control Reg */
+#define AC_M_SFSRX 0x1300 /* s Synch Fault Status Reg prim */
+#define AC_M_SFARX 0x1400 /* s Synch Fault Address Reg prim */
+#define AC_M_RPR1 0x1500 /* h Root Pointer Reg (entry 2) */
+#define AC_M_IAPTP1 0x1600 /* h Instruction Access PTP (entry 2) */
+#define AC_M_DAPTP1 0x1700 /* h Data Access PTP (entry 2) */
+
+#endif /* _M68K_CONTREGS_H */
diff --git a/arch/m68k/include/asm/current.h b/arch/m68k/include/asm/current.h
new file mode 100644
index 0000000..6390ef2
--- /dev/null
+++ b/arch/m68k/include/asm/current.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_CURRENT_H
+#define _M68K_CURRENT_H
+
+#ifdef CONFIG_MMU
+
+register struct task_struct *current __asm__("%a2");
+
+#else
+
+/*
+ * Rather than dedicate a register (as the m68k source does), we
+ * just keep a global, we should probably just change it all to be
+ * current and lose _current_task.
+ */
+#include <linux/thread_info.h>
+
+struct task_struct;
+
+static inline struct task_struct *get_current(void)
+{
+ return(current_thread_info()->task);
+}
+
+#define current get_current()
+
+#endif /* CONFNIG_MMU */
+
+#endif /* !(_M68K_CURRENT_H) */
diff --git a/arch/m68k/include/asm/delay.h b/arch/m68k/include/asm/delay.h
new file mode 100644
index 0000000..751712f
--- /dev/null
+++ b/arch/m68k/include/asm/delay.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_DELAY_H
+#define _M68K_DELAY_H
+
+#include <asm/param.h>
+
+/*
+ * Copyright (C) 1994 Hamish Macdonald
+ * Copyright (C) 2004 Greg Ungerer <gerg@uclinux.com>
+ *
+ * Delay routines, using a pre-computed "loops_per_jiffy" value.
+ */
+
+#if defined(CONFIG_COLDFIRE)
+/*
+ * The ColdFire runs the delay loop at significantly different speeds
+ * depending upon long word alignment or not. We'll pad it to
+ * long word alignment which is the faster version.
+ * The 0x4a8e is of course a 'tstl %fp' instruction. This is better
+ * than using a NOP (0x4e71) instruction because it executes in one
+ * cycle not three and doesn't allow for an arbitrary delay waiting
+ * for bus cycles to finish. Also fp/a6 isn't likely to cause a
+ * stall waiting for the register to become valid if such is added
+ * to the coldfire at some stage.
+ */
+#define DELAY_ALIGN ".balignw 4, 0x4a8e\n\t"
+#else
+/*
+ * No instruction alignment required for other m68k types.
+ */
+#define DELAY_ALIGN
+#endif
+
+static inline void __delay(unsigned long loops)
+{
+ __asm__ __volatile__ (
+ DELAY_ALIGN
+ "1: subql #1,%0\n\t"
+ "jcc 1b"
+ : "=d" (loops)
+ : "0" (loops));
+}
+
+extern void __bad_udelay(void);
+
+
+#ifdef CONFIG_CPU_HAS_NO_MULDIV64
+/*
+ * The simpler m68k and ColdFire processors do not have a 32*32->64
+ * multiply instruction. So we need to handle them a little differently.
+ * We use a bit of shifting and a single 32*32->32 multiply to get close.
+ */
+#define HZSCALE (268435456 / (1000000 / HZ))
+
+#define __const_udelay(u) \
+ __delay(((((u) * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6)
+
+#else
+
+static inline void __xdelay(unsigned long xloops)
+{
+ unsigned long tmp;
+
+ __asm__ ("mulul %2,%0:%1"
+ : "=d" (xloops), "=d" (tmp)
+ : "d" (xloops), "1" (loops_per_jiffy));
+ __delay(xloops * HZ);
+}
+
+/*
+ * The definition of __const_udelay is specifically made a macro so that
+ * the const factor (4295 = 2**32 / 1000000) can be optimized out when
+ * the delay is a const.
+ */
+#define __const_udelay(n) (__xdelay((n) * 4295))
+
+#endif
+
+static inline void __udelay(unsigned long usecs)
+{
+ __const_udelay(usecs);
+}
+
+/*
+ * Use only for very small delays ( < 1 msec). Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays. This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+#define udelay(n) (__builtin_constant_p(n) ? \
+ ((n) > 20000 ? __bad_udelay() : __const_udelay(n)) : __udelay(n))
+
+/*
+ * nanosecond delay:
+ *
+ * ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6) is the number of loops
+ * per microsecond
+ *
+ * 1000 / ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6) is the number of
+ * nanoseconds per loop
+ *
+ * So n / ( 1000 / ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6) ) would
+ * be the number of loops for n nanoseconds
+ */
+
+/*
+ * The simpler m68k and ColdFire processors do not have a 32*32->64
+ * multiply instruction. So we need to handle them a little differently.
+ * We use a bit of shifting and a single 32*32->32 multiply to get close.
+ * This is a macro so that the const version can factor out the first
+ * multiply and shift.
+ */
+#define HZSCALE (268435456 / (1000000 / HZ))
+
+static inline void ndelay(unsigned long nsec)
+{
+ __delay(DIV_ROUND_UP(nsec *
+ ((((HZSCALE) >> 11) *
+ (loops_per_jiffy >> 11)) >> 6),
+ 1000));
+}
+#define ndelay(n) ndelay(n)
+
+#endif /* defined(_M68K_DELAY_H) */
diff --git a/arch/m68k/include/asm/div64.h b/arch/m68k/include/asm/div64.h
new file mode 100644
index 0000000..365f39f
--- /dev/null
+++ b/arch/m68k/include/asm/div64.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_DIV64_H
+#define _M68K_DIV64_H
+
+#ifdef CONFIG_CPU_HAS_NO_MULDIV64
+#include <asm-generic/div64.h>
+#else
+
+#include <linux/types.h>
+
+/* n = n / base; return rem; */
+
+#define do_div(n, base) ({ \
+ union { \
+ unsigned long n32[2]; \
+ unsigned long long n64; \
+ } __n; \
+ unsigned long __rem, __upper; \
+ unsigned long __base = (base); \
+ \
+ __n.n64 = (n); \
+ if ((__upper = __n.n32[0])) { \
+ asm ("divul.l %2,%1:%0" \
+ : "=d" (__n.n32[0]), "=d" (__upper) \
+ : "d" (__base), "0" (__n.n32[0])); \
+ } \
+ asm ("divu.l %2,%1:%0" \
+ : "=d" (__n.n32[1]), "=d" (__rem) \
+ : "d" (__base), "1" (__upper), "0" (__n.n32[1])); \
+ (n) = __n.n64; \
+ __rem; \
+})
+
+#endif /* CONFIG_CPU_HAS_NO_MULDIV64 */
+
+#endif /* _M68K_DIV64_H */
diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h
new file mode 100644
index 0000000..ae20219
--- /dev/null
+++ b/arch/m68k/include/asm/dma.h
@@ -0,0 +1,498 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_DMA_H
+#define _M68K_DMA_H 1
+
+#ifdef CONFIG_COLDFIRE
+/*
+ * ColdFire DMA Model:
+ * ColdFire DMA supports two forms of DMA: Single and Dual address. Single
+ * address mode emits a source address, and expects that the device will either
+ * pick up the data (DMA READ) or source data (DMA WRITE). This implies that
+ * the device will place data on the correct byte(s) of the data bus, as the
+ * memory transactions are always 32 bits. This implies that only 32 bit
+ * devices will find single mode transfers useful. Dual address DMA mode
+ * performs two cycles: source read and destination write. ColdFire will
+ * align the data so that the device will always get the correct bytes, thus
+ * is useful for 8 and 16 bit devices. This is the mode that is supported
+ * below.
+ *
+ * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
+ * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
+ *
+ * AUG/25/2000 : added support for 8, 16 and 32-bit Single-Address-Mode (K)2000
+ * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
+ *
+ * APR/18/2002 : added proper support for MCF5272 DMA controller.
+ * Arthur Shipkowski (art@videon-central.com)
+ */
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfdma.h>
+
+/*
+ * Set number of channels of DMA on ColdFire for different implementations.
+ */
+#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
+ defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
+ defined(CONFIG_M528x) || defined(CONFIG_M525x)
+
+#define MAX_M68K_DMA_CHANNELS 4
+#elif defined(CONFIG_M5272)
+#define MAX_M68K_DMA_CHANNELS 1
+#elif defined(CONFIG_M53xx)
+#define MAX_M68K_DMA_CHANNELS 0
+#else
+#define MAX_M68K_DMA_CHANNELS 2
+#endif
+
+extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
+extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
+
+#if !defined(CONFIG_M5272)
+#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
+#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
+#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
+#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
+
+/* I/O to memory, 8 bits, mode */
+#define DMA_MODE_READ 0
+/* memory to I/O, 8 bits, mode */
+#define DMA_MODE_WRITE 1
+/* I/O to memory, 16 bits, mode */
+#define DMA_MODE_READ_WORD 2
+/* memory to I/O, 16 bits, mode */
+#define DMA_MODE_WRITE_WORD 3
+/* I/O to memory, 32 bits, mode */
+#define DMA_MODE_READ_LONG 4
+/* memory to I/O, 32 bits, mode */
+#define DMA_MODE_WRITE_LONG 5
+/* I/O to memory, 8 bits, single-address-mode */
+#define DMA_MODE_READ_SINGLE 8
+/* memory to I/O, 8 bits, single-address-mode */
+#define DMA_MODE_WRITE_SINGLE 9
+/* I/O to memory, 16 bits, single-address-mode */
+#define DMA_MODE_READ_WORD_SINGLE 10
+/* memory to I/O, 16 bits, single-address-mode */
+#define DMA_MODE_WRITE_WORD_SINGLE 11
+/* I/O to memory, 32 bits, single-address-mode */
+#define DMA_MODE_READ_LONG_SINGLE 12
+/* memory to I/O, 32 bits, single-address-mode */
+#define DMA_MODE_WRITE_LONG_SINGLE 13
+
+#else /* CONFIG_M5272 is defined */
+
+/* Source static-address mode */
+#define DMA_MODE_SRC_SA_BIT 0x01
+/* Two bits to select between all four modes */
+#define DMA_MODE_SSIZE_MASK 0x06
+/* Offset to shift bits in */
+#define DMA_MODE_SSIZE_OFF 0x01
+/* Destination static-address mode */
+#define DMA_MODE_DES_SA_BIT 0x10
+/* Two bits to select between all four modes */
+#define DMA_MODE_DSIZE_MASK 0x60
+/* Offset to shift bits in */
+#define DMA_MODE_DSIZE_OFF 0x05
+/* Size modifiers */
+#define DMA_MODE_SIZE_LONG 0x00
+#define DMA_MODE_SIZE_BYTE 0x01
+#define DMA_MODE_SIZE_WORD 0x02
+#define DMA_MODE_SIZE_LINE 0x03
+
+/*
+ * Aliases to help speed quick ports; these may be suboptimal, however. They
+ * do not include the SINGLE mode modifiers since the MCF5272 does not have a
+ * mode where the device is in control of its addressing.
+ */
+
+/* I/O to memory, 8 bits, mode */
+#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
+/* memory to I/O, 8 bits, mode */
+#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
+/* I/O to memory, 16 bits, mode */
+#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
+/* memory to I/O, 16 bits, mode */
+#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
+/* I/O to memory, 32 bits, mode */
+#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
+/* memory to I/O, 32 bits, mode */
+#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
+
+#endif /* !defined(CONFIG_M5272) */
+
+#if !defined(CONFIG_M5272)
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+ volatile unsigned short *dmawp;
+
+#ifdef DMA_DEBUG
+ printk("enable_dma(dmanr=%d)\n", dmanr);
+#endif
+
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+ dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+ volatile unsigned short *dmawp;
+ volatile unsigned char *dmapb;
+
+#ifdef DMA_DEBUG
+ printk("disable_dma(dmanr=%d)\n", dmanr);
+#endif
+
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+ dmapb = (unsigned char *) dma_base_addr[dmanr];
+
+ /* Turn off external requests, and stop any DMA in progress */
+ dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
+ dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
+}
+
+/*
+ * Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while interrupts are disabled! ---
+ *
+ * This is a NOP for ColdFire. Provide a stub for compatibility.
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+
+ volatile unsigned char *dmabp;
+ volatile unsigned short *dmawp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
+#endif
+
+ dmabp = (unsigned char *) dma_base_addr[dmanr];
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+
+ /* Clear config errors */
+ dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
+
+ /* Set command register */
+ dmawp[MCFDMA_DCR] =
+ MCFDMA_DCR_INT | /* Enable completion irq */
+ MCFDMA_DCR_CS | /* Force one xfer per request */
+ MCFDMA_DCR_AA | /* Enable auto alignment */
+ /* single-address-mode */
+ ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
+ /* sets s_rw (-> r/w) high if Memory to I/0 */
+ ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
+ /* Memory to I/O or I/O to Memory */
+ ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
+ /* 32 bit, 16 bit or 8 bit transfers */
+ ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
+ ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
+ MCFDMA_DCR_SSIZE_BYTE)) |
+ ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
+ ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
+ MCFDMA_DCR_DSIZE_BYTE));
+
+#ifdef DEBUG_DMA
+ printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
+ dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
+ (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
+#endif
+}
+
+/* Set transfer address for specific DMA channel */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+ volatile unsigned short *dmawp;
+ volatile unsigned int *dmalp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
+#endif
+
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+
+ /* Determine which address registers are used for memory/device accesses */
+ if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
+ /* Source incrementing, must be memory */
+ dmalp[MCFDMA_SAR] = a;
+ /* Set dest address, must be device */
+ dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
+ } else {
+ /* Destination incrementing, must be memory */
+ dmalp[MCFDMA_DAR] = a;
+ /* Set source address, must be device */
+ dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
+ }
+
+#ifdef DEBUG_DMA
+ printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
+ __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
+ (int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
+ (int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
+#endif
+}
+
+/*
+ * Specific for Coldfire - sets device address.
+ * Should be called after the mode set call, and before set DMA address.
+ */
+static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
+{
+#ifdef DMA_DEBUG
+ printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
+#endif
+
+ dma_device_address[dmanr] = a;
+}
+
+/*
+ * NOTE 2: "count" represents _bytes_.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+ volatile unsigned short *dmawp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
+#endif
+
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+ dmawp[MCFDMA_BCR] = (unsigned short)count;
+}
+
+/*
+ * Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+ volatile unsigned short *dmawp;
+ unsigned short count;
+
+#ifdef DMA_DEBUG
+ printk("get_dma_residue(dmanr=%d)\n", dmanr);
+#endif
+
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+ count = dmawp[MCFDMA_BCR];
+ return((int) count);
+}
+#else /* CONFIG_M5272 is defined */
+
+/*
+ * The MCF5272 DMA controller is very different than the controller defined above
+ * in terms of register mapping. For instance, with the exception of the 16-bit
+ * interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
+ *
+ * The big difference, however, is the lack of device-requested DMA. All modes
+ * are dual address transfer, and there is no 'device' setup or direction bit.
+ * You can DMA between a device and memory, between memory and memory, or even between
+ * two devices directly, with any combination of incrementing and non-incrementing
+ * addresses you choose. This puts a crimp in distinguishing between the 'device
+ * address' set up by set_dma_device_addr.
+ *
+ * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
+ * which will act exactly as above in -- it will look to see if the source is set to
+ * autoincrement, and if so it will make the source use the set_dma_addr value and the
+ * destination the set_dma_device_addr value. Otherwise the source will be set to the
+ * set_dma_device_addr value and the destination will get the set_dma_addr value.
+ *
+ * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
+ * and make it explicit. Depending on what you're doing, one of these two should work
+ * for you, but don't mix them in the same transfer setup.
+ */
+
+/* enable/disable a specific DMA channel */
+static __inline__ void enable_dma(unsigned int dmanr)
+{
+ volatile unsigned int *dmalp;
+
+#ifdef DMA_DEBUG
+ printk("enable_dma(dmanr=%d)\n", dmanr);
+#endif
+
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+ dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
+}
+
+static __inline__ void disable_dma(unsigned int dmanr)
+{
+ volatile unsigned int *dmalp;
+
+#ifdef DMA_DEBUG
+ printk("disable_dma(dmanr=%d)\n", dmanr);
+#endif
+
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+
+ /* Turn off external requests, and stop any DMA in progress */
+ dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
+ dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
+}
+
+/*
+ * Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while interrupts are disabled! ---
+ *
+ * This is a NOP for ColdFire. Provide a stub for compatibility.
+ */
+static __inline__ void clear_dma_ff(unsigned int dmanr)
+{
+}
+
+/* set mode (above) for a specific DMA channel */
+static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
+{
+
+ volatile unsigned int *dmalp;
+ volatile unsigned short *dmawp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
+#endif
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+ dmawp = (unsigned short *) dma_base_addr[dmanr];
+
+ /* Clear config errors */
+ dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
+
+ /* Set command register */
+ dmalp[MCFDMA_DMR] =
+ MCFDMA_DMR_RQM_DUAL | /* Mandatory Request Mode setting */
+ MCFDMA_DMR_DSTT_SD | /* Set up addressing types; set to supervisor-data. */
+ MCFDMA_DMR_SRCT_SD | /* Set up addressing types; set to supervisor-data. */
+ /* source static-address-mode */
+ ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
+ /* dest static-address-mode */
+ ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
+ /* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */
+ (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
+ (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
+
+ dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
+
+#ifdef DEBUG_DMA
+ printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
+ dmanr, (int) &dmalp[MCFDMA_DMR], dmalp[MCFDMA_DMR],
+ (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
+#endif
+}
+
+/* Set transfer address for specific DMA channel */
+static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+ volatile unsigned int *dmalp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
+#endif
+
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+
+ /* Determine which address registers are used for memory/device accesses */
+ if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
+ /* Source incrementing, must be memory */
+ dmalp[MCFDMA_DSAR] = a;
+ /* Set dest address, must be device */
+ dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
+ } else {
+ /* Destination incrementing, must be memory */
+ dmalp[MCFDMA_DDAR] = a;
+ /* Set source address, must be device */
+ dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
+ }
+
+#ifdef DEBUG_DMA
+ printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
+ __FILE__, __LINE__, dmanr, (int) &dmalp[MCFDMA_DMR], dmalp[MCFDMA_DMR],
+ (int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
+ (int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
+#endif
+}
+
+/*
+ * Specific for Coldfire - sets device address.
+ * Should be called after the mode set call, and before set DMA address.
+ */
+static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
+{
+#ifdef DMA_DEBUG
+ printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
+#endif
+
+ dma_device_address[dmanr] = a;
+}
+
+/*
+ * NOTE 2: "count" represents _bytes_.
+ *
+ * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
+ */
+static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+ volatile unsigned int *dmalp;
+
+#ifdef DMA_DEBUG
+ printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
+#endif
+
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+ dmalp[MCFDMA_DBCR] = count;
+}
+
+/*
+ * Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ */
+static __inline__ int get_dma_residue(unsigned int dmanr)
+{
+ volatile unsigned int *dmalp;
+ unsigned int count;
+
+#ifdef DMA_DEBUG
+ printk("get_dma_residue(dmanr=%d)\n", dmanr);
+#endif
+
+ dmalp = (unsigned int *) dma_base_addr[dmanr];
+ count = dmalp[MCFDMA_DBCR];
+ return(count);
+}
+
+#endif /* !defined(CONFIG_M5272) */
+#endif /* CONFIG_COLDFIRE */
+
+/* it's useless on the m68k, but unfortunately needed by the new
+ bootmem allocator (but this should do it for this) */
+#define MAX_DMA_ADDRESS PAGE_OFFSET
+
+#define MAX_DMA_CHANNELS 8
+
+extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
+extern void free_dma(unsigned int dmanr); /* release it again */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy (0)
+#endif
+
+#endif /* _M68K_DMA_H */
diff --git a/arch/m68k/include/asm/dsp56k.h b/arch/m68k/include/asm/dsp56k.h
new file mode 100644
index 0000000..2d8c0c9
--- /dev/null
+++ b/arch/m68k/include/asm/dsp56k.h
@@ -0,0 +1,35 @@
+/*
+ * linux/include/asm-m68k/dsp56k.h - defines and declarations for
+ * DSP56k device driver
+ *
+ * Copyright (C) 1996,1997 Fredrik Noring, lars brinkhoff & Tomas Berndtsson
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+
+/* Used for uploading DSP binary code */
+struct dsp56k_upload {
+ int len;
+ char __user *bin;
+};
+
+/* For the DSP host flags */
+struct dsp56k_host_flags {
+ int dir; /* Bit field. 1 = write output bit, 0 = do nothing.
+ * 0x0000 means reading only, 0x0011 means
+ * writing the bits stored in `out' on HF0 and HF1.
+ * Note that HF2 and HF3 can only be read.
+ */
+ int out; /* Bit field like above. */
+ int status; /* Host register's current state is returned */
+};
+
+/* ioctl command codes */
+#define DSP56K_UPLOAD 1 /* Upload DSP binary program */
+#define DSP56K_SET_TX_WSIZE 2 /* Host transmit word size (1-4) */
+#define DSP56K_SET_RX_WSIZE 3 /* Host receive word size (1-4) */
+#define DSP56K_HOST_FLAGS 4 /* Host flag registers */
+#define DSP56K_HOST_CMD 5 /* Trig Host Command (0-31) */
diff --git a/arch/m68k/include/asm/dvma.h b/arch/m68k/include/asm/dvma.h
new file mode 100644
index 0000000..f609ec1
--- /dev/null
+++ b/arch/m68k/include/asm/dvma.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/asm-m68k/dma.h
+ *
+ * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
+ *
+ * Hacked to fit Sun3x needs by Thomas Bogendoerfer
+ */
+
+#ifndef __M68K_DVMA_H
+#define __M68K_DVMA_H
+
+
+#define DVMA_PAGE_SHIFT 13
+#define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT)
+#define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
+#define DVMA_PAGE_ALIGN(addr) ALIGN(addr, DVMA_PAGE_SIZE)
+
+extern void dvma_init(void);
+extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
+ int len);
+
+#define dvma_malloc(x) dvma_malloc_align(x, 0)
+#define dvma_map(x, y) dvma_map_align(x, y, 0)
+#define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
+#define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
+extern unsigned long dvma_map_align(unsigned long kaddr, int len,
+ int align);
+extern void *dvma_malloc_align(unsigned long len, unsigned long align);
+
+extern void dvma_unmap(void *baddr);
+extern void dvma_free(void *vaddr);
+
+
+#ifdef CONFIG_SUN3
+/* sun3 dvma page support */
+
+/* memory and pmegs potentially reserved for dvma */
+#define DVMA_PMEG_START 10
+#define DVMA_PMEG_END 16
+#define DVMA_START 0xf00000
+#define DVMA_END 0xfe0000
+#define DVMA_SIZE (DVMA_END-DVMA_START)
+#define IOMMU_TOTAL_ENTRIES 128
+#define IOMMU_ENTRIES 120
+
+/* empirical kludge -- dvma regions only seem to work right on 0x10000
+ byte boundaries */
+#define DVMA_REGION_SIZE 0x10000
+#define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
+ ~(DVMA_REGION_SIZE-1))
+
+/* virt <-> phys conversions */
+#define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
+#define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
+#define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
+#define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
+#define dvma_vtob(x) dvma_vtop(x)
+#define dvma_btov(x) dvma_ptov(x)
+
+static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr,
+ int len)
+{
+ return 0;
+}
+
+#else /* Sun3x */
+
+/* sun3x dvma page support */
+
+#define DVMA_START 0x0
+#define DVMA_END 0xf00000
+#define DVMA_SIZE (DVMA_END-DVMA_START)
+#define IOMMU_TOTAL_ENTRIES 2048
+/* the prom takes the top meg */
+#define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
+
+#define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
+#define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
+
+extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len);
+
+
+
+/* everything below this line is specific to dma used for the onboard
+ ESP scsi on sun3x */
+
+/* Structure to describe the current status of DMA registers on the Sparc */
+struct sparc_dma_registers {
+ __volatile__ unsigned long cond_reg; /* DMA condition register */
+ __volatile__ unsigned long st_addr; /* Start address of this transfer */
+ __volatile__ unsigned long cnt; /* How many bytes to transfer */
+ __volatile__ unsigned long dma_test; /* DMA test register */
+};
+
+/* DVMA chip revisions */
+enum dvma_rev {
+ dvmarev0,
+ dvmaesc1,
+ dvmarev1,
+ dvmarev2,
+ dvmarev3,
+ dvmarevplus,
+ dvmahme
+};
+
+#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
+
+/* Linux DMA information structure, filled during probe. */
+struct Linux_SBus_DMA {
+ struct Linux_SBus_DMA *next;
+ struct linux_sbus_device *SBus_dev;
+ struct sparc_dma_registers *regs;
+
+ /* Status, misc info */
+ int node; /* Prom node for this DMA device */
+ int running; /* Are we doing DMA now? */
+ int allocated; /* Are we "owned" by anyone yet? */
+
+ /* Transfer information. */
+ unsigned long addr; /* Start address of current transfer */
+ int nbytes; /* Size of current transfer */
+ int realbytes; /* For splitting up large transfers, etc. */
+
+ /* DMA revision */
+ enum dvma_rev revision;
+};
+
+extern struct Linux_SBus_DMA *dma_chain;
+
+/* Broken hardware... */
+#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
+#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
+
+/* Fields in the cond_reg register */
+/* First, the version identification bits */
+#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
+#define DMA_VERS0 0x00000000 /* Sunray DMA version */
+#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
+#define DMA_VERS1 0x80000000 /* DMA rev 1 */
+#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
+#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
+#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
+
+#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
+#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
+#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
+#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
+#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
+#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
+#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
+#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
+#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
+#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
+#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
+#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
+#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
+#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
+#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
+#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
+#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
+#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
+#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
+#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
+#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
+#define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */
+#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
+#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
+#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
+#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
+#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
+#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
+#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
+#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
+#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
+#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
+#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
+#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
+#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
+#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
+#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
+
+/* Values describing the burst-size property from the PROM */
+#define DMA_BURST1 0x01
+#define DMA_BURST2 0x02
+#define DMA_BURST4 0x04
+#define DMA_BURST8 0x08
+#define DMA_BURST16 0x10
+#define DMA_BURST32 0x20
+#define DMA_BURST64 0x40
+#define DMA_BURSTBITS 0x7f
+
+/* Determine highest possible final transfer address given a base */
+#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
+
+/* Yes, I hack a lot of elisp in my spare time... */
+#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
+#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
+#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
+#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
+#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
+#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
+#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
+#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
+#define DMA_BEGINDMA_W(regs) \
+ ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
+#define DMA_BEGINDMA_R(regs) \
+ ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
+
+/* For certain DMA chips, we need to disable ints upon irq entry
+ * and turn them back on when we are done. So in any ESP interrupt
+ * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
+ * when leaving the handler. You have been warned...
+ */
+#define DMA_IRQ_ENTRY(dma, dregs) do { \
+ if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
+ } while (0)
+
+#define DMA_IRQ_EXIT(dma, dregs) do { \
+ if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
+ } while(0)
+
+/* Reset the friggin' thing... */
+#define DMA_RESET(dma) do { \
+ struct sparc_dma_registers *regs = dma->regs; \
+ /* Let the current FIFO drain itself */ \
+ sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
+ /* Reset the logic */ \
+ regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
+ __delay(400); /* let the bits set ;) */ \
+ regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
+ sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
+ /* Enable FAST transfers if available */ \
+ if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
+ dma->running = 0; \
+} while(0)
+
+
+#endif /* !CONFIG_SUN3 */
+
+#endif /* !(__M68K_DVMA_H) */
diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h
new file mode 100644
index 0000000..3d387ce
--- /dev/null
+++ b/arch/m68k/include/asm/elf.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASMm68k_ELF_H
+#define __ASMm68k_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include <asm/ptrace.h>
+#include <asm/user.h>
+
+/*
+ * 68k ELF relocation types
+ */
+#define R_68K_NONE 0
+#define R_68K_32 1
+#define R_68K_16 2
+#define R_68K_8 3
+#define R_68K_PC32 4
+#define R_68K_PC16 5
+#define R_68K_PC8 6
+#define R_68K_GOT32 7
+#define R_68K_GOT16 8
+#define R_68K_GOT8 9
+#define R_68K_GOT32O 10
+#define R_68K_GOT16O 11
+#define R_68K_GOT8O 12
+#define R_68K_PLT32 13
+#define R_68K_PLT16 14
+#define R_68K_PLT8 15
+#define R_68K_PLT32O 16
+#define R_68K_PLT16O 17
+#define R_68K_PLT8O 18
+#define R_68K_COPY 19
+#define R_68K_GLOB_DAT 20
+#define R_68K_JMP_SLOT 21
+#define R_68K_RELATIVE 22
+
+typedef unsigned long elf_greg_t;
+
+#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct user_m68kfp_struct elf_fpregset_t;
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == EM_68K)
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS ELFCLASS32
+#define ELF_DATA ELFDATA2MSB
+#define ELF_ARCH EM_68K
+
+/* For SVR4/m68k the function pointer to be registered with `atexit' is
+ passed in %a1. Although my copy of the ABI has no such statement, it
+ is actually used on ASV. */
+#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
+
+#if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE)
+#define ELF_EXEC_PAGESIZE 8192
+#else
+#define ELF_EXEC_PAGESIZE 4096
+#endif
+
+/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
+ use of this is to invoke "./ld.so someprog" to test out a new version of
+ the loader. We need to make sure that it is out of the way of the program
+ that it will "exec", and that there is sufficient room for the brk. */
+
+#ifndef CONFIG_SUN3
+#define ELF_ET_DYN_BASE 0xD0000000UL
+#else
+#define ELF_ET_DYN_BASE 0x0D800000UL
+#endif
+
+#define ELF_CORE_COPY_REGS(pr_reg, regs) \
+ /* Bleech. */ \
+ pr_reg[0] = regs->d1; \
+ pr_reg[1] = regs->d2; \
+ pr_reg[2] = regs->d3; \
+ pr_reg[3] = regs->d4; \
+ pr_reg[4] = regs->d5; \
+ pr_reg[7] = regs->a0; \
+ pr_reg[8] = regs->a1; \
+ pr_reg[9] = regs->a2; \
+ pr_reg[14] = regs->d0; \
+ pr_reg[15] = rdusp(); \
+ pr_reg[16] = regs->orig_d0; \
+ pr_reg[17] = regs->sr; \
+ pr_reg[18] = regs->pc; \
+ pr_reg[19] = (regs->format << 12) | regs->vector; \
+ { \
+ struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
+ pr_reg[5] = sw->d6; \
+ pr_reg[6] = sw->d7; \
+ pr_reg[10] = sw->a3; \
+ pr_reg[11] = sw->a4; \
+ pr_reg[12] = sw->a5; \
+ pr_reg[13] = sw->a6; \
+ }
+
+/* This yields a mask that user programs can use to figure out what
+ instruction set this cpu supports. */
+
+#define ELF_HWCAP (0)
+
+/* This yields a string that ld.so will use to load implementation
+ specific libraries for optimization. This is more specific in
+ intent than poking at uname or /proc/cpuinfo. */
+
+#define ELF_PLATFORM (NULL)
+
+#endif
diff --git a/arch/m68k/include/asm/entry.h b/arch/m68k/include/asm/entry.h
new file mode 100644
index 0000000..9b52b06
--- /dev/null
+++ b/arch/m68k/include/asm/entry.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __M68K_ENTRY_H
+#define __M68K_ENTRY_H
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#ifdef __ASSEMBLY__
+#include <asm/thread_info.h>
+#endif
+
+/*
+ * Stack layout in 'ret_from_exception':
+ *
+ * This allows access to the syscall arguments in registers d1-d5
+ *
+ * 0(sp) - d1
+ * 4(sp) - d2
+ * 8(sp) - d3
+ * C(sp) - d4
+ * 10(sp) - d5
+ * 14(sp) - a0
+ * 18(sp) - a1
+ * 1C(sp) - a2
+ * 20(sp) - d0
+ * 24(sp) - orig_d0
+ * 28(sp) - stack adjustment
+ * 2C(sp) - [ sr ] [ format & vector ]
+ * 2E(sp) - [ pc-hiword ] [ sr ]
+ * 30(sp) - [ pc-loword ] [ pc-hiword ]
+ * 32(sp) - [ format & vector ] [ pc-loword ]
+ * ^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^
+ * M68K COLDFIRE
+ */
+
+/* the following macro is used when enabling interrupts */
+#if defined(MACH_ATARI_ONLY)
+ /* block out HSYNC = ipl 2 on the atari */
+#define ALLOWINT (~0x500)
+#else
+ /* portable version */
+#define ALLOWINT (~0x700)
+#endif /* machine compilation types */
+
+#ifdef __ASSEMBLY__
+/*
+ * This defines the normal kernel pt-regs layout.
+ *
+ * regs a3-a6 and d6-d7 are preserved by C code
+ * the kernel doesn't mess with usp unless it needs to
+ */
+#define SWITCH_STACK_SIZE (6*4+4) /* includes return address */
+
+#ifdef CONFIG_COLDFIRE
+#ifdef CONFIG_COLDFIRE_SW_A7
+/*
+ * This is made a little more tricky on older ColdFires. There is no
+ * separate supervisor and user stack pointers. Need to artificially
+ * construct a usp in software... When doing this we need to disable
+ * interrupts, otherwise bad things will happen.
+ */
+.globl sw_usp
+.globl sw_ksp
+
+.macro SAVE_ALL_SYS
+ move #0x2700,%sr /* disable intrs */
+ btst #5,%sp@(2) /* from user? */
+ bnes 6f /* no, skip */
+ movel %sp,sw_usp /* save user sp */
+ addql #8,sw_usp /* remove exception */
+ movel sw_ksp,%sp /* kernel sp */
+ subql #8,%sp /* room for exception */
+ clrl %sp@- /* stkadj */
+ movel %d0,%sp@- /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ lea %sp@(-32),%sp /* space for 8 regs */
+ moveml %d1-%d5/%a0-%a2,%sp@
+ movel sw_usp,%a0 /* get usp */
+ movel %a0@-,%sp@(PT_OFF_PC) /* copy exception program counter */
+ movel %a0@-,%sp@(PT_OFF_FORMATVEC)/*copy exception format/vector/sr */
+ bra 7f
+ 6:
+ clrl %sp@- /* stkadj */
+ movel %d0,%sp@- /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ lea %sp@(-32),%sp /* space for 8 regs */
+ moveml %d1-%d5/%a0-%a2,%sp@
+ 7:
+.endm
+
+.macro SAVE_ALL_INT
+ SAVE_ALL_SYS
+ moveq #-1,%d0 /* not system call entry */
+ movel %d0,%sp@(PT_OFF_ORIG_D0)
+.endm
+
+.macro RESTORE_USER
+ move #0x2700,%sr /* disable intrs */
+ movel sw_usp,%a0 /* get usp */
+ movel %sp@(PT_OFF_PC),%a0@- /* copy exception program counter */
+ movel %sp@(PT_OFF_FORMATVEC),%a0@-/*copy exception format/vector/sr */
+ moveml %sp@,%d1-%d5/%a0-%a2
+ lea %sp@(32),%sp /* space for 8 regs */
+ movel %sp@+,%d0
+ addql #4,%sp /* orig d0 */
+ addl %sp@+,%sp /* stkadj */
+ addql #8,%sp /* remove exception */
+ movel %sp,sw_ksp /* save ksp */
+ subql #8,sw_usp /* set exception */
+ movel sw_usp,%sp /* restore usp */
+ rte
+.endm
+
+.macro RDUSP
+ movel sw_usp,%a3
+.endm
+
+.macro WRUSP
+ movel %a3,sw_usp
+.endm
+
+#else /* !CONFIG_COLDFIRE_SW_A7 */
+/*
+ * Modern ColdFire parts have separate supervisor and user stack
+ * pointers. Simple load and restore macros for this case.
+ */
+.macro SAVE_ALL_SYS
+ move #0x2700,%sr /* disable intrs */
+ clrl %sp@- /* stkadj */
+ movel %d0,%sp@- /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ lea %sp@(-32),%sp /* space for 8 regs */
+ moveml %d1-%d5/%a0-%a2,%sp@
+.endm
+
+.macro SAVE_ALL_INT
+ move #0x2700,%sr /* disable intrs */
+ clrl %sp@- /* stkadj */
+ pea -1:w /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ lea %sp@(-32),%sp /* space for 8 regs */
+ moveml %d1-%d5/%a0-%a2,%sp@
+.endm
+
+.macro RESTORE_USER
+ moveml %sp@,%d1-%d5/%a0-%a2
+ lea %sp@(32),%sp /* space for 8 regs */
+ movel %sp@+,%d0
+ addql #4,%sp /* orig d0 */
+ addl %sp@+,%sp /* stkadj */
+ rte
+.endm
+
+.macro RDUSP
+ /*move %usp,%a3*/
+ .word 0x4e6b
+.endm
+
+.macro WRUSP
+ /*move %a3,%usp*/
+ .word 0x4e63
+.endm
+
+#endif /* !CONFIG_COLDFIRE_SW_A7 */
+
+.macro SAVE_SWITCH_STACK
+ lea %sp@(-24),%sp /* 6 regs */
+ moveml %a3-%a6/%d6-%d7,%sp@
+.endm
+
+.macro RESTORE_SWITCH_STACK
+ moveml %sp@,%a3-%a6/%d6-%d7
+ lea %sp@(24),%sp /* 6 regs */
+.endm
+
+#else /* !CONFIG_COLDFIRE */
+
+/*
+ * All other types of m68k parts (68000, 680x0, CPU32) have the same
+ * entry and exit code.
+ */
+
+/*
+ * a -1 in the orig_d0 field signifies
+ * that the stack frame is NOT for syscall
+ */
+.macro SAVE_ALL_INT
+ clrl %sp@- /* stk_adj */
+ pea -1:w /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ moveml %d1-%d5/%a0-%a2,%sp@-
+.endm
+
+.macro SAVE_ALL_SYS
+ clrl %sp@- /* stk_adj */
+ movel %d0,%sp@- /* orig d0 */
+ movel %d0,%sp@- /* d0 */
+ moveml %d1-%d5/%a0-%a2,%sp@-
+.endm
+
+.macro RESTORE_ALL
+ moveml %sp@+,%a0-%a2/%d1-%d5
+ movel %sp@+,%d0
+ addql #4,%sp /* orig d0 */
+ addl %sp@+,%sp /* stk adj */
+ rte
+.endm
+
+
+.macro SAVE_SWITCH_STACK
+ moveml %a3-%a6/%d6-%d7,%sp@-
+.endm
+
+.macro RESTORE_SWITCH_STACK
+ moveml %sp@+,%a3-%a6/%d6-%d7
+.endm
+
+#endif /* !CONFIG_COLDFIRE */
+
+/*
+ * Register %a2 is reserved and set to current task on MMU enabled systems.
+ * Non-MMU systems do not reserve %a2 in this way, and this definition is
+ * not used for them.
+ */
+#ifdef CONFIG_MMU
+
+#define curptr a2
+
+#define GET_CURRENT(tmp) get_current tmp
+.macro get_current reg=%d0
+ movel %sp,\reg
+ andl #-THREAD_SIZE,\reg
+ movel \reg,%curptr
+ movel %curptr@,%curptr
+.endm
+
+#else
+
+#define GET_CURRENT(tmp)
+
+#endif /* CONFIG_MMU */
+
+#else /* C source */
+
+#define STR(X) STR1(X)
+#define STR1(X) #X
+
+#define SAVE_ALL_INT \
+ "clrl %%sp@-;" /* stk_adj */ \
+ "pea -1:w;" /* orig d0 = -1 */ \
+ "movel %%d0,%%sp@-;" /* d0 */ \
+ "moveml %%d1-%%d5/%%a0-%%a2,%%sp@-"
+
+#define GET_CURRENT(tmp) \
+ "movel %%sp,"#tmp"\n\t" \
+ "andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \
+ "movel "#tmp",%%a2\n\t" \
+ "movel %%a2@,%%a2"
+
+#endif
+
+#endif /* __M68K_ENTRY_H */
diff --git a/arch/m68k/include/asm/export.h b/arch/m68k/include/asm/export.h
new file mode 100644
index 0000000..0af20f4
--- /dev/null
+++ b/arch/m68k/include/asm/export.h
@@ -0,0 +1,3 @@
+#define KSYM_ALIGN 2
+#define KCRC_ALIGN 2
+#include <asm-generic/export.h>
diff --git a/arch/m68k/include/asm/fb.h b/arch/m68k/include/asm/fb.h
new file mode 100644
index 0000000..b86c6e2
--- /dev/null
+++ b/arch/m68k/include/asm/fb.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_FB_H_
+#define _ASM_FB_H_
+
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+
+#ifdef CONFIG_MMU
+#ifdef CONFIG_SUN3
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+ unsigned long off)
+{
+ pgprot_val(vma->vm_page_prot) |= SUN3_PAGE_NOCACHE;
+}
+#else
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+ unsigned long off)
+{
+ if (CPU_IS_020_OR_030)
+ pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE030;
+ if (CPU_IS_040_OR_060) {
+ pgprot_val(vma->vm_page_prot) &= _CACHEMASK040;
+ /* Use no-cache mode, serialized */
+ pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE_S;
+ }
+}
+#endif /* CONFIG_SUN3 */
+#else
+#define fb_pgprotect(...) do {} while (0)
+#endif /* CONFIG_MMU */
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+ return 0;
+}
+
+#endif /* _ASM_FB_H_ */
diff --git a/arch/m68k/include/asm/fbio.h b/arch/m68k/include/asm/fbio.h
new file mode 100644
index 0000000..590b923
--- /dev/null
+++ b/arch/m68k/include/asm/fbio.h
@@ -0,0 +1,331 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_FBIO_H
+#define __LINUX_FBIO_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+/* Constants used for fbio SunOS compatibility */
+/* (C) 1996 Miguel de Icaza */
+
+/* Frame buffer types */
+#define FBTYPE_NOTYPE -1
+#define FBTYPE_SUN1BW 0 /* mono */
+#define FBTYPE_SUN1COLOR 1
+#define FBTYPE_SUN2BW 2
+#define FBTYPE_SUN2COLOR 3
+#define FBTYPE_SUN2GP 4
+#define FBTYPE_SUN5COLOR 5
+#define FBTYPE_SUN3COLOR 6
+#define FBTYPE_MEMCOLOR 7
+#define FBTYPE_SUN4COLOR 8
+
+#define FBTYPE_NOTSUN1 9
+#define FBTYPE_NOTSUN2 10
+#define FBTYPE_NOTSUN3 11
+
+#define FBTYPE_SUNFAST_COLOR 12 /* cg6 */
+#define FBTYPE_SUNROP_COLOR 13
+#define FBTYPE_SUNFB_VIDEO 14
+#define FBTYPE_SUNGIFB 15
+#define FBTYPE_SUNGPLAS 16
+#define FBTYPE_SUNGP3 17
+#define FBTYPE_SUNGT 18
+#define FBTYPE_SUNLEO 19 /* zx Leo card */
+#define FBTYPE_MDICOLOR 20 /* cg14 */
+#define FBTYPE_TCXCOLOR 21 /* SUNW,tcx card */
+
+#define FBTYPE_LASTPLUSONE 21 /* This is not last + 1 in fact... */
+
+/* Does not seem to be listed in the Sun file either */
+#define FBTYPE_CREATOR 22
+#define FBTYPE_PCI_IGA1682 23
+#define FBTYPE_P9100COLOR 24
+
+#define FBTYPE_PCI_GENERIC 1000
+#define FBTYPE_PCI_MACH64 1001
+
+/* fbio ioctls */
+/* Returned by FBIOGTYPE */
+struct fbtype {
+ int fb_type; /* fb type, see above */
+ int fb_height; /* pixels */
+ int fb_width; /* pixels */
+ int fb_depth;
+ int fb_cmsize; /* color map entries */
+ int fb_size; /* fb size in bytes */
+};
+#define FBIOGTYPE _IOR('F', 0, struct fbtype)
+
+struct fbcmap {
+ int index; /* first element (0 origin) */
+ int count;
+ unsigned char __user *red;
+ unsigned char __user *green;
+ unsigned char __user *blue;
+};
+
+#ifdef __KERNEL__
+#define FBIOPUTCMAP_SPARC _IOW('F', 3, struct fbcmap)
+#define FBIOGETCMAP_SPARC _IOW('F', 4, struct fbcmap)
+#else
+#define FBIOPUTCMAP _IOW('F', 3, struct fbcmap)
+#define FBIOGETCMAP _IOW('F', 4, struct fbcmap)
+#endif
+
+/* # of device specific values */
+#define FB_ATTR_NDEVSPECIFIC 8
+/* # of possible emulations */
+#define FB_ATTR_NEMUTYPES 4
+
+struct fbsattr {
+ int flags;
+ int emu_type; /* -1 if none */
+ int dev_specific[FB_ATTR_NDEVSPECIFIC];
+};
+
+struct fbgattr {
+ int real_type; /* real frame buffer type */
+ int owner; /* unknown */
+ struct fbtype fbtype; /* real frame buffer fbtype */
+ struct fbsattr sattr;
+ int emu_types[FB_ATTR_NEMUTYPES]; /* supported emulations */
+};
+#define FBIOSATTR _IOW('F', 5, struct fbgattr) /* Unsupported: */
+#define FBIOGATTR _IOR('F', 6, struct fbgattr) /* supported */
+
+#define FBIOSVIDEO _IOW('F', 7, int)
+#define FBIOGVIDEO _IOR('F', 8, int)
+
+struct fbcursor {
+ short set; /* what to set, choose from the list above */
+ short enable; /* cursor on/off */
+ struct fbcurpos pos; /* cursor position */
+ struct fbcurpos hot; /* cursor hot spot */
+ struct fbcmap cmap; /* color map info */
+ struct fbcurpos size; /* cursor bit map size */
+ char __user *image; /* cursor image bits */
+ char __user *mask; /* cursor mask bits */
+};
+
+/* set/get cursor attributes/shape */
+#define FBIOSCURSOR _IOW('F', 24, struct fbcursor)
+#define FBIOGCURSOR _IOWR('F', 25, struct fbcursor)
+
+/* set/get cursor position */
+#define FBIOSCURPOS _IOW('F', 26, struct fbcurpos)
+#define FBIOGCURPOS _IOW('F', 27, struct fbcurpos)
+
+/* get max cursor size */
+#define FBIOGCURMAX _IOR('F', 28, struct fbcurpos)
+
+/* wid manipulation */
+struct fb_wid_alloc {
+#define FB_WID_SHARED_8 0
+#define FB_WID_SHARED_24 1
+#define FB_WID_DBL_8 2
+#define FB_WID_DBL_24 3
+ __u32 wa_type;
+ __s32 wa_index; /* Set on return */
+ __u32 wa_count;
+};
+struct fb_wid_item {
+ __u32 wi_type;
+ __s32 wi_index;
+ __u32 wi_attrs;
+ __u32 wi_values[32];
+};
+struct fb_wid_list {
+ __u32 wl_flags;
+ __u32 wl_count;
+ struct fb_wid_item *wl_list;
+};
+
+#define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
+#define FBIO_WID_FREE _IOW('F', 31, struct fb_wid_alloc)
+#define FBIO_WID_PUT _IOW('F', 32, struct fb_wid_list)
+#define FBIO_WID_GET _IOWR('F', 33, struct fb_wid_list)
+
+/* Creator ioctls */
+#define FFB_IOCTL ('F'<<8)
+#define FFB_SYS_INFO (FFB_IOCTL|80)
+#define FFB_CLUTREAD (FFB_IOCTL|81)
+#define FFB_CLUTPOST (FFB_IOCTL|82)
+#define FFB_SETDIAGMODE (FFB_IOCTL|83)
+#define FFB_GETMONITORID (FFB_IOCTL|84)
+#define FFB_GETVIDEOMODE (FFB_IOCTL|85)
+#define FFB_SETVIDEOMODE (FFB_IOCTL|86)
+#define FFB_SETSERVER (FFB_IOCTL|87)
+#define FFB_SETOVCTL (FFB_IOCTL|88)
+#define FFB_GETOVCTL (FFB_IOCTL|89)
+#define FFB_GETSAXNUM (FFB_IOCTL|90)
+#define FFB_FBDEBUG (FFB_IOCTL|91)
+
+/* Cg14 ioctls */
+#define MDI_IOCTL ('M'<<8)
+#define MDI_RESET (MDI_IOCTL|1)
+#define MDI_GET_CFGINFO (MDI_IOCTL|2)
+#define MDI_SET_PIXELMODE (MDI_IOCTL|3)
+# define MDI_32_PIX 32
+# define MDI_16_PIX 16
+# define MDI_8_PIX 8
+
+struct mdi_cfginfo {
+ int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
+ int mdi_type; /* FBTYPE name */
+ int mdi_height; /* height */
+ int mdi_width; /* width */
+ int mdi_size; /* available ram */
+ int mdi_mode; /* 8bpp, 16bpp or 32bpp */
+ int mdi_pixfreq; /* pixel clock (from PROM) */
+};
+
+/* SparcLinux specific ioctl for the MDI, should be replaced for
+ * the SET_XLUT/SET_CLUTn ioctls instead
+ */
+#define MDI_CLEAR_XLUT (MDI_IOCTL|9)
+
+/* leo & ffb ioctls */
+struct fb_clut_alloc {
+ __u32 clutid; /* Set on return */
+ __u32 flag;
+ __u32 index;
+};
+
+struct fb_clut {
+#define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
+ __u32 flag;
+ __u32 clutid;
+ __u32 offset;
+ __u32 count;
+ char * red;
+ char * green;
+ char * blue;
+};
+
+struct fb_clut32 {
+ __u32 flag;
+ __u32 clutid;
+ __u32 offset;
+ __u32 count;
+ __u32 red;
+ __u32 green;
+ __u32 blue;
+};
+
+#define LEO_CLUTALLOC _IOWR('L', 53, struct fb_clut_alloc)
+#define LEO_CLUTFREE _IOW('L', 54, struct fb_clut_alloc)
+#define LEO_CLUTREAD _IOW('L', 55, struct fb_clut)
+#define LEO_CLUTPOST _IOW('L', 56, struct fb_clut)
+#define LEO_SETGAMMA _IOW('L', 68, int) /* Not yet implemented */
+#define LEO_GETGAMMA _IOR('L', 69, int) /* Not yet implemented */
+
+#ifdef __KERNEL__
+/* Addresses on the fd of a cgsix that are mappable */
+#define CG6_FBC 0x70000000
+#define CG6_TEC 0x70001000
+#define CG6_BTREGS 0x70002000
+#define CG6_FHC 0x70004000
+#define CG6_THC 0x70005000
+#define CG6_ROM 0x70006000
+#define CG6_RAM 0x70016000
+#define CG6_DHC 0x80000000
+
+#define CG3_MMAP_OFFSET 0x4000000
+
+/* Addresses on the fd of a tcx that are mappable */
+#define TCX_RAM8BIT 0x00000000
+#define TCX_RAM24BIT 0x01000000
+#define TCX_UNK3 0x10000000
+#define TCX_UNK4 0x20000000
+#define TCX_CONTROLPLANE 0x28000000
+#define TCX_UNK6 0x30000000
+#define TCX_UNK7 0x38000000
+#define TCX_TEC 0x70000000
+#define TCX_BTREGS 0x70002000
+#define TCX_THC 0x70004000
+#define TCX_DHC 0x70008000
+#define TCX_ALT 0x7000a000
+#define TCX_SYNC 0x7000e000
+#define TCX_UNK2 0x70010000
+
+/* CG14 definitions */
+
+/* Offsets into the OBIO space: */
+#define CG14_REGS 0 /* registers */
+#define CG14_CURSORREGS 0x1000 /* cursor registers */
+#define CG14_DACREGS 0x2000 /* DAC registers */
+#define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
+#define CG14_CLUT1 0x4000 /* Color Look Up Table */
+#define CG14_CLUT2 0x5000 /* Color Look Up Table */
+#define CG14_CLUT3 0x6000 /* Color Look Up Table */
+#define CG14_AUTO 0xf000
+
+#endif /* KERNEL */
+
+/* These are exported to userland for applications to use */
+/* Mappable offsets for the cg14: control registers */
+#define MDI_DIRECT_MAP 0x10000000
+#define MDI_CTLREG_MAP 0x20000000
+#define MDI_CURSOR_MAP 0x30000000
+#define MDI_SHDW_VRT_MAP 0x40000000
+
+/* Mappable offsets for the cg14: frame buffer resolutions */
+/* 32 bits */
+#define MDI_CHUNKY_XBGR_MAP 0x50000000
+#define MDI_CHUNKY_BGR_MAP 0x60000000
+
+/* 16 bits */
+#define MDI_PLANAR_X16_MAP 0x70000000
+#define MDI_PLANAR_C16_MAP 0x80000000
+
+/* 8 bit is done as CG3 MMAP offset */
+/* 32 bits, planar */
+#define MDI_PLANAR_X32_MAP 0x90000000
+#define MDI_PLANAR_B32_MAP 0xa0000000
+#define MDI_PLANAR_G32_MAP 0xb0000000
+#define MDI_PLANAR_R32_MAP 0xc0000000
+
+/* Mappable offsets on leo */
+#define LEO_SS0_MAP 0x00000000
+#define LEO_LC_SS0_USR_MAP 0x00800000
+#define LEO_LD_SS0_MAP 0x00801000
+#define LEO_LX_CURSOR_MAP 0x00802000
+#define LEO_SS1_MAP 0x00803000
+#define LEO_LC_SS1_USR_MAP 0x01003000
+#define LEO_LD_SS1_MAP 0x01004000
+#define LEO_UNK_MAP 0x01005000
+#define LEO_LX_KRN_MAP 0x01006000
+#define LEO_LC_SS0_KRN_MAP 0x01007000
+#define LEO_LC_SS1_KRN_MAP 0x01008000
+#define LEO_LD_GBL_MAP 0x01009000
+#define LEO_UNK2_MAP 0x0100a000
+
+#ifdef __KERNEL__
+struct fbcmap32 {
+ int index; /* first element (0 origin) */
+ int count;
+ u32 red;
+ u32 green;
+ u32 blue;
+};
+
+#define FBIOPUTCMAP32 _IOW('F', 3, struct fbcmap32)
+#define FBIOGETCMAP32 _IOW('F', 4, struct fbcmap32)
+
+struct fbcursor32 {
+ short set; /* what to set, choose from the list above */
+ short enable; /* cursor on/off */
+ struct fbcurpos pos; /* cursor position */
+ struct fbcurpos hot; /* cursor hot spot */
+ struct fbcmap32 cmap; /* color map info */
+ struct fbcurpos size; /* cursor bit map size */
+ u32 image; /* cursor image bits */
+ u32 mask; /* cursor mask bits */
+};
+
+#define FBIOSCURSOR32 _IOW('F', 24, struct fbcursor32)
+#define FBIOGCURSOR32 _IOW('F', 25, struct fbcursor32)
+#endif
+
+#endif /* __LINUX_FBIO_H */
diff --git a/arch/m68k/include/asm/flat.h b/arch/m68k/include/asm/flat.h
new file mode 100644
index 0000000..4f1d1e3
--- /dev/null
+++ b/arch/m68k/include/asm/flat.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * flat.h -- uClinux flat-format executables
+ */
+
+#ifndef __M68KNOMMU_FLAT_H__
+#define __M68KNOMMU_FLAT_H__
+
+#include <linux/uaccess.h>
+
+#define flat_argvp_envp_on_stack() 1
+#define flat_old_ram_flag(flags) (flags)
+#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
+static inline int flat_get_addr_from_rp(u32 __user *rp, u32 relval, u32 flags,
+ u32 *addr, u32 *persistent)
+{
+#ifdef CONFIG_CPU_HAS_NO_UNALIGNED
+ return copy_from_user(addr, rp, 4) ? -EFAULT : 0;
+#else
+ return get_user(*addr, rp);
+#endif
+}
+
+static inline int flat_put_addr_at_rp(u32 __user *rp, u32 addr, u32 rel)
+{
+#ifdef CONFIG_CPU_HAS_NO_UNALIGNED
+ return copy_to_user(rp, &addr, 4) ? -EFAULT : 0;
+#else
+ return put_user(addr, rp);
+#endif
+}
+#define flat_get_relocate_addr(rel) (rel)
+
+static inline int flat_set_persistent(u32 relval, u32 *persistent)
+{
+ return 0;
+}
+
+#define FLAT_PLAT_INIT(regs) \
+ do { \
+ if (current->mm) \
+ (regs)->d5 = current->mm->start_data; \
+ } while (0)
+
+#endif /* __M68KNOMMU_FLAT_H__ */
diff --git a/arch/m68k/include/asm/floppy.h b/arch/m68k/include/asm/floppy.h
new file mode 100644
index 0000000..c3b9ad6
--- /dev/null
+++ b/arch/m68k/include/asm/floppy.h
@@ -0,0 +1,254 @@
+/*
+ * Implementation independent bits of the Floppy driver.
+ *
+ * much of this file is derived from what was originally the Q40 floppy driver.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999, 2000, 2001
+ *
+ * Sun3x support added 2/4/2000 Sam Creasey (sammy@sammy.net)
+ *
+ */
+
+#include <asm/io.h>
+
+#include <linux/vmalloc.h>
+
+asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id);
+
+/* constants... */
+
+#undef MAX_DMA_ADDRESS
+#define MAX_DMA_ADDRESS 0x00 /* nothing like that */
+
+
+/*
+ * Again, the CMOS information doesn't work on m68k..
+ */
+#define FLOPPY0_TYPE (MACH_IS_Q40 ? 6 : 4)
+#define FLOPPY1_TYPE 0
+
+/* basically PC init + set use_virtual_dma */
+#define FDC1 m68k_floppy_init()
+
+#define N_FDC 1
+#define N_DRIVE 8
+
+
+/* vdma globals adapted from asm-i386/floppy.h */
+
+static int virtual_dma_count=0;
+static int virtual_dma_residue=0;
+static char *virtual_dma_addr=NULL;
+static int virtual_dma_mode=0;
+static int doing_pdma=0;
+
+#include <asm/sun3xflop.h>
+
+extern spinlock_t dma_spin_lock;
+
+static __inline__ unsigned long claim_dma_lock(void)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&dma_spin_lock, flags);
+ return flags;
+}
+
+static __inline__ void release_dma_lock(unsigned long flags)
+{
+ spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+
+static __inline__ unsigned char fd_inb(int port)
+{
+ if(MACH_IS_Q40)
+ return inb_p(port);
+ else if(MACH_IS_SUN3X)
+ return sun3x_82072_fd_inb(port);
+ return 0;
+}
+
+static __inline__ void fd_outb(unsigned char value, int port)
+{
+ if(MACH_IS_Q40)
+ outb_p(value, port);
+ else if(MACH_IS_SUN3X)
+ sun3x_82072_fd_outb(value, port);
+}
+
+
+static int fd_request_irq(void)
+{
+ if(MACH_IS_Q40)
+ return request_irq(FLOPPY_IRQ, floppy_hardint,
+ 0, "floppy", floppy_hardint);
+ else if(MACH_IS_SUN3X)
+ return sun3xflop_request_irq();
+ return -ENXIO;
+}
+
+static void fd_free_irq(void)
+{
+ if(MACH_IS_Q40)
+ free_irq(FLOPPY_IRQ, floppy_hardint);
+}
+
+#define fd_request_dma() vdma_request_dma(FLOPPY_DMA,"floppy")
+#define fd_get_dma_residue() vdma_get_dma_residue(FLOPPY_DMA)
+#define fd_dma_mem_alloc(size) vdma_mem_alloc(size)
+#define fd_dma_setup(addr, size, mode, io) vdma_dma_setup(addr, size, mode, io)
+
+#define fd_enable_irq() /* nothing... */
+#define fd_disable_irq() /* nothing... */
+
+#define fd_free_dma() /* nothing */
+
+/* No 64k boundary crossing problems on Q40 - no DMA at all */
+#define CROSS_64KB(a,s) (0)
+
+#define DMA_MODE_READ 0x44 /* i386 look-alike */
+#define DMA_MODE_WRITE 0x48
+
+
+static int m68k_floppy_init(void)
+{
+ use_virtual_dma =1;
+ can_use_virtual_dma = 1;
+
+
+ if (MACH_IS_Q40)
+ return 0x3f0;
+ else if(MACH_IS_SUN3X)
+ return sun3xflop_init();
+ else
+ return -1;
+}
+
+
+static int vdma_request_dma(unsigned int dmanr, const char * device_id)
+{
+ return 0;
+}
+
+
+static int vdma_get_dma_residue(unsigned int dummy)
+{
+ return virtual_dma_count + virtual_dma_residue;
+}
+
+
+static unsigned long vdma_mem_alloc(unsigned long size)
+{
+ return (unsigned long) vmalloc(size);
+
+}
+
+static void _fd_dma_mem_free(unsigned long addr, unsigned long size)
+{
+ vfree((void *)addr);
+}
+#define fd_dma_mem_free(addr,size) _fd_dma_mem_free(addr, size)
+
+
+/* choose_dma_mode ???*/
+
+static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
+{
+ doing_pdma = 1;
+ virtual_dma_port = (MACH_IS_Q40 ? io : 0);
+ virtual_dma_mode = (mode == DMA_MODE_WRITE);
+ virtual_dma_addr = addr;
+ virtual_dma_count = size;
+ virtual_dma_residue = 0;
+ return 0;
+}
+
+
+
+static void fd_disable_dma(void)
+{
+ doing_pdma = 0;
+ virtual_dma_residue += virtual_dma_count;
+ virtual_dma_count=0;
+}
+
+
+
+/* this is the only truly Q40 specific function */
+
+asmlinkage irqreturn_t floppy_hardint(int irq, void *dev_id)
+{
+ register unsigned char st;
+
+#undef TRACE_FLPY_INT
+#define NO_FLOPPY_ASSEMBLER
+
+#ifdef TRACE_FLPY_INT
+ static int calls=0;
+ static int bytes=0;
+ static int dma_wait=0;
+#endif
+ if(!doing_pdma) {
+ floppy_interrupt(irq, dev_id);
+ return IRQ_HANDLED;
+ }
+
+#ifdef TRACE_FLPY_INT
+ if(!calls)
+ bytes = virtual_dma_count;
+#endif
+
+ {
+ register int lcount;
+ register char *lptr;
+
+ /* serve 1st byte fast: */
+
+ st=1;
+ for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
+ lcount; lcount--, lptr++) {
+ st=inb(virtual_dma_port+4) & 0xa0 ;
+ if(st != 0xa0)
+ break;
+ if(virtual_dma_mode)
+ outb_p(*lptr, virtual_dma_port+5);
+ else
+ *lptr = inb_p(virtual_dma_port+5);
+ }
+
+ virtual_dma_count = lcount;
+ virtual_dma_addr = lptr;
+ st = inb(virtual_dma_port+4);
+ }
+
+#ifdef TRACE_FLPY_INT
+ calls++;
+#endif
+ if(st == 0x20)
+ return IRQ_HANDLED;
+ if(!(st & 0x20)) {
+ virtual_dma_residue += virtual_dma_count;
+ virtual_dma_count=0;
+#ifdef TRACE_FLPY_INT
+ pr_info("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
+ virtual_dma_count, virtual_dma_residue, calls, bytes,
+ dma_wait);
+ calls = 0;
+ dma_wait=0;
+#endif
+ doing_pdma = 0;
+ floppy_interrupt(irq, dev_id);
+ return IRQ_HANDLED;
+ }
+#ifdef TRACE_FLPY_INT
+ if(!virtual_dma_count)
+ dma_wait++;
+#endif
+ return IRQ_HANDLED;
+}
+
+#define EXTRA_FLOPPY_PARAMS
diff --git a/arch/m68k/include/asm/fpu.h b/arch/m68k/include/asm/fpu.h
new file mode 100644
index 0000000..ab12be8
--- /dev/null
+++ b/arch/m68k/include/asm/fpu.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __M68K_FPU_H
+#define __M68K_FPU_H
+
+
+/*
+ * MAX floating point unit state size (FSAVE/FRESTORE)
+ */
+
+#if defined(CONFIG_M68020) || defined(CONFIG_M68030)
+#define FPSTATESIZE (216)
+#elif defined(CONFIG_M68040)
+#define FPSTATESIZE (96)
+#elif defined(CONFIG_M68KFPU_EMU)
+#define FPSTATESIZE (28)
+#elif defined(CONFIG_COLDFIRE) && defined(CONFIG_MMU)
+#define FPSTATESIZE (16)
+#elif defined(CONFIG_M68060)
+#define FPSTATESIZE (12)
+#else
+#define FPSTATESIZE (0)
+#endif
+
+#endif /* __M68K_FPU_H */
diff --git a/arch/m68k/include/asm/ftrace.h b/arch/m68k/include/asm/ftrace.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/m68k/include/asm/ftrace.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
new file mode 100644
index 0000000..2f6eec1
--- /dev/null
+++ b/arch/m68k/include/asm/gpio.h
@@ -0,0 +1,110 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+*/
+
+#ifndef coldfire_gpio_h
+#define coldfire_gpio_h
+
+#include <linux/io.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+/*
+ * The Generic GPIO functions
+ *
+ * If the gpio is a compile time constant and is one of the Coldfire gpios,
+ * use the inline version, otherwise dispatch thru gpiolib.
+ */
+
+static inline int gpio_get_value(unsigned gpio)
+{
+ if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
+ return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
+ else
+ return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+ if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX) {
+ if (gpio < MCFGPIO_SCR_START) {
+ unsigned long flags;
+ MCFGPIO_PORTTYPE data;
+
+ local_irq_save(flags);
+ data = mcfgpio_read(__mcfgpio_podr(gpio));
+ if (value)
+ data |= mcfgpio_bit(gpio);
+ else
+ data &= ~mcfgpio_bit(gpio);
+ mcfgpio_write(data, __mcfgpio_podr(gpio));
+ local_irq_restore(flags);
+ } else {
+ if (value)
+ mcfgpio_write(mcfgpio_bit(gpio),
+ MCFGPIO_SETR_PORT(gpio));
+ else
+ mcfgpio_write(~mcfgpio_bit(gpio),
+ MCFGPIO_CLRR_PORT(gpio));
+ }
+ } else
+ __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+#if defined(MCFGPIO_IRQ_MIN)
+ if ((gpio >= MCFGPIO_IRQ_MIN) && (gpio < MCFGPIO_IRQ_MAX))
+#else
+ if (gpio < MCFGPIO_IRQ_MAX)
+#endif
+ return gpio + MCFGPIO_IRQ_VECBASE;
+ else
+ return __gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned irq)
+{
+ return (irq >= MCFGPIO_IRQ_VECBASE &&
+ irq < (MCFGPIO_IRQ_VECBASE + MCFGPIO_IRQ_MAX)) ?
+ irq - MCFGPIO_IRQ_VECBASE : -ENXIO;
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+ return gpio < MCFGPIO_PIN_MAX ? 0 : __gpio_cansleep(gpio);
+}
+
+#ifndef CONFIG_GPIOLIB
+static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
+{
+ int err;
+
+ err = gpio_request(gpio, label);
+ if (err)
+ return err;
+
+ if (flags & GPIOF_DIR_IN)
+ err = gpio_direction_input(gpio);
+ else
+ err = gpio_direction_output(gpio,
+ (flags & GPIOF_INIT_HIGH) ? 1 : 0);
+
+ if (err)
+ gpio_free(gpio);
+
+ return err;
+}
+#endif /* !CONFIG_GPIOLIB */
+#endif
diff --git a/arch/m68k/include/asm/hardirq.h b/arch/m68k/include/asm/hardirq.h
new file mode 100644
index 0000000..1179316
--- /dev/null
+++ b/arch/m68k/include/asm/hardirq.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __M68K_HARDIRQ_H
+#define __M68K_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/cache.h>
+#include <asm/irq.h>
+
+#ifdef CONFIG_MMU
+
+static inline void ack_bad_irq(unsigned int irq)
+{
+ pr_crit("unexpected IRQ trap at vector %02x\n", irq);
+}
+
+/* entry.S is sensitive to the offsets of these fields */
+typedef struct {
+ unsigned int __softirq_pending;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
+
+#else
+
+#include <asm-generic/hardirq.h>
+
+#endif /* !CONFIG_MMU */
+
+#endif
diff --git a/arch/m68k/include/asm/hash.h b/arch/m68k/include/asm/hash.h
new file mode 100644
index 0000000..6d0d0c8
--- /dev/null
+++ b/arch/m68k/include/asm/hash.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_HASH_H
+#define _ASM_HASH_H
+
+/*
+ * If CONFIG_M68000=y (original mc68000/010), this file is #included
+ * to work around the lack of a MULU.L instruction.
+ */
+
+#define HAVE_ARCH__HASH_32 1
+/*
+ * While it would be legal to substitute a different hash operation
+ * entirely, let's keep it simple and just use an optimized multiply
+ * by GOLDEN_RATIO_32 = 0x61C88647.
+ *
+ * The best way to do that appears to be to multiply by 0x8647 with
+ * shifts and adds, and use mulu.w to multiply the high half by 0x61C8.
+ *
+ * Because the 68000 has multi-cycle shifts, this addition chain is
+ * chosen to minimise the shift distances.
+ *
+ * Despite every attempt to spoon-feed it simple operations, GCC
+ * 6.1.1 doggedly insists on doing annoying things like converting
+ * "lsl.l #2,<reg>" (12 cycles) to two adds (8+8 cycles).
+ *
+ * It also likes to notice two shifts in a row, like "a = x << 2" and
+ * "a <<= 7", and convert that to "a = x << 9". But shifts longer
+ * than 8 bits are extra-slow on m68k, so that's a lose.
+ *
+ * Since the 68000 is a very simple in-order processor with no
+ * instruction scheduling effects on execution time, we can safely
+ * take it out of GCC's hands and write one big asm() block.
+ *
+ * Without calling overhead, this operation is 30 bytes (14 instructions
+ * plus one immediate constant) and 166 cycles.
+ *
+ * (Because %2 is fetched twice, it can't be postincrement, and thus it
+ * can't be a fully general "g" or "m". Register is preferred, but
+ * offsettable memory or immediate will work.)
+ */
+static inline u32 __attribute_const__ __hash_32(u32 x)
+{
+ u32 a, b;
+
+ asm( "move.l %2,%0" /* a = x * 0x0001 */
+ "\n lsl.l #2,%0" /* a = x * 0x0004 */
+ "\n move.l %0,%1"
+ "\n lsl.l #7,%0" /* a = x * 0x0200 */
+ "\n add.l %2,%0" /* a = x * 0x0201 */
+ "\n add.l %0,%1" /* b = x * 0x0205 */
+ "\n add.l %0,%0" /* a = x * 0x0402 */
+ "\n add.l %0,%1" /* b = x * 0x0607 */
+ "\n lsl.l #5,%0" /* a = x * 0x8040 */
+ : "=&d,d" (a), "=&r,r" (b)
+ : "r,roi?" (x)); /* a+b = x*0x8647 */
+
+ return ((u16)(x*0x61c8) << 16) + a + b;
+}
+
+#endif /* _ASM_HASH_H */
diff --git a/arch/m68k/include/asm/hp300hw.h b/arch/m68k/include/asm/hp300hw.h
new file mode 100644
index 0000000..0909800
--- /dev/null
+++ b/arch/m68k/include/asm/hp300hw.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_HP300HW_H
+#define _M68K_HP300HW_H
+
+#include <asm/bootinfo-hp300.h>
+
+
+extern unsigned long hp300_model;
+
+#endif /* _M68K_HP300HW_H */
diff --git a/arch/m68k/include/asm/hwtest.h b/arch/m68k/include/asm/hwtest.h
new file mode 100644
index 0000000..f8d6462
--- /dev/null
+++ b/arch/m68k/include/asm/hwtest.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Routines to test for presence/absence of hardware registers:
+ * see arch/m68k/mm/hwtest.c.
+ * -- PMM <pmaydell@chiark.greenend.org.uk> 05/1998
+ *
+ * Removed __init from decls. We might want them in modules, and
+ * the code is tiny anyway. 16/5/98 pb
+ */
+
+#ifndef __ASM_HWTEST_H
+#define __ASM_HWTEST_H
+
+extern int hwreg_present(volatile void *regp);
+extern int hwreg_write(volatile void *regp, unsigned short val);
+
+#endif
diff --git a/arch/m68k/include/asm/ide.h b/arch/m68k/include/asm/ide.h
new file mode 100644
index 0000000..05cc7dc
--- /dev/null
+++ b/arch/m68k/include/asm/ide.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1994-1996 Linus Torvalds & authors
+ */
+
+/* Copyright(c) 1996 Kars de Jong */
+/* Based on the ide driver from 1.2.13pl8 */
+
+/*
+ * Credits (alphabetical):
+ *
+ * - Bjoern Brauel
+ * - Kars de Jong
+ * - Torsten Ebeling
+ * - Dwight Engen
+ * - Thorsten Floeck
+ * - Roman Hodek
+ * - Guenther Kelleter
+ * - Chris Lawrence
+ * - Michael Rausch
+ * - Christian Sauer
+ * - Michael Schmitz
+ * - Jes Soerensen
+ * - Michael Thurm
+ * - Geert Uytterhoeven
+ */
+
+#ifndef _M68K_IDE_H
+#define _M68K_IDE_H
+
+#ifdef __KERNEL__
+#include <asm/setup.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#ifdef CONFIG_MMU
+
+/*
+ * Get rid of defs from io.h - ide has its private and conflicting versions
+ * Since so far no single m68k platform uses ISA/PCI I/O space for IDE, we
+ * always use the `raw' MMIO versions
+ */
+#undef readb
+#undef readw
+#undef writeb
+#undef writew
+
+#define readb in_8
+#define readw in_be16
+#define __ide_mm_insw(port, addr, n) raw_insw((u16 *)port, addr, n)
+#define __ide_mm_insl(port, addr, n) raw_insl((u32 *)port, addr, n)
+#define writeb(val, port) out_8(port, val)
+#define writew(val, port) out_be16(port, val)
+#define __ide_mm_outsw(port, addr, n) raw_outsw((u16 *)port, addr, n)
+#define __ide_mm_outsl(port, addr, n) raw_outsl((u32 *)port, addr, n)
+
+#else
+
+#define __ide_mm_insw(port, addr, n) io_insw((unsigned int)port, addr, n)
+#define __ide_mm_insl(port, addr, n) io_insl((unsigned int)port, addr, n)
+#define __ide_mm_outsw(port, addr, n) io_outsw((unsigned int)port, addr, n)
+#define __ide_mm_outsl(port, addr, n) io_outsl((unsigned int)port, addr, n)
+
+#endif /* CONFIG_MMU */
+
+#endif /* __KERNEL__ */
+#endif /* _M68K_IDE_H */
diff --git a/arch/m68k/include/asm/idprom.h b/arch/m68k/include/asm/idprom.h
new file mode 100644
index 0000000..13b099d
--- /dev/null
+++ b/arch/m68k/include/asm/idprom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_IDPROM_H
+#define _M68K_IDPROM_H
+/*
+ * idprom.h: Macros and defines for idprom routines
+ *
+ * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#include <linux/types.h>
+
+struct idprom {
+ u8 id_format; /* Format identifier (always 0x01) */
+ u8 id_machtype; /* Machine type */
+ u8 id_ethaddr[6]; /* Hardware ethernet address */
+ s32 id_date; /* Date of manufacture */
+ u32 id_sernum:24; /* Unique serial number */
+ u8 id_cksum; /* Checksum - xor of the data bytes */
+ u8 reserved[16];
+};
+
+extern struct idprom *idprom;
+extern void idprom_init(void);
+
+/* Sun3: in control space */
+#define SUN3_IDPROM_BASE 0x00000000
+
+#endif /* !(_M68K_IDPROM_H) */
diff --git a/arch/m68k/include/asm/intersil.h b/arch/m68k/include/asm/intersil.h
new file mode 100644
index 0000000..b696348
--- /dev/null
+++ b/arch/m68k/include/asm/intersil.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _SUN3_INTERSIL_H
+#define _SUN3_INTERSIL_H
+/* bits 0 and 1 */
+#define INTERSIL_FREQ_32K 0x00
+#define INTERSIL_FREQ_1M 0x01
+#define INTERSIL_FREQ_2M 0x02
+#define INTERSIL_FREQ_4M 0x03
+
+/* bit 2 */
+#define INTERSIL_12H_MODE 0x00
+#define INTERSIL_24H_MODE 0x04
+
+/* bit 3 */
+#define INTERSIL_STOP 0x00
+#define INTERSIL_RUN 0x08
+
+/* bit 4 */
+#define INTERSIL_INT_ENABLE 0x10
+#define INTERSIL_INT_DISABLE 0x00
+
+/* bit 5 */
+#define INTERSIL_MODE_NORMAL 0x00
+#define INTERSIL_MODE_TEST 0x20
+
+#define INTERSIL_HZ_100_MASK 0x02
+
+struct intersil_dt {
+ unsigned char csec;
+ unsigned char hour;
+ unsigned char minute;
+ unsigned char second;
+ unsigned char month;
+ unsigned char day;
+ unsigned char year;
+ unsigned char weekday;
+};
+
+struct intersil_7170 {
+ struct intersil_dt counter;
+ struct intersil_dt alarm;
+ unsigned char int_reg;
+ unsigned char cmd_reg;
+};
+
+extern volatile char* clock_va;
+#define intersil_clock ((volatile struct intersil_7170 *) clock_va)
+#define intersil_clear() (void)intersil_clock->int_reg
+#endif
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
new file mode 100644
index 0000000..aabe642
--- /dev/null
+++ b/arch/m68k/include/asm/io.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_IO_H
+#define _M68K_IO_H
+
+#if defined(__uClinux__) || defined(CONFIG_COLDFIRE)
+#include <asm/io_no.h>
+#else
+#include <asm/io_mm.h>
+#endif
+
+#include <asm-generic/io.h>
+
+#endif /* _M68K_IO_H */
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
new file mode 100644
index 0000000..782b78f
--- /dev/null
+++ b/arch/m68k/include/asm/io_mm.h
@@ -0,0 +1,411 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * linux/include/asm-m68k/io.h
+ *
+ * 4/1/00 RZ: - rewritten to avoid clashes between ISA/PCI and other
+ * IO access
+ * - added Q40 support
+ * - added skeleton for GG-II and Amiga PCMCIA
+ * 2/3/01 RZ: - moved a few more defs into raw_io.h
+ *
+ * inX/outX should not be used by any driver unless it does
+ * ISA access. Other drivers should use function defined in raw_io.h
+ * or define its own macros on top of these.
+ *
+ * inX(),outX() are for ISA I/O
+ * isa_readX(),isa_writeX() are for ISA memory
+ */
+
+#ifndef _M68K_IO_MM_H
+#define _M68K_IO_MM_H
+
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <asm/raw_io.h>
+#include <asm/virtconvert.h>
+#include <asm/kmap.h>
+
+#include <asm-generic/iomap.h>
+
+#ifdef CONFIG_ATARI
+#include <asm/atarihw.h>
+#endif
+
+
+/*
+ * IO/MEM definitions for various ISA bridges
+ */
+
+
+#ifdef CONFIG_Q40
+
+#define q40_isa_io_base 0xff400000
+#define q40_isa_mem_base 0xff800000
+
+#define Q40_ISA_IO_B(ioaddr) (q40_isa_io_base+1+4*((unsigned long)(ioaddr)))
+#define Q40_ISA_IO_W(ioaddr) (q40_isa_io_base+ 4*((unsigned long)(ioaddr)))
+#define Q40_ISA_MEM_B(madr) (q40_isa_mem_base+1+4*((unsigned long)(madr)))
+#define Q40_ISA_MEM_W(madr) (q40_isa_mem_base+ 4*((unsigned long)(madr)))
+
+#define MULTI_ISA 0
+#endif /* Q40 */
+
+#ifdef CONFIG_AMIGA_PCMCIA
+#include <asm/amigayle.h>
+
+#define AG_ISA_IO_B(ioaddr) ( GAYLE_IO+(ioaddr)+(((ioaddr)&1)*GAYLE_ODD) )
+#define AG_ISA_IO_W(ioaddr) ( GAYLE_IO+(ioaddr) )
+
+#ifndef MULTI_ISA
+#define MULTI_ISA 0
+#else
+#undef MULTI_ISA
+#define MULTI_ISA 1
+#endif
+#endif /* AMIGA_PCMCIA */
+
+#ifdef CONFIG_ATARI_ROM_ISA
+
+#define enec_isa_read_base 0xfffa0000
+#define enec_isa_write_base 0xfffb0000
+
+#define ENEC_ISA_IO_B(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
+#define ENEC_ISA_IO_W(ioaddr) (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
+#define ENEC_ISA_MEM_B(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
+#define ENEC_ISA_MEM_W(madr) (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
+
+#ifndef MULTI_ISA
+#define MULTI_ISA 0
+#else
+#undef MULTI_ISA
+#define MULTI_ISA 1
+#endif
+#endif /* ATARI_ROM_ISA */
+
+
+#if defined(CONFIG_ISA) || defined(CONFIG_ATARI_ROM_ISA)
+
+#if MULTI_ISA == 0
+#undef MULTI_ISA
+#endif
+
+#define ISA_TYPE_Q40 (1)
+#define ISA_TYPE_AG (2)
+#define ISA_TYPE_ENEC (3)
+
+#if defined(CONFIG_Q40) && !defined(MULTI_ISA)
+#define ISA_TYPE ISA_TYPE_Q40
+#define ISA_SEX 0
+#endif
+#if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA)
+#define ISA_TYPE ISA_TYPE_AG
+#define ISA_SEX 1
+#endif
+#if defined(CONFIG_ATARI_ROM_ISA) && !defined(MULTI_ISA)
+#define ISA_TYPE ISA_TYPE_ENEC
+#define ISA_SEX 0
+#endif
+
+#ifdef MULTI_ISA
+extern int isa_type;
+extern int isa_sex;
+
+#define ISA_TYPE isa_type
+#define ISA_SEX isa_sex
+#endif
+
+/*
+ * define inline addr translation functions. Normally only one variant will
+ * be compiled in so the case statement will be optimised away
+ */
+
+static inline u8 __iomem *isa_itb(unsigned long addr)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_IO_B(addr);
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: return (u8 __iomem *)AG_ISA_IO_B(addr);
+#endif
+#ifdef CONFIG_ATARI_ROM_ISA
+ case ISA_TYPE_ENEC: return (u8 __iomem *)ENEC_ISA_IO_B(addr);
+#endif
+ default: return NULL; /* avoid warnings, just in case */
+ }
+}
+static inline u16 __iomem *isa_itw(unsigned long addr)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_IO_W(addr);
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: return (u16 __iomem *)AG_ISA_IO_W(addr);
+#endif
+#ifdef CONFIG_ATARI_ROM_ISA
+ case ISA_TYPE_ENEC: return (u16 __iomem *)ENEC_ISA_IO_W(addr);
+#endif
+ default: return NULL; /* avoid warnings, just in case */
+ }
+}
+static inline u32 __iomem *isa_itl(unsigned long addr)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: return (u32 __iomem *)AG_ISA_IO_W(addr);
+#endif
+ default: return 0; /* avoid warnings, just in case */
+ }
+}
+static inline u8 __iomem *isa_mtb(unsigned long addr)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case ISA_TYPE_Q40: return (u8 __iomem *)Q40_ISA_MEM_B(addr);
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: return (u8 __iomem *)addr;
+#endif
+#ifdef CONFIG_ATARI_ROM_ISA
+ case ISA_TYPE_ENEC: return (u8 __iomem *)ENEC_ISA_MEM_B(addr);
+#endif
+ default: return NULL; /* avoid warnings, just in case */
+ }
+}
+static inline u16 __iomem *isa_mtw(unsigned long addr)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case ISA_TYPE_Q40: return (u16 __iomem *)Q40_ISA_MEM_W(addr);
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: return (u16 __iomem *)addr;
+#endif
+#ifdef CONFIG_ATARI_ROM_ISA
+ case ISA_TYPE_ENEC: return (u16 __iomem *)ENEC_ISA_MEM_W(addr);
+#endif
+ default: return NULL; /* avoid warnings, just in case */
+ }
+}
+
+
+#define isa_inb(port) in_8(isa_itb(port))
+#define isa_inw(port) (ISA_SEX ? in_be16(isa_itw(port)) : in_le16(isa_itw(port)))
+#define isa_inl(port) (ISA_SEX ? in_be32(isa_itl(port)) : in_le32(isa_itl(port)))
+#define isa_outb(val,port) out_8(isa_itb(port),(val))
+#define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val)))
+#define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val)))
+
+#define isa_readb(p) in_8(isa_mtb((unsigned long)(p)))
+#define isa_readw(p) \
+ (ISA_SEX ? in_be16(isa_mtw((unsigned long)(p))) \
+ : in_le16(isa_mtw((unsigned long)(p))))
+#define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val))
+#define isa_writew(val,p) \
+ (ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \
+ : out_le16(isa_mtw((unsigned long)(p)),(val)))
+
+#ifdef CONFIG_ATARI_ROM_ISA
+#define isa_rom_inb(port) rom_in_8(isa_itb(port))
+#define isa_rom_inw(port) \
+ (ISA_SEX ? rom_in_be16(isa_itw(port)) \
+ : rom_in_le16(isa_itw(port)))
+
+#define isa_rom_outb(val, port) rom_out_8(isa_itb(port), (val))
+#define isa_rom_outw(val, port) \
+ (ISA_SEX ? rom_out_be16(isa_itw(port), (val)) \
+ : rom_out_le16(isa_itw(port), (val)))
+
+#define isa_rom_readb(p) rom_in_8(isa_mtb((unsigned long)(p)))
+#define isa_rom_readw(p) \
+ (ISA_SEX ? rom_in_be16(isa_mtw((unsigned long)(p))) \
+ : rom_in_le16(isa_mtw((unsigned long)(p))))
+#define isa_rom_readw_swap(p) \
+ (ISA_SEX ? rom_in_le16(isa_mtw((unsigned long)(p))) \
+ : rom_in_be16(isa_mtw((unsigned long)(p))))
+#define isa_rom_readw_raw(p) rom_in_be16(isa_mtw((unsigned long)(p)))
+
+#define isa_rom_writeb(val, p) rom_out_8(isa_mtb((unsigned long)(p)), (val))
+#define isa_rom_writew(val, p) \
+ (ISA_SEX ? rom_out_be16(isa_mtw((unsigned long)(p)), (val)) \
+ : rom_out_le16(isa_mtw((unsigned long)(p)), (val)))
+#define isa_rom_writew_swap(val, p) \
+ (ISA_SEX ? rom_out_le16(isa_mtw((unsigned long)(p)), (val)) \
+ : rom_out_be16(isa_mtw((unsigned long)(p)), (val)))
+#define isa_rom_writew_raw(val, p) rom_out_be16(isa_mtw((unsigned long)(p)), (val))
+#endif /* CONFIG_ATARI_ROM_ISA */
+
+static inline void isa_delay(void)
+{
+ switch(ISA_TYPE)
+ {
+#ifdef CONFIG_Q40
+ case ISA_TYPE_Q40: isa_outb(0,0x80); break;
+#endif
+#ifdef CONFIG_AMIGA_PCMCIA
+ case ISA_TYPE_AG: break;
+#endif
+#ifdef CONFIG_ATARI_ROM_ISA
+ case ISA_TYPE_ENEC: break;
+#endif
+ default: break; /* avoid warnings */
+ }
+}
+
+#define isa_inb_p(p) ({u8 v=isa_inb(p);isa_delay();v;})
+#define isa_outb_p(v,p) ({isa_outb((v),(p));isa_delay();})
+#define isa_inw_p(p) ({u16 v=isa_inw(p);isa_delay();v;})
+#define isa_outw_p(v,p) ({isa_outw((v),(p));isa_delay();})
+#define isa_inl_p(p) ({u32 v=isa_inl(p);isa_delay();v;})
+#define isa_outl_p(v,p) ({isa_outl((v),(p));isa_delay();})
+
+#define isa_insb(port, buf, nr) raw_insb(isa_itb(port), (u8 *)(buf), (nr))
+#define isa_outsb(port, buf, nr) raw_outsb(isa_itb(port), (u8 *)(buf), (nr))
+
+#define isa_insw(port, buf, nr) \
+ (ISA_SEX ? raw_insw(isa_itw(port), (u16 *)(buf), (nr)) : \
+ raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
+
+#define isa_outsw(port, buf, nr) \
+ (ISA_SEX ? raw_outsw(isa_itw(port), (u16 *)(buf), (nr)) : \
+ raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
+
+#define isa_insl(port, buf, nr) \
+ (ISA_SEX ? raw_insl(isa_itl(port), (u32 *)(buf), (nr)) : \
+ raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
+
+#define isa_outsl(port, buf, nr) \
+ (ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \
+ raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
+
+
+#ifdef CONFIG_ATARI_ROM_ISA
+#define isa_rom_inb_p(p) ({ u8 _v = isa_rom_inb(p); isa_delay(); _v; })
+#define isa_rom_inw_p(p) ({ u16 _v = isa_rom_inw(p); isa_delay(); _v; })
+#define isa_rom_outb_p(v, p) ({ isa_rom_outb((v), (p)); isa_delay(); })
+#define isa_rom_outw_p(v, p) ({ isa_rom_outw((v), (p)); isa_delay(); })
+
+#define isa_rom_insb(port, buf, nr) raw_rom_insb(isa_itb(port), (u8 *)(buf), (nr))
+
+#define isa_rom_insw(port, buf, nr) \
+ (ISA_SEX ? raw_rom_insw(isa_itw(port), (u16 *)(buf), (nr)) : \
+ raw_rom_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
+
+#define isa_rom_outsb(port, buf, nr) raw_rom_outsb(isa_itb(port), (u8 *)(buf), (nr))
+
+#define isa_rom_outsw(port, buf, nr) \
+ (ISA_SEX ? raw_rom_outsw(isa_itw(port), (u16 *)(buf), (nr)) : \
+ raw_rom_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
+#endif /* CONFIG_ATARI_ROM_ISA */
+
+#endif /* CONFIG_ISA || CONFIG_ATARI_ROM_ISA */
+
+
+#if defined(CONFIG_ISA) && !defined(CONFIG_ATARI_ROM_ISA)
+#define inb isa_inb
+#define inb_p isa_inb_p
+#define outb isa_outb
+#define outb_p isa_outb_p
+#define inw isa_inw
+#define inw_p isa_inw_p
+#define outw isa_outw
+#define outw_p isa_outw_p
+#define inl isa_inl
+#define inl_p isa_inl_p
+#define outl isa_outl
+#define outl_p isa_outl_p
+#define insb isa_insb
+#define insw isa_insw
+#define insl isa_insl
+#define outsb isa_outsb
+#define outsw isa_outsw
+#define outsl isa_outsl
+#define readb isa_readb
+#define readw isa_readw
+#define writeb isa_writeb
+#define writew isa_writew
+#endif /* CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */
+
+#ifdef CONFIG_ATARI_ROM_ISA
+/*
+ * kernel with both ROM port ISA and IDE compiled in, those have
+ * conflicting defs for in/out. Simply consider port < 1024
+ * ROM port ISA and everything else regular ISA for IDE. read,write defined
+ * below.
+ */
+#define inb(port) ((port) < 1024 ? isa_rom_inb(port) : in_8(port))
+#define inb_p(port) ((port) < 1024 ? isa_rom_inb_p(port) : in_8(port))
+#define inw(port) ((port) < 1024 ? isa_rom_inw(port) : in_le16(port))
+#define inw_p(port) ((port) < 1024 ? isa_rom_inw_p(port) : in_le16(port))
+#define inl isa_inl
+#define inl_p isa_inl_p
+
+#define outb(val, port) ((port) < 1024 ? isa_rom_outb((val), (port)) : out_8((port), (val)))
+#define outb_p(val, port) ((port) < 1024 ? isa_rom_outb_p((val), (port)) : out_8((port), (val)))
+#define outw(val, port) ((port) < 1024 ? isa_rom_outw((val), (port)) : out_le16((port), (val)))
+#define outw_p(val, port) ((port) < 1024 ? isa_rom_outw_p((val), (port)) : out_le16((port), (val)))
+#define outl isa_outl
+#define outl_p isa_outl_p
+
+#define insb(port, buf, nr) ((port) < 1024 ? isa_rom_insb((port), (buf), (nr)) : isa_insb((port), (buf), (nr)))
+#define insw(port, buf, nr) ((port) < 1024 ? isa_rom_insw((port), (buf), (nr)) : isa_insw((port), (buf), (nr)))
+#define insl isa_insl
+#define outsb(port, buf, nr) ((port) < 1024 ? isa_rom_outsb((port), (buf), (nr)) : isa_outsb((port), (buf), (nr)))
+#define outsw(port, buf, nr) ((port) < 1024 ? isa_rom_outsw((port), (buf), (nr)) : isa_outsw((port), (buf), (nr)))
+#define outsl isa_outsl
+
+#define readb(addr) in_8(addr)
+#define writeb(val, addr) out_8((addr), (val))
+#define readw(addr) in_le16(addr)
+#define writew(val, addr) out_le16((addr), (val))
+#endif /* CONFIG_ATARI_ROM_ISA */
+
+#define readl(addr) in_le32(addr)
+#define writel(val,addr) out_le32((addr),(val))
+
+#define readsb(port, buf, nr) raw_insb((port), (u8 *)(buf), (nr))
+#define readsw(port, buf, nr) raw_insw((port), (u16 *)(buf), (nr))
+#define readsl(port, buf, nr) raw_insl((port), (u32 *)(buf), (nr))
+#define writesb(port, buf, nr) raw_outsb((port), (u8 *)(buf), (nr))
+#define writesw(port, buf, nr) raw_outsw((port), (u16 *)(buf), (nr))
+#define writesl(port, buf, nr) raw_outsl((port), (u32 *)(buf), (nr))
+
+#define mmiowb()
+
+#ifndef CONFIG_SUN3
+#define IO_SPACE_LIMIT 0xffff
+#else
+#define IO_SPACE_LIMIT 0x0fffffff
+#endif
+
+#endif /* __KERNEL__ */
+
+#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p) __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p) p
+
+#define readb_relaxed(addr) readb(addr)
+#define readw_relaxed(addr) readw(addr)
+#define readl_relaxed(addr) readl(addr)
+
+#define writeb_relaxed(b, addr) writeb(b, addr)
+#define writew_relaxed(b, addr) writew(b, addr)
+#define writel_relaxed(b, addr) writel(b, addr)
+
+#endif /* _M68K_IO_MM_H */
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
new file mode 100644
index 0000000..0498192
--- /dev/null
+++ b/arch/m68k/include/asm/io_no.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68KNOMMU_IO_H
+#define _M68KNOMMU_IO_H
+
+/*
+ * Convert a physical memory address into a IO memory address.
+ * For us this is trivially a type cast.
+ */
+#define iomem(a) ((void __iomem *) (a))
+
+/*
+ * The non-MMU m68k and ColdFire IO and memory mapped hardware access
+ * functions have always worked in CPU native endian. We need to define
+ * that behavior here first before we include asm-generic/io.h.
+ */
+#define __raw_readb(addr) \
+ ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
+#define __raw_readw(addr) \
+ ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
+#define __raw_readl(addr) \
+ ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+#define __raw_writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define __raw_writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define __raw_writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+#if defined(CONFIG_COLDFIRE)
+/*
+ * For ColdFire platforms we may need to do some extra checks for what
+ * type of address range we are accessing. Include the ColdFire platform
+ * definitions so we can figure out if need to do something special.
+ */
+#include <asm/byteorder.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#endif /* CONFIG_COLDFIRE */
+
+#if defined(IOMEMBASE)
+/*
+ * The ColdFire SoC internal peripherals are mapped into virtual address
+ * space using the ACR registers of the cache control unit. This means we
+ * are using a 1:1 physical:virtual mapping for them. We can quickly
+ * determine if we are accessing an internal peripheral device given the
+ * physical or vitrual address using the same range check. This check logic
+ * applies just the same of there is no MMU but something like a PCI bus
+ * is present.
+ */
+static int __cf_internalio(unsigned long addr)
+{
+ return (addr >= IOMEMBASE) && (addr <= IOMEMBASE + IOMEMSIZE - 1);
+}
+
+static int cf_internalio(const volatile void __iomem *addr)
+{
+ return __cf_internalio((unsigned long) addr);
+}
+
+/*
+ * We need to treat built-in peripherals and bus based address ranges
+ * differently. Local built-in peripherals (and the ColdFire SoC parts
+ * have quite a lot of them) are always native endian - which is big
+ * endian on m68k/ColdFire. Bus based address ranges, like the PCI bus,
+ * are accessed little endian - so we need to byte swap those.
+ */
+#define readw readw
+static inline u16 readw(const volatile void __iomem *addr)
+{
+ if (cf_internalio(addr))
+ return __raw_readw(addr);
+ return __le16_to_cpu(__raw_readw(addr));
+}
+
+#define readl readl
+static inline u32 readl(const volatile void __iomem *addr)
+{
+ if (cf_internalio(addr))
+ return __raw_readl(addr);
+ return __le32_to_cpu(__raw_readl(addr));
+}
+
+#define writew writew
+static inline void writew(u16 value, volatile void __iomem *addr)
+{
+ if (cf_internalio(addr))
+ __raw_writew(value, addr);
+ else
+ __raw_writew(__cpu_to_le16(value), addr);
+}
+
+#define writel writel
+static inline void writel(u32 value, volatile void __iomem *addr)
+{
+ if (cf_internalio(addr))
+ __raw_writel(value, addr);
+ else
+ __raw_writel(__cpu_to_le32(value), addr);
+}
+
+#else
+
+#define readb __raw_readb
+#define readw __raw_readw
+#define readl __raw_readl
+#define writeb __raw_writeb
+#define writew __raw_writew
+#define writel __raw_writel
+
+#endif /* IOMEMBASE */
+
+#if defined(CONFIG_PCI)
+/*
+ * Support for PCI bus access uses the asm-generic access functions.
+ * We need to supply the base address and masks for the normal memory
+ * and IO address space mappings.
+ */
+#define PCI_MEM_PA 0xf0000000 /* Host physical address */
+#define PCI_MEM_BA 0xf0000000 /* Bus physical address */
+#define PCI_MEM_SIZE 0x08000000 /* 128 MB */
+#define PCI_MEM_MASK (PCI_MEM_SIZE - 1)
+
+#define PCI_IO_PA 0xf8000000 /* Host physical address */
+#define PCI_IO_BA 0x00000000 /* Bus physical address */
+#define PCI_IO_SIZE 0x00010000 /* 64k */
+#define PCI_IO_MASK (PCI_IO_SIZE - 1)
+
+#define HAVE_ARCH_PIO_SIZE
+#define PIO_OFFSET 0
+#define PIO_MASK 0xffff
+#define PIO_RESERVED 0x10000
+#define PCI_IOBASE ((void __iomem *) PCI_IO_PA)
+#define PCI_SPACE_LIMIT PCI_IO_MASK
+#endif /* CONFIG_PCI */
+
+#include <asm/kmap.h>
+#include <asm/virtconvert.h>
+
+#endif /* _M68KNOMMU_IO_H */
diff --git a/arch/m68k/include/asm/irq.h b/arch/m68k/include/asm/irq.h
new file mode 100644
index 0000000..91dd493
--- /dev/null
+++ b/arch/m68k/include/asm/irq.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_IRQ_H_
+#define _M68K_IRQ_H_
+
+/*
+ * This should be the same as the max(NUM_X_SOURCES) for all the
+ * different m68k hosts compiled into the kernel.
+ * Currently the Atari has 72 and the Amiga 24, but if both are
+ * supported in the kernel it is better to make room for 72.
+ * With EtherNAT add-on card on Atari, the highest interrupt
+ * number is 140 so NR_IRQS needs to be 141.
+ */
+#if defined(CONFIG_COLDFIRE)
+#define NR_IRQS 256
+#elif defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
+#define NR_IRQS 200
+#elif defined(CONFIG_ATARI)
+#define NR_IRQS 141
+#elif defined(CONFIG_MAC)
+#define NR_IRQS 72
+#elif defined(CONFIG_Q40)
+#define NR_IRQS 43
+#elif defined(CONFIG_AMIGA) || !defined(CONFIG_MMU)
+#define NR_IRQS 32
+#elif defined(CONFIG_APOLLO)
+#define NR_IRQS 24
+#elif defined(CONFIG_HP300)
+#define NR_IRQS 8
+#else
+#define NR_IRQS 0
+#endif
+
+#if defined(CONFIG_M68020) || defined(CONFIG_M68030) || \
+ defined(CONFIG_M68040) || defined(CONFIG_M68060)
+
+/*
+ * Interrupt source definitions
+ * General interrupt sources are the level 1-7.
+ * Adding an interrupt service routine for one of these sources
+ * results in the addition of that routine to a chain of routines.
+ * Each one is called in succession. Each individual interrupt
+ * service routine should determine if the device associated with
+ * that routine requires service.
+ */
+
+#define IRQ_SPURIOUS 0
+
+#define IRQ_AUTO_1 1 /* level 1 interrupt */
+#define IRQ_AUTO_2 2 /* level 2 interrupt */
+#define IRQ_AUTO_3 3 /* level 3 interrupt */
+#define IRQ_AUTO_4 4 /* level 4 interrupt */
+#define IRQ_AUTO_5 5 /* level 5 interrupt */
+#define IRQ_AUTO_6 6 /* level 6 interrupt */
+#define IRQ_AUTO_7 7 /* level 7 interrupt (non-maskable) */
+
+#define IRQ_USER 8
+
+struct irq_data;
+struct irq_chip;
+struct irq_desc;
+extern unsigned int m68k_irq_startup(struct irq_data *data);
+extern unsigned int m68k_irq_startup_irq(unsigned int irq);
+extern void m68k_irq_shutdown(struct irq_data *data);
+extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int,
+ struct pt_regs *));
+extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt);
+extern void m68k_setup_irq_controller(struct irq_chip *,
+ void (*handle)(struct irq_desc *desc),
+ unsigned int irq, unsigned int cnt);
+
+extern unsigned int irq_canonicalize(unsigned int irq);
+
+#else
+#define irq_canonicalize(irq) (irq)
+#endif /* !(CONFIG_M68020 || CONFIG_M68030 || CONFIG_M68040 || CONFIG_M68060) */
+
+asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
+extern atomic_t irq_err_count;
+
+#endif /* _M68K_IRQ_H_ */
diff --git a/arch/m68k/include/asm/irqflags.h b/arch/m68k/include/asm/irqflags.h
new file mode 100644
index 0000000..3799a24
--- /dev/null
+++ b/arch/m68k/include/asm/irqflags.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_IRQFLAGS_H
+#define _M68K_IRQFLAGS_H
+
+#include <linux/types.h>
+#include <linux/preempt.h>
+#include <asm/thread_info.h>
+#include <asm/entry.h>
+
+static inline unsigned long arch_local_save_flags(void)
+{
+ unsigned long flags;
+ asm volatile ("movew %%sr,%0" : "=d" (flags) : : "memory");
+ return flags;
+}
+
+static inline void arch_local_irq_disable(void)
+{
+#ifdef CONFIG_COLDFIRE
+ asm volatile (
+ "move %/sr,%%d0 \n\t"
+ "ori.l #0x0700,%%d0 \n\t"
+ "move %%d0,%/sr \n"
+ : /* no outputs */
+ :
+ : "cc", "%d0", "memory");
+#else
+ asm volatile ("oriw #0x0700,%%sr" : : : "memory");
+#endif
+}
+
+static inline void arch_local_irq_enable(void)
+{
+#if defined(CONFIG_COLDFIRE)
+ asm volatile (
+ "move %/sr,%%d0 \n\t"
+ "andi.l #0xf8ff,%%d0 \n\t"
+ "move %%d0,%/sr \n"
+ : /* no outputs */
+ :
+ : "cc", "%d0", "memory");
+#else
+# if defined(CONFIG_MMU)
+ if (MACH_IS_Q40 || !hardirq_count())
+# endif
+ asm volatile (
+ "andiw %0,%%sr"
+ :
+ : "i" (ALLOWINT)
+ : "memory");
+#endif
+}
+
+static inline unsigned long arch_local_irq_save(void)
+{
+ unsigned long flags = arch_local_save_flags();
+ arch_local_irq_disable();
+ return flags;
+}
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+ asm volatile ("movew %0,%%sr" : : "d" (flags) : "memory");
+}
+
+static inline bool arch_irqs_disabled_flags(unsigned long flags)
+{
+ if (MACH_IS_ATARI) {
+ /* Ignore HSYNC = ipl 2 on Atari */
+ return (flags & ~(ALLOWINT | 0x200)) != 0;
+ }
+ return (flags & ~ALLOWINT) != 0;
+}
+
+static inline bool arch_irqs_disabled(void)
+{
+ return arch_irqs_disabled_flags(arch_local_save_flags());
+}
+
+#endif /* _M68K_IRQFLAGS_H */
diff --git a/arch/m68k/include/asm/kexec.h b/arch/m68k/include/asm/kexec.h
new file mode 100644
index 0000000..f5a8b2d
--- /dev/null
+++ b/arch/m68k/include/asm/kexec.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_KEXEC_H
+#define _ASM_M68K_KEXEC_H
+
+#ifdef CONFIG_KEXEC
+
+/* Maximum physical address we can use pages from */
+#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
+/* Maximum address we can reach in physical address mode */
+#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
+/* Maximum address we can use for the control code buffer */
+#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
+
+#define KEXEC_CONTROL_PAGE_SIZE 4096
+
+#define KEXEC_ARCH KEXEC_ARCH_68K
+
+#ifndef __ASSEMBLY__
+
+static inline void crash_setup_regs(struct pt_regs *newregs,
+ struct pt_regs *oldregs)
+{
+ /* Dummy implementation for now */
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_KEXEC */
+
+#endif /* _ASM_M68K_KEXEC_H */
diff --git a/arch/m68k/include/asm/kmap.h b/arch/m68k/include/asm/kmap.h
new file mode 100644
index 0000000..aac7f04
--- /dev/null
+++ b/arch/m68k/include/asm/kmap.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _KMAP_H
+#define _KMAP_H
+
+#ifdef CONFIG_MMU
+
+#define ARCH_HAS_IOREMAP_WT
+
+/* Values for nocacheflag and cmode */
+#define IOMAP_FULL_CACHING 0
+#define IOMAP_NOCACHE_SER 1
+#define IOMAP_NOCACHE_NONSER 2
+#define IOMAP_WRITETHROUGH 3
+
+/*
+ * These functions exported by arch/m68k/mm/kmap.c.
+ * Only needed on MMU enabled systems.
+ */
+extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
+ int cacheflag);
+#define iounmap iounmap
+extern void iounmap(void __iomem *addr);
+extern void __iounmap(void *addr, unsigned long size);
+
+#define ioremap ioremap
+static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+
+#define ioremap_nocache ioremap_nocache
+static inline void __iomem *ioremap_nocache(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+
+#define ioremap_uc ioremap_nocache
+#define ioremap_wt ioremap_wt
+static inline void __iomem *ioremap_wt(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+
+#define ioremap_fullcache ioremap_fullcache
+static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+#define memset_io memset_io
+static inline void memset_io(volatile void __iomem *addr, unsigned char val,
+ int count)
+{
+ __builtin_memset((void __force *) addr, val, count);
+}
+
+#define memcpy_fromio memcpy_fromio
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
+ int count)
+{
+ __builtin_memcpy(dst, (void __force *) src, count);
+}
+
+#define memcpy_toio memcpy_toio
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
+ int count)
+{
+ __builtin_memcpy((void __force *) dst, src, count);
+}
+
+#endif /* CONFIG_MMU */
+
+#define ioport_map ioport_map
+static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+ return (void __iomem *) port;
+}
+
+#define ioport_unmap ioport_unmap
+static inline void ioport_unmap(void __iomem *p)
+{
+}
+
+#endif /* _KMAP_H */
diff --git a/arch/m68k/include/asm/linkage.h b/arch/m68k/include/asm/linkage.h
new file mode 100644
index 0000000..c8b8428
--- /dev/null
+++ b/arch/m68k/include/asm/linkage.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .align 4
+#define __ALIGN_STR ".align 4"
+
+/*
+ * Make sure the compiler doesn't do anything stupid with the
+ * arguments on the stack - they are owned by the *caller*, not
+ * the callee. This just fools gcc into not spilling into them,
+ * and keeps it from doing tailcall recursion and/or using the
+ * stack slots for temporaries, since they are live and "used"
+ * all the way to the end of the function.
+ */
+#define asmlinkage_protect(n, ret, args...) \
+ __asmlinkage_protect##n(ret, ##args)
+#define __asmlinkage_protect_n(ret, args...) \
+ __asm__ __volatile__ ("" : "=r" (ret) : "0" (ret), ##args)
+#define __asmlinkage_protect0(ret) \
+ __asmlinkage_protect_n(ret)
+#define __asmlinkage_protect1(ret, arg1) \
+ __asmlinkage_protect_n(ret, "m" (arg1))
+#define __asmlinkage_protect2(ret, arg1, arg2) \
+ __asmlinkage_protect_n(ret, "m" (arg1), "m" (arg2))
+#define __asmlinkage_protect3(ret, arg1, arg2, arg3) \
+ __asmlinkage_protect_n(ret, "m" (arg1), "m" (arg2), "m" (arg3))
+#define __asmlinkage_protect4(ret, arg1, arg2, arg3, arg4) \
+ __asmlinkage_protect_n(ret, "m" (arg1), "m" (arg2), "m" (arg3), \
+ "m" (arg4))
+#define __asmlinkage_protect5(ret, arg1, arg2, arg3, arg4, arg5) \
+ __asmlinkage_protect_n(ret, "m" (arg1), "m" (arg2), "m" (arg3), \
+ "m" (arg4), "m" (arg5))
+#define __asmlinkage_protect6(ret, arg1, arg2, arg3, arg4, arg5, arg6) \
+ __asmlinkage_protect_n(ret, "m" (arg1), "m" (arg2), "m" (arg3), \
+ "m" (arg4), "m" (arg5), "m" (arg6))
+
+#endif
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
new file mode 100644
index 0000000..ceb4267
--- /dev/null
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m5206sim.h -- ColdFire 5206 System Integration Module support.
+ *
+ * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ */
+
+/****************************************************************************/
+#ifndef m5206sim_h
+#define m5206sim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m5206)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK MCF_CLK
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 5206 SIM register set addresses.
+ */
+#define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
+#define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
+#define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
+#define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
+#ifdef CONFIG_M5206e
+#define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
+#define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
+#endif
+
+#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
+#define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
+
+#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
+#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
+
+#define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
+#define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
+
+#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
+#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
+#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
+#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
+
+#define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
+#define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
+#define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
+#define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
+#define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
+#define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
+#define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
+#define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
+#define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
+#define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
+#define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
+#define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
+#define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
+#define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
+#define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
+#define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
+#define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
+#define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
+#define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
+#define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
+#define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
+#define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
+#define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
+#define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
+#define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */
+
+#ifdef CONFIG_M5206e
+#define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */
+#else
+#define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */
+#endif
+
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
+
+#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
+#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
+
+#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
+
+#if defined(CONFIG_NETtel)
+#define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
+#else
+#define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
+#endif
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
+#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
+#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+#define MCF_IRQ_UART0 73 /* UART0 */
+#define MCF_IRQ_UART1 74 /* UART1 */
+
+/*
+ * Generic GPIO
+ */
+#define MCFGPIO_PIN_MAX 8
+#define MCFGPIO_IRQ_VECBASE -1
+#define MCFGPIO_IRQ_MAX -1
+
+/*
+ * Some symbol defines for the Parallel Port Pin Assignment Register
+ */
+#ifdef CONFIG_M5206e
+#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */
+ /* Clear to select T0 input */
+#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */
+ /* Clear to select T0 output */
+#endif
+
+/*
+ * Some symbol defines for the Interrupt Control Register
+ */
+#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
+#define MCFSIM_I2CICR MCFSIM_ICR11 /* I2C ICR */
+#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
+#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
+#ifdef CONFIG_M5206e
+#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
+#endif
+
+/*
+ * I2C Controller
+*/
+#define MCFI2C_BASE0 (MCF_MBAR + 0x1e0)
+#define MCFI2C_SIZE0 0x40
+
+/****************************************************************************/
+#endif /* m5206sim_h */
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
new file mode 100644
index 0000000..8b3da56
--- /dev/null
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
+ *
+ * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
+ */
+
+/****************************************************************************/
+#ifndef m520xsim_h
+#define m520xsim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m520x)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 520x SIM register set addresses.
+ */
+#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */
+#define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+/*
+ * The common interrupt controller code just wants to know the absolute
+ * address to the SIMR and CIMR registers (not offsets into IPSBAR).
+ * The 520x family only has a single INTC unit.
+ */
+#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
+#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
+#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
+#define MCFINTC1_SIMR (0)
+#define MCFINTC1_CIMR (0)
+#define MCFINTC1_ICR0 (0)
+#define MCFINTC2_SIMR (0)
+#define MCFINTC2_CIMR (0)
+#define MCFINTC2_ICR0 (0)
+
+#define MCFINT_VECBASE 64
+#define MCFINT_UART0 26 /* Interrupt number for UART0 */
+#define MCFINT_UART1 27 /* Interrupt number for UART1 */
+#define MCFINT_UART2 28 /* Interrupt number for UART2 */
+#define MCFINT_I2C0 30 /* Interrupt number for I2C */
+#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */
+#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */
+#define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */
+#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
+
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
+#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
+
+#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
+/*
+ * SDRAM configuration registers.
+ */
+#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
+#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
+#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
+#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
+#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
+#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
+
+/*
+ * EPORT and GPIO registers.
+ */
+#define MCFEPORT_EPPAR 0xFC088000
+#define MCFEPORT_EPDDR 0xFC088002
+#define MCFEPORT_EPIER 0xFC088003
+#define MCFEPORT_EPDR 0xFC088004
+#define MCFEPORT_EPPDR 0xFC088005
+#define MCFEPORT_EPFR 0xFC088006
+
+#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
+#define MCFGPIO_PODR_BE 0xFC0A4001
+#define MCFGPIO_PODR_CS 0xFC0A4002
+#define MCFGPIO_PODR_FECI2C 0xFC0A4003
+#define MCFGPIO_PODR_QSPI 0xFC0A4004
+#define MCFGPIO_PODR_TIMER 0xFC0A4005
+#define MCFGPIO_PODR_UART 0xFC0A4006
+#define MCFGPIO_PODR_FECH 0xFC0A4007
+#define MCFGPIO_PODR_FECL 0xFC0A4008
+
+#define MCFGPIO_PDDR_BUSCTL 0xFC0A400C
+#define MCFGPIO_PDDR_BE 0xFC0A400D
+#define MCFGPIO_PDDR_CS 0xFC0A400E
+#define MCFGPIO_PDDR_FECI2C 0xFC0A400F
+#define MCFGPIO_PDDR_QSPI 0xFC0A4010
+#define MCFGPIO_PDDR_TIMER 0xFC0A4011
+#define MCFGPIO_PDDR_UART 0xFC0A4012
+#define MCFGPIO_PDDR_FECH 0xFC0A4013
+#define MCFGPIO_PDDR_FECL 0xFC0A4014
+
+#define MCFGPIO_PPDSDR_CS 0xFC0A401A
+#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B
+#define MCFGPIO_PPDSDR_QSPI 0xFC0A401C
+#define MCFGPIO_PPDSDR_TIMER 0xFC0A401D
+#define MCFGPIO_PPDSDR_UART 0xFC0A401E
+#define MCFGPIO_PPDSDR_FECH 0xFC0A401F
+#define MCFGPIO_PPDSDR_FECL 0xFC0A4020
+
+#define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024
+#define MCFGPIO_PCLRR_BE 0xFC0A4025
+#define MCFGPIO_PCLRR_CS 0xFC0A4026
+#define MCFGPIO_PCLRR_FECI2C 0xFC0A4027
+#define MCFGPIO_PCLRR_QSPI 0xFC0A4028
+#define MCFGPIO_PCLRR_TIMER 0xFC0A4029
+#define MCFGPIO_PCLRR_UART 0xFC0A402A
+#define MCFGPIO_PCLRR_FECH 0xFC0A402B
+#define MCFGPIO_PCLRR_FECL 0xFC0A402C
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_CS
+#define MCFGPIO_PDDR MCFGPIO_PDDR_CS
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_CS
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_CS
+
+#define MCFGPIO_PIN_MAX 80
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+#define MCF_GPIO_PAR_UART 0xFC0A4036
+#define MCF_GPIO_PAR_FECI2C 0xFC0A4033
+#define MCF_GPIO_PAR_QSPI 0xFC0A4034
+#define MCF_GPIO_PAR_FEC 0xFC0A4038
+
+#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
+#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
+
+#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
+
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
+
+/*
+ * PIT timer module.
+ */
+#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
+#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */
+#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */
+#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */
+
+/*
+ * FEC module.
+ */
+#define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */
+#define MCFFEC_SIZE0 0x800 /* Register set size */
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */
+#define MCFQSPI_SIZE 0x40 /* Register set size */
+
+#define MCFQSPI_CS0 46
+#define MCFQSPI_CS1 47
+#define MCFQSPI_CS2 27
+
+/*
+ * Reset Control Unit.
+ */
+#define MCF_RCR 0xFC0A0000
+#define MCF_RSR 0xFC0A0001
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+/*
+ * Power Management.
+ */
+#define MCFPM_WCR 0xfc040013
+#define MCFPM_PPMSR0 0xfc04002c
+#define MCFPM_PPMCR0 0xfc04002d
+#define MCFPM_PPMHR0 0xfc040030
+#define MCFPM_PPMLR0 0xfc040034
+#define MCFPM_LPCR 0xfc0a0007
+
+/*
+ * I2C module.
+ */
+#define MCFI2C_BASE0 0xFC058000
+#define MCFI2C_SIZE0 0x40
+
+/****************************************************************************/
+#endif /* m520xsim_h */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
new file mode 100644
index 0000000..a308241
--- /dev/null
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m523xsim.h -- ColdFire 523x System Integration Module support.
+ *
+ * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
+ */
+
+/****************************************************************************/
+#ifndef m523xsim_h
+#define m523xsim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m523x)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 523x SIM register set addresses.
+ */
+#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
+
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+#define MCFINT_VECBASE 64 /* Vector base number */
+#define MCFINT_UART0 13 /* Interrupt number for UART0 */
+#define MCFINT_UART1 14 /* Interrupt number for UART1 */
+#define MCFINT_UART2 15 /* Interrupt number for UART2 */
+#define MCFINT_I2C0 17 /* Interrupt number for I2C */
+#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
+#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
+#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
+#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
+
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
+#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
+#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
+
+/*
+ * SDRAM configuration registers.
+ */
+#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
+#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
+#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
+
+/*
+ * Reset Control Unit (relative to IPSBAR).
+ */
+#define MCF_RCR (MCF_IPSBAR + 0x110000)
+#define MCF_RSR (MCF_IPSBAR + 0x110001)
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
+
+/*
+ * FEC ethernet module.
+ */
+#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
+#define MCFFEC_SIZE0 0x800
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE 0x40
+
+#define MCFQSPI_CS0 91
+#define MCFQSPI_CS1 92
+#define MCFQSPI_CS2 103
+#define MCFQSPI_CS3 99
+
+/*
+ * GPIO module.
+ */
+#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
+#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
+#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
+#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
+#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
+#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
+#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
+#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
+#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
+#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
+#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
+#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
+#define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
+
+#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
+#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
+#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
+#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
+#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
+#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
+#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
+#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
+#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
+#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
+#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
+#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
+#define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
+
+#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
+#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
+#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
+#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
+#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
+#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
+#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
+#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
+#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
+#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
+#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
+#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
+#define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
+
+#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
+#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
+#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
+#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
+#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
+#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
+#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
+#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
+#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
+#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
+#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
+#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
+#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
+
+/*
+ * PIT timer base addresses.
+ */
+#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
+#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
+#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
+#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
+
+/*
+ * EPort
+ */
+#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
+#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
+#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
+#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
+#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
+
+#define MCFGPIO_PIN_MAX 107
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+/*
+ * Pin Assignment
+*/
+#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
+#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
+#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
+#define MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E)
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
+#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
+#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
+#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
+
+/*
+ * I2C module.
+ */
+#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
+#define MCFI2C_SIZE0 0x40
+
+/****************************************************************************/
+#endif /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
new file mode 100644
index 0000000..de01b70
--- /dev/null
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -0,0 +1,309 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m525xsim.h -- ColdFire 525x System Integration Module support.
+ *
+ * (C) Copyright 2012, Steven king <sfking@fdwdc.com>
+ * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/****************************************************************************/
+#ifndef m525xsim_h
+#define m525xsim_h
+/****************************************************************************/
+
+/*
+ * This header supports ColdFire 5249, 5251 and 5253. There are a few
+ * little differences between them, but most of the peripheral support
+ * can be used by all of them.
+ */
+#define CPU_NAME "COLDFIRE(m525x)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m52xxacr.h>
+
+/*
+ * The 525x has a second MBAR region, define its address.
+ */
+#define MCF_MBAR2 0x80000000
+
+/*
+ * Define the 525x SIM register set addresses.
+ */
+#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
+#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
+#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
+#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
+#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
+#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
+#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
+#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
+#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
+#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
+#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
+#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
+#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
+#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
+#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
+#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
+#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
+#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
+#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
+#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
+#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
+#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
+
+#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
+#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
+#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
+
+/*
+ * Secondary Interrupt Controller (in MBAR2)
+*/
+#define MCFINTC2_INTBASE (MCF_MBAR2 + 0x168) /* Base Vector Reg */
+#define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
+#define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
+#define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
+#define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
+#define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
+#define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
+#define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
+#define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
+
+#define MCFINTC2_INTPRI_REG(i) (MCFINTC2_INTPRI1 + \
+ ((((i) - MCFINTC2_VECBASE) / 8) * 4))
+#define MCFINTC2_INTPRI_BITS(b, i) ((b) << (((i) % 8) * 4))
+
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE (MCF_MBAR + 0x400) /* Base address QSPI */
+#define MCFQSPI_SIZE 0x40 /* Register set size */
+
+#ifdef CONFIG_M5249
+#define MCFQSPI_CS0 29
+#define MCFQSPI_CS1 24
+#define MCFQSPI_CS2 21
+#define MCFQSPI_CS3 22
+#else
+#define MCFQSPI_CS0 15
+#define MCFQSPI_CS1 16
+#define MCFQSPI_CS2 24
+#define MCFQSPI_CS3 28
+#endif
+
+/*
+ * I2C module.
+ */
+#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base address I2C0 */
+#define MCFI2C_SIZE0 0x20 /* Register set size */
+
+#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base address I2C1 */
+#define MCFI2C_SIZE1 0x20 /* Register set size */
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
+#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
+#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
+
+/*
+ * Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
+#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
+#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
+#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
+#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
+#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
+#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
+#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
+#define MCF_IRQ_I2C0 29
+#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
+#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+
+#define MCF_IRQ_UART0 73 /* UART0 */
+#define MCF_IRQ_UART1 74 /* UART1 */
+
+/*
+ * Define the base interrupt for the second interrupt controller.
+ * We set it to 128, out of the way of the base interrupts, and plenty
+ * of room for its 64 interrupts.
+ */
+#define MCFINTC2_VECBASE 128
+
+#define MCF_IRQ_GPIO0 (MCFINTC2_VECBASE + 32)
+#define MCF_IRQ_GPIO1 (MCFINTC2_VECBASE + 33)
+#define MCF_IRQ_GPIO2 (MCFINTC2_VECBASE + 34)
+#define MCF_IRQ_GPIO3 (MCFINTC2_VECBASE + 35)
+#define MCF_IRQ_GPIO4 (MCFINTC2_VECBASE + 36)
+#define MCF_IRQ_GPIO5 (MCFINTC2_VECBASE + 37)
+#define MCF_IRQ_GPIO6 (MCFINTC2_VECBASE + 38)
+#define MCF_IRQ_GPIO7 (MCFINTC2_VECBASE + 39)
+
+#define MCF_IRQ_USBWUP (MCFINTC2_VECBASE + 40)
+#define MCF_IRQ_I2C1 (MCFINTC2_VECBASE + 62)
+
+/*
+ * General purpose IO registers (in MBAR2).
+ */
+#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
+#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
+#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
+#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
+#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
+#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
+#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
+#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
+
+#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
+#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
+#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
+
+#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
+#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
+#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX 64
+#ifdef CONFIG_M5249
+#define MCFGPIO_IRQ_MAX -1
+#define MCFGPIO_IRQ_VECBASE -1
+#else
+#define MCFGPIO_IRQ_MAX 7
+#define MCFGPIO_IRQ_VECBASE MCF_IRQ_GPIO0
+#endif
+
+/****************************************************************************/
+
+#ifdef __ASSEMBLER__
+#ifdef CONFIG_M5249C3
+/*
+ * The M5249C3 board needs a little help getting all its SIM devices
+ * initialized at kernel start time. dBUG doesn't set much up, so
+ * we need to do it manually.
+ */
+.macro m5249c3_setup
+ /*
+ * Set MBAR1 and MBAR2, just incase they are not set.
+ */
+ movel #0x10000001,%a0
+ movec %a0,%MBAR /* map MBAR region */
+ subql #1,%a0 /* get MBAR address in a0 */
+
+ movel #0x80000001,%a1
+ movec %a1,#3086 /* map MBAR2 region */
+ subql #1,%a1 /* get MBAR2 address in a1 */
+
+ /*
+ * Move secondary interrupts to their base (128).
+ */
+ moveb #MCFINTC2_VECBASE,%d0
+ moveb %d0,0x16b(%a1) /* interrupt base register */
+
+ /*
+ * Work around broken CSMR0/DRAM vector problem.
+ */
+ movel #0x001F0021,%d0 /* disable C/I bit */
+ movel %d0,0x84(%a0) /* set CSMR0 */
+
+ /*
+ * Disable the PLL firstly. (Who knows what state it is
+ * in here!).
+ */
+ movel 0x180(%a1),%d0 /* get current PLL value */
+ andl #0xfffffffe,%d0 /* PLL bypass first */
+ movel %d0,0x180(%a1) /* set PLL register */
+ nop
+
+#if CONFIG_CLOCK_FREQ == 140000000
+ /*
+ * Set initial clock frequency. This assumes M5249C3 board
+ * is fitted with 11.2896MHz crystal. It will program the
+ * PLL for 140MHz. Lets go fast :-)
+ */
+ movel #0x125a40f0,%d0 /* set for 140MHz */
+ movel %d0,0x180(%a1) /* set PLL register */
+ orl #0x1,%d0
+ movel %d0,0x180(%a1) /* set PLL register */
+#endif
+
+ /*
+ * Setup CS1 for ethernet controller.
+ * (Setup as per M5249C3 doco).
+ */
+ movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
+ movel %d0,0x8c(%a0)
+ movel #0x001f0021,%d0 /* CS1 size of 1Mb */
+ movel %d0,0x90(%a0)
+ movew #0x0080,%d0 /* CS1 = 16bit port, AA */
+ movew %d0,0x96(%a0)
+
+ /*
+ * Setup CS2 for IDE interface.
+ */
+ movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
+ movel %d0,0x98(%a0)
+ movel #0x001f0001,%d0 /* CS2 size of 1MB */
+ movel %d0,0x9c(%a0)
+ movew #0x0080,%d0 /* CS2 = 16bit, TA */
+ movew %d0,0xa2(%a0)
+
+ movel #0x00107000,%d0 /* IDEconfig1 */
+ movel %d0,0x18c(%a1)
+ movel #0x000c0400,%d0 /* IDEconfig2 */
+ movel %d0,0x190(%a1)
+
+ movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
+ orl %d0,0xc(%a1) /* function GPIO19 */
+ orl %d0,0x8(%a1) /* enable GPIO19 as output */
+ orl %d0,0x4(%a1) /* de-assert IDE reset */
+.endm
+
+#define PLATFORM_SETUP m5249c3_setup
+
+#endif /* CONFIG_M5249C3 */
+#endif /* __ASSEMBLER__ */
+/****************************************************************************/
+#endif /* m525xsim_h */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
new file mode 100644
index 0000000..135dd50
--- /dev/null
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m5272sim.h -- ColdFire 5272 System Integration Module support.
+ *
+ * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ */
+
+/****************************************************************************/
+#ifndef m5272sim_h
+#define m5272sim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m5272)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK MCF_CLK
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 5272 SIM register set addresses.
+ */
+#define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */
+#define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */
+#define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */
+#define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */
+#define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */
+
+#define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */
+
+#define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */
+#define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */
+#define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */
+#define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */
+
+#define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */
+#define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */
+#define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */
+#define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */
+
+#define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */
+#define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */
+#define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */
+#define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */
+#define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */
+#define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */
+#define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */
+#define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */
+#define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */
+#define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */
+#define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */
+#define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */
+#define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */
+#define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */
+#define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */
+#define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */
+
+#define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */
+#define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */
+#define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */
+#define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */
+#define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
+#define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
+#define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
+#define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
+
+#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
+
+#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
+#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
+#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
+#define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
+#define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
+#define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */
+#define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */
+#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
+#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
+
+#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
+
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
+#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
+#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
+
+#define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
+#define MCFFEC_SIZE0 0x1d0
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCFINT_VECBASE 64 /* Base of interrupts */
+#define MCF_IRQ_SPURIOUS 64 /* User Spurious */
+#define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
+#define MCF_IRQ_EINT2 66 /* External Interrupt 2 */
+#define MCF_IRQ_EINT3 67 /* External Interrupt 3 */
+#define MCF_IRQ_EINT4 68 /* External Interrupt 4 */
+#define MCF_IRQ_TIMER1 69 /* Timer 1 */
+#define MCF_IRQ_TIMER2 70 /* Timer 2 */
+#define MCF_IRQ_TIMER3 71 /* Timer 3 */
+#define MCF_IRQ_TIMER4 72 /* Timer 4 */
+#define MCF_IRQ_UART0 73 /* UART 0 */
+#define MCF_IRQ_UART1 74 /* UART 1 */
+#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
+#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
+#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
+#define MCF_IRQ_USB1 78 /* USB Endpoint 1 */
+#define MCF_IRQ_USB2 79 /* USB Endpoint 2 */
+#define MCF_IRQ_USB3 80 /* USB Endpoint 3 */
+#define MCF_IRQ_USB4 81 /* USB Endpoint 4 */
+#define MCF_IRQ_USB5 82 /* USB Endpoint 5 */
+#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
+#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
+#define MCF_IRQ_DMA 85 /* DMA Controller */
+#define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */
+#define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */
+#define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */
+#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
+#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
+#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
+#define MCF_IRQ_SWTO 92 /* Software Watchdog */
+#define MCFINT_VECMAX 95 /* Maxmum interrupt */
+
+#define MCF_IRQ_TIMER MCF_IRQ_TIMER1
+#define MCF_IRQ_PROFILER MCF_IRQ_TIMER2
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX 48
+#define MCFGPIO_IRQ_MAX -1
+#define MCFGPIO_IRQ_VECBASE -1
+
+/****************************************************************************/
+#endif /* m5272sim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
new file mode 100644
index 0000000..d92814b
--- /dev/null
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -0,0 +1,366 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
+ *
+ * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/****************************************************************************/
+#ifndef m527xsim_h
+#define m527xsim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m527x)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 5270/5271 SIM register set addresses.
+ */
+#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
+
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+#define MCFINT_VECBASE 64 /* Vector base number */
+#define MCFINT_UART0 13 /* Interrupt number for UART0 */
+#define MCFINT_UART1 14 /* Interrupt number for UART1 */
+#define MCFINT_UART2 15 /* Interrupt number for UART2 */
+#define MCFINT_I2C0 17 /* Interrupt number for I2C */
+#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
+#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
+#define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */
+#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
+
+#define MCFINT2_VECBASE 128 /* Vector base number 2 */
+#define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */
+#define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */
+#define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */
+
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+#define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1)
+#define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1)
+#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1)
+
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
+#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
+#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
+
+/*
+ * SDRAM configuration registers.
+ */
+#ifdef CONFIG_M5271
+#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */
+#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
+#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
+#endif
+#ifdef CONFIG_M5275
+#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */
+#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
+#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */
+#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */
+#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */
+#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */
+#endif
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_IPSBAR + 0x100)
+#define MCFDMA_BASE1 (MCF_IPSBAR + 0x140)
+#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
+#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE0 (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x280)
+
+/*
+ * FEC ethernet module.
+ */
+#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
+#define MCFFEC_SIZE0 0x800
+#ifdef CONFIG_M5275
+#define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800)
+#define MCFFEC_SIZE1 0x800
+#endif
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE 0x40
+
+#ifdef CONFIG_M5271
+#define MCFQSPI_CS0 91
+#define MCFQSPI_CS1 92
+#define MCFQSPI_CS2 99
+#define MCFQSPI_CS3 103
+#endif
+#ifdef CONFIG_M5275
+#define MCFQSPI_CS0 59
+#define MCFQSPI_CS1 60
+#define MCFQSPI_CS2 61
+#define MCFQSPI_CS3 62
+#endif
+
+/*
+ * GPIO module.
+ */
+#ifdef CONFIG_M5271
+#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
+#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
+#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
+#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
+#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
+#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
+#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
+#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
+#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
+#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
+#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
+#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
+
+#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
+#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
+#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
+#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
+#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
+#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
+#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
+#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
+#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
+#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
+#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
+#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
+
+#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
+#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
+#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
+#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
+#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
+#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
+#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
+#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
+#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
+#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
+#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
+#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
+
+#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
+#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
+#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
+#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
+#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
+#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
+#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
+#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
+#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
+#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
+#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
+#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
+#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
+
+#define MCFGPIO_PIN_MAX 100
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
+#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
+#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
+
+#define UART0_ENABLE_MASK 0x000f
+#define UART1_ENABLE_MASK 0x0ff0
+#define UART2_ENABLE_MASK 0x3000
+#endif /* CONFIG_M5271 */
+
+#ifdef CONFIG_M5275
+#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004)
+#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005)
+#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008)
+#define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A)
+#define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B)
+#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C)
+#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D)
+#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E)
+#define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F)
+#define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010)
+#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011)
+#define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012)
+#define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013)
+#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014)
+#define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015)
+#define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016)
+#define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017)
+#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018)
+
+#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020)
+#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021)
+#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024)
+#define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026)
+#define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027)
+#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028)
+#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029)
+#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A)
+#define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B)
+#define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C)
+#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D)
+#define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E)
+#define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F)
+#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030)
+#define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031)
+#define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032)
+#define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033)
+#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034)
+
+#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C)
+#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D)
+#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040)
+#define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042)
+#define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043)
+#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044)
+#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045)
+#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046)
+#define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047)
+#define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048)
+#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049)
+#define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A)
+#define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B)
+#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C)
+#define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D)
+#define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E)
+#define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F)
+#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050)
+
+#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058)
+#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059)
+#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C)
+#define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E)
+#define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F)
+#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060)
+#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061)
+#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062)
+#define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063)
+#define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064)
+#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065)
+#define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066)
+#define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067)
+#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068)
+#define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069)
+#define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A)
+#define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B)
+#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C)
+
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
+#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
+
+#define MCFGPIO_PIN_MAX 148
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+/*
+ * Port Pin Assignment registers.
+ */
+#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070)
+#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071)
+#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072)
+#define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076)
+#define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078)
+#define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079)
+#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A)
+#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C)
+#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
+#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080)
+#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082)
+#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084)
+
+#define UART0_ENABLE_MASK 0x000f
+#define UART1_ENABLE_MASK 0x00f0
+#define UART2_ENABLE_MASK 0x3f00
+#endif /* CONFIG_M5275 */
+
+/*
+ * PIT timer base addresses.
+ */
+#define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000)
+#define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000)
+#define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000)
+#define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000)
+
+/*
+ * EPort
+ */
+#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000)
+#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003)
+#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
+#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
+#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
+
+/*
+ * Reset Control Unit (relative to IPSBAR).
+ */
+#define MCF_RCR (MCF_IPSBAR + 0x110000)
+#define MCF_RSR (MCF_IPSBAR + 0x110001)
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+/*
+ * I2C module.
+ */
+#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
+#define MCFI2C_SIZE0 0x40
+
+/****************************************************************************/
+#endif /* m527xsim_h */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
new file mode 100644
index 0000000..7b60a57
--- /dev/null
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -0,0 +1,256 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
+ *
+ * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/****************************************************************************/
+#ifndef m528xsim_h
+#define m528xsim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m528x)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK MCF_CLK
+
+#include <asm/m52xxacr.h>
+
+/*
+ * Define the 5280/5282 SIM register set addresses.
+ */
+#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
+
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+#define MCFINT_VECBASE 64 /* Vector base number */
+#define MCFINT_UART0 13 /* Interrupt number for UART0 */
+#define MCFINT_UART1 14 /* Interrupt number for UART1 */
+#define MCFINT_UART2 15 /* Interrupt number for UART2 */
+#define MCFINT_I2C0 17 /* Interrupt number for I2C */
+#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
+#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
+#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
+#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
+
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
+#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
+#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
+
+/*
+ * SDRAM configuration registers.
+ */
+#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
+#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
+#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
+#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
+#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
+#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
+#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
+#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200)
+#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240)
+#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280)
+
+/*
+ * FEC ethernet module.
+ */
+#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000)
+#define MCFFEC_SIZE0 0x800
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE 0x40
+
+#define MCFQSPI_CS0 147
+#define MCFQSPI_CS1 148
+#define MCFQSPI_CS2 149
+#define MCFQSPI_CS3 150
+
+/*
+ * GPIO registers
+ */
+#define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000)
+#define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001)
+#define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002)
+#define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003)
+#define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004)
+#define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005)
+#define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006)
+#define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007)
+#define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008)
+#define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009)
+#define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A)
+#define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B)
+#define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C)
+#define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D)
+#define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E)
+#define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F)
+#define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010)
+#define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011)
+
+#define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014)
+#define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015)
+#define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016)
+#define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017)
+#define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018)
+#define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019)
+#define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A)
+#define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B)
+#define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C)
+#define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D)
+#define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E)
+#define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F)
+#define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020)
+#define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021)
+#define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022)
+#define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023)
+#define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024)
+#define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025)
+
+#define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028)
+#define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029)
+#define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A)
+#define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B)
+#define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C)
+#define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D)
+#define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E)
+#define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F)
+#define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030)
+#define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031)
+#define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032)
+#define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033)
+#define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034)
+#define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035)
+#define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036)
+#define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037)
+#define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038)
+#define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039)
+
+#define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C)
+#define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D)
+#define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E)
+#define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F)
+#define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040)
+#define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041)
+#define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042)
+#define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043)
+#define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044)
+#define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045)
+#define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046)
+#define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047)
+#define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048)
+#define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049)
+#define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A)
+#define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B)
+#define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C)
+#define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D)
+
+#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050)
+#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051)
+#define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052)
+#define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054)
+#define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055)
+#define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056)
+#define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058)
+#define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059)
+#define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A)
+#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
+#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
+
+/*
+ * PIT timer base addresses.
+ */
+#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
+#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
+#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
+#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
+
+/*
+ * Edge Port registers
+ */
+#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
+#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002)
+#define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003)
+#define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004)
+#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005)
+#define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006)
+
+/*
+ * Queued ADC registers
+ */
+#define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006)
+#define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007)
+#define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008)
+#define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009)
+
+/*
+ * General Purpose Timers registers
+ */
+#define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D)
+#define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E)
+#define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D)
+#define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E)
+/*
+ *
+ * definitions for generic gpio support
+ *
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */
+#define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */
+
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+#define MCFGPIO_PIN_MAX 180
+
+/*
+ * Reset Control Unit (relative to IPSBAR).
+ */
+#define MCF_RCR (MCF_IPSBAR + 0x110000)
+#define MCF_RSR (MCF_IPSBAR + 0x110001)
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+/*
+ * I2C module
+ */
+#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
+#define MCFI2C_SIZE0 0x40
+
+/****************************************************************************/
+#endif /* m528xsim_h */
diff --git a/arch/m68k/include/asm/m52xxacr.h b/arch/m68k/include/asm/m52xxacr.h
new file mode 100644
index 0000000..2cb29ed
--- /dev/null
+++ b/arch/m68k/include/asm/m52xxacr.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m52xxacr.h -- ColdFire version 2 core cache support
+ *
+ * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
+ */
+
+/****************************************************************************/
+#ifndef m52xxacr_h
+#define m52xxacr_h
+/****************************************************************************/
+
+/*
+ * All varients of the ColdFire using version 2 cores have a similar
+ * cache setup. Although not absolutely identical the cache register
+ * definitions are compatible for all of them. Mostly they support a
+ * configurable cache memory that can be instruction only, data only,
+ * or split instruction and data. The exception is the very old version 2
+ * core based parts, like the 5206(e), 5249 and 5272, which are instruction
+ * cache only. Cache size varies from 2k up to 16k.
+ */
+
+/*
+ * Define the Cache Control register flags.
+ */
+#define CACR_CENB 0x80000000 /* Enable cache */
+#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */
+#define CACR_CFRZ 0x08000000 /* Cache freeze mode */
+#define CACR_CINV 0x01000000 /* Invalidate cache */
+#define CACR_DISI 0x00800000 /* Disable instruction cache */
+#define CACR_DISD 0x00400000 /* Disable data cache */
+#define CACR_INVI 0x00200000 /* Invalidate instruction cache */
+#define CACR_INVD 0x00100000 /* Invalidate data cache */
+#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */
+#define CACR_DCM 0x00000200 /* Default cache mode */
+#define CACR_DBWE 0x00000100 /* Buffered write enable */
+#define CACR_DWP 0x00000020 /* Write protection */
+#define CACR_EUSP 0x00000010 /* Enable separate user a7 */
+
+/*
+ * Define the Access Control register flags.
+ */
+#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
+#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
+#define ACR_ENABLE 0x00008000 /* Enable this ACR */
+#define ACR_USER 0x00000000 /* Allow only user accesses */
+#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
+#define ACR_ANY 0x00004000 /* Allow any access type */
+#define ACR_CENB 0x00000000 /* Caching of region enabled */
+#define ACR_CDIS 0x00000040 /* Caching of region disabled */
+#define ACR_BWE 0x00000020 /* Write buffer enabled */
+#define ACR_WPROTECT 0x00000004 /* Write protect region */
+
+/*
+ * Set the cache controller settings we will use. On the cores that support
+ * a split cache configuration we allow all the combinations at Kconfig
+ * time. For those cores that only have an instruction cache we just set
+ * that as on.
+ */
+#if defined(CONFIG_CACHE_I)
+#define CACHE_TYPE (CACR_DISD + CACR_EUSP)
+#define CACHE_INVTYPEI 0
+#elif defined(CONFIG_CACHE_D)
+#define CACHE_TYPE (CACR_DISI + CACR_EUSP)
+#define CACHE_INVTYPED 0
+#elif defined(CONFIG_CACHE_BOTH)
+#define CACHE_TYPE CACR_EUSP
+#define CACHE_INVTYPEI CACR_INVI
+#define CACHE_INVTYPED CACR_INVD
+#else
+/* This is the instruction cache only devices (no split cache, no eusp) */
+#define CACHE_TYPE 0
+#define CACHE_INVTYPEI 0
+#endif
+
+#define CACHE_INIT (CACR_CINV + CACHE_TYPE)
+#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM)
+
+#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
+#if defined(CACHE_INVTYPEI)
+#define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)
+#endif
+#if defined(CACHE_INVTYPED)
+#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED)
+#endif
+
+#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
+ (0x000f0000) + \
+ (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
+#define ACR1_MODE 0
+
+/****************************************************************************/
+#endif /* m52xxsim_h */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
new file mode 100644
index 0000000..25059f2
--- /dev/null
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m5307sim.h -- ColdFire 5307 System Integration Module support.
+ *
+ * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
+ * (C) Copyright 1999, Lineo (www.lineo.com)
+ *
+ * Modified by David W. Miller for the MCF5307 Eval Board.
+ */
+
+/****************************************************************************/
+#ifndef m5307sim_h
+#define m5307sim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m5307)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m53xxacr.h>
+
+/*
+ * Define the 5307 SIM register set addresses.
+ */
+#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
+#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
+#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
+#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
+#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
+#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
+#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
+#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
+#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
+#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
+#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
+#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
+#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
+#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
+#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
+#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
+#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
+
+#ifdef CONFIG_OLDMASK
+#define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
+#define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */
+#define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */
+#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
+#define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */
+#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
+#define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */
+#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
+#define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */
+#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
+#define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */
+#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
+#define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */
+#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
+#else
+#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
+#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
+#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
+#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
+#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
+#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
+#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
+#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
+#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
+#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
+#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
+#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
+#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
+#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
+#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
+#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
+#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
+#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
+#endif /* CONFIG_OLDMASK */
+
+#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
+#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */
+#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */
+
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
+
+#define MCFSIM_PADDR (MCF_MBAR + 0x244)
+#define MCFSIM_PADAT (MCF_MBAR + 0x248)
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
+#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
+#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
+
+/*
+ * UART module.
+ */
+#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
+#define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */
+#else
+#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
+#endif
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX 16
+#define MCFGPIO_IRQ_MAX -1
+#define MCFGPIO_IRQ_VECBASE -1
+
+
+/* Definition offset address for CS2-7 -- old mask 5307 */
+
+#define MCF5307_CS2 (0x400000)
+#define MCF5307_CS3 (0x600000)
+#define MCF5307_CS4 (0x800000)
+#define MCF5307_CS5 (0xA00000)
+#define MCF5307_CS6 (0xC00000)
+#define MCF5307_CS7 (0xE00000)
+
+
+/*
+ * Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
+#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
+#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
+#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
+#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
+#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
+#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
+
+/*
+ * Some symbol defines for the Parallel Port Pin Assignment Register
+ */
+#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
+ /* Clear to select par I/O */
+#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
+ /* Clear to select par I/O */
+
+/*
+ * Defines for the IRQPAR Register
+ */
+#define IRQ5_LEVEL4 0x80
+#define IRQ3_LEVEL6 0x40
+#define IRQ1_LEVEL2 0x20
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
+#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
+#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+#define MCF_IRQ_UART0 73 /* UART0 */
+#define MCF_IRQ_UART1 74 /* UART1 */
+
+/*
+ * I2C module
+ */
+#define MCFI2C_BASE0 (MCF_MBAR + 0x280)
+#define MCFI2C_SIZE0 0x40
+
+/****************************************************************************/
+#endif /* m5307sim_h */
diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
new file mode 100644
index 0000000..9138a62
--- /dev/null
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m53xxacr.h -- ColdFire version 3 core cache support
+ *
+ * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
+ */
+
+/****************************************************************************/
+#ifndef m53xxacr_h
+#define m53xxacr_h
+/****************************************************************************/
+
+/*
+ * All varients of the ColdFire using version 3 cores have a similar
+ * cache setup. They have a unified instruction and data cache, with
+ * configurable write-through or copy-back operation.
+ */
+
+/*
+ * Define the Cache Control register flags.
+ */
+#define CACR_EC 0x80000000 /* Enable cache */
+#define CACR_ESB 0x20000000 /* Enable store buffer */
+#define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */
+#define CACR_HLCK 0x08000000 /* Half cache lock mode */
+#define CACR_CINVA 0x01000000 /* Invalidate cache */
+#define CACR_DNFB 0x00000400 /* Inhibited fill buffer */
+#define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
+#define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
+#define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */
+#define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */
+#define CACR_WPROTECT 0x00000020 /* Write protect*/
+#define CACR_EUSP 0x00000010 /* Eanble separate user a7 */
+
+/*
+ * Define the Access Control register flags.
+ */
+#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
+#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
+#define ACR_ENABLE 0x00008000 /* Enable this ACR */
+#define ACR_USER 0x00000000 /* Allow only user accesses */
+#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
+#define ACR_ANY 0x00004000 /* Allow any access type */
+#define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
+#define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
+#define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */
+#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */
+#define ACR_WPROTECT 0x00000004 /* Write protect region */
+
+/*
+ * Define the cache type and arrangement (needed for pushes).
+ */
+#if defined(CONFIG_M5307)
+#define CACHE_SIZE 0x2000 /* 8k of unified cache */
+#define ICACHE_SIZE CACHE_SIZE
+#define DCACHE_SIZE CACHE_SIZE
+#elif defined(CONFIG_M53xx)
+#define CACHE_SIZE 0x4000 /* 16k of unified cache */
+#define ICACHE_SIZE CACHE_SIZE
+#define DCACHE_SIZE CACHE_SIZE
+#endif
+
+#define CACHE_LINE_SIZE 16 /* 16 byte line size */
+#define CACHE_WAYS 4 /* 4 ways - set associative */
+
+/*
+ * Set the cache controller settings we will use. This default in the
+ * CACR is cache inhibited, we use the ACR register to set cacheing
+ * enabled on the regions we want (eg RAM).
+ */
+#if defined(CONFIG_CACHE_COPYBACK)
+#define CACHE_TYPE ACR_CM_CB
+#define CACHE_PUSH
+#else
+#define CACHE_TYPE ACR_CM_WT
+#endif
+
+#ifdef CONFIG_COLDFIRE_SW_A7
+#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE)
+#else
+#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
+#endif
+
+/*
+ * Unified cache means we will never need to flush for coherency of
+ * instruction fetch. We will need to flush to maintain memory/DMA
+ * coherency though in all cases. And for copyback caches we will need
+ * to push cached data as well.
+ */
+#define CACHE_INIT CACR_CINVA
+#define CACHE_INVALIDATE CACR_CINVA
+#define CACHE_INVALIDATED CACR_CINVA
+
+#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
+ (0x000f0000) + \
+ (ACR_ENABLE + ACR_ANY + CACHE_TYPE))
+#define ACR1_MODE 0
+
+/****************************************************************************/
+#endif /* m53xxsim_h */
diff --git a/arch/m68k/include/asm/m53xxsim.h b/arch/m68k/include/asm/m53xxsim.h
new file mode 100644
index 0000000..22c1c92
--- /dev/null
+++ b/arch/m68k/include/asm/m53xxsim.h
@@ -0,0 +1,1250 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m53xxsim.h -- ColdFire 5329 registers
+ */
+
+/****************************************************************************/
+#ifndef m53xxsim_h
+#define m53xxsim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m53xx)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 3)
+
+#include <asm/m53xxacr.h>
+
+#define MCFINT_VECBASE 64
+#define MCFINT_UART0 26 /* Interrupt number for UART0 */
+#define MCFINT_UART1 27 /* Interrupt number for UART1 */
+#define MCFINT_UART2 28 /* Interrupt number for UART2 */
+#define MCFINT_I2C0 30 /* Interrupt number for I2C */
+#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
+#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
+#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
+#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
+
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
+
+#define MCF_WTM_WCR 0xFC098000
+
+/*
+ * Define the 532x SIM register set addresses.
+ */
+#define MCFSIM_IPRL 0xFC048004
+#define MCFSIM_IPRH 0xFC048000
+#define MCFSIM_IPR MCFSIM_IPRL
+#define MCFSIM_IMRL 0xFC04800C
+#define MCFSIM_IMRH 0xFC048008
+#define MCFSIM_IMR MCFSIM_IMRL
+#define MCFSIM_ICR0 0xFC048040
+#define MCFSIM_ICR1 0xFC048041
+#define MCFSIM_ICR2 0xFC048042
+#define MCFSIM_ICR3 0xFC048043
+#define MCFSIM_ICR4 0xFC048044
+#define MCFSIM_ICR5 0xFC048045
+#define MCFSIM_ICR6 0xFC048046
+#define MCFSIM_ICR7 0xFC048047
+#define MCFSIM_ICR8 0xFC048048
+#define MCFSIM_ICR9 0xFC048049
+#define MCFSIM_ICR10 0xFC04804A
+#define MCFSIM_ICR11 0xFC04804B
+
+/*
+ * Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
+#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
+#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
+#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
+#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
+#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
+
+
+#define MCFINTC0_SIMR 0xFC04801C
+#define MCFINTC0_CIMR 0xFC04801D
+#define MCFINTC0_ICR0 0xFC048040
+#define MCFINTC1_SIMR 0xFC04C01C
+#define MCFINTC1_CIMR 0xFC04C01D
+#define MCFINTC1_ICR0 0xFC04C040
+#define MCFINTC2_SIMR (0)
+#define MCFINTC2_CIMR (0)
+#define MCFINTC2_ICR0 (0)
+
+#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
+#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_TIMER (64 + 32) /* Timer0 */
+#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
+#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
+#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
+
+/*
+ * FEC module.
+ */
+#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
+#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
+
+/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE 0xFC05C000 /* Base address of QSPI */
+#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
+
+#define MCFQSPI_CS0 84
+#define MCFQSPI_CS1 85
+#define MCFQSPI_CS2 86
+
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
+#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
+#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
+#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
+
+/*********************************************************************
+ *
+ * Reset Controller Module
+ *
+ *********************************************************************/
+
+#define MCF_RCR 0xFC0A0000
+#define MCF_RSR 0xFC0A0001
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+
+/*
+ * Power Management
+ */
+#define MCFPM_WCR 0xfc040013
+#define MCFPM_PPMSR0 0xfc04002c
+#define MCFPM_PPMCR0 0xfc04002d
+#define MCFPM_PPMSR1 0xfc04002e
+#define MCFPM_PPMCR1 0xfc04002f
+#define MCFPM_PPMHR0 0xfc040030
+#define MCFPM_PPMLR0 0xfc040034
+#define MCFPM_PPMHR1 0xfc040038
+#define MCFPM_LPCR 0xec090007
+
+/*
+ * The M5329EVB board needs a help getting its devices initialized
+ * at kernel start time if dBUG doesn't set it up (for example
+ * it is not used), so we need to do it manually.
+ */
+#ifdef __ASSEMBLER__
+.macro m5329EVB_setup
+ movel #0xFC098000, %a7
+ movel #0x0, (%a7)
+#define CORE_SRAM 0x80000000
+#define CORE_SRAM_SIZE 0x8000
+ movel #CORE_SRAM, %d0
+ addl #0x221, %d0
+ movec %d0,%RAMBAR1
+ movel #CORE_SRAM, %sp
+ addl #CORE_SRAM_SIZE, %sp
+ jsr sysinit
+.endm
+#define PLATFORM_SETUP m5329EVB_setup
+
+#endif /* __ASSEMBLER__ */
+
+/*********************************************************************
+ *
+ * Chip Configuration Module (CCM)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CCM_CCR 0xFC0A0004
+#define MCF_CCM_RCON 0xFC0A0008
+#define MCF_CCM_CIR 0xFC0A000A
+#define MCF_CCM_MISCCR 0xFC0A0010
+#define MCF_CCM_CDR 0xFC0A0012
+#define MCF_CCM_UHCSR 0xFC0A0014
+#define MCF_CCM_UOCSR 0xFC0A0016
+
+/* Bit definitions and macros for MCF_CCM_CCR */
+#define MCF_CCM_CCR_RESERVED (0x0001)
+#define MCF_CCM_CCR_PLL_MODE (0x0003)
+#define MCF_CCM_CCR_OSC_MODE (0x0005)
+#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
+#define MCF_CCM_CCR_LOAD (0x0021)
+#define MCF_CCM_CCR_LIMP (0x0041)
+#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
+
+/* Bit definitions and macros for MCF_CCM_RCON */
+#define MCF_CCM_RCON_RESERVED (0x0001)
+#define MCF_CCM_RCON_PLL_MODE (0x0003)
+#define MCF_CCM_RCON_OSC_MODE (0x0005)
+#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
+#define MCF_CCM_RCON_LOAD (0x0021)
+#define MCF_CCM_RCON_LIMP (0x0041)
+#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
+
+/* Bit definitions and macros for MCF_CCM_CIR */
+#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
+#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
+
+/* Bit definitions and macros for MCF_CCM_MISCCR */
+#define MCF_CCM_MISCCR_USBSRC (0x0001)
+#define MCF_CCM_MISCCR_USBDIV (0x0002)
+#define MCF_CCM_MISCCR_SSI_SRC (0x0010)
+#define MCF_CCM_MISCCR_TIM_DMA (0x0020)
+#define MCF_CCM_MISCCR_SSI_PUS (0x0040)
+#define MCF_CCM_MISCCR_SSI_PUE (0x0080)
+#define MCF_CCM_MISCCR_LCD_CHEN (0x0100)
+#define MCF_CCM_MISCCR_LIMP (0x1000)
+#define MCF_CCM_MISCCR_PLL_LOCK (0x2000)
+
+/* Bit definitions and macros for MCF_CCM_CDR */
+#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0)
+#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
+
+/* Bit definitions and macros for MCF_CCM_UHCSR */
+#define MCF_CCM_UHCSR_XPDE (0x0001)
+#define MCF_CCM_UHCSR_UHMIE (0x0002)
+#define MCF_CCM_UHCSR_WKUP (0x0004)
+#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for MCF_CCM_UOCSR */
+#define MCF_CCM_UOCSR_XPDE (0x0001)
+#define MCF_CCM_UOCSR_UOMIE (0x0002)
+#define MCF_CCM_UOCSR_WKUP (0x0004)
+#define MCF_CCM_UOCSR_PWRFLT (0x0008)
+#define MCF_CCM_UOCSR_SEND (0x0010)
+#define MCF_CCM_UOCSR_VVLD (0x0020)
+#define MCF_CCM_UOCSR_BVLD (0x0040)
+#define MCF_CCM_UOCSR_AVLD (0x0080)
+#define MCF_CCM_UOCSR_DPPU (0x0100)
+#define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
+#define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
+#define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
+#define MCF_CCM_UOCSR_DMPD (0x1000)
+#define MCF_CCM_UOCSR_DPPD (0x2000)
+#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
+
+/*********************************************************************
+ *
+ * FlexBus Chip Selects (FBCS)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR 0xFC008000
+#define MCF_FBCS0_CSMR 0xFC008004
+#define MCF_FBCS0_CSCR 0xFC008008
+#define MCF_FBCS1_CSAR 0xFC00800C
+#define MCF_FBCS1_CSMR 0xFC008010
+#define MCF_FBCS1_CSCR 0xFC008014
+#define MCF_FBCS2_CSAR 0xFC008018
+#define MCF_FBCS2_CSMR 0xFC00801C
+#define MCF_FBCS2_CSCR 0xFC008020
+#define MCF_FBCS3_CSAR 0xFC008024
+#define MCF_FBCS3_CSMR 0xFC008028
+#define MCF_FBCS3_CSCR 0xFC00802C
+#define MCF_FBCS4_CSAR 0xFC008030
+#define MCF_FBCS4_CSMR 0xFC008034
+#define MCF_FBCS4_CSCR 0xFC008038
+#define MCF_FBCS5_CSAR 0xFC00803C
+#define MCF_FBCS5_CSMR 0xFC008040
+#define MCF_FBCS5_CSCR 0xFC008044
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V (0x00000001)
+#define MCF_FBCS_CSMR_WP (0x00000100)
+#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
+#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
+#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
+#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
+#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
+#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
+#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
+#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
+#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
+#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
+#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
+#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
+#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
+#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
+#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW (0x00000008)
+#define MCF_FBCS_CSCR_BSTR (0x00000010)
+#define MCF_FBCS_CSCR_BEM (0x00000020)
+#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
+#define MCF_FBCS_CSCR_AA (0x00000100)
+#define MCF_FBCS_CSCR_SBM (0x00000200)
+#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
+#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
+#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
+#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
+#define MCF_FBCS_CSCR_SWSEN (0x00800000)
+#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
+#define MCF_FBCS_CSCR_PS_8 (0x0040)
+#define MCF_FBCS_CSCR_PS_16 (0x0080)
+#define MCF_FBCS_CSCR_PS_32 (0x0000)
+
+/*********************************************************************
+ *
+ * General Purpose I/O (GPIO)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCFGPIO_PODR_FECH (0xFC0A4000)
+#define MCFGPIO_PODR_FECL (0xFC0A4001)
+#define MCFGPIO_PODR_SSI (0xFC0A4002)
+#define MCFGPIO_PODR_BUSCTL (0xFC0A4003)
+#define MCFGPIO_PODR_BE (0xFC0A4004)
+#define MCFGPIO_PODR_CS (0xFC0A4005)
+#define MCFGPIO_PODR_PWM (0xFC0A4006)
+#define MCFGPIO_PODR_FECI2C (0xFC0A4007)
+#define MCFGPIO_PODR_UART (0xFC0A4009)
+#define MCFGPIO_PODR_QSPI (0xFC0A400A)
+#define MCFGPIO_PODR_TIMER (0xFC0A400B)
+#define MCFGPIO_PODR_LCDDATAH (0xFC0A400D)
+#define MCFGPIO_PODR_LCDDATAM (0xFC0A400E)
+#define MCFGPIO_PODR_LCDDATAL (0xFC0A400F)
+#define MCFGPIO_PODR_LCDCTLH (0xFC0A4010)
+#define MCFGPIO_PODR_LCDCTLL (0xFC0A4011)
+#define MCFGPIO_PDDR_FECH (0xFC0A4014)
+#define MCFGPIO_PDDR_FECL (0xFC0A4015)
+#define MCFGPIO_PDDR_SSI (0xFC0A4016)
+#define MCFGPIO_PDDR_BUSCTL (0xFC0A4017)
+#define MCFGPIO_PDDR_BE (0xFC0A4018)
+#define MCFGPIO_PDDR_CS (0xFC0A4019)
+#define MCFGPIO_PDDR_PWM (0xFC0A401A)
+#define MCFGPIO_PDDR_FECI2C (0xFC0A401B)
+#define MCFGPIO_PDDR_UART (0xFC0A401C)
+#define MCFGPIO_PDDR_QSPI (0xFC0A401E)
+#define MCFGPIO_PDDR_TIMER (0xFC0A401F)
+#define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021)
+#define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022)
+#define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023)
+#define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024)
+#define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025)
+#define MCFGPIO_PPDSDR_FECH (0xFC0A4028)
+#define MCFGPIO_PPDSDR_FECL (0xFC0A4029)
+#define MCFGPIO_PPDSDR_SSI (0xFC0A402A)
+#define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B)
+#define MCFGPIO_PPDSDR_BE (0xFC0A402C)
+#define MCFGPIO_PPDSDR_CS (0xFC0A402D)
+#define MCFGPIO_PPDSDR_PWM (0xFC0A402E)
+#define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F)
+#define MCFGPIO_PPDSDR_UART (0xFC0A4031)
+#define MCFGPIO_PPDSDR_QSPI (0xFC0A4032)
+#define MCFGPIO_PPDSDR_TIMER (0xFC0A4033)
+#define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035)
+#define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036)
+#define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037)
+#define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038)
+#define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039)
+#define MCFGPIO_PCLRR_FECH (0xFC0A403C)
+#define MCFGPIO_PCLRR_FECL (0xFC0A403D)
+#define MCFGPIO_PCLRR_SSI (0xFC0A403E)
+#define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F)
+#define MCFGPIO_PCLRR_BE (0xFC0A4040)
+#define MCFGPIO_PCLRR_CS (0xFC0A4041)
+#define MCFGPIO_PCLRR_PWM (0xFC0A4042)
+#define MCFGPIO_PCLRR_FECI2C (0xFC0A4043)
+#define MCFGPIO_PCLRR_UART (0xFC0A4045)
+#define MCFGPIO_PCLRR_QSPI (0xFC0A4046)
+#define MCFGPIO_PCLRR_TIMER (0xFC0A4047)
+#define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049)
+#define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A)
+#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
+#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
+#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
+#define MCFGPIO_PAR_FEC (0xFC0A4050)
+#define MCFGPIO_PAR_PWM (0xFC0A4051)
+#define MCFGPIO_PAR_BUSCTL (0xFC0A4052)
+#define MCFGPIO_PAR_FECI2C (0xFC0A4053)
+#define MCFGPIO_PAR_BE (0xFC0A4054)
+#define MCFGPIO_PAR_CS (0xFC0A4055)
+#define MCFGPIO_PAR_SSI (0xFC0A4056)
+#define MCFGPIO_PAR_UART (0xFC0A4058)
+#define MCFGPIO_PAR_QSPI (0xFC0A405A)
+#define MCFGPIO_PAR_TIMER (0xFC0A405C)
+#define MCFGPIO_PAR_LCDDATA (0xFC0A405D)
+#define MCFGPIO_PAR_LCDCTL (0xFC0A405E)
+#define MCFGPIO_PAR_IRQ (0xFC0A4060)
+#define MCFGPIO_MSCR_FLEXBUS (0xFC0A4064)
+#define MCFGPIO_MSCR_SDRAM (0xFC0A4065)
+#define MCFGPIO_DSCR_I2C (0xFC0A4068)
+#define MCFGPIO_DSCR_PWM (0xFC0A4069)
+#define MCFGPIO_DSCR_FEC (0xFC0A406A)
+#define MCFGPIO_DSCR_UART (0xFC0A406B)
+#define MCFGPIO_DSCR_QSPI (0xFC0A406C)
+#define MCFGPIO_DSCR_TIMER (0xFC0A406D)
+#define MCFGPIO_DSCR_SSI (0xFC0A406E)
+#define MCFGPIO_DSCR_LCD (0xFC0A406F)
+#define MCFGPIO_DSCR_DEBUG (0xFC0A4070)
+#define MCFGPIO_DSCR_CLKRST (0xFC0A4071)
+#define MCFGPIO_DSCR_IRQ (0xFC0A4072)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
+#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
+#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02)
+#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04)
+#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08)
+#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10)
+#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20)
+#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40)
+#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECL */
+#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01)
+#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02)
+#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04)
+#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08)
+#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10)
+#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20)
+#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40)
+#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_SSI */
+#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01)
+#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02)
+#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04)
+#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08)
+#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
+#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
+#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_BE */
+#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01)
+#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02)
+#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04)
+#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_CS */
+#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
+#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
+#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
+#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
+#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PWM */
+#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04)
+#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08)
+#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10)
+#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_UART */
+#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01)
+#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02)
+#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04)
+#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08)
+#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10)
+#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20)
+#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40)
+#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
+#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
+#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
+#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01)
+#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40)
+#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40)
+#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
+#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40)
+#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40)
+#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40)
+#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
+#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01)
+#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02)
+#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04)
+#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08)
+#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
+#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
+#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_BE */
+#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01)
+#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02)
+#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04)
+#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
+#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
+#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
+#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
+#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
+#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
+#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04)
+#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08)
+#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10)
+#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_UART */
+#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01)
+#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02)
+#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04)
+#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08)
+#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10)
+#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20)
+#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40)
+#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
+#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
+#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
+#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01)
+#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40)
+#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40)
+#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
+#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40)
+#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40)
+#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40)
+#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
+#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01)
+#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02)
+#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04)
+#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08)
+#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
+#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
+#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
+#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01)
+#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02)
+#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04)
+#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
+#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
+#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04)
+#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08)
+#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10)
+#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40)
+#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
+#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
+#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
+#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01)
+#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40)
+#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40)
+#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
+#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40)
+#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40)
+#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40)
+#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
+#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01)
+#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02)
+#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04)
+#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08)
+#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
+#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
+#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
+#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01)
+#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02)
+#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04)
+#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
+#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
+#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04)
+#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08)
+#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10)
+#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40)
+#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
+#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
+#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
+#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01)
+#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40)
+#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40)
+#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
+#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40)
+#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_FEC */
+#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01)
+#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_PWM */
+#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10)
+#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3)
+#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40)
+#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80)
+#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00)
+#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40)
+#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00)
+#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10)
+#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20)
+#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
+#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
+#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_BE */
+#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01)
+#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02)
+#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04)
+#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_CS */
+#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
+#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
+#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
+#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
+#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
+#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00)
+#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01)
+#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_SSI */
+#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080)
+#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12)
+#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_UART */
+#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001)
+#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002)
+#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004)
+#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800)
+#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400)
+#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00)
+#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200)
+#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100)
+#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300)
+#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080)
+#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040)
+#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010)
+#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
+#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12)
+#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
+#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01)
+#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
+#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0)
+#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
+#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001)
+#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002)
+#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004)
+#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008)
+#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010)
+#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020)
+#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040)
+#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080)
+#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100)
+
+/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
+#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4)
+#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6)
+#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8)
+#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10)
+#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12)
+
+/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
+#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0)
+#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2)
+#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4)
+
+/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
+#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0)
+#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2)
+#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
+#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
+#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
+#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
+#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0)
+#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
+#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
+#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
+#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
+#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
+#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
+#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0)
+
+/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
+#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR MCFGPIO_PODR_FECH
+#define MCFGPIO_PDDR MCFGPIO_PDDR_FECH
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH
+
+#define MCFGPIO_PIN_MAX 136
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+/*********************************************************************
+ *
+ * Phase Locked Loop (PLL)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PLL_PODR 0xFC0C0000
+#define MCF_PLL_PLLCR 0xFC0C0004
+#define MCF_PLL_PMDR 0xFC0C0008
+#define MCF_PLL_PFDR 0xFC0C000C
+
+/* Bit definitions and macros for MCF_PLL_PODR */
+#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
+#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
+
+/* Bit definitions and macros for MCF_PLL_PLLCR */
+#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0)
+#define MCF_PLL_PLLCR_DITHEN (0x80)
+
+/* Bit definitions and macros for MCF_PLL_PMDR */
+#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PLL_PFDR */
+#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0)
+
+/*********************************************************************
+ *
+ * System Control Module Registers (SCM)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SCM_MPR 0xFC000000
+#define MCF_SCM_PACRA 0xFC000020
+#define MCF_SCM_PACRB 0xFC000024
+#define MCF_SCM_PACRC 0xFC000028
+#define MCF_SCM_PACRD 0xFC00002C
+#define MCF_SCM_PACRE 0xFC000040
+#define MCF_SCM_PACRF 0xFC000044
+
+#define MCF_SCM_BCR 0xFC040024
+
+/*********************************************************************
+ *
+ * SDRAM Controller (SDRAMC)
+ *
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDMR 0xFC0B8000
+#define MCF_SDRAMC_SDCR 0xFC0B8004
+#define MCF_SDRAMC_SDCFG1 0xFC0B8008
+#define MCF_SDRAMC_SDCFG2 0xFC0B800C
+#define MCF_SDRAMC_LIMP_FIX 0xFC0B8080
+#define MCF_SDRAMC_SDDS 0xFC0B8100
+#define MCF_SDRAMC_SDCS0 0xFC0B8110
+#define MCF_SDRAMC_SDCS1 0xFC0B8114
+#define MCF_SDRAMC_SDCS2 0xFC0B8118
+#define MCF_SDRAMC_SDCS3 0xFC0B811C
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD (0x00010000)
+#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
+#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
+#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
+#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
+#define MCF_SDRAMC_SDCR_IREF (0x00000004)
+#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
+#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12)
+#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
+#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000)
+#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
+#define MCF_SDRAMC_SDCR_REF (0x10000000)
+#define MCF_SDRAMC_SDCR_DDR (0x20000000)
+#define MCF_SDRAMC_SDCR_CKE (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
+#define MCF_SDRAMC_SDCR_PS_16 (0x00002000)
+#define MCF_SDRAMC_SDCR_PS_32 (0x00000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
+
+/* Device Errata - LIMP mode work around */
+#define MCF_SDRAMC_REFRESH (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDDS */
+#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0)
+#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
+#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
+#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
+#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCS */
+#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0)
+#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
+#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
+#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
+#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
+#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
+#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
+#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
+#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
+#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
+#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
+#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
+#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
+#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
+#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
+#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
+#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
+
+/*
+ * Edge Port Module (EPORT)
+ */
+#define MCFEPORT_EPPAR (0xFC094000)
+#define MCFEPORT_EPDDR (0xFC094002)
+#define MCFEPORT_EPIER (0xFC094003)
+#define MCFEPORT_EPDR (0xFC094004)
+#define MCFEPORT_EPPDR (0xFC094005)
+#define MCFEPORT_EPFR (0xFC094006)
+
+/*
+ * I2C Module
+ */
+#define MCFI2C_BASE0 (0xFc058000)
+#define MCFI2C_SIZE0 0x40
+
+/********************************************************************/
+#endif /* m53xxsim_h */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
new file mode 100644
index 0000000..0c2720d
--- /dev/null
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * m5407sim.h -- ColdFire 5407 System Integration Module support.
+ *
+ * (C) Copyright 2000, Lineo (www.lineo.com)
+ * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
+ *
+ * Modified by David W. Miller for the MCF5307 Eval Board.
+ */
+
+/****************************************************************************/
+#ifndef m5407sim_h
+#define m5407sim_h
+/****************************************************************************/
+
+#define CPU_NAME "COLDFIRE(m5407)"
+#define CPU_INSTR_PER_JIFFY 3
+#define MCF_BUSCLK (MCF_CLK / 2)
+
+#include <asm/m54xxacr.h>
+
+/*
+ * Define the 5407 SIM register set addresses.
+ */
+#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
+#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
+#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
+#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
+#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
+#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
+#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
+#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
+#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
+#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
+#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
+#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
+#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
+
+#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
+#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
+#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
+#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
+#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
+#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
+
+#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
+#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
+#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
+#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
+#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
+#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
+#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
+#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
+#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
+#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
+#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
+#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
+#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
+#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
+#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
+#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
+#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
+#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
+
+#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
+#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
+#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
+#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
+
+/*
+ * Timer module.
+ */
+#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
+#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
+
+#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
+
+#define MCFSIM_PADDR (MCF_MBAR + 0x244)
+#define MCFSIM_PADAT (MCF_MBAR + 0x248)
+
+/*
+ * DMA unit base addresses.
+ */
+#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
+#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
+#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
+#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX 16
+#define MCFGPIO_IRQ_MAX -1
+#define MCFGPIO_IRQ_VECBASE -1
+
+/*
+ * Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
+#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
+#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
+#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
+#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
+#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
+#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
+
+/*
+ * Some symbol defines for the Parallel Port Pin Assignment Register
+ */
+#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
+ /* Clear to select par I/O */
+#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
+ /* Clear to select par I/O */
+
+/*
+ * Defines for the IRQPAR Register
+ */
+#define IRQ5_LEVEL4 0x80
+#define IRQ3_LEVEL6 0x40
+#define IRQ1_LEVEL2 0x20
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
+#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
+#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
+#define MCF_IRQ_UART0 73 /* UART0 */
+#define MCF_IRQ_UART1 74 /* UART1 */
+
+/*
+ * I2C module
+ */
+#define MCFI2C_BASE0 (MCF_MBAR + 0x280)
+#define MCFI2C_SIZE0 0x40
+
+/****************************************************************************/
+#endif /* m5407sim_h */
diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h
new file mode 100644
index 0000000..c87556d
--- /dev/null
+++ b/arch/m68k/include/asm/m5441xsim.h
@@ -0,0 +1,287 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * m5441xsim.h -- Coldfire 5441x register definitions
+ *
+ * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
+*/
+
+#ifndef m5441xsim_h
+#define m5441xsim_h
+
+#define CPU_NAME "COLDFIRE(m5441x)"
+#define CPU_INSTR_PER_JIFFY 2
+#define MCF_BUSCLK (MCF_CLK / 2)
+#define MACHINE MACH_M5441X
+#define FPUTYPE 0
+#define IOMEMBASE 0xe0000000
+#define IOMEMSIZE 0x20000000
+
+#include <asm/m54xxacr.h>
+
+/*
+ * Reset Controller Module.
+ */
+
+#define MCF_RCR 0xec090000
+#define MCF_RSR 0xec090001
+
+#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
+#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
+
+/*
+ * Interrupt Controller Modules.
+ */
+/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
+#define MCFINT_VECBASE 64
+#define MCFINT0_VECBASE MCFINT_VECBASE
+#define MCFINT1_VECBASE (MCFINT0_VECBASE + 64)
+#define MCFINT2_VECBASE (MCFINT1_VECBASE + 64)
+
+/* interrupt controller 0 */
+#define MCFINTC0_SIMR 0xfc04801c
+#define MCFINTC0_CIMR 0xfc04801d
+#define MCFINTC0_ICR0 0xfc048040
+/* interrupt controller 1 */
+#define MCFINTC1_SIMR 0xfc04c01c
+#define MCFINTC1_CIMR 0xfc04c01d
+#define MCFINTC1_ICR0 0xfc04c040
+/* interrupt controller 2 */
+#define MCFINTC2_SIMR 0xfc05001c
+#define MCFINTC2_CIMR 0xfc05001d
+#define MCFINTC2_ICR0 0xfc050040
+
+/* on interrupt controller 0 */
+#define MCFINT0_EPORT0 1
+#define MCFINT0_UART0 26
+#define MCFINT0_UART1 27
+#define MCFINT0_UART2 28
+#define MCFINT0_UART3 29
+#define MCFINT0_I2C0 30
+#define MCFINT0_DSPI0 31
+
+#define MCFINT0_TIMER0 32
+#define MCFINT0_TIMER1 33
+#define MCFINT0_TIMER2 34
+#define MCFINT0_TIMER3 35
+
+#define MCFINT0_FECRX0 36
+#define MCFINT0_FECTX0 40
+#define MCFINT0_FECENTC0 42
+
+#define MCFINT0_FECRX1 49
+#define MCFINT0_FECTX1 53
+#define MCFINT0_FECENTC1 55
+
+/* on interrupt controller 1 */
+#define MCFINT1_UART4 48
+#define MCFINT1_UART5 49
+#define MCFINT1_UART6 50
+#define MCFINT1_UART7 51
+#define MCFINT1_UART8 52
+#define MCFINT1_UART9 53
+#define MCFINT1_DSPI1 54
+#define MCFINT1_DSPI2 55
+#define MCFINT1_DSPI3 56
+#define MCFINT1_I2C1 57
+#define MCFINT1_I2C2 58
+#define MCFINT1_I2C3 59
+#define MCFINT1_I2C4 60
+#define MCFINT1_I2C5 61
+
+/* on interrupt controller 2 */
+#define MCFINT2_PIT0 13
+#define MCFINT2_PIT1 14
+#define MCFINT2_PIT2 15
+#define MCFINT2_PIT3 16
+#define MCFINT2_RTC 26
+
+/*
+ * PIT timer module.
+ */
+#define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */
+#define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
+#define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */
+#define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */
+
+
+#define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1)
+
+/*
+ * Power Management
+ */
+#define MCFPM_WCR 0xfc040013
+#define MCFPM_PPMSR0 0xfc04002c
+#define MCFPM_PPMCR0 0xfc04002d
+#define MCFPM_PPMSR1 0xfc04002e
+#define MCFPM_PPMCR1 0xfc04002f
+#define MCFPM_PPMHR0 0xfc040030
+#define MCFPM_PPMLR0 0xfc040034
+#define MCFPM_PPMHR1 0xfc040038
+#define MCFPM_PPMLR1 0xfc04003c
+#define MCFPM_LPCR 0xec090007
+/*
+ * UART module.
+ */
+#define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */
+#define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */
+#define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */
+#define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */
+#define MCFUART_BASE4 0xec060000 /* Base address of UART4 */
+#define MCFUART_BASE5 0xec064000 /* Base address of UART5 */
+#define MCFUART_BASE6 0xec068000 /* Base address of UART6 */
+#define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */
+#define MCFUART_BASE8 0xec070000 /* Base address of UART8 */
+#define MCFUART_BASE9 0xec074000 /* Base address of UART9 */
+
+#define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0)
+#define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1)
+#define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2)
+#define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3)
+#define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4)
+#define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5)
+#define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6)
+#define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7)
+#define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8)
+#define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9)
+/*
+ * FEC modules.
+ */
+#define MCFFEC_BASE0 0xfc0d4000
+#define MCFFEC_SIZE0 0x800
+#define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0)
+#define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0)
+#define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0)
+
+#define MCFFEC_BASE1 0xfc0d8000
+#define MCFFEC_SIZE1 0x800
+#define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1)
+#define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1)
+#define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1)
+/*
+ * I2C modules.
+ */
+#define MCFI2C_BASE0 0xfc058000
+#define MCFI2C_SIZE0 0x20
+#define MCFI2C_BASE1 0xfc038000
+#define MCFI2C_SIZE1 0x20
+#define MCFI2C_BASE2 0xec010000
+#define MCFI2C_SIZE2 0x20
+#define MCFI2C_BASE3 0xec014000
+#define MCFI2C_SIZE3 0x20
+#define MCFI2C_BASE4 0xec018000
+#define MCFI2C_SIZE4 0x20
+#define MCFI2C_BASE5 0xec01c000
+#define MCFI2C_SIZE5 0x20
+
+#define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0)
+#define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1)
+#define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2)
+#define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3)
+#define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4)
+#define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5)
+/*
+ * EPORT Module.
+ */
+#define MCFEPORT_EPPAR 0xfc090000
+#define MCFEPORT_EPIER 0xfc090003
+#define MCFEPORT_EPFR 0xfc090006
+/*
+ * RTC Module.
+ */
+#define MCFRTC_BASE 0xfc0a8000
+#define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000)
+#define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC)
+
+/*
+ * GPIO Module.
+ */
+#define MCFGPIO_PODR_A 0xec094000
+#define MCFGPIO_PODR_B 0xec094001
+#define MCFGPIO_PODR_C 0xec094002
+#define MCFGPIO_PODR_D 0xec094003
+#define MCFGPIO_PODR_E 0xec094004
+#define MCFGPIO_PODR_F 0xec094005
+#define MCFGPIO_PODR_G 0xec094006
+#define MCFGPIO_PODR_H 0xec094007
+#define MCFGPIO_PODR_I 0xec094008
+#define MCFGPIO_PODR_J 0xec094009
+#define MCFGPIO_PODR_K 0xec09400a
+
+#define MCFGPIO_PDDR_A 0xec09400c
+#define MCFGPIO_PDDR_B 0xec09400d
+#define MCFGPIO_PDDR_C 0xec09400e
+#define MCFGPIO_PDDR_D 0xec09400f
+#define MCFGPIO_PDDR_E 0xec094010
+#define MCFGPIO_PDDR_F 0xec094011
+#define MCFGPIO_PDDR_G 0xec094012
+#define MCFGPIO_PDDR_H 0xec094013
+#define MCFGPIO_PDDR_I 0xec094014
+#define MCFGPIO_PDDR_J 0xec094015
+#define MCFGPIO_PDDR_K 0xec094016
+
+#define MCFGPIO_PPDSDR_A 0xec094018
+#define MCFGPIO_PPDSDR_B 0xec094019
+#define MCFGPIO_PPDSDR_C 0xec09401a
+#define MCFGPIO_PPDSDR_D 0xec09401b
+#define MCFGPIO_PPDSDR_E 0xec09401c
+#define MCFGPIO_PPDSDR_F 0xec09401d
+#define MCFGPIO_PPDSDR_G 0xec09401e
+#define MCFGPIO_PPDSDR_H 0xec09401f
+#define MCFGPIO_PPDSDR_I 0xec094020
+#define MCFGPIO_PPDSDR_J 0xec094021
+#define MCFGPIO_PPDSDR_K 0xec094022
+
+#define MCFGPIO_PCLRR_A 0xec094024
+#define MCFGPIO_PCLRR_B 0xec094025
+#define MCFGPIO_PCLRR_C 0xec094026
+#define MCFGPIO_PCLRR_D 0xec094027
+#define MCFGPIO_PCLRR_E 0xec094028
+#define MCFGPIO_PCLRR_F 0xec094029
+#define MCFGPIO_PCLRR_G 0xec09402a
+#define MCFGPIO_PCLRR_H 0xec09402b
+#define MCFGPIO_PCLRR_I 0xec09402c
+#define MCFGPIO_PCLRR_J 0xec09402d
+#define MCFGPIO_PCLRR_K 0xec09402e
+
+#define MCFGPIO_PAR_FBCTL 0xec094048
+#define MCFGPIO_PAR_BE 0xec094049
+#define MCFGPIO_PAR_CS 0xec09404a
+#define MCFGPIO_PAR_CANI2C 0xec09404b
+#define MCFGPIO_PAR_IRQ0H 0xec09404c
+#define MCFGPIO_PAR_IRQ0L 0xec09404d
+#define MCFGPIO_PAR_DSPIOWH 0xec09404e
+#define MCFGPIO_PAR_DSPIOWL 0xec09404f
+#define MCFGPIO_PAR_TIMER 0xec094050
+#define MCFGPIO_PAR_UART2 0xec094051
+#define MCFGPIO_PAR_UART1 0xec094052
+#define MCFGPIO_PAR_UART0 0xec094053
+#define MCFGPIO_PAR_SDHCH 0xec094054
+#define MCFGPIO_PAR_SDHCL 0xec094055
+#define MCFGPIO_PAR_SIMP0H 0xec094056
+#define MCFGPIO_PAR_SIMP0L 0xec094057
+#define MCFGPIO_PAR_SSI0H 0xec094058
+#define MCFGPIO_PAR_SSI0L 0xec094059
+#define MCFGPIO_PAR_DEBUGH1 0xec09405a
+#define MCFGPIO_PAR_DEBUGH0 0xec09405b
+#define MCFGPIO_PAR_DEBUGl 0xec09405c
+#define MCFGPIO_PAR_FEC 0xec09405e
+
+/* generalization for generic gpio support */
+#define MCFGPIO_PODR MCFGPIO_PODR_A
+#define MCFGPIO_PDDR MCFGPIO_PDDR_A
+#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A
+#define MCFGPIO_SETR MCFGPIO_PPDSDR_A
+#define MCFGPIO_CLRR MCFGPIO_PCLRR_A
+
+#define MCFGPIO_IRQ_MIN 17
+#define MCFGPIO_IRQ_MAX 24
+#define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
+#define MCFGPIO_PIN_MAX 87
+
+/*
+ * DSPI module.
+ */
+#define MCFDSPI_BASE0 0xfc05c000
+#define MCF_IRQ_DSPI0 (MCFINT0_VECBASE + MCFINT0_DSPI0)
+
+#endif /* m5441xsim_h */
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
new file mode 100644
index 0000000..466df7b
--- /dev/null
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Bit definitions for the MCF54xx ACR and CACR registers.
+ */
+
+#ifndef m54xxacr_h
+#define m54xxacr_h
+
+/*
+ * Define the Cache register flags.
+ */
+#define CACR_DEC 0x80000000 /* Enable data cache */
+#define CACR_DWP 0x40000000 /* Data write protection */
+#define CACR_DESB 0x20000000 /* Enable data store buffer */
+#define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */
+#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */
+#define CACR_DDCM_WT 0x00000000 /* Write through cache*/
+#define CACR_DDCM_CP 0x02000000 /* Copyback cache */
+#define CACR_DDCM_P 0x04000000 /* No cache, precise */
+#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */
+#define CACR_DCINVA 0x01000000 /* Invalidate data cache */
+#define CACR_BEC 0x00080000 /* Enable branch cache */
+#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */
+#define CACR_IEC 0x00008000 /* Enable instruction cache */
+#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
+#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
+#define CACR_IHLCK 0x00000800 /* Instruction cache half lock */
+#define CACR_IDCM 0x00000400 /* Instruction cache inhibit */
+#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
+#define CACR_EUSP 0x00000020 /* Enable separate user a7 */
+
+#define ACR_BASE_POS 24 /* Address Base */
+#define ACR_MASK_POS 16 /* Address Mask */
+#define ACR_ENABLE 0x00008000 /* Enable address */
+#define ACR_USER 0x00000000 /* User mode access only */
+#define ACR_SUPER 0x00002000 /* Supervisor mode only */
+#define ACR_ANY 0x00004000 /* Match any access mode */
+#define ACR_CM_WT 0x00000000 /* Write through mode */
+#define ACR_CM_CP 0x00000020 /* Copyback mode */
+#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */
+#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */
+#define ACR_CM 0x00000060 /* Cache mode mask */
+#define ACR_SP 0x00000008 /* Supervisor protect */
+#define ACR_WPROTECT 0x00000004 /* Write protect */
+
+#define ACR_BA(x) ((x) & 0xff000000)
+#define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
+
+#if defined(CONFIG_M5407)
+
+#define ICACHE_SIZE 0x4000 /* instruction - 16k */
+#define DCACHE_SIZE 0x2000 /* data - 8k */
+
+#elif defined(CONFIG_M54xx)
+
+#define ICACHE_SIZE 0x8000 /* instruction - 32k */
+#define DCACHE_SIZE 0x8000 /* data - 32k */
+
+#elif defined(CONFIG_M5441x)
+
+#define ICACHE_SIZE 0x2000 /* instruction - 8k */
+#define DCACHE_SIZE 0x2000 /* data - 8k */
+#endif
+
+#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
+#define CACHE_WAYS 4 /* 4 ways */
+
+#define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
+#define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
+#define ICACHE_MAX_ADDR ICACHE_SET_MASK
+#define DCACHE_MAX_ADDR DCACHE_SET_MASK
+
+/*
+ * Version 4 cores have a true harvard style separate instruction
+ * and data cache. Enable data and instruction caches, also enable write
+ * buffers and branch accelerator.
+ */
+/* attention : enabling CACR_DESB requires a "nop" to flush the store buffer */
+/* use '+' instead of '|' for assembler's sake */
+
+ /* Enable data cache */
+ /* Enable data store buffer */
+ /* outside ACRs : No cache, precise */
+ /* Enable instruction+branch caches */
+#if defined(CONFIG_M5407)
+#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC)
+#else
+#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
+#endif
+#define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
+
+#if defined(CONFIG_MMU)
+/*
+ * If running with the MMU enabled then we need to map the internal
+ * register region as non-cacheable. And then we map all our RAM as
+ * cacheable and supervisor access only.
+ */
+#define ACR0_MODE (ACR_BA(IOMEMBASE)+ACR_ADMSK(IOMEMSIZE)+ \
+ ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
+#if defined(CONFIG_CACHE_COPYBACK)
+#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
+ ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)
+#else
+#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
+ ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT)
+#endif
+#define ACR2_MODE 0
+#define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
+ ACR_ENABLE+ACR_SUPER+ACR_SP)
+
+#else
+
+/*
+ * For the non-MMU enabled case we map all of RAM as cacheable.
+ */
+#if defined(CONFIG_CACHE_COPYBACK)
+#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP)
+#else
+#define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
+#endif
+#define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
+
+#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
+#define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA)
+#define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA)
+#define ACR0_MODE (0x000f0000+DATA_CACHE_MODE)
+#define ACR1_MODE 0
+#define ACR2_MODE (0x000f0000+INSN_CACHE_MODE)
+#define ACR3_MODE 0
+
+#if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP)
+/* Copyback cache mode must push dirty cache lines first */
+#define CACHE_PUSH
+#endif
+
+#endif /* CONFIG_MMU */
+#endif /* m54xxacr_h */
diff --git a/arch/m68k/include/asm/m54xxgpt.h b/arch/m68k/include/asm/m54xxgpt.h
new file mode 100644
index 0000000..b1f9121
--- /dev/null
+++ b/arch/m68k/include/asm/m54xxgpt.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * File: m54xxgpt.h
+ * Purpose: Register and bit definitions for the MCF54XX
+ *
+ * Notes:
+ *
+ */
+
+#ifndef m54xxgpt_h
+#define m54xxgpt_h
+
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
+#define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
+#define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
+#define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
+#define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
+#define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
+#define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
+#define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
+#define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
+#define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)
+#define MCF_GPT_GPWM2 (MCF_MBAR + 0x000828)
+#define MCF_GPT_GSR2 (MCF_MBAR + 0x00082C)
+#define MCF_GPT_GMS3 (MCF_MBAR + 0x000830)
+#define MCF_GPT_GCIR3 (MCF_MBAR + 0x000834)
+#define MCF_GPT_GPWM3 (MCF_MBAR + 0x000838)
+#define MCF_GPT_GSR3 (MCF_MBAR + 0x00083C)
+#define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010))
+#define MCF_GPT_GCIR(x) (MCF_MBAR + 0x000804 + ((x) * 0x010))
+#define MCF_GPT_GPWM(x) (MCF_MBAR + 0x000808 + ((x) * 0x010))
+#define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010))
+
+/* Bit definitions and macros for MCF_GPT_GMS */
+#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
+#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
+#define MCF_GPT_GMS_IEN (0x00000100)
+#define MCF_GPT_GMS_OD (0x00000200)
+#define MCF_GPT_GMS_SC (0x00000400)
+#define MCF_GPT_GMS_CE (0x00001000)
+#define MCF_GPT_GMS_WDEN (0x00008000)
+#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
+#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
+#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
+#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
+#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
+#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
+#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
+#define MCF_GPT_GMS_ICT_ANY (0x00000000)
+#define MCF_GPT_GMS_ICT_RISE (0x00010000)
+#define MCF_GPT_GMS_ICT_FALL (0x00020000)
+#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
+#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
+#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
+#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
+#define MCF_GPT_GMS_GPIO_MASK (0x00000030)
+#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
+#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
+#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
+#define MCF_GPT_GMS_TMS_PWM (0x00000003)
+#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
+#define MCF_GPT_GMS_TMS_MASK (0x00000007)
+
+/* Bit definitions and macros for MCF_GPT_GCIR */
+#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
+#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_GPT_GPWM */
+#define MCF_GPT_GPWM_LOAD (0x00000001)
+#define MCF_GPT_GPWM_PWMOP (0x00000100)
+#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for MCF_GPT_GSR */
+#define MCF_GPT_GSR_CAPT (0x00000001)
+#define MCF_GPT_GSR_COMP (0x00000002)
+#define MCF_GPT_GSR_PWMP (0x00000004)
+#define MCF_GPT_GSR_TEXP (0x00000008)
+#define MCF_GPT_GSR_PIN (0x00000100)
+#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
+#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
+
+/********************************************************************/
+
+#endif /* m54xxgpt_h */
diff --git a/arch/m68k/include/asm/m54xxpci.h b/arch/m68k/include/asm/m54xxpci.h
new file mode 100644
index 0000000..4687f5a
--- /dev/null
+++ b/arch/m68k/include/asm/m54xxpci.h
@@ -0,0 +1,138 @@
+/****************************************************************************/
+
+/*
+ * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
+ *
+ * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+/****************************************************************************/
+#ifndef M54XXPCI_H
+#define M54XXPCI_H
+/****************************************************************************/
+
+/*
+ * The core set of PCI support registers are mapped into the MBAR region.
+ */
+#define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
+#define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
+#define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
+#define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
+#define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
+#define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
+#define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
+#define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
+#define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
+#define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
+#define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */
+
+#define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */
+#define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */
+#define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */
+#define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */
+#define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */
+#define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */
+#define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */
+#define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */
+#define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */
+#define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */
+#define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */
+
+#define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
+#define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
+#define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
+#define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
+#define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
+#define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
+#define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
+#define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
+#define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
+#define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */
+#define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
+#define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
+#define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
+#define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
+
+#define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */
+#define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */
+#define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */
+#define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */
+#define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */
+#define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */
+#define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */
+#define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */
+#define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */
+#define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */
+#define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */
+#define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */
+#define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
+
+#define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
+#define PASR (CONFIG_MBAR + 0xc04) /* PCI arbiter status */
+
+/*
+ * Definitions for the Global status and control register.
+ */
+#define PCIGSCR_PE 0x20000000 /* Parity error detected */
+#define PCIGSCR_SE 0x10000000 /* System error detected */
+#define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */
+#define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */
+#define PCIGSCR_SEE 0x00001000 /* System error intr enable */
+#define PCIGSCR_RESET 0x00000001 /* Reset bit */
+
+/*
+ * Bit definitions for the PCICAR configuration address register.
+ */
+#define PCICAR_E 0x80000000 /* Enable config space */
+#define PCICAR_BUSN 16 /* Move bus bits */
+#define PCICAR_DEVFNN 8 /* Move devfn bits */
+#define PCICAR_DWORDN 0 /* Move dword bits */
+
+/*
+ * The initiator windows hold the memory and IO mapping information.
+ * This macro creates the register values from the desired addresses.
+ */
+#define WXBTAR(hostaddr, pciaddr, size) \
+ (((hostaddr) & 0xff000000) | \
+ ((((size) - 1) & 0xff000000) >> 8) | \
+ (((pciaddr) & 0xff000000) >> 16))
+
+#define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */
+#define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */
+#define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */
+#define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */
+#define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */
+#define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */
+
+#define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */
+#define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */
+#define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */
+#define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */
+#define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */
+#define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */
+
+/*
+ * Bit definitions for the PCIBATR registers.
+ */
+#define PCITBATR0_E 0x00000001 /* Enable window 0 */
+#define PCITBATR1_E 0x00000001 /* Enable window 1 */
+
+/*
+ * PCI arbiter support definitions and macros.
+ */
+#define PACR_INTMPRI 0x00000001
+#define PACR_EXTMPRI(x) (((x) & 0x1f) << 1)
+#define PACR_INTMINTE 0x00010000
+#define PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
+#define PACR_PKMD 0x40000000
+#define PACR_DS 0x80000000
+
+#define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */
+#define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */
+
+/****************************************************************************/
+#endif /* M54XXPCI_H */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
new file mode 100644
index 0000000..2a3305f
--- /dev/null
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
+ */
+
+#ifndef m54xxsim_h
+#define m54xxsim_h
+
+#define CPU_NAME "COLDFIRE(m54xx)"
+#define CPU_INSTR_PER_JIFFY 2
+#define MCF_BUSCLK (MCF_CLK / 2)
+#define MACHINE MACH_M54XX
+#define FPUTYPE FPU_COLDFIRE
+#define IOMEMBASE MCF_MBAR
+#define IOMEMSIZE 0x01000000
+
+#include <asm/m54xxacr.h>
+
+#define MCFINT_VECBASE 64
+
+/*
+ * Interrupt Controller Registers
+ */
+#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
+
+#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
+#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
+#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
+#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
+#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
+#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
+#define MCFINTC_IRLR 0x18 /* */
+#define MCFINTC_IACKL 0x19 /* */
+#define MCFINTC_ICR0 0x40 /* Base ICR register */
+
+/*
+ * UART module.
+ */
+#define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
+#define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
+#define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
+#define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
+
+/*
+ * Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
+#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
+#define MCF_IRQ_I2C0 (MCFINT_VECBASE + 40)
+#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
+#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
+#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
+#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
+
+/*
+ * Slice Timer support.
+ */
+#define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
+#define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PODR (MCF_MBAR + 0xA00)
+#define MCFGPIO_PDDR (MCF_MBAR + 0xA10)
+#define MCFGPIO_PPDR (MCF_MBAR + 0xA20)
+#define MCFGPIO_SETR (MCF_MBAR + 0xA20)
+#define MCFGPIO_CLRR (MCF_MBAR + 0xA30)
+
+#define MCFGPIO_PIN_MAX 136 /* 128 gpio + 8 eport */
+#define MCFGPIO_IRQ_MAX 8
+#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
+
+/*
+ * EDGE Port support.
+ */
+#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
+#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
+#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
+#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
+#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
+#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
+
+/*
+ * Pin Assignment register definitions
+ */
+#define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
+#define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
+#define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
+#define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
+#define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
+#define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
+#define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
+#define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
+#define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
+#define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
+#define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
+#define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
+
+#define MCF_PAR_SDA (0x0008)
+#define MCF_PAR_SCL (0x0004)
+#define MCF_PAR_PSC_TXD (0x04)
+#define MCF_PAR_PSC_RXD (0x08)
+#define MCF_PAR_PSC_CTS_GPIO (0x00)
+#define MCF_PAR_PSC_CTS_BCLK (0x80)
+#define MCF_PAR_PSC_CTS_CTS (0xC0)
+#define MCF_PAR_PSC_RTS_GPIO (0x00)
+#define MCF_PAR_PSC_RTS_FSYNC (0x20)
+#define MCF_PAR_PSC_RTS_RTS (0x30)
+#define MCF_PAR_PSC_CANRX (0x40)
+
+#define MCF_PAR_FECI2CIRQ (MCF_MBAR + 0x00000a44) /* FEC/I2C/IRQ */
+#define MCF_PAR_FECI2CIRQ_SDA (1 << 3)
+#define MCF_PAR_FECI2CIRQ_SCL (1 << 2)
+
+/*
+ * I2C module.
+ */
+#define MCFI2C_BASE0 (MCF_MBAR + 0x8f00)
+#define MCFI2C_SIZE0 0x40
+
+#endif /* m54xxsim_h */
diff --git a/arch/m68k/include/asm/mac_asc.h b/arch/m68k/include/asm/mac_asc.h
new file mode 100644
index 0000000..0759902
--- /dev/null
+++ b/arch/m68k/include/asm/mac_asc.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Apple Sound Chip
+ */
+
+#ifndef __ASM_MAC_ASC_H
+#define __ASM_MAC_ASC_H
+
+/*
+ * ASC offsets and controls
+ */
+
+#define ASC_BUF_BASE 0x00 /* RAM buffer offset */
+#define ASC_BUF_SIZE 0x800
+
+#define ASC_CONTROL 0x800
+#define ASC_CONTROL_OFF 0x00
+#define ASC_FREQ(chan,byte) ((0x810)+((chan)<<3)+(byte))
+#define ASC_ENABLE 0x801
+#define ASC_ENABLE_SAMPLE 0x02
+#define ASC_MODE 0x802
+#define ASC_MODE_SAMPLE 0x02
+
+#define ASC_VOLUME 0x806
+#define ASC_CHAN 0x807 /* ??? */
+
+
+#endif
diff --git a/arch/m68k/include/asm/mac_baboon.h b/arch/m68k/include/asm/mac_baboon.h
new file mode 100644
index 0000000..08d9b88
--- /dev/null
+++ b/arch/m68k/include/asm/mac_baboon.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Definitions for the "Baboon" custom IC on the PowerBook 190.
+ */
+
+#define BABOON_BASE (0x50F1A000) /* same as IDE controller base */
+
+#ifndef __ASSEMBLY__
+
+struct baboon {
+ char pad1[208]; /* generic IDE registers, not used here */
+ short mb_control; /* Control register:
+ * bit 5 : slot 2 power control
+ * bit 6 : slot 1 power control
+ */
+ char pad2[2];
+ short mb_status; /* (0xD4) media bay status register:
+ *
+ * bit 0: ????
+ * bit 1: IDE interrupt active?
+ * bit 2: bay status, 0 = full, 1 = empty
+ * bit 3: ????
+ */
+ char pad3[2]; /* (0xD6) not used */
+ short mb_ifr; /* (0xD8) media bay interrupt flags register:
+ *
+ * bit 0: ????
+ * bit 1: IDE controller interrupt
+ * bit 2: media bay status change interrupt
+ */
+};
+
+extern int baboon_present;
+
+extern void baboon_register_interrupts(void);
+extern void baboon_irq_enable(int);
+extern void baboon_irq_disable(int);
+
+#endif /* __ASSEMBLY **/
diff --git a/arch/m68k/include/asm/mac_iop.h b/arch/m68k/include/asm/mac_iop.h
new file mode 100644
index 0000000..32f1c79
--- /dev/null
+++ b/arch/m68k/include/asm/mac_iop.h
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * I/O Processor (IOP) defines and structures, mostly snagged from A/UX
+ * header files.
+ *
+ * The original header from which this was taken is copyrighted. I've done some
+ * rewriting (in fact my changes make this a bit more readable, IMHO) but some
+ * more should be done.
+ */
+
+/*
+ * This is the base address of the IOPs. Use this as the address of
+ * a "struct iop" (see below) to see where the actual registers fall.
+ */
+
+#define SCC_IOP_BASE_IIFX (0x50F04000)
+#define ISM_IOP_BASE_IIFX (0x50F12000)
+
+#define SCC_IOP_BASE_QUADRA (0x50F0C000)
+#define ISM_IOP_BASE_QUADRA (0x50F1E000)
+
+/* IOP status/control register bits: */
+
+#define IOP_BYPASS 0x01 /* bypass-mode hardware access */
+#define IOP_AUTOINC 0x02 /* allow autoincrement of ramhi/lo */
+#define IOP_RUN 0x04 /* set to 0 to reset IOP chip */
+#define IOP_IRQ 0x08 /* generate IRQ to IOP if 1 */
+#define IOP_INT0 0x10 /* intr priority from IOP to host */
+#define IOP_INT1 0x20 /* intr priority from IOP to host */
+#define IOP_HWINT 0x40 /* IRQ from hardware; bypass mode only */
+#define IOP_DMAINACTIVE 0x80 /* no DMA request active; bypass mode only */
+
+#define NUM_IOPS 2
+#define NUM_IOP_CHAN 7
+#define NUM_IOP_MSGS NUM_IOP_CHAN*8
+#define IOP_MSG_LEN 32
+
+/* IOP reference numbers, used by the globally-visible iop_xxx functions */
+
+#define IOP_NUM_SCC 0
+#define IOP_NUM_ISM 1
+
+/* IOP channel states */
+
+#define IOP_MSG_IDLE 0 /* idle */
+#define IOP_MSG_NEW 1 /* new message sent */
+#define IOP_MSG_RCVD 2 /* message received; processing */
+#define IOP_MSG_COMPLETE 3 /* message processing complete */
+
+/* IOP message status codes */
+
+#define IOP_MSGSTATUS_UNUSED 0 /* Unused message structure */
+#define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */
+#define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */
+#define IOP_MSGSTATUS_COMPLETE 3 /* message complete and reply rcvd */
+#define IOP_MSGSTATUS_UNSOL 6 /* message is unsolicited */
+
+/* IOP memory addresses of the members of the mac_iop_kernel structure. */
+
+#define IOP_ADDR_MAX_SEND_CHAN 0x0200
+#define IOP_ADDR_SEND_STATE 0x0201
+#define IOP_ADDR_PATCH_CTRL 0x021F
+#define IOP_ADDR_SEND_MSG 0x0220
+#define IOP_ADDR_MAX_RECV_CHAN 0x0300
+#define IOP_ADDR_RECV_STATE 0x0301
+#define IOP_ADDR_ALIVE 0x031F
+#define IOP_ADDR_RECV_MSG 0x0320
+
+#ifndef __ASSEMBLY__
+
+/*
+ * IOP Control registers, staggered because in usual Apple style they were
+ * too lazy to decode the A0 bit. This structure is assumed to begin at
+ * one of the xxx_IOP_BASE addresses given above.
+ */
+
+struct mac_iop {
+ __u8 ram_addr_hi; /* shared RAM address hi byte */
+ __u8 pad0;
+ __u8 ram_addr_lo; /* shared RAM address lo byte */
+ __u8 pad1;
+ __u8 status_ctrl; /* status/control register */
+ __u8 pad2[3];
+ __u8 ram_data; /* RAM data byte at ramhi/lo */
+
+ __u8 pad3[23];
+
+ /* Bypass-mode hardware access registers */
+
+ union {
+ struct { /* SCC registers */
+ __u8 sccb_cmd; /* SCC B command reg */
+ __u8 pad4;
+ __u8 scca_cmd; /* SCC A command reg */
+ __u8 pad5;
+ __u8 sccb_data; /* SCC B data */
+ __u8 pad6;
+ __u8 scca_data; /* SCC A data */
+ } scc_regs;
+
+ struct { /* ISM registers */
+ __u8 wdata; /* write a data byte */
+ __u8 pad7;
+ __u8 wmark; /* write a mark byte */
+ __u8 pad8;
+ __u8 wcrc; /* write 2-byte crc to disk */
+ __u8 pad9;
+ __u8 wparams; /* write the param regs */
+ __u8 pad10;
+ __u8 wphase; /* write the phase states & dirs */
+ __u8 pad11;
+ __u8 wsetup; /* write the setup register */
+ __u8 pad12;
+ __u8 wzeroes; /* mode reg: 1's clr bits, 0's are x */
+ __u8 pad13;
+ __u8 wones; /* mode reg: 1's set bits, 0's are x */
+ __u8 pad14;
+ __u8 rdata; /* read a data byte */
+ __u8 pad15;
+ __u8 rmark; /* read a mark byte */
+ __u8 pad16;
+ __u8 rerror; /* read the error register */
+ __u8 pad17;
+ __u8 rparams; /* read the param regs */
+ __u8 pad18;
+ __u8 rphase; /* read the phase states & dirs */
+ __u8 pad19;
+ __u8 rsetup; /* read the setup register */
+ __u8 pad20;
+ __u8 rmode; /* read the mode register */
+ __u8 pad21;
+ __u8 rhandshake; /* read the handshake register */
+ } ism_regs;
+ } b;
+};
+
+/* This structure is used to track IOP messages in the Linux kernel */
+
+struct iop_msg {
+ struct iop_msg *next; /* next message in queue or NULL */
+ uint iop_num; /* IOP number */
+ uint channel; /* channel number */
+ void *caller_priv; /* caller private data */
+ int status; /* status of this message */
+ __u8 message[IOP_MSG_LEN]; /* the message being sent/received */
+ __u8 reply[IOP_MSG_LEN]; /* the reply to the message */
+ void (*handler)(struct iop_msg *);
+ /* function to call when reply recvd */
+};
+
+extern int iop_scc_present,iop_ism_present;
+
+extern int iop_listen(uint, uint,
+ void (*handler)(struct iop_msg *),
+ const char *);
+extern int iop_send_message(uint, uint, void *, uint, __u8 *,
+ void (*)(struct iop_msg *));
+extern void iop_complete_message(struct iop_msg *);
+extern void iop_upload_code(uint, __u8 *, uint, __u16);
+extern void iop_download_code(uint, __u8 *, uint, __u16);
+extern __u8 *iop_compare_code(uint, __u8 *, uint, __u16);
+extern void iop_ism_irq_poll(uint);
+
+extern void iop_register_interrupts(void);
+
+#endif /* __ASSEMBLY__ */
diff --git a/arch/m68k/include/asm/mac_oss.h b/arch/m68k/include/asm/mac_oss.h
new file mode 100644
index 0000000..56ef986
--- /dev/null
+++ b/arch/m68k/include/asm/mac_oss.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * OSS
+ *
+ * This is used in place of VIA2 on the IIfx.
+ */
+
+#define OSS_BASE (0x50f1a000)
+
+/*
+ * Interrupt level offsets for mac_oss->irq_level
+ */
+
+#define OSS_NUBUS0 0
+#define OSS_NUBUS1 1
+#define OSS_NUBUS2 2
+#define OSS_NUBUS3 3
+#define OSS_NUBUS4 4
+#define OSS_NUBUS5 5
+#define OSS_IOPISM 6
+#define OSS_IOPSCC 7
+#define OSS_SOUND 8
+#define OSS_SCSI 9
+#define OSS_60HZ 10
+#define OSS_VIA1 11
+#define OSS_UNUSED1 12
+#define OSS_UNUSED2 13
+#define OSS_PARITY 14
+#define OSS_UNUSED3 15
+
+#define OSS_NUM_SOURCES 16
+
+/*
+ * Pending interrupt bits in mac_oss->irq_pending
+ */
+
+#define OSS_IP_NUBUS0 0x0001
+#define OSS_IP_NUBUS1 0x0002
+#define OSS_IP_NUBUS2 0x0004
+#define OSS_IP_NUBUS3 0x0008
+#define OSS_IP_NUBUS4 0x0010
+#define OSS_IP_NUBUS5 0x0020
+#define OSS_IP_IOPISM 0x0040
+#define OSS_IP_IOPSCC 0x0080
+#define OSS_IP_SOUND 0x0100
+#define OSS_IP_SCSI 0x0200
+#define OSS_IP_60HZ 0x0400
+#define OSS_IP_VIA1 0x0800
+#define OSS_IP_UNUSED1 0x1000
+#define OSS_IP_UNUSED2 0x2000
+#define OSS_IP_PARITY 0x4000
+#define OSS_IP_UNUSED3 0x8000
+
+#define OSS_IP_NUBUS (OSS_IP_NUBUS0|OSS_IP_NUBUS1|OSS_IP_NUBUS2|OSS_IP_NUBUS3|OSS_IP_NUBUS4|OSS_IP_NUBUS5)
+
+/*
+ * Rom Control Register
+ */
+
+#define OSS_POWEROFF 0x80
+
+#ifndef __ASSEMBLY__
+
+struct mac_oss {
+ __u8 irq_level[0x10]; /* [0x000-0x00f] Interrupt levels */
+ __u8 padding0[0x1F2]; /* [0x010-0x201] IO space filler */
+ __u16 irq_pending; /* [0x202-0x203] pending interrupts bits */
+ __u8 rom_ctrl; /* [0x204-0x204] ROM cntl reg (for poweroff) */
+ __u8 padding1[0x2]; /* [0x205-0x206] currently unused by A/UX */
+ __u8 ack_60hz; /* [0x207-0x207] 60 Hz ack. */
+};
+
+extern volatile struct mac_oss *oss;
+extern int oss_present;
+
+extern void oss_register_interrupts(void);
+extern void oss_irq_enable(int);
+extern void oss_irq_disable(int);
+
+#endif /* __ASSEMBLY__ */
diff --git a/arch/m68k/include/asm/mac_psc.h b/arch/m68k/include/asm/mac_psc.h
new file mode 100644
index 0000000..86a5a5e
--- /dev/null
+++ b/arch/m68k/include/asm/mac_psc.h
@@ -0,0 +1,252 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Apple Peripheral System Controller (PSC)
+ *
+ * The PSC is used on the AV Macs to control IO functions not handled
+ * by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA
+ * channels.
+ *
+ * The first seven DMA channels appear to be "one-shot" and are actually
+ * sets of two channels; one member is active while the other is being
+ * configured, and then you flip the active member and start all over again.
+ * The one-shot channels are grouped together and are:
+ *
+ * 1. SCSI
+ * 2. Ethernet Read
+ * 3. Ethernet Write
+ * 4. Floppy Disk Controller
+ * 5. SCC Channel A Receive
+ * 6. SCC Channel B Receive
+ * 7. SCC Channel A Transmit
+ *
+ * The remaining two channels are handled somewhat differently. They appear
+ * to be closely tied and share one set of registers. They also seem to run
+ * continuously, although how you keep the buffer filled in this scenario is
+ * not understood as there seems to be only one input and one output buffer
+ * pointer.
+ *
+ * Much of this was extrapolated from what was known about the Ethernet
+ * registers and subsequently confirmed using MacsBug (ie by pinging the
+ * machine with easy-to-find patterns and looking for them in the DMA
+ * buffers, or by sending a file over the serial ports and finding the
+ * file in the buffers.)
+ *
+ * 1999-05-25 (jmt)
+ */
+
+#define PSC_BASE (0x50F31000)
+
+/*
+ * The IER/IFR registers work like the VIA, except that it has 4
+ * of them each on different interrupt levels, and each register
+ * set only seems to handle four interrupts instead of seven.
+ *
+ * To access a particular set of registers, add 0xn0 to the base
+ * where n = 3,4,5 or 6.
+ */
+
+#define pIFRbase 0x100
+#define pIERbase 0x104
+
+/*
+ * One-shot DMA control registers
+ */
+
+#define PSC_MYSTERY 0x804
+
+#define PSC_CTL_BASE 0xC00
+
+#define PSC_SCSI_CTL 0xC00
+#define PSC_ENETRD_CTL 0xC10
+#define PSC_ENETWR_CTL 0xC20
+#define PSC_FDC_CTL 0xC30
+#define PSC_SCCA_CTL 0xC40
+#define PSC_SCCB_CTL 0xC50
+#define PSC_SCCATX_CTL 0xC60
+
+/*
+ * DMA channels. Add +0x10 for the second channel in the set.
+ * You're supposed to use one channel while the other runs and
+ * then flip channels and do the whole thing again.
+ */
+
+#define PSC_ADDR_BASE 0x1000
+#define PSC_LEN_BASE 0x1004
+#define PSC_CMD_BASE 0x1008
+
+#define PSC_SET0 0x00
+#define PSC_SET1 0x10
+
+#define PSC_SCSI_ADDR 0x1000 /* confirmed */
+#define PSC_SCSI_LEN 0x1004 /* confirmed */
+#define PSC_SCSI_CMD 0x1008 /* confirmed */
+#define PSC_ENETRD_ADDR 0x1020 /* confirmed */
+#define PSC_ENETRD_LEN 0x1024 /* confirmed */
+#define PSC_ENETRD_CMD 0x1028 /* confirmed */
+#define PSC_ENETWR_ADDR 0x1040 /* confirmed */
+#define PSC_ENETWR_LEN 0x1044 /* confirmed */
+#define PSC_ENETWR_CMD 0x1048 /* confirmed */
+#define PSC_FDC_ADDR 0x1060 /* strongly suspected */
+#define PSC_FDC_LEN 0x1064 /* strongly suspected */
+#define PSC_FDC_CMD 0x1068 /* strongly suspected */
+#define PSC_SCCA_ADDR 0x1080 /* confirmed */
+#define PSC_SCCA_LEN 0x1084 /* confirmed */
+#define PSC_SCCA_CMD 0x1088 /* confirmed */
+#define PSC_SCCB_ADDR 0x10A0 /* confirmed */
+#define PSC_SCCB_LEN 0x10A4 /* confirmed */
+#define PSC_SCCB_CMD 0x10A8 /* confirmed */
+#define PSC_SCCATX_ADDR 0x10C0 /* confirmed */
+#define PSC_SCCATX_LEN 0x10C4 /* confirmed */
+#define PSC_SCCATX_CMD 0x10C8 /* confirmed */
+
+/*
+ * Free-running DMA registers. The only part known for sure are the bits in
+ * the control register, the buffer addresses and the buffer length. Everything
+ * else is anybody's guess.
+ *
+ * These registers seem to be mirrored every thirty-two bytes up until offset
+ * 0x300. It's safe to assume then that a new set of registers starts there.
+ */
+
+#define PSC_SND_CTL 0x200 /*
+ * [ 16-bit ]
+ * Sound (Singer?) control register.
+ *
+ * bit 0 : ????
+ * bit 1 : ????
+ * bit 2 : Set to one to enable sound
+ * output. Possibly a mute flag.
+ * bit 3 : ????
+ * bit 4 : ????
+ * bit 5 : ????
+ * bit 6 : Set to one to enable pass-thru
+ * audio. In this mode the audio data
+ * seems to appear in both the input
+ * buffer and the output buffer.
+ * bit 7 : Set to one to activate the
+ * sound input DMA or zero to
+ * disable it.
+ * bit 8 : Set to one to activate the
+ * sound output DMA or zero to
+ * disable it.
+ * bit 9 : \
+ * bit 11 : |
+ * These two bits control the sample
+ * rate. Usually set to binary 10 and
+ * MacOS 8.0 says I'm at 48 KHz. Using
+ * a binary value of 01 makes things
+ * sound about 1/2 speed (24 KHz?) and
+ * binary 00 is slower still (22 KHz?)
+ *
+ * Setting this to 0x0000 is a good way to
+ * kill all DMA at boot time so that the
+ * PSC won't overwrite the kernel image
+ * with sound data.
+ */
+
+/*
+ * 0x0202 - 0x0203 is unused. Writing there
+ * seems to clobber the control register.
+ */
+
+#define PSC_SND_SOURCE 0x204 /*
+ * [ 32-bit ]
+ * Controls input source and volume:
+ *
+ * bits 12-15 : input source volume, 0 - F
+ * bits 16-19 : unknown, always 0x5
+ * bits 20-23 : input source selection:
+ * 0x3 = CD Audio
+ * 0x4 = External Audio
+ *
+ * The volume is definitely not the general
+ * output volume as it doesn't affect the
+ * alert sound volume.
+ */
+#define PSC_SND_STATUS1 0x208 /*
+ * [ 32-bit ]
+ * Appears to be a read-only status register.
+ * The usual value is 0x00400002.
+ */
+#define PSC_SND_HUH3 0x20C /*
+ * [ 16-bit ]
+ * Unknown 16-bit value, always 0x0000.
+ */
+#define PSC_SND_BITS2GO 0x20E /*
+ * [ 16-bit ]
+ * Counts down to zero from some constant
+ * value. The value appears to be the
+ * number of _bits_ remaining before the
+ * buffer is full, which would make sense
+ * since Apple's docs say the sound DMA
+ * channels are 1 bit wide.
+ */
+#define PSC_SND_INADDR 0x210 /*
+ * [ 32-bit ]
+ * Address of the sound input DMA buffer
+ */
+#define PSC_SND_OUTADDR 0x214 /*
+ * [ 32-bit ]
+ * Address of the sound output DMA buffer
+ */
+#define PSC_SND_LEN 0x218 /*
+ * [ 16-bit ]
+ * Length of both buffers in eight-byte units.
+ */
+#define PSC_SND_HUH4 0x21A /*
+ * [ 16-bit ]
+ * Unknown, always 0x0000.
+ */
+#define PSC_SND_STATUS2 0x21C /*
+ * [ 16-bit ]
+ * Appears to e a read-only status register.
+ * The usual value is 0x0200.
+ */
+#define PSC_SND_HUH5 0x21E /*
+ * [ 16-bit ]
+ * Unknown, always 0x0000.
+ */
+
+#ifndef __ASSEMBLY__
+
+extern volatile __u8 *psc;
+
+extern void psc_register_interrupts(void);
+extern void psc_irq_enable(int);
+extern void psc_irq_disable(int);
+
+/*
+ * Access functions
+ */
+
+static inline void psc_write_byte(int offset, __u8 data)
+{
+ *((volatile __u8 *)(psc + offset)) = data;
+}
+
+static inline void psc_write_word(int offset, __u16 data)
+{
+ *((volatile __u16 *)(psc + offset)) = data;
+}
+
+static inline void psc_write_long(int offset, __u32 data)
+{
+ *((volatile __u32 *)(psc + offset)) = data;
+}
+
+static inline u8 psc_read_byte(int offset)
+{
+ return *((volatile __u8 *)(psc + offset));
+}
+
+static inline u16 psc_read_word(int offset)
+{
+ return *((volatile __u16 *)(psc + offset));
+}
+
+static inline u32 psc_read_long(int offset)
+{
+ return *((volatile __u32 *)(psc + offset));
+}
+
+#endif /* __ASSEMBLY__ */
diff --git a/arch/m68k/include/asm/mac_via.h b/arch/m68k/include/asm/mac_via.h
new file mode 100644
index 0000000..de1470c
--- /dev/null
+++ b/arch/m68k/include/asm/mac_via.h
@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * 6522 Versatile Interface Adapter (VIA)
+ *
+ * There are two of these on the Mac II. Some IRQ's are vectored
+ * via them as are assorted bits and bobs - eg rtc, adb. The picture
+ * is a bit incomplete as the Mac documentation doesn't cover this well
+ */
+
+#ifndef _ASM_MAC_VIA_H_
+#define _ASM_MAC_VIA_H_
+
+/*
+ * Base addresses for the VIAs. There are two in every machine,
+ * although on some machines the second is an RBV or an OSS.
+ * The OSS is different enough that it's handled separately.
+ *
+ * Do not use these values directly; use the via1 and via2 variables
+ * instead (and don't forget to check rbv_present when using via2!)
+ */
+
+#define VIA1_BASE (0x50F00000)
+#define VIA2_BASE (0x50F02000)
+#define RBV_BASE (0x50F26000)
+
+/*
+ * Not all of these are true post MacII I think.
+ * CSA: probably the ones CHRP marks as 'unused' change purposes
+ * when the IWM becomes the SWIM.
+ * http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html
+ * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
+ *
+ * also, http://developer.apple.com/technotes/hw/hw_09.html claims the
+ * following changes for IIfx:
+ * VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP.
+ * Also, "All of the functionality of VIA2 has been moved to other chips".
+ */
+
+#define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
+ * [CHRP] SCC WREQ: Reflects the state of the
+ * Wait/Request pins from the SCC.
+ * [Macintosh Family Hardware]
+ * as CHRP on SE/30,II,IIx,IIcx,IIci.
+ * on IIfx, "0 means an active request"
+ */
+#define VIA1A_vRev8 0x40 /* Revision 8 board ???
+ * [CHRP] En WaitReqB: Lets the WaitReq_L
+ * signal from port B of the SCC appear on
+ * the PA7 input pin. Output.
+ * [Macintosh Family] On the SE/30, this
+ * is the bit to flip screen buffers.
+ * 0=alternate, 1=main.
+ * on II,IIx,IIcx,IIci,IIfx this is a bit
+ * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
+ */
+#define VIA1A_vHeadSel 0x20 /* Head select for IWM.
+ * [CHRP] unused.
+ * [Macintosh Family] "Floppy disk
+ * state-control line SEL" on all but IIfx
+ */
+#define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx
+ * this bit enables the "Overlay" address
+ * map in the address decoders as it is on
+ * reset for mapping the ROM over the reset
+ * vector. 1=use overlay map.
+ * On the IIci,IIfx it is another bit of the
+ * CPU ID: 0=normal IIci, 1=IIci with parity
+ * feature or IIfx.
+ * [CHRP] En WaitReqA: Lets the WaitReq_L
+ * signal from port A of the SCC appear
+ * on the PA7 input pin (CHRP). Output.
+ * [MkLinux] "Drive Select"
+ * (with 0x20 being 'disk head select')
+ */
+#define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select:
+ * 1: select the external serial clock to
+ * drive the SCC's /RTxCA pin.
+ * 0: Select the 3.6864MHz clock to drive
+ * the SCC cell.
+ * [Macintosh Family] Correct on all but IIfx
+ */
+
+/* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
+ * on Macs which had the PWM sound hardware. Reserved on newer models.
+ * On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
+ * bit 2: 1=IIci, 0=IIfx
+ * bit 1: 1 on both IIci and IIfx.
+ * MkLinux sez bit 0 is 'burnin flag' in this case.
+ * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
+ * inputs, these bits will read 0.
+ */
+#define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */
+#define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */
+#define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */
+#define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */
+#define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */
+
+/* Info on VIA1B is from Macintosh Family Hardware & MkLinux.
+ * CHRP offers no info. */
+#define VIA1B_vSound 0x80 /* Sound enable (for compatibility with
+ * PWM hardware) 0=enabled.
+ * Also, on IIci w/parity, shows parity error
+ * 0=error, 1=OK. */
+#define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=enabled,1=disabled
+ * On SE/30, vertical sync interrupt enable.
+ * 0=enabled. This vSync interrupt shows up
+ * as a slot $E interrupt. */
+#define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */
+#define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */
+#define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/
+#define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */
+#define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
+#define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
+
+/* MkLinux defines the following "VIA1 Register B contents where they
+ * differ from standard VIA1". From the naming scheme, we assume they
+ * correspond to a VIA work-alike named 'EVR'. */
+#define EVRB_XCVR 0x08 /* XCVR_SESSION* */
+#define EVRB_FULL 0x10 /* VIA_FULL */
+#define EVRB_SYSES 0x20 /* SYS_SESSION */
+#define EVRB_AUXIE 0x00 /* Enable A/UX Interrupt Scheme */
+#define EVRB_AUXID 0x40 /* Disable A/UX Interrupt Scheme */
+#define EVRB_SFTWRIE 0x00 /* Software Interrupt ReQuest */
+#define EVRB_SFTWRID 0x80 /* Software Interrupt ReQuest */
+
+/*
+ * VIA2 A register is the interrupt lines raised off the nubus
+ * slots.
+ * The below info is from 'Macintosh Family Hardware.'
+ * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.'
+ * It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and
+ * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
+ * Perhaps OSS uses vRAM1 and vRAM2 for ADB.
+ */
+
+#define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */
+#define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */
+#define VIA2A_vIRQE 0x20 /* IRQ from slot $E */
+#define VIA2A_vIRQD 0x10 /* IRQ from slot $D */
+#define VIA2A_vIRQC 0x08 /* IRQ from slot $C */
+#define VIA2A_vIRQB 0x04 /* IRQ from slot $B */
+#define VIA2A_vIRQA 0x02 /* IRQ from slot $A */
+#define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */
+
+/* RAM size bits decoded as follows:
+ * bit1 bit0 size of ICs in bank A
+ * 0 0 256 kbit
+ * 0 1 1 Mbit
+ * 1 0 4 Mbit
+ * 1 1 16 Mbit
+ */
+
+/*
+ * Register B has the fun stuff in it
+ */
+
+#define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by
+ * timer T1.
+ * on IIci, parity test: 0=test mode.
+ * [MkLinux] RBV_PARODD: 1=odd,0=even. */
+#define VIA2B_vSndJck 0x40 /* External sound jack status.
+ * 0=plug is inserted. On SE/30, always 0 */
+#define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */
+#define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */
+#define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush
+ * on II, AMU/PMMU control.
+ * if AMU, 0=24bit to 32bit translation
+ * if PMMU, 1=PMMU is accessing page table.
+ * on SE/30 tied low.
+ * on IIx,IIcx,IIfx, unused.
+ * on IIci/RBV, cache control. 0=flush cache.
+ */
+#define VIA2B_vPower 0x04 /* Power off, 0=shut off power.
+ * on SE/30 this signal sent to PDS card. */
+#define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=locked.
+ * on SE/30 sent to PDS card. */
+#define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=disable cache card
+ * on others, 0=disable processor's instruction
+ * and data caches. */
+
+/* Apple sez: http://developer.apple.com/technotes/ov/ov_04.html
+ * Another example of a valid function that has no ROM support is the use
+ * of the alternate video page for page-flipping animation. Since there
+ * is no ROM call to flip pages, it is necessary to go play with the
+ * right bit in the VIA chip (6522 Versatile Interface Adapter).
+ * [CSA: don't know which one this is, but it's one of 'em!]
+ */
+
+/*
+ * 6522 registers - see databook.
+ * CSA: Assignments for VIA1 confirmed from CHRP spec.
+ */
+
+/* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */
+/* Note: 15 VIA regs, 8 RBV regs */
+
+#define vBufB 0x0000 /* [VIA/RBV] Register B */
+#define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
+#define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
+#define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
+#define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
+#define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
+#define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
+#define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
+#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
+#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
+#define vSR 0x1400 /* [VIA only] Shift register. */
+#define vACR 0x1600 /* [VIA only] Auxiliary control register. */
+#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
+ /* CHRP sez never ever to *write* this.
+ * Mac family says never to *change* this.
+ * In fact we need to initialize it once at start. */
+#define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */
+#define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */
+#define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */
+
+/* The RBV only decodes the bottom eight address lines; the VIA doesn't
+ * decode the bottom eight -- so vBufB | rBufB will always get you BufB */
+/* CSA: in fact, only bits 0,1, and 4 seem to be decoded.
+ * BUT note the values for rIER and rIFR, where the top 8 bits *do* seem
+ * to matter. In fact *all* of the top 8 bits seem to matter;
+ * setting rIER=0x1813 and rIFR=0x1803 doesn't work, either.
+ * Perhaps some sort of 'compatibility mode' is built-in? [21-May-1999]
+ */
+
+#define rBufB 0x0000 /* [VIA/RBV] Register B */
+#define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */
+#define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */
+#define rIFR 0x1a03 /* [VIA/RBV] RBV interrupt flag register. */
+#define rMonP 0x0010 /* [RBV only] RBV video monitor type. */
+#define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */
+#define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */
+#define rIER 0x1c13 /* [VIA/RBV] RBV interrupt flag enable register. */
+#define rBufA rSIFR /* the 'slot interrupts register' is BufA on a VIA */
+
+/*
+ * Video monitor parameters, for rMonP:
+ */
+#define RBV_DEPTH 0x07 /* bits per pixel: 000=1,001=2,010=4,011=8 */
+#define RBV_MONID 0x38 /* monitor type, as below. */
+#define RBV_VIDOFF 0x40 /* 1 turns off onboard video */
+/* Supported monitor types: */
+#define MON_15BW (1<<3) /* 15" BW portrait. */
+#define MON_IIGS (2<<3) /* 12" color (modified IIGS monitor). */
+#define MON_15RGB (5<<3) /* 15" RGB portrait. */
+#define MON_12OR13 (6<<3) /* 12" BW or 13" RGB. */
+#define MON_NONE (7<<3) /* No monitor attached. */
+
+/* To clarify IER manipulations */
+#define IER_SET_BIT(b) (0x80 | (1<<(b)) )
+#define IER_CLR_BIT(b) (0x7F & (1<<(b)) )
+
+#ifndef __ASSEMBLY__
+
+extern volatile __u8 *via1,*via2;
+extern int rbv_present,via_alt_mapping;
+
+struct irq_desc;
+
+extern void via_register_interrupts(void);
+extern void via_irq_enable(int);
+extern void via_irq_disable(int);
+extern void via_nubus_irq_startup(int irq);
+extern void via_nubus_irq_shutdown(int irq);
+extern void via1_irq(struct irq_desc *desc);
+extern void via1_set_head(int);
+extern int via2_scsi_drq_pending(void);
+
+static inline int rbv_set_video_bpp(int bpp)
+{
+ char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1;
+ if (!rbv_present || val<0) return -1;
+ via2[rMonP] = (via2[rMonP] & ~RBV_DEPTH) | val;
+ return 0;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_MAC_VIA_H_ */
diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h
new file mode 100644
index 0000000..49bd326
--- /dev/null
+++ b/arch/m68k/include/asm/machdep.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_MACHDEP_H
+#define _M68K_MACHDEP_H
+
+#include <linux/seq_file.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+
+struct pt_regs;
+struct mktime;
+struct rtc_time;
+struct rtc_pll_info;
+struct buffer_head;
+
+extern void (*mach_sched_init) (irq_handler_t handler);
+/* machine dependent irq functions */
+extern void (*mach_init_IRQ) (void);
+extern void (*mach_get_model) (char *model);
+extern void (*mach_get_hardware_list) (struct seq_file *m);
+/* machine dependent timer functions */
+extern int (*mach_hwclk)(int, struct rtc_time*);
+extern unsigned int (*mach_get_ss)(void);
+extern int (*mach_get_rtc_pll)(struct rtc_pll_info *);
+extern int (*mach_set_rtc_pll)(struct rtc_pll_info *);
+extern void (*mach_reset)( void );
+extern void (*mach_halt)( void );
+extern void (*mach_power_off)( void );
+extern unsigned long (*mach_hd_init) (unsigned long, unsigned long);
+extern void (*mach_hd_setup)(char *, int *);
+extern long mach_max_dma_address;
+extern void (*mach_heartbeat) (int);
+extern void (*mach_l2_flush) (int);
+extern void (*mach_beep) (unsigned int, unsigned int);
+
+/* Hardware clock functions */
+extern void hw_timer_init(irq_handler_t handler);
+extern unsigned long hw_timer_offset(void);
+
+extern void config_BSP(char *command, int len);
+
+#endif /* _M68K_MACHDEP_H */
diff --git a/arch/m68k/include/asm/machines.h b/arch/m68k/include/asm/machines.h
new file mode 100644
index 0000000..1332bad
--- /dev/null
+++ b/arch/m68k/include/asm/machines.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * machines.h: Defines for taking apart the machine type value in the
+ * idprom and determining the kind of machine we are on.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ * Sun3/3x models added by David Monro (davidm@psrg.cs.usyd.edu.au)
+ */
+#ifndef _SPARC_MACHINES_H
+#define _SPARC_MACHINES_H
+
+struct Sun_Machine_Models {
+ char *name;
+ unsigned char id_machtype;
+};
+
+/* Current number of machines we know about that has an IDPROM
+ * machtype entry including one entry for the 0x80 OBP machines.
+ */
+// reduced along with table in arch/m68k/sun3/idprom.c
+// sun3 port doesn't need to know about sparc machines.
+//#define NUM_SUN_MACHINES 23
+#define NUM_SUN_MACHINES 8
+
+/* The machine type in the idprom area looks like this:
+ *
+ * ---------------
+ * | ARCH | MACH |
+ * ---------------
+ * 7 4 3 0
+ *
+ * The ARCH field determines the architecture line (sun4, sun4c, etc).
+ * The MACH field determines the machine make within that architecture.
+ */
+
+#define SM_ARCH_MASK 0xf0
+#define SM_SUN3 0x10
+#define SM_SUN4 0x20
+#define SM_SUN3X 0x40
+#define SM_SUN4C 0x50
+#define SM_SUN4M 0x70
+#define SM_SUN4M_OBP 0x80
+
+#define SM_TYP_MASK 0x0f
+/* Sun3 machines */
+#define SM_3_160 0x01 /* Sun 3/160 series */
+#define SM_3_50 0x02 /* Sun 3/50 series */
+#define SM_3_260 0x03 /* Sun 3/260 series */
+#define SM_3_110 0x04 /* Sun 3/110 series */
+#define SM_3_60 0x07 /* Sun 3/60 series */
+#define SM_3_E 0x08 /* Sun 3/E series */
+
+/* Sun3x machines */
+#define SM_3_460 0x01 /* Sun 3/460 (460,470,480) series */
+#define SM_3_80 0x02 /* Sun 3/80 series */
+
+/* Sun4 machines */
+#define SM_4_260 0x01 /* Sun 4/200 series */
+#define SM_4_110 0x02 /* Sun 4/100 series */
+#define SM_4_330 0x03 /* Sun 4/300 series */
+#define SM_4_470 0x04 /* Sun 4/400 series */
+
+/* Sun4c machines Full Name - PROM NAME */
+#define SM_4C_SS1 0x01 /* Sun4c SparcStation 1 - Sun 4/60 */
+#define SM_4C_IPC 0x02 /* Sun4c SparcStation IPC - Sun 4/40 */
+#define SM_4C_SS1PLUS 0x03 /* Sun4c SparcStation 1+ - Sun 4/65 */
+#define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */
+#define SM_4C_SS2 0x05 /* Sun4c SparcStation 2 - Sun 4/75 */
+#define SM_4C_ELC 0x06 /* Sun4c SparcStation ELC - Sun 4/25 */
+#define SM_4C_IPX 0x07 /* Sun4c SparcStation IPX - Sun 4/50 */
+
+/* Sun4m machines, these predate the OpenBoot. These values only mean
+ * something if the value in the ARCH field is SM_SUN4M, if it is
+ * SM_SUN4M_OBP then you have the following situation:
+ * 1) You either have a sun4d, a sun4e, or a recently made sun4m.
+ * 2) You have to consult OpenBoot to determine which machine this is.
+ */
+#define SM_4M_SS60 0x01 /* Sun4m SparcSystem 600 */
+#define SM_4M_SS50 0x02 /* Sun4m SparcStation 10 */
+#define SM_4M_SS40 0x03 /* Sun4m SparcStation 5 */
+
+/* Sun4d machines -- N/A */
+/* Sun4e machines -- N/A */
+/* Sun4u machines -- N/A */
+
+#endif /* !(_SPARC_MACHINES_H) */
diff --git a/arch/m68k/include/asm/machw.h b/arch/m68k/include/asm/machw.h
new file mode 100644
index 0000000..a220951
--- /dev/null
+++ b/arch/m68k/include/asm/machw.h
@@ -0,0 +1,24 @@
+/*
+** linux/machw.h -- This header defines some macros and pointers for
+** the various Macintosh custom hardware registers.
+**
+** Copyright 1997 by Michael Schmitz
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+*/
+
+#ifndef _ASM_MACHW_H_
+#define _ASM_MACHW_H_
+
+/*
+ * head.S maps the videomem to VIDEOMEMBASE
+ */
+
+#define VIDEOMEMBASE 0xf0000000
+#define VIDEOMEMSIZE (4096*1024)
+#define VIDEOMEMMASK (-4096*1024)
+
+#endif /* linux/machw.h */
diff --git a/arch/m68k/include/asm/macintosh.h b/arch/m68k/include/asm/macintosh.h
new file mode 100644
index 0000000..08cee11
--- /dev/null
+++ b/arch/m68k/include/asm/macintosh.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACINTOSH_H
+#define __ASM_MACINTOSH_H
+
+#include <linux/seq_file.h>
+#include <linux/interrupt.h>
+
+#include <asm/bootinfo-mac.h>
+
+
+/*
+ * Apple Macintoshisms
+ */
+
+extern void mac_reset(void);
+extern void mac_poweroff(void);
+extern void mac_init_IRQ(void);
+
+extern void mac_irq_enable(struct irq_data *data);
+extern void mac_irq_disable(struct irq_data *data);
+
+/*
+ * Macintosh Table
+ */
+
+struct mac_model
+{
+ short ident;
+ char *name;
+ char adb_type;
+ char via_type;
+ char scsi_type;
+ char ide_type;
+ char scc_type;
+ char ether_type;
+ char expansion_type;
+ char floppy_type;
+};
+
+#define MAC_ADB_NONE 0
+#define MAC_ADB_II 1
+#define MAC_ADB_EGRET 2
+#define MAC_ADB_CUDA 3
+#define MAC_ADB_PB1 4
+#define MAC_ADB_PB2 5
+#define MAC_ADB_IOP 6
+
+#define MAC_VIA_II 1
+#define MAC_VIA_IICI 2
+#define MAC_VIA_QUADRA 3
+
+#define MAC_SCSI_NONE 0
+#define MAC_SCSI_OLD 1
+#define MAC_SCSI_QUADRA 2
+#define MAC_SCSI_QUADRA2 3
+#define MAC_SCSI_QUADRA3 4
+#define MAC_SCSI_IIFX 5
+#define MAC_SCSI_DUO 6
+#define MAC_SCSI_LC 7
+
+#define MAC_IDE_NONE 0
+#define MAC_IDE_QUADRA 1
+#define MAC_IDE_PB 2
+#define MAC_IDE_BABOON 3
+
+#define MAC_SCC_II 1
+#define MAC_SCC_IOP 2
+#define MAC_SCC_QUADRA 3
+#define MAC_SCC_PSC 4
+
+#define MAC_ETHER_NONE 0
+#define MAC_ETHER_SONIC 1
+#define MAC_ETHER_MACE 2
+
+#define MAC_EXP_NONE 0
+#define MAC_EXP_PDS 1 /* Accepts only a PDS card */
+#define MAC_EXP_NUBUS 2 /* Accepts only NuBus card(s) */
+#define MAC_EXP_PDS_NUBUS 3 /* Accepts PDS card and/or NuBus card(s) */
+#define MAC_EXP_PDS_COMM 4 /* Accepts PDS card or Comm Slot card */
+
+#define MAC_FLOPPY_IWM 0
+#define MAC_FLOPPY_SWIM_ADDR1 1
+#define MAC_FLOPPY_SWIM_ADDR2 2
+#define MAC_FLOPPY_SWIM_IOP 3
+#define MAC_FLOPPY_AV 4
+
+extern struct mac_model *macintosh_config;
+
+
+ /*
+ * Internal representation of the Mac hardware, filled in from bootinfo
+ */
+
+struct mac_booter_data
+{
+ unsigned long videoaddr;
+ unsigned long videorow;
+ unsigned long videodepth;
+ unsigned long dimensions;
+ unsigned long boottime;
+ unsigned long gmtbias;
+ unsigned long videological;
+ unsigned long sccbase;
+ unsigned long id;
+ unsigned long memsize;
+ unsigned long cpuid;
+ unsigned long rombase;
+};
+
+extern struct mac_booter_data mac_bi_data;
+
+#endif
diff --git a/arch/m68k/include/asm/macints.h b/arch/m68k/include/asm/macints.h
new file mode 100644
index 0000000..cddb2d3
--- /dev/null
+++ b/arch/m68k/include/asm/macints.h
@@ -0,0 +1,127 @@
+/*
+** macints.h -- Macintosh Linux interrupt handling structs and prototypes
+**
+** Copyright 1997 by Michael Schmitz
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+*/
+
+#ifndef _ASM_MACINTS_H_
+#define _ASM_MACINTS_H_
+
+#include <asm/irq.h>
+
+/*
+ * Base IRQ number for all Mac68K interrupt sources. Each source
+ * has eight indexes (base -> base+7).
+ */
+
+#define VIA1_SOURCE_BASE 8
+#define VIA2_SOURCE_BASE 16
+#define PSC3_SOURCE_BASE 24
+#define PSC4_SOURCE_BASE 32
+#define PSC5_SOURCE_BASE 40
+#define PSC6_SOURCE_BASE 48
+#define NUBUS_SOURCE_BASE 56
+#define BABOON_SOURCE_BASE 64
+
+/*
+ * Maximum IRQ number is BABOON_SOURCE_BASE + 7,
+ * giving us IRQs up through 71
+ */
+
+#define NUM_MAC_SOURCES 72
+
+/*
+ * clean way to separate IRQ into its source and index
+ */
+
+#define IRQ_SRC(irq) (irq >> 3)
+#define IRQ_IDX(irq) (irq & 7)
+
+/* VIA1 interrupts */
+#define IRQ_VIA1_0 (8) /* one second int. */
+#define IRQ_VIA1_1 (9) /* VBlank int. */
+#define IRQ_MAC_VBL IRQ_VIA1_1
+#define IRQ_VIA1_2 (10) /* ADB SR shifts complete */
+#define IRQ_MAC_ADB IRQ_VIA1_2
+#define IRQ_MAC_ADB_SR IRQ_VIA1_2
+#define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */
+#define IRQ_MAC_ADB_SD IRQ_VIA1_3
+#define IRQ_VIA1_4 (12) /* ADB SR ext. clock pulse */
+#define IRQ_MAC_ADB_CL IRQ_VIA1_4
+#define IRQ_VIA1_5 (13)
+#define IRQ_MAC_TIMER_2 IRQ_VIA1_5
+#define IRQ_VIA1_6 (14)
+#define IRQ_MAC_TIMER_1 IRQ_VIA1_6
+#define IRQ_VIA1_7 (15)
+
+/* VIA2/RBV interrupts */
+#define IRQ_VIA2_0 (16)
+#define IRQ_MAC_SCSIDRQ IRQ_VIA2_0
+#define IRQ_VIA2_1 (17)
+#define IRQ_MAC_NUBUS IRQ_VIA2_1
+#define IRQ_VIA2_2 (18)
+#define IRQ_VIA2_3 (19)
+#define IRQ_MAC_SCSI IRQ_VIA2_3
+#define IRQ_VIA2_4 (20)
+#define IRQ_VIA2_5 (21)
+#define IRQ_VIA2_6 (22)
+#define IRQ_VIA2_7 (23)
+
+/* Level 3 (PSC, AV Macs only) interrupts */
+#define IRQ_PSC3_0 (24)
+#define IRQ_MAC_MACE IRQ_PSC3_0
+#define IRQ_PSC3_1 (25)
+#define IRQ_PSC3_2 (26)
+#define IRQ_PSC3_3 (27)
+
+/* Level 4 (PSC, AV Macs only) interrupts */
+#define IRQ_PSC4_0 (32)
+#define IRQ_PSC4_1 (33)
+#define IRQ_MAC_SCC_A IRQ_PSC4_1
+#define IRQ_PSC4_2 (34)
+#define IRQ_MAC_SCC_B IRQ_PSC4_2
+#define IRQ_PSC4_3 (35)
+#define IRQ_MAC_MACE_DMA IRQ_PSC4_3
+
+/* OSS Level 4 interrupts */
+#define IRQ_MAC_SCC (33)
+
+/* Level 5 (PSC, AV Macs only) interrupts */
+#define IRQ_PSC5_0 (40)
+#define IRQ_PSC5_1 (41)
+#define IRQ_PSC5_2 (42)
+#define IRQ_PSC5_3 (43)
+
+/* Level 6 (PSC, AV Macs only) interrupts */
+#define IRQ_PSC6_0 (48)
+#define IRQ_PSC6_1 (49)
+#define IRQ_PSC6_2 (50)
+#define IRQ_PSC6_3 (51)
+
+/* Nubus interrupts (cascaded to VIA2) */
+#define IRQ_NUBUS_9 (56)
+#define IRQ_NUBUS_A (57)
+#define IRQ_NUBUS_B (58)
+#define IRQ_NUBUS_C (59)
+#define IRQ_NUBUS_D (60)
+#define IRQ_NUBUS_E (61)
+#define IRQ_NUBUS_F (62)
+
+/* Baboon interrupts (cascaded to nubus slot $C) */
+#define IRQ_BABOON_0 (64)
+#define IRQ_BABOON_1 (65)
+#define IRQ_BABOON_2 (66)
+#define IRQ_BABOON_3 (67)
+
+#define SLOT2IRQ(x) (x + 47)
+#define IRQ2SLOT(x) (x - 47)
+
+#define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */
+#define INT_TICKS 246 /* to make sched_time = 99.902... HZ */
+
+#endif /* asm/macints.h */
diff --git a/arch/m68k/include/asm/math-emu.h b/arch/m68k/include/asm/math-emu.h
new file mode 100644
index 0000000..eefaa3a
--- /dev/null
+++ b/arch/m68k/include/asm/math-emu.h
@@ -0,0 +1,316 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_SETUP_H
+#define _ASM_M68K_SETUP_H
+
+#include <asm/setup.h>
+#include <linux/linkage.h>
+
+/* Status Register bits */
+
+/* accrued exception bits */
+#define FPSR_AEXC_INEX 3
+#define FPSR_AEXC_DZ 4
+#define FPSR_AEXC_UNFL 5
+#define FPSR_AEXC_OVFL 6
+#define FPSR_AEXC_IOP 7
+
+/* exception status bits */
+#define FPSR_EXC_INEX1 8
+#define FPSR_EXC_INEX2 9
+#define FPSR_EXC_DZ 10
+#define FPSR_EXC_UNFL 11
+#define FPSR_EXC_OVFL 12
+#define FPSR_EXC_OPERR 13
+#define FPSR_EXC_SNAN 14
+#define FPSR_EXC_BSUN 15
+
+/* quotient byte, assumes big-endian, of course */
+#define FPSR_QUOTIENT(fpsr) (*((signed char *) &(fpsr) + 1))
+
+/* condition code bits */
+#define FPSR_CC_NAN 24
+#define FPSR_CC_INF 25
+#define FPSR_CC_Z 26
+#define FPSR_CC_NEG 27
+
+
+/* Control register bits */
+
+/* rounding mode */
+#define FPCR_ROUND_RN 0 /* round to nearest/even */
+#define FPCR_ROUND_RZ 1 /* round to zero */
+#define FPCR_ROUND_RM 2 /* minus infinity */
+#define FPCR_ROUND_RP 3 /* plus infinity */
+
+/* rounding precision */
+#define FPCR_PRECISION_X 0 /* long double */
+#define FPCR_PRECISION_S 1 /* double */
+#define FPCR_PRECISION_D 2 /* float */
+
+
+/* Flags to select the debugging output */
+#define PDECODE 0
+#define PEXECUTE 1
+#define PCONV 2
+#define PNORM 3
+#define PREGISTER 4
+#define PINSTR 5
+#define PUNIMPL 6
+#define PMOVEM 7
+
+#define PMDECODE (1<<PDECODE)
+#define PMEXECUTE (1<<PEXECUTE)
+#define PMCONV (1<<PCONV)
+#define PMNORM (1<<PNORM)
+#define PMREGISTER (1<<PREGISTER)
+#define PMINSTR (1<<PINSTR)
+#define PMUNIMPL (1<<PUNIMPL)
+#define PMMOVEM (1<<PMOVEM)
+
+#ifndef __ASSEMBLY__
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+union fp_mant64 {
+ unsigned long long m64;
+ unsigned long m32[2];
+};
+
+union fp_mant128 {
+ unsigned long long m64[2];
+ unsigned long m32[4];
+};
+
+/* internal representation of extended fp numbers */
+struct fp_ext {
+ unsigned char lowmant;
+ unsigned char sign;
+ unsigned short exp;
+ union fp_mant64 mant;
+};
+
+/* C representation of FPU registers */
+/* NOTE: if you change this, you have to change the assembler offsets
+ below and the size in <asm/fpu.h>, too */
+struct fp_data {
+ struct fp_ext fpreg[8];
+ unsigned int fpcr;
+ unsigned int fpsr;
+ unsigned int fpiar;
+ unsigned short prec;
+ unsigned short rnd;
+ struct fp_ext temp[2];
+};
+
+#ifdef FPU_EMU_DEBUG
+extern unsigned int fp_debugprint;
+
+#define dprint(bit, fmt, ...) ({ \
+ if (fp_debugprint & (1 << (bit))) \
+ pr_info(fmt, ##__VA_ARGS__); \
+})
+#else
+#define dprint(bit, fmt, ...) no_printk(fmt, ##__VA_ARGS__)
+#endif
+
+#define uprint(str) ({ \
+ static int __count = 3; \
+ \
+ if (__count > 0) { \
+ pr_err("You just hit an unimplemented " \
+ "fpu instruction (%s)\n", str); \
+ pr_err("Please report this to ....\n"); \
+ __count--; \
+ } \
+})
+
+#define FPDATA ((struct fp_data *)current->thread.fp)
+
+#else /* __ASSEMBLY__ */
+
+#define FPDATA %a2
+
+/* offsets from the base register to the floating point data in the task struct */
+#define FPD_FPREG (TASK_THREAD+THREAD_FPREG+0)
+#define FPD_FPCR (TASK_THREAD+THREAD_FPREG+96)
+#define FPD_FPSR (TASK_THREAD+THREAD_FPREG+100)
+#define FPD_FPIAR (TASK_THREAD+THREAD_FPREG+104)
+#define FPD_PREC (TASK_THREAD+THREAD_FPREG+108)
+#define FPD_RND (TASK_THREAD+THREAD_FPREG+110)
+#define FPD_TEMPFP1 (TASK_THREAD+THREAD_FPREG+112)
+#define FPD_TEMPFP2 (TASK_THREAD+THREAD_FPREG+124)
+#define FPD_SIZEOF (TASK_THREAD+THREAD_FPREG+136)
+
+/* offsets on the stack to access saved registers,
+ * these are only used during instruction decoding
+ * where we always know how deep we're on the stack.
+ */
+#define FPS_DO (PT_OFF_D0)
+#define FPS_D1 (PT_OFF_D1)
+#define FPS_D2 (PT_OFF_D2)
+#define FPS_A0 (PT_OFF_A0)
+#define FPS_A1 (PT_OFF_A1)
+#define FPS_A2 (PT_OFF_A2)
+#define FPS_SR (PT_OFF_SR)
+#define FPS_PC (PT_OFF_PC)
+#define FPS_EA (PT_OFF_PC+6)
+#define FPS_PC2 (PT_OFF_PC+10)
+
+.macro fp_get_fp_reg
+ lea (FPD_FPREG,FPDATA,%d0.w*4),%a0
+ lea (%a0,%d0.w*8),%a0
+.endm
+
+/* Macros used to get/put the current program counter.
+ * 020/030 use a different stack frame then 040/060, for the
+ * 040/060 the return pc points already to the next location,
+ * so this only needs to be modified for jump instructions.
+ */
+.macro fp_get_pc dest
+ move.l (FPS_PC+4,%sp),\dest
+.endm
+
+.macro fp_put_pc src,jump=0
+ move.l \src,(FPS_PC+4,%sp)
+.endm
+
+.macro fp_get_instr_data f,s,dest,label
+ getuser \f,%sp@(FPS_PC+4)@(0),\dest,\label,%sp@(FPS_PC+4)
+ addq.l #\s,%sp@(FPS_PC+4)
+.endm
+
+.macro fp_get_instr_word dest,label,addr
+ fp_get_instr_data w,2,\dest,\label,\addr
+.endm
+
+.macro fp_get_instr_long dest,label,addr
+ fp_get_instr_data l,4,\dest,\label,\addr
+.endm
+
+/* These macros are used to read from/write to user space
+ * on error we jump to the fixup section, load the fault
+ * address into %a0 and jump to the exit.
+ * (derived from <asm/uaccess.h>)
+ */
+.macro getuser size,src,dest,label,addr
+| printf ,"[\size<%08x]",1,\addr
+.Lu1\@: moves\size \src,\dest
+
+ .section .fixup,"ax"
+ .even
+.Lu2\@: move.l \addr,%a0
+ jra \label
+ .previous
+
+ .section __ex_table,"a"
+ .align 4
+ .long .Lu1\@,.Lu2\@
+ .previous
+.endm
+
+.macro putuser size,src,dest,label,addr
+| printf ,"[\size>%08x]",1,\addr
+.Lu1\@: moves\size \src,\dest
+.Lu2\@:
+
+ .section .fixup,"ax"
+ .even
+.Lu3\@: move.l \addr,%a0
+ jra \label
+ .previous
+
+ .section __ex_table,"a"
+ .align 4
+ .long .Lu1\@,.Lu3\@
+ .long .Lu2\@,.Lu3\@
+ .previous
+.endm
+
+/* work around binutils idiocy */
+old_gas=-1
+.irp gas_ident.x .x
+old_gas=old_gas+1
+.endr
+.if !old_gas
+.irp m b,w,l
+.macro getuser.\m src,dest,label,addr
+ getuser .\m,\src,\dest,\label,\addr
+.endm
+.macro putuser.\m src,dest,label,addr
+ putuser .\m,\src,\dest,\label,\addr
+.endm
+.endr
+.endif
+
+.macro movestack nr,arg1,arg2,arg3,arg4,arg5
+ .if \nr
+ movestack (\nr-1),\arg2,\arg3,\arg4,\arg5
+ move.l \arg1,-(%sp)
+ .endif
+.endm
+
+.macro printf bit=-1,string,nr=0,arg1,arg2,arg3,arg4,arg5
+#ifdef FPU_EMU_DEBUG
+ .data
+.Lpdata\@:
+ .string "\string"
+ .previous
+
+ movem.l %d0/%d1/%a0/%a1,-(%sp)
+ .if \bit+1
+#if 0
+ moveq #\bit,%d0
+ andw #7,%d0
+ btst %d0,fp_debugprint+((31-\bit)/8)
+#else
+ btst #\bit,fp_debugprint+((31-\bit)/8)
+#endif
+ jeq .Lpskip\@
+ .endif
+ movestack \nr,\arg1,\arg2,\arg3,\arg4,\arg5
+ pea .Lpdata\@
+ jsr printk
+ lea ((\nr+1)*4,%sp),%sp
+.Lpskip\@:
+ movem.l (%sp)+,%d0/%d1/%a0/%a1
+#endif
+.endm
+
+.macro printx bit,fp
+#ifdef FPU_EMU_DEBUG
+ movem.l %d0/%a0,-(%sp)
+ lea \fp,%a0
+#if 0
+ moveq #'+',%d0
+ tst.w (%a0)
+ jeq .Lx1\@
+ moveq #'-',%d0
+.Lx1\@: printf \bit," %c",1,%d0
+ move.l (4,%a0),%d0
+ bclr #31,%d0
+ jne .Lx2\@
+ printf \bit,"0."
+ jra .Lx3\@
+.Lx2\@: printf \bit,"1."
+.Lx3\@: printf \bit,"%08x%08x",2,%d0,%a0@(8)
+ move.w (2,%a0),%d0
+ ext.l %d0
+ printf \bit,"E%04x",1,%d0
+#else
+ printf \bit," %08x%08x%08x",3,%a0@,%a0@(4),%a0@(8)
+#endif
+ movem.l (%sp)+,%d0/%a0
+#endif
+.endm
+
+.macro debug instr,args
+#ifdef FPU_EMU_DEBUG
+ \instr \args
+#endif
+.endm
+
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_M68K_SETUP_H */
diff --git a/arch/m68k/include/asm/mc146818rtc.h b/arch/m68k/include/asm/mc146818rtc.h
new file mode 100644
index 0000000..6e9f319
--- /dev/null
+++ b/arch/m68k/include/asm/mc146818rtc.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef _ASM_MC146818RTC_H
+#define _ASM_MC146818RTC_H
+
+
+#ifdef CONFIG_ATARI
+/* RTC in Atari machines */
+
+#include <asm/atarihw.h>
+
+#define ATARI_RTC_PORT(x) (TT_RTC_BAS + 2*(x))
+#define RTC_ALWAYS_BCD 0
+
+#define CMOS_READ(addr) ({ \
+atari_outb_p((addr), ATARI_RTC_PORT(0)); \
+atari_inb_p(ATARI_RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+atari_outb_p((addr), ATARI_RTC_PORT(0)); \
+atari_outb_p((val), ATARI_RTC_PORT(1)); \
+})
+#endif /* CONFIG_ATARI */
+
+#endif /* _ASM_MC146818RTC_H */
diff --git a/arch/m68k/include/asm/mcf8390.h b/arch/m68k/include/asm/mcf8390.h
new file mode 100644
index 0000000..412360e
--- /dev/null
+++ b/arch/m68k/include/asm/mcf8390.h
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * mcf8390.h -- NS8390 support for ColdFire eval boards.
+ *
+ * (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo (www.lineo.com)
+ * (C) Copyright 2001, SnapGear (www.snapgear.com)
+ *
+ * 19990409 David W. Miller Converted from m5206ne.h for 5307 eval board
+ *
+ * Hacked support for m5206e Cadre III evaluation board
+ * Fred Stevens (fred.stevens@pemstar.com) 13 April 1999
+ */
+
+/****************************************************************************/
+#ifndef mcf8390_h
+#define mcf8390_h
+/****************************************************************************/
+
+
+/*
+ * Support for NE2000 clones devices in ColdFire based boards.
+ * Not all boards address these parts the same way, some use a
+ * direct addressing method, others use a side-band address space
+ * to access odd address registers, some require byte swapping
+ * others do not.
+ */
+#define BSWAP(w) (((w) << 8) | ((w) >> 8))
+#define RSWAP(w) (w)
+
+
+/*
+ * Define the basic hardware resources of NE2000 boards.
+ */
+
+#if defined(CONFIG_ARN5206)
+#define NE2000_ADDR 0x40000300
+#define NE2000_ODDOFFSET 0x00010000
+#define NE2000_ADDRSIZE 0x00020000
+#define NE2000_IRQ_VECTOR 0xf0
+#define NE2000_IRQ_PRIORITY 2
+#define NE2000_IRQ_LEVEL 4
+#define NE2000_BYTE volatile unsigned short
+#endif
+
+#if defined(CONFIG_M5206eC3)
+#define NE2000_ADDR 0x40000300
+#define NE2000_ODDOFFSET 0x00010000
+#define NE2000_ADDRSIZE 0x00020000
+#define NE2000_IRQ_VECTOR 0x1c
+#define NE2000_IRQ_PRIORITY 2
+#define NE2000_IRQ_LEVEL 4
+#define NE2000_BYTE volatile unsigned short
+#endif
+
+#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
+#define NE2000_ADDR 0x30000300
+#define NE2000_ADDRSIZE 0x00001000
+#define NE2000_IRQ_VECTOR 25
+#define NE2000_IRQ_PRIORITY 1
+#define NE2000_IRQ_LEVEL 3
+#define NE2000_BYTE volatile unsigned char
+#endif
+
+#if defined(CONFIG_M5307C3)
+#define NE2000_ADDR 0x40000300
+#define NE2000_ODDOFFSET 0x00010000
+#define NE2000_ADDRSIZE 0x00020000
+#define NE2000_IRQ_VECTOR 0x1b
+#define NE2000_BYTE volatile unsigned short
+#endif
+
+#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
+#define NE2000_ADDR 0x30600300
+#define NE2000_ODDOFFSET 0x00008000
+#define NE2000_ADDRSIZE 0x00010000
+#define NE2000_IRQ_VECTOR 67
+#undef BSWAP
+#define BSWAP(w) (w)
+#define NE2000_BYTE volatile unsigned short
+#undef RSWAP
+#define RSWAP(w) (((w) << 8) | ((w) >> 8))
+#endif
+
+#if defined(CONFIG_M5307) && defined(CONFIG_NETtel)
+#define NE2000_ADDR0 0x30600300
+#define NE2000_ADDR1 0x30800300
+#define NE2000_ODDOFFSET 0x00008000
+#define NE2000_ADDRSIZE 0x00010000
+#define NE2000_IRQ_VECTOR0 27
+#define NE2000_IRQ_VECTOR1 29
+#undef BSWAP
+#define BSWAP(w) (w)
+#define NE2000_BYTE volatile unsigned short
+#undef RSWAP
+#define RSWAP(w) (((w) << 8) | ((w) >> 8))
+#endif
+
+#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3)
+#define NE2000_ADDR 0x30600300
+#define NE2000_ODDOFFSET 0x00008000
+#define NE2000_ADDRSIZE 0x00010000
+#define NE2000_IRQ_VECTOR 27
+#undef BSWAP
+#define BSWAP(w) (w)
+#define NE2000_BYTE volatile unsigned short
+#undef RSWAP
+#define RSWAP(w) (((w) << 8) | ((w) >> 8))
+#endif
+
+#if defined(CONFIG_ARN5307)
+#define NE2000_ADDR 0xfe600300
+#define NE2000_ODDOFFSET 0x00010000
+#define NE2000_ADDRSIZE 0x00020000
+#define NE2000_IRQ_VECTOR 0x1b
+#define NE2000_IRQ_PRIORITY 2
+#define NE2000_IRQ_LEVEL 3
+#define NE2000_BYTE volatile unsigned short
+#endif
+
+#if defined(CONFIG_M5407C3)
+#define NE2000_ADDR 0x40000300
+#define NE2000_ODDOFFSET 0x00010000
+#define NE2000_ADDRSIZE 0x00020000
+#define NE2000_IRQ_VECTOR 0x1b
+#define NE2000_BYTE volatile unsigned short
+#endif
+
+/****************************************************************************/
+#endif /* mcf8390_h */
diff --git a/arch/m68k/include/asm/mcf_pgalloc.h b/arch/m68k/include/asm/mcf_pgalloc.h
new file mode 100644
index 0000000..12fe700
--- /dev/null
+++ b/arch/m68k/include/asm/mcf_pgalloc.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef M68K_MCF_PGALLOC_H
+#define M68K_MCF_PGALLOC_H
+
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+
+extern inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+ free_page((unsigned long) pte);
+}
+
+extern const char bad_pmd_string[];
+
+extern inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+ unsigned long address)
+{
+ unsigned long page = __get_free_page(GFP_DMA);
+
+ if (!page)
+ return NULL;
+
+ memset((void *)page, 0, PAGE_SIZE);
+ return (pte_t *) (page);
+}
+
+extern inline pmd_t *pmd_alloc_kernel(pgd_t *pgd, unsigned long address)
+{
+ return (pmd_t *) pgd;
+}
+
+#define pmd_alloc_one_fast(mm, address) ({ BUG(); ((pmd_t *)1); })
+#define pmd_alloc_one(mm, address) ({ BUG(); ((pmd_t *)2); })
+
+#define pte_alloc_one_fast(mm, addr) pte_alloc_one(mm, addr)
+
+#define pmd_populate(mm, pmd, page) (pmd_val(*pmd) = \
+ (unsigned long)(page_address(page)))
+
+#define pmd_populate_kernel(mm, pmd, pte) (pmd_val(*pmd) = (unsigned long)(pte))
+
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t page,
+ unsigned long address)
+{
+ pgtable_page_dtor(page);
+ __free_page(page);
+}
+
+#define __pmd_free_tlb(tlb, pmd, address) do { } while (0)
+
+static inline struct page *pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
+{
+ struct page *page = alloc_pages(GFP_DMA, 0);
+ pte_t *pte;
+
+ if (!page)
+ return NULL;
+ if (!pgtable_page_ctor(page)) {
+ __free_page(page);
+ return NULL;
+ }
+
+ pte = kmap(page);
+ if (pte) {
+ clear_page(pte);
+ __flush_page_to_ram(pte);
+ flush_tlb_kernel_page(pte);
+ nocache_page(pte);
+ }
+ kunmap(page);
+
+ return page;
+}
+
+static inline void pte_free(struct mm_struct *mm, struct page *page)
+{
+ pgtable_page_dtor(page);
+ __free_page(page);
+}
+
+/*
+ * In our implementation, each pgd entry contains 1 pmd that is never allocated
+ * or freed. pgd_present is always 1, so this should never be called. -NL
+ */
+#define pmd_free(mm, pmd) BUG()
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+ free_page((unsigned long) pgd);
+}
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+ pgd_t *new_pgd;
+
+ new_pgd = (pgd_t *)__get_free_page(GFP_DMA | __GFP_NOWARN);
+ if (!new_pgd)
+ return NULL;
+ memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE);
+ memset(new_pgd, 0, PAGE_OFFSET >> PGDIR_SHIFT);
+ return new_pgd;
+}
+
+#define pgd_populate(mm, pmd, pte) BUG()
+
+#endif /* M68K_MCF_PGALLOC_H */
diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h
new file mode 100644
index 0000000..5d5502c
--- /dev/null
+++ b/arch/m68k/include/asm/mcf_pgtable.h
@@ -0,0 +1,408 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MCF_PGTABLE_H
+#define _MCF_PGTABLE_H
+
+#include <asm/mcfmmu.h>
+#include <asm/page.h>
+
+/*
+ * MMUDR bits, in proper place. We write these directly into the MMUDR
+ * after masking from the pte.
+ */
+#define CF_PAGE_LOCKED MMUDR_LK /* 0x00000002 */
+#define CF_PAGE_EXEC MMUDR_X /* 0x00000004 */
+#define CF_PAGE_WRITABLE MMUDR_W /* 0x00000008 */
+#define CF_PAGE_READABLE MMUDR_R /* 0x00000010 */
+#define CF_PAGE_SYSTEM MMUDR_SP /* 0x00000020 */
+#define CF_PAGE_COPYBACK MMUDR_CM_CCB /* 0x00000040 */
+#define CF_PAGE_NOCACHE MMUDR_CM_NCP /* 0x00000080 */
+
+#define CF_CACHEMASK (~MMUDR_CM_CCB)
+#define CF_PAGE_MMUDR_MASK 0x000000fe
+
+#define _PAGE_NOCACHE030 CF_PAGE_NOCACHE
+
+/*
+ * MMUTR bits, need shifting down.
+ */
+#define CF_PAGE_MMUTR_MASK 0x00000c00
+#define CF_PAGE_MMUTR_SHIFT 10
+
+#define CF_PAGE_VALID (MMUTR_V << CF_PAGE_MMUTR_SHIFT)
+#define CF_PAGE_SHARED (MMUTR_SG << CF_PAGE_MMUTR_SHIFT)
+
+/*
+ * Fake bits, not implemented in CF, will get masked out before
+ * hitting hardware.
+ */
+#define CF_PAGE_DIRTY 0x00000001
+#define CF_PAGE_ACCESSED 0x00001000
+
+#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */
+#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */
+#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */
+#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */
+#define _DESCTYPE_MASK 0x003
+#define _CACHEMASK040 (~0x060)
+#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
+
+/*
+ * Externally used page protection values.
+ */
+#define _PAGE_PRESENT (CF_PAGE_VALID)
+#define _PAGE_ACCESSED (CF_PAGE_ACCESSED)
+#define _PAGE_DIRTY (CF_PAGE_DIRTY)
+#define _PAGE_READWRITE (CF_PAGE_READABLE \
+ | CF_PAGE_WRITABLE \
+ | CF_PAGE_SYSTEM \
+ | CF_PAGE_SHARED)
+
+/*
+ * Compound page protection values.
+ */
+#define PAGE_NONE __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED)
+
+#define PAGE_SHARED __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_SHARED)
+
+#define PAGE_INIT __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_READABLE \
+ | CF_PAGE_WRITABLE \
+ | CF_PAGE_EXEC \
+ | CF_PAGE_SYSTEM)
+
+#define PAGE_KERNEL __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_READABLE \
+ | CF_PAGE_WRITABLE \
+ | CF_PAGE_EXEC \
+ | CF_PAGE_SYSTEM \
+ | CF_PAGE_SHARED)
+
+#define PAGE_COPY __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_READABLE \
+ | CF_PAGE_DIRTY)
+
+/*
+ * Page protections for initialising protection_map. See mm/mmap.c
+ * for use. In general, the bit positions are xwr, and P-items are
+ * private, the S-items are shared.
+ */
+#define __P000 PAGE_NONE
+#define __P001 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_READABLE)
+#define __P010 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_WRITABLE)
+#define __P011 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_READABLE \
+ | CF_PAGE_WRITABLE)
+#define __P100 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_EXEC)
+#define __P101 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_READABLE \
+ | CF_PAGE_EXEC)
+#define __P110 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_WRITABLE \
+ | CF_PAGE_EXEC)
+#define __P111 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_READABLE \
+ | CF_PAGE_WRITABLE \
+ | CF_PAGE_EXEC)
+
+#define __S000 PAGE_NONE
+#define __S001 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_READABLE)
+#define __S010 PAGE_SHARED
+#define __S011 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_SHARED \
+ | CF_PAGE_READABLE)
+#define __S100 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_EXEC)
+#define __S101 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_READABLE \
+ | CF_PAGE_EXEC)
+#define __S110 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_SHARED \
+ | CF_PAGE_EXEC)
+#define __S111 __pgprot(CF_PAGE_VALID \
+ | CF_PAGE_ACCESSED \
+ | CF_PAGE_SHARED \
+ | CF_PAGE_READABLE \
+ | CF_PAGE_EXEC)
+
+#define PTE_MASK PAGE_MASK
+#define CF_PAGE_CHG_MASK (PTE_MASK | CF_PAGE_ACCESSED | CF_PAGE_DIRTY)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+ pte_val(pte) = (pte_val(pte) & CF_PAGE_CHG_MASK) | pgprot_val(newprot);
+ return pte;
+}
+
+#define pmd_set(pmdp, ptep) do {} while (0)
+
+static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp)
+{
+ pgd_val(*pgdp) = virt_to_phys(pmdp);
+}
+
+#define __pte_page(pte) ((unsigned long) (pte_val(pte) & PAGE_MASK))
+#define __pmd_page(pmd) ((unsigned long) (pmd_val(pmd)))
+
+static inline int pte_none(pte_t pte)
+{
+ return !pte_val(pte);
+}
+
+static inline int pte_present(pte_t pte)
+{
+ return pte_val(pte) & CF_PAGE_VALID;
+}
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep)
+{
+ pte_val(*ptep) = 0;
+}
+
+#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
+#define pte_page(pte) virt_to_page(__pte_page(pte))
+
+static inline int pmd_none2(pmd_t *pmd) { return !pmd_val(*pmd); }
+#define pmd_none(pmd) pmd_none2(&(pmd))
+static inline int pmd_bad2(pmd_t *pmd) { return 0; }
+#define pmd_bad(pmd) pmd_bad2(&(pmd))
+#define pmd_present(pmd) (!pmd_none2(&(pmd)))
+static inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = 0; }
+
+static inline int pgd_none(pgd_t pgd) { return 0; }
+static inline int pgd_bad(pgd_t pgd) { return 0; }
+static inline int pgd_present(pgd_t pgd) { return 1; }
+static inline void pgd_clear(pgd_t *pgdp) {}
+
+#define pte_ERROR(e) \
+ printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \
+ __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+ printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \
+ __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+ printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
+ __FILE__, __LINE__, pgd_val(e))
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not...
+ * [we have the full set here even if they don't change from m68k]
+ */
+static inline int pte_read(pte_t pte)
+{
+ return pte_val(pte) & CF_PAGE_READABLE;
+}
+
+static inline int pte_write(pte_t pte)
+{
+ return pte_val(pte) & CF_PAGE_WRITABLE;
+}
+
+static inline int pte_exec(pte_t pte)
+{
+ return pte_val(pte) & CF_PAGE_EXEC;
+}
+
+static inline int pte_dirty(pte_t pte)
+{
+ return pte_val(pte) & CF_PAGE_DIRTY;
+}
+
+static inline int pte_young(pte_t pte)
+{
+ return pte_val(pte) & CF_PAGE_ACCESSED;
+}
+
+static inline int pte_special(pte_t pte)
+{
+ return 0;
+}
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+ pte_val(pte) &= ~CF_PAGE_WRITABLE;
+ return pte;
+}
+
+static inline pte_t pte_rdprotect(pte_t pte)
+{
+ pte_val(pte) &= ~CF_PAGE_READABLE;
+ return pte;
+}
+
+static inline pte_t pte_exprotect(pte_t pte)
+{
+ pte_val(pte) &= ~CF_PAGE_EXEC;
+ return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+ pte_val(pte) &= ~CF_PAGE_DIRTY;
+ return pte;
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+ pte_val(pte) &= ~CF_PAGE_ACCESSED;
+ return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+ pte_val(pte) |= CF_PAGE_WRITABLE;
+ return pte;
+}
+
+static inline pte_t pte_mkread(pte_t pte)
+{
+ pte_val(pte) |= CF_PAGE_READABLE;
+ return pte;
+}
+
+static inline pte_t pte_mkexec(pte_t pte)
+{
+ pte_val(pte) |= CF_PAGE_EXEC;
+ return pte;
+}
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+ pte_val(pte) |= CF_PAGE_DIRTY;
+ return pte;
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+ pte_val(pte) |= CF_PAGE_ACCESSED;
+ return pte;
+}
+
+static inline pte_t pte_mknocache(pte_t pte)
+{
+ pte_val(pte) |= 0x80 | (pte_val(pte) & ~0x40);
+ return pte;
+}
+
+static inline pte_t pte_mkcache(pte_t pte)
+{
+ pte_val(pte) &= ~CF_PAGE_NOCACHE;
+ return pte;
+}
+
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+ return pte;
+}
+
+#define swapper_pg_dir kernel_pg_dir
+extern pgd_t kernel_pg_dir[PTRS_PER_PGD];
+
+/*
+ * Find an entry in a pagetable directory.
+ */
+#define pgd_index(address) ((address) >> PGDIR_SHIFT)
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+
+/*
+ * Find an entry in a kernel pagetable directory.
+ */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/*
+ * Find an entry in the second-level pagetable.
+ */
+static inline pmd_t *pmd_offset(pgd_t *pgd, unsigned long address)
+{
+ return (pmd_t *) pgd;
+}
+
+/*
+ * Find an entry in the third-level pagetable.
+ */
+#define __pte_offset(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir, address) \
+ ((pte_t *) __pmd_page(*(dir)) + __pte_offset(address))
+
+/*
+ * Disable caching for page at given kernel virtual address.
+ */
+static inline void nocache_page(void *vaddr)
+{
+ pgd_t *dir;
+ pmd_t *pmdp;
+ pte_t *ptep;
+ unsigned long addr = (unsigned long) vaddr;
+
+ dir = pgd_offset_k(addr);
+ pmdp = pmd_offset(dir, addr);
+ ptep = pte_offset_kernel(pmdp, addr);
+ *ptep = pte_mknocache(*ptep);
+}
+
+/*
+ * Enable caching for page at given kernel virtual address.
+ */
+static inline void cache_page(void *vaddr)
+{
+ pgd_t *dir;
+ pmd_t *pmdp;
+ pte_t *ptep;
+ unsigned long addr = (unsigned long) vaddr;
+
+ dir = pgd_offset_k(addr);
+ pmdp = pmd_offset(dir, addr);
+ ptep = pte_offset_kernel(pmdp, addr);
+ *ptep = pte_mkcache(*ptep);
+}
+
+/*
+ * Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e))
+ */
+#define __swp_type(x) ((x).val & 0xFF)
+#define __swp_offset(x) ((x).val >> 11)
+#define __swp_entry(typ, off) ((swp_entry_t) { (typ) | \
+ (off << 11) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x) (__pte((x).val))
+
+#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
+
+#define pte_offset_map(pmdp, addr) ((pte_t *)__pmd_page(*pmdp) + \
+ __pte_offset(addr))
+#define pte_unmap(pte) ((void) 0)
+#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _MCF_PGTABLE_H */
diff --git a/arch/m68k/include/asm/mcfclk.h b/arch/m68k/include/asm/mcfclk.h
new file mode 100644
index 0000000..0aca504
--- /dev/null
+++ b/arch/m68k/include/asm/mcfclk.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mcfclk.h -- coldfire specific clock structure
+ */
+
+
+#ifndef mcfclk_h
+#define mcfclk_h
+
+struct clk;
+
+struct clk_ops {
+ void (*enable)(struct clk *);
+ void (*disable)(struct clk *);
+};
+
+struct clk {
+ const char *name;
+ struct clk_ops *clk_ops;
+ unsigned long rate;
+ unsigned long enabled;
+ u8 slot;
+};
+
+extern struct clk *mcf_clks[];
+
+#ifdef MCFPM_PPMCR0
+extern struct clk_ops clk_ops0;
+#ifdef MCFPM_PPMCR1
+extern struct clk_ops clk_ops1;
+#endif /* MCFPM_PPMCR1 */
+
+#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
+static struct clk __clk_##clk_bank##_##clk_slot = { \
+ .name = clk_name, \
+ .clk_ops = &clk_ops##clk_bank, \
+ .rate = clk_rate, \
+ .slot = clk_slot, \
+}
+
+void __clk_init_enabled(struct clk *);
+void __clk_init_disabled(struct clk *);
+#else
+#define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
+ static struct clk clk_##clk_ref = { \
+ .name = clk_name, \
+ .rate = clk_rate, \
+ }
+#endif /* MCFPM_PPMCR0 */
+
+#endif /* mcfclk_h */
diff --git a/arch/m68k/include/asm/mcfdma.h b/arch/m68k/include/asm/mcfdma.h
new file mode 100644
index 0000000..6227317
--- /dev/null
+++ b/arch/m68k/include/asm/mcfdma.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * mcfdma.h -- Coldfire internal DMA support defines.
+ *
+ * (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org)
+ */
+
+/****************************************************************************/
+#ifndef mcfdma_h
+#define mcfdma_h
+/****************************************************************************/
+
+#if !defined(CONFIG_M5272)
+
+/*
+ * Define the DMA register set addresses.
+ * Note: these are longword registers, use unsigned long as data type
+ */
+#define MCFDMA_SAR 0x00 /* DMA source address (r/w) */
+#define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */
+/* these are word registers, use unsigned short data type */
+#define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */
+#define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */
+/* these are byte registers, use unsiged char data type */
+#define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */
+#define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */
+
+/*
+ * Bit definitions for the DMA Control Register (DCR).
+ */
+#define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */
+#define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */
+#define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */
+#define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */
+#define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */
+#define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */
+#define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */
+#define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */
+#define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */
+#define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */
+#define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */
+#define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */
+#define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */
+#define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */
+#define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */
+#define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */
+#define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */
+#define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */
+#define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */
+#define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */
+#define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */
+#define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */
+#define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */
+#define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */
+#define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */
+#define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */
+#define MCFDMA_DCR_START 0x0001 /* Start transfer */
+
+/*
+ * Bit definitions for the DMA Status Register (DSR).
+ */
+#define MCFDMA_DSR_CE 0x40 /* Config error */
+#define MCFDMA_DSR_BES 0x20 /* Bus Error on source */
+#define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */
+#define MCFDMA_DSR_REQ 0x04 /* Requests remaining */
+#define MCFDMA_DSR_BSY 0x02 /* Busy */
+#define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */
+
+#else /* This is an MCF5272 */
+
+#define MCFDMA_DMR 0x00 /* Mode Register (r/w) */
+#define MCFDMA_DIR 0x03 /* Interrupt trigger register (r/w) */
+#define MCFDMA_DSAR 0x03 /* Source Address register (r/w) */
+#define MCFDMA_DDAR 0x04 /* Destination Address register (r/w) */
+#define MCFDMA_DBCR 0x02 /* Byte Count Register (r/w) */
+
+/* Bit definitions for the DMA Mode Register (DMR) */
+#define MCFDMA_DMR_RESET 0x80000000L /* Reset bit */
+#define MCFDMA_DMR_EN 0x40000000L /* DMA enable */
+#define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */
+#define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */
+#define MCFDMA_DMR_DSTM 0x00002000L /* Destination addressing mask */
+#define MCFDMA_DMR_DSTM_SA 0x00000000L /* Destination uses static addressing */
+#define MCFDMA_DMR_DSTM_IA 0x00002000L /* Destination uses incremental addressing */
+#define MCFDMA_DMR_DSTT_UD 0x00000400L /* Destination is user data */
+#define MCFDMA_DMR_DSTT_UC 0x00000800L /* Destination is user code */
+#define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */
+#define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */
+#define MCFDMA_DMR_DSTS_OFF 0x8 /* offset to the destination size bits */
+#define MCFDMA_DMR_DSTS_LONG 0x00000000L /* Long destination size */
+#define MCFDMA_DMR_DSTS_BYTE 0x00000100L /* Byte destination size */
+#define MCFDMA_DMR_DSTS_WORD 0x00000200L /* Word destination size */
+#define MCFDMA_DMR_DSTS_LINE 0x00000300L /* Line destination size */
+#define MCFDMA_DMR_SRCM 0x00000020L /* Source addressing mask */
+#define MCFDMA_DMR_SRCM_SA 0x00000000L /* Source uses static addressing */
+#define MCFDMA_DMR_SRCM_IA 0x00000020L /* Source uses incremental addressing */
+#define MCFDMA_DMR_SRCT_UD 0x00000004L /* Source is user data */
+#define MCFDMA_DMR_SRCT_UC 0x00000008L /* Source is user code */
+#define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */
+#define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */
+#define MCFDMA_DMR_SRCS_OFF 0x0 /* Offset to the source size bits */
+#define MCFDMA_DMR_SRCS_LONG 0x00000000L /* Long source size */
+#define MCFDMA_DMR_SRCS_BYTE 0x00000001L /* Byte source size */
+#define MCFDMA_DMR_SRCS_WORD 0x00000002L /* Word source size */
+#define MCFDMA_DMR_SRCS_LINE 0x00000003L /* Line source size */
+
+/* Bit definitions for the DMA interrupt register (DIR) */
+#define MCFDMA_DIR_INVEN 0x1000 /* Invalid Combination interrupt enable */
+#define MCFDMA_DIR_ASCEN 0x0800 /* Address Sequence Complete (Completion) interrupt enable */
+#define MCFDMA_DIR_TEEN 0x0200 /* Transfer Error interrupt enable */
+#define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */
+#define MCFDMA_DIR_INV 0x0010 /* Invalid Combination */
+#define MCFDMA_DIR_ASC 0x0008 /* Address Sequence Complete (DMA Completion) */
+#define MCFDMA_DIR_TE 0x0002 /* Transfer Error */
+#define MCFDMA_DIR_TC 0x0001 /* Transfer Complete */
+
+#endif /* !defined(CONFIG_M5272) */
+
+/****************************************************************************/
+#endif /* mcfdma_h */
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
new file mode 100644
index 0000000..66203c3
--- /dev/null
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -0,0 +1,308 @@
+/*
+ * Coldfire generic GPIO support.
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef mcfgpio_h
+#define mcfgpio_h
+
+#ifdef CONFIG_GPIOLIB
+#include <asm-generic/gpio.h>
+#else
+
+int __mcfgpio_get_value(unsigned gpio);
+void __mcfgpio_set_value(unsigned gpio, int value);
+int __mcfgpio_direction_input(unsigned gpio);
+int __mcfgpio_direction_output(unsigned gpio, int value);
+int __mcfgpio_request(unsigned gpio);
+void __mcfgpio_free(unsigned gpio);
+
+/* our alternate 'gpiolib' functions */
+static inline int __gpio_get_value(unsigned gpio)
+{
+ if (gpio < MCFGPIO_PIN_MAX)
+ return __mcfgpio_get_value(gpio);
+ else
+ return -EINVAL;
+}
+
+static inline void __gpio_set_value(unsigned gpio, int value)
+{
+ if (gpio < MCFGPIO_PIN_MAX)
+ __mcfgpio_set_value(gpio, value);
+}
+
+static inline int __gpio_cansleep(unsigned gpio)
+{
+ if (gpio < MCFGPIO_PIN_MAX)
+ return 0;
+ else
+ return -EINVAL;
+}
+
+static inline int __gpio_to_irq(unsigned gpio)
+{
+ return -EINVAL;
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+ if (gpio < MCFGPIO_PIN_MAX)
+ return __mcfgpio_direction_input(gpio);
+ else
+ return -EINVAL;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+ if (gpio < MCFGPIO_PIN_MAX)
+ return __mcfgpio_direction_output(gpio, value);
+ else
+ return -EINVAL;
+}
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+ if (gpio < MCFGPIO_PIN_MAX)
+ return __mcfgpio_request(gpio);
+ else
+ return -EINVAL;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+ if (gpio < MCFGPIO_PIN_MAX)
+ __mcfgpio_free(gpio);
+}
+
+#endif /* CONFIG_GPIOLIB */
+
+
+/*
+ * The Freescale Coldfire family is quite varied in how they implement GPIO.
+ * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
+ * only one port, others have multiple ports; some have a single data latch
+ * for both input and output, others have a separate pin data register to read
+ * input; some require a read-modify-write access to change an output, others
+ * have set and clear registers for some of the outputs; Some have all the
+ * GPIOs in a single control area, others have some GPIOs implemented in
+ * different modules.
+ *
+ * This implementation attempts accommodate the differences while presenting
+ * a generic interface that will optimize to as few instructions as possible.
+ */
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+ defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+ defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
+ defined(CONFIG_M5441x)
+
+/* These parts have GPIO organized by 8 bit ports */
+
+#define MCFGPIO_PORTTYPE u8
+#define MCFGPIO_PORTSIZE 8
+#define mcfgpio_read(port) __raw_readb(port)
+#define mcfgpio_write(data, port) __raw_writeb(data, port)
+
+#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
+
+/* These parts have GPIO organized by 16 bit ports */
+
+#define MCFGPIO_PORTTYPE u16
+#define MCFGPIO_PORTSIZE 16
+#define mcfgpio_read(port) __raw_readw(port)
+#define mcfgpio_write(data, port) __raw_writew(data, port)
+
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+
+/* These parts have GPIO organized by 32 bit ports */
+
+#define MCFGPIO_PORTTYPE u32
+#define MCFGPIO_PORTSIZE 32
+#define mcfgpio_read(port) __raw_readl(port)
+#define mcfgpio_write(data, port) __raw_writel(data, port)
+
+#endif
+
+#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
+#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
+
+#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+ defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
+ defined(CONFIG_M5441x)
+/*
+ * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
+ * read-modify-write to change an output and a GPIO module which has separate
+ * set/clr registers to directly change outputs with a single write access.
+ */
+#if defined(CONFIG_M528x)
+/*
+ * The 528x also has GPIOs in other modules (GPT, QADC) which use
+ * read-modify-write as well as those controlled by the EPORT and GPIO modules.
+ */
+#define MCFGPIO_SCR_START 40
+#elif defined(CONFIGM5441x)
+/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
+#define MCFGPIO_SCR_START 0
+#else
+#define MCFGPIO_SCR_START 8
+#endif
+
+#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
+ mcfgpio_port(gpio - MCFGPIO_SCR_START))
+
+#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
+ mcfgpio_port(gpio - MCFGPIO_SCR_START))
+#else
+
+#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
+/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
+#define MCFGPIO_SETR_PORT(gpio) 0
+#define MCFGPIO_CLRR_PORT(gpio) 0
+
+#endif
+/*
+ * Coldfire specific helper functions
+ */
+
+/* return the port pin data register for a gpio */
+static inline u32 __mcfgpio_ppdr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+ defined(CONFIG_M5307) || defined(CONFIG_M5407)
+ return MCFSIM_PADAT;
+#elif defined(CONFIG_M5272)
+ if (gpio < 16)
+ return MCFSIM_PADAT;
+ else if (gpio < 32)
+ return MCFSIM_PBDAT;
+ else
+ return MCFSIM_PCDAT;
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+ if (gpio < 32)
+ return MCFSIM2_GPIOREAD;
+ else
+ return MCFSIM2_GPIO1READ;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+ defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
+ defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
+ if (gpio < 8)
+ return MCFEPORT_EPPDR;
+#if defined(CONFIG_M528x)
+ else if (gpio < 16)
+ return MCFGPTA_GPTPORT;
+ else if (gpio < 24)
+ return MCFGPTB_GPTPORT;
+ else if (gpio < 32)
+ return MCFQADC_PORTQA;
+ else if (gpio < 40)
+ return MCFQADC_PORTQB;
+#endif /* defined(CONFIG_M528x) */
+ else
+#endif /* !defined(CONFIG_M5441x) */
+ return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+ return 0;
+#endif
+}
+
+/* return the port output data register for a gpio */
+static inline u32 __mcfgpio_podr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+ defined(CONFIG_M5307) || defined(CONFIG_M5407)
+ return MCFSIM_PADAT;
+#elif defined(CONFIG_M5272)
+ if (gpio < 16)
+ return MCFSIM_PADAT;
+ else if (gpio < 32)
+ return MCFSIM_PBDAT;
+ else
+ return MCFSIM_PCDAT;
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+ if (gpio < 32)
+ return MCFSIM2_GPIOWRITE;
+ else
+ return MCFSIM2_GPIO1WRITE;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+ defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
+ defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
+ if (gpio < 8)
+ return MCFEPORT_EPDR;
+#if defined(CONFIG_M528x)
+ else if (gpio < 16)
+ return MCFGPTA_GPTPORT;
+ else if (gpio < 24)
+ return MCFGPTB_GPTPORT;
+ else if (gpio < 32)
+ return MCFQADC_PORTQA;
+ else if (gpio < 40)
+ return MCFQADC_PORTQB;
+#endif /* defined(CONFIG_M528x) */
+ else
+#endif /* !defined(CONFIG_M5441x) */
+ return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+ return 0;
+#endif
+}
+
+/* return the port direction data register for a gpio */
+static inline u32 __mcfgpio_pddr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+ defined(CONFIG_M5307) || defined(CONFIG_M5407)
+ return MCFSIM_PADDR;
+#elif defined(CONFIG_M5272)
+ if (gpio < 16)
+ return MCFSIM_PADDR;
+ else if (gpio < 32)
+ return MCFSIM_PBDDR;
+ else
+ return MCFSIM_PCDDR;
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+ if (gpio < 32)
+ return MCFSIM2_GPIOENABLE;
+ else
+ return MCFSIM2_GPIO1ENABLE;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+ defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+ defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
+ defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
+ if (gpio < 8)
+ return MCFEPORT_EPDDR;
+#if defined(CONFIG_M528x)
+ else if (gpio < 16)
+ return MCFGPTA_GPTDDR;
+ else if (gpio < 24)
+ return MCFGPTB_GPTDDR;
+ else if (gpio < 32)
+ return MCFQADC_DDRQA;
+ else if (gpio < 40)
+ return MCFQADC_DDRQB;
+#endif /* defined(CONFIG_M528x) */
+ else
+#endif /* !defined(CONFIG_M5441x) */
+ return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+ return 0;
+#endif
+}
+
+#endif /* mcfgpio_h */
diff --git a/arch/m68k/include/asm/mcfintc.h b/arch/m68k/include/asm/mcfintc.h
new file mode 100644
index 0000000..8bcfa33
--- /dev/null
+++ b/arch/m68k/include/asm/mcfintc.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * mcfintc.h -- support definitions for the simple ColdFire
+ * Interrupt Controller
+ *
+ * (C) Copyright 2009, Greg Ungerer <gerg@uclinux.org>
+ */
+
+/****************************************************************************/
+#ifndef mcfintc_h
+#define mcfintc_h
+/****************************************************************************/
+
+/*
+ * Most of the older ColdFire parts use the same simple interrupt
+ * controller. This is currently used on the 5206, 5206e, 5249, 5307
+ * and 5407 parts.
+ *
+ * The builtin peripherals are masked through dedicated bits in the
+ * Interrupt Mask register (IMR) - and this is not indexed (or in any way
+ * related to) the actual interrupt number they use. So knowing the IRQ
+ * number doesn't explicitly map to a certain internal device for
+ * interrupt control purposes.
+ */
+
+/*
+ * Bit definitions for the ICR family of registers.
+ */
+#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
+#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
+#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
+#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
+#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
+#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
+#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
+#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
+
+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
+
+/*
+ * IMR bit position definitions. Not all ColdFire parts with this interrupt
+ * controller actually support all of these interrupt sources. But the bit
+ * numbers are the same in all cores.
+ */
+#define MCFINTC_EINT1 1 /* External int #1 */
+#define MCFINTC_EINT2 2 /* External int #2 */
+#define MCFINTC_EINT3 3 /* External int #3 */
+#define MCFINTC_EINT4 4 /* External int #4 */
+#define MCFINTC_EINT5 5 /* External int #5 */
+#define MCFINTC_EINT6 6 /* External int #6 */
+#define MCFINTC_EINT7 7 /* External int #7 */
+#define MCFINTC_SWT 8 /* Software Watchdog */
+#define MCFINTC_TIMER1 9
+#define MCFINTC_TIMER2 10
+#define MCFINTC_I2C 11 /* I2C / MBUS */
+#define MCFINTC_UART0 12
+#define MCFINTC_UART1 13
+#define MCFINTC_DMA0 14
+#define MCFINTC_DMA1 15
+#define MCFINTC_DMA2 16
+#define MCFINTC_DMA3 17
+#define MCFINTC_QSPI 18
+
+#ifndef __ASSEMBLER__
+
+/*
+ * There is no one-is-one correspondance between the interrupt number (irq)
+ * and the bit fields on the mask register. So we create a per-cpu type
+ * mapping of irq to mask bit. The CPU platform code needs to register
+ * its supported irq's at init time, using this function.
+ */
+extern unsigned char mcf_irq2imr[];
+static inline void mcf_mapirq2imr(int irq, int imr)
+{
+ mcf_irq2imr[irq] = imr;
+}
+
+void mcf_autovector(int irq);
+void mcf_setimr(int index);
+void mcf_clrimr(int index);
+#endif
+
+/****************************************************************************/
+#endif /* mcfintc_h */
diff --git a/arch/m68k/include/asm/mcfmmu.h b/arch/m68k/include/asm/mcfmmu.h
new file mode 100644
index 0000000..283352a
--- /dev/null
+++ b/arch/m68k/include/asm/mcfmmu.h
@@ -0,0 +1,114 @@
+/*
+ * mcfmmu.h -- definitions for the ColdFire v4e MMU
+ *
+ * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef MCFMMU_H
+#define MCFMMU_H
+
+/*
+ * The MMU support registers are mapped into the address space using
+ * the processor MMUBASE register. We used a fixed address for mapping,
+ * there doesn't seem any need to make this configurable yet.
+ */
+#define MMUBASE 0xfe000000
+
+/*
+ * The support registers of the MMU. Names are the sames as those
+ * used in the Freescale v4e documentation.
+ */
+#define MMUCR (MMUBASE + 0x00) /* Control register */
+#define MMUOR (MMUBASE + 0x04) /* Operation register */
+#define MMUSR (MMUBASE + 0x08) /* Status register */
+#define MMUAR (MMUBASE + 0x10) /* TLB Address register */
+#define MMUTR (MMUBASE + 0x14) /* TLB Tag register */
+#define MMUDR (MMUBASE + 0x18) /* TLB Data register */
+
+/*
+ * MMU Control register bit flags
+ */
+#define MMUCR_EN 0x00000001 /* Virtual mode enable */
+#define MMUCR_ASM 0x00000002 /* Address space mode */
+
+/*
+ * MMU Operation register.
+ */
+#define MMUOR_UAA 0x00000001 /* Update allocation address */
+#define MMUOR_ACC 0x00000002 /* TLB access */
+#define MMUOR_RD 0x00000004 /* TLB access read */
+#define MMUOR_WR 0x00000000 /* TLB access write */
+#define MMUOR_ADR 0x00000008 /* TLB address select */
+#define MMUOR_ITLB 0x00000010 /* ITLB operation */
+#define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */
+#define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */
+#define MMUOR_CA 0x00000080 /* Clear all TLBs */
+#define MMUOR_STLB 0x00000100 /* Search TLBs */
+#define MMUOR_AAN 16 /* TLB allocation address */
+#define MMUOR_AAMASK 0xffff0000 /* AA mask */
+
+/*
+ * MMU Status register.
+ */
+#define MMUSR_HIT 0x00000002 /* Search TLB hit */
+#define MMUSR_WF 0x00000008 /* Write access fault */
+#define MMUSR_RF 0x00000010 /* Read access fault */
+#define MMUSR_SPF 0x00000020 /* Supervisor protect fault */
+
+/*
+ * MMU Read/Write Tag register.
+ */
+#define MMUTR_V 0x00000001 /* Valid */
+#define MMUTR_SG 0x00000002 /* Shared global */
+#define MMUTR_IDN 2 /* Address Space ID */
+#define MMUTR_IDMASK 0x000003fc /* ASID mask */
+#define MMUTR_VAN 10 /* Virtual Address */
+#define MMUTR_VAMASK 0xfffffc00 /* VA mask */
+
+/*
+ * MMU Read/Write Data register.
+ */
+#define MMUDR_LK 0x00000002 /* Lock entry */
+#define MMUDR_X 0x00000004 /* Execute access enable */
+#define MMUDR_W 0x00000008 /* Write access enable */
+#define MMUDR_R 0x00000010 /* Read access enable */
+#define MMUDR_SP 0x00000020 /* Supervisor access enable */
+#define MMUDR_CM_CWT 0x00000000 /* Cachable write thru */
+#define MMUDR_CM_CCB 0x00000040 /* Cachable copy back */
+#define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */
+#define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */
+#define MMUDR_SZ_1MB 0x00000000 /* 1MB page size */
+#define MMUDR_SZ_4KB 0x00000100 /* 4kB page size */
+#define MMUDR_SZ_8KB 0x00000200 /* 8kB page size */
+#define MMUDR_SZ_1KB 0x00000300 /* 1kB page size */
+#define MMUDR_PAN 10 /* Physical address */
+#define MMUDR_PAMASK 0xfffffc00 /* PA mask */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Simple access functions for the MMU registers. Nothing fancy
+ * currently required, just simple 32bit access.
+ */
+static inline u32 mmu_read(u32 a)
+{
+ return *((volatile u32 *) a);
+}
+
+static inline void mmu_write(u32 a, u32 v)
+{
+ *((volatile u32 *) a) = v;
+ __asm__ __volatile__ ("nop");
+}
+
+void cf_bootmem_alloc(void);
+void cf_mmu_context_init(void);
+int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word);
+
+#endif
+
+#endif /* MCFMMU_H */
diff --git a/arch/m68k/include/asm/mcfpit.h b/arch/m68k/include/asm/mcfpit.h
new file mode 100644
index 0000000..20c81e0
--- /dev/null
+++ b/arch/m68k/include/asm/mcfpit.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * mcfpit.h -- ColdFire internal PIT timer support defines.
+ *
+ * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/****************************************************************************/
+#ifndef mcfpit_h
+#define mcfpit_h
+/****************************************************************************/
+
+/*
+ * Define the PIT timer register address offsets.
+ */
+#define MCFPIT_PCSR 0x0 /* PIT control register */
+#define MCFPIT_PMR 0x2 /* PIT modulus register */
+#define MCFPIT_PCNTR 0x4 /* PIT count register */
+
+/*
+ * Bit definitions for the PIT Control and Status register.
+ */
+#define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
+#define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
+#define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
+#define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
+#define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
+#define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
+#define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
+#define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */
+#define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */
+#define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */
+#define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */
+#define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */
+#define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */
+#define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */
+#define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */
+#define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */
+#define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */
+#define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */
+#define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */
+#define MCFPIT_PCSR_PIE 0x0008 /* Enable PIT interrupt */
+#define MCFPIT_PCSR_PIF 0x0004 /* PIT interrupt flag */
+#define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */
+#define MCFPIT_PCSR_EN 0x0001 /* Enable PIT */
+#define MCFPIT_PCSR_DISABLE 0x0000 /* Disable PIT */
+
+/****************************************************************************/
+#endif /* mcfpit_h */
diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h
new file mode 100644
index 0000000..256da0e
--- /dev/null
+++ b/arch/m68k/include/asm/mcfqspi.h
@@ -0,0 +1,50 @@
+/*
+ * Definitions for Freescale Coldfire QSPI module
+ *
+ * Copyright 2010 Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+*/
+
+#ifndef mcfqspi_h
+#define mcfqspi_h
+
+/**
+ * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
+ * @setup: setup the control; allocate gpio's, etc. May be NULL.
+ * @teardown: finish with the control; free gpio's, etc. May be NULL.
+ * @select: output the signals to select the device. Can not be NULL.
+ * @deselect: output the signals to deselect the device. Can not be NULL.
+ *
+ * The QSPI module has 4 hardware chip selects. We don't use them. Instead
+ * platforms are required to supply a mcfqspi_cs_control as a part of the
+ * platform data for each QSPI master controller. Only the select and
+ * deselect functions are required.
+*/
+struct mcfqspi_cs_control {
+ int (*setup)(struct mcfqspi_cs_control *);
+ void (*teardown)(struct mcfqspi_cs_control *);
+ void (*select)(struct mcfqspi_cs_control *, u8, bool);
+ void (*deselect)(struct mcfqspi_cs_control *, u8, bool);
+};
+
+/**
+ * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
+ * @bus_num: board specific identifier for this qspi driver.
+ * @num_chipselects: number of chip selects supported by this qspi driver.
+ * @cs_control: platform dependent chip select control.
+*/
+struct mcfqspi_platform_data {
+ s16 bus_num;
+ u16 num_chipselect;
+ struct mcfqspi_cs_control *cs_control;
+};
+
+#endif /* mcfqspi_h */
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
new file mode 100644
index 0000000..bef0895
--- /dev/null
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * mcfsim.h -- ColdFire System Integration Module support.
+ *
+ * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ */
+
+/****************************************************************************/
+#ifndef mcfsim_h
+#define mcfsim_h
+/****************************************************************************/
+
+/*
+ * Include the appropriate ColdFire CPU specific System Integration Module
+ * (SIM) definitions.
+ */
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
+#include <asm/m5206sim.h>
+#include <asm/mcfintc.h>
+#elif defined(CONFIG_M520x)
+#include <asm/m520xsim.h>
+#elif defined(CONFIG_M523x)
+#include <asm/m523xsim.h>
+#include <asm/mcfintc.h>
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+#include <asm/m525xsim.h>
+#include <asm/mcfintc.h>
+#elif defined(CONFIG_M527x)
+#include <asm/m527xsim.h>
+#elif defined(CONFIG_M5272)
+#include <asm/m5272sim.h>
+#elif defined(CONFIG_M528x)
+#include <asm/m528xsim.h>
+#elif defined(CONFIG_M5307)
+#include <asm/m5307sim.h>
+#include <asm/mcfintc.h>
+#elif defined(CONFIG_M53xx)
+#include <asm/m53xxsim.h>
+#elif defined(CONFIG_M5407)
+#include <asm/m5407sim.h>
+#include <asm/mcfintc.h>
+#elif defined(CONFIG_M54xx)
+#include <asm/m54xxsim.h>
+#elif defined(CONFIG_M5441x)
+#include <asm/m5441xsim.h>
+#endif
+
+/****************************************************************************/
+#endif /* mcfsim_h */
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
new file mode 100644
index 0000000..a539f0e
--- /dev/null
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
+ *
+ * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
+ */
+
+/****************************************************************************/
+#ifndef mcfslt_h
+#define mcfslt_h
+/****************************************************************************/
+
+/*
+ * Define the SLT timer register set addresses.
+ */
+#define MCFSLT_STCNT 0x00 /* Terminal count */
+#define MCFSLT_SCR 0x04 /* Control */
+#define MCFSLT_SCNT 0x08 /* Current count */
+#define MCFSLT_SSR 0x0C /* Status */
+
+/*
+ * Bit definitions for the SCR control register.
+ */
+#define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */
+#define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */
+#define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */
+
+/*
+ * Bit definitions for the SSR status register.
+ */
+#define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */
+#define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */
+
+/****************************************************************************/
+#endif /* mcfslt_h */
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
new file mode 100644
index 0000000..4fe83db
--- /dev/null
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * mcftimer.h -- ColdFire internal TIMER support defines.
+ *
+ * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>
+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ */
+
+/****************************************************************************/
+#ifndef mcftimer_h
+#define mcftimer_h
+/****************************************************************************/
+
+/*
+ * Define the TIMER register set addresses.
+ */
+#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
+#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
+#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
+#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
+#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
+#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
+#else
+#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
+#endif
+
+/*
+ * Bit definitions for the Timer Mode Register (TMR).
+ * Register bit flags are common across ColdFires.
+ */
+#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
+#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
+#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
+#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
+#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
+#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
+#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
+#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
+#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
+#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
+#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
+#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
+#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
+#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
+#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
+#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
+#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
+
+/*
+ * Bit definitions for the Timer Event Registers (TER).
+ */
+#define MCFTIMER_TER_CAP 0x01 /* Capture event */
+#define MCFTIMER_TER_REF 0x02 /* Reference event */
+
+/****************************************************************************/
+#endif /* mcftimer_h */
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
new file mode 100644
index 0000000..a1f3535
--- /dev/null
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * mcfuart.h -- ColdFire internal UART support defines.
+ *
+ * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
+ * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ */
+
+/****************************************************************************/
+#ifndef mcfuart_h
+#define mcfuart_h
+/****************************************************************************/
+
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+struct mcf_platform_uart {
+ unsigned long mapbase; /* Physical address base */
+ void __iomem *membase; /* Virtual address if mapped */
+ unsigned int irq; /* Interrupt vector */
+ unsigned int uartclk; /* UART clock rate */
+};
+
+/*
+ * Define the ColdFire UART register set addresses.
+ */
+#define MCFUART_UMR 0x00 /* Mode register (r/w) */
+#define MCFUART_USR 0x04 /* Status register (r) */
+#define MCFUART_UCSR 0x04 /* Clock Select (w) */
+#define MCFUART_UCR 0x08 /* Command register (w) */
+#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
+#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
+#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
+#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
+#define MCFUART_UISR 0x14 /* Interrupt Status (r) */
+#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
+#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
+#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
+#ifdef CONFIG_M5272
+#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
+#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
+#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
+#endif
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+ defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
+ defined(CONFIG_M5307) || defined(CONFIG_M5407)
+#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
+#endif
+#define MCFUART_UIPR 0x34 /* Input Port (r) */
+#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
+#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
+
+
+/*
+ * Define bit flags in Mode Register 1 (MR1).
+ */
+#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
+#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
+#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
+#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
+#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
+
+#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
+#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
+#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
+#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
+#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
+
+#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
+#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
+#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
+#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
+
+/*
+ * Define bit flags in Mode Register 2 (MR2).
+ */
+#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
+#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
+#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
+#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
+#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
+
+#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
+#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
+#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
+
+/*
+ * Define bit flags in Status Register (USR).
+ */
+#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
+#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
+#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
+#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
+#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
+#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
+#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
+#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
+
+#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
+ MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
+
+/*
+ * Define bit flags in Clock Select Register (UCSR).
+ */
+#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
+#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
+#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
+
+#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
+#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
+#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
+
+/*
+ * Define bit flags in Command Register (UCR).
+ */
+#define MCFUART_UCR_CMDNULL 0x00 /* No command */
+#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
+#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
+#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
+#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
+#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
+#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
+#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
+
+#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
+#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
+#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
+#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
+#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
+#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
+
+/*
+ * Define bit flags in Input Port Change Register (UIPCR).
+ */
+#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
+#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
+
+/*
+ * Define bit flags in Input Port Register (UIP).
+ */
+#define MCFUART_UIPR_CTS 0x01 /* CTS value */
+
+/*
+ * Define bit flags in Output Port Registers (UOP).
+ * Clear bit by writing to UOP0, set by writing to UOP1.
+ */
+#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
+
+/*
+ * Define bit flags in the Auxiliary Control Register (UACR).
+ */
+#define MCFUART_UACR_IEC 0x01 /* Input enable control */
+
+/*
+ * Define bit flags in Interrupt Status Register (UISR).
+ * These same bits are used for the Interrupt Mask Register (UIMR).
+ */
+#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
+#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
+#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
+#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
+
+#ifdef CONFIG_M5272
+/*
+ * Define bit flags in the Transmitter FIFO Register (UTF).
+ */
+#define MCFUART_UTF_TXB 0x1f /* Transmitter data level */
+#define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */
+#define MCFUART_UTF_TXS 0xc0 /* Transmitter status */
+
+/*
+ * Define bit flags in the Receiver FIFO Register (URF).
+ */
+#define MCFUART_URF_RXB 0x1f /* Receiver data level */
+#define MCFUART_URF_FULL 0x20 /* Receiver fifo full */
+#define MCFUART_URF_RXS 0xc0 /* Receiver status */
+#endif
+
+#if defined(CONFIG_M54xx)
+#define MCFUART_TXFIFOSIZE 512
+#elif defined(CONFIG_M5272)
+#define MCFUART_TXFIFOSIZE 25
+#else
+#define MCFUART_TXFIFOSIZE 1
+#endif
+/****************************************************************************/
+#endif /* mcfuart_h */
diff --git a/arch/m68k/include/asm/mcfwdebug.h b/arch/m68k/include/asm/mcfwdebug.h
new file mode 100644
index 0000000..bbe06cf
--- /dev/null
+++ b/arch/m68k/include/asm/mcfwdebug.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * mcfdebug.h -- ColdFire Debug Module support.
+ *
+ * (C) Copyright 2001, Lineo Inc. (www.lineo.com)
+ */
+
+/****************************************************************************/
+#ifndef mcfdebug_h
+#define mcfdebug_h
+/****************************************************************************/
+
+/* Define the debug module registers */
+#define MCFDEBUG_CSR 0x0 /* Configuration status */
+#define MCFDEBUG_BAAR 0x5 /* BDM address attribute */
+#define MCFDEBUG_AATR 0x6 /* Address attribute trigger */
+#define MCFDEBUG_TDR 0x7 /* Trigger definition */
+#define MCFDEBUG_PBR 0x8 /* PC breakpoint */
+#define MCFDEBUG_PBMR 0x9 /* PC breakpoint mask */
+#define MCFDEBUG_ABHR 0xc /* High address breakpoint */
+#define MCFDEBUG_ABLR 0xd /* Low address breakpoint */
+#define MCFDEBUG_DBR 0xe /* Data breakpoint */
+#define MCFDEBUG_DBMR 0xf /* Data breakpoint mask */
+
+/* Define some handy constants for the trigger definition register */
+#define MCFDEBUG_TDR_TRC_DISP 0x00000000 /* display on DDATA only */
+#define MCFDEBUG_TDR_TRC_HALT 0x40000000 /* Processor halt on BP */
+#define MCFDEBUG_TDR_TRC_INTR 0x80000000 /* Debug intr on BP */
+#define MCFDEBUG_TDR_LXT1 0x00004000 /* TDR level 1 */
+#define MCFDEBUG_TDR_LXT2 0x00008000 /* TDR level 2 */
+#define MCFDEBUG_TDR_EBL1 0x00002000 /* Enable breakpoint level 1 */
+#define MCFDEBUG_TDR_EBL2 0x20000000 /* Enable breakpoint level 2 */
+#define MCFDEBUG_TDR_EDLW1 0x00001000 /* Enable data BP longword */
+#define MCFDEBUG_TDR_EDLW2 0x10000000
+#define MCFDEBUG_TDR_EDWL1 0x00000800 /* Enable data BP lower word */
+#define MCFDEBUG_TDR_EDWL2 0x08000000
+#define MCFDEBUG_TDR_EDWU1 0x00000400 /* Enable data BP upper word */
+#define MCFDEBUG_TDR_EDWU2 0x04000000
+#define MCFDEBUG_TDR_EDLL1 0x00000200 /* Enable data BP low low byte */
+#define MCFDEBUG_TDR_EDLL2 0x02000000
+#define MCFDEBUG_TDR_EDLM1 0x00000100 /* Enable data BP low mid byte */
+#define MCFDEBUG_TDR_EDLM2 0x01000000
+#define MCFDEBUG_TDR_EDUM1 0x00000080 /* Enable data BP up mid byte */
+#define MCFDEBUG_TDR_EDUM2 0x00800000
+#define MCFDEBUG_TDR_EDUU1 0x00000040 /* Enable data BP up up byte */
+#define MCFDEBUG_TDR_EDUU2 0x00400000
+#define MCFDEBUG_TDR_DI1 0x00000020 /* Data BP invert */
+#define MCFDEBUG_TDR_DI2 0x00200000
+#define MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */
+#define MCFDEBUG_TDR_EAI2 0x00100000
+#define MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */
+#define MCFDEBUG_TDR_EAR2 0x00080000
+#define MCFDEBUG_TDR_EAL1 0x00000004 /* Enable address BP low */
+#define MCFDEBUG_TDR_EAL2 0x00040000
+#define MCFDEBUG_TDR_EPC1 0x00000002 /* Enable PC BP */
+#define MCFDEBUG_TDR_EPC2 0x00020000
+#define MCFDEBUG_TDR_PCI1 0x00000001 /* PC BP invert */
+#define MCFDEBUG_TDR_PCI2 0x00010000
+
+/* Constants for the address attribute trigger register */
+#define MCFDEBUG_AAR_RESET 0x00000005
+/* Fields not yet implemented */
+
+/* And some definitions for the writable sections of the CSR */
+#define MCFDEBUG_CSR_RESET 0x00100000
+#define MCFDEBUG_CSR_PSTCLK 0x00020000 /* PSTCLK disable */
+#define MCFDEBUG_CSR_IPW 0x00010000 /* Inhibit processor writes */
+#define MCFDEBUG_CSR_MAP 0x00008000 /* Processor refs in emul mode */
+#define MCFDEBUG_CSR_TRC 0x00004000 /* Emul mode on trace exception */
+#define MCFDEBUG_CSR_EMU 0x00002000 /* Force emulation mode */
+#define MCFDEBUG_CSR_DDC_READ 0x00000800 /* Debug data control */
+#define MCFDEBUG_CSR_DDC_WRITE 0x00001000
+#define MCFDEBUG_CSR_UHE 0x00000400 /* User mode halt enable */
+#define MCFDEBUG_CSR_BTB0 0x00000000 /* Branch target 0 bytes */
+#define MCFDEBUG_CSR_BTB2 0x00000100 /* Branch target 2 bytes */
+#define MCFDEBUG_CSR_BTB3 0x00000200 /* Branch target 3 bytes */
+#define MCFDEBUG_CSR_BTB4 0x00000300 /* Branch target 4 bytes */
+#define MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */
+#define MCFDEBUG_CSR_SSM 0x00000010 /* Single step mode */
+
+/* Constants for the BDM address attribute register */
+#define MCFDEBUG_BAAR_RESET 0x00000005
+/* Fields not yet implemented */
+
+
+/* This routine wrappers up the wdebug asm instruction so that the register
+ * and value can be relatively easily specified. The biggest hassle here is
+ * that the debug module instructions (2 longs) must be long word aligned and
+ * some pointer fiddling is performed to ensure this.
+ */
+static inline void wdebug(int reg, unsigned long data) {
+ unsigned short dbg_spc[6];
+ unsigned short *dbg;
+
+ // Force alignment to long word boundary
+ dbg = (unsigned short *)((((unsigned long)dbg_spc) + 3) & 0xfffffffc);
+
+ // Build up the debug instruction
+ dbg[0] = 0x2c80 | (reg & 0xf);
+ dbg[1] = (data >> 16) & 0xffff;
+ dbg[2] = data & 0xffff;
+ dbg[3] = 0;
+
+ // Perform the wdebug instruction
+#if 0
+ // This strain is for gas which doesn't have the wdebug instructions defined
+ asm( "move.l %0, %%a0\n\t"
+ ".word 0xfbd0\n\t"
+ ".word 0x0003\n\t"
+ :: "g" (dbg) : "a0");
+#else
+ // And this is for when it does
+ asm( "wdebug (%0)" :: "a" (dbg));
+#endif
+}
+
+#endif
diff --git a/arch/m68k/include/asm/mmu.h b/arch/m68k/include/asm/mmu.h
new file mode 100644
index 0000000..5c15aac
--- /dev/null
+++ b/arch/m68k/include/asm/mmu.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __MMU_H
+#define __MMU_H
+
+#ifdef CONFIG_MMU
+/* Default "unsigned long" context */
+typedef unsigned long mm_context_t;
+#else
+typedef struct {
+ unsigned long end_brk;
+} mm_context_t;
+#endif
+
+#endif
diff --git a/arch/m68k/include/asm/mmu_context.h b/arch/m68k/include/asm/mmu_context.h
new file mode 100644
index 0000000..f5b1852
--- /dev/null
+++ b/arch/m68k/include/asm/mmu_context.h
@@ -0,0 +1,328 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __M68K_MMU_CONTEXT_H
+#define __M68K_MMU_CONTEXT_H
+
+#include <asm-generic/mm_hooks.h>
+#include <linux/mm_types.h>
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+#ifdef CONFIG_MMU
+
+#if defined(CONFIG_COLDFIRE)
+
+#include <asm/atomic.h>
+#include <asm/bitops.h>
+#include <asm/mcfmmu.h>
+#include <asm/mmu.h>
+
+#define NO_CONTEXT 256
+#define LAST_CONTEXT 255
+#define FIRST_CONTEXT 1
+
+extern unsigned long context_map[];
+extern mm_context_t next_mmu_context;
+
+extern atomic_t nr_free_contexts;
+extern struct mm_struct *context_mm[LAST_CONTEXT+1];
+extern void steal_context(void);
+
+static inline void get_mmu_context(struct mm_struct *mm)
+{
+ mm_context_t ctx;
+
+ if (mm->context != NO_CONTEXT)
+ return;
+ while (atomic_dec_and_test_lt(&nr_free_contexts)) {
+ atomic_inc(&nr_free_contexts);
+ steal_context();
+ }
+ ctx = next_mmu_context;
+ while (test_and_set_bit(ctx, context_map)) {
+ ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
+ if (ctx > LAST_CONTEXT)
+ ctx = 0;
+ }
+ next_mmu_context = (ctx + 1) & LAST_CONTEXT;
+ mm->context = ctx;
+ context_mm[ctx] = mm;
+}
+
+/*
+ * Set up the context for a new address space.
+ */
+#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
+
+/*
+ * We're finished using the context for an address space.
+ */
+static inline void destroy_context(struct mm_struct *mm)
+{
+ if (mm->context != NO_CONTEXT) {
+ clear_bit(mm->context, context_map);
+ mm->context = NO_CONTEXT;
+ atomic_inc(&nr_free_contexts);
+ }
+}
+
+static inline void set_context(mm_context_t context, pgd_t *pgd)
+{
+ __asm__ __volatile__ ("movec %0,%%asid" : : "d" (context));
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+ struct task_struct *tsk)
+{
+ get_mmu_context(tsk->mm);
+ set_context(tsk->mm->context, next->pgd);
+}
+
+/*
+ * After we have set current->mm to a new value, this activates
+ * the context for the new mm so we see the new mappings.
+ */
+static inline void activate_mm(struct mm_struct *active_mm,
+ struct mm_struct *mm)
+{
+ get_mmu_context(mm);
+ set_context(mm->context, mm->pgd);
+}
+
+#define deactivate_mm(tsk, mm) do { } while (0)
+
+#define prepare_arch_switch(next) load_ksp_mmu(next)
+
+static inline void load_ksp_mmu(struct task_struct *task)
+{
+ unsigned long flags;
+ struct mm_struct *mm;
+ int asid;
+ pgd_t *pgd;
+ pmd_t *pmd;
+ pte_t *pte;
+ unsigned long mmuar;
+
+ local_irq_save(flags);
+ mmuar = task->thread.ksp;
+
+ /* Search for a valid TLB entry, if one is found, don't remap */
+ mmu_write(MMUAR, mmuar);
+ mmu_write(MMUOR, MMUOR_STLB | MMUOR_ADR);
+ if (mmu_read(MMUSR) & MMUSR_HIT)
+ goto end;
+
+ if (mmuar >= PAGE_OFFSET) {
+ mm = &init_mm;
+ } else {
+ pr_info("load_ksp_mmu: non-kernel mm found: 0x%p\n", task->mm);
+ mm = task->mm;
+ }
+
+ if (!mm)
+ goto bug;
+
+ pgd = pgd_offset(mm, mmuar);
+ if (pgd_none(*pgd))
+ goto bug;
+
+ pmd = pmd_offset(pgd, mmuar);
+ if (pmd_none(*pmd))
+ goto bug;
+
+ pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar)
+ : pte_offset_map(pmd, mmuar);
+ if (pte_none(*pte) || !pte_present(*pte))
+ goto bug;
+
+ set_pte(pte, pte_mkyoung(*pte));
+ asid = mm->context & 0xff;
+ if (!pte_dirty(*pte) && mmuar <= PAGE_OFFSET)
+ set_pte(pte, pte_wrprotect(*pte));
+
+ mmu_write(MMUTR, (mmuar & PAGE_MASK) | (asid << MMUTR_IDN) |
+ (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK)
+ >> CF_PAGE_MMUTR_SHIFT) | MMUTR_V);
+
+ mmu_write(MMUDR, (pte_val(*pte) & PAGE_MASK) |
+ ((pte->pte) & CF_PAGE_MMUDR_MASK) | MMUDR_SZ_8KB | MMUDR_X);
+
+ mmu_write(MMUOR, MMUOR_ACC | MMUOR_UAA);
+
+ goto end;
+
+bug:
+ pr_info("ksp load failed: mm=0x%p ksp=0x08%lx\n", mm, mmuar);
+end:
+ local_irq_restore(flags);
+}
+
+#elif defined(CONFIG_SUN3)
+#include <asm/sun3mmu.h>
+#include <linux/sched.h>
+
+extern unsigned long get_free_context(struct mm_struct *mm);
+extern void clear_context(unsigned long context);
+
+/* set the context for a new task to unmapped */
+static inline int init_new_context(struct task_struct *tsk,
+ struct mm_struct *mm)
+{
+ mm->context = SUN3_INVALID_CONTEXT;
+ return 0;
+}
+
+/* find the context given to this process, and if it hasn't already
+ got one, go get one for it. */
+static inline void get_mmu_context(struct mm_struct *mm)
+{
+ if (mm->context == SUN3_INVALID_CONTEXT)
+ mm->context = get_free_context(mm);
+}
+
+/* flush context if allocated... */
+static inline void destroy_context(struct mm_struct *mm)
+{
+ if (mm->context != SUN3_INVALID_CONTEXT)
+ clear_context(mm->context);
+}
+
+static inline void activate_context(struct mm_struct *mm)
+{
+ get_mmu_context(mm);
+ sun3_put_context(mm->context);
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+ struct task_struct *tsk)
+{
+ activate_context(tsk->mm);
+}
+
+#define deactivate_mm(tsk, mm) do { } while (0)
+
+static inline void activate_mm(struct mm_struct *prev_mm,
+ struct mm_struct *next_mm)
+{
+ activate_context(next_mm);
+}
+
+#else
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/pgalloc.h>
+
+static inline int init_new_context(struct task_struct *tsk,
+ struct mm_struct *mm)
+{
+ mm->context = virt_to_phys(mm->pgd);
+ return 0;
+}
+
+#define destroy_context(mm) do { } while(0)
+
+static inline void switch_mm_0230(struct mm_struct *mm)
+{
+ unsigned long crp[2] = {
+ 0x80000000 | _PAGE_TABLE, mm->context
+ };
+ unsigned long tmp;
+
+ asm volatile (".chip 68030");
+
+ /* flush MC68030/MC68020 caches (they are virtually addressed) */
+ asm volatile (
+ "movec %%cacr,%0;"
+ "orw %1,%0; "
+ "movec %0,%%cacr"
+ : "=d" (tmp) : "di" (FLUSH_I_AND_D));
+
+ /* Switch the root pointer. For a 030-only kernel,
+ * avoid flushing the whole ATC, we only need to
+ * flush the user entries. The 68851 does this by
+ * itself. Avoid a runtime check here.
+ */
+ asm volatile (
+#ifdef CPU_M68030_ONLY
+ "pmovefd %0,%%crp; "
+ "pflush #0,#4"
+#else
+ "pmove %0,%%crp"
+#endif
+ : : "m" (crp[0]));
+
+ asm volatile (".chip 68k");
+}
+
+static inline void switch_mm_0460(struct mm_struct *mm)
+{
+ asm volatile (".chip 68040");
+
+ /* flush address translation cache (user entries) */
+ asm volatile ("pflushan");
+
+ /* switch the root pointer */
+ asm volatile ("movec %0,%%urp" : : "r" (mm->context));
+
+ if (CPU_IS_060) {
+ unsigned long tmp;
+
+ /* clear user entries in the branch cache */
+ asm volatile (
+ "movec %%cacr,%0; "
+ "orl %1,%0; "
+ "movec %0,%%cacr"
+ : "=d" (tmp): "di" (0x00200000));
+ }
+
+ asm volatile (".chip 68k");
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
+{
+ if (prev != next) {
+ if (CPU_IS_020_OR_030)
+ switch_mm_0230(next);
+ else
+ switch_mm_0460(next);
+ }
+}
+
+#define deactivate_mm(tsk,mm) do { } while (0)
+
+static inline void activate_mm(struct mm_struct *prev_mm,
+ struct mm_struct *next_mm)
+{
+ next_mm->context = virt_to_phys(next_mm->pgd);
+
+ if (CPU_IS_020_OR_030)
+ switch_mm_0230(next_mm);
+ else
+ switch_mm_0460(next_mm);
+}
+
+#endif
+
+#else /* !CONFIG_MMU */
+
+static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+ return 0;
+}
+
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
+{
+}
+
+#define destroy_context(mm) do { } while (0)
+#define deactivate_mm(tsk,mm) do { } while (0)
+
+static inline void activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
+{
+}
+
+#endif /* CONFIG_MMU */
+#endif /* __M68K_MMU_CONTEXT_H */
diff --git a/arch/m68k/include/asm/mmzone.h b/arch/m68k/include/asm/mmzone.h
new file mode 100644
index 0000000..64573fe
--- /dev/null
+++ b/arch/m68k/include/asm/mmzone.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_MMZONE_H_
+#define _ASM_M68K_MMZONE_H_
+
+extern pg_data_t pg_data_map[];
+
+#define NODE_DATA(nid) (&pg_data_map[nid])
+#define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map)
+
+#endif /* _ASM_M68K_MMZONE_H_ */
diff --git a/arch/m68k/include/asm/module.h b/arch/m68k/include/asm/module.h
new file mode 100644
index 0000000..36cb06c
--- /dev/null
+++ b/arch/m68k/include/asm/module.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_MODULE_H
+#define _ASM_M68K_MODULE_H
+
+#include <asm-generic/module.h>
+
+enum m68k_fixup_type {
+ m68k_fixup_memoffset,
+ m68k_fixup_vnode_shift,
+};
+
+struct m68k_fixup_info {
+ enum m68k_fixup_type type;
+ void *addr;
+};
+
+struct mod_arch_specific {
+ struct m68k_fixup_info *fixup_start, *fixup_end;
+};
+
+#ifdef CONFIG_MMU
+
+#define MODULE_ARCH_INIT { \
+ .fixup_start = __start_fixup, \
+ .fixup_end = __stop_fixup, \
+}
+
+
+#define m68k_fixup(type, addr) \
+ " .section \".m68k_fixup\",\"aw\"\n" \
+ " .long " #type "," #addr "\n" \
+ " .previous\n"
+
+#endif /* CONFIG_MMU */
+
+extern struct m68k_fixup_info __start_fixup[], __stop_fixup[];
+
+struct module;
+extern void module_fixup(struct module *mod, struct m68k_fixup_info *start,
+ struct m68k_fixup_info *end);
+
+#endif /* _ASM_M68K_MODULE_H */
diff --git a/arch/m68k/include/asm/motorola_pgalloc.h b/arch/m68k/include/asm/motorola_pgalloc.h
new file mode 100644
index 0000000..7859a86
--- /dev/null
+++ b/arch/m68k/include/asm/motorola_pgalloc.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MOTOROLA_PGALLOC_H
+#define _MOTOROLA_PGALLOC_H
+
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+
+extern pmd_t *get_pointer_table(void);
+extern int free_pointer_table(pmd_t *);
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
+{
+ pte_t *pte;
+
+ pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
+ if (pte) {
+ __flush_page_to_ram(pte);
+ flush_tlb_kernel_page(pte);
+ nocache_page(pte);
+ }
+
+ return pte;
+}
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+ cache_page(pte);
+ free_page((unsigned long) pte);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+ struct page *page;
+ pte_t *pte;
+
+ page = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
+ if(!page)
+ return NULL;
+ if (!pgtable_page_ctor(page)) {
+ __free_page(page);
+ return NULL;
+ }
+
+ pte = kmap(page);
+ __flush_page_to_ram(pte);
+ flush_tlb_kernel_page(pte);
+ nocache_page(pte);
+ kunmap(page);
+ return page;
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t page)
+{
+ pgtable_page_dtor(page);
+ cache_page(kmap(page));
+ kunmap(page);
+ __free_page(page);
+}
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t page,
+ unsigned long address)
+{
+ pgtable_page_dtor(page);
+ cache_page(kmap(page));
+ kunmap(page);
+ __free_page(page);
+}
+
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+ return get_pointer_table();
+}
+
+static inline int pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+ return free_pointer_table(pmd);
+}
+
+static inline int __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
+ unsigned long address)
+{
+ return free_pointer_table(pmd);
+}
+
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+ pmd_free(mm, (pmd_t *)pgd);
+}
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+ return (pgd_t *)get_pointer_table();
+}
+
+
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte)
+{
+ pmd_set(pmd, pte);
+}
+
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page)
+{
+ pmd_set(pmd, page_address(page));
+}
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmd)
+{
+ pgd_set(pgd, pmd);
+}
+
+#endif /* _MOTOROLA_PGALLOC_H */
diff --git a/arch/m68k/include/asm/motorola_pgtable.h b/arch/m68k/include/asm/motorola_pgtable.h
new file mode 100644
index 0000000..7f66a7b
--- /dev/null
+++ b/arch/m68k/include/asm/motorola_pgtable.h
@@ -0,0 +1,276 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MOTOROLA_PGTABLE_H
+#define _MOTOROLA_PGTABLE_H
+
+
+/*
+ * Definitions for MMU descriptors
+ */
+#define _PAGE_PRESENT 0x001
+#define _PAGE_SHORT 0x002
+#define _PAGE_RONLY 0x004
+#define _PAGE_READWRITE 0x000
+#define _PAGE_ACCESSED 0x008
+#define _PAGE_DIRTY 0x010
+#define _PAGE_SUPER 0x080 /* 68040 supervisor only */
+#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
+#define _PAGE_NOCACHE030 0x040 /* 68030 no-cache mode */
+#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */
+#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */
+#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */
+#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */
+
+#define _DESCTYPE_MASK 0x003
+
+#define _CACHEMASK040 (~0x060)
+#define _TABLE_MASK (0xfffffe00)
+
+#define _PAGE_TABLE (_PAGE_SHORT)
+#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_NOCACHE)
+
+#define _PAGE_PROTNONE 0x004
+
+#ifndef __ASSEMBLY__
+
+/* This is the cache mode to be used for pages containing page descriptors for
+ * processors >= '040. It is in pte_mknocache(), and the variable is defined
+ * and initialized in head.S */
+extern int m68k_pgtable_cachemode;
+
+/* This is the cache mode for normal pages, for supervisor access on
+ * processors >= '040. It is used in pte_mkcache(), and the variable is
+ * defined and initialized in head.S */
+
+#if defined(CPU_M68060_ONLY) && defined(CONFIG_060_WRITETHROUGH)
+#define m68k_supervisor_cachemode _PAGE_CACHE040W
+#elif defined(CPU_M68040_OR_M68060_ONLY)
+#define m68k_supervisor_cachemode _PAGE_CACHE040
+#elif defined(CPU_M68020_OR_M68030_ONLY)
+#define m68k_supervisor_cachemode 0
+#else
+extern int m68k_supervisor_cachemode;
+#endif
+
+#if defined(CPU_M68040_OR_M68060_ONLY)
+#define mm_cachebits _PAGE_CACHE040
+#elif defined(CPU_M68020_OR_M68030_ONLY)
+#define mm_cachebits 0
+#else
+extern unsigned long mm_cachebits;
+#endif
+
+#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED | mm_cachebits)
+#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | mm_cachebits)
+#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits)
+#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits)
+#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED | mm_cachebits)
+
+/* Alternate definitions that are compile time constants, for
+ initializing protection_map. The cachebits are fixed later. */
+#define PAGE_NONE_C __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
+#define PAGE_SHARED_C __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
+#define PAGE_COPY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
+#define PAGE_READONLY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
+
+/*
+ * The m68k can't do page protection for execute, and considers that the same are read.
+ * Also, write permissions imply read permissions. This is the closest we can get..
+ */
+#define __P000 PAGE_NONE_C
+#define __P001 PAGE_READONLY_C
+#define __P010 PAGE_COPY_C
+#define __P011 PAGE_COPY_C
+#define __P100 PAGE_READONLY_C
+#define __P101 PAGE_READONLY_C
+#define __P110 PAGE_COPY_C
+#define __P111 PAGE_COPY_C
+
+#define __S000 PAGE_NONE_C
+#define __S001 PAGE_READONLY_C
+#define __S010 PAGE_SHARED_C
+#define __S011 PAGE_SHARED_C
+#define __S100 PAGE_READONLY_C
+#define __S101 PAGE_READONLY_C
+#define __S110 PAGE_SHARED_C
+#define __S111 PAGE_SHARED_C
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
+ return pte;
+}
+
+static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
+{
+ unsigned long ptbl = virt_to_phys(ptep) | _PAGE_TABLE | _PAGE_ACCESSED;
+ unsigned long *ptr = pmdp->pmd;
+ short i = 16;
+ while (--i >= 0) {
+ *ptr++ = ptbl;
+ ptbl += (sizeof(pte_t)*PTRS_PER_PTE/16);
+ }
+}
+
+static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp)
+{
+ pgd_val(*pgdp) = _PAGE_TABLE | _PAGE_ACCESSED | __pa(pmdp);
+}
+
+#define __pte_page(pte) ((unsigned long)__va(pte_val(pte) & PAGE_MASK))
+#define __pmd_page(pmd) ((unsigned long)__va(pmd_val(pmd) & _TABLE_MASK))
+#define __pgd_page(pgd) ((unsigned long)__va(pgd_val(pgd) & _TABLE_MASK))
+
+
+#define pte_none(pte) (!pte_val(pte))
+#define pte_present(pte) (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROTNONE))
+#define pte_clear(mm,addr,ptep) ({ pte_val(*(ptep)) = 0; })
+
+#define pte_page(pte) virt_to_page(__va(pte_val(pte)))
+#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
+#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+
+#define pmd_none(pmd) (!pmd_val(pmd))
+#define pmd_bad(pmd) ((pmd_val(pmd) & _DESCTYPE_MASK) != _PAGE_TABLE)
+#define pmd_present(pmd) (pmd_val(pmd) & _PAGE_TABLE)
+#define pmd_clear(pmdp) ({ \
+ unsigned long *__ptr = pmdp->pmd; \
+ short __i = 16; \
+ while (--__i >= 0) \
+ *__ptr++ = 0; \
+})
+#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
+
+
+#define pgd_none(pgd) (!pgd_val(pgd))
+#define pgd_bad(pgd) ((pgd_val(pgd) & _DESCTYPE_MASK) != _PAGE_TABLE)
+#define pgd_present(pgd) (pgd_val(pgd) & _PAGE_TABLE)
+#define pgd_clear(pgdp) ({ pgd_val(*pgdp) = 0; })
+#define pgd_page(pgd) (mem_map + ((unsigned long)(__va(pgd_val(pgd)) - PAGE_OFFSET) >> PAGE_SHIFT))
+
+#define pte_ERROR(e) \
+ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+ printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_RONLY); }
+static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_special(pte_t pte) { return 0; }
+
+static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_RONLY; return pte; }
+static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_RONLY; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mknocache(pte_t pte)
+{
+ pte_val(pte) = (pte_val(pte) & _CACHEMASK040) | m68k_pgtable_cachemode;
+ return pte;
+}
+static inline pte_t pte_mkcache(pte_t pte)
+{
+ pte_val(pte) = (pte_val(pte) & _CACHEMASK040) | m68k_supervisor_cachemode;
+ return pte;
+}
+static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
+
+#define PAGE_DIR_OFFSET(tsk,address) pgd_offset((tsk),(address))
+
+#define pgd_index(address) ((address) >> PGDIR_SHIFT)
+
+/* to find an entry in a page-table-directory */
+static inline pgd_t *pgd_offset(const struct mm_struct *mm,
+ unsigned long address)
+{
+ return mm->pgd + pgd_index(address);
+}
+
+#define swapper_pg_dir kernel_pg_dir
+extern pgd_t kernel_pg_dir[128];
+
+static inline pgd_t *pgd_offset_k(unsigned long address)
+{
+ return kernel_pg_dir + (address >> PGDIR_SHIFT);
+}
+
+
+/* Find an entry in the second-level page table.. */
+static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
+{
+ return (pmd_t *)__pgd_page(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PMD-1));
+}
+
+/* Find an entry in the third-level page table.. */
+static inline pte_t *pte_offset_kernel(pmd_t *pmdp, unsigned long address)
+{
+ return (pte_t *)__pmd_page(*pmdp) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
+}
+
+#define pte_offset_map(pmdp,address) ((pte_t *)__pmd_page(*pmdp) + (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+#define pte_unmap(pte) ((void)0)
+
+/*
+ * Allocate and free page tables. The xxx_kernel() versions are
+ * used to allocate a kernel page table - this turns on ASN bits
+ * if any.
+ */
+
+/* Prior to calling these routines, the page should have been flushed
+ * from both the cache and ATC, or the CPU might not notice that the
+ * cache setting for the page has been changed. -jskov
+ */
+static inline void nocache_page(void *vaddr)
+{
+ unsigned long addr = (unsigned long)vaddr;
+
+ if (CPU_IS_040_OR_060) {
+ pgd_t *dir;
+ pmd_t *pmdp;
+ pte_t *ptep;
+
+ dir = pgd_offset_k(addr);
+ pmdp = pmd_offset(dir, addr);
+ ptep = pte_offset_kernel(pmdp, addr);
+ *ptep = pte_mknocache(*ptep);
+ }
+}
+
+static inline void cache_page(void *vaddr)
+{
+ unsigned long addr = (unsigned long)vaddr;
+
+ if (CPU_IS_040_OR_060) {
+ pgd_t *dir;
+ pmd_t *pmdp;
+ pte_t *ptep;
+
+ dir = pgd_offset_k(addr);
+ pmdp = pmd_offset(dir, addr);
+ ptep = pte_offset_kernel(pmdp, addr);
+ *ptep = pte_mkcache(*ptep);
+ }
+}
+
+/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
+#define __swp_type(x) (((x).val >> 4) & 0xff)
+#define __swp_offset(x) ((x).val >> 12)
+#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 12) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _MOTOROLA_PGTABLE_H */
diff --git a/arch/m68k/include/asm/movs.h b/arch/m68k/include/asm/movs.h
new file mode 100644
index 0000000..390d7b4
--- /dev/null
+++ b/arch/m68k/include/asm/movs.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __MOVS_H__
+#define __MOVS_H__
+
+/*
+** movs.h
+**
+** Inline assembly macros to generate movs & related instructions
+*/
+
+/* Set DFC register value */
+
+#define SET_DFC(x) \
+ __asm__ __volatile__ (" movec %0,%/dfc" : : "d" (x));
+
+/* Get DFC register value */
+
+#define GET_DFC(x) \
+ __asm__ __volatile__ (" movec %/dfc, %0" : "=d" (x) : );
+
+/* Set SFC register value */
+
+#define SET_SFC(x) \
+ __asm__ __volatile__ (" movec %0,%/sfc" : : "d" (x));
+
+/* Get SFC register value */
+
+#define GET_SFC(x) \
+ __asm__ __volatile__ (" movec %/sfc, %0" : "=d" (x) : );
+
+#define SET_VBR(x) \
+ __asm__ __volatile__ (" movec %0,%/vbr" : : "r" (x));
+
+#define GET_VBR(x) \
+ __asm__ __volatile__ (" movec %/vbr, %0" : "=g" (x) : );
+
+/* Set a byte using the "movs" instruction */
+
+#define SET_CONTROL_BYTE(addr,value) \
+ __asm__ __volatile__ (" movsb %0, %1@" : : "d" (value), "a" (addr));
+
+/* Get a byte using the "movs" instruction */
+
+#define GET_CONTROL_BYTE(addr,value) \
+ __asm__ __volatile__ (" movsb %1@, %0" : "=d" (value) : "a" (addr));
+
+/* Set a (long)word using the "movs" instruction */
+
+#define SET_CONTROL_WORD(addr,value) \
+ __asm__ __volatile__ (" movsl %0, %1@" : : "d" (value), "a" (addr));
+
+/* Get a (long)word using the "movs" instruction */
+
+#define GET_CONTROL_WORD(addr,value) \
+ __asm__ __volatile__ (" movsl %1@, %0" : "=d" (value) : "a" (addr));
+#endif
diff --git a/arch/m68k/include/asm/mvme147hw.h b/arch/m68k/include/asm/mvme147hw.h
new file mode 100644
index 0000000..9c7ff67
--- /dev/null
+++ b/arch/m68k/include/asm/mvme147hw.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MVME147HW_H_
+#define _MVME147HW_H_
+
+#include <asm/irq.h>
+
+typedef struct {
+ unsigned char
+ ctrl,
+ bcd_sec,
+ bcd_min,
+ bcd_hr,
+ bcd_dow,
+ bcd_dom,
+ bcd_mth,
+ bcd_year;
+} MK48T02;
+
+#define RTC_WRITE 0x80
+#define RTC_READ 0x40
+#define RTC_STOP 0x20
+
+#define m147_rtc ((MK48T02 * volatile)0xfffe07f8)
+
+
+struct pcc_regs {
+ volatile u_long dma_tadr;
+ volatile u_long dma_dadr;
+ volatile u_long dma_bcr;
+ volatile u_long dma_hr;
+ volatile u_short t1_preload;
+ volatile u_short t1_count;
+ volatile u_short t2_preload;
+ volatile u_short t2_count;
+ volatile u_char t1_int_cntrl;
+ volatile u_char t1_cntrl;
+ volatile u_char t2_int_cntrl;
+ volatile u_char t2_cntrl;
+ volatile u_char ac_fail;
+ volatile u_char watchdog;
+ volatile u_char lpt_intr;
+ volatile u_char lpt_cntrl;
+ volatile u_char dma_intr;
+ volatile u_char dma_cntrl;
+ volatile u_char bus_error;
+ volatile u_char dma_status;
+ volatile u_char abort;
+ volatile u_char ta_fnctl;
+ volatile u_char serial_cntrl;
+ volatile u_char general_cntrl;
+ volatile u_char lan_cntrl;
+ volatile u_char general_status;
+ volatile u_char scsi_interrupt;
+ volatile u_char slave;
+ volatile u_char soft1_cntrl;
+ volatile u_char int_base;
+ volatile u_char soft2_cntrl;
+ volatile u_char revision_level;
+ volatile u_char lpt_data;
+ volatile u_char lpt_status;
+ };
+
+#define m147_pcc ((struct pcc_regs * volatile)0xfffe1000)
+
+
+#define PCC_INT_ENAB 0x08
+
+#define PCC_TIMER_INT_CLR 0x80
+#define PCC_TIMER_PRELOAD 63936l
+
+#define PCC_LEVEL_ABORT 0x07
+#define PCC_LEVEL_SERIAL 0x04
+#define PCC_LEVEL_ETH 0x04
+#define PCC_LEVEL_TIMER1 0x04
+#define PCC_LEVEL_SCSI_PORT 0x04
+#define PCC_LEVEL_SCSI_DMA 0x04
+
+#define PCC_IRQ_AC_FAIL (IRQ_USER+0)
+#define PCC_IRQ_BERR (IRQ_USER+1)
+#define PCC_IRQ_ABORT (IRQ_USER+2)
+/* #define PCC_IRQ_SERIAL (IRQ_USER+3) */
+#define PCC_IRQ_PRINTER (IRQ_USER+7)
+#define PCC_IRQ_TIMER1 (IRQ_USER+8)
+#define PCC_IRQ_TIMER2 (IRQ_USER+9)
+#define PCC_IRQ_SOFTWARE1 (IRQ_USER+10)
+#define PCC_IRQ_SOFTWARE2 (IRQ_USER+11)
+
+
+#define M147_SCC_A_ADDR 0xfffe3002
+#define M147_SCC_B_ADDR 0xfffe3000
+#define M147_SCC_PCLK 5000000
+
+#define MVME147_IRQ_SCSI_PORT (IRQ_USER+0x45)
+#define MVME147_IRQ_SCSI_DMA (IRQ_USER+0x46)
+
+/* SCC interrupts, for MVME147 */
+
+#define MVME147_IRQ_TYPE_PRIO 0
+#define MVME147_IRQ_SCC_BASE (IRQ_USER+32)
+#define MVME147_IRQ_SCCB_TX (IRQ_USER+32)
+#define MVME147_IRQ_SCCB_STAT (IRQ_USER+34)
+#define MVME147_IRQ_SCCB_RX (IRQ_USER+36)
+#define MVME147_IRQ_SCCB_SPCOND (IRQ_USER+38)
+#define MVME147_IRQ_SCCA_TX (IRQ_USER+40)
+#define MVME147_IRQ_SCCA_STAT (IRQ_USER+42)
+#define MVME147_IRQ_SCCA_RX (IRQ_USER+44)
+#define MVME147_IRQ_SCCA_SPCOND (IRQ_USER+46)
+
+#define MVME147_LANCE_BASE 0xfffe1800
+#define MVME147_LANCE_IRQ (IRQ_USER+4)
+
+#define ETHERNET_ADDRESS 0xfffe0778
+
+#endif
diff --git a/arch/m68k/include/asm/mvme16xhw.h b/arch/m68k/include/asm/mvme16xhw.h
new file mode 100644
index 0000000..cc7f5ae
--- /dev/null
+++ b/arch/m68k/include/asm/mvme16xhw.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_MVME16xHW_H_
+#define _M68K_MVME16xHW_H_
+
+#include <asm/irq.h>
+
+
+typedef struct {
+ u_char ack_icr,
+ flt_icr,
+ sel_icr,
+ pe_icr,
+ bsy_icr,
+ spare1,
+ isr,
+ cr,
+ spare2,
+ spare3,
+ spare4,
+ data;
+} MVMElp, *MVMElpPtr;
+
+#define MVME_LPR_BASE 0xfff42030
+
+#define mvmelp ((*(volatile MVMElpPtr)(MVME_LPR_BASE)))
+
+typedef struct {
+ unsigned char
+ ctrl,
+ bcd_sec,
+ bcd_min,
+ bcd_hr,
+ bcd_dow,
+ bcd_dom,
+ bcd_mth,
+ bcd_year;
+} MK48T08_t, *MK48T08ptr_t;
+
+#define RTC_WRITE 0x80
+#define RTC_READ 0x40
+#define RTC_STOP 0x20
+
+#define MVME_RTC_BASE 0xfffc1ff8
+
+#define MVME_I596_BASE 0xfff46000
+
+#define MVME_SCC_A_ADDR 0xfff45005
+#define MVME_SCC_B_ADDR 0xfff45001
+#define MVME_SCC_PCLK 10000000
+
+#define MVME162_IRQ_TYPE_PRIO 0
+
+#define MVME167_IRQ_PRN (IRQ_USER+20)
+#define MVME16x_IRQ_I596 (IRQ_USER+23)
+#define MVME16x_IRQ_SCSI (IRQ_USER+21)
+#define MVME16x_IRQ_FLY (IRQ_USER+63)
+#define MVME167_IRQ_SER_ERR (IRQ_USER+28)
+#define MVME167_IRQ_SER_MODEM (IRQ_USER+29)
+#define MVME167_IRQ_SER_TX (IRQ_USER+30)
+#define MVME167_IRQ_SER_RX (IRQ_USER+31)
+#define MVME16x_IRQ_TIMER (IRQ_USER+25)
+#define MVME167_IRQ_ABORT (IRQ_USER+46)
+#define MVME162_IRQ_ABORT (IRQ_USER+30)
+
+/* SCC interrupts, for MVME162 */
+#define MVME162_IRQ_SCC_BASE (IRQ_USER+0)
+#define MVME162_IRQ_SCCB_TX (IRQ_USER+0)
+#define MVME162_IRQ_SCCB_STAT (IRQ_USER+2)
+#define MVME162_IRQ_SCCB_RX (IRQ_USER+4)
+#define MVME162_IRQ_SCCB_SPCOND (IRQ_USER+6)
+#define MVME162_IRQ_SCCA_TX (IRQ_USER+8)
+#define MVME162_IRQ_SCCA_STAT (IRQ_USER+10)
+#define MVME162_IRQ_SCCA_RX (IRQ_USER+12)
+#define MVME162_IRQ_SCCA_SPCOND (IRQ_USER+14)
+
+/* MVME162 version register */
+
+#define MVME162_VERSION_REG 0xfff4202e
+
+extern unsigned short mvme16x_config;
+
+/* Lower 8 bits must match the revision register in the MC2 chip */
+
+#define MVME16x_CONFIG_SPEED_32 0x0001
+#define MVME16x_CONFIG_NO_VMECHIP2 0x0002
+#define MVME16x_CONFIG_NO_SCSICHIP 0x0004
+#define MVME16x_CONFIG_NO_ETHERNET 0x0008
+#define MVME16x_CONFIG_GOT_FPU 0x0010
+
+#define MVME16x_CONFIG_GOT_LP 0x0100
+#define MVME16x_CONFIG_GOT_CD2401 0x0200
+#define MVME16x_CONFIG_GOT_SCCA 0x0400
+#define MVME16x_CONFIG_GOT_SCCB 0x0800
+
+#endif
diff --git a/arch/m68k/include/asm/natfeat.h b/arch/m68k/include/asm/natfeat.h
new file mode 100644
index 0000000..2d2424d
--- /dev/null
+++ b/arch/m68k/include/asm/natfeat.h
@@ -0,0 +1,23 @@
+/*
+ * ARAnyM hardware support via Native Features (natfeats)
+ *
+ * Copyright (c) 2005 Petr Stehlik of ARAnyM dev team
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL), incorporated herein by reference.
+ */
+#include <linux/compiler.h>
+
+#ifndef _NATFEAT_H
+#define _NATFEAT_H
+
+long nf_get_id(const char *feature_name);
+long nf_call(long id, ...);
+
+void nf_init(void);
+void nf_shutdown(void);
+
+void nfprint(const char *fmt, ...)
+ __printf(1, 2);
+
+# endif /* _NATFEAT_H */
diff --git a/arch/m68k/include/asm/nettel.h b/arch/m68k/include/asm/nettel.h
new file mode 100644
index 0000000..45716ea
--- /dev/null
+++ b/arch/m68k/include/asm/nettel.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/****************************************************************************/
+
+/*
+ * nettel.h -- Lineo (formerly Moreton Bay) NETtel support.
+ *
+ * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com)
+ * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com)
+ * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com)
+ */
+
+/****************************************************************************/
+#ifndef nettel_h
+#define nettel_h
+/****************************************************************************/
+
+
+/****************************************************************************/
+#ifdef CONFIG_NETtel
+/****************************************************************************/
+
+#ifdef CONFIG_COLDFIRE
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/io.h>
+#endif
+
+/*---------------------------------------------------------------------------*/
+#if defined(CONFIG_M5307)
+/*
+ * NETtel/5307 based hardware first. DTR/DCD lines are wired to
+ * GPIO lines. Most of the LED's are driver through a latch
+ * connected to CS2.
+ */
+#define MCFPP_DCD1 0x0001
+#define MCFPP_DCD0 0x0002
+#define MCFPP_DTR1 0x0004
+#define MCFPP_DTR0 0x0008
+
+#define NETtel_LEDADDR 0x30400000
+
+#ifndef __ASSEMBLY__
+
+extern volatile unsigned short ppdata;
+
+/*
+ * These functions defined to give quasi generic access to the
+ * PPIO bits used for DTR/DCD.
+ */
+static __inline__ unsigned int mcf_getppdata(void)
+{
+ volatile unsigned short *pp;
+ pp = (volatile unsigned short *) MCFSIM_PADAT;
+ return((unsigned int) *pp);
+}
+
+static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
+{
+ volatile unsigned short *pp;
+ pp = (volatile unsigned short *) MCFSIM_PADAT;
+ ppdata = (ppdata & ~mask) | bits;
+ *pp = ppdata;
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
+#elif defined(CONFIG_M5206e)
+/*
+ * NETtel/5206e based hardware has leds on latch on CS3.
+ * No support modem for lines??
+ */
+#define NETtel_LEDADDR 0x50000000
+
+/*---------------------------------------------------------------------------*/
+#elif defined(CONFIG_M5272)
+/*
+ * NETtel/5272 based hardware. DTR/DCD lines are wired to GPB lines.
+ */
+#define MCFPP_DCD0 0x0080
+#define MCFPP_DCD1 0x0000 /* Port 1 no DCD support */
+#define MCFPP_DTR0 0x0040
+#define MCFPP_DTR1 0x0000 /* Port 1 no DTR support */
+
+#ifndef __ASSEMBLY__
+/*
+ * These functions defined to give quasi generic access to the
+ * PPIO bits used for DTR/DCD.
+ */
+static __inline__ unsigned int mcf_getppdata(void)
+{
+ return readw(MCFSIM_PBDAT);
+}
+
+static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
+{
+ writew((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
+}
+#endif
+
+#endif
+/*---------------------------------------------------------------------------*/
+
+/****************************************************************************/
+#endif /* CONFIG_NETtel */
+/****************************************************************************/
+#endif /* nettel_h */
diff --git a/arch/m68k/include/asm/nubus.h b/arch/m68k/include/asm/nubus.h
new file mode 100644
index 0000000..c2281da
--- /dev/null
+++ b/arch/m68k/include/asm/nubus.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_NUBUS_H
+#define _ASM_M68K_NUBUS_H
+
+#include <asm/raw_io.h>
+#include <asm/kmap.h>
+
+#define nubus_readb raw_inb
+#define nubus_readw raw_inw
+#define nubus_readl raw_inl
+
+#define nubus_writeb raw_outb
+#define nubus_writew raw_outw
+#define nubus_writel raw_outl
+
+#define nubus_memset_io(a,b,c) memset((void *)(a),(b),(c))
+#define nubus_memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
+#define nubus_memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+
+static inline void *nubus_remap_nocache_ser(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+
+static inline void *nubus_remap_nocache_nonser(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_NONSER);
+}
+
+static inline void *nbus_remap_writethrough(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+
+static inline void *nubus_remap_fullcache(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+#define nubus_unmap iounmap
+#define nubus_iounmap iounmap
+#define nubus_ioremap nubus_remap_nocache_ser
+
+#endif /* _ASM_NUBUS_H */
diff --git a/arch/m68k/include/asm/openprom.h b/arch/m68k/include/asm/openprom.h
new file mode 100644
index 0000000..dd22e64
--- /dev/null
+++ b/arch/m68k/include/asm/openprom.h
@@ -0,0 +1,313 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SPARC_OPENPROM_H
+#define __SPARC_OPENPROM_H
+
+/* openprom.h: Prom structures and defines for access to the OPENBOOT
+ * prom routines and data areas.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+
+/* Empirical constants... */
+#ifdef CONFIG_SUN3
+#define KADB_DEBUGGER_BEGVM 0x0fee0000 /* There is no kadb yet but...*/
+#define LINUX_OPPROM_BEGVM 0x0fef0000
+#define LINUX_OPPROM_ENDVM 0x0ff10000 /* I think this is right - tm */
+#else
+#define KADB_DEBUGGER_BEGVM 0xffc00000 /* Where kern debugger is in virt-mem */
+#define LINUX_OPPROM_BEGVM 0xffd00000
+#define LINUX_OPPROM_ENDVM 0xfff00000
+#define LINUX_OPPROM_MAGIC 0x10010407
+#endif
+
+#ifndef __ASSEMBLY__
+/* V0 prom device operations. */
+struct linux_dev_v0_funcs {
+ int (*v0_devopen)(char *device_str);
+ int (*v0_devclose)(int dev_desc);
+ int (*v0_rdblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
+ int (*v0_wrblkdev)(int dev_desc, int num_blks, int blk_st, char *buf);
+ int (*v0_wrnetdev)(int dev_desc, int num_bytes, char *buf);
+ int (*v0_rdnetdev)(int dev_desc, int num_bytes, char *buf);
+ int (*v0_rdchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
+ int (*v0_wrchardev)(int dev_desc, int num_bytes, int dummy, char *buf);
+ int (*v0_seekdev)(int dev_desc, long logical_offst, int from);
+};
+
+/* V2 and later prom device operations. */
+struct linux_dev_v2_funcs {
+ int (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */
+ char * (*v2_dumb_mem_alloc)(char *va, unsigned sz);
+ void (*v2_dumb_mem_free)(char *va, unsigned sz);
+
+ /* To map devices into virtual I/O space. */
+ char * (*v2_dumb_mmap)(char *virta, int which_io, unsigned paddr, unsigned sz);
+ void (*v2_dumb_munmap)(char *virta, unsigned size);
+
+ int (*v2_dev_open)(char *devpath);
+ void (*v2_dev_close)(int d);
+ int (*v2_dev_read)(int d, char *buf, int nbytes);
+ int (*v2_dev_write)(int d, char *buf, int nbytes);
+ int (*v2_dev_seek)(int d, int hi, int lo);
+
+ /* Never issued (multistage load support) */
+ void (*v2_wheee2)(void);
+ void (*v2_wheee3)(void);
+};
+
+struct linux_mlist_v0 {
+ struct linux_mlist_v0 *theres_more;
+ char *start_adr;
+ unsigned num_bytes;
+};
+
+struct linux_mem_v0 {
+ struct linux_mlist_v0 **v0_totphys;
+ struct linux_mlist_v0 **v0_prommap;
+ struct linux_mlist_v0 **v0_available; /* What we can use */
+};
+
+/* Arguments sent to the kernel from the boot prompt. */
+struct linux_arguments_v0 {
+ char *argv[8];
+ char args[100];
+ char boot_dev[2];
+ int boot_dev_ctrl;
+ int boot_dev_unit;
+ int dev_partition;
+ char *kernel_file_name;
+ void *aieee1; /* XXX */
+};
+
+/* V2 and up boot things. */
+struct linux_bootargs_v2 {
+ char **bootpath;
+ char **bootargs;
+ int *fd_stdin;
+ int *fd_stdout;
+};
+
+#if defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
+struct linux_romvec {
+ char *pv_initsp;
+ int (*pv_startmon)(void);
+
+ int *diagberr;
+
+ struct linux_arguments_v0 **pv_v0bootargs;
+ unsigned *pv_sun3mem;
+
+ unsigned char (*pv_getchar)(void);
+ int (*pv_putchar)(int ch);
+ int (*pv_nbgetchar)(void);
+ int (*pv_nbputchar)(int ch);
+ unsigned char *pv_echo;
+ unsigned char *pv_insource;
+ unsigned char *pv_outsink;
+
+ int (*pv_getkey)(void);
+ int (*pv_initgetkey)(void);
+ unsigned int *pv_translation;
+ unsigned char *pv_keybid;
+ int *pv_screen_x;
+ int *pv_screen_y;
+ struct keybuf *pv_keybuf;
+
+ char *pv_monid;
+
+ /*
+ * Frame buffer output and terminal emulation
+ */
+
+ int (*pv_fbwritechar)(char);
+ int *pv_fbaddr;
+ char **pv_font;
+ int (*pv_fbwritestr)(char);
+
+ void (*pv_reboot)(char *bootstr);
+
+ /*
+ * Line input and parsing
+ */
+
+ unsigned char *pv_linebuf;
+ unsigned char **pv_lineptr;
+ int *pv_linesize;
+ int (*pv_getline)(void);
+ unsigned char (*pv_getnextchar)(void);
+ unsigned char (*pv_peeknextchar)(void);
+ int *pv_fbthere;
+ int (*pv_getnum)(void);
+
+ void (*pv_printf)(const char *fmt, ...);
+ int (*pv_printhex)(void);
+
+ unsigned char *pv_leds;
+ int (*pv_setleds)(void);
+
+ /*
+ * Non-maskable interrupt (nmi) information
+ */
+
+ int (*pv_nmiaddr)(void);
+ int (*pv_abortentry)(void);
+ int *pv_nmiclock;
+
+ int *pv_fbtype;
+
+ /*
+ * Assorted other things
+ */
+
+ unsigned pv_romvers;
+ struct globram *pv_globram;
+ char *pv_kbdzscc;
+
+ int *pv_keyrinit;
+ unsigned char *pv_keyrtick;
+ unsigned *pv_memoryavail;
+ long *pv_resetaddr;
+ long *pv_resetmap;
+
+ void (*pv_halt)(void);
+ unsigned char *pv_memorybitmap;
+
+#ifdef CONFIG_SUN3
+ void (*pv_setctxt)(int ctxt, char *va, int pmeg);
+ void (*pv_vector_cmd)(void);
+ int dummy1z;
+ int dummy2z;
+ int dummy3z;
+ int dummy4z;
+#endif
+};
+#else
+/* The top level PROM vector. */
+struct linux_romvec {
+ /* Version numbers. */
+ unsigned int pv_magic_cookie;
+ unsigned int pv_romvers;
+ unsigned int pv_plugin_revision;
+ unsigned int pv_printrev;
+
+ /* Version 0 memory descriptors. */
+ struct linux_mem_v0 pv_v0mem;
+
+ /* Node operations. */
+ struct linux_nodeops *pv_nodeops;
+
+ char **pv_bootstr;
+ struct linux_dev_v0_funcs pv_v0devops;
+
+ char *pv_stdin;
+ char *pv_stdout;
+#define PROMDEV_KBD 0 /* input from keyboard */
+#define PROMDEV_SCREEN 0 /* output to screen */
+#define PROMDEV_TTYA 1 /* in/out to ttya */
+#define PROMDEV_TTYB 2 /* in/out to ttyb */
+
+ /* Blocking getchar/putchar. NOT REENTRANT! (grr) */
+ int (*pv_getchar)(void);
+ void (*pv_putchar)(int ch);
+
+ /* Non-blocking variants. */
+ int (*pv_nbgetchar)(void);
+ int (*pv_nbputchar)(int ch);
+
+ void (*pv_putstr)(char *str, int len);
+
+ /* Miscellany. */
+ void (*pv_reboot)(char *bootstr);
+ void (*pv_printf)(__const__ char *fmt, ...);
+ void (*pv_abort)(void);
+ __volatile__ int *pv_ticks;
+ void (*pv_halt)(void);
+ void (**pv_synchook)(void);
+
+ /* Evaluate a forth string, not different proto for V0 and V2->up. */
+ union {
+ void (*v0_eval)(int len, char *str);
+ void (*v2_eval)(char *str);
+ } pv_fortheval;
+
+ struct linux_arguments_v0 **pv_v0bootargs;
+
+ /* Get ether address. */
+ unsigned int (*pv_enaddr)(int d, char *enaddr);
+
+ struct linux_bootargs_v2 pv_v2bootargs;
+ struct linux_dev_v2_funcs pv_v2devops;
+
+ int filler[15];
+
+ /* This one is sun4c/sun4 only. */
+ void (*pv_setctxt)(int ctxt, char *va, int pmeg);
+
+ /* Prom version 3 Multiprocessor routines. This stuff is crazy.
+ * No joke. Calling these when there is only one cpu probably
+ * crashes the machine, have to test this. :-)
+ */
+
+ /* v3_cpustart() will start the cpu 'whichcpu' in mmu-context
+ * 'thiscontext' executing at address 'prog_counter'
+ */
+ int (*v3_cpustart)(unsigned int whichcpu, int ctxtbl_ptr,
+ int thiscontext, char *prog_counter);
+
+ /* v3_cpustop() will cause cpu 'whichcpu' to stop executing
+ * until a resume cpu call is made.
+ */
+ int (*v3_cpustop)(unsigned int whichcpu);
+
+ /* v3_cpuidle() will idle cpu 'whichcpu' until a stop or
+ * resume cpu call is made.
+ */
+ int (*v3_cpuidle)(unsigned int whichcpu);
+
+ /* v3_cpuresume() will resume processor 'whichcpu' executing
+ * starting with whatever 'pc' and 'npc' were left at the
+ * last 'idle' or 'stop' call.
+ */
+ int (*v3_cpuresume)(unsigned int whichcpu);
+};
+#endif
+
+/* Routines for traversing the prom device tree. */
+struct linux_nodeops {
+ int (*no_nextnode)(int node);
+ int (*no_child)(int node);
+ int (*no_proplen)(int node, char *name);
+ int (*no_getprop)(int node, char *name, char *val);
+ int (*no_setprop)(int node, char *name, char *val, int len);
+ char * (*no_nextprop)(int node, char *name);
+};
+
+/* More fun PROM structures for device probing. */
+#define PROMREG_MAX 16
+#define PROMVADDR_MAX 16
+#define PROMINTR_MAX 15
+
+struct linux_prom_registers {
+ int which_io; /* is this in OBIO space? */
+ char *phys_addr; /* The physical address of this register */
+ int reg_size; /* How many bytes does this register take up? */
+};
+
+struct linux_prom_irqs {
+ int pri; /* IRQ priority */
+ int vector; /* This is foobar, what does it do? */
+};
+
+/* Element of the "ranges" vector */
+struct linux_prom_ranges {
+ unsigned int ot_child_space;
+ unsigned int ot_child_base; /* Bus feels this */
+ unsigned int ot_parent_space;
+ unsigned int ot_parent_base; /* CPU looks from here */
+ unsigned int or_size;
+};
+
+#endif /* !(__ASSEMBLY__) */
+
+#endif /* !(__SPARC_OPENPROM_H) */
diff --git a/arch/m68k/include/asm/oplib.h b/arch/m68k/include/asm/oplib.h
new file mode 100644
index 0000000..48cb4fd
--- /dev/null
+++ b/arch/m68k/include/asm/oplib.h
@@ -0,0 +1,292 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * oplib.h: Describes the interface and available routines in the
+ * Linux Prom library.
+ *
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ */
+
+#ifndef __SPARC_OPLIB_H
+#define __SPARC_OPLIB_H
+
+#include <asm/openprom.h>
+
+/* The master romvec pointer... */
+extern struct linux_romvec *romvec;
+
+/* Enumeration to describe the prom major version we have detected. */
+enum prom_major_version {
+ PROM_V0, /* Original sun4c V0 prom */
+ PROM_V2, /* sun4c and early sun4m V2 prom */
+ PROM_V3, /* sun4m and later, up to sun4d/sun4e machines V3 */
+ PROM_P1275, /* IEEE compliant ISA based Sun PROM, only sun4u */
+};
+
+extern enum prom_major_version prom_vers;
+/* Revision, and firmware revision. */
+extern unsigned int prom_rev, prom_prev;
+
+/* Root node of the prom device tree, this stays constant after
+ * initialization is complete.
+ */
+extern int prom_root_node;
+
+/* Pointer to prom structure containing the device tree traversal
+ * and usage utility functions. Only prom-lib should use these,
+ * users use the interface defined by the library only!
+ */
+extern struct linux_nodeops *prom_nodeops;
+
+/* The functions... */
+
+/* You must call prom_init() before using any of the library services,
+ * preferably as early as possible. Pass it the romvec pointer.
+ */
+extern void prom_init(struct linux_romvec *rom_ptr);
+
+/* Boot argument acquisition, returns the boot command line string. */
+extern char *prom_getbootargs(void);
+
+/* Device utilities. */
+
+/* Map and unmap devices in IO space at virtual addresses. Note that the
+ * virtual address you pass is a request and the prom may put your mappings
+ * somewhere else, so check your return value as that is where your new
+ * mappings really are!
+ *
+ * Another note, these are only available on V2 or higher proms!
+ */
+extern char *prom_mapio(char *virt_hint, int io_space, unsigned int phys_addr, unsigned int num_bytes);
+extern void prom_unmapio(char *virt_addr, unsigned int num_bytes);
+
+/* Device operations. */
+
+/* Open the device described by the passed string. Note, that the format
+ * of the string is different on V0 vs. V2->higher proms. The caller must
+ * know what he/she is doing! Returns the device descriptor, an int.
+ */
+extern int prom_devopen(char *device_string);
+
+/* Close a previously opened device described by the passed integer
+ * descriptor.
+ */
+extern int prom_devclose(int device_handle);
+
+/* Do a seek operation on the device described by the passed integer
+ * descriptor.
+ */
+extern void prom_seek(int device_handle, unsigned int seek_hival,
+ unsigned int seek_lowval);
+
+/* Machine memory configuration routine. */
+
+/* This function returns a V0 format memory descriptor table, it has three
+ * entries. One for the total amount of physical ram on the machine, one
+ * for the amount of physical ram available, and one describing the virtual
+ * areas which are allocated by the prom. So, in a sense the physical
+ * available is a calculation of the total physical minus the physical mapped
+ * by the prom with virtual mappings.
+ *
+ * These lists are returned pre-sorted, this should make your life easier
+ * since the prom itself is way too lazy to do such nice things.
+ */
+extern struct linux_mem_v0 *prom_meminfo(void);
+
+/* Miscellaneous routines, don't really fit in any category per se. */
+
+/* Reboot the machine with the command line passed. */
+extern void prom_reboot(char *boot_command);
+
+/* Evaluate the forth string passed. */
+extern void prom_feval(char *forth_string);
+
+/* Enter the prom, with possibility of continuation with the 'go'
+ * command in newer proms.
+ */
+extern void prom_cmdline(void);
+
+/* Enter the prom, with no chance of continuation for the stand-alone
+ * which calls this.
+ */
+extern void prom_halt(void);
+
+/* Set the PROM 'sync' callback function to the passed function pointer.
+ * When the user gives the 'sync' command at the prom prompt while the
+ * kernel is still active, the prom will call this routine.
+ *
+ * XXX The arguments are different on V0 vs. V2->higher proms, grrr! XXX
+ */
+typedef void (*sync_func_t)(void);
+extern void prom_setsync(sync_func_t func_ptr);
+
+/* Acquire the IDPROM of the root node in the prom device tree. This
+ * gets passed a buffer where you would like it stuffed. The return value
+ * is the format type of this idprom or 0xff on error.
+ */
+extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
+
+/* Get the prom major version. */
+extern int prom_version(void);
+
+/* Get the prom plugin revision. */
+extern int prom_getrev(void);
+
+/* Get the prom firmware revision. */
+extern int prom_getprev(void);
+
+/* Character operations to/from the console.... */
+
+/* Non-blocking get character from console. */
+extern int prom_nbgetchar(void);
+
+/* Non-blocking put character to console. */
+extern int prom_nbputchar(char character);
+
+/* Blocking get character from console. */
+extern char prom_getchar(void);
+
+/* Blocking put character to console. */
+extern void prom_putchar(char character);
+
+/* Prom's internal printf routine, don't use in kernel/boot code. */
+void prom_printf(char *fmt, ...);
+
+/* Query for input device type */
+
+enum prom_input_device {
+ PROMDEV_IKBD, /* input from keyboard */
+ PROMDEV_ITTYA, /* input from ttya */
+ PROMDEV_ITTYB, /* input from ttyb */
+ PROMDEV_I_UNK,
+};
+
+extern enum prom_input_device prom_query_input_device(void);
+
+/* Query for output device type */
+
+enum prom_output_device {
+ PROMDEV_OSCREEN, /* to screen */
+ PROMDEV_OTTYA, /* to ttya */
+ PROMDEV_OTTYB, /* to ttyb */
+ PROMDEV_O_UNK,
+};
+
+extern enum prom_output_device prom_query_output_device(void);
+
+/* Multiprocessor operations... */
+
+/* Start the CPU with the given device tree node, context table, and context
+ * at the passed program counter.
+ */
+extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table,
+ int context, char *program_counter);
+
+/* Stop the CPU with the passed device tree node. */
+extern int prom_stopcpu(int cpunode);
+
+/* Idle the CPU with the passed device tree node. */
+extern int prom_idlecpu(int cpunode);
+
+/* Re-Start the CPU with the passed device tree node. */
+extern int prom_restartcpu(int cpunode);
+
+/* PROM memory allocation facilities... */
+
+/* Allocated at possibly the given virtual address a chunk of the
+ * indicated size.
+ */
+extern char *prom_alloc(char *virt_hint, unsigned int size);
+
+/* Free a previously allocated chunk. */
+extern void prom_free(char *virt_addr, unsigned int size);
+
+/* Sun4/sun4c specific memory-management startup hook. */
+
+/* Map the passed segment in the given context at the passed
+ * virtual address.
+ */
+extern void prom_putsegment(int context, unsigned long virt_addr,
+ int physical_segment);
+
+/* PROM device tree traversal functions... */
+
+/* Get the child node of the given node, or zero if no child exists. */
+extern int prom_getchild(int parent_node);
+
+/* Get the next sibling node of the given node, or zero if no further
+ * siblings exist.
+ */
+extern int prom_getsibling(int node);
+
+/* Get the length, at the passed node, of the given property type.
+ * Returns -1 on error (ie. no such property at this node).
+ */
+extern int prom_getproplen(int thisnode, char *property);
+
+/* Fetch the requested property using the given buffer. Returns
+ * the number of bytes the prom put into your buffer or -1 on error.
+ */
+extern int prom_getproperty(int thisnode, char *property,
+ char *prop_buffer, int propbuf_size);
+
+/* Acquire an integer property. */
+extern int prom_getint(int node, char *property);
+
+/* Acquire an integer property, with a default value. */
+extern int prom_getintdefault(int node, char *property, int defval);
+
+/* Acquire a boolean property, 0=FALSE 1=TRUE. */
+extern int prom_getbool(int node, char *prop);
+
+/* Acquire a string property, null string on error. */
+extern void prom_getstring(int node, char *prop, char *buf, int bufsize);
+
+/* Does the passed node have the given "name"? YES=1 NO=0 */
+extern int prom_nodematch(int thisnode, char *name);
+
+/* Search all siblings starting at the passed node for "name" matching
+ * the given string. Returns the node on success, zero on failure.
+ */
+extern int prom_searchsiblings(int node_start, char *name);
+
+/* Return the first property type, as a string, for the given node.
+ * Returns a null string on error.
+ */
+extern char *prom_firstprop(int node);
+
+/* Returns the next property after the passed property for the given
+ * node. Returns null string on failure.
+ */
+extern char *prom_nextprop(int node, char *prev_property);
+
+/* Returns 1 if the specified node has given property. */
+extern int prom_node_has_property(int node, char *property);
+
+/* Set the indicated property at the given node with the passed value.
+ * Returns the number of bytes of your value that the prom took.
+ */
+extern int prom_setprop(int node, char *prop_name, char *prop_value,
+ int value_size);
+
+extern int prom_pathtoinode(char *path);
+extern int prom_inst2pkg(int);
+
+/* Dorking with Bus ranges... */
+
+/* Adjust reg values with the passed ranges. */
+extern void prom_adjust_regs(struct linux_prom_registers *regp, int nregs,
+ struct linux_prom_ranges *rangep, int nranges);
+
+/* Adjust child ranges with the passed parent ranges. */
+extern void prom_adjust_ranges(struct linux_prom_ranges *cranges, int ncranges,
+ struct linux_prom_ranges *pranges, int npranges);
+
+/* Apply promlib probed OBIO ranges to registers. */
+extern void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nregs);
+
+/* Apply ranges of any prom node (and optionally parent node as well) to registers. */
+extern void prom_apply_generic_ranges(int node, int parent,
+ struct linux_prom_registers *sbusregs, int nregs);
+
+
+#endif /* !(__SPARC_OPLIB_H) */
diff --git a/arch/m68k/include/asm/page.h b/arch/m68k/include/asm/page.h
new file mode 100644
index 0000000..700d819
--- /dev/null
+++ b/arch/m68k/include/asm/page.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_PAGE_H
+#define _M68K_PAGE_H
+
+#include <linux/const.h>
+#include <asm/setup.h>
+#include <asm/page_offset.h>
+
+/* PAGE_SHIFT determines the page size */
+#if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE)
+#define PAGE_SHIFT 13
+#else
+#define PAGE_SHIFT 12
+#endif
+#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
+#define PAGE_MASK (~(PAGE_SIZE-1))
+#define PAGE_OFFSET (PAGE_OFFSET_RAW)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { unsigned long pte; } pte_t;
+typedef struct { unsigned long pmd[16]; } pmd_t;
+typedef struct { unsigned long pgd; } pgd_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct page *pgtable_t;
+
+#define pte_val(x) ((x).pte)
+#define pmd_val(x) ((&x)->pmd[0])
+#define pgd_val(x) ((x).pgd)
+#define pgprot_val(x) ((x).pgprot)
+
+#define __pte(x) ((pte_t) { (x) } )
+#define __pmd(x) ((pmd_t) { { (x) }, })
+#define __pgd(x) ((pgd_t) { (x) } )
+#define __pgprot(x) ((pgprot_t) { (x) } )
+
+extern unsigned long _rambase;
+extern unsigned long _ramstart;
+extern unsigned long _ramend;
+
+#endif /* !__ASSEMBLY__ */
+
+#ifdef CONFIG_MMU
+#include <asm/page_mm.h>
+#else
+#include <asm/page_no.h>
+#endif
+
+#define __phys_to_pfn(paddr) ((unsigned long)((paddr) >> PAGE_SHIFT))
+#define __pfn_to_phys(pfn) PFN_PHYS(pfn)
+
+#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/getorder.h>
+
+#endif /* _M68K_PAGE_H */
diff --git a/arch/m68k/include/asm/page_mm.h b/arch/m68k/include/asm/page_mm.h
new file mode 100644
index 0000000..e6b7599
--- /dev/null
+++ b/arch/m68k/include/asm/page_mm.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_PAGE_MM_H
+#define _M68K_PAGE_MM_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/compiler.h>
+#include <asm/module.h>
+
+/*
+ * We don't need to check for alignment etc.
+ */
+#ifdef CPU_M68040_OR_M68060_ONLY
+static inline void copy_page(void *to, void *from)
+{
+ unsigned long tmp;
+
+ __asm__ __volatile__("1:\t"
+ ".chip 68040\n\t"
+ "move16 %1@+,%0@+\n\t"
+ "move16 %1@+,%0@+\n\t"
+ ".chip 68k\n\t"
+ "dbra %2,1b\n\t"
+ : "=a" (to), "=a" (from), "=d" (tmp)
+ : "0" (to), "1" (from) , "2" (PAGE_SIZE / 32 - 1)
+ );
+}
+
+static inline void clear_page(void *page)
+{
+ unsigned long tmp;
+ unsigned long *sp = page;
+
+ *sp++ = 0;
+ *sp++ = 0;
+ *sp++ = 0;
+ *sp++ = 0;
+
+ __asm__ __volatile__("1:\t"
+ ".chip 68040\n\t"
+ "move16 %2@+,%0@+\n\t"
+ ".chip 68k\n\t"
+ "subqw #8,%2\n\t"
+ "subqw #8,%2\n\t"
+ "dbra %1,1b\n\t"
+ : "=a" (sp), "=d" (tmp)
+ : "a" (page), "0" (sp),
+ "1" ((PAGE_SIZE - 16) / 16 - 1));
+}
+
+#else
+#define clear_page(page) memset((page), 0, PAGE_SIZE)
+#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
+#endif
+
+#define clear_user_page(addr, vaddr, page) \
+ do { clear_page(addr); \
+ flush_dcache_page(page); \
+ } while (0)
+#define copy_user_page(to, from, vaddr, page) \
+ do { copy_page(to, from); \
+ flush_dcache_page(page); \
+ } while (0)
+
+extern unsigned long m68k_memoffset;
+
+#ifndef CONFIG_SUN3
+
+#define WANT_PAGE_VIRTUAL
+
+static inline unsigned long ___pa(void *vaddr)
+{
+ unsigned long paddr;
+ asm (
+ "1: addl #0,%0\n"
+ m68k_fixup(%c2, 1b+2)
+ : "=r" (paddr)
+ : "0" (vaddr), "i" (m68k_fixup_memoffset));
+ return paddr;
+}
+#define __pa(vaddr) ___pa((void *)(long)(vaddr))
+static inline void *__va(unsigned long paddr)
+{
+ void *vaddr;
+ asm (
+ "1: subl #0,%0\n"
+ m68k_fixup(%c2, 1b+2)
+ : "=r" (vaddr)
+ : "0" (paddr), "i" (m68k_fixup_memoffset));
+ return vaddr;
+}
+
+#else /* !CONFIG_SUN3 */
+/* This #define is a horrible hack to suppress lots of warnings. --m */
+#define __pa(x) ___pa((unsigned long)(x))
+static inline unsigned long ___pa(unsigned long x)
+{
+ if(x == 0)
+ return 0;
+ if(x >= PAGE_OFFSET)
+ return (x-PAGE_OFFSET);
+ else
+ return (x+0x2000000);
+}
+
+static inline void *__va(unsigned long x)
+{
+ if(x == 0)
+ return (void *)0;
+
+ if(x < 0x2000000)
+ return (void *)(x+PAGE_OFFSET);
+ else
+ return (void *)(x-0x2000000);
+}
+#endif /* CONFIG_SUN3 */
+
+/*
+ * NOTE: virtual isn't really correct, actually it should be the offset into the
+ * memory node, but we have no highmem, so that works for now.
+ * TODO: implement (fast) pfn<->pgdat_idx conversion functions, this makes lots
+ * of the shifts unnecessary.
+ */
+#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
+#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
+
+extern int m68k_virt_to_node_shift;
+
+#ifdef CONFIG_SINGLE_MEMORY_CHUNK
+#define __virt_to_node(addr) (&pg_data_map[0])
+#else
+extern struct pglist_data *pg_data_table[];
+
+static inline __attribute_const__ int __virt_to_node_shift(void)
+{
+ int shift;
+
+ asm (
+ "1: moveq #0,%0\n"
+ m68k_fixup(%c1, 1b)
+ : "=d" (shift)
+ : "i" (m68k_fixup_vnode_shift));
+ return shift;
+}
+
+#define __virt_to_node(addr) (pg_data_table[(unsigned long)(addr) >> __virt_to_node_shift()])
+#endif
+
+#define virt_to_page(addr) ({ \
+ pfn_to_page(virt_to_pfn(addr)); \
+})
+#define page_to_virt(page) ({ \
+ pfn_to_virt(page_to_pfn(page)); \
+})
+
+#define pfn_to_page(pfn) ({ \
+ unsigned long __pfn = (pfn); \
+ struct pglist_data *pgdat; \
+ pgdat = __virt_to_node((unsigned long)pfn_to_virt(__pfn)); \
+ pgdat->node_mem_map + (__pfn - pgdat->node_start_pfn); \
+})
+#define page_to_pfn(_page) ({ \
+ const struct page *__p = (_page); \
+ struct pglist_data *pgdat; \
+ pgdat = &pg_data_map[page_to_nid(__p)]; \
+ ((__p) - pgdat->node_mem_map) + pgdat->node_start_pfn; \
+})
+
+#define virt_addr_valid(kaddr) ((void *)(kaddr) >= (void *)PAGE_OFFSET && (void *)(kaddr) < high_memory)
+#define pfn_valid(pfn) virt_addr_valid(pfn_to_virt(pfn))
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _M68K_PAGE_MM_H */
diff --git a/arch/m68k/include/asm/page_no.h b/arch/m68k/include/asm/page_no.h
new file mode 100644
index 0000000..6bbe520
--- /dev/null
+++ b/arch/m68k/include/asm/page_no.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_PAGE_NO_H
+#define _M68K_PAGE_NO_H
+
+#ifndef __ASSEMBLY__
+
+extern unsigned long memory_start;
+extern unsigned long memory_end;
+
+#define clear_page(page) memset((page), 0, PAGE_SIZE)
+#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
+
+#define clear_user_page(page, vaddr, pg) clear_page(page)
+#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
+
+#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
+ alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
+#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
+
+#define __pa(vaddr) ((unsigned long)(vaddr))
+#define __va(paddr) ((void *)((unsigned long)(paddr)))
+
+#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
+#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT)
+
+#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
+#define page_to_virt(page) __va(((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET))
+
+#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn))
+#define page_to_pfn(page) virt_to_pfn(page_to_virt(page))
+#define pfn_valid(pfn) ((pfn) < max_mapnr)
+
+#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
+ ((void *)(kaddr) < (void *)memory_end))
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _M68K_PAGE_NO_H */
diff --git a/arch/m68k/include/asm/page_offset.h b/arch/m68k/include/asm/page_offset.h
new file mode 100644
index 0000000..11dc3cb
--- /dev/null
+++ b/arch/m68k/include/asm/page_offset.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* This handles the memory map.. */
+
+#if defined(CONFIG_RAMBASE)
+#define PAGE_OFFSET_RAW CONFIG_RAMBASE
+#elif defined(CONFIG_SUN3)
+#define PAGE_OFFSET_RAW 0x0E000000
+#else
+#define PAGE_OFFSET_RAW 0x00000000
+#endif
diff --git a/arch/m68k/include/asm/parport.h b/arch/m68k/include/asm/parport.h
new file mode 100644
index 0000000..becfebd
--- /dev/null
+++ b/arch/m68k/include/asm/parport.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * parport.h: platform-specific PC-style parport initialisation
+ *
+ * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
+ *
+ * This file should only be included by drivers/parport/parport_pc.c.
+ *
+ * RZ: for use with Q40 and other ISA machines
+ */
+
+#ifndef _ASM_M68K_PARPORT_H
+#define _ASM_M68K_PARPORT_H 1
+
+#undef insl
+#undef outsl
+#define insl(port,buf,len) isa_insb(port,buf,(len)<<2)
+#define outsl(port,buf,len) isa_outsb(port,buf,(len)<<2)
+
+/* no dma, or IRQ autoprobing */
+static int parport_pc_find_isa_ports (int autoirq, int autodma);
+static int parport_pc_find_nonpci_ports (int autoirq, int autodma)
+{
+ if (! (MACH_IS_Q40))
+ return 0; /* count=0 */
+ return parport_pc_find_isa_ports (PARPORT_IRQ_NONE, PARPORT_DMA_NONE);
+}
+
+#endif /* !(_ASM_M68K_PARPORT_H) */
diff --git a/arch/m68k/include/asm/pci.h b/arch/m68k/include/asm/pci.h
new file mode 100644
index 0000000..5a4bc22
--- /dev/null
+++ b/arch/m68k/include/asm/pci.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_PCI_H
+#define _ASM_M68K_PCI_H
+
+#include <asm-generic/pci.h>
+
+#define pcibios_assign_all_busses() 1
+
+#define PCIBIOS_MIN_IO 0x00000100
+#define PCIBIOS_MIN_MEM 0x02000000
+
+#endif /* _ASM_M68K_PCI_H */
diff --git a/arch/m68k/include/asm/pgalloc.h b/arch/m68k/include/asm/pgalloc.h
new file mode 100644
index 0000000..24ca46d
--- /dev/null
+++ b/arch/m68k/include/asm/pgalloc.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef M68K_PGALLOC_H
+#define M68K_PGALLOC_H
+
+#include <linux/mm.h>
+#include <linux/highmem.h>
+#include <asm/setup.h>
+
+#ifdef CONFIG_MMU
+#include <asm/virtconvert.h>
+#if defined(CONFIG_COLDFIRE)
+#include <asm/mcf_pgalloc.h>
+#elif defined(CONFIG_SUN3)
+#include <asm/sun3_pgalloc.h>
+#else
+#include <asm/motorola_pgalloc.h>
+#endif
+
+extern void m68k_setup_node(int node);
+#endif
+
+#endif /* M68K_PGALLOC_H */
diff --git a/arch/m68k/include/asm/pgtable.h b/arch/m68k/include/asm/pgtable.h
new file mode 100644
index 0000000..ad15d65
--- /dev/null
+++ b/arch/m68k/include/asm/pgtable.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifdef __uClinux__
+#include <asm/pgtable_no.h>
+#else
+#include <asm/pgtable_mm.h>
+#endif
diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h
new file mode 100644
index 0000000..fe3ddd7
--- /dev/null
+++ b/arch/m68k/include/asm/pgtable_mm.h
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_PGTABLE_H
+#define _M68K_PGTABLE_H
+
+#include <asm-generic/4level-fixup.h>
+
+#include <asm/setup.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/processor.h>
+#include <linux/sched.h>
+#include <linux/threads.h>
+
+/*
+ * This file contains the functions and defines necessary to modify and use
+ * the m68k page table tree.
+ */
+
+#include <asm/virtconvert.h>
+
+/* Certain architectures need to do special things when pte's
+ * within a page table are directly modified. Thus, the following
+ * hook is made available.
+ */
+#define set_pte(pteptr, pteval) \
+ do{ \
+ *(pteptr) = (pteval); \
+ } while(0)
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+
+/* PMD_SHIFT determines the size of the area a second-level page table can map */
+#ifdef CONFIG_SUN3
+#define PMD_SHIFT 17
+#else
+#define PMD_SHIFT 22
+#endif
+#define PMD_SIZE (1UL << PMD_SHIFT)
+#define PMD_MASK (~(PMD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#ifdef CONFIG_SUN3
+#define PGDIR_SHIFT 17
+#elif defined(CONFIG_COLDFIRE)
+#define PGDIR_SHIFT 22
+#else
+#define PGDIR_SHIFT 25
+#endif
+#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE-1))
+
+/*
+ * entries per page directory level: the m68k is configured as three-level,
+ * so we do have PMD level physically.
+ */
+#ifdef CONFIG_SUN3
+#define PTRS_PER_PTE 16
+#define __PAGETABLE_PMD_FOLDED 1
+#define PTRS_PER_PMD 1
+#define PTRS_PER_PGD 2048
+#elif defined(CONFIG_COLDFIRE)
+#define PTRS_PER_PTE 512
+#define __PAGETABLE_PMD_FOLDED 1
+#define PTRS_PER_PMD 1
+#define PTRS_PER_PGD 1024
+#else
+#define PTRS_PER_PTE 1024
+#define PTRS_PER_PMD 8
+#define PTRS_PER_PGD 128
+#endif
+#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
+#define FIRST_USER_ADDRESS 0UL
+
+/* Virtual address region for use by kernel_map() */
+#ifdef CONFIG_SUN3
+#define KMAP_START 0x0DC00000
+#define KMAP_END 0x0E000000
+#elif defined(CONFIG_COLDFIRE)
+#define KMAP_START 0xe0000000
+#define KMAP_END 0xf0000000
+#else
+#define KMAP_START 0xd0000000
+#define KMAP_END 0xf0000000
+#endif
+
+#ifdef CONFIG_SUN3
+extern unsigned long m68k_vmalloc_end;
+#define VMALLOC_START 0x0f800000
+#define VMALLOC_END m68k_vmalloc_end
+#elif defined(CONFIG_COLDFIRE)
+#define VMALLOC_START 0xd0000000
+#define VMALLOC_END 0xe0000000
+#else
+/* Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts. That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET (8*1024*1024)
+#define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END KMAP_START
+#endif
+
+/* zero page used for uninitialized stuff */
+extern void *empty_zero_page;
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+
+/* number of bits that fit into a memory pointer */
+#define BITS_PER_PTR (8*sizeof(unsigned long))
+
+/* to align the pointer to a pointer address */
+#define PTR_MASK (~(sizeof(void*)-1))
+
+/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
+/* 64-bit machines, beware! SRB. */
+#define SIZEOF_PTR_LOG2 2
+
+extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode);
+
+/*
+ * The m68k doesn't have any external MMU info: the kernel page
+ * tables contain all the necessary information. The Sun3 does, but
+ * they are updated on demand.
+ */
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+ unsigned long address, pte_t *ptep)
+{
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#define kern_addr_valid(addr) (1)
+
+/* MMU-specific headers */
+
+#ifdef CONFIG_SUN3
+#include <asm/sun3_pgtable.h>
+#elif defined(CONFIG_COLDFIRE)
+#include <asm/mcf_pgtable.h>
+#else
+#include <asm/motorola_pgtable.h>
+#endif
+
+#ifndef __ASSEMBLY__
+/*
+ * Macro to mark a page protection value as "uncacheable".
+ */
+#ifdef CONFIG_COLDFIRE
+# define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | CF_PAGE_NOCACHE))
+#else
+#ifdef SUN3_PAGE_NOCACHE
+# define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE
+#else
+# define __SUN3_PAGE_NOCACHE 0
+#endif
+#define pgprot_noncached(prot) \
+ (MMU_IS_SUN3 \
+ ? (__pgprot(pgprot_val(prot) | __SUN3_PAGE_NOCACHE)) \
+ : ((MMU_IS_851 || MMU_IS_030) \
+ ? (__pgprot(pgprot_val(prot) | _PAGE_NOCACHE030)) \
+ : (MMU_IS_040 || MMU_IS_060) \
+ ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \
+ : (prot)))
+
+#endif /* CONFIG_COLDFIRE */
+#include <asm-generic/pgtable.h>
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init() do { } while (0)
+
+#define check_pgt_cache() do { } while (0)
+
+#endif /* _M68K_PGTABLE_H */
diff --git a/arch/m68k/include/asm/pgtable_no.h b/arch/m68k/include/asm/pgtable_no.h
new file mode 100644
index 0000000..fc3a96c
--- /dev/null
+++ b/arch/m68k/include/asm/pgtable_no.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68KNOMMU_PGTABLE_H
+#define _M68KNOMMU_PGTABLE_H
+
+#include <asm-generic/4level-fixup.h>
+
+/*
+ * (C) Copyright 2000-2002, Greg Ungerer <gerg@snapgear.com>
+ */
+
+#include <linux/slab.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/io.h>
+
+/*
+ * Trivial page table functions.
+ */
+#define pgd_present(pgd) (1)
+#define pgd_none(pgd) (0)
+#define pgd_bad(pgd) (0)
+#define pgd_clear(pgdp)
+#define kern_addr_valid(addr) (1)
+#define pmd_offset(a, b) ((void *)0)
+
+#define PAGE_NONE __pgprot(0)
+#define PAGE_SHARED __pgprot(0)
+#define PAGE_COPY __pgprot(0)
+#define PAGE_READONLY __pgprot(0)
+#define PAGE_KERNEL __pgprot(0)
+
+extern void paging_init(void);
+#define swapper_pg_dir ((pgd_t *) 0)
+
+#define __swp_type(x) (0)
+#define __swp_offset(x) (0)
+#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+#define ZERO_PAGE(vaddr) (virt_to_page(0))
+
+/*
+ * No page table caches to initialise.
+ */
+#define pgtable_cache_init() do { } while (0)
+
+/*
+ * All 32bit addresses are effectively valid for vmalloc...
+ * Sort of meaningless for non-VM targets.
+ */
+#define VMALLOC_START 0
+#define VMALLOC_END 0xffffffff
+#define KMAP_START 0
+#define KMAP_END 0xffffffff
+
+#include <asm-generic/pgtable.h>
+
+#define check_pgt_cache() do { } while (0)
+
+#endif /* _M68KNOMMU_PGTABLE_H */
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h
new file mode 100644
index 0000000..464e9f5
--- /dev/null
+++ b/arch/m68k/include/asm/processor.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/asm-m68k/processor.h
+ *
+ * Copyright (C) 1995 Hamish Macdonald
+ */
+
+#ifndef __ASM_M68K_PROCESSOR_H
+#define __ASM_M68K_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#include <linux/thread_info.h>
+#include <asm/segment.h>
+#include <asm/fpu.h>
+#include <asm/ptrace.h>
+
+static inline unsigned long rdusp(void)
+{
+#ifdef CONFIG_COLDFIRE_SW_A7
+ extern unsigned int sw_usp;
+ return sw_usp;
+#else
+ register unsigned long usp __asm__("a0");
+ /* move %usp,%a0 */
+ __asm__ __volatile__(".word 0x4e68" : "=a" (usp));
+ return usp;
+#endif
+}
+
+static inline void wrusp(unsigned long usp)
+{
+#ifdef CONFIG_COLDFIRE_SW_A7
+ extern unsigned int sw_usp;
+ sw_usp = usp;
+#else
+ register unsigned long a0 __asm__("a0") = usp;
+ /* move %a0,%usp */
+ __asm__ __volatile__(".word 0x4e60" : : "a" (a0) );
+#endif
+}
+
+/*
+ * User space process size: 3.75GB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.
+ */
+#ifdef CONFIG_MMU
+#if defined(CONFIG_COLDFIRE)
+#define TASK_SIZE (0xC0000000UL)
+#elif defined(CONFIG_SUN3)
+#define TASK_SIZE (0x0E000000UL)
+#else
+#define TASK_SIZE (0xF0000000UL)
+#endif
+#else
+#define TASK_SIZE (0xFFFFFFFFUL)
+#endif
+
+#ifdef __KERNEL__
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
+#endif
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#ifdef CONFIG_MMU
+#if defined(CONFIG_COLDFIRE)
+#define TASK_UNMAPPED_BASE 0x60000000UL
+#elif defined(CONFIG_SUN3)
+#define TASK_UNMAPPED_BASE 0x0A000000UL
+#else
+#define TASK_UNMAPPED_BASE 0xC0000000UL
+#endif
+#define TASK_UNMAPPED_ALIGN(addr, off) PAGE_ALIGN(addr)
+#else
+#define TASK_UNMAPPED_BASE 0
+#endif
+
+struct thread_struct {
+ unsigned long ksp; /* kernel stack pointer */
+ unsigned long usp; /* user stack pointer */
+ unsigned short sr; /* saved status register */
+ unsigned short fs; /* saved fs (sfc, dfc) */
+ unsigned long crp[2]; /* cpu root pointer */
+ unsigned long esp0; /* points to SR of stack frame */
+ unsigned long faddr; /* info about last fault */
+ int signo, code;
+ unsigned long fp[8*3];
+ unsigned long fpcntl[3]; /* fp control regs */
+ unsigned char fpstate[FPSTATESIZE]; /* floating point state */
+};
+
+#define INIT_THREAD { \
+ .ksp = sizeof(init_stack) + (unsigned long) init_stack, \
+ .sr = PS_S, \
+ .fs = __KERNEL_DS, \
+}
+
+/*
+ * ColdFire stack format sbould be 0x4 for an aligned usp (will always be
+ * true on thread creation). We need to set this explicitly.
+ */
+#ifdef CONFIG_COLDFIRE
+#define setframeformat(_regs) do { (_regs)->format = 0x4; } while(0)
+#else
+#define setframeformat(_regs) do { } while (0)
+#endif
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+static inline void start_thread(struct pt_regs * regs, unsigned long pc,
+ unsigned long usp)
+{
+ regs->pc = pc;
+ regs->sr &= ~0x2000;
+ setframeformat(regs);
+ wrusp(usp);
+}
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+static inline void release_thread(struct task_struct *dead_task)
+{
+}
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk) \
+ ({ \
+ unsigned long eip = 0; \
+ if ((tsk)->thread.esp0 > PAGE_SIZE && \
+ (virt_addr_valid((tsk)->thread.esp0))) \
+ eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
+ eip; })
+#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
+
+#define task_pt_regs(tsk) ((struct pt_regs *) ((tsk)->thread.esp0))
+
+#define cpu_relax() barrier()
+
+#endif
diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h
new file mode 100644
index 0000000..ea5a80c
--- /dev/null
+++ b/arch/m68k/include/asm/ptrace.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_PTRACE_H
+#define _M68K_PTRACE_H
+
+#include <uapi/asm/ptrace.h>
+
+#ifndef __ASSEMBLY__
+
+#ifndef PS_S
+#define PS_S (0x2000)
+#define PS_M (0x1000)
+#endif
+
+#define user_mode(regs) (!((regs)->sr & PS_S))
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+#define current_pt_regs() \
+ (struct pt_regs *)((char *)current_thread_info() + THREAD_SIZE) - 1
+#define current_user_stack_pointer() rdusp()
+
+#define arch_has_single_step() (1)
+
+#ifdef CONFIG_MMU
+#define arch_has_block_step() (1)
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* _M68K_PTRACE_H */
diff --git a/arch/m68k/include/asm/q40_master.h b/arch/m68k/include/asm/q40_master.h
new file mode 100644
index 0000000..9b00fb8
--- /dev/null
+++ b/arch/m68k/include/asm/q40_master.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Q40 master Chip Control
+ * RTC stuff merged for compactness.
+*/
+
+#ifndef _Q40_MASTER_H
+#define _Q40_MASTER_H
+
+#include <asm/raw_io.h>
+#include <asm/kmap.h>
+
+#define q40_master_addr 0xff000000
+
+#define IIRQ_REG 0x0 /* internal IRQ reg */
+#define EIRQ_REG 0x4 /* external ... */
+#define KEYCODE_REG 0x1c /* value of received scancode */
+#define DISPLAY_CONTROL_REG 0x18
+#define FRAME_CLEAR_REG 0x24
+#define LED_REG 0x30
+
+#define Q40_LED_ON() master_outb(1,LED_REG)
+#define Q40_LED_OFF() master_outb(0,LED_REG)
+
+#define INTERRUPT_REG IIRQ_REG /* "native" ints */
+#define KEY_IRQ_ENABLE_REG 0x08 /**/
+#define KEYBOARD_UNLOCK_REG 0x20 /* clear kb int */
+
+#define SAMPLE_ENABLE_REG 0x14 /* generate SAMPLE ints */
+#define SAMPLE_RATE_REG 0x2c
+#define SAMPLE_CLEAR_REG 0x28
+#define SAMPLE_LOW 0x00
+#define SAMPLE_HIGH 0x01
+
+#define FRAME_RATE_REG 0x38 /* generate FRAME ints at 200 HZ rate */
+
+#if 0
+#define SER_ENABLE_REG 0x0c /* allow serial ints to be generated */
+#endif
+#define EXT_ENABLE_REG 0x10 /* ... rest of the ISA ints ... */
+
+
+#define master_inb(_reg_) in_8((unsigned char *)q40_master_addr+_reg_)
+#define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_)
+
+/* RTC defines */
+
+#define Q40_RTC_BASE (0xff021ffc)
+
+#define Q40_RTC_YEAR (*(volatile unsigned char *)(Q40_RTC_BASE+0))
+#define Q40_RTC_MNTH (*(volatile unsigned char *)(Q40_RTC_BASE-4))
+#define Q40_RTC_DATE (*(volatile unsigned char *)(Q40_RTC_BASE-8))
+#define Q40_RTC_DOW (*(volatile unsigned char *)(Q40_RTC_BASE-12))
+#define Q40_RTC_HOUR (*(volatile unsigned char *)(Q40_RTC_BASE-16))
+#define Q40_RTC_MINS (*(volatile unsigned char *)(Q40_RTC_BASE-20))
+#define Q40_RTC_SECS (*(volatile unsigned char *)(Q40_RTC_BASE-24))
+#define Q40_RTC_CTRL (*(volatile unsigned char *)(Q40_RTC_BASE-28))
+
+/* some control bits */
+#define Q40_RTC_READ 64 /* prepare for reading */
+#define Q40_RTC_WRITE 128
+
+/* define some Q40 specific ints */
+#include <asm/q40ints.h>
+
+/* misc defs */
+#define DAC_LEFT ((unsigned char *)0xff008000)
+#define DAC_RIGHT ((unsigned char *)0xff008004)
+
+#endif /* _Q40_MASTER_H */
diff --git a/arch/m68k/include/asm/q40ints.h b/arch/m68k/include/asm/q40ints.h
new file mode 100644
index 0000000..7c93ac4
--- /dev/null
+++ b/arch/m68k/include/asm/q40ints.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * contains some Q40 related interrupt definitions
+ */
+
+#define Q40_IRQ_MAX (34)
+
+#define Q40_IRQ_SAMPLE (34)
+#define Q40_IRQ_KEYBOARD (32)
+#define Q40_IRQ_FRAME (33)
+
+
+/* masks for interrupt regiosters*/
+/* internal, IIRQ_REG */
+#define Q40_IRQ_KEYB_MASK (2)
+#define Q40_IRQ_SER_MASK (1<<2)
+#define Q40_IRQ_FRAME_MASK (1<<3)
+#define Q40_IRQ_EXT_MASK (1<<4) /* is a EIRQ */
+/* eirq, EIRQ_REG */
+#define Q40_IRQ3_MASK (1)
+#define Q40_IRQ4_MASK (1<<1)
+#define Q40_IRQ5_MASK (1<<2)
+#define Q40_IRQ6_MASK (1<<3)
+#define Q40_IRQ7_MASK (1<<4)
+#define Q40_IRQ10_MASK (1<<5)
+#define Q40_IRQ14_MASK (1<<6)
+#define Q40_IRQ15_MASK (1<<7)
diff --git a/arch/m68k/include/asm/quicc_simple.h b/arch/m68k/include/asm/quicc_simple.h
new file mode 100644
index 0000000..b9e2808
--- /dev/null
+++ b/arch/m68k/include/asm/quicc_simple.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/***********************************
+ * $Id: quicc_simple.h,v 1.1 2002/03/02 15:01:10 gerg Exp $
+ ***********************************
+ *
+ ***************************************
+ * Simple drivers common header
+ ***************************************
+ */
+
+#ifndef __SIMPLE_H
+#define __SIMPLE_H
+
+/* #include "quicc.h" */
+
+#define GLB_SCC_0 0
+#define GLB_SCC_1 1
+#define GLB_SCC_2 2
+#define GLB_SCC_3 3
+
+typedef void (int_routine)(unsigned short interrupt_event);
+typedef int_routine *int_routine_ptr;
+typedef void *(alloc_routine)(int length);
+typedef void (free_routine)(int scc_num, int channel_num, void *buf);
+typedef void (store_rx_buffer_routine)(int scc_num, int channel_num, void *buff, int length);
+typedef int (handle_tx_error_routine)(int scc_num, int channel_num, QUICC_BD *tbd);
+typedef void (handle_rx_error_routine)(int scc_num, int channel_num, QUICC_BD *rbd);
+typedef void (handle_lost_error_routine)(int scc_num, int channel_num);
+
+/* user defined functions for global errors */
+typedef void (handle_glob_overrun_routine)(int scc_number);
+typedef void (handle_glob_underrun_routine)(int scc_number);
+typedef void (glob_intr_q_overflow_routine)(int scc_number);
+
+/*
+ * General initialization and command routines
+ */
+void quicc_issue_cmd (unsigned short cmd, int scc_num);
+void quicc_init(void);
+void quicc_scc_init(int scc_number, int number_of_rx_buf, int number_of_tx_buf);
+void quicc_smc_init(int smc_number, int number_of_rx_buf, int number_of_tx_buf);
+void quicc_scc_start(int scc_num);
+void quicc_scc_loopback(int scc_num);
+
+/* Interrupt enable/disable routines for critical pieces of code*/
+unsigned short IntrDis(void);
+void IntrEna(unsigned short old_sr);
+
+/* For debugging */
+void print_rbd(int scc_num);
+void print_tbd(int scc_num);
+
+#endif
diff --git a/arch/m68k/include/asm/raw_io.h b/arch/m68k/include/asm/raw_io.h
new file mode 100644
index 0000000..8576125
--- /dev/null
+++ b/arch/m68k/include/asm/raw_io.h
@@ -0,0 +1,441 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * linux/include/asm-m68k/raw_io.h
+ *
+ * 10/20/00 RZ: - created from bits of io.h and ide.h to cleanup namespace
+ *
+ */
+
+#ifndef _RAW_IO_H
+#define _RAW_IO_H
+
+#ifdef __KERNEL__
+
+#include <asm/byteorder.h>
+
+/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
+ * two accesses to memory, which may be undesirable for some devices.
+ */
+#define in_8(addr) \
+ ({ u8 __v = (*(__force volatile u8 *) (addr)); __v; })
+#define in_be16(addr) \
+ ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; })
+#define in_be32(addr) \
+ ({ u32 __v = (*(__force volatile u32 *) (addr)); __v; })
+#define in_le16(addr) \
+ ({ u16 __v = le16_to_cpu(*(__force volatile __le16 *) (addr)); __v; })
+#define in_le32(addr) \
+ ({ u32 __v = le32_to_cpu(*(__force volatile __le32 *) (addr)); __v; })
+
+#define out_8(addr,b) (void)((*(__force volatile u8 *) (addr)) = (b))
+#define out_be16(addr,w) (void)((*(__force volatile u16 *) (addr)) = (w))
+#define out_be32(addr,l) (void)((*(__force volatile u32 *) (addr)) = (l))
+#define out_le16(addr,w) (void)((*(__force volatile __le16 *) (addr)) = cpu_to_le16(w))
+#define out_le32(addr,l) (void)((*(__force volatile __le32 *) (addr)) = cpu_to_le32(l))
+
+#define raw_inb in_8
+#define raw_inw in_be16
+#define raw_inl in_be32
+#define __raw_readb in_8
+#define __raw_readw in_be16
+#define __raw_readl in_be32
+
+#define raw_outb(val,port) out_8((port),(val))
+#define raw_outw(val,port) out_be16((port),(val))
+#define raw_outl(val,port) out_be32((port),(val))
+#define __raw_writeb(val,addr) out_8((addr),(val))
+#define __raw_writew(val,addr) out_be16((addr),(val))
+#define __raw_writel(val,addr) out_be32((addr),(val))
+
+/*
+ * Atari ROM port (cartridge port) ISA adapter, used for the EtherNEC NE2000
+ * network card driver.
+ * The ISA adapter connects address lines A9-A13 to ISA address lines A0-A4,
+ * and hardwires the rest of the ISA addresses for a base address of 0x300.
+ *
+ * Data lines D8-D15 are connected to ISA data lines D0-D7 for reading.
+ * For writes, address lines A1-A8 are latched to ISA data lines D0-D7
+ * (meaning the bit pattern on A1-A8 can be read back as byte).
+ *
+ * Read and write operations are distinguished by the base address used:
+ * reads are from the ROM A side range, writes are through the B side range
+ * addresses (A side base + 0x10000).
+ *
+ * Reads and writes are byte only.
+ *
+ * 16 bit reads and writes are necessary for the NetUSBee adapter's USB
+ * chipset - 16 bit words are read straight off the ROM port while 16 bit
+ * reads are split into two byte writes. The low byte is latched to the
+ * NetUSBee buffer by a read from the _read_ window (with the data pattern
+ * asserted as A1-A8 address pattern). The high byte is then written to the
+ * write range as usual, completing the write cycle.
+ */
+
+#if defined(CONFIG_ATARI_ROM_ISA)
+#define rom_in_8(addr) \
+ ({ u16 __v = (*(__force volatile u16 *) (addr)); __v >>= 8; __v; })
+#define rom_in_be16(addr) \
+ ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; })
+#define rom_in_le16(addr) \
+ ({ u16 __v = le16_to_cpu(*(__force volatile u16 *) (addr)); __v; })
+
+#define rom_out_8(addr, b) \
+ ({u8 __w, __v = (b); u32 _addr = ((u32) (addr)); \
+ __w = ((*(__force volatile u8 *) ((_addr | 0x10000) + (__v<<1)))); })
+#define rom_out_be16(addr, w) \
+ ({u16 __w, __v = (w); u32 _addr = ((u32) (addr)); \
+ __w = ((*(__force volatile u16 *) ((_addr & 0xFFFF0000UL) + ((__v & 0xFF)<<1)))); \
+ __w = ((*(__force volatile u16 *) ((_addr | 0x10000) + ((__v >> 8)<<1)))); })
+#define rom_out_le16(addr, w) \
+ ({u16 __w, __v = (w); u32 _addr = ((u32) (addr)); \
+ __w = ((*(__force volatile u16 *) ((_addr & 0xFFFF0000UL) + ((__v >> 8)<<1)))); \
+ __w = ((*(__force volatile u16 *) ((_addr | 0x10000) + ((__v & 0xFF)<<1)))); })
+
+#define raw_rom_inb rom_in_8
+#define raw_rom_inw rom_in_be16
+
+#define raw_rom_outb(val, port) rom_out_8((port), (val))
+#define raw_rom_outw(val, port) rom_out_be16((port), (val))
+#endif /* CONFIG_ATARI_ROM_ISA */
+
+static inline void raw_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len)
+{
+ unsigned int i;
+
+ for (i = 0; i < len; i++)
+ *buf++ = in_8(port);
+}
+
+static inline void raw_outsb(volatile u8 __iomem *port, const u8 *buf,
+ unsigned int len)
+{
+ unsigned int i;
+
+ for (i = 0; i < len; i++)
+ out_8(port, *buf++);
+}
+
+static inline void raw_insw(volatile u16 __iomem *port, u16 *buf, unsigned int nr)
+{
+ unsigned int tmp;
+
+ if (nr & 15) {
+ tmp = (nr & 15) - 1;
+ asm volatile (
+ "1: movew %2@,%0@+; dbra %1,1b"
+ : "=a" (buf), "=d" (tmp)
+ : "a" (port), "0" (buf),
+ "1" (tmp));
+ }
+ if (nr >> 4) {
+ tmp = (nr >> 4) - 1;
+ asm volatile (
+ "1: "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "movew %2@,%0@+; "
+ "dbra %1,1b"
+ : "=a" (buf), "=d" (tmp)
+ : "a" (port), "0" (buf),
+ "1" (tmp));
+ }
+}
+
+static inline void raw_outsw(volatile u16 __iomem *port, const u16 *buf,
+ unsigned int nr)
+{
+ unsigned int tmp;
+
+ if (nr & 15) {
+ tmp = (nr & 15) - 1;
+ asm volatile (
+ "1: movew %0@+,%2@; dbra %1,1b"
+ : "=a" (buf), "=d" (tmp)
+ : "a" (port), "0" (buf),
+ "1" (tmp));
+ }
+ if (nr >> 4) {
+ tmp = (nr >> 4) - 1;
+ asm volatile (
+ "1: "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "movew %0@+,%2@; "
+ "dbra %1,1b"
+ : "=a" (buf), "=d" (tmp)
+ : "a" (port), "0" (buf),
+ "1" (tmp));
+ }
+}
+
+static inline void raw_insl(volatile u32 __iomem *port, u32 *buf, unsigned int nr)
+{
+ unsigned int tmp;
+
+ if (nr & 15) {
+ tmp = (nr & 15) - 1;
+ asm volatile (
+ "1: movel %2@,%0@+; dbra %1,1b"
+ : "=a" (buf), "=d" (tmp)
+ : "a" (port), "0" (buf),
+ "1" (tmp));
+ }
+ if (nr >> 4) {
+ tmp = (nr >> 4) - 1;
+ asm volatile (
+ "1: "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "movel %2@,%0@+; "
+ "dbra %1,1b"
+ : "=a" (buf), "=d" (tmp)
+ : "a" (port), "0" (buf),
+ "1" (tmp));
+ }
+}
+
+static inline void raw_outsl(volatile u32 __iomem *port, const u32 *buf,
+ unsigned int nr)
+{
+ unsigned int tmp;
+
+ if (nr & 15) {
+ tmp = (nr & 15) - 1;
+ asm volatile (
+ "1: movel %0@+,%2@; dbra %1,1b"
+ : "=a" (buf), "=d" (tmp)
+ : "a" (port), "0" (buf),
+ "1" (tmp));
+ }
+ if (nr >> 4) {
+ tmp = (nr >> 4) - 1;
+ asm volatile (
+ "1: "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "movel %0@+,%2@; "
+ "dbra %1,1b"
+ : "=a" (buf), "=d" (tmp)
+ : "a" (port), "0" (buf),
+ "1" (tmp));
+ }
+}
+
+
+static inline void raw_insw_swapw(volatile u16 __iomem *port, u16 *buf,
+ unsigned int nr)
+{
+ if ((nr) % 8)
+ __asm__ __volatile__
+ ("\tmovel %0,%/a0\n\t"
+ "movel %1,%/a1\n\t"
+ "movel %2,%/d6\n\t"
+ "subql #1,%/d6\n"
+ "1:\tmovew %/a0@,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a1@+\n\t"
+ "dbra %/d6,1b"
+ :
+ : "g" (port), "g" (buf), "g" (nr)
+ : "d0", "a0", "a1", "d6");
+ else
+ __asm__ __volatile__
+ ("movel %0,%/a0\n\t"
+ "movel %1,%/a1\n\t"
+ "movel %2,%/d6\n\t"
+ "lsrl #3,%/d6\n\t"
+ "subql #1,%/d6\n"
+ "1:\tmovew %/a0@,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a1@+\n\t"
+ "movew %/a0@,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a1@+\n\t"
+ "movew %/a0@,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a1@+\n\t"
+ "movew %/a0@,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a1@+\n\t"
+ "movew %/a0@,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a1@+\n\t"
+ "movew %/a0@,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a1@+\n\t"
+ "movew %/a0@,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a1@+\n\t"
+ "movew %/a0@,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a1@+\n\t"
+ "dbra %/d6,1b"
+ :
+ : "g" (port), "g" (buf), "g" (nr)
+ : "d0", "a0", "a1", "d6");
+}
+
+static inline void raw_outsw_swapw(volatile u16 __iomem *port, const u16 *buf,
+ unsigned int nr)
+{
+ if ((nr) % 8)
+ __asm__ __volatile__
+ ("movel %0,%/a0\n\t"
+ "movel %1,%/a1\n\t"
+ "movel %2,%/d6\n\t"
+ "subql #1,%/d6\n"
+ "1:\tmovew %/a1@+,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a0@\n\t"
+ "dbra %/d6,1b"
+ :
+ : "g" (port), "g" (buf), "g" (nr)
+ : "d0", "a0", "a1", "d6");
+ else
+ __asm__ __volatile__
+ ("movel %0,%/a0\n\t"
+ "movel %1,%/a1\n\t"
+ "movel %2,%/d6\n\t"
+ "lsrl #3,%/d6\n\t"
+ "subql #1,%/d6\n"
+ "1:\tmovew %/a1@+,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a0@\n\t"
+ "movew %/a1@+,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a0@\n\t"
+ "movew %/a1@+,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a0@\n\t"
+ "movew %/a1@+,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a0@\n\t"
+ "movew %/a1@+,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a0@\n\t"
+ "movew %/a1@+,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a0@\n\t"
+ "movew %/a1@+,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a0@\n\t"
+ "movew %/a1@+,%/d0\n\t"
+ "rolw #8,%/d0\n\t"
+ "movew %/d0,%/a0@\n\t"
+ "dbra %/d6,1b"
+ :
+ : "g" (port), "g" (buf), "g" (nr)
+ : "d0", "a0", "a1", "d6");
+}
+
+
+#if defined(CONFIG_ATARI_ROM_ISA)
+static inline void raw_rom_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len)
+{
+ unsigned int i;
+
+ for (i = 0; i < len; i++)
+ *buf++ = rom_in_8(port);
+}
+
+static inline void raw_rom_outsb(volatile u8 __iomem *port, const u8 *buf,
+ unsigned int len)
+{
+ unsigned int i;
+
+ for (i = 0; i < len; i++)
+ rom_out_8(port, *buf++);
+}
+
+static inline void raw_rom_insw(volatile u16 __iomem *port, u16 *buf,
+ unsigned int nr)
+{
+ unsigned int i;
+
+ for (i = 0; i < nr; i++)
+ *buf++ = rom_in_be16(port);
+}
+
+static inline void raw_rom_outsw(volatile u16 __iomem *port, const u16 *buf,
+ unsigned int nr)
+{
+ unsigned int i;
+
+ for (i = 0; i < nr; i++)
+ rom_out_be16(port, *buf++);
+}
+
+static inline void raw_rom_insw_swapw(volatile u16 __iomem *port, u16 *buf,
+ unsigned int nr)
+{
+ unsigned int i;
+
+ for (i = 0; i < nr; i++)
+ *buf++ = rom_in_le16(port);
+}
+
+static inline void raw_rom_outsw_swapw(volatile u16 __iomem *port, const u16 *buf,
+ unsigned int nr)
+{
+ unsigned int i;
+
+ for (i = 0; i < nr; i++)
+ rom_out_le16(port, *buf++);
+}
+#endif /* CONFIG_ATARI_ROM_ISA */
+
+#endif /* __KERNEL__ */
+
+#endif /* _RAW_IO_H */
diff --git a/arch/m68k/include/asm/segment.h b/arch/m68k/include/asm/segment.h
new file mode 100644
index 0000000..0b4cc1e
--- /dev/null
+++ b/arch/m68k/include/asm/segment.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_SEGMENT_H
+#define _M68K_SEGMENT_H
+
+/* define constants */
+/* Address spaces (FC0-FC2) */
+#define USER_DATA (1)
+#ifndef __USER_DS
+#define __USER_DS (USER_DATA)
+#endif
+#define USER_PROGRAM (2)
+#define SUPER_DATA (5)
+#ifndef __KERNEL_DS
+#define __KERNEL_DS (SUPER_DATA)
+#endif
+#define SUPER_PROGRAM (6)
+#define CPU_SPACE (7)
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+ unsigned long seg;
+} mm_segment_t;
+
+#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
+
+#ifdef CONFIG_CPU_HAS_ADDRESS_SPACES
+/*
+ * Get/set the SFC/DFC registers for MOVES instructions
+ */
+#define USER_DS MAKE_MM_SEG(__USER_DS)
+#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS)
+
+static inline mm_segment_t get_fs(void)
+{
+ mm_segment_t _v;
+ __asm__ ("movec %/dfc,%0":"=r" (_v.seg):);
+ return _v;
+}
+
+static inline void set_fs(mm_segment_t val)
+{
+ __asm__ __volatile__ ("movec %0,%/sfc\n\t"
+ "movec %0,%/dfc\n\t"
+ : /* no outputs */ : "r" (val.seg) : "memory");
+}
+
+static inline mm_segment_t get_ds(void)
+{
+ /* return the supervisor data space code */
+ return KERNEL_DS;
+}
+
+#else
+#define USER_DS MAKE_MM_SEG(TASK_SIZE)
+#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
+#define get_ds() (KERNEL_DS)
+#define get_fs() (current_thread_info()->addr_limit)
+#define set_fs(x) (current_thread_info()->addr_limit = (x))
+#endif
+
+#define segment_eq(a, b) ((a).seg == (b).seg)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _M68K_SEGMENT_H */
diff --git a/arch/m68k/include/asm/serial.h b/arch/m68k/include/asm/serial.h
new file mode 100644
index 0000000..3f76bc7
--- /dev/null
+++ b/arch/m68k/include/asm/serial.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/asm-m68k/serial.h
+ *
+ * currently this seems useful only for a Q40,
+ * it's an almost exact copy of ../asm-alpha/serial.h
+ *
+ */
+
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD ( 1843200 / 16 )
+
+/* Standard COM flags (except for COM4, because of the 8514 problem) */
+#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
+#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ)
+#define STD_COM4_FLAGS (UPF_BOOT_AUTOCONF | UPF_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
+#define STD_COM4_FLAGS UPF_BOOT_AUTOCONF
+#endif
+
+#ifdef CONFIG_ISA
+#define SERIAL_PORT_DFNS \
+ /* UART CLK PORT IRQ FLAGS */ \
+ { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
+ { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
+ { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
+ { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
+#endif
diff --git a/arch/m68k/include/asm/setup.h b/arch/m68k/include/asm/setup.h
new file mode 100644
index 0000000..8f2023f
--- /dev/null
+++ b/arch/m68k/include/asm/setup.h
@@ -0,0 +1,311 @@
+/*
+** asm/setup.h -- Definition of the Linux/m68k setup information
+**
+** Copyright 1992 by Greg Harp
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License. See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Created 09/29/92 by Greg Harp
+**
+** 5/2/94 Roman Hodek:
+** Added bi_atari part of the machine dependent union bi_un; for now it
+** contains just a model field to distinguish between TT and Falcon.
+** 26/7/96 Roman Zippel:
+** Renamed to setup.h; added some useful macros to allow gcc some
+** optimizations if possible.
+** 5/10/96 Geert Uytterhoeven:
+** Redesign of the boot information structure; moved boot information
+** structure to bootinfo.h
+*/
+#ifndef _M68K_SETUP_H
+#define _M68K_SETUP_H
+
+#include <uapi/asm/bootinfo.h>
+#include <uapi/asm/setup.h>
+
+
+#define CL_SIZE COMMAND_LINE_SIZE
+
+#ifndef __ASSEMBLY__
+extern unsigned long m68k_machtype;
+#endif /* !__ASSEMBLY__ */
+
+#if !defined(CONFIG_AMIGA)
+# define MACH_IS_AMIGA (0)
+#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \
+ || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \
+ || defined(CONFIG_HP300) || defined(CONFIG_Q40) \
+ || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
+# define MACH_IS_AMIGA (m68k_machtype == MACH_AMIGA)
+#else
+# define MACH_AMIGA_ONLY
+# define MACH_IS_AMIGA (1)
+# define MACH_TYPE (MACH_AMIGA)
+#endif
+
+#if !defined(CONFIG_ATARI)
+# define MACH_IS_ATARI (0)
+#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \
+ || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \
+ || defined(CONFIG_HP300) || defined(CONFIG_Q40) \
+ || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
+# define MACH_IS_ATARI (m68k_machtype == MACH_ATARI)
+#else
+# define MACH_ATARI_ONLY
+# define MACH_IS_ATARI (1)
+# define MACH_TYPE (MACH_ATARI)
+#endif
+
+#if !defined(CONFIG_MAC)
+# define MACH_IS_MAC (0)
+#elif defined(CONFIG_AMIGA) || defined(CONFIG_ATARI) || defined(CONFIG_APOLLO) \
+ || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \
+ || defined(CONFIG_HP300) || defined(CONFIG_Q40) \
+ || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
+# define MACH_IS_MAC (m68k_machtype == MACH_MAC)
+#else
+# define MACH_MAC_ONLY
+# define MACH_IS_MAC (1)
+# define MACH_TYPE (MACH_MAC)
+#endif
+
+#if defined(CONFIG_SUN3)
+#define MACH_IS_SUN3 (1)
+#define MACH_SUN3_ONLY (1)
+#define MACH_TYPE (MACH_SUN3)
+#else
+#define MACH_IS_SUN3 (0)
+#endif
+
+#if !defined (CONFIG_APOLLO)
+# define MACH_IS_APOLLO (0)
+#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
+ || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \
+ || defined(CONFIG_HP300) || defined(CONFIG_Q40) \
+ || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
+# define MACH_IS_APOLLO (m68k_machtype == MACH_APOLLO)
+#else
+# define MACH_APOLLO_ONLY
+# define MACH_IS_APOLLO (1)
+# define MACH_TYPE (MACH_APOLLO)
+#endif
+
+#if !defined (CONFIG_MVME147)
+# define MACH_IS_MVME147 (0)
+#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
+ || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \
+ || defined(CONFIG_HP300) || defined(CONFIG_Q40) \
+ || defined(CONFIG_SUN3X) || defined(CONFIG_MVME16x)
+# define MACH_IS_MVME147 (m68k_machtype == MACH_MVME147)
+#else
+# define MACH_MVME147_ONLY
+# define MACH_IS_MVME147 (1)
+# define MACH_TYPE (MACH_MVME147)
+#endif
+
+#if !defined (CONFIG_MVME16x)
+# define MACH_IS_MVME16x (0)
+#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
+ || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \
+ || defined(CONFIG_HP300) || defined(CONFIG_Q40) \
+ || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
+# define MACH_IS_MVME16x (m68k_machtype == MACH_MVME16x)
+#else
+# define MACH_MVME16x_ONLY
+# define MACH_IS_MVME16x (1)
+# define MACH_TYPE (MACH_MVME16x)
+#endif
+
+#if !defined (CONFIG_BVME6000)
+# define MACH_IS_BVME6000 (0)
+#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
+ || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \
+ || defined(CONFIG_HP300) || defined(CONFIG_Q40) \
+ || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
+# define MACH_IS_BVME6000 (m68k_machtype == MACH_BVME6000)
+#else
+# define MACH_BVME6000_ONLY
+# define MACH_IS_BVME6000 (1)
+# define MACH_TYPE (MACH_BVME6000)
+#endif
+
+#if !defined (CONFIG_HP300)
+# define MACH_IS_HP300 (0)
+#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
+ || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \
+ || defined(CONFIG_BVME6000) || defined(CONFIG_Q40) \
+ || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
+# define MACH_IS_HP300 (m68k_machtype == MACH_HP300)
+#else
+# define MACH_HP300_ONLY
+# define MACH_IS_HP300 (1)
+# define MACH_TYPE (MACH_HP300)
+#endif
+
+#if !defined (CONFIG_Q40)
+# define MACH_IS_Q40 (0)
+#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
+ || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \
+ || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \
+ || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147)
+# define MACH_IS_Q40 (m68k_machtype == MACH_Q40)
+#else
+# define MACH_Q40_ONLY
+# define MACH_IS_Q40 (1)
+# define MACH_TYPE (MACH_Q40)
+#endif
+
+#if !defined (CONFIG_SUN3X)
+# define MACH_IS_SUN3X (0)
+#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \
+ || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \
+ || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \
+ || defined(CONFIG_Q40) || defined(CONFIG_MVME147)
+# define MACH_IS_SUN3X (m68k_machtype == MACH_SUN3X)
+#else
+# define CONFIG_SUN3X_ONLY
+# define MACH_IS_SUN3X (1)
+# define MACH_TYPE (MACH_SUN3X)
+#endif
+
+#ifndef MACH_TYPE
+# define MACH_TYPE (m68k_machtype)
+#endif
+
+
+#ifndef __ASSEMBLY__
+extern unsigned long m68k_cputype;
+extern unsigned long m68k_fputype;
+extern unsigned long m68k_mmutype;
+#ifdef CONFIG_VME
+extern unsigned long vme_brdtype;
+#endif
+
+ /*
+ * m68k_is040or060 is != 0 for a '040 or higher;
+ * used numbers are 4 for 68040 and 6 for 68060.
+ */
+
+extern int m68k_is040or060;
+#endif /* !__ASSEMBLY__ */
+
+#if !defined(CONFIG_M68020)
+# define CPU_IS_020 (0)
+# define MMU_IS_851 (0)
+# define MMU_IS_SUN3 (0)
+#elif defined(CONFIG_M68030) || defined(CONFIG_M68040) || defined(CONFIG_M68060)
+# define CPU_IS_020 (m68k_cputype & CPU_68020)
+# define MMU_IS_851 (m68k_mmutype & MMU_68851)
+# define MMU_IS_SUN3 (0) /* Sun3 not supported with other CPU enabled */
+#else
+# define CPU_M68020_ONLY
+# define CPU_IS_020 (1)
+#ifdef MACH_SUN3_ONLY
+# define MMU_IS_SUN3 (1)
+# define MMU_IS_851 (0)
+#else
+# define MMU_IS_SUN3 (0)
+# define MMU_IS_851 (1)
+#endif
+#endif
+
+#if !defined(CONFIG_M68030)
+# define CPU_IS_030 (0)
+# define MMU_IS_030 (0)
+#elif defined(CONFIG_M68020) || defined(CONFIG_M68040) || defined(CONFIG_M68060)
+# define CPU_IS_030 (m68k_cputype & CPU_68030)
+# define MMU_IS_030 (m68k_mmutype & MMU_68030)
+#else
+# define CPU_M68030_ONLY
+# define CPU_IS_030 (1)
+# define MMU_IS_030 (1)
+#endif
+
+#if !defined(CONFIG_M68040)
+# define CPU_IS_040 (0)
+# define MMU_IS_040 (0)
+#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68060)
+# define CPU_IS_040 (m68k_cputype & CPU_68040)
+# define MMU_IS_040 (m68k_mmutype & MMU_68040)
+#else
+# define CPU_M68040_ONLY
+# define CPU_IS_040 (1)
+# define MMU_IS_040 (1)
+#endif
+
+#if !defined(CONFIG_M68060)
+# define CPU_IS_060 (0)
+# define MMU_IS_060 (0)
+#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68040)
+# define CPU_IS_060 (m68k_cputype & CPU_68060)
+# define MMU_IS_060 (m68k_mmutype & MMU_68060)
+#else
+# define CPU_M68060_ONLY
+# define CPU_IS_060 (1)
+# define MMU_IS_060 (1)
+#endif
+
+#if !defined(CONFIG_M68020) && !defined(CONFIG_M68030)
+# define CPU_IS_020_OR_030 (0)
+#else
+# define CPU_M68020_OR_M68030
+# if defined(CONFIG_M68040) || defined(CONFIG_M68060)
+# define CPU_IS_020_OR_030 (!m68k_is040or060)
+# else
+# define CPU_M68020_OR_M68030_ONLY
+# define CPU_IS_020_OR_030 (1)
+# endif
+#endif
+
+#if !defined(CONFIG_M68040) && !defined(CONFIG_M68060)
+# define CPU_IS_040_OR_060 (0)
+#else
+# define CPU_M68040_OR_M68060
+# if defined(CONFIG_M68020) || defined(CONFIG_M68030)
+# define CPU_IS_040_OR_060 (m68k_is040or060)
+# else
+# define CPU_M68040_OR_M68060_ONLY
+# define CPU_IS_040_OR_060 (1)
+# endif
+#endif
+
+#if !defined(CONFIG_COLDFIRE)
+# define CPU_IS_COLDFIRE (0)
+#else
+# define CPU_IS_COLDFIRE (1)
+# define MMU_IS_COLDFIRE (1)
+#endif
+
+#define CPU_TYPE (m68k_cputype)
+
+#ifdef CONFIG_M68KFPU_EMU
+# ifdef CONFIG_M68KFPU_EMU_ONLY
+# define FPU_IS_EMU (1)
+# else
+# define FPU_IS_EMU (!m68k_fputype)
+# endif
+#else
+# define FPU_IS_EMU (0)
+#endif
+
+
+ /*
+ * Miscellaneous
+ */
+
+#define NUM_MEMINFO 4
+
+#ifndef __ASSEMBLY__
+struct m68k_mem_info {
+ unsigned long addr; /* physical address of memory chunk */
+ unsigned long size; /* length of memory chunk (in bytes) */
+};
+
+extern int m68k_num_memory; /* # of memory blocks found (and used) */
+extern int m68k_realnum_memory; /* real # of memory blocks found */
+extern struct m68k_mem_info m68k_memory[NUM_MEMINFO];/* memory description */
+#endif
+
+#endif /* _M68K_SETUP_H */
diff --git a/arch/m68k/include/asm/signal.h b/arch/m68k/include/asm/signal.h
new file mode 100644
index 0000000..8af85c3
--- /dev/null
+++ b/arch/m68k/include/asm/signal.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_SIGNAL_H
+#define _M68K_SIGNAL_H
+
+#include <uapi/asm/signal.h>
+
+/* Most things should be clean enough to redefine this at will, if care
+ is taken to make libc match. */
+
+#define _NSIG 64
+#define _NSIG_BPW 32
+#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t; /* at least 32 bits */
+
+typedef struct {
+ unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#define __ARCH_HAS_SA_RESTORER
+
+#include <asm/sigcontext.h>
+
+#ifndef CONFIG_CPU_HAS_NO_BITFIELDS
+#define __HAVE_ARCH_SIG_BITOPS
+
+static inline void sigaddset(sigset_t *set, int _sig)
+{
+ asm ("bfset %0{%1,#1}"
+ : "+o" (*set)
+ : "id" ((_sig - 1) ^ 31)
+ : "cc");
+}
+
+static inline void sigdelset(sigset_t *set, int _sig)
+{
+ asm ("bfclr %0{%1,#1}"
+ : "+o" (*set)
+ : "id" ((_sig - 1) ^ 31)
+ : "cc");
+}
+
+static inline int __const_sigismember(sigset_t *set, int _sig)
+{
+ unsigned long sig = _sig - 1;
+ return 1 & (set->sig[sig / _NSIG_BPW] >> (sig % _NSIG_BPW));
+}
+
+static inline int __gen_sigismember(sigset_t *set, int _sig)
+{
+ int ret;
+ asm ("bfextu %1{%2,#1},%0"
+ : "=d" (ret)
+ : "o" (*set), "id" ((_sig-1) ^ 31)
+ : "cc");
+ return ret;
+}
+
+#define sigismember(set,sig) \
+ (__builtin_constant_p(sig) ? \
+ __const_sigismember(set,sig) : \
+ __gen_sigismember(set,sig))
+
+#endif /* !CONFIG_CPU_HAS_NO_BITFIELDS */
+
+#endif /* _M68K_SIGNAL_H */
diff --git a/arch/m68k/include/asm/smp.h b/arch/m68k/include/asm/smp.h
new file mode 100644
index 0000000..9e9bd7e
--- /dev/null
+++ b/arch/m68k/include/asm/smp.h
@@ -0,0 +1 @@
+/* nothing required here yet */
diff --git a/arch/m68k/include/asm/string.h b/arch/m68k/include/asm/string.h
new file mode 100644
index 0000000..f759d94
--- /dev/null
+++ b/arch/m68k/include/asm/string.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_STRING_H_
+#define _M68K_STRING_H_
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+#define __HAVE_ARCH_STRNLEN
+static inline size_t strnlen(const char *s, size_t count)
+{
+ const char *sc = s;
+
+ asm volatile ("\n"
+ "1: subq.l #1,%1\n"
+ " jcs 2f\n"
+ " tst.b (%0)+\n"
+ " jne 1b\n"
+ " subq.l #1,%0\n"
+ "2:"
+ : "+a" (sc), "+d" (count));
+ return sc - s;
+}
+
+#define __HAVE_ARCH_STRNCPY
+static inline char *strncpy(char *dest, const char *src, size_t n)
+{
+ char *xdest = dest;
+
+ asm volatile ("\n"
+ " jra 2f\n"
+ "1: move.b (%1),(%0)+\n"
+ " jeq 2f\n"
+ " addq.l #1,%1\n"
+ "2: subq.l #1,%2\n"
+ " jcc 1b\n"
+ : "+a" (dest), "+a" (src), "+d" (n)
+ : : "memory");
+ return xdest;
+}
+
+#ifndef CONFIG_COLDFIRE
+#define __HAVE_ARCH_STRCMP
+static inline int strcmp(const char *cs, const char *ct)
+{
+ char res;
+
+ asm ("\n"
+ "1: move.b (%0)+,%2\n" /* get *cs */
+ " cmp.b (%1)+,%2\n" /* compare a byte */
+ " jne 2f\n" /* not equal, break out */
+ " tst.b %2\n" /* at end of cs? */
+ " jne 1b\n" /* no, keep going */
+ " jra 3f\n" /* strings are equal */
+ "2: sub.b -(%1),%2\n" /* *cs - *ct */
+ "3:"
+ : "+a" (cs), "+a" (ct), "=d" (res));
+ return res;
+}
+#endif /* CONFIG_COLDFIRE */
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#define memcmp(d, s, n) __builtin_memcmp(d, s, n)
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+#define memset(d, c, n) __builtin_memset(d, c, n)
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+#define memcpy(d, s, n) __builtin_memcpy(d, s, n)
+
+#endif /* _M68K_STRING_H_ */
diff --git a/arch/m68k/include/asm/sun3-head.h b/arch/m68k/include/asm/sun3-head.h
new file mode 100644
index 0000000..5656a26
--- /dev/null
+++ b/arch/m68k/include/asm/sun3-head.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SUN3_HEAD_H
+#define __SUN3_HEAD_H
+
+#define KERNBASE 0xE000000 /* First address the kernel will eventually be */
+#define LOAD_ADDR 0x4000 /* prom jumps to us here unless this is elf /boot */
+#define FC_CONTROL 3
+#define FC_SUPERD 5
+#define FC_CPU 7
+
+#endif /* __SUN3_HEAD_H */
diff --git a/arch/m68k/include/asm/sun3_pgalloc.h b/arch/m68k/include/asm/sun3_pgalloc.h
new file mode 100644
index 0000000..11485d3
--- /dev/null
+++ b/arch/m68k/include/asm/sun3_pgalloc.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* sun3_pgalloc.h --
+ * reorganization around 2.3.39, routines moved from sun3_pgtable.h
+ *
+ *
+ * 02/27/2002 -- Modified to support "highpte" implementation in 2.5.5 (Sam)
+ *
+ * moved 1/26/2000 Sam Creasey
+ */
+
+#ifndef _SUN3_PGALLOC_H
+#define _SUN3_PGALLOC_H
+
+#include <asm/tlb.h>
+
+extern const char bad_pmd_string[];
+
+#define pmd_alloc_one(mm,address) ({ BUG(); ((pmd_t *)2); })
+
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+ free_page((unsigned long) pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t page)
+{
+ pgtable_page_dtor(page);
+ __free_page(page);
+}
+
+#define __pte_free_tlb(tlb,pte,addr) \
+do { \
+ pgtable_page_dtor(pte); \
+ tlb_remove_page((tlb), pte); \
+} while (0)
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+ unsigned long address)
+{
+ unsigned long page = __get_free_page(GFP_KERNEL);
+
+ if (!page)
+ return NULL;
+
+ memset((void *)page, 0, PAGE_SIZE);
+ return (pte_t *) (page);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
+{
+ struct page *page = alloc_pages(GFP_KERNEL, 0);
+
+ if (page == NULL)
+ return NULL;
+
+ clear_highpage(page);
+ if (!pgtable_page_ctor(page)) {
+ __free_page(page);
+ return NULL;
+ }
+ return page;
+
+}
+
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte)
+{
+ pmd_val(*pmd) = __pa((unsigned long)pte);
+}
+
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page)
+{
+ pmd_val(*pmd) = __pa((unsigned long)page_address(page));
+}
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+/*
+ * allocating and freeing a pmd is trivial: the 1-entry pmd is
+ * inside the pgd, so has no extra memory associated with it.
+ */
+#define pmd_free(mm, x) do { } while (0)
+#define __pmd_free_tlb(tlb, x, addr) do { } while (0)
+
+static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+ free_page((unsigned long) pgd);
+}
+
+static inline pgd_t * pgd_alloc(struct mm_struct *mm)
+{
+ pgd_t *new_pgd;
+
+ new_pgd = (pgd_t *)get_zeroed_page(GFP_KERNEL);
+ memcpy(new_pgd, swapper_pg_dir, PAGE_SIZE);
+ memset(new_pgd, 0, (PAGE_OFFSET >> PGDIR_SHIFT));
+ return new_pgd;
+}
+
+#define pgd_populate(mm, pmd, pte) BUG()
+
+#endif /* SUN3_PGALLOC_H */
diff --git a/arch/m68k/include/asm/sun3_pgtable.h b/arch/m68k/include/asm/sun3_pgtable.h
new file mode 100644
index 0000000..c987d50
--- /dev/null
+++ b/arch/m68k/include/asm/sun3_pgtable.h
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _SUN3_PGTABLE_H
+#define _SUN3_PGTABLE_H
+
+#include <asm/sun3mmu.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/virtconvert.h>
+#include <linux/linkage.h>
+
+/*
+ * This file contains all the things which change drastically for the sun3
+ * pagetable stuff, to avoid making too much of a mess of the generic m68k
+ * `pgtable.h'; this should only be included from the generic file. --m
+ */
+
+/* For virtual address to physical address conversion */
+#define VTOP(addr) __pa(addr)
+#define PTOV(addr) __va(addr)
+
+
+#endif /* !__ASSEMBLY__ */
+
+/* These need to be defined for compatibility although the sun3 doesn't use them */
+#define _PAGE_NOCACHE030 0x040
+#define _CACHEMASK040 (~0x060)
+#define _PAGE_NOCACHE_S 0x040
+
+/* Page protection values within PTE. */
+#define SUN3_PAGE_VALID (0x80000000)
+#define SUN3_PAGE_WRITEABLE (0x40000000)
+#define SUN3_PAGE_SYSTEM (0x20000000)
+#define SUN3_PAGE_NOCACHE (0x10000000)
+#define SUN3_PAGE_ACCESSED (0x02000000)
+#define SUN3_PAGE_MODIFIED (0x01000000)
+
+
+/* Externally used page protection values. */
+#define _PAGE_PRESENT (SUN3_PAGE_VALID)
+#define _PAGE_ACCESSED (SUN3_PAGE_ACCESSED)
+
+/* Compound page protection values. */
+//todo: work out which ones *should* have SUN3_PAGE_NOCACHE and fix...
+// is it just PAGE_KERNEL and PAGE_SHARED?
+#define PAGE_NONE __pgprot(SUN3_PAGE_VALID \
+ | SUN3_PAGE_ACCESSED \
+ | SUN3_PAGE_NOCACHE)
+#define PAGE_SHARED __pgprot(SUN3_PAGE_VALID \
+ | SUN3_PAGE_WRITEABLE \
+ | SUN3_PAGE_ACCESSED \
+ | SUN3_PAGE_NOCACHE)
+#define PAGE_COPY __pgprot(SUN3_PAGE_VALID \
+ | SUN3_PAGE_ACCESSED \
+ | SUN3_PAGE_NOCACHE)
+#define PAGE_READONLY __pgprot(SUN3_PAGE_VALID \
+ | SUN3_PAGE_ACCESSED \
+ | SUN3_PAGE_NOCACHE)
+#define PAGE_KERNEL __pgprot(SUN3_PAGE_VALID \
+ | SUN3_PAGE_WRITEABLE \
+ | SUN3_PAGE_SYSTEM \
+ | SUN3_PAGE_NOCACHE \
+ | SUN3_PAGE_ACCESSED \
+ | SUN3_PAGE_MODIFIED)
+#define PAGE_INIT __pgprot(SUN3_PAGE_VALID \
+ | SUN3_PAGE_WRITEABLE \
+ | SUN3_PAGE_SYSTEM \
+ | SUN3_PAGE_NOCACHE)
+
+/*
+ * Page protections for initialising protection_map. The sun3 has only two
+ * protection settings, valid (implying read and execute) and writeable. These
+ * are as close as we can get...
+ */
+#define __P000 PAGE_NONE
+#define __P001 PAGE_READONLY
+#define __P010 PAGE_COPY
+#define __P011 PAGE_COPY
+#define __P100 PAGE_READONLY
+#define __P101 PAGE_READONLY
+#define __P110 PAGE_COPY
+#define __P111 PAGE_COPY
+
+#define __S000 PAGE_NONE
+#define __S001 PAGE_READONLY
+#define __S010 PAGE_SHARED
+#define __S011 PAGE_SHARED
+#define __S100 PAGE_READONLY
+#define __S101 PAGE_READONLY
+#define __S110 PAGE_SHARED
+#define __S111 PAGE_SHARED
+
+/* Use these fake page-protections on PMDs. */
+#define SUN3_PMD_VALID (0x00000001)
+#define SUN3_PMD_MASK (0x0000003F)
+#define SUN3_PMD_MAGIC (0x0000002B)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+ pte_val(pte) = (pte_val(pte) & SUN3_PAGE_CHG_MASK) | pgprot_val(newprot);
+ return pte;
+}
+
+#define pmd_set(pmdp,ptep) do {} while (0)
+
+static inline void pgd_set(pgd_t *pgdp, pmd_t *pmdp)
+{
+ pgd_val(*pgdp) = virt_to_phys(pmdp);
+}
+
+#define __pte_page(pte) \
+((unsigned long) __va ((pte_val (pte) & SUN3_PAGE_PGNUM_MASK) << PAGE_SHIFT))
+#define __pmd_page(pmd) \
+((unsigned long) __va (pmd_val (pmd) & PAGE_MASK))
+
+static inline int pte_none (pte_t pte) { return !pte_val (pte); }
+static inline int pte_present (pte_t pte) { return pte_val (pte) & SUN3_PAGE_VALID; }
+static inline void pte_clear (struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+ pte_val (*ptep) = 0;
+}
+
+#define pte_pfn(pte) (pte_val(pte) & SUN3_PAGE_PGNUM_MASK)
+#define pfn_pte(pfn, pgprot) \
+({ pte_t __pte; pte_val(__pte) = pfn | pgprot_val(pgprot); __pte; })
+
+#define pte_page(pte) virt_to_page(__pte_page(pte))
+#define pmd_page(pmd) virt_to_page(__pmd_page(pmd))
+
+
+static inline int pmd_none2 (pmd_t *pmd) { return !pmd_val (*pmd); }
+#define pmd_none(pmd) pmd_none2(&(pmd))
+//static inline int pmd_bad (pmd_t pmd) { return (pmd_val (pmd) & SUN3_PMD_MASK) != SUN3_PMD_MAGIC; }
+static inline int pmd_bad2 (pmd_t *pmd) { return 0; }
+#define pmd_bad(pmd) pmd_bad2(&(pmd))
+static inline int pmd_present2 (pmd_t *pmd) { return pmd_val (*pmd) & SUN3_PMD_VALID; }
+/* #define pmd_present(pmd) pmd_present2(&(pmd)) */
+#define pmd_present(pmd) (!pmd_none2(&(pmd)))
+static inline void pmd_clear (pmd_t *pmdp) { pmd_val (*pmdp) = 0; }
+
+static inline int pgd_none (pgd_t pgd) { return 0; }
+static inline int pgd_bad (pgd_t pgd) { return 0; }
+static inline int pgd_present (pgd_t pgd) { return 1; }
+static inline void pgd_clear (pgd_t *pgdp) {}
+
+
+#define pte_ERROR(e) \
+ pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+ pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+ pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not...
+ * [we have the full set here even if they don't change from m68k]
+ */
+static inline int pte_write(pte_t pte) { return pte_val(pte) & SUN3_PAGE_WRITEABLE; }
+static inline int pte_dirty(pte_t pte) { return pte_val(pte) & SUN3_PAGE_MODIFIED; }
+static inline int pte_young(pte_t pte) { return pte_val(pte) & SUN3_PAGE_ACCESSED; }
+static inline int pte_special(pte_t pte) { return 0; }
+
+static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~SUN3_PAGE_WRITEABLE; return pte; }
+static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~SUN3_PAGE_MODIFIED; return pte; }
+static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~SUN3_PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= SUN3_PAGE_WRITEABLE; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= SUN3_PAGE_MODIFIED; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= SUN3_PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mknocache(pte_t pte) { pte_val(pte) |= SUN3_PAGE_NOCACHE; return pte; }
+// use this version when caches work...
+//static inline pte_t pte_mkcache(pte_t pte) { pte_val(pte) &= SUN3_PAGE_NOCACHE; return pte; }
+// until then, use:
+static inline pte_t pte_mkcache(pte_t pte) { return pte; }
+static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern pgd_t kernel_pg_dir[PTRS_PER_PGD];
+
+/* Find an entry in a pagetable directory. */
+#define pgd_index(address) ((address) >> PGDIR_SHIFT)
+
+#define pgd_offset(mm, address) \
+((mm)->pgd + pgd_index(address))
+
+/* Find an entry in a kernel pagetable directory. */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/* Find an entry in the second-level pagetable. */
+static inline pmd_t *pmd_offset (pgd_t *pgd, unsigned long address)
+{
+ return (pmd_t *) pgd;
+}
+
+/* Find an entry in the third-level pagetable. */
+#define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
+#define pte_offset_kernel(pmd, address) ((pte_t *) __pmd_page(*pmd) + pte_index(address))
+#define pte_offset_map(pmd, address) ((pte_t *)page_address(pmd_page(*pmd)) + pte_index(address))
+#define pte_unmap(pte) do { } while (0)
+
+/* Macros to (de)construct the fake PTEs representing swap pages. */
+#define __swp_type(x) ((x).val & 0x7F)
+#define __swp_offset(x) (((x).val) >> 7)
+#define __swp_entry(type,offset) ((swp_entry_t) { ((type) | ((offset) << 7)) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
+
+#endif /* !__ASSEMBLY__ */
+#endif /* !_SUN3_PGTABLE_H */
diff --git a/arch/m68k/include/asm/sun3ints.h b/arch/m68k/include/asm/sun3ints.h
new file mode 100644
index 0000000..309d6e6
--- /dev/null
+++ b/arch/m68k/include/asm/sun3ints.h
@@ -0,0 +1,37 @@
+/*
+ * sun3ints.h -- Linux/Sun3 interrupt handling code definitions
+ *
+ * Erik Verbruggen (erik@bigmama.xtdnet.nl)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef SUN3INTS_H
+#define SUN3INTS_H
+
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <asm/intersil.h>
+#include <asm/oplib.h>
+#include <asm/traps.h>
+#include <asm/irq.h>
+
+#define SUN3_INT_VECS 192
+
+void sun3_enable_irq(unsigned int irq);
+void sun3_disable_irq(unsigned int irq);
+extern void sun3_init_IRQ (void);
+extern void sun3_enable_interrupts (void);
+extern void sun3_disable_interrupts (void);
+extern volatile unsigned char* sun3_intreg;
+
+/* master list of VME vectors -- don't fuck with this */
+#define SUN3_VEC_FLOPPY (IRQ_USER+0)
+#define SUN3_VEC_VMESCSI0 (IRQ_USER+0)
+#define SUN3_VEC_VMESCSI1 (IRQ_USER+1)
+#define SUN3_VEC_CG (IRQ_USER+104)
+
+
+#endif /* SUN3INTS_H */
diff --git a/arch/m68k/include/asm/sun3mmu.h b/arch/m68k/include/asm/sun3mmu.h
new file mode 100644
index 0000000..21a75da
--- /dev/null
+++ b/arch/m68k/include/asm/sun3mmu.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Definitions for Sun3 custom MMU.
+ */
+#ifndef __SUN3_MMU_H__
+#define __SUN3_MMU_H__
+
+#include <linux/types.h>
+#include <asm/movs.h>
+#include <asm/sun3-head.h>
+
+/* MMU characteristics. */
+#define SUN3_SEGMAPS_PER_CONTEXT 2048
+#define SUN3_PMEGS_NUM 256
+#define SUN3_CONTEXTS_NUM 8
+
+#define SUN3_PMEG_SIZE_BITS 17
+#define SUN3_PMEG_SIZE (1 << SUN3_PMEG_SIZE_BITS)
+#define SUN3_PMEG_MASK (SUN3_PMEG_SIZE - 1)
+
+#define SUN3_PTE_SIZE_BITS 13
+#define SUN3_PTE_SIZE (1 << SUN3_PTE_SIZE_BITS)
+#define SUN3_PTE_MASK (SUN3_PTE_SIZE - 1)
+
+#define SUN3_CONTROL_MASK (0x0FFFFFFC)
+#define SUN3_INVALID_PMEG 255
+#define SUN3_INVALID_CONTEXT 255
+
+#define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
+#define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
+#define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
+#define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
+#define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
+#define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
+#define AC_BUS_ERROR 0x60000000 /* 34 Cleared on read, byte. */
+#define AC_SYNC_ERR 0x60000000 /* c fault type */
+#define AC_SYNC_VA 0x60000004 /* c fault virtual address */
+#define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
+#define AC_ASYNC_VA 0x6000000c /* c async fault virtual address */
+#define AC_LEDS 0x70000000 /* 34 Zero turns on LEDs, byte */
+#define AC_CACHETAGS 0x80000000 /* 34c direct access to the VAC tags */
+#define AC_CACHEDDATA 0x90000000 /* 3 c direct access to the VAC data */
+#define AC_UDVMA_MAP 0xD0000000 /* 4 Not used on Sun boards, byte */
+#define AC_VME_VECTOR 0xE0000000 /* 4 For non-Autovector VME, byte */
+#define AC_BOOT_SCC 0xF0000000 /* 34 bypass to access Zilog 8530. byte.*/
+
+#define SUN3_PAGE_CHG_MASK (SUN3_PAGE_PGNUM_MASK \
+ | SUN3_PAGE_ACCESSED | SUN3_PAGE_MODIFIED)
+
+/* Bus access type within PTE. */
+#define SUN3_PAGE_TYPE_MASK (0x0c000000)
+#define SUN3_PAGE_TYPE_MEMORY (0x00000000)
+#define SUN3_PAGE_TYPE_IO (0x04000000)
+#define SUN3_PAGE_TYPE_VME16 (0x08000000)
+#define SUN3_PAGE_TYPE_VME32 (0x0c000000)
+
+/* Mask for page number within PTE. */
+#define SUN3_PAGE_PGNUM_MASK (0x0007FFFF)
+
+/* Bits within bus-error register. */
+#define SUN3_BUSERR_WATCHDOG (0x01)
+#define SUN3_BUSERR_unused (0x02)
+#define SUN3_BUSERR_FPAENERR (0x04)
+#define SUN3_BUSERR_FPABERR (0x08)
+#define SUN3_BUSERR_VMEBERR (0x10)
+#define SUN3_BUSERR_TIMEOUT (0x20)
+#define SUN3_BUSERR_PROTERR (0x40)
+#define SUN3_BUSERR_INVALID (0x80)
+
+#ifndef __ASSEMBLY__
+
+/* Read bus error status register (implicitly clearing it). */
+static inline unsigned char sun3_get_buserr(void)
+{
+ unsigned char sfc, c;
+
+ GET_SFC (sfc);
+ SET_SFC (FC_CONTROL);
+ GET_CONTROL_BYTE (AC_BUS_ERROR, c);
+ SET_SFC (sfc);
+
+ return c;
+}
+
+/* Read segmap from hardware MMU. */
+static inline unsigned long sun3_get_segmap(unsigned long addr)
+{
+ register unsigned long entry;
+ unsigned char c, sfc;
+
+ GET_SFC (sfc);
+ SET_SFC (FC_CONTROL);
+ GET_CONTROL_BYTE (AC_SEGMAP | (addr & SUN3_CONTROL_MASK), c);
+ SET_SFC (sfc);
+ entry = c;
+
+ return entry;
+}
+
+/* Write segmap to hardware MMU. */
+static inline void sun3_put_segmap(unsigned long addr, unsigned long entry)
+{
+ unsigned char sfc;
+
+ GET_DFC (sfc);
+ SET_DFC (FC_CONTROL);
+ SET_CONTROL_BYTE (AC_SEGMAP | (addr & SUN3_CONTROL_MASK), entry);
+ SET_DFC (sfc);
+
+ return;
+}
+
+/* Read PTE from hardware MMU. */
+static inline unsigned long sun3_get_pte(unsigned long addr)
+{
+ register unsigned long entry;
+ unsigned char sfc;
+
+ GET_SFC (sfc);
+ SET_SFC (FC_CONTROL);
+ GET_CONTROL_WORD (AC_PAGEMAP | (addr & SUN3_CONTROL_MASK), entry);
+ SET_SFC (sfc);
+
+ return entry;
+}
+
+/* Write PTE to hardware MMU. */
+static inline void sun3_put_pte(unsigned long addr, unsigned long entry)
+{
+ unsigned char sfc;
+
+ GET_DFC (sfc);
+ SET_DFC (FC_CONTROL);
+ SET_CONTROL_WORD (AC_PAGEMAP | (addr & SUN3_CONTROL_MASK), entry);
+ SET_DFC (sfc);
+
+ return;
+}
+
+/* get current context */
+static inline unsigned char sun3_get_context(void)
+{
+ unsigned char sfc, c;
+
+ GET_SFC(sfc);
+ SET_SFC(FC_CONTROL);
+ GET_CONTROL_BYTE(AC_CONTEXT, c);
+ SET_SFC(sfc);
+
+ return c;
+}
+
+/* set alternate context */
+static inline void sun3_put_context(unsigned char c)
+{
+ unsigned char dfc;
+ GET_DFC(dfc);
+ SET_DFC(FC_CONTROL);
+ SET_CONTROL_BYTE(AC_CONTEXT, c);
+ SET_DFC(dfc);
+
+ return;
+}
+
+extern void __iomem *sun3_ioremap(unsigned long phys, unsigned long size,
+ unsigned long type);
+
+extern int sun3_map_test(unsigned long addr, char *val);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* !__SUN3_MMU_H__ */
diff --git a/arch/m68k/include/asm/sun3x.h b/arch/m68k/include/asm/sun3x.h
new file mode 100644
index 0000000..b3a83bc
--- /dev/null
+++ b/arch/m68k/include/asm/sun3x.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef SUN3X_H
+#define SUN3X_H
+
+/* hardware addresses */
+#define SUN3X_IOMMU 0x60000000
+#define SUN3X_ENAREG 0x61000000
+#define SUN3X_INTREG 0x61001400
+#define SUN3X_DIAGREG 0x61001800
+#define SUN3X_ZS1 0x62000000
+#define SUN3X_ZS2 0x62002000
+#define SUN3X_LANCE 0x65002000
+#define SUN3X_EEPROM 0x64000000
+#define SUN3X_IDPROM 0x640007d8
+#define SUN3X_VIDEO_BASE 0x50000000
+#define SUN3X_VIDEO_P4ID 0x50300000
+#define SUN3X_ESP_BASE 0x66000000
+#define SUN3X_ESP_DMA 0x66001000
+#define SUN3X_FDC 0x6e000000
+#define SUN3X_FDC_FCR 0x6e000400
+#define SUN3X_FDC_FVR 0x6e000800
+
+/* some NVRAM addresses */
+#define SUN3X_EEPROM_CONS (SUN3X_EEPROM + 0x1f)
+#define SUN3X_EEPROM_PORTA (SUN3X_EEPROM + 0x58)
+#define SUN3X_EEPROM_PORTB (SUN3X_EEPROM + 0x60)
+
+#endif
diff --git a/arch/m68k/include/asm/sun3xflop.h b/arch/m68k/include/asm/sun3xflop.h
new file mode 100644
index 0000000..ef04c43
--- /dev/null
+++ b/arch/m68k/include/asm/sun3xflop.h
@@ -0,0 +1,263 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* sun3xflop.h: Sun3/80 specific parts of the floppy driver.
+ *
+ * Derived partially from asm-sparc/floppy.h, which is:
+ * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
+ *
+ * Sun3x version 2/4/2000 Sam Creasey (sammy@sammy.net)
+ */
+
+#ifndef __ASM_SUN3X_FLOPPY_H
+#define __ASM_SUN3X_FLOPPY_H
+
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+#include <asm/sun3x.h>
+
+/* default interrupt vector */
+#define SUN3X_FDC_IRQ 0x40
+
+/* some constants */
+#define FCR_TC 0x1
+#define FCR_EJECT 0x2
+#define FCR_MTRON 0x4
+#define FCR_DSEL1 0x8
+#define FCR_DSEL0 0x10
+
+/* We don't need no stinkin' I/O port allocation crap. */
+#undef release_region
+#undef request_region
+#define release_region(X, Y) do { } while(0)
+#define request_region(X, Y, Z) (1)
+
+struct sun3xflop_private {
+ volatile unsigned char *status_r;
+ volatile unsigned char *data_r;
+ volatile unsigned char *fcr_r;
+ volatile unsigned char *fvr_r;
+ unsigned char fcr;
+} sun3x_fdc;
+
+/* Super paranoid... */
+#undef HAVE_DISABLE_HLT
+
+/* Routines unique to each controller type on a Sun. */
+static unsigned char sun3x_82072_fd_inb(int port)
+{
+ static int once = 0;
+// udelay(5);
+ switch(port & 7) {
+ default:
+ pr_crit("floppy: Asked to read unknown port %d\n", port);
+ panic("floppy: Port bolixed.");
+ case 4: /* FD_STATUS */
+ return (*sun3x_fdc.status_r) & ~STATUS_DMA;
+ case 5: /* FD_DATA */
+ return (*sun3x_fdc.data_r);
+ case 7: /* FD_DIR */
+ /* ugly hack, I can't find a way to actually detect the disk */
+ if(!once) {
+ once = 1;
+ return 0x80;
+ }
+ return 0;
+ };
+ panic("sun_82072_fd_inb: How did I get here?");
+}
+
+static void sun3x_82072_fd_outb(unsigned char value, int port)
+{
+// udelay(5);
+ switch(port & 7) {
+ default:
+ pr_crit("floppy: Asked to write to unknown port %d\n", port);
+ panic("floppy: Port bolixed.");
+ case 2: /* FD_DOR */
+ /* Oh geese, 82072 on the Sun has no DOR register,
+ * so we make do with taunting the FCR.
+ *
+ * ASSUMPTIONS: There will only ever be one floppy
+ * drive attached to a Sun controller
+ * and it will be at drive zero.
+ */
+
+ {
+ unsigned char fcr = sun3x_fdc.fcr;
+
+ if(value & 0x10) {
+ fcr |= (FCR_DSEL0 | FCR_MTRON);
+ } else
+ fcr &= ~(FCR_DSEL0 | FCR_MTRON);
+
+
+ if(fcr != sun3x_fdc.fcr) {
+ *(sun3x_fdc.fcr_r) = fcr;
+ sun3x_fdc.fcr = fcr;
+ }
+ }
+ break;
+ case 5: /* FD_DATA */
+ *(sun3x_fdc.data_r) = value;
+ break;
+ case 7: /* FD_DCR */
+ *(sun3x_fdc.status_r) = value;
+ break;
+ case 4: /* FD_STATUS */
+ *(sun3x_fdc.status_r) = value;
+ break;
+ };
+ return;
+}
+
+
+asmlinkage irqreturn_t sun3xflop_hardint(int irq, void *dev_id)
+{
+ register unsigned char st;
+
+#undef TRACE_FLPY_INT
+#define NO_FLOPPY_ASSEMBLER
+
+#ifdef TRACE_FLPY_INT
+ static int calls=0;
+ static int bytes=0;
+ static int dma_wait=0;
+#endif
+ if(!doing_pdma) {
+ floppy_interrupt(irq, dev_id);
+ return IRQ_HANDLED;
+ }
+
+// pr_info("doing pdma\n");// st %x\n", sun_fdc->status_82072);
+
+#ifdef TRACE_FLPY_INT
+ if(!calls)
+ bytes = virtual_dma_count;
+#endif
+
+ {
+ register int lcount;
+ register char *lptr;
+
+ for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
+ lcount; lcount--, lptr++) {
+/* st=fd_inb(virtual_dma_port+4) & 0x80 ; */
+ st = *(sun3x_fdc.status_r);
+/* if(st != 0xa0) */
+/* break; */
+
+ if((st & 0x80) == 0) {
+ virtual_dma_count = lcount;
+ virtual_dma_addr = lptr;
+ return IRQ_HANDLED;
+ }
+
+ if((st & 0x20) == 0)
+ break;
+
+ if(virtual_dma_mode)
+/* fd_outb(*lptr, virtual_dma_port+5); */
+ *(sun3x_fdc.data_r) = *lptr;
+ else
+/* *lptr = fd_inb(virtual_dma_port+5); */
+ *lptr = *(sun3x_fdc.data_r);
+ }
+
+ virtual_dma_count = lcount;
+ virtual_dma_addr = lptr;
+/* st = fd_inb(virtual_dma_port+4); */
+ st = *(sun3x_fdc.status_r);
+ }
+
+#ifdef TRACE_FLPY_INT
+ calls++;
+#endif
+// pr_info("st=%02x\n", st);
+ if(st == 0x20)
+ return IRQ_HANDLED;
+ if(!(st & 0x20)) {
+ virtual_dma_residue += virtual_dma_count;
+ virtual_dma_count=0;
+ doing_pdma = 0;
+
+#ifdef TRACE_FLPY_INT
+ pr_info("count=%x, residue=%x calls=%d bytes=%x dma_wait=%d\n",
+ virtual_dma_count, virtual_dma_residue, calls, bytes,
+ dma_wait);
+ calls = 0;
+ dma_wait=0;
+#endif
+
+ floppy_interrupt(irq, dev_id);
+ return IRQ_HANDLED;
+ }
+
+
+#ifdef TRACE_FLPY_INT
+ if(!virtual_dma_count)
+ dma_wait++;
+#endif
+ return IRQ_HANDLED;
+}
+
+static int sun3xflop_request_irq(void)
+{
+ static int once = 0;
+ int error;
+
+ if(!once) {
+ once = 1;
+ error = request_irq(FLOPPY_IRQ, sun3xflop_hardint,
+ 0, "floppy", NULL);
+ return ((error == 0) ? 0 : -1);
+ } else return 0;
+}
+
+static void __init floppy_set_flags(int *ints,int param, int param2);
+
+static int sun3xflop_init(void)
+{
+ if(FLOPPY_IRQ < 0x40)
+ FLOPPY_IRQ = SUN3X_FDC_IRQ;
+
+ sun3x_fdc.status_r = (volatile unsigned char *)SUN3X_FDC;
+ sun3x_fdc.data_r = (volatile unsigned char *)(SUN3X_FDC+1);
+ sun3x_fdc.fcr_r = (volatile unsigned char *)SUN3X_FDC_FCR;
+ sun3x_fdc.fvr_r = (volatile unsigned char *)SUN3X_FDC_FVR;
+ sun3x_fdc.fcr = 0;
+
+ /* Last minute sanity check... */
+ if(*sun3x_fdc.status_r == 0xff) {
+ return -1;
+ }
+
+ *sun3x_fdc.fvr_r = FLOPPY_IRQ;
+
+ *sun3x_fdc.fcr_r = FCR_TC;
+ udelay(10);
+ *sun3x_fdc.fcr_r = 0;
+
+ /* Success... */
+ floppy_set_flags(NULL, 1, FD_BROKEN_DCL); // I don't know how to detect this.
+ allowed_drive_mask = 0x01;
+ return (int) SUN3X_FDC;
+}
+
+/* I'm not precisely sure this eject routine works */
+static int sun3x_eject(void)
+{
+ if(MACH_IS_SUN3X) {
+
+ sun3x_fdc.fcr |= (FCR_DSEL0 | FCR_EJECT);
+ *(sun3x_fdc.fcr_r) = sun3x_fdc.fcr;
+ udelay(10);
+ sun3x_fdc.fcr &= ~(FCR_DSEL0 | FCR_EJECT);
+ *(sun3x_fdc.fcr_r) = sun3x_fdc.fcr;
+ }
+
+ return 0;
+}
+
+#define fd_eject(drive) sun3x_eject()
+
+#endif /* !(__ASM_SUN3X_FLOPPY_H) */
diff --git a/arch/m68k/include/asm/sun3xprom.h b/arch/m68k/include/asm/sun3xprom.h
new file mode 100644
index 0000000..d244ca4
--- /dev/null
+++ b/arch/m68k/include/asm/sun3xprom.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Useful PROM locations */
+
+#ifndef SUN3X_PROM_H
+#define SUN3X_PROM_H
+
+extern void (*sun3x_putchar)(int);
+extern int (*sun3x_getchar)(void);
+extern int (*sun3x_mayget)(void);
+extern int (*sun3x_mayput)(int);
+
+void sun3x_reboot(void);
+void sun3x_abort(void);
+void sun3x_prom_init(void);
+unsigned long sun3x_prom_ptov(unsigned long pa, unsigned long size);
+
+/* interesting hardware locations */
+#define SUN3X_IOMMU 0x60000000
+#define SUN3X_ENAREG 0x61000000
+#define SUN3X_INTREG 0x61001400
+#define SUN3X_DIAGREG 0x61001800
+#define SUN3X_ZS1 0x62000000
+#define SUN3X_ZS2 0x62002000
+#define SUN3X_LANCE 0x65002000
+#define SUN3X_EEPROM 0x64000000
+#define SUN3X_IDPROM 0x640007d8
+#define SUN3X_VIDEO_BASE 0x50400000
+#define SUN3X_VIDEO_REGS 0x50300000
+
+/* vector table */
+#define SUN3X_PROM_BASE 0xfefe0000
+#define SUN3X_P_GETCHAR (SUN3X_PROM_BASE + 20)
+#define SUN3X_P_PUTCHAR (SUN3X_PROM_BASE + 24)
+#define SUN3X_P_MAYGET (SUN3X_PROM_BASE + 28)
+#define SUN3X_P_MAYPUT (SUN3X_PROM_BASE + 32)
+#define SUN3X_P_REBOOT (SUN3X_PROM_BASE + 96)
+#define SUN3X_P_SETLEDS (SUN3X_PROM_BASE + 144)
+#define SUN3X_P_ABORT (SUN3X_PROM_BASE + 152)
+
+/* mapped area */
+#define SUN3X_MAP_START 0xfee00000
+#define SUN3X_MAP_END 0xff000000
+
+#endif
diff --git a/arch/m68k/include/asm/switch_to.h b/arch/m68k/include/asm/switch_to.h
new file mode 100644
index 0000000..94f02f4
--- /dev/null
+++ b/arch/m68k/include/asm/switch_to.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_SWITCH_TO_H
+#define _M68K_SWITCH_TO_H
+
+/*
+ * switch_to(n) should switch tasks to task ptr, first checking that
+ * ptr isn't the current task, in which case it does nothing. This
+ * also clears the TS-flag if the task we switched to has used the
+ * math co-processor latest.
+ */
+/*
+ * switch_to() saves the extra registers, that are not saved
+ * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
+ * a0-a1. Some of these are used by schedule() and its predecessors
+ * and so we might get see unexpected behaviors when a task returns
+ * with unexpected register values.
+ *
+ * syscall stores these registers itself and none of them are used
+ * by syscall after the function in the syscall has been called.
+ *
+ * Beware that resume now expects *next to be in d1 and the offset of
+ * tss to be in a1. This saves a few instructions as we no longer have
+ * to push them onto the stack and read them back right after.
+ *
+ * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
+ *
+ * Changed 96/09/19 by Andreas Schwab
+ * pass prev in a0, next in a1
+ */
+asmlinkage void resume(void);
+#define switch_to(prev,next,last) do { \
+ register void *_prev __asm__ ("a0") = (prev); \
+ register void *_next __asm__ ("a1") = (next); \
+ register void *_last __asm__ ("d1"); \
+ __asm__ __volatile__("jbsr resume" \
+ : "=a" (_prev), "=a" (_next), "=d" (_last) \
+ : "0" (_prev), "1" (_next) \
+ : "d0", "d2", "d3", "d4", "d5"); \
+ (last) = _last; \
+} while (0)
+
+#endif /* _M68K_SWITCH_TO_H */
diff --git a/arch/m68k/include/asm/thread_info.h b/arch/m68k/include/asm/thread_info.h
new file mode 100644
index 0000000..015f1ca
--- /dev/null
+++ b/arch/m68k/include/asm/thread_info.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_THREAD_INFO_H
+#define _ASM_M68K_THREAD_INFO_H
+
+#include <asm/types.h>
+#include <asm/page.h>
+#include <asm/segment.h>
+
+/*
+ * On machines with 4k pages we default to an 8k thread size, though we
+ * allow a 4k with config option. Any other machine page size then
+ * the thread size must match the page size (which is 8k and larger here).
+ */
+#if PAGE_SHIFT < 13
+#ifdef CONFIG_4KSTACKS
+#define THREAD_SIZE 4096
+#else
+#define THREAD_SIZE 8192
+#endif
+#else
+#define THREAD_SIZE PAGE_SIZE
+#endif
+#define THREAD_SIZE_ORDER ((THREAD_SIZE / PAGE_SIZE) - 1)
+
+#ifndef __ASSEMBLY__
+
+struct thread_info {
+ struct task_struct *task; /* main task structure */
+ unsigned long flags;
+ mm_segment_t addr_limit; /* thread address space */
+ int preempt_count; /* 0 => preemptable, <0 => BUG */
+ __u32 cpu; /* should always be 0 on m68k */
+ unsigned long tp_value; /* thread pointer */
+};
+#endif /* __ASSEMBLY__ */
+
+#define INIT_THREAD_INFO(tsk) \
+{ \
+ .task = &tsk, \
+ .addr_limit = KERNEL_DS, \
+ .preempt_count = INIT_PREEMPT_COUNT, \
+}
+
+#ifndef __ASSEMBLY__
+/* how to get the thread information struct from C */
+static inline struct thread_info *current_thread_info(void)
+{
+ struct thread_info *ti;
+ __asm__(
+ "move.l %%sp, %0 \n\t"
+ "and.l %1, %0"
+ : "=&d"(ti)
+ : "di" (~(THREAD_SIZE-1))
+ );
+ return ti;
+}
+#endif
+
+/* entry.S relies on these definitions!
+ * bits 0-7 are tested at every exception exit
+ * bits 8-15 are also tested at syscall exit
+ */
+#define TIF_NOTIFY_RESUME 5 /* callback before returning to user */
+#define TIF_SIGPENDING 6 /* signal pending */
+#define TIF_NEED_RESCHED 7 /* rescheduling necessary */
+#define TIF_DELAYED_TRACE 14 /* single step a syscall */
+#define TIF_SYSCALL_TRACE 15 /* syscall trace active */
+#define TIF_MEMDIE 16 /* is terminating due to OOM killer */
+#define TIF_RESTORE_SIGMASK 18 /* restore signal mask in do_signal */
+
+#endif /* _ASM_M68K_THREAD_INFO_H */
diff --git a/arch/m68k/include/asm/timex.h b/arch/m68k/include/asm/timex.h
new file mode 100644
index 0000000..6a21d93
--- /dev/null
+++ b/arch/m68k/include/asm/timex.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * linux/include/asm-m68k/timex.h
+ *
+ * m68k architecture timex specifications
+ */
+#ifndef _ASMm68K_TIMEX_H
+#define _ASMm68K_TIMEX_H
+
+#ifdef CONFIG_COLDFIRE
+/*
+ * CLOCK_TICK_RATE should give the underlying frequency of the tick timer
+ * to make ntp work best. For Coldfires, that's the main clock.
+ */
+#include <asm/coldfire.h>
+#define CLOCK_TICK_RATE MCF_CLK
+#else
+/*
+ * This default CLOCK_TICK_RATE is probably wrong for many 68k boards
+ * Users of those boards will need to check and modify accordingly
+ */
+#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
+#endif
+
+typedef unsigned long cycles_t;
+
+static inline cycles_t get_cycles(void)
+{
+ return 0;
+}
+
+extern unsigned long (*mach_random_get_entropy)(void);
+
+static inline unsigned long random_get_entropy(void)
+{
+ if (mach_random_get_entropy)
+ return mach_random_get_entropy();
+ return 0;
+}
+#define random_get_entropy random_get_entropy
+
+#endif
diff --git a/arch/m68k/include/asm/tlb.h b/arch/m68k/include/asm/tlb.h
new file mode 100644
index 0000000..b4b9efb
--- /dev/null
+++ b/arch/m68k/include/asm/tlb.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_TLB_H
+#define _M68K_TLB_H
+
+/*
+ * m68k doesn't need any special per-pte or
+ * per-vma handling..
+ */
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_end_vma(tlb, vma) do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
+
+/*
+ * .. because we flush the whole mm when it
+ * fills up.
+ */
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+
+#include <asm-generic/tlb.h>
+
+#endif /* _M68K_TLB_H */
diff --git a/arch/m68k/include/asm/tlbflush.h b/arch/m68k/include/asm/tlbflush.h
new file mode 100644
index 0000000..191e75a
--- /dev/null
+++ b/arch/m68k/include/asm/tlbflush.h
@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_TLBFLUSH_H
+#define _M68K_TLBFLUSH_H
+
+#ifdef CONFIG_MMU
+#ifndef CONFIG_SUN3
+
+#include <asm/current.h>
+#include <asm/mcfmmu.h>
+
+static inline void flush_tlb_kernel_page(void *addr)
+{
+ if (CPU_IS_COLDFIRE) {
+ mmu_write(MMUOR, MMUOR_CNL);
+ } else if (CPU_IS_040_OR_060) {
+ mm_segment_t old_fs = get_fs();
+ set_fs(KERNEL_DS);
+ __asm__ __volatile__(".chip 68040\n\t"
+ "pflush (%0)\n\t"
+ ".chip 68k"
+ : : "a" (addr));
+ set_fs(old_fs);
+ } else if (CPU_IS_020_OR_030)
+ __asm__ __volatile__("pflush #4,#4,(%0)" : : "a" (addr));
+}
+
+/*
+ * flush all user-space atc entries.
+ */
+static inline void __flush_tlb(void)
+{
+ if (CPU_IS_COLDFIRE) {
+ mmu_write(MMUOR, MMUOR_CNL);
+ } else if (CPU_IS_040_OR_060) {
+ __asm__ __volatile__(".chip 68040\n\t"
+ "pflushan\n\t"
+ ".chip 68k");
+ } else if (CPU_IS_020_OR_030) {
+ __asm__ __volatile__("pflush #0,#4");
+ }
+}
+
+static inline void __flush_tlb040_one(unsigned long addr)
+{
+ __asm__ __volatile__(".chip 68040\n\t"
+ "pflush (%0)\n\t"
+ ".chip 68k"
+ : : "a" (addr));
+}
+
+static inline void __flush_tlb_one(unsigned long addr)
+{
+ if (CPU_IS_COLDFIRE)
+ mmu_write(MMUOR, MMUOR_CNL);
+ else if (CPU_IS_040_OR_060)
+ __flush_tlb040_one(addr);
+ else if (CPU_IS_020_OR_030)
+ __asm__ __volatile__("pflush #0,#4,(%0)" : : "a" (addr));
+}
+
+#define flush_tlb() __flush_tlb()
+
+/*
+ * flush all atc entries (both kernel and user-space entries).
+ */
+static inline void flush_tlb_all(void)
+{
+ if (CPU_IS_COLDFIRE) {
+ mmu_write(MMUOR, MMUOR_CNL);
+ } else if (CPU_IS_040_OR_060) {
+ __asm__ __volatile__(".chip 68040\n\t"
+ "pflusha\n\t"
+ ".chip 68k");
+ } else if (CPU_IS_020_OR_030) {
+ __asm__ __volatile__("pflusha");
+ }
+}
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+ if (mm == current->active_mm)
+ __flush_tlb();
+}
+
+static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
+{
+ if (vma->vm_mm == current->active_mm) {
+ mm_segment_t old_fs = get_fs();
+ set_fs(USER_DS);
+ __flush_tlb_one(addr);
+ set_fs(old_fs);
+ }
+}
+
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ if (vma->vm_mm == current->active_mm)
+ __flush_tlb();
+}
+
+static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end)
+{
+ flush_tlb_all();
+}
+
+#else
+
+
+/* Reserved PMEGs. */
+extern char sun3_reserved_pmeg[SUN3_PMEGS_NUM];
+extern unsigned long pmeg_vaddr[SUN3_PMEGS_NUM];
+extern unsigned char pmeg_alloc[SUN3_PMEGS_NUM];
+extern unsigned char pmeg_ctx[SUN3_PMEGS_NUM];
+
+/* Flush all userspace mappings one by one... (why no flush command,
+ sun?) */
+static inline void flush_tlb_all(void)
+{
+ unsigned long addr;
+ unsigned char ctx, oldctx;
+
+ oldctx = sun3_get_context();
+ for(addr = 0x00000000; addr < TASK_SIZE; addr += SUN3_PMEG_SIZE) {
+ for(ctx = 0; ctx < 8; ctx++) {
+ sun3_put_context(ctx);
+ sun3_put_segmap(addr, SUN3_INVALID_PMEG);
+ }
+ }
+
+ sun3_put_context(oldctx);
+ /* erase all of the userspace pmeg maps, we've clobbered them
+ all anyway */
+ for(addr = 0; addr < SUN3_INVALID_PMEG; addr++) {
+ if(pmeg_alloc[addr] == 1) {
+ pmeg_alloc[addr] = 0;
+ pmeg_ctx[addr] = 0;
+ pmeg_vaddr[addr] = 0;
+ }
+ }
+
+}
+
+/* Clear user TLB entries within the context named in mm */
+static inline void flush_tlb_mm (struct mm_struct *mm)
+{
+ unsigned char oldctx;
+ unsigned char seg;
+ unsigned long i;
+
+ oldctx = sun3_get_context();
+ sun3_put_context(mm->context);
+
+ for(i = 0; i < TASK_SIZE; i += SUN3_PMEG_SIZE) {
+ seg = sun3_get_segmap(i);
+ if(seg == SUN3_INVALID_PMEG)
+ continue;
+
+ sun3_put_segmap(i, SUN3_INVALID_PMEG);
+ pmeg_alloc[seg] = 0;
+ pmeg_ctx[seg] = 0;
+ pmeg_vaddr[seg] = 0;
+ }
+
+ sun3_put_context(oldctx);
+
+}
+
+/* Flush a single TLB page. In this case, we're limited to flushing a
+ single PMEG */
+static inline void flush_tlb_page (struct vm_area_struct *vma,
+ unsigned long addr)
+{
+ unsigned char oldctx;
+ unsigned char i;
+
+ oldctx = sun3_get_context();
+ sun3_put_context(vma->vm_mm->context);
+ addr &= ~SUN3_PMEG_MASK;
+ if((i = sun3_get_segmap(addr)) != SUN3_INVALID_PMEG)
+ {
+ pmeg_alloc[i] = 0;
+ pmeg_ctx[i] = 0;
+ pmeg_vaddr[i] = 0;
+ sun3_put_segmap (addr, SUN3_INVALID_PMEG);
+ }
+ sun3_put_context(oldctx);
+
+}
+/* Flush a range of pages from TLB. */
+
+static inline void flush_tlb_range (struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ struct mm_struct *mm = vma->vm_mm;
+ unsigned char seg, oldctx;
+
+ start &= ~SUN3_PMEG_MASK;
+
+ oldctx = sun3_get_context();
+ sun3_put_context(mm->context);
+
+ while(start < end)
+ {
+ if((seg = sun3_get_segmap(start)) == SUN3_INVALID_PMEG)
+ goto next;
+ if(pmeg_ctx[seg] == mm->context) {
+ pmeg_alloc[seg] = 0;
+ pmeg_ctx[seg] = 0;
+ pmeg_vaddr[seg] = 0;
+ }
+ sun3_put_segmap(start, SUN3_INVALID_PMEG);
+ next:
+ start += SUN3_PMEG_SIZE;
+ }
+}
+
+static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end)
+{
+ flush_tlb_all();
+}
+
+/* Flush kernel page from TLB. */
+static inline void flush_tlb_kernel_page (unsigned long addr)
+{
+ sun3_put_segmap (addr & ~(SUN3_PMEG_SIZE - 1), SUN3_INVALID_PMEG);
+}
+
+#endif
+
+#else /* !CONFIG_MMU */
+
+/*
+ * flush all user-space atc entries.
+ */
+static inline void __flush_tlb(void)
+{
+ BUG();
+}
+
+static inline void __flush_tlb_one(unsigned long addr)
+{
+ BUG();
+}
+
+#define flush_tlb() __flush_tlb()
+
+/*
+ * flush all atc entries (both kernel and user-space entries).
+ */
+static inline void flush_tlb_all(void)
+{
+ BUG();
+}
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+ BUG();
+}
+
+static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
+{
+ BUG();
+}
+
+static inline void flush_tlb_range(struct mm_struct *mm,
+ unsigned long start, unsigned long end)
+{
+ BUG();
+}
+
+static inline void flush_tlb_kernel_page(unsigned long addr)
+{
+ BUG();
+}
+
+#endif /* CONFIG_MMU */
+
+#endif /* _M68K_TLBFLUSH_H */
diff --git a/arch/m68k/include/asm/traps.h b/arch/m68k/include/asm/traps.h
new file mode 100644
index 0000000..4aff335
--- /dev/null
+++ b/arch/m68k/include/asm/traps.h
@@ -0,0 +1,272 @@
+/*
+ * linux/include/asm/traps.h
+ *
+ * Copyright (C) 1993 Hamish Macdonald
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _M68K_TRAPS_H
+#define _M68K_TRAPS_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/linkage.h>
+#include <asm/ptrace.h>
+
+typedef void (*e_vector)(void);
+extern e_vector vectors[];
+extern e_vector *_ramvec;
+
+asmlinkage void auto_inthandler(void);
+asmlinkage void user_inthandler(void);
+asmlinkage void bad_inthandler(void);
+
+#endif
+
+#define VEC_RESETSP (0)
+#define VEC_RESETPC (1)
+#define VEC_BUSERR (2)
+#define VEC_ADDRERR (3)
+#define VEC_ILLEGAL (4)
+#define VEC_ZERODIV (5)
+#define VEC_CHK (6)
+#define VEC_TRAP (7)
+#define VEC_PRIV (8)
+#define VEC_TRACE (9)
+#define VEC_LINE10 (10)
+#define VEC_LINE11 (11)
+#define VEC_RESV12 (12)
+#define VEC_COPROC (13)
+#define VEC_FORMAT (14)
+#define VEC_UNINT (15)
+#define VEC_RESV16 (16)
+#define VEC_RESV17 (17)
+#define VEC_RESV18 (18)
+#define VEC_RESV19 (19)
+#define VEC_RESV20 (20)
+#define VEC_RESV21 (21)
+#define VEC_RESV22 (22)
+#define VEC_RESV23 (23)
+#define VEC_SPUR (24)
+#define VEC_INT1 (25)
+#define VEC_INT2 (26)
+#define VEC_INT3 (27)
+#define VEC_INT4 (28)
+#define VEC_INT5 (29)
+#define VEC_INT6 (30)
+#define VEC_INT7 (31)
+#define VEC_SYS (32)
+#define VEC_TRAP1 (33)
+#define VEC_TRAP2 (34)
+#define VEC_TRAP3 (35)
+#define VEC_TRAP4 (36)
+#define VEC_TRAP5 (37)
+#define VEC_TRAP6 (38)
+#define VEC_TRAP7 (39)
+#define VEC_TRAP8 (40)
+#define VEC_TRAP9 (41)
+#define VEC_TRAP10 (42)
+#define VEC_TRAP11 (43)
+#define VEC_TRAP12 (44)
+#define VEC_TRAP13 (45)
+#define VEC_TRAP14 (46)
+#define VEC_TRAP15 (47)
+#define VEC_FPBRUC (48)
+#define VEC_FPIR (49)
+#define VEC_FPDIVZ (50)
+#define VEC_FPUNDER (51)
+#define VEC_FPOE (52)
+#define VEC_FPOVER (53)
+#define VEC_FPNAN (54)
+#define VEC_FPUNSUP (55)
+#define VEC_MMUCFG (56)
+#define VEC_MMUILL (57)
+#define VEC_MMUACC (58)
+#define VEC_RESV59 (59)
+#define VEC_UNIMPEA (60)
+#define VEC_UNIMPII (61)
+#define VEC_RESV62 (62)
+#define VEC_RESV63 (63)
+#define VEC_USER (64)
+
+#define VECOFF(vec) ((vec)<<2)
+
+#ifndef __ASSEMBLY__
+
+/* Status register bits */
+#define PS_T (0x8000)
+#define PS_S (0x2000)
+#define PS_M (0x1000)
+#define PS_C (0x0001)
+
+/* bits for 68020/68030 special status word */
+
+#define FC (0x8000)
+#define FB (0x4000)
+#define RC (0x2000)
+#define RB (0x1000)
+#define DF (0x0100)
+#define RM (0x0080)
+#define RW (0x0040)
+#define SZ (0x0030)
+#define DFC (0x0007)
+
+/* bits for 68030 MMU status register (mmusr,psr) */
+
+#define MMU_B (0x8000) /* bus error */
+#define MMU_L (0x4000) /* limit violation */
+#define MMU_S (0x2000) /* supervisor violation */
+#define MMU_WP (0x0800) /* write-protected */
+#define MMU_I (0x0400) /* invalid descriptor */
+#define MMU_M (0x0200) /* ATC entry modified */
+#define MMU_T (0x0040) /* transparent translation */
+#define MMU_NUM (0x0007) /* number of levels traversed */
+
+
+/* bits for 68040 special status word */
+#define CP_040 (0x8000)
+#define CU_040 (0x4000)
+#define CT_040 (0x2000)
+#define CM_040 (0x1000)
+#define MA_040 (0x0800)
+#define ATC_040 (0x0400)
+#define LK_040 (0x0200)
+#define RW_040 (0x0100)
+#define SIZ_040 (0x0060)
+#define TT_040 (0x0018)
+#define TM_040 (0x0007)
+
+/* bits for 68040 write back status word */
+#define WBV_040 (0x80)
+#define WBSIZ_040 (0x60)
+#define WBBYT_040 (0x20)
+#define WBWRD_040 (0x40)
+#define WBLNG_040 (0x00)
+#define WBTT_040 (0x18)
+#define WBTM_040 (0x07)
+
+/* bus access size codes */
+#define BA_SIZE_BYTE (0x20)
+#define BA_SIZE_WORD (0x40)
+#define BA_SIZE_LONG (0x00)
+#define BA_SIZE_LINE (0x60)
+
+/* bus access transfer type codes */
+#define BA_TT_MOVE16 (0x08)
+
+/* bits for 68040 MMU status register (mmusr) */
+#define MMU_B_040 (0x0800)
+#define MMU_G_040 (0x0400)
+#define MMU_S_040 (0x0080)
+#define MMU_CM_040 (0x0060)
+#define MMU_M_040 (0x0010)
+#define MMU_WP_040 (0x0004)
+#define MMU_T_040 (0x0002)
+#define MMU_R_040 (0x0001)
+
+/* bits in the 68060 fault status long word (FSLW) */
+#define MMU060_MA (0x08000000) /* misaligned */
+#define MMU060_LK (0x02000000) /* locked transfer */
+#define MMU060_RW (0x01800000) /* read/write */
+# define MMU060_RW_W (0x00800000) /* write */
+# define MMU060_RW_R (0x01000000) /* read */
+# define MMU060_RW_RMW (0x01800000) /* read/modify/write */
+# define MMU060_W (0x00800000) /* general write, includes rmw */
+#define MMU060_SIZ (0x00600000) /* transfer size */
+#define MMU060_TT (0x00180000) /* transfer type (TT) bits */
+#define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */
+#define MMU060_IO (0x00008000) /* instruction or operand */
+#define MMU060_PBE (0x00004000) /* push buffer bus error */
+#define MMU060_SBE (0x00002000) /* store buffer bus error */
+#define MMU060_PTA (0x00001000) /* pointer A fault */
+#define MMU060_PTB (0x00000800) /* pointer B fault */
+#define MMU060_IL (0x00000400) /* double indirect descr fault */
+#define MMU060_PF (0x00000200) /* page fault (invalid descr) */
+#define MMU060_SP (0x00000100) /* supervisor protection */
+#define MMU060_WP (0x00000080) /* write protection */
+#define MMU060_TWE (0x00000040) /* bus error on table search */
+#define MMU060_RE (0x00000020) /* bus error on read */
+#define MMU060_WE (0x00000010) /* bus error on write */
+#define MMU060_TTR (0x00000008) /* error caused by TTR translation */
+#define MMU060_BPE (0x00000004) /* branch prediction error */
+#define MMU060_SEE (0x00000001) /* software emulated error */
+
+/* cases of missing or invalid descriptors */
+#define MMU060_DESC_ERR (MMU060_PTA | MMU060_PTB | \
+ MMU060_IL | MMU060_PF)
+/* bits that indicate real errors */
+#define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | MMU060_SP | \
+ MMU060_WP | MMU060_TWE | MMU060_RE | MMU060_WE)
+
+/* structure for stack frames */
+
+struct frame {
+ struct pt_regs ptregs;
+ union {
+ struct {
+ unsigned long iaddr; /* instruction address */
+ } fmt2;
+ struct {
+ unsigned long effaddr; /* effective address */
+ } fmt3;
+ struct {
+ unsigned long effaddr; /* effective address */
+ unsigned long pc; /* pc of faulted instr */
+ } fmt4;
+ struct {
+ unsigned long effaddr; /* effective address */
+ unsigned short ssw; /* special status word */
+ unsigned short wb3s; /* write back 3 status */
+ unsigned short wb2s; /* write back 2 status */
+ unsigned short wb1s; /* write back 1 status */
+ unsigned long faddr; /* fault address */
+ unsigned long wb3a; /* write back 3 address */
+ unsigned long wb3d; /* write back 3 data */
+ unsigned long wb2a; /* write back 2 address */
+ unsigned long wb2d; /* write back 2 data */
+ unsigned long wb1a; /* write back 1 address */
+ unsigned long wb1dpd0; /* write back 1 data/push data 0*/
+ unsigned long pd1; /* push data 1*/
+ unsigned long pd2; /* push data 2*/
+ unsigned long pd3; /* push data 3*/
+ } fmt7;
+ struct {
+ unsigned long iaddr; /* instruction address */
+ unsigned short int1[4]; /* internal registers */
+ } fmt9;
+ struct {
+ unsigned short int1;
+ unsigned short ssw; /* special status word */
+ unsigned short isc; /* instruction stage c */
+ unsigned short isb; /* instruction stage b */
+ unsigned long daddr; /* data cycle fault address */
+ unsigned short int2[2];
+ unsigned long dobuf; /* data cycle output buffer */
+ unsigned short int3[2];
+ } fmta;
+ struct {
+ unsigned short int1;
+ unsigned short ssw; /* special status word */
+ unsigned short isc; /* instruction stage c */
+ unsigned short isb; /* instruction stage b */
+ unsigned long daddr; /* data cycle fault address */
+ unsigned short int2[2];
+ unsigned long dobuf; /* data cycle output buffer */
+ unsigned short int3[4];
+ unsigned long baddr; /* stage B address */
+ unsigned short int4[2];
+ unsigned long dibuf; /* data cycle input buffer */
+ unsigned short int5[3];
+ unsigned ver : 4; /* stack frame version # */
+ unsigned int6:12;
+ unsigned short int7[18];
+ } fmtb;
+ } un;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _M68K_TRAPS_H */
diff --git a/arch/m68k/include/asm/uaccess.h b/arch/m68k/include/asm/uaccess.h
new file mode 100644
index 0000000..e896466
--- /dev/null
+++ b/arch/m68k/include/asm/uaccess.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifdef __uClinux__
+#include <asm/uaccess_no.h>
+#else
+#include <asm/uaccess_mm.h>
+#endif
+#include <asm/extable.h>
diff --git a/arch/m68k/include/asm/uaccess_mm.h b/arch/m68k/include/asm/uaccess_mm.h
new file mode 100644
index 0000000..c4cb889
--- /dev/null
+++ b/arch/m68k/include/asm/uaccess_mm.h
@@ -0,0 +1,390 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __M68K_UACCESS_H
+#define __M68K_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/segment.h>
+
+/* We let the MMU do all checking */
+static inline int access_ok(int type, const void __user *addr,
+ unsigned long size)
+{
+ return 1;
+}
+
+/*
+ * Not all varients of the 68k family support the notion of address spaces.
+ * The traditional 680x0 parts do, and they use the sfc/dfc registers and
+ * the "moves" instruction to access user space from kernel space. Other
+ * family members like ColdFire don't support this, and only have a single
+ * address space, and use the usual "move" instruction for user space access.
+ *
+ * Outside of this difference the user space access functions are the same.
+ * So lets keep the code simple and just define in what we need to use.
+ */
+#ifdef CONFIG_CPU_HAS_ADDRESS_SPACES
+#define MOVES "moves"
+#else
+#define MOVES "move"
+#endif
+
+extern int __put_user_bad(void);
+extern int __get_user_bad(void);
+
+#define __put_user_asm(res, x, ptr, bwl, reg, err) \
+asm volatile ("\n" \
+ "1: "MOVES"."#bwl" %2,%1\n" \
+ "2:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "10: moveq.l %3,%0\n" \
+ " jra 2b\n" \
+ " .previous\n" \
+ "\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 1b,10b\n" \
+ " .long 2b,10b\n" \
+ " .previous" \
+ : "+d" (res), "=m" (*(ptr)) \
+ : #reg (x), "i" (err))
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ */
+
+#define __put_user(x, ptr) \
+({ \
+ typeof(*(ptr)) __pu_val = (x); \
+ int __pu_err = 0; \
+ __chk_user_ptr(ptr); \
+ switch (sizeof (*(ptr))) { \
+ case 1: \
+ __put_user_asm(__pu_err, __pu_val, ptr, b, d, -EFAULT); \
+ break; \
+ case 2: \
+ __put_user_asm(__pu_err, __pu_val, ptr, w, r, -EFAULT); \
+ break; \
+ case 4: \
+ __put_user_asm(__pu_err, __pu_val, ptr, l, r, -EFAULT); \
+ break; \
+ case 8: \
+ { \
+ const void __user *__pu_ptr = (ptr); \
+ asm volatile ("\n" \
+ "1: "MOVES".l %2,(%1)+\n" \
+ "2: "MOVES".l %R2,(%1)\n" \
+ "3:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "10: movel %3,%0\n" \
+ " jra 3b\n" \
+ " .previous\n" \
+ "\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 1b,10b\n" \
+ " .long 2b,10b\n" \
+ " .long 3b,10b\n" \
+ " .previous" \
+ : "+d" (__pu_err), "+a" (__pu_ptr) \
+ : "r" (__pu_val), "i" (-EFAULT) \
+ : "memory"); \
+ break; \
+ } \
+ default: \
+ __pu_err = __put_user_bad(); \
+ break; \
+ } \
+ __pu_err; \
+})
+#define put_user(x, ptr) __put_user(x, ptr)
+
+
+#define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \
+ type __gu_val; \
+ asm volatile ("\n" \
+ "1: "MOVES"."#bwl" %2,%1\n" \
+ "2:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "10: move.l %3,%0\n" \
+ " sub.l %1,%1\n" \
+ " jra 2b\n" \
+ " .previous\n" \
+ "\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 1b,10b\n" \
+ " .previous" \
+ : "+d" (res), "=&" #reg (__gu_val) \
+ : "m" (*(ptr)), "i" (err)); \
+ (x) = (__force typeof(*(ptr)))(__force unsigned long)__gu_val; \
+})
+
+#define __get_user(x, ptr) \
+({ \
+ int __gu_err = 0; \
+ __chk_user_ptr(ptr); \
+ switch (sizeof(*(ptr))) { \
+ case 1: \
+ __get_user_asm(__gu_err, x, ptr, u8, b, d, -EFAULT); \
+ break; \
+ case 2: \
+ __get_user_asm(__gu_err, x, ptr, u16, w, r, -EFAULT); \
+ break; \
+ case 4: \
+ __get_user_asm(__gu_err, x, ptr, u32, l, r, -EFAULT); \
+ break; \
+ case 8: { \
+ const void *__gu_ptr = (ptr); \
+ union { \
+ u64 l; \
+ __typeof__(*(ptr)) t; \
+ } __gu_val; \
+ asm volatile ("\n" \
+ "1: "MOVES".l (%2)+,%1\n" \
+ "2: "MOVES".l (%2),%R1\n" \
+ "3:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "10: move.l %3,%0\n" \
+ " sub.l %1,%1\n" \
+ " sub.l %R1,%R1\n" \
+ " jra 3b\n" \
+ " .previous\n" \
+ "\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 1b,10b\n" \
+ " .long 2b,10b\n" \
+ " .previous" \
+ : "+d" (__gu_err), "=&r" (__gu_val.l), \
+ "+a" (__gu_ptr) \
+ : "i" (-EFAULT) \
+ : "memory"); \
+ (x) = __gu_val.t; \
+ break; \
+ } \
+ default: \
+ __gu_err = __get_user_bad(); \
+ break; \
+ } \
+ __gu_err; \
+})
+#define get_user(x, ptr) __get_user(x, ptr)
+
+unsigned long __generic_copy_from_user(void *to, const void __user *from, unsigned long n);
+unsigned long __generic_copy_to_user(void __user *to, const void *from, unsigned long n);
+
+#define __suffix0
+#define __suffix1 b
+#define __suffix2 w
+#define __suffix4 l
+
+#define ____constant_copy_from_user_asm(res, to, from, tmp, n1, n2, n3, s1, s2, s3)\
+ asm volatile ("\n" \
+ "1: "MOVES"."#s1" (%2)+,%3\n" \
+ " move."#s1" %3,(%1)+\n" \
+ " .ifnc \""#s2"\",\"\"\n" \
+ "2: "MOVES"."#s2" (%2)+,%3\n" \
+ " move."#s2" %3,(%1)+\n" \
+ " .ifnc \""#s3"\",\"\"\n" \
+ "3: "MOVES"."#s3" (%2)+,%3\n" \
+ " move."#s3" %3,(%1)+\n" \
+ " .endif\n" \
+ " .endif\n" \
+ "4:\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 1b,10f\n" \
+ " .ifnc \""#s2"\",\"\"\n" \
+ " .long 2b,20f\n" \
+ " .ifnc \""#s3"\",\"\"\n" \
+ " .long 3b,30f\n" \
+ " .endif\n" \
+ " .endif\n" \
+ " .previous\n" \
+ "\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "10: addq.l #"#n1",%0\n" \
+ " .ifnc \""#s2"\",\"\"\n" \
+ "20: addq.l #"#n2",%0\n" \
+ " .ifnc \""#s3"\",\"\"\n" \
+ "30: addq.l #"#n3",%0\n" \
+ " .endif\n" \
+ " .endif\n" \
+ " jra 4b\n" \
+ " .previous\n" \
+ : "+d" (res), "+&a" (to), "+a" (from), "=&d" (tmp) \
+ : : "memory")
+
+#define ___constant_copy_from_user_asm(res, to, from, tmp, n1, n2, n3, s1, s2, s3)\
+ ____constant_copy_from_user_asm(res, to, from, tmp, n1, n2, n3, s1, s2, s3)
+#define __constant_copy_from_user_asm(res, to, from, tmp, n1, n2, n3) \
+ ___constant_copy_from_user_asm(res, to, from, tmp, n1, n2, n3, \
+ __suffix##n1, __suffix##n2, __suffix##n3)
+
+static __always_inline unsigned long
+__constant_copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+ unsigned long res = 0, tmp;
+
+ switch (n) {
+ case 1:
+ __constant_copy_from_user_asm(res, to, from, tmp, 1, 0, 0);
+ break;
+ case 2:
+ __constant_copy_from_user_asm(res, to, from, tmp, 2, 0, 0);
+ break;
+ case 3:
+ __constant_copy_from_user_asm(res, to, from, tmp, 2, 1, 0);
+ break;
+ case 4:
+ __constant_copy_from_user_asm(res, to, from, tmp, 4, 0, 0);
+ break;
+ case 5:
+ __constant_copy_from_user_asm(res, to, from, tmp, 4, 1, 0);
+ break;
+ case 6:
+ __constant_copy_from_user_asm(res, to, from, tmp, 4, 2, 0);
+ break;
+ case 7:
+ __constant_copy_from_user_asm(res, to, from, tmp, 4, 2, 1);
+ break;
+ case 8:
+ __constant_copy_from_user_asm(res, to, from, tmp, 4, 4, 0);
+ break;
+ case 9:
+ __constant_copy_from_user_asm(res, to, from, tmp, 4, 4, 1);
+ break;
+ case 10:
+ __constant_copy_from_user_asm(res, to, from, tmp, 4, 4, 2);
+ break;
+ case 12:
+ __constant_copy_from_user_asm(res, to, from, tmp, 4, 4, 4);
+ break;
+ default:
+ /* we limit the inlined version to 3 moves */
+ return __generic_copy_from_user(to, from, n);
+ }
+
+ return res;
+}
+
+#define __constant_copy_to_user_asm(res, to, from, tmp, n, s1, s2, s3) \
+ asm volatile ("\n" \
+ " move."#s1" (%2)+,%3\n" \
+ "11: "MOVES"."#s1" %3,(%1)+\n" \
+ "12: move."#s2" (%2)+,%3\n" \
+ "21: "MOVES"."#s2" %3,(%1)+\n" \
+ "22:\n" \
+ " .ifnc \""#s3"\",\"\"\n" \
+ " move."#s3" (%2)+,%3\n" \
+ "31: "MOVES"."#s3" %3,(%1)+\n" \
+ "32:\n" \
+ " .endif\n" \
+ "4:\n" \
+ "\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 4\n" \
+ " .long 11b,5f\n" \
+ " .long 12b,5f\n" \
+ " .long 21b,5f\n" \
+ " .long 22b,5f\n" \
+ " .ifnc \""#s3"\",\"\"\n" \
+ " .long 31b,5f\n" \
+ " .long 32b,5f\n" \
+ " .endif\n" \
+ " .previous\n" \
+ "\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .even\n" \
+ "5: moveq.l #"#n",%0\n" \
+ " jra 4b\n" \
+ " .previous\n" \
+ : "+d" (res), "+a" (to), "+a" (from), "=&d" (tmp) \
+ : : "memory")
+
+static __always_inline unsigned long
+__constant_copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+ unsigned long res = 0, tmp;
+
+ switch (n) {
+ case 1:
+ __put_user_asm(res, *(u8 *)from, (u8 __user *)to, b, d, 1);
+ break;
+ case 2:
+ __put_user_asm(res, *(u16 *)from, (u16 __user *)to, w, r, 2);
+ break;
+ case 3:
+ __constant_copy_to_user_asm(res, to, from, tmp, 3, w, b,);
+ break;
+ case 4:
+ __put_user_asm(res, *(u32 *)from, (u32 __user *)to, l, r, 4);
+ break;
+ case 5:
+ __constant_copy_to_user_asm(res, to, from, tmp, 5, l, b,);
+ break;
+ case 6:
+ __constant_copy_to_user_asm(res, to, from, tmp, 6, l, w,);
+ break;
+ case 7:
+ __constant_copy_to_user_asm(res, to, from, tmp, 7, l, w, b);
+ break;
+ case 8:
+ __constant_copy_to_user_asm(res, to, from, tmp, 8, l, l,);
+ break;
+ case 9:
+ __constant_copy_to_user_asm(res, to, from, tmp, 9, l, l, b);
+ break;
+ case 10:
+ __constant_copy_to_user_asm(res, to, from, tmp, 10, l, l, w);
+ break;
+ case 12:
+ __constant_copy_to_user_asm(res, to, from, tmp, 12, l, l, l);
+ break;
+ default:
+ /* limit the inlined version to 3 moves */
+ return __generic_copy_to_user(to, from, n);
+ }
+
+ return res;
+}
+
+static inline unsigned long
+raw_copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+ if (__builtin_constant_p(n))
+ return __constant_copy_from_user(to, from, n);
+ return __generic_copy_from_user(to, from, n);
+}
+
+static inline unsigned long
+raw_copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+ if (__builtin_constant_p(n))
+ return __constant_copy_to_user(to, from, n);
+ return __generic_copy_to_user(to, from, n);
+}
+#define INLINE_COPY_FROM_USER
+#define INLINE_COPY_TO_USER
+
+#define user_addr_max() \
+ (uaccess_kernel() ? ~0UL : TASK_SIZE)
+
+extern long strncpy_from_user(char *dst, const char __user *src, long count);
+extern __must_check long strnlen_user(const char __user *str, long n);
+
+unsigned long __clear_user(void __user *to, unsigned long n);
+
+#define clear_user __clear_user
+
+#endif /* _M68K_UACCESS_H */
diff --git a/arch/m68k/include/asm/uaccess_no.h b/arch/m68k/include/asm/uaccess_no.h
new file mode 100644
index 0000000..892efb5
--- /dev/null
+++ b/arch/m68k/include/asm/uaccess_no.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __M68KNOMMU_UACCESS_H
+#define __M68KNOMMU_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <linux/mm.h>
+#include <linux/string.h>
+
+#include <asm/segment.h>
+
+#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size))
+
+/*
+ * It is not enough to just have access_ok check for a real RAM address.
+ * This would disallow the case of code/ro-data running XIP in flash/rom.
+ * Ideally we would check the possible flash ranges too, but that is
+ * currently not so easy.
+ */
+static inline int _access_ok(unsigned long addr, unsigned long size)
+{
+ return 1;
+}
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ */
+
+#define put_user(x, ptr) \
+({ \
+ int __pu_err = 0; \
+ typeof(*(ptr)) __pu_val = (x); \
+ switch (sizeof (*(ptr))) { \
+ case 1: \
+ __put_user_asm(__pu_err, __pu_val, ptr, b); \
+ break; \
+ case 2: \
+ __put_user_asm(__pu_err, __pu_val, ptr, w); \
+ break; \
+ case 4: \
+ __put_user_asm(__pu_err, __pu_val, ptr, l); \
+ break; \
+ case 8: \
+ memcpy(ptr, &__pu_val, sizeof (*(ptr))); \
+ break; \
+ default: \
+ __pu_err = __put_user_bad(); \
+ break; \
+ } \
+ __pu_err; \
+})
+#define __put_user(x, ptr) put_user(x, ptr)
+
+extern int __put_user_bad(void);
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define __put_user_asm(err,x,ptr,bwl) \
+ __asm__ ("move" #bwl " %0,%1" \
+ : /* no outputs */ \
+ :"d" (x),"m" (*__ptr(ptr)) : "memory")
+
+#define get_user(x, ptr) \
+({ \
+ int __gu_err = 0; \
+ typeof(x) __gu_val = 0; \
+ switch (sizeof(*(ptr))) { \
+ case 1: \
+ __get_user_asm(__gu_err, __gu_val, ptr, b, "=d"); \
+ break; \
+ case 2: \
+ __get_user_asm(__gu_err, __gu_val, ptr, w, "=r"); \
+ break; \
+ case 4: \
+ __get_user_asm(__gu_err, __gu_val, ptr, l, "=r"); \
+ break; \
+ case 8: \
+ memcpy((void *) &__gu_val, ptr, sizeof (*(ptr))); \
+ break; \
+ default: \
+ __gu_val = 0; \
+ __gu_err = __get_user_bad(); \
+ break; \
+ } \
+ (x) = (typeof(*(ptr))) __gu_val; \
+ __gu_err; \
+})
+#define __get_user(x, ptr) get_user(x, ptr)
+
+extern int __get_user_bad(void);
+
+#define __get_user_asm(err,x,ptr,bwl,reg) \
+ __asm__ ("move" #bwl " %1,%0" \
+ : "=d" (x) \
+ : "m" (*__ptr(ptr)))
+
+static inline unsigned long
+raw_copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+ memcpy(to, (__force const void *)from, n);
+ return 0;
+}
+
+static inline unsigned long
+raw_copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+ memcpy((__force void *)to, from, n);
+ return 0;
+}
+#define INLINE_COPY_FROM_USER
+#define INLINE_COPY_TO_USER
+
+/*
+ * Copy a null terminated string from userspace.
+ */
+
+static inline long
+strncpy_from_user(char *dst, const char *src, long count)
+{
+ char *tmp;
+ strncpy(dst, src, count);
+ for (tmp = dst; *tmp && count > 0; tmp++, count--)
+ ;
+ return(tmp - dst); /* DAVIDM should we count a NUL ? check getname */
+}
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return 0 on exception, a value greater than N if too long
+ */
+static inline long strnlen_user(const char *src, long n)
+{
+ return(strlen(src) + 1); /* DAVIDM make safer */
+}
+
+/*
+ * Zero Userspace
+ */
+
+static inline unsigned long
+__clear_user(void *to, unsigned long n)
+{
+ memset(to, 0, n);
+ return 0;
+}
+
+#define clear_user(to,n) __clear_user(to,n)
+
+#endif /* _M68KNOMMU_UACCESS_H */
diff --git a/arch/m68k/include/asm/ucontext.h b/arch/m68k/include/asm/ucontext.h
new file mode 100644
index 0000000..1523a8e
--- /dev/null
+++ b/arch/m68k/include/asm/ucontext.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_UCONTEXT_H
+#define _M68K_UCONTEXT_H
+
+typedef int greg_t;
+#define NGREG 18
+typedef greg_t gregset_t[NGREG];
+
+typedef struct fpregset {
+ int f_fpcntl[3];
+ int f_fpregs[8*3];
+} fpregset_t;
+
+struct mcontext {
+ int version;
+ gregset_t gregs;
+ fpregset_t fpregs;
+};
+
+#define MCONTEXT_VERSION 2
+
+struct ucontext {
+ unsigned long uc_flags;
+ struct ucontext *uc_link;
+ stack_t uc_stack;
+ struct mcontext uc_mcontext;
+ unsigned long uc_filler[80];
+ sigset_t uc_sigmask; /* mask last for extensibility */
+};
+
+#endif
diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h
new file mode 100644
index 0000000..98c8930
--- /dev/null
+++ b/arch/m68k/include/asm/unaligned.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_UNALIGNED_H
+#define _ASM_M68K_UNALIGNED_H
+
+
+#ifdef CONFIG_CPU_HAS_NO_UNALIGNED
+#include <linux/unaligned/be_struct.h>
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+#define get_unaligned __get_unaligned_be
+#define put_unaligned __put_unaligned_be
+
+#else
+/*
+ * The m68k can do unaligned accesses itself.
+ */
+#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/generic.h>
+
+#define get_unaligned __get_unaligned_be
+#define put_unaligned __put_unaligned_be
+
+#endif
+
+#endif /* _ASM_M68K_UNALIGNED_H */
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
new file mode 100644
index 0000000..30d0d3f
--- /dev/null
+++ b/arch/m68k/include/asm/unistd.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_UNISTD_H_
+#define _ASM_M68K_UNISTD_H_
+
+#include <uapi/asm/unistd.h>
+
+
+#define NR_syscalls 380
+
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_OLD_STAT
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_IPC
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLD_MMAP
+#define __ARCH_WANT_SYS_OLD_SELECT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_FORK
+#define __ARCH_WANT_SYS_VFORK
+
+#endif /* _ASM_M68K_UNISTD_H_ */
diff --git a/arch/m68k/include/asm/user.h b/arch/m68k/include/asm/user.h
new file mode 100644
index 0000000..509d555
--- /dev/null
+++ b/arch/m68k/include/asm/user.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _M68K_USER_H
+#define _M68K_USER_H
+
+/* Core file format: The core file is written in such a way that gdb
+ can understand it and provide useful information to the user (under
+ linux we use the 'trad-core' bfd). There are quite a number of
+ obstacles to being able to view the contents of the floating point
+ registers, and until these are solved you will not be able to view the
+ contents of them. Actually, you can read in the core file and look at
+ the contents of the user struct to find out what the floating point
+ registers contain.
+ The actual file contents are as follows:
+ UPAGE: 1 page consisting of a user struct that tells gdb what is present
+ in the file. Directly after this is a copy of the task_struct, which
+ is currently not used by gdb, but it may come in useful at some point.
+ All of the registers are stored as part of the upage. The upage should
+ always be only one page.
+ DATA: The data area is stored. We use current->end_text to
+ current->brk to pick up all of the user variables, plus any memory
+ that may have been malloced. No attempt is made to determine if a page
+ is demand-zero or if a page is totally unused, we just cover the entire
+ range. All of the addresses are rounded in such a way that an integral
+ number of pages is written.
+ STACK: We need the stack information in order to get a meaningful
+ backtrace. We need to write the data from (esp) to
+ current->start_stack, so we round each of these off in order to be able
+ to write an integer number of pages.
+ The minimum core file size is 3 pages, or 12288 bytes.
+*/
+
+struct user_m68kfp_struct {
+ unsigned long fpregs[8*3]; /* fp0-fp7 registers */
+ unsigned long fpcntl[3]; /* fp control regs */
+};
+
+/* This is the old layout of "struct pt_regs" as of Linux 1.x, and
+ is still the layout used by user (the new pt_regs doesn't have
+ all registers). */
+struct user_regs_struct {
+ long d1,d2,d3,d4,d5,d6,d7;
+ long a0,a1,a2,a3,a4,a5,a6;
+ long d0;
+ long usp;
+ long orig_d0;
+ short stkadj;
+ short sr;
+ long pc;
+ short fmtvec;
+ short __fill;
+};
+
+
+/* When the kernel dumps core, it starts by dumping the user struct -
+ this will be used by gdb to figure out where the data and stack segments
+ are within the file, and what virtual addresses to use. */
+struct user{
+/* We start with the registers, to mimic the way that "memory" is returned
+ from the ptrace(3,...) function. */
+ struct user_regs_struct regs; /* Where the registers are actually stored */
+/* ptrace does not yet supply these. Someday.... */
+ int u_fpvalid; /* True if math co-processor being used. */
+ /* for this mess. Not yet used. */
+ struct user_m68kfp_struct m68kfp; /* Math Co-processor registers. */
+/* The rest of this junk is to help gdb figure out what goes where */
+ unsigned long int u_tsize; /* Text segment size (pages). */
+ unsigned long int u_dsize; /* Data segment size (pages). */
+ unsigned long int u_ssize; /* Stack segment size (pages). */
+ unsigned long start_code; /* Starting virtual address of text. */
+ unsigned long start_stack; /* Starting virtual address of stack area.
+ This is actually the bottom of the stack,
+ the top of the stack is always found in the
+ esp register. */
+ long int signal; /* Signal that caused the core dump. */
+ int reserved; /* No longer used */
+ unsigned long u_ar0; /* Used by gdb to help find the values for */
+ /* the registers. */
+ struct user_m68kfp_struct* u_fpstate; /* Math Co-processor pointer. */
+ unsigned long magic; /* To uniquely identify a core file */
+ char u_comm[32]; /* User command that was responsible */
+};
+#define NBPG 4096
+#define UPAGES 1
+#define HOST_TEXT_START_ADDR (u.start_code)
+#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
+
+#endif
diff --git a/arch/m68k/include/asm/vga.h b/arch/m68k/include/asm/vga.h
new file mode 100644
index 0000000..4742e6b
--- /dev/null
+++ b/arch/m68k/include/asm/vga.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_VGA_H
+#define _ASM_M68K_VGA_H
+
+/*
+ * Some ColdFire platforms do in fact have a PCI bus. So for those we want
+ * to use the real IO access functions, don't fake them out or redirect them
+ * for that case.
+ */
+#ifndef CONFIG_PCI
+
+#include <asm/raw_io.h>
+#include <asm/kmap.h>
+
+/*
+ * FIXME
+ * Ugh, we don't have PCI space, so map readb() and friends to use raw I/O
+ * accessors, which are identical to the z_*() Zorro bus accessors.
+ * This should make cirrusfb work again on Amiga
+ */
+#undef inb_p
+#undef inw_p
+#undef outb_p
+#undef outw
+#undef readb
+#undef writeb
+#undef writew
+#define inb_p(port) 0
+#define inw_p(port) 0
+#define outb_p(port, val) do { } while (0)
+#define outw(port, val) do { } while (0)
+#define readb raw_inb
+#define writeb raw_outb
+#define writew raw_outw
+
+#endif /* CONFIG_PCI */
+#endif /* _ASM_M68K_VGA_H */
diff --git a/arch/m68k/include/asm/virtconvert.h b/arch/m68k/include/asm/virtconvert.h
new file mode 100644
index 0000000..dfe4308
--- /dev/null
+++ b/arch/m68k/include/asm/virtconvert.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __VIRT_CONVERT__
+#define __VIRT_CONVERT__
+
+/*
+ * Macros used for converting between virtual and physical mappings.
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/compiler.h>
+#include <linux/mmzone.h>
+#include <asm/setup.h>
+#include <asm/page.h>
+
+/*
+ * Change virtual addresses to physical addresses and vv.
+ */
+#define virt_to_phys virt_to_phys
+static inline unsigned long virt_to_phys(void *address)
+{
+ return __pa(address);
+}
+
+#define phys_to_virt phys_to_virt
+static inline void *phys_to_virt(unsigned long address)
+{
+ return __va(address);
+}
+
+/* Permanent address of a page. */
+#if defined(CONFIG_MMU) && defined(CONFIG_SINGLE_MEMORY_CHUNK)
+#define page_to_phys(page) \
+ __pa(PAGE_OFFSET + (((page) - pg_data_map[0].node_mem_map) << PAGE_SHIFT))
+#else
+#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
+#endif
+
+/*
+ * IO bus memory addresses are 1:1 with the physical address,
+ */
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
+#endif
+#endif
diff --git a/arch/m68k/include/asm/zorro.h b/arch/m68k/include/asm/zorro.h
new file mode 100644
index 0000000..60fc4b6
--- /dev/null
+++ b/arch/m68k/include/asm/zorro.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_M68K_ZORRO_H
+#define _ASM_M68K_ZORRO_H
+
+#include <asm/raw_io.h>
+#include <asm/kmap.h>
+
+#define z_readb raw_inb
+#define z_readw raw_inw
+#define z_readl raw_inl
+
+#define z_writeb raw_outb
+#define z_writew raw_outw
+#define z_writel raw_outl
+
+#define z_memset_io(a,b,c) memset((void *)(a),(b),(c))
+#define z_memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
+#define z_memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
+
+static inline void __iomem *z_remap_nocache_ser(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+
+static inline void __iomem *z_remap_nocache_nonser(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_NOCACHE_NONSER);
+}
+
+static inline void __iomem *z_remap_writethrough(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
+}
+static inline void __iomem *z_remap_fullcache(unsigned long physaddr,
+ unsigned long size)
+{
+ return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
+}
+
+#define z_unmap iounmap
+#define z_iounmap iounmap
+#define z_ioremap z_remap_nocache_ser
+
+#endif /* _ASM_M68K_ZORRO_H */