Update Linux to v5.10.109
Sourced from [1]
[1] https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.10.109.tar.xz
Change-Id: I19bca9fc6762d4e63bcf3e4cba88bbe560d9c76c
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h
index 030981c..a250a52 100644
--- a/include/dt-bindings/clock/actions,s500-cmu.h
+++ b/include/dt-bindings/clock/actions,s500-cmu.h
@@ -72,7 +72,12 @@
#define CLK_NAND 52
#define CLK_ECC 53
#define CLK_RMII_REF 54
+#define CLK_GPIO 55
-#define CLK_NR_CLKS (CLK_RMII_REF + 1)
+/* system clock (part 2) */
+#define CLK_APB 56
+#define CLK_DMAC 57
+
+#define CLK_NR_CLKS (CLK_DMAC + 1)
#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */
diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h
new file mode 100644
index 0000000..06feca0
--- /dev/null
+++ b/include/dt-bindings/clock/agilex-clock.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+#ifndef __AGILEX_CLOCK_H
+#define __AGILEX_CLOCK_H
+
+/* fixed rate clocks */
+#define AGILEX_OSC1 0
+#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1
+#define AGILEX_CB_INTOSC_LS_CLK 2
+#define AGILEX_L4_SYS_FREE_CLK 3
+#define AGILEX_F2S_FREE_CLK 4
+
+/* PLL clocks */
+#define AGILEX_MAIN_PLL_CLK 5
+#define AGILEX_MAIN_PLL_C0_CLK 6
+#define AGILEX_MAIN_PLL_C1_CLK 7
+#define AGILEX_MAIN_PLL_C2_CLK 8
+#define AGILEX_MAIN_PLL_C3_CLK 9
+#define AGILEX_PERIPH_PLL_CLK 10
+#define AGILEX_PERIPH_PLL_C0_CLK 11
+#define AGILEX_PERIPH_PLL_C1_CLK 12
+#define AGILEX_PERIPH_PLL_C2_CLK 13
+#define AGILEX_PERIPH_PLL_C3_CLK 14
+#define AGILEX_MPU_FREE_CLK 15
+#define AGILEX_MPU_CCU_CLK 16
+#define AGILEX_BOOT_CLK 17
+
+/* fixed factor clocks */
+#define AGILEX_L3_MAIN_FREE_CLK 18
+#define AGILEX_NOC_FREE_CLK 19
+#define AGILEX_S2F_USR0_CLK 20
+#define AGILEX_NOC_CLK 21
+#define AGILEX_EMAC_A_FREE_CLK 22
+#define AGILEX_EMAC_B_FREE_CLK 23
+#define AGILEX_EMAC_PTP_FREE_CLK 24
+#define AGILEX_GPIO_DB_FREE_CLK 25
+#define AGILEX_SDMMC_FREE_CLK 26
+#define AGILEX_S2F_USER0_FREE_CLK 27
+#define AGILEX_S2F_USER1_FREE_CLK 28
+#define AGILEX_PSI_REF_FREE_CLK 29
+
+/* Gate clocks */
+#define AGILEX_MPU_CLK 30
+#define AGILEX_MPU_L2RAM_CLK 31
+#define AGILEX_MPU_PERIPH_CLK 32
+#define AGILEX_L4_MAIN_CLK 33
+#define AGILEX_L4_MP_CLK 34
+#define AGILEX_L4_SP_CLK 35
+#define AGILEX_CS_AT_CLK 36
+#define AGILEX_CS_TRACE_CLK 37
+#define AGILEX_CS_PDBG_CLK 38
+#define AGILEX_CS_TIMER_CLK 39
+#define AGILEX_S2F_USER0_CLK 40
+#define AGILEX_EMAC0_CLK 41
+#define AGILEX_EMAC1_CLK 43
+#define AGILEX_EMAC2_CLK 44
+#define AGILEX_EMAC_PTP_CLK 45
+#define AGILEX_GPIO_DB_CLK 46
+#define AGILEX_NAND_CLK 47
+#define AGILEX_PSI_REF_CLK 48
+#define AGILEX_S2F_USER1_CLK 49
+#define AGILEX_SDMMC_CLK 50
+#define AGILEX_SPI_M_CLK 51
+#define AGILEX_USB_CLK 52
+#define AGILEX_NAND_X_CLK 53
+#define AGILEX_NAND_ECC_CLK 54
+#define AGILEX_NUM_CLKS 55
+
+#endif /* __AGILEX_CLOCK_H */
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index f437386..9ff4f6e 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -39,6 +39,8 @@
#define ASPEED_CLK_BCLK 33
#define ASPEED_CLK_MPLL 34
#define ASPEED_CLK_24M 35
+#define ASPEED_CLK_MAC1RCLK 36
+#define ASPEED_CLK_MAC2RCLK 37
#define ASPEED_RESET_XDMA 0
#define ASPEED_RESET_MCTP 1
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 38074a5..62b9520 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -83,6 +83,10 @@
#define ASPEED_CLK_MAC12 64
#define ASPEED_CLK_MAC34 65
#define ASPEED_CLK_USBPHY_40M 66
+#define ASPEED_CLK_MAC1RCLK 67
+#define ASPEED_CLK_MAC2RCLK 68
+#define ASPEED_CLK_MAC3RCLK 69
+#define ASPEED_CLK_MAC4RCLK 70
/* Only list resets here that are not part of a gate */
#define ASPEED_RESET_ADC 55
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index 38b5554..eba1710 100644
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -12,6 +12,7 @@
#define PMC_TYPE_SYSTEM 1
#define PMC_TYPE_PERIPHERAL 2
#define PMC_TYPE_GCK 3
+#define PMC_TYPE_PROGRAMMABLE 4
#define PMC_SLOW 0
#define PMC_MCK 1
@@ -20,6 +21,9 @@
#define PMC_MCK2 4
#define PMC_I2S0_MUX 5
#define PMC_I2S1_MUX 6
+#define PMC_PLLACK 7
+#define PMC_PLLBCK 8
+#define PMC_AUDIOPLLCK 9
#ifndef AT91_PMC_MOSCS
#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
index 75901c6..f561f5c 100644
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -80,5 +80,15 @@
#define AUD_CLKID_TDM_SCLK_PAD0 160
#define AUD_CLKID_TDM_SCLK_PAD1 161
#define AUD_CLKID_TDM_SCLK_PAD2 162
+#define AUD_CLKID_TOP 163
+#define AUD_CLKID_TORAM 164
+#define AUD_CLKID_EQDRC 165
+#define AUD_CLKID_RESAMPLE_B 166
+#define AUD_CLKID_TOVAD 167
+#define AUD_CLKID_LOCKER 168
+#define AUD_CLKID_SPDIFIN_LB 169
+#define AUD_CLKID_FRDDR_D 170
+#define AUD_CLKID_TODDR_D 171
+#define AUD_CLKID_LOOPBACK_B 172
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/clock/bcm3368-clock.h b/include/dt-bindings/clock/bcm3368-clock.h
new file mode 100644
index 0000000..74a7382
--- /dev/null
+++ b/include/dt-bindings/clock/bcm3368-clock.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM3368_H
+#define __DT_BINDINGS_CLOCK_BCM3368_H
+
+#define BCM3368_CLK_MAC 3
+#define BCM3368_CLK_TC 5
+#define BCM3368_CLK_US_TOP 6
+#define BCM3368_CLK_DS_TOP 7
+#define BCM3368_CLK_ACM 8
+#define BCM3368_CLK_SPI 9
+#define BCM3368_CLK_USBS 10
+#define BCM3368_CLK_BMU 11
+#define BCM3368_CLK_PCM 12
+#define BCM3368_CLK_NTP 13
+#define BCM3368_CLK_ACP_B 14
+#define BCM3368_CLK_ACP_A 15
+#define BCM3368_CLK_EMUSB 17
+#define BCM3368_CLK_ENET0 18
+#define BCM3368_CLK_ENET1 19
+#define BCM3368_CLK_USBSU 20
+#define BCM3368_CLK_EPHY 21
+
+#endif /* __DT_BINDINGS_CLOCK_BCM3368_H */
diff --git a/include/dt-bindings/clock/bcm6318-clock.h b/include/dt-bindings/clock/bcm6318-clock.h
new file mode 100644
index 0000000..c4417f8
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6318-clock.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6318_H
+#define __DT_BINDINGS_CLOCK_BCM6318_H
+
+#define BCM6318_CLK_ADSL_ASB 0
+#define BCM6318_CLK_USB_ASB 1
+#define BCM6318_CLK_MIPS_ASB 2
+#define BCM6318_CLK_PCIE_ASB 3
+#define BCM6318_CLK_PHYMIPS_ASB 4
+#define BCM6318_CLK_ROBOSW_ASB 5
+#define BCM6318_CLK_SAR_ASB 6
+#define BCM6318_CLK_SDR_ASB 7
+#define BCM6318_CLK_SWREG_ASB 8
+#define BCM6318_CLK_PERIPH_ASB 9
+#define BCM6318_CLK_CPUBUS160 10
+#define BCM6318_CLK_ADSL 11
+#define BCM6318_CLK_SAR125 12
+#define BCM6318_CLK_MIPS 13
+#define BCM6318_CLK_PCIE 14
+#define BCM6318_CLK_ROBOSW250 16
+#define BCM6318_CLK_ROBOSW025 17
+#define BCM6318_CLK_SDR 19
+#define BCM6318_CLK_USBD 20
+#define BCM6318_CLK_HSSPI 25
+#define BCM6318_CLK_PCIE25 27
+#define BCM6318_CLK_PHYMIPS 28
+#define BCM6318_CLK_AFE 29
+#define BCM6318_CLK_QPROC 30
+
+#define BCM6318_UCLK_ADSL 0
+#define BCM6318_UCLK_ARB 1
+#define BCM6318_UCLK_MIPS 2
+#define BCM6318_UCLK_PCIE 3
+#define BCM6318_UCLK_PERIPH 4
+#define BCM6318_UCLK_PHYMIPS 5
+#define BCM6318_UCLK_ROBOSW 6
+#define BCM6318_UCLK_SAR 7
+#define BCM6318_UCLK_SDR 8
+#define BCM6318_UCLK_USB 9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */
diff --git a/include/dt-bindings/clock/bcm63268-clock.h b/include/dt-bindings/clock/bcm63268-clock.h
new file mode 100644
index 0000000..da23e69
--- /dev/null
+++ b/include/dt-bindings/clock/bcm63268-clock.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM63268_H
+#define __DT_BINDINGS_CLOCK_BCM63268_H
+
+#define BCM63268_CLK_DIS_GLESS 0
+#define BCM63268_CLK_VDSL_QPROC 1
+#define BCM63268_CLK_VDSL_AFE 2
+#define BCM63268_CLK_VDSL 3
+#define BCM63268_CLK_MIPS 4
+#define BCM63268_CLK_WLAN_OCP 5
+#define BCM63268_CLK_DECT 6
+#define BCM63268_CLK_FAP0 7
+#define BCM63268_CLK_FAP1 8
+#define BCM63268_CLK_SAR 9
+#define BCM63268_CLK_ROBOSW 10
+#define BCM63268_CLK_PCM 11
+#define BCM63268_CLK_USBD 12
+#define BCM63268_CLK_USBH 13
+#define BCM63268_CLK_IPSEC 14
+#define BCM63268_CLK_SPI 15
+#define BCM63268_CLK_HSSPI 16
+#define BCM63268_CLK_PCIE 17
+#define BCM63268_CLK_PHYMIPS 18
+#define BCM63268_CLK_GMAC 19
+#define BCM63268_CLK_NAND 20
+#define BCM63268_CLK_TBUS 27
+#define BCM63268_CLK_ROBOSW250 31
+
+#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */
diff --git a/include/dt-bindings/clock/bcm6328-clock.h b/include/dt-bindings/clock/bcm6328-clock.h
new file mode 100644
index 0000000..1f6a310
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6328-clock.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6328_H
+#define __DT_BINDINGS_CLOCK_BCM6328_H
+
+#define BCM6328_CLK_PHYMIPS 0
+#define BCM6328_CLK_ADSL_QPROC 1
+#define BCM6328_CLK_ADSL_AFE 2
+#define BCM6328_CLK_ADSL 3
+#define BCM6328_CLK_MIPS 4
+#define BCM6328_CLK_SAR 5
+#define BCM6328_CLK_PCM 6
+#define BCM6328_CLK_USBD 7
+#define BCM6328_CLK_USBH 8
+#define BCM6328_CLK_HSSPI 9
+#define BCM6328_CLK_PCIE 10
+#define BCM6328_CLK_ROBOSW 11
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */
diff --git a/include/dt-bindings/clock/bcm6358-clock.h b/include/dt-bindings/clock/bcm6358-clock.h
new file mode 100644
index 0000000..980c9ca
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6358-clock.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6358_H
+#define __DT_BINDINGS_CLOCK_BCM6358_H
+
+#define BCM6358_CLK_ENET 4
+#define BCM6358_CLK_ADSLPHY 5
+#define BCM6358_CLK_PCM 8
+#define BCM6358_CLK_SPI 9
+#define BCM6358_CLK_USBS 10
+#define BCM6358_CLK_SAR 11
+#define BCM6358_CLK_EMUSB 17
+#define BCM6358_CLK_ENET0 18
+#define BCM6358_CLK_ENET1 19
+#define BCM6358_CLK_USBSU 20
+#define BCM6358_CLK_EPHY 21
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */
diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h
new file mode 100644
index 0000000..17655cd
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6362-clock.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6362_H
+#define __DT_BINDINGS_CLOCK_BCM6362_H
+
+#define BCM6362_CLK_ADSL_QPROC 1
+#define BCM6362_CLK_ADSL_AFE 2
+#define BCM6362_CLK_ADSL 3
+#define BCM6362_CLK_MIPS 4
+#define BCM6362_CLK_WLAN_OCP 5
+#define BCM6362_CLK_SWPKT_USB 7
+#define BCM6362_CLK_SWPKT_SAR 8
+#define BCM6362_CLK_SAR 9
+#define BCM6362_CLK_ROBOSW 10
+#define BCM6362_CLK_PCM 11
+#define BCM6362_CLK_USBD 12
+#define BCM6362_CLK_USBH 13
+#define BCM6362_CLK_IPSEC 14
+#define BCM6362_CLK_SPI 15
+#define BCM6362_CLK_HSSPI 16
+#define BCM6362_CLK_PCIE 17
+#define BCM6362_CLK_FAP 18
+#define BCM6362_CLK_PHYMIPS 19
+#define BCM6362_CLK_NAND 20
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */
diff --git a/include/dt-bindings/clock/bcm6368-clock.h b/include/dt-bindings/clock/bcm6368-clock.h
new file mode 100644
index 0000000..f161d53
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6368-clock.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6368_H
+#define __DT_BINDINGS_CLOCK_BCM6368_H
+
+#define BCM6368_CLK_VDSL_QPROC 2
+#define BCM6368_CLK_VDSL_AFE 3
+#define BCM6368_CLK_VDSL_BONDING 4
+#define BCM6368_CLK_VDSL 5
+#define BCM6368_CLK_PHYMIPS 6
+#define BCM6368_CLK_SWPKT_USB 7
+#define BCM6368_CLK_SWPKT_SAR 8
+#define BCM6368_CLK_SPI 9
+#define BCM6368_CLK_USBD 10
+#define BCM6368_CLK_SAR 11
+#define BCM6368_CLK_ROBOSW 12
+#define BCM6368_CLK_UTOPIA 13
+#define BCM6368_CLK_PCM 14
+#define BCM6368_CLK_USBH 15
+#define BCM6368_CLK_DIS_GLESS 16
+#define BCM6368_CLK_NAND 17
+#define BCM6368_CLK_IPSEC 18
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */
diff --git a/include/dt-bindings/clock/bm1880-clock.h b/include/dt-bindings/clock/bm1880-clock.h
new file mode 100644
index 0000000..b467323
--- /dev/null
+++ b/include/dt-bindings/clock/bm1880-clock.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Device Tree binding constants for Bitmain BM1880 SoC
+ *
+ * Copyright (c) 2019 Linaro Ltd.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BM1880_H
+#define __DT_BINDINGS_CLOCK_BM1880_H
+
+#define BM1880_CLK_OSC 0
+#define BM1880_CLK_MPLL 1
+#define BM1880_CLK_SPLL 2
+#define BM1880_CLK_FPLL 3
+#define BM1880_CLK_DDRPLL 4
+#define BM1880_CLK_A53 5
+#define BM1880_CLK_50M_A53 6
+#define BM1880_CLK_AHB_ROM 7
+#define BM1880_CLK_AXI_SRAM 8
+#define BM1880_CLK_DDR_AXI 9
+#define BM1880_CLK_EFUSE 10
+#define BM1880_CLK_APB_EFUSE 11
+#define BM1880_CLK_AXI5_EMMC 12
+#define BM1880_CLK_EMMC 13
+#define BM1880_CLK_100K_EMMC 14
+#define BM1880_CLK_AXI5_SD 15
+#define BM1880_CLK_SD 16
+#define BM1880_CLK_100K_SD 17
+#define BM1880_CLK_500M_ETH0 18
+#define BM1880_CLK_AXI4_ETH0 19
+#define BM1880_CLK_500M_ETH1 20
+#define BM1880_CLK_AXI4_ETH1 21
+#define BM1880_CLK_AXI1_GDMA 22
+#define BM1880_CLK_APB_GPIO 23
+#define BM1880_CLK_APB_GPIO_INTR 24
+#define BM1880_CLK_GPIO_DB 25
+#define BM1880_CLK_AXI1_MINER 26
+#define BM1880_CLK_AHB_SF 27
+#define BM1880_CLK_SDMA_AXI 28
+#define BM1880_CLK_SDMA_AUD 29
+#define BM1880_CLK_APB_I2C 30
+#define BM1880_CLK_APB_WDT 31
+#define BM1880_CLK_APB_JPEG 32
+#define BM1880_CLK_JPEG_AXI 33
+#define BM1880_CLK_AXI5_NF 34
+#define BM1880_CLK_APB_NF 35
+#define BM1880_CLK_NF 36
+#define BM1880_CLK_APB_PWM 37
+#define BM1880_CLK_DIV_0_RV 38
+#define BM1880_CLK_DIV_1_RV 39
+#define BM1880_CLK_MUX_RV 40
+#define BM1880_CLK_RV 41
+#define BM1880_CLK_APB_SPI 42
+#define BM1880_CLK_TPU_AXI 43
+#define BM1880_CLK_DIV_UART_500M 44
+#define BM1880_CLK_UART_500M 45
+#define BM1880_CLK_APB_UART 46
+#define BM1880_CLK_APB_I2S 47
+#define BM1880_CLK_AXI4_USB 48
+#define BM1880_CLK_APB_USB 49
+#define BM1880_CLK_125M_USB 50
+#define BM1880_CLK_33K_USB 51
+#define BM1880_CLK_DIV_12M_USB 52
+#define BM1880_CLK_12M_USB 53
+#define BM1880_CLK_APB_VIDEO 54
+#define BM1880_CLK_VIDEO_AXI 55
+#define BM1880_CLK_VPP_AXI 56
+#define BM1880_CLK_APB_VPP 57
+#define BM1880_CLK_DIV_0_AXI1 58
+#define BM1880_CLK_DIV_1_AXI1 59
+#define BM1880_CLK_AXI1 60
+#define BM1880_CLK_AXI2 61
+#define BM1880_CLK_AXI3 62
+#define BM1880_CLK_AXI4 63
+#define BM1880_CLK_AXI5 64
+#define BM1880_CLK_DIV_0_AXI6 65
+#define BM1880_CLK_DIV_1_AXI6 66
+#define BM1880_CLK_MUX_AXI6 67
+#define BM1880_CLK_AXI6 68
+#define BM1880_NR_CLKS 69
+
+#endif /* __DT_BINDINGS_CLOCK_BM1880_H */
diff --git a/include/dt-bindings/clock/bt1-ccu.h b/include/dt-bindings/clock/bt1-ccu.h
new file mode 100644
index 0000000..5f166d2
--- /dev/null
+++ b/include/dt-bindings/clock/bt1-ccu.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+ *
+ * Baikal-T1 CCU clock indices
+ */
+#ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H
+#define __DT_BINDINGS_CLOCK_BT1_CCU_H
+
+#define CCU_CPU_PLL 0
+#define CCU_SATA_PLL 1
+#define CCU_DDR_PLL 2
+#define CCU_PCIE_PLL 3
+#define CCU_ETH_PLL 4
+
+#define CCU_AXI_MAIN_CLK 0
+#define CCU_AXI_DDR_CLK 1
+#define CCU_AXI_SATA_CLK 2
+#define CCU_AXI_GMAC0_CLK 3
+#define CCU_AXI_GMAC1_CLK 4
+#define CCU_AXI_XGMAC_CLK 5
+#define CCU_AXI_PCIE_M_CLK 6
+#define CCU_AXI_PCIE_S_CLK 7
+#define CCU_AXI_USB_CLK 8
+#define CCU_AXI_HWA_CLK 9
+#define CCU_AXI_SRAM_CLK 10
+
+#define CCU_SYS_SATA_REF_CLK 0
+#define CCU_SYS_APB_CLK 1
+#define CCU_SYS_GMAC0_TX_CLK 2
+#define CCU_SYS_GMAC0_PTP_CLK 3
+#define CCU_SYS_GMAC1_TX_CLK 4
+#define CCU_SYS_GMAC1_PTP_CLK 5
+#define CCU_SYS_XGMAC_REF_CLK 6
+#define CCU_SYS_XGMAC_PTP_CLK 7
+#define CCU_SYS_USB_CLK 8
+#define CCU_SYS_PVT_CLK 9
+#define CCU_SYS_HWA_CLK 10
+#define CCU_SYS_UART_CLK 11
+#define CCU_SYS_I2C1_CLK 12
+#define CCU_SYS_I2C2_CLK 13
+#define CCU_SYS_GPIO_CLK 14
+#define CCU_SYS_TIMER0_CLK 15
+#define CCU_SYS_TIMER1_CLK 16
+#define CCU_SYS_TIMER2_CLK 17
+#define CCU_SYS_WDT_CLK 18
+
+#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */
diff --git a/include/dt-bindings/clock/dm814.h b/include/dt-bindings/clock/dm814.h
index f0f04e0..33b8826 100644
--- a/include/dt-bindings/clock/dm814.h
+++ b/include/dt-bindings/clock/dm814.h
@@ -34,4 +34,9 @@
#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220)
#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224)
+/* alwon_ethernet clocks */
+#define DM814_ETHERNET_CLKCTRL_OFFSET 0x1d4
+#define DM814_ETHERNET_CLKCTRL_INDEX(offset) ((offset) - DM814_ETHERNET_CLKCTRL_OFFSET)
+#define DM814_ETHERNET_CPGMAC0_CLKCTRL DM814_ETHERNET_CLKCTRL_INDEX(0x1d4)
+
#endif
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h
index 72f2e84..5ec4137 100644
--- a/include/dt-bindings/clock/dra7.h
+++ b/include/dt-bindings/clock/dra7.h
@@ -29,6 +29,16 @@
#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
+/* vip clocks */
+#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+
+/* vpe clocks */
+#define DRA7_VPE_CLKCTRL_OFFSET 0x60
+#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
+#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
+
/* coreaon clocks */
#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
@@ -78,6 +88,9 @@
#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+/* gpu clocks */
+#define DRA7_GPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+
/* l3init clocks */
#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
@@ -192,6 +205,16 @@
/* rtc clocks */
#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44)
+/* vip clocks */
+#define DRA7_CAM_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_CAM_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_CAM_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+
+/* vpe clocks */
+#define DRA7_VPE_CLKCTRL_OFFSET 0x60
+#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
+#define DRA7_VPE_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64)
+
/* coreaon clocks */
#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
@@ -309,6 +332,7 @@
#define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
#define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
#define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
+#define DRA7_L4SEC_SHAM2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1f8)
/* l4per2 clocks */
#define DRA7_L4PER2_CLKCTRL_OFFSET 0xc
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index bc8a3c5..e259cc0 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -172,8 +172,10 @@
#define CLK_MOUT_GPLL 1025
#define CLK_MOUT_ACLK200_DISP1_SUB 1026
#define CLK_MOUT_ACLK300_DISP1_SUB 1027
+#define CLK_MOUT_APLL 1028
+#define CLK_MOUT_MPLL 1029
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 1028
+#define CLK_NR_CLKS 1030
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 02d5ac4..9fffc6c 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -230,6 +230,12 @@
#define CLK_MOUT_USER_MAU_EPLL 659
#define CLK_MOUT_SCLK_SPLL 660
#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
+#define CLK_MOUT_SW_ACLK_G3D 662
+#define CLK_MOUT_APLL 663
+#define CLK_MOUT_MSPLL_CPU 664
+#define CLK_MOUT_KPLL 665
+#define CLK_MOUT_MSPLL_KFC 666
+
/* divider clocks */
#define CLK_DOUT_PIXEL 768
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 0837c1a..40d4994 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -143,5 +143,9 @@
#define CLKID_CPU1_CLK 253
#define CLKID_CPU2_CLK 254
#define CLKID_CPU3_CLK 255
+#define CLKID_SPICC0_SCLK 258
+#define CLKID_SPICC1_SCLK 261
+#define CLKID_NNA_AXI_CLK 264
+#define CLKID_NNA_CORE_CLK 267
#endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index db0763e..4073eb7 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -146,5 +146,6 @@
#define CLKID_CTS_VDAC 201
#define CLKID_HDMI_TX 202
#define CLKID_HDMI 205
+#define CLKID_ACODEC 206
#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index e6a670e..1d4c0df 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -451,5 +451,6 @@
#define IMX7D_SNVS_CLK 442
#define IMX7D_CAAM_CLK 443
#define IMX7D_KPP_ROOT_CLK 444
-#define IMX7D_CLK_END 445
+#define IMX7D_PXP_CLK 445
+#define IMX7D_CLK_END 446
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
index 6f66f90..b58370d 100644
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -49,6 +49,7 @@
#define IMX7ULP_CLK_NIC1_DIV 36
#define IMX7ULP_CLK_NIC1_BUS_DIV 37
#define IMX7ULP_CLK_NIC1_EXT_DIV 38
+/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
#define IMX7ULP_CLK_MIPI_PLL 39
#define IMX7ULP_CLK_SIRC 40
#define IMX7ULP_CLK_SOSC_BUS_CLK 41
@@ -57,7 +58,10 @@
#define IMX7ULP_CLK_HSRUN_SYS_SEL 44
#define IMX7ULP_CLK_HSRUN_CORE_DIV 45
-#define IMX7ULP_CLK_SCG1_END 46
+#define IMX7ULP_CLK_CORE 46
+#define IMX7ULP_CLK_HSRUN_CORE 47
+
+#define IMX7ULP_CLK_SCG1_END 48
/* PCC2 */
#define IMX7ULP_CLK_DMA1 0
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index 07e6c68..e63a553 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -248,6 +248,32 @@
#define IMX8MM_CLK_SNVS_ROOT 228
#define IMX8MM_CLK_GIC 229
-#define IMX8MM_CLK_END 230
+#define IMX8MM_SYS_PLL1_40M_CG 230
+#define IMX8MM_SYS_PLL1_80M_CG 231
+#define IMX8MM_SYS_PLL1_100M_CG 232
+#define IMX8MM_SYS_PLL1_133M_CG 233
+#define IMX8MM_SYS_PLL1_160M_CG 234
+#define IMX8MM_SYS_PLL1_200M_CG 235
+#define IMX8MM_SYS_PLL1_266M_CG 236
+#define IMX8MM_SYS_PLL1_400M_CG 237
+#define IMX8MM_SYS_PLL2_50M_CG 238
+#define IMX8MM_SYS_PLL2_100M_CG 239
+#define IMX8MM_SYS_PLL2_125M_CG 240
+#define IMX8MM_SYS_PLL2_166M_CG 241
+#define IMX8MM_SYS_PLL2_200M_CG 242
+#define IMX8MM_SYS_PLL2_250M_CG 243
+#define IMX8MM_SYS_PLL2_333M_CG 244
+#define IMX8MM_SYS_PLL2_500M_CG 245
+
+#define IMX8MM_CLK_M4_CORE 246
+#define IMX8MM_CLK_VPU_CORE 247
+#define IMX8MM_CLK_GPU3D_CORE 248
+#define IMX8MM_CLK_GPU2D_CORE 249
+
+#define IMX8MM_CLK_CLKO2 250
+
+#define IMX8MM_CLK_A53_CORE 251
+
+#define IMX8MM_CLK_END 252
#endif
diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
index 0c7c750..621ea0e 100644
--- a/include/dt-bindings/clock/imx8mn-clock.h
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -211,6 +211,29 @@
#define IMX8MN_CLK_GPU_CORE_ROOT 193
#define IMX8MN_CLK_GIC 194
-#define IMX8MN_CLK_END 195
+#define IMX8MN_SYS_PLL1_40M_CG 195
+#define IMX8MN_SYS_PLL1_80M_CG 196
+#define IMX8MN_SYS_PLL1_100M_CG 197
+#define IMX8MN_SYS_PLL1_133M_CG 198
+#define IMX8MN_SYS_PLL1_160M_CG 199
+#define IMX8MN_SYS_PLL1_200M_CG 200
+#define IMX8MN_SYS_PLL1_266M_CG 201
+#define IMX8MN_SYS_PLL1_400M_CG 202
+#define IMX8MN_SYS_PLL2_50M_CG 203
+#define IMX8MN_SYS_PLL2_100M_CG 204
+#define IMX8MN_SYS_PLL2_125M_CG 205
+#define IMX8MN_SYS_PLL2_166M_CG 206
+#define IMX8MN_SYS_PLL2_200M_CG 207
+#define IMX8MN_SYS_PLL2_250M_CG 208
+#define IMX8MN_SYS_PLL2_333M_CG 209
+#define IMX8MN_SYS_PLL2_500M_CG 210
+
+#define IMX8MN_CLK_SNVS_ROOT 211
+#define IMX8MN_CLK_GPU_CORE 212
+#define IMX8MN_CLK_GPU_SHADER 213
+
+#define IMX8MN_CLK_A53_CORE 214
+
+#define IMX8MN_CLK_END 215
#endif
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
new file mode 100644
index 0000000..e8d68fb
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -0,0 +1,389 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MP_H
+#define __DT_BINDINGS_CLOCK_IMX8MP_H
+
+#define IMX8MP_CLK_DUMMY 0
+#define IMX8MP_CLK_32K 1
+#define IMX8MP_CLK_24M 2
+#define IMX8MP_OSC_HDMI_CLK 3
+#define IMX8MP_CLK_EXT1 4
+#define IMX8MP_CLK_EXT2 5
+#define IMX8MP_CLK_EXT3 6
+#define IMX8MP_CLK_EXT4 7
+#define IMX8MP_AUDIO_PLL1_REF_SEL 8
+#define IMX8MP_AUDIO_PLL2_REF_SEL 9
+#define IMX8MP_VIDEO_PLL1_REF_SEL 10
+#define IMX8MP_DRAM_PLL_REF_SEL 11
+#define IMX8MP_GPU_PLL_REF_SEL 12
+#define IMX8MP_VPU_PLL_REF_SEL 13
+#define IMX8MP_ARM_PLL_REF_SEL 14
+#define IMX8MP_SYS_PLL1_REF_SEL 15
+#define IMX8MP_SYS_PLL2_REF_SEL 16
+#define IMX8MP_SYS_PLL3_REF_SEL 17
+#define IMX8MP_AUDIO_PLL1 18
+#define IMX8MP_AUDIO_PLL2 19
+#define IMX8MP_VIDEO_PLL1 20
+#define IMX8MP_DRAM_PLL 21
+#define IMX8MP_GPU_PLL 22
+#define IMX8MP_VPU_PLL 23
+#define IMX8MP_ARM_PLL 24
+#define IMX8MP_SYS_PLL1 25
+#define IMX8MP_SYS_PLL2 26
+#define IMX8MP_SYS_PLL3 27
+#define IMX8MP_AUDIO_PLL1_BYPASS 28
+#define IMX8MP_AUDIO_PLL2_BYPASS 29
+#define IMX8MP_VIDEO_PLL1_BYPASS 30
+#define IMX8MP_DRAM_PLL_BYPASS 31
+#define IMX8MP_GPU_PLL_BYPASS 32
+#define IMX8MP_VPU_PLL_BYPASS 33
+#define IMX8MP_ARM_PLL_BYPASS 34
+#define IMX8MP_SYS_PLL1_BYPASS 35
+#define IMX8MP_SYS_PLL2_BYPASS 36
+#define IMX8MP_SYS_PLL3_BYPASS 37
+#define IMX8MP_AUDIO_PLL1_OUT 38
+#define IMX8MP_AUDIO_PLL2_OUT 39
+#define IMX8MP_VIDEO_PLL1_OUT 40
+#define IMX8MP_DRAM_PLL_OUT 41
+#define IMX8MP_GPU_PLL_OUT 42
+#define IMX8MP_VPU_PLL_OUT 43
+#define IMX8MP_ARM_PLL_OUT 44
+#define IMX8MP_SYS_PLL1_OUT 45
+#define IMX8MP_SYS_PLL2_OUT 46
+#define IMX8MP_SYS_PLL3_OUT 47
+#define IMX8MP_SYS_PLL1_40M 48
+#define IMX8MP_SYS_PLL1_80M 49
+#define IMX8MP_SYS_PLL1_100M 50
+#define IMX8MP_SYS_PLL1_133M 51
+#define IMX8MP_SYS_PLL1_160M 52
+#define IMX8MP_SYS_PLL1_200M 53
+#define IMX8MP_SYS_PLL1_266M 54
+#define IMX8MP_SYS_PLL1_400M 55
+#define IMX8MP_SYS_PLL1_800M 56
+#define IMX8MP_SYS_PLL2_50M 57
+#define IMX8MP_SYS_PLL2_100M 58
+#define IMX8MP_SYS_PLL2_125M 59
+#define IMX8MP_SYS_PLL2_166M 60
+#define IMX8MP_SYS_PLL2_200M 61
+#define IMX8MP_SYS_PLL2_250M 62
+#define IMX8MP_SYS_PLL2_333M 63
+#define IMX8MP_SYS_PLL2_500M 64
+#define IMX8MP_SYS_PLL2_1000M 65
+#define IMX8MP_CLK_A53_SRC 66
+#define IMX8MP_CLK_M7_SRC 67
+#define IMX8MP_CLK_ML_SRC 68
+#define IMX8MP_CLK_GPU3D_CORE_SRC 69
+#define IMX8MP_CLK_GPU3D_SHADER_SRC 70
+#define IMX8MP_CLK_GPU2D_SRC 71
+#define IMX8MP_CLK_AUDIO_AXI_SRC 72
+#define IMX8MP_CLK_HSIO_AXI_SRC 73
+#define IMX8MP_CLK_MEDIA_ISP_SRC 74
+#define IMX8MP_CLK_A53_CG 75
+#define IMX8MP_CLK_M4_CG 76
+#define IMX8MP_CLK_ML_CG 77
+#define IMX8MP_CLK_GPU3D_CORE_CG 78
+#define IMX8MP_CLK_GPU3D_SHADER_CG 79
+#define IMX8MP_CLK_GPU2D_CG 80
+#define IMX8MP_CLK_AUDIO_AXI_CG 81
+#define IMX8MP_CLK_HSIO_AXI_CG 82
+#define IMX8MP_CLK_MEDIA_ISP_CG 83
+#define IMX8MP_CLK_A53_DIV 84
+#define IMX8MP_CLK_M7_DIV 85
+#define IMX8MP_CLK_ML_DIV 86
+#define IMX8MP_CLK_GPU3D_CORE_DIV 87
+#define IMX8MP_CLK_GPU3D_SHADER_DIV 88
+#define IMX8MP_CLK_GPU2D_DIV 89
+#define IMX8MP_CLK_AUDIO_AXI_DIV 90
+#define IMX8MP_CLK_HSIO_AXI_DIV 91
+#define IMX8MP_CLK_MEDIA_ISP_DIV 92
+#define IMX8MP_CLK_MAIN_AXI 93
+#define IMX8MP_CLK_ENET_AXI 94
+#define IMX8MP_CLK_NAND_USDHC_BUS 95
+#define IMX8MP_CLK_VPU_BUS 96
+#define IMX8MP_CLK_MEDIA_AXI 97
+#define IMX8MP_CLK_MEDIA_APB 98
+#define IMX8MP_CLK_HDMI_APB 99
+#define IMX8MP_CLK_HDMI_AXI 100
+#define IMX8MP_CLK_GPU_AXI 101
+#define IMX8MP_CLK_GPU_AHB 102
+#define IMX8MP_CLK_NOC 103
+#define IMX8MP_CLK_NOC_IO 104
+#define IMX8MP_CLK_ML_AXI 105
+#define IMX8MP_CLK_ML_AHB 106
+#define IMX8MP_CLK_AHB 107
+#define IMX8MP_CLK_AUDIO_AHB 108
+#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109
+#define IMX8MP_CLK_IPG_ROOT 110
+#define IMX8MP_CLK_IPG_AUDIO_ROOT 111
+#define IMX8MP_CLK_DRAM_ALT 112
+#define IMX8MP_CLK_DRAM_APB 113
+#define IMX8MP_CLK_VPU_G1 114
+#define IMX8MP_CLK_VPU_G2 115
+#define IMX8MP_CLK_CAN1 116
+#define IMX8MP_CLK_CAN2 117
+#define IMX8MP_CLK_MEMREPAIR 118
+#define IMX8MP_CLK_PCIE_PHY 119
+#define IMX8MP_CLK_PCIE_AUX 120
+#define IMX8MP_CLK_I2C5 121
+#define IMX8MP_CLK_I2C6 122
+#define IMX8MP_CLK_SAI1 123
+#define IMX8MP_CLK_SAI2 124
+#define IMX8MP_CLK_SAI3 125
+#define IMX8MP_CLK_SAI4 126
+#define IMX8MP_CLK_SAI5 127
+#define IMX8MP_CLK_SAI6 128
+#define IMX8MP_CLK_ENET_QOS 129
+#define IMX8MP_CLK_ENET_QOS_TIMER 130
+#define IMX8MP_CLK_ENET_REF 131
+#define IMX8MP_CLK_ENET_TIMER 132
+#define IMX8MP_CLK_ENET_PHY_REF 133
+#define IMX8MP_CLK_NAND 134
+#define IMX8MP_CLK_QSPI 135
+#define IMX8MP_CLK_USDHC1 136
+#define IMX8MP_CLK_USDHC2 137
+#define IMX8MP_CLK_I2C1 138
+#define IMX8MP_CLK_I2C2 139
+#define IMX8MP_CLK_I2C3 140
+#define IMX8MP_CLK_I2C4 141
+#define IMX8MP_CLK_UART1 142
+#define IMX8MP_CLK_UART2 143
+#define IMX8MP_CLK_UART3 144
+#define IMX8MP_CLK_UART4 145
+#define IMX8MP_CLK_USB_CORE_REF 146
+#define IMX8MP_CLK_USB_PHY_REF 147
+#define IMX8MP_CLK_GIC 148
+#define IMX8MP_CLK_ECSPI1 149
+#define IMX8MP_CLK_ECSPI2 150
+#define IMX8MP_CLK_PWM1 151
+#define IMX8MP_CLK_PWM2 152
+#define IMX8MP_CLK_PWM3 153
+#define IMX8MP_CLK_PWM4 154
+#define IMX8MP_CLK_GPT1 155
+#define IMX8MP_CLK_GPT2 156
+#define IMX8MP_CLK_GPT3 157
+#define IMX8MP_CLK_GPT4 158
+#define IMX8MP_CLK_GPT5 159
+#define IMX8MP_CLK_GPT6 160
+#define IMX8MP_CLK_TRACE 161
+#define IMX8MP_CLK_WDOG 162
+#define IMX8MP_CLK_WRCLK 163
+#define IMX8MP_CLK_IPP_DO_CLKO1 164
+#define IMX8MP_CLK_IPP_DO_CLKO2 165
+#define IMX8MP_CLK_HDMI_FDCC_TST 166
+#define IMX8MP_CLK_HDMI_24M 167
+#define IMX8MP_CLK_HDMI_REF_266M 168
+#define IMX8MP_CLK_USDHC3 169
+#define IMX8MP_CLK_MEDIA_CAM1_PIX 170
+#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171
+#define IMX8MP_CLK_MEDIA_DISP1_PIX 172
+#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
+#define IMX8MP_CLK_MEDIA_LDB 174
+#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
+#define IMX8MP_CLK_PCIE2_CTRL 176
+#define IMX8MP_CLK_PCIE2_PHY 177
+#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
+#define IMX8MP_CLK_ECSPI3 179
+#define IMX8MP_CLK_PDM 180
+#define IMX8MP_CLK_VPU_VC8000E 181
+#define IMX8MP_CLK_SAI7 182
+#define IMX8MP_CLK_GPC_ROOT 183
+#define IMX8MP_CLK_ANAMIX_ROOT 184
+#define IMX8MP_CLK_CPU_ROOT 185
+#define IMX8MP_CLK_CSU_ROOT 186
+#define IMX8MP_CLK_DEBUG_ROOT 187
+#define IMX8MP_CLK_DRAM1_ROOT 188
+#define IMX8MP_CLK_ECSPI1_ROOT 189
+#define IMX8MP_CLK_ECSPI2_ROOT 190
+#define IMX8MP_CLK_ECSPI3_ROOT 191
+#define IMX8MP_CLK_ENET1_ROOT 192
+#define IMX8MP_CLK_GPIO1_ROOT 193
+#define IMX8MP_CLK_GPIO2_ROOT 194
+#define IMX8MP_CLK_GPIO3_ROOT 195
+#define IMX8MP_CLK_GPIO4_ROOT 196
+#define IMX8MP_CLK_GPIO5_ROOT 197
+#define IMX8MP_CLK_GPT1_ROOT 198
+#define IMX8MP_CLK_GPT2_ROOT 199
+#define IMX8MP_CLK_GPT3_ROOT 200
+#define IMX8MP_CLK_GPT4_ROOT 201
+#define IMX8MP_CLK_GPT5_ROOT 202
+#define IMX8MP_CLK_GPT6_ROOT 203
+#define IMX8MP_CLK_HS_ROOT 204
+#define IMX8MP_CLK_I2C1_ROOT 205
+#define IMX8MP_CLK_I2C2_ROOT 206
+#define IMX8MP_CLK_I2C3_ROOT 207
+#define IMX8MP_CLK_I2C4_ROOT 208
+#define IMX8MP_CLK_IOMUX_ROOT 209
+#define IMX8MP_CLK_IPMUX1_ROOT 210
+#define IMX8MP_CLK_IPMUX2_ROOT 211
+#define IMX8MP_CLK_IPMUX3_ROOT 212
+#define IMX8MP_CLK_MU_ROOT 213
+#define IMX8MP_CLK_OCOTP_ROOT 214
+#define IMX8MP_CLK_OCRAM_ROOT 215
+#define IMX8MP_CLK_OCRAM_S_ROOT 216
+#define IMX8MP_CLK_PCIE_ROOT 217
+#define IMX8MP_CLK_PERFMON1_ROOT 218
+#define IMX8MP_CLK_PERFMON2_ROOT 219
+#define IMX8MP_CLK_PWM1_ROOT 220
+#define IMX8MP_CLK_PWM2_ROOT 221
+#define IMX8MP_CLK_PWM3_ROOT 222
+#define IMX8MP_CLK_PWM4_ROOT 223
+#define IMX8MP_CLK_QOS_ROOT 224
+#define IMX8MP_CLK_QOS_ENET_ROOT 225
+#define IMX8MP_CLK_QSPI_ROOT 226
+#define IMX8MP_CLK_NAND_ROOT 227
+#define IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228
+#define IMX8MP_CLK_RDC_ROOT 229
+#define IMX8MP_CLK_ROM_ROOT 230
+#define IMX8MP_CLK_I2C5_ROOT 231
+#define IMX8MP_CLK_I2C6_ROOT 232
+#define IMX8MP_CLK_CAN1_ROOT 233
+#define IMX8MP_CLK_CAN2_ROOT 234
+#define IMX8MP_CLK_SCTR_ROOT 235
+#define IMX8MP_CLK_SDMA1_ROOT 236
+#define IMX8MP_CLK_ENET_QOS_ROOT 237
+#define IMX8MP_CLK_SEC_DEBUG_ROOT 238
+#define IMX8MP_CLK_SEMA1_ROOT 239
+#define IMX8MP_CLK_SEMA2_ROOT 240
+#define IMX8MP_CLK_IRQ_STEER_ROOT 241
+#define IMX8MP_CLK_SIM_ENET_ROOT 242
+#define IMX8MP_CLK_SIM_M_ROOT 243
+#define IMX8MP_CLK_SIM_MAIN_ROOT 244
+#define IMX8MP_CLK_SIM_S_ROOT 245
+#define IMX8MP_CLK_SIM_WAKEUP_ROOT 246
+#define IMX8MP_CLK_GPU2D_ROOT 247
+#define IMX8MP_CLK_GPU3D_ROOT 248
+#define IMX8MP_CLK_SNVS_ROOT 249
+#define IMX8MP_CLK_TRACE_ROOT 250
+#define IMX8MP_CLK_UART1_ROOT 251
+#define IMX8MP_CLK_UART2_ROOT 252
+#define IMX8MP_CLK_UART3_ROOT 253
+#define IMX8MP_CLK_UART4_ROOT 254
+#define IMX8MP_CLK_USB_ROOT 255
+#define IMX8MP_CLK_USB_PHY_ROOT 256
+#define IMX8MP_CLK_USDHC1_ROOT 257
+#define IMX8MP_CLK_USDHC2_ROOT 258
+#define IMX8MP_CLK_WDOG1_ROOT 259
+#define IMX8MP_CLK_WDOG2_ROOT 260
+#define IMX8MP_CLK_WDOG3_ROOT 261
+#define IMX8MP_CLK_VPU_G1_ROOT 262
+#define IMX8MP_CLK_GPU_ROOT 263
+#define IMX8MP_CLK_NOC_WRAPPER_ROOT 264
+#define IMX8MP_CLK_VPU_VC8KE_ROOT 265
+#define IMX8MP_CLK_VPU_G2_ROOT 266
+#define IMX8MP_CLK_NPU_ROOT 267
+#define IMX8MP_CLK_HSIO_ROOT 268
+#define IMX8MP_CLK_MEDIA_APB_ROOT 269
+#define IMX8MP_CLK_MEDIA_AXI_ROOT 270
+#define IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 271
+#define IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 272
+#define IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 273
+#define IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 274
+#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 275
+#define IMX8MP_CLK_MEDIA_ISP_ROOT 276
+#define IMX8MP_CLK_USDHC3_ROOT 277
+#define IMX8MP_CLK_HDMI_ROOT 278
+#define IMX8MP_CLK_XTAL_ROOT 279
+#define IMX8MP_CLK_PLL_ROOT 280
+#define IMX8MP_CLK_TSENSOR_ROOT 281
+#define IMX8MP_CLK_VPU_ROOT 282
+#define IMX8MP_CLK_MRPR_ROOT 283
+#define IMX8MP_CLK_AUDIO_ROOT 284
+#define IMX8MP_CLK_DRAM_ALT_ROOT 285
+#define IMX8MP_CLK_DRAM_CORE 286
+#define IMX8MP_CLK_ARM 287
+#define IMX8MP_CLK_A53_CORE 288
+
+#define IMX8MP_SYS_PLL1_40M_CG 289
+#define IMX8MP_SYS_PLL1_80M_CG 290
+#define IMX8MP_SYS_PLL1_100M_CG 291
+#define IMX8MP_SYS_PLL1_133M_CG 292
+#define IMX8MP_SYS_PLL1_160M_CG 293
+#define IMX8MP_SYS_PLL1_200M_CG 294
+#define IMX8MP_SYS_PLL1_266M_CG 295
+#define IMX8MP_SYS_PLL1_400M_CG 296
+#define IMX8MP_SYS_PLL2_50M_CG 297
+#define IMX8MP_SYS_PLL2_100M_CG 298
+#define IMX8MP_SYS_PLL2_125M_CG 299
+#define IMX8MP_SYS_PLL2_166M_CG 300
+#define IMX8MP_SYS_PLL2_200M_CG 301
+#define IMX8MP_SYS_PLL2_250M_CG 302
+#define IMX8MP_SYS_PLL2_333M_CG 303
+#define IMX8MP_SYS_PLL2_500M_CG 304
+
+#define IMX8MP_CLK_M7_CORE 305
+#define IMX8MP_CLK_ML_CORE 306
+#define IMX8MP_CLK_GPU3D_CORE 307
+#define IMX8MP_CLK_GPU3D_SHADER_CORE 308
+#define IMX8MP_CLK_GPU2D_CORE 309
+#define IMX8MP_CLK_AUDIO_AXI 310
+#define IMX8MP_CLK_HSIO_AXI 311
+#define IMX8MP_CLK_MEDIA_ISP 312
+
+#define IMX8MP_CLK_END 313
+
+#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
+#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
+#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2
+#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3
+#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4
+#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5
+#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6
+#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7
+#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8
+#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9
+#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10
+#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11
+#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12
+#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13
+#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14
+#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15
+#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16
+#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17
+#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18
+#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19
+#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20
+#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21
+#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22
+#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23
+#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24
+#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25
+#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26
+#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27
+#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28
+#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29
+#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30
+#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31
+#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32
+#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33
+#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34
+#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35
+#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36
+#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37
+#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38
+#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39
+#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40
+#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41
+#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42
+#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43
+#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44
+#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45
+#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46
+#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47
+#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48
+#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49
+#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50
+#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51
+#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52
+#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53
+#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54
+#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55
+#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56
+#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57
+#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58
+
+#define IMX8MP_CLK_AUDIOMIX_END 59
+
+#endif
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 6546367..da62c9f 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -403,5 +403,15 @@
#define IMX8MQ_CLK_SNVS_ROOT 264
#define IMX8MQ_CLK_GIC 265
-#define IMX8MQ_CLK_END 266
+#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266
+
+#define IMX8MQ_CLK_GPU_CORE 285
+#define IMX8MQ_CLK_GPU_SHADER 286
+#define IMX8MQ_CLK_M4_CORE 287
+#define IMX8MQ_CLK_VPU_CORE 288
+
+#define IMX8MQ_CLK_A53_CORE 289
+
+#define IMX8MQ_CLK_END 290
+
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/include/dt-bindings/clock/ingenic,sysost.h b/include/dt-bindings/clock/ingenic,sysost.h
new file mode 100644
index 0000000..9ac88e9
--- /dev/null
+++ b/include/dt-bindings/clock/ingenic,sysost.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,tcu DT binding.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_INGENIC_OST_H__
+#define __DT_BINDINGS_CLOCK_INGENIC_OST_H__
+
+#define OST_CLK_PERCPU_TIMER 0
+#define OST_CLK_GLOBAL_TIMER 1
+
+#endif /* __DT_BINDINGS_CLOCK_INGENIC_OST_H__ */
diff --git a/include/dt-bindings/clock/intel,lgm-clk.h b/include/dt-bindings/clock/intel,lgm-clk.h
new file mode 100644
index 0000000..92f5be6
--- /dev/null
+++ b/include/dt-bindings/clock/intel,lgm-clk.h
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2020 Intel Corporation.
+ * Lei Chuanhua <Chuanhua.lei@intel.com>
+ * Zhu Yixin <Yixin.zhu@intel.com>
+ */
+#ifndef __INTEL_LGM_CLK_H
+#define __INTEL_LGM_CLK_H
+
+/* PLL clocks */
+#define LGM_CLK_OSC 1
+#define LGM_CLK_PLLPP 2
+#define LGM_CLK_PLL2 3
+#define LGM_CLK_PLL0CZ 4
+#define LGM_CLK_PLL0B 5
+#define LGM_CLK_PLL1 6
+#define LGM_CLK_LJPLL3 7
+#define LGM_CLK_LJPLL4 8
+#define LGM_CLK_PLL0CM0 9
+#define LGM_CLK_PLL0CM1 10
+
+/* clocks from PLLs */
+
+/* ROPLL clocks */
+#define LGM_CLK_PP_HW 15
+#define LGM_CLK_PP_UC 16
+#define LGM_CLK_PP_FXD 17
+#define LGM_CLK_PP_TBM 18
+
+/* PLL2 clocks */
+#define LGM_CLK_DDR 20
+
+/* PLL0CZ */
+#define LGM_CLK_CM 25
+#define LGM_CLK_IC 26
+#define LGM_CLK_SDXC3 27
+
+/* PLL0B */
+#define LGM_CLK_NGI 30
+#define LGM_CLK_NOC4 31
+#define LGM_CLK_SW 32
+#define LGM_CLK_QSPI 33
+#define LGM_CLK_CQEM LGM_CLK_SW
+#define LGM_CLK_EMMC5 LGM_CLK_NOC4
+
+/* PLL1 */
+#define LGM_CLK_CT 35
+#define LGM_CLK_DSP 36
+#define LGM_CLK_VIF 37
+
+/* LJPLL3 */
+#define LGM_CLK_CML 40
+#define LGM_CLK_SERDES 41
+#define LGM_CLK_POOL 42
+#define LGM_CLK_PTP 43
+
+/* LJPLL4 */
+#define LGM_CLK_PCIE 45
+#define LGM_CLK_SATA LGM_CLK_PCIE
+
+/* PLL0CM0 */
+#define LGM_CLK_CPU0 50
+
+/* PLL0CM1 */
+#define LGM_CLK_CPU1 55
+
+/* Miscellaneous clocks */
+#define LGM_CLK_EMMC4 60
+#define LGM_CLK_SDXC2 61
+#define LGM_CLK_EMMC 62
+#define LGM_CLK_SDXC 63
+#define LGM_CLK_SLIC 64
+#define LGM_CLK_DCL 65
+#define LGM_CLK_DOCSIS 66
+#define LGM_CLK_PCM 67
+#define LGM_CLK_DDR_PHY 68
+#define LGM_CLK_PONDEF 69
+#define LGM_CLK_PL25M 70
+#define LGM_CLK_PL10M 71
+#define LGM_CLK_PL1544K 72
+#define LGM_CLK_PL2048K 73
+#define LGM_CLK_PL8K 74
+#define LGM_CLK_PON_NTR 75
+#define LGM_CLK_SYNC0 76
+#define LGM_CLK_SYNC1 77
+#define LGM_CLK_PROGDIV 78
+#define LGM_CLK_OD0 79
+#define LGM_CLK_OD1 80
+#define LGM_CLK_CBPHY0 81
+#define LGM_CLK_CBPHY1 82
+#define LGM_CLK_CBPHY2 83
+#define LGM_CLK_CBPHY3 84
+
+/* Gate clocks */
+/* Gate CLK0 */
+#define LGM_GCLK_C55 100
+#define LGM_GCLK_QSPI 101
+#define LGM_GCLK_EIP197 102
+#define LGM_GCLK_VAULT 103
+#define LGM_GCLK_TOE 104
+#define LGM_GCLK_SDXC 105
+#define LGM_GCLK_EMMC 106
+#define LGM_GCLK_SPI_DBG 107
+#define LGM_GCLK_DMA3 108
+
+/* Gate CLK1 */
+#define LGM_GCLK_DMA0 120
+#define LGM_GCLK_LEDC0 121
+#define LGM_GCLK_LEDC1 122
+#define LGM_GCLK_I2S0 123
+#define LGM_GCLK_I2S1 124
+#define LGM_GCLK_EBU 125
+#define LGM_GCLK_PWM 126
+#define LGM_GCLK_I2C0 127
+#define LGM_GCLK_I2C1 128
+#define LGM_GCLK_I2C2 129
+#define LGM_GCLK_I2C3 130
+#define LGM_GCLK_SSC0 131
+#define LGM_GCLK_SSC1 132
+#define LGM_GCLK_SSC2 133
+#define LGM_GCLK_SSC3 134
+#define LGM_GCLK_GPTC0 135
+#define LGM_GCLK_GPTC1 136
+#define LGM_GCLK_GPTC2 137
+#define LGM_GCLK_GPTC3 138
+#define LGM_GCLK_ASC0 139
+#define LGM_GCLK_ASC1 140
+#define LGM_GCLK_ASC2 141
+#define LGM_GCLK_ASC3 142
+#define LGM_GCLK_PCM0 143
+#define LGM_GCLK_PCM1 144
+#define LGM_GCLK_PCM2 145
+
+/* Gate CLK2 */
+#define LGM_GCLK_PCIE10 150
+#define LGM_GCLK_PCIE11 151
+#define LGM_GCLK_PCIE30 152
+#define LGM_GCLK_PCIE31 153
+#define LGM_GCLK_PCIE20 154
+#define LGM_GCLK_PCIE21 155
+#define LGM_GCLK_PCIE40 156
+#define LGM_GCLK_PCIE41 157
+#define LGM_GCLK_XPCS0 158
+#define LGM_GCLK_XPCS1 159
+#define LGM_GCLK_XPCS2 160
+#define LGM_GCLK_XPCS3 161
+#define LGM_GCLK_SATA0 162
+#define LGM_GCLK_SATA1 163
+#define LGM_GCLK_SATA2 164
+#define LGM_GCLK_SATA3 165
+
+/* Gate CLK3 */
+#define LGM_GCLK_ARCEM4 170
+#define LGM_GCLK_IDMAR1 171
+#define LGM_GCLK_IDMAT0 172
+#define LGM_GCLK_IDMAT1 173
+#define LGM_GCLK_IDMAT2 174
+#define LGM_GCLK_PPV4 175
+#define LGM_GCLK_GSWIPO 176
+#define LGM_GCLK_CQEM 177
+#define LGM_GCLK_XPCS5 178
+#define LGM_GCLK_USB1 179
+#define LGM_GCLK_USB2 180
+
+#endif /* __INTEL_LGM_CLK_H */
diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h
index 1859ce5..85cf8eb 100644
--- a/include/dt-bindings/clock/jz4780-cgu.h
+++ b/include/dt-bindings/clock/jz4780-cgu.h
@@ -12,78 +12,80 @@
#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
-#define JZ4780_CLK_EXCLK 0
-#define JZ4780_CLK_RTCLK 1
-#define JZ4780_CLK_APLL 2
-#define JZ4780_CLK_MPLL 3
-#define JZ4780_CLK_EPLL 4
-#define JZ4780_CLK_VPLL 5
-#define JZ4780_CLK_OTGPHY 6
-#define JZ4780_CLK_SCLKA 7
-#define JZ4780_CLK_CPUMUX 8
-#define JZ4780_CLK_CPU 9
-#define JZ4780_CLK_L2CACHE 10
-#define JZ4780_CLK_AHB0 11
-#define JZ4780_CLK_AHB2PMUX 12
-#define JZ4780_CLK_AHB2 13
-#define JZ4780_CLK_PCLK 14
-#define JZ4780_CLK_DDR 15
-#define JZ4780_CLK_VPU 16
-#define JZ4780_CLK_I2SPLL 17
-#define JZ4780_CLK_I2S 18
+#define JZ4780_CLK_EXCLK 0
+#define JZ4780_CLK_RTCLK 1
+#define JZ4780_CLK_APLL 2
+#define JZ4780_CLK_MPLL 3
+#define JZ4780_CLK_EPLL 4
+#define JZ4780_CLK_VPLL 5
+#define JZ4780_CLK_OTGPHY 6
+#define JZ4780_CLK_SCLKA 7
+#define JZ4780_CLK_CPUMUX 8
+#define JZ4780_CLK_CPU 9
+#define JZ4780_CLK_L2CACHE 10
+#define JZ4780_CLK_AHB0 11
+#define JZ4780_CLK_AHB2PMUX 12
+#define JZ4780_CLK_AHB2 13
+#define JZ4780_CLK_PCLK 14
+#define JZ4780_CLK_DDR 15
+#define JZ4780_CLK_VPU 16
+#define JZ4780_CLK_I2SPLL 17
+#define JZ4780_CLK_I2S 18
#define JZ4780_CLK_LCD0PIXCLK 19
#define JZ4780_CLK_LCD1PIXCLK 20
-#define JZ4780_CLK_MSCMUX 21
-#define JZ4780_CLK_MSC0 22
-#define JZ4780_CLK_MSC1 23
-#define JZ4780_CLK_MSC2 24
-#define JZ4780_CLK_UHC 25
-#define JZ4780_CLK_SSIPLL 26
-#define JZ4780_CLK_SSI 27
-#define JZ4780_CLK_CIMMCLK 28
-#define JZ4780_CLK_PCMPLL 29
-#define JZ4780_CLK_PCM 30
-#define JZ4780_CLK_GPU 31
-#define JZ4780_CLK_HDMI 32
-#define JZ4780_CLK_BCH 33
-#define JZ4780_CLK_NEMC 34
-#define JZ4780_CLK_OTG0 35
-#define JZ4780_CLK_SSI0 36
-#define JZ4780_CLK_SMB0 37
-#define JZ4780_CLK_SMB1 38
-#define JZ4780_CLK_SCC 39
-#define JZ4780_CLK_AIC 40
-#define JZ4780_CLK_TSSI0 41
-#define JZ4780_CLK_OWI 42
-#define JZ4780_CLK_KBC 43
-#define JZ4780_CLK_SADC 44
-#define JZ4780_CLK_UART0 45
-#define JZ4780_CLK_UART1 46
-#define JZ4780_CLK_UART2 47
-#define JZ4780_CLK_UART3 48
-#define JZ4780_CLK_SSI1 49
-#define JZ4780_CLK_SSI2 50
-#define JZ4780_CLK_PDMA 51
-#define JZ4780_CLK_GPS 52
-#define JZ4780_CLK_MAC 53
-#define JZ4780_CLK_SMB2 54
-#define JZ4780_CLK_CIM 55
-#define JZ4780_CLK_LCD 56
-#define JZ4780_CLK_TVE 57
-#define JZ4780_CLK_IPU 58
-#define JZ4780_CLK_DDR0 59
-#define JZ4780_CLK_DDR1 60
-#define JZ4780_CLK_SMB3 61
-#define JZ4780_CLK_TSSI1 62
-#define JZ4780_CLK_COMPRESS 63
-#define JZ4780_CLK_AIC1 64
-#define JZ4780_CLK_GPVLC 65
-#define JZ4780_CLK_OTG1 66
-#define JZ4780_CLK_UART4 67
-#define JZ4780_CLK_AHBMON 68
-#define JZ4780_CLK_SMB4 69
-#define JZ4780_CLK_DES 70
-#define JZ4780_CLK_X2D 71
-#define JZ4780_CLK_CORE1 72
+#define JZ4780_CLK_MSCMUX 21
+#define JZ4780_CLK_MSC0 22
+#define JZ4780_CLK_MSC1 23
+#define JZ4780_CLK_MSC2 24
+#define JZ4780_CLK_UHC 25
+#define JZ4780_CLK_SSIPLL 26
+#define JZ4780_CLK_SSI 27
+#define JZ4780_CLK_CIMMCLK 28
+#define JZ4780_CLK_PCMPLL 29
+#define JZ4780_CLK_PCM 30
+#define JZ4780_CLK_GPU 31
+#define JZ4780_CLK_HDMI 32
+#define JZ4780_CLK_BCH 33
+#define JZ4780_CLK_NEMC 34
+#define JZ4780_CLK_OTG0 35
+#define JZ4780_CLK_SSI0 36
+#define JZ4780_CLK_SMB0 37
+#define JZ4780_CLK_SMB1 38
+#define JZ4780_CLK_SCC 39
+#define JZ4780_CLK_AIC 40
+#define JZ4780_CLK_TSSI0 41
+#define JZ4780_CLK_OWI 42
+#define JZ4780_CLK_KBC 43
+#define JZ4780_CLK_SADC 44
+#define JZ4780_CLK_UART0 45
+#define JZ4780_CLK_UART1 46
+#define JZ4780_CLK_UART2 47
+#define JZ4780_CLK_UART3 48
+#define JZ4780_CLK_SSI1 49
+#define JZ4780_CLK_SSI2 50
+#define JZ4780_CLK_PDMA 51
+#define JZ4780_CLK_GPS 52
+#define JZ4780_CLK_MAC 53
+#define JZ4780_CLK_SMB2 54
+#define JZ4780_CLK_CIM 55
+#define JZ4780_CLK_LCD 56
+#define JZ4780_CLK_TVE 57
+#define JZ4780_CLK_IPU 58
+#define JZ4780_CLK_DDR0 59
+#define JZ4780_CLK_DDR1 60
+#define JZ4780_CLK_SMB3 61
+#define JZ4780_CLK_TSSI1 62
+#define JZ4780_CLK_COMPRESS 63
+#define JZ4780_CLK_AIC1 64
+#define JZ4780_CLK_GPVLC 65
+#define JZ4780_CLK_OTG1 66
+#define JZ4780_CLK_UART4 67
+#define JZ4780_CLK_AHBMON 68
+#define JZ4780_CLK_SMB4 69
+#define JZ4780_CLK_DES 70
+#define JZ4780_CLK_X2D 71
+#define JZ4780_CLK_CORE1 72
+#define JZ4780_CLK_EXCLK_DIV512 73
+#define JZ4780_CLK_RTC 74
#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
diff --git a/include/dt-bindings/clock/k210-clk.h b/include/dt-bindings/clock/k210-clk.h
new file mode 100644
index 0000000..5a2fd64
--- /dev/null
+++ b/include/dt-bindings/clock/k210-clk.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ */
+#ifndef K210_CLK_H
+#define K210_CLK_H
+
+/*
+ * Arbitrary identifiers for clocks.
+ * The structure is: in0 -> pll0 -> aclk -> cpu
+ *
+ * Since we use the hardware defaults for now, set all these to the same clock.
+ */
+#define K210_CLK_PLL0 0
+#define K210_CLK_PLL1 0
+#define K210_CLK_ACLK 0
+#define K210_CLK_CPU 0
+
+#endif /* K210_CLK_H */
diff --git a/include/dt-bindings/clock/marvell,mmp2-audio.h b/include/dt-bindings/clock/marvell,mmp2-audio.h
new file mode 100644
index 0000000..2066477
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,mmp2-audio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */
+#ifndef __DT_BINDINGS_CLOCK_MARVELL_MMP2_AUDIO_H
+#define __DT_BINDINGS_CLOCK_MARVELL_MMP2_AUDIO_H
+
+#define MMP2_CLK_AUDIO_SYSCLK 0
+#define MMP2_CLK_AUDIO_SSPA0 1
+#define MMP2_CLK_AUDIO_SSPA1 2
+
+#define MMP2_CLK_AUDIO_NR_CLKS 3
+#endif
diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h
index e785c6e..87f5ad5 100644
--- a/include/dt-bindings/clock/marvell,mmp2.h
+++ b/include/dt-bindings/clock/marvell,mmp2.h
@@ -26,6 +26,11 @@
#define MMP2_CLK_VCTCXO_4 25
#define MMP2_CLK_UART_PLL 26
#define MMP2_CLK_USB_PLL 27
+#define MMP3_CLK_PLL1_P 28
+#define MMP3_CLK_PLL2_P 29
+#define MMP3_CLK_PLL3 30
+#define MMP2_CLK_I2S0 31
+#define MMP2_CLK_I2S1 32
/* apb periphrals */
#define MMP2_CLK_TWSI0 60
@@ -50,6 +55,10 @@
#define MMP2_CLK_SSP2 79
#define MMP2_CLK_SSP3 80
#define MMP2_CLK_TIMER 81
+#define MMP2_CLK_THERMAL0 82
+#define MMP3_CLK_THERMAL1 83
+#define MMP3_CLK_THERMAL2 84
+#define MMP3_CLK_THERMAL3 85
/* axi periphrals */
#define MMP2_CLK_SDH0 101
@@ -72,6 +81,15 @@
#define MMP2_CLK_CCIC1_PHY 118
#define MMP2_CLK_CCIC1_SPHY 119
#define MMP2_CLK_DISP0_LCDC 120
+#define MMP2_CLK_USBHSIC0 121
+#define MMP2_CLK_USBHSIC1 122
+#define MMP2_CLK_GPU_BUS 123
+#define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS
+#define MMP2_CLK_GPU_3D 124
+#define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D
+#define MMP3_CLK_GPU_2D 125
+#define MMP3_CLK_SDH4 126
+#define MMP2_CLK_AUDIO 127
#define MMP2_NR_CLKS 200
#endif
diff --git a/include/dt-bindings/clock/meson8-ddr-clkc.h b/include/dt-bindings/clock/meson8-ddr-clkc.h
new file mode 100644
index 0000000..a8e0fa2
--- /dev/null
+++ b/include/dt-bindings/clock/meson8-ddr-clkc.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#define DDR_CLKID_DDR_PLL_DCO 0
+#define DDR_CLKID_DDR_PLL 1
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 68862aa..4c5965a 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -107,6 +107,7 @@
#define CLKID_PERIPH 126
#define CLKID_AXI 128
#define CLKID_L2_DRAM 130
+#define CLKID_HDMI_SYS 174
#define CLKID_VPU 190
#define CLKID_VDEC_1 196
#define CLKID_VDEC_HCODEC 199
diff --git a/include/dt-bindings/clock/microchip,sparx5.h b/include/dt-bindings/clock/microchip,sparx5.h
new file mode 100644
index 0000000..4b04dab
--- /dev/null
+++ b/include/dt-bindings/clock/microchip,sparx5.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019 Microchip Inc.
+ *
+ * Author: Lars Povlsen <lars.povlsen@microchip.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SPARX5_H
+#define _DT_BINDINGS_CLK_SPARX5_H
+
+#define CLK_ID_CORE 0
+#define CLK_ID_DDR 1
+#define CLK_ID_CPU2 2
+#define CLK_ID_ARM2 3
+#define CLK_ID_AUX1 4
+#define CLK_ID_AUX2 5
+#define CLK_ID_AUX3 6
+#define CLK_ID_AUX4 7
+#define CLK_ID_SYNCE 8
+
+#define N_CLOCKS 9
+
+#endif
diff --git a/include/dt-bindings/clock/mt6765-clk.h b/include/dt-bindings/clock/mt6765-clk.h
new file mode 100644
index 0000000..eb97e56
--- /dev/null
+++ b/include/dt-bindings/clock/mt6765-clk.h
@@ -0,0 +1,313 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _DT_BINDINGS_CLK_MT6765_H
+#define _DT_BINDINGS_CLK_MT6765_H
+
+/* FIX Clks */
+#define CLK_TOP_CLK26M 0
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_L 0
+#define CLK_APMIXED_ARMPLL 1
+#define CLK_APMIXED_CCIPLL 2
+#define CLK_APMIXED_MAINPLL 3
+#define CLK_APMIXED_MFGPLL 4
+#define CLK_APMIXED_MMPLL 5
+#define CLK_APMIXED_UNIV2PLL 6
+#define CLK_APMIXED_MSDCPLL 7
+#define CLK_APMIXED_APLL1 8
+#define CLK_APMIXED_MPLL 9
+#define CLK_APMIXED_ULPOSC1 10
+#define CLK_APMIXED_ULPOSC2 11
+#define CLK_APMIXED_SSUSB26M 12
+#define CLK_APMIXED_APPLL26M 13
+#define CLK_APMIXED_MIPIC0_26M 14
+#define CLK_APMIXED_MDPLLGP26M 15
+#define CLK_APMIXED_MMSYS_F26M 16
+#define CLK_APMIXED_UFS26M 17
+#define CLK_APMIXED_MIPIC1_26M 18
+#define CLK_APMIXED_MEMPLL26M 19
+#define CLK_APMIXED_CLKSQ_LVPLL_26M 20
+#define CLK_APMIXED_MIPID0_26M 21
+#define CLK_APMIXED_NR_CLK 22
+
+/* TOPCKGEN */
+#define CLK_TOP_SYSPLL 0
+#define CLK_TOP_SYSPLL_D2 1
+#define CLK_TOP_SYSPLL1_D2 2
+#define CLK_TOP_SYSPLL1_D4 3
+#define CLK_TOP_SYSPLL1_D8 4
+#define CLK_TOP_SYSPLL1_D16 5
+#define CLK_TOP_SYSPLL_D3 6
+#define CLK_TOP_SYSPLL2_D2 7
+#define CLK_TOP_SYSPLL2_D4 8
+#define CLK_TOP_SYSPLL2_D8 9
+#define CLK_TOP_SYSPLL_D5 10
+#define CLK_TOP_SYSPLL3_D2 11
+#define CLK_TOP_SYSPLL3_D4 12
+#define CLK_TOP_SYSPLL_D7 13
+#define CLK_TOP_SYSPLL4_D2 14
+#define CLK_TOP_SYSPLL4_D4 15
+#define CLK_TOP_USB20_192M 16
+#define CLK_TOP_USB20_192M_D4 17
+#define CLK_TOP_USB20_192M_D8 18
+#define CLK_TOP_USB20_192M_D16 19
+#define CLK_TOP_USB20_192M_D32 20
+#define CLK_TOP_UNIVPLL 21
+#define CLK_TOP_UNIVPLL_D2 22
+#define CLK_TOP_UNIVPLL1_D2 23
+#define CLK_TOP_UNIVPLL1_D4 24
+#define CLK_TOP_UNIVPLL_D3 25
+#define CLK_TOP_UNIVPLL2_D2 26
+#define CLK_TOP_UNIVPLL2_D4 27
+#define CLK_TOP_UNIVPLL2_D8 28
+#define CLK_TOP_UNIVPLL2_D32 29
+#define CLK_TOP_UNIVPLL_D5 30
+#define CLK_TOP_UNIVPLL3_D2 31
+#define CLK_TOP_UNIVPLL3_D4 32
+#define CLK_TOP_MMPLL 33
+#define CLK_TOP_MMPLL_D2 34
+#define CLK_TOP_MPLL 35
+#define CLK_TOP_DA_MPLL_104M_DIV 36
+#define CLK_TOP_DA_MPLL_52M_DIV 37
+#define CLK_TOP_MFGPLL 38
+#define CLK_TOP_MSDCPLL 39
+#define CLK_TOP_MSDCPLL_D2 40
+#define CLK_TOP_APLL1 41
+#define CLK_TOP_APLL1_D2 42
+#define CLK_TOP_APLL1_D4 43
+#define CLK_TOP_APLL1_D8 44
+#define CLK_TOP_ULPOSC1 45
+#define CLK_TOP_ULPOSC1_D2 46
+#define CLK_TOP_ULPOSC1_D4 47
+#define CLK_TOP_ULPOSC1_D8 48
+#define CLK_TOP_ULPOSC1_D16 49
+#define CLK_TOP_ULPOSC1_D32 50
+#define CLK_TOP_DMPLL 51
+#define CLK_TOP_F_FRTC 52
+#define CLK_TOP_F_F26M 53
+#define CLK_TOP_AXI 54
+#define CLK_TOP_MM 55
+#define CLK_TOP_SCP 56
+#define CLK_TOP_MFG 57
+#define CLK_TOP_F_FUART 58
+#define CLK_TOP_SPI 59
+#define CLK_TOP_MSDC50_0 60
+#define CLK_TOP_MSDC30_1 61
+#define CLK_TOP_AUDIO 62
+#define CLK_TOP_AUD_1 63
+#define CLK_TOP_AUD_ENGEN1 64
+#define CLK_TOP_F_FDISP_PWM 65
+#define CLK_TOP_SSPM 66
+#define CLK_TOP_DXCC 67
+#define CLK_TOP_I2C 68
+#define CLK_TOP_F_FPWM 69
+#define CLK_TOP_F_FSENINF 70
+#define CLK_TOP_AES_FDE 71
+#define CLK_TOP_F_BIST2FPC 72
+#define CLK_TOP_ARMPLL_DIVIDER_PLL0 73
+#define CLK_TOP_ARMPLL_DIVIDER_PLL1 74
+#define CLK_TOP_ARMPLL_DIVIDER_PLL2 75
+#define CLK_TOP_DA_USB20_48M_DIV 76
+#define CLK_TOP_DA_UNIV_48M_DIV 77
+#define CLK_TOP_APLL12_DIV0 78
+#define CLK_TOP_APLL12_DIV1 79
+#define CLK_TOP_APLL12_DIV2 80
+#define CLK_TOP_APLL12_DIV3 81
+#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82
+#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83
+#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84
+#define CLK_TOP_FMEM_OCC_DRC_EN 85
+#define CLK_TOP_USB20_48M_EN 86
+#define CLK_TOP_UNIVPLL_48M_EN 87
+#define CLK_TOP_MPLL_104M_EN 88
+#define CLK_TOP_MPLL_52M_EN 89
+#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90
+#define CLK_TOP_F_BIST2FPC_EN 91
+#define CLK_TOP_MD_32K 92
+#define CLK_TOP_MD_26M 93
+#define CLK_TOP_MD2_32K 94
+#define CLK_TOP_MD2_26M 95
+#define CLK_TOP_AXI_SEL 96
+#define CLK_TOP_MEM_SEL 97
+#define CLK_TOP_MM_SEL 98
+#define CLK_TOP_SCP_SEL 99
+#define CLK_TOP_MFG_SEL 100
+#define CLK_TOP_ATB_SEL 101
+#define CLK_TOP_CAMTG_SEL 102
+#define CLK_TOP_CAMTG1_SEL 103
+#define CLK_TOP_CAMTG2_SEL 104
+#define CLK_TOP_CAMTG3_SEL 105
+#define CLK_TOP_UART_SEL 106
+#define CLK_TOP_SPI_SEL 107
+#define CLK_TOP_MSDC50_0_HCLK_SEL 108
+#define CLK_TOP_MSDC50_0_SEL 109
+#define CLK_TOP_MSDC30_1_SEL 110
+#define CLK_TOP_AUDIO_SEL 111
+#define CLK_TOP_AUD_INTBUS_SEL 112
+#define CLK_TOP_AUD_1_SEL 113
+#define CLK_TOP_AUD_ENGEN1_SEL 114
+#define CLK_TOP_DISP_PWM_SEL 115
+#define CLK_TOP_SSPM_SEL 116
+#define CLK_TOP_DXCC_SEL 117
+#define CLK_TOP_USB_TOP_SEL 118
+#define CLK_TOP_SPM_SEL 119
+#define CLK_TOP_I2C_SEL 120
+#define CLK_TOP_PWM_SEL 121
+#define CLK_TOP_SENINF_SEL 122
+#define CLK_TOP_AES_FDE_SEL 123
+#define CLK_TOP_PWRAP_ULPOSC_SEL 124
+#define CLK_TOP_CAMTM_SEL 125
+#define CLK_TOP_NR_CLK 126
+
+/* INFRACFG */
+#define CLK_IFR_ICUSB 0
+#define CLK_IFR_GCE 1
+#define CLK_IFR_THERM 2
+#define CLK_IFR_I2C_AP 3
+#define CLK_IFR_I2C_CCU 4
+#define CLK_IFR_I2C_SSPM 5
+#define CLK_IFR_I2C_RSV 6
+#define CLK_IFR_PWM_HCLK 7
+#define CLK_IFR_PWM1 8
+#define CLK_IFR_PWM2 9
+#define CLK_IFR_PWM3 10
+#define CLK_IFR_PWM4 11
+#define CLK_IFR_PWM5 12
+#define CLK_IFR_PWM 13
+#define CLK_IFR_UART0 14
+#define CLK_IFR_UART1 15
+#define CLK_IFR_GCE_26M 16
+#define CLK_IFR_CQ_DMA_FPC 17
+#define CLK_IFR_BTIF 18
+#define CLK_IFR_SPI0 19
+#define CLK_IFR_MSDC0 20
+#define CLK_IFR_MSDC1 21
+#define CLK_IFR_TRNG 22
+#define CLK_IFR_AUXADC 23
+#define CLK_IFR_CCIF1_AP 24
+#define CLK_IFR_CCIF1_MD 25
+#define CLK_IFR_AUXADC_MD 26
+#define CLK_IFR_AP_DMA 27
+#define CLK_IFR_DEVICE_APC 28
+#define CLK_IFR_CCIF_AP 29
+#define CLK_IFR_AUDIO 30
+#define CLK_IFR_CCIF_MD 31
+#define CLK_IFR_RG_PWM_FBCLK6 32
+#define CLK_IFR_DISP_PWM 33
+#define CLK_IFR_CLDMA_BCLK 34
+#define CLK_IFR_AUDIO_26M_BCLK 35
+#define CLK_IFR_SPI1 36
+#define CLK_IFR_I2C4 37
+#define CLK_IFR_SPI2 38
+#define CLK_IFR_SPI3 39
+#define CLK_IFR_I2C5 40
+#define CLK_IFR_I2C5_ARBITER 41
+#define CLK_IFR_I2C5_IMM 42
+#define CLK_IFR_I2C1_ARBITER 43
+#define CLK_IFR_I2C1_IMM 44
+#define CLK_IFR_I2C2_ARBITER 45
+#define CLK_IFR_I2C2_IMM 46
+#define CLK_IFR_SPI4 47
+#define CLK_IFR_SPI5 48
+#define CLK_IFR_CQ_DMA 49
+#define CLK_IFR_FAES_FDE 50
+#define CLK_IFR_MSDC0_SELF 51
+#define CLK_IFR_MSDC1_SELF 52
+#define CLK_IFR_I2C6 53
+#define CLK_IFR_AP_MSDC0 54
+#define CLK_IFR_MD_MSDC0 55
+#define CLK_IFR_MSDC0_SRC 56
+#define CLK_IFR_MSDC1_SRC 57
+#define CLK_IFR_AES_TOP0_BCLK 58
+#define CLK_IFR_MCU_PM_BCLK 59
+#define CLK_IFR_CCIF2_AP 60
+#define CLK_IFR_CCIF2_MD 61
+#define CLK_IFR_CCIF3_AP 62
+#define CLK_IFR_CCIF3_MD 63
+#define CLK_IFR_NR_CLK 64
+
+/* AUDIO */
+#define CLK_AUDIO_AFE 0
+#define CLK_AUDIO_22M 1
+#define CLK_AUDIO_APLL_TUNER 2
+#define CLK_AUDIO_ADC 3
+#define CLK_AUDIO_DAC 4
+#define CLK_AUDIO_DAC_PREDIS 5
+#define CLK_AUDIO_TML 6
+#define CLK_AUDIO_I2S1_BCLK 7
+#define CLK_AUDIO_I2S2_BCLK 8
+#define CLK_AUDIO_I2S3_BCLK 9
+#define CLK_AUDIO_I2S4_BCLK 10
+#define CLK_AUDIO_NR_CLK 11
+
+/* MIPI_RX_ANA_CSI0A */
+
+#define CLK_MIPI0A_CSR_CSI_EN_0A 0
+#define CLK_MIPI0A_NR_CLK 1
+
+/* MMSYS_CONFIG */
+
+#define CLK_MM_MDP_RDMA0 0
+#define CLK_MM_MDP_CCORR0 1
+#define CLK_MM_MDP_RSZ0 2
+#define CLK_MM_MDP_RSZ1 3
+#define CLK_MM_MDP_TDSHP0 4
+#define CLK_MM_MDP_WROT0 5
+#define CLK_MM_MDP_WDMA0 6
+#define CLK_MM_DISP_OVL0 7
+#define CLK_MM_DISP_OVL0_2L 8
+#define CLK_MM_DISP_RSZ0 9
+#define CLK_MM_DISP_RDMA0 10
+#define CLK_MM_DISP_WDMA0 11
+#define CLK_MM_DISP_COLOR0 12
+#define CLK_MM_DISP_CCORR0 13
+#define CLK_MM_DISP_AAL0 14
+#define CLK_MM_DISP_GAMMA0 15
+#define CLK_MM_DISP_DITHER0 16
+#define CLK_MM_DSI0 17
+#define CLK_MM_FAKE_ENG 18
+#define CLK_MM_SMI_COMMON 19
+#define CLK_MM_SMI_LARB0 20
+#define CLK_MM_SMI_COMM0 21
+#define CLK_MM_SMI_COMM1 22
+#define CLK_MM_CAM_MDP 23
+#define CLK_MM_SMI_IMG 24
+#define CLK_MM_SMI_CAM 25
+#define CLK_MM_IMG_DL_RELAY 26
+#define CLK_MM_IMG_DL_ASYNC_TOP 27
+#define CLK_MM_DIG_DSI 28
+#define CLK_MM_F26M_HRTWT 29
+#define CLK_MM_NR_CLK 30
+
+/* IMGSYS */
+
+#define CLK_IMG_LARB2 0
+#define CLK_IMG_DIP 1
+#define CLK_IMG_FDVT 2
+#define CLK_IMG_DPE 3
+#define CLK_IMG_RSC 4
+#define CLK_IMG_NR_CLK 5
+
+/* VENCSYS */
+
+#define CLK_VENC_SET0_LARB 0
+#define CLK_VENC_SET1_VENC 1
+#define CLK_VENC_SET2_JPGENC 2
+#define CLK_VENC_SET3_VDEC 3
+#define CLK_VENC_NR_CLK 4
+
+/* CAMSYS */
+
+#define CLK_CAM_LARB3 0
+#define CLK_CAM_DFP_VAD 1
+#define CLK_CAM 2
+#define CLK_CAMTG 3
+#define CLK_CAM_SENINF 4
+#define CLK_CAMSV0 5
+#define CLK_CAMSV1 6
+#define CLK_CAMSV2 7
+#define CLK_CAM_CCU 8
+#define CLK_CAM_NR_CLK 9
+
+#endif /* _DT_BINDINGS_CLK_MT6765_H */
diff --git a/include/dt-bindings/clock/mt8167-clk.h b/include/dt-bindings/clock/mt8167-clk.h
new file mode 100644
index 0000000..a96158e
--- /dev/null
+++ b/include/dt-bindings/clock/mt8167-clk.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2020 BayLibre, SAS.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ * Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8167_H
+#define _DT_BINDINGS_CLK_MT8167_H
+
+/* MT8167 is based on MT8516 */
+#include <dt-bindings/clock/mt8516-clk.h>
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0)
+#define CLK_APMIXED_LVDSPLL (CLK_APMIXED_NR_CLK + 1)
+#define CLK_APMIXED_HDMI_REF (CLK_APMIXED_NR_CLK + 2)
+#define MT8167_CLK_APMIXED_NR_CLK (CLK_APMIXED_NR_CLK + 3)
+
+/* TOPCKGEN */
+
+#define CLK_TOP_DSI0_LNTC_DSICK (CLK_TOP_NR_CLK + 0)
+#define CLK_TOP_VPLL_DPIX (CLK_TOP_NR_CLK + 1)
+#define CLK_TOP_LVDSTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 2)
+#define CLK_TOP_HDMTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 3)
+#define CLK_TOP_LVDSPLL (CLK_TOP_NR_CLK + 4)
+#define CLK_TOP_LVDSPLL_D2 (CLK_TOP_NR_CLK + 5)
+#define CLK_TOP_LVDSPLL_D4 (CLK_TOP_NR_CLK + 6)
+#define CLK_TOP_LVDSPLL_D8 (CLK_TOP_NR_CLK + 7)
+#define CLK_TOP_MIPI_26M (CLK_TOP_NR_CLK + 8)
+#define CLK_TOP_TVDPLL (CLK_TOP_NR_CLK + 9)
+#define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10)
+#define CLK_TOP_TVDPLL_D4 (CLK_TOP_NR_CLK + 11)
+#define CLK_TOP_TVDPLL_D8 (CLK_TOP_NR_CLK + 12)
+#define CLK_TOP_TVDPLL_D16 (CLK_TOP_NR_CLK + 13)
+#define CLK_TOP_PWM_MM (CLK_TOP_NR_CLK + 14)
+#define CLK_TOP_CAM_MM (CLK_TOP_NR_CLK + 15)
+#define CLK_TOP_MFG_MM (CLK_TOP_NR_CLK + 16)
+#define CLK_TOP_SPM_52M (CLK_TOP_NR_CLK + 17)
+#define CLK_TOP_MIPI_26M_DBG (CLK_TOP_NR_CLK + 18)
+#define CLK_TOP_SCAM_MM (CLK_TOP_NR_CLK + 19)
+#define CLK_TOP_SMI_MM (CLK_TOP_NR_CLK + 20)
+#define CLK_TOP_26M_HDMI_SIFM (CLK_TOP_NR_CLK + 21)
+#define CLK_TOP_26M_CEC (CLK_TOP_NR_CLK + 22)
+#define CLK_TOP_32K_CEC (CLK_TOP_NR_CLK + 23)
+#define CLK_TOP_GCPU_B (CLK_TOP_NR_CLK + 24)
+#define CLK_TOP_RG_VDEC (CLK_TOP_NR_CLK + 25)
+#define CLK_TOP_RG_FDPI0 (CLK_TOP_NR_CLK + 26)
+#define CLK_TOP_RG_FDPI1 (CLK_TOP_NR_CLK + 27)
+#define CLK_TOP_RG_AXI_MFG (CLK_TOP_NR_CLK + 28)
+#define CLK_TOP_RG_SLOW_MFG (CLK_TOP_NR_CLK + 29)
+#define CLK_TOP_GFMUX_EMI1X_SEL (CLK_TOP_NR_CLK + 30)
+#define CLK_TOP_CSW_MUX_MFG_SEL (CLK_TOP_NR_CLK + 31)
+#define CLK_TOP_CAMTG_MM_SEL (CLK_TOP_NR_CLK + 32)
+#define CLK_TOP_PWM_MM_SEL (CLK_TOP_NR_CLK + 33)
+#define CLK_TOP_SPM_52M_SEL (CLK_TOP_NR_CLK + 34)
+#define CLK_TOP_MFG_MM_SEL (CLK_TOP_NR_CLK + 35)
+#define CLK_TOP_SMI_MM_SEL (CLK_TOP_NR_CLK + 36)
+#define CLK_TOP_SCAM_MM_SEL (CLK_TOP_NR_CLK + 37)
+#define CLK_TOP_VDEC_MM_SEL (CLK_TOP_NR_CLK + 38)
+#define CLK_TOP_DPI0_MM_SEL (CLK_TOP_NR_CLK + 39)
+#define CLK_TOP_DPI1_MM_SEL (CLK_TOP_NR_CLK + 40)
+#define CLK_TOP_AXI_MFG_IN_SEL (CLK_TOP_NR_CLK + 41)
+#define CLK_TOP_SLOW_MFG_SEL (CLK_TOP_NR_CLK + 42)
+#define MT8167_CLK_TOP_NR_CLK (CLK_TOP_NR_CLK + 43)
+
+/* MFGCFG */
+
+#define CLK_MFG_BAXI 0
+#define CLK_MFG_BMEM 1
+#define CLK_MFG_BG3D 2
+#define CLK_MFG_B26M 3
+#define CLK_MFG_NR_CLK 4
+
+/* MMSYS */
+
+#define CLK_MM_SMI_COMMON 0
+#define CLK_MM_SMI_LARB0 1
+#define CLK_MM_CAM_MDP 2
+#define CLK_MM_MDP_RDMA 3
+#define CLK_MM_MDP_RSZ0 4
+#define CLK_MM_MDP_RSZ1 5
+#define CLK_MM_MDP_TDSHP 6
+#define CLK_MM_MDP_WDMA 7
+#define CLK_MM_MDP_WROT 8
+#define CLK_MM_FAKE_ENG 9
+#define CLK_MM_DISP_OVL0 10
+#define CLK_MM_DISP_RDMA0 11
+#define CLK_MM_DISP_RDMA1 12
+#define CLK_MM_DISP_WDMA 13
+#define CLK_MM_DISP_COLOR 14
+#define CLK_MM_DISP_CCORR 15
+#define CLK_MM_DISP_AAL 16
+#define CLK_MM_DISP_GAMMA 17
+#define CLK_MM_DISP_DITHER 18
+#define CLK_MM_DISP_UFOE 19
+#define CLK_MM_DISP_PWM_MM 20
+#define CLK_MM_DISP_PWM_26M 21
+#define CLK_MM_DSI_ENGINE 22
+#define CLK_MM_DSI_DIGITAL 23
+#define CLK_MM_DPI0_ENGINE 24
+#define CLK_MM_DPI0_PXL 25
+#define CLK_MM_LVDS_PXL 26
+#define CLK_MM_LVDS_CTS 27
+#define CLK_MM_DPI1_ENGINE 28
+#define CLK_MM_DPI1_PXL 29
+#define CLK_MM_HDMI_PXL 30
+#define CLK_MM_HDMI_SPDIF 31
+#define CLK_MM_HDMI_ADSP_BCK 32
+#define CLK_MM_HDMI_PLL 33
+#define CLK_MM_NR_CLK 34
+
+/* IMGSYS */
+
+#define CLK_IMG_LARB1_SMI 0
+#define CLK_IMG_CAM_SMI 1
+#define CLK_IMG_CAM_CAM 2
+#define CLK_IMG_SEN_TG 3
+#define CLK_IMG_SEN_CAM 4
+#define CLK_IMG_VENC 5
+#define CLK_IMG_NR_CLK 6
+
+/* VDECSYS */
+
+#define CLK_VDEC_CKEN 0
+#define CLK_VDEC_LARB1_CKEN 1
+#define CLK_VDEC_NR_CLK 2
+
+#endif /* _DT_BINDINGS_CLK_MT8167_H */
diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h
index 5167b2d..88d73be 100644
--- a/include/dt-bindings/clock/omap4.h
+++ b/include/dt-bindings/clock/omap4.h
@@ -124,6 +124,17 @@
#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158)
#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160)
+/* l4_secure clocks */
+#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0
+#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET)
+#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0)
+#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8)
+#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0)
+#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8)
+#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0)
+#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8)
+#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8)
+
/* l4_wkup clocks */
#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h
index e541193..4177527 100644
--- a/include/dt-bindings/clock/omap5.h
+++ b/include/dt-bindings/clock/omap5.h
@@ -16,6 +16,7 @@
/* abe clocks */
#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
@@ -86,6 +87,21 @@
#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
+/* l4_secure clocks */
+#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
+#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
+#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
+#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
+#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
+#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
+#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
+#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
+#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
+
+/* iva clocks */
+#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+
/* dss clocks */
#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h
index 0010147..5b1416f 100644
--- a/include/dt-bindings/clock/px30-cru.h
+++ b/include/dt-bindings/clock/px30-cru.h
@@ -85,6 +85,8 @@
#define SCLK_EMMC_DIV50 83
#define SCLK_DDRCLK 84
#define SCLK_UART1_SRC 85
+#define SCLK_SDMMC_DIV 86
+#define SCLK_SDMMC_DIV50 87
/* dclk gates */
#define DCLK_VOPB 150
diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h
new file mode 100644
index 0000000..77b6e05
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,apss-ipq.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H
+#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H
+
+#define APCS_ALIAS0_CLK_SRC 0
+#define APCS_ALIAS0_CORE_CLK 1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7180.h b/include/dt-bindings/clock/qcom,dispcc-sc7180.h
new file mode 100644
index 0000000..b9b5161
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sc7180.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
+
+#define DISP_CC_PLL0 0
+#define DISP_CC_PLL0_OUT_EVEN 1
+#define DISP_CC_MDSS_AHB_CLK 2
+#define DISP_CC_MDSS_AHB_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_CLK 4
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
+#define DISP_CC_MDSS_DP_AUX_CLK 8
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC 9
+#define DISP_CC_MDSS_DP_CRYPTO_CLK 10
+#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 11
+#define DISP_CC_MDSS_DP_LINK_CLK 12
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC 13
+#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 14
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK 15
+#define DISP_CC_MDSS_DP_PIXEL_CLK 16
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17
+#define DISP_CC_MDSS_ESC0_CLK 18
+#define DISP_CC_MDSS_ESC0_CLK_SRC 19
+#define DISP_CC_MDSS_MDP_CLK 20
+#define DISP_CC_MDSS_MDP_CLK_SRC 21
+#define DISP_CC_MDSS_MDP_LUT_CLK 22
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23
+#define DISP_CC_MDSS_PCLK0_CLK 24
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 25
+#define DISP_CC_MDSS_ROT_CLK 26
+#define DISP_CC_MDSS_ROT_CLK_SRC 27
+#define DISP_CC_MDSS_RSCC_AHB_CLK 28
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29
+#define DISP_CC_MDSS_VSYNC_CLK 30
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 31
+#define DISP_CC_XO_CLK 32
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
index 11eed4b..4016fd1 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
@@ -35,6 +35,17 @@
#define DISP_CC_PLL0 25
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27
+#define DISP_CC_MDSS_DP_AUX_CLK 28
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29
+#define DISP_CC_MDSS_DP_CRYPTO_CLK 30
+#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31
+#define DISP_CC_MDSS_DP_LINK_CLK 32
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34
+#define DISP_CC_MDSS_DP_PIXEL1_CLK 35
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36
+#define DISP_CC_MDSS_DP_PIXEL_CLK 37
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38
/* DISP_CC Reset */
#define DISP_CC_MDSS_RSCC_BCR 0
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8150.h b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
new file mode 120000
index 0000000..0312b45
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
@@ -0,0 +1 @@
+qcom,dispcc-sm8250.h
\ No newline at end of file
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
new file mode 100644
index 0000000..fdaca6a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK 0
+#define DISP_CC_MDSS_AHB_CLK_SRC 1
+#define DISP_CC_MDSS_BYTE0_CLK 2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 5
+#define DISP_CC_MDSS_BYTE1_CLK 6
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 7
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 9
+#define DISP_CC_MDSS_DP_AUX1_CLK 10
+#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11
+#define DISP_CC_MDSS_DP_AUX_CLK 12
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13
+#define DISP_CC_MDSS_DP_LINK1_CLK 14
+#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15
+#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16
+#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17
+#define DISP_CC_MDSS_DP_LINK_CLK 18
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19
+#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21
+#define DISP_CC_MDSS_DP_PIXEL1_CLK 22
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23
+#define DISP_CC_MDSS_DP_PIXEL2_CLK 24
+#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25
+#define DISP_CC_MDSS_DP_PIXEL_CLK 26
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27
+#define DISP_CC_MDSS_ESC0_CLK 28
+#define DISP_CC_MDSS_ESC0_CLK_SRC 29
+#define DISP_CC_MDSS_ESC1_CLK 30
+#define DISP_CC_MDSS_ESC1_CLK_SRC 31
+#define DISP_CC_MDSS_MDP_CLK 32
+#define DISP_CC_MDSS_MDP_CLK_SRC 33
+#define DISP_CC_MDSS_MDP_LUT_CLK 34
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 35
+#define DISP_CC_MDSS_PCLK0_CLK 36
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 37
+#define DISP_CC_MDSS_PCLK1_CLK 38
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 39
+#define DISP_CC_MDSS_ROT_CLK 40
+#define DISP_CC_MDSS_ROT_CLK_SRC 41
+#define DISP_CC_MDSS_RSCC_AHB_CLK 42
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 43
+#define DISP_CC_MDSS_VSYNC_CLK 44
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 45
+#define DISP_CC_PLL0 46
+#define DISP_CC_PLL1 47
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_RSCC_BCR 1
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq6018.h b/include/dt-bindings/clock/qcom,gcc-ipq6018.h
new file mode 100644
index 0000000..6f4be3a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq6018.h
@@ -0,0 +1,262 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
+
+#define GPLL0 0
+#define UBI32_PLL 1
+#define GPLL6 2
+#define GPLL4 3
+#define PCNOC_BFDCD_CLK_SRC 4
+#define GPLL2 5
+#define NSS_CRYPTO_PLL 6
+#define NSS_PPE_CLK_SRC 7
+#define GCC_XO_CLK_SRC 8
+#define NSS_CE_CLK_SRC 9
+#define GCC_SLEEP_CLK_SRC 10
+#define APSS_AHB_CLK_SRC 11
+#define NSS_PORT5_RX_CLK_SRC 12
+#define NSS_PORT5_TX_CLK_SRC 13
+#define PCIE0_AXI_CLK_SRC 14
+#define USB0_MASTER_CLK_SRC 15
+#define APSS_AHB_POSTDIV_CLK_SRC 16
+#define NSS_PORT1_RX_CLK_SRC 17
+#define NSS_PORT1_TX_CLK_SRC 18
+#define NSS_PORT2_RX_CLK_SRC 19
+#define NSS_PORT2_TX_CLK_SRC 20
+#define NSS_PORT3_RX_CLK_SRC 21
+#define NSS_PORT3_TX_CLK_SRC 22
+#define NSS_PORT4_RX_CLK_SRC 23
+#define NSS_PORT4_TX_CLK_SRC 24
+#define NSS_PORT5_RX_DIV_CLK_SRC 25
+#define NSS_PORT5_TX_DIV_CLK_SRC 26
+#define APSS_AXI_CLK_SRC 27
+#define NSS_CRYPTO_CLK_SRC 28
+#define NSS_PORT1_RX_DIV_CLK_SRC 29
+#define NSS_PORT1_TX_DIV_CLK_SRC 30
+#define NSS_PORT2_RX_DIV_CLK_SRC 31
+#define NSS_PORT2_TX_DIV_CLK_SRC 32
+#define NSS_PORT3_RX_DIV_CLK_SRC 33
+#define NSS_PORT3_TX_DIV_CLK_SRC 34
+#define NSS_PORT4_RX_DIV_CLK_SRC 35
+#define NSS_PORT4_TX_DIV_CLK_SRC 36
+#define NSS_UBI0_CLK_SRC 37
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 38
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 39
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 40
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 41
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 42
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 43
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 44
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 45
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 46
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 47
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 48
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 49
+#define BLSP1_UART1_APPS_CLK_SRC 50
+#define BLSP1_UART2_APPS_CLK_SRC 51
+#define BLSP1_UART3_APPS_CLK_SRC 52
+#define BLSP1_UART4_APPS_CLK_SRC 53
+#define BLSP1_UART5_APPS_CLK_SRC 54
+#define BLSP1_UART6_APPS_CLK_SRC 55
+#define CRYPTO_CLK_SRC 56
+#define NSS_UBI0_DIV_CLK_SRC 57
+#define PCIE0_AUX_CLK_SRC 58
+#define PCIE0_PIPE_CLK_SRC 59
+#define SDCC1_APPS_CLK_SRC 60
+#define USB0_AUX_CLK_SRC 61
+#define USB0_MOCK_UTMI_CLK_SRC 62
+#define USB0_PIPE_CLK_SRC 63
+#define USB1_MOCK_UTMI_CLK_SRC 64
+#define GCC_APSS_AHB_CLK 65
+#define GCC_APSS_AXI_CLK 66
+#define GCC_BLSP1_AHB_CLK 67
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 68
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 69
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 70
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 71
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 72
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 73
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 74
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 75
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 76
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 77
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 78
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 79
+#define GCC_BLSP1_UART1_APPS_CLK 80
+#define GCC_BLSP1_UART2_APPS_CLK 81
+#define GCC_BLSP1_UART3_APPS_CLK 82
+#define GCC_BLSP1_UART4_APPS_CLK 83
+#define GCC_BLSP1_UART5_APPS_CLK 84
+#define GCC_BLSP1_UART6_APPS_CLK 85
+#define GCC_CRYPTO_AHB_CLK 86
+#define GCC_CRYPTO_AXI_CLK 87
+#define GCC_CRYPTO_CLK 88
+#define GCC_XO_CLK 89
+#define GCC_XO_DIV4_CLK 90
+#define GCC_MDIO_AHB_CLK 91
+#define GCC_CRYPTO_PPE_CLK 92
+#define GCC_NSS_CE_APB_CLK 93
+#define GCC_NSS_CE_AXI_CLK 94
+#define GCC_NSS_CFG_CLK 95
+#define GCC_NSS_CRYPTO_CLK 96
+#define GCC_NSS_CSR_CLK 97
+#define GCC_NSS_EDMA_CFG_CLK 98
+#define GCC_NSS_EDMA_CLK 99
+#define GCC_NSS_NOC_CLK 100
+#define GCC_NSS_PORT1_RX_CLK 101
+#define GCC_NSS_PORT1_TX_CLK 102
+#define GCC_NSS_PORT2_RX_CLK 103
+#define GCC_NSS_PORT2_TX_CLK 104
+#define GCC_NSS_PORT3_RX_CLK 105
+#define GCC_NSS_PORT3_TX_CLK 106
+#define GCC_NSS_PORT4_RX_CLK 107
+#define GCC_NSS_PORT4_TX_CLK 108
+#define GCC_NSS_PORT5_RX_CLK 109
+#define GCC_NSS_PORT5_TX_CLK 110
+#define GCC_NSS_PPE_CFG_CLK 111
+#define GCC_NSS_PPE_CLK 112
+#define GCC_NSS_PPE_IPE_CLK 113
+#define GCC_NSS_PTP_REF_CLK 114
+#define GCC_NSSNOC_CE_APB_CLK 115
+#define GCC_NSSNOC_CE_AXI_CLK 116
+#define GCC_NSSNOC_CRYPTO_CLK 117
+#define GCC_NSSNOC_PPE_CFG_CLK 118
+#define GCC_NSSNOC_PPE_CLK 119
+#define GCC_NSSNOC_QOSGEN_REF_CLK 120
+#define GCC_NSSNOC_TIMEOUT_REF_CLK 121
+#define GCC_NSSNOC_UBI0_AHB_CLK 122
+#define GCC_PORT1_MAC_CLK 123
+#define GCC_PORT2_MAC_CLK 124
+#define GCC_PORT3_MAC_CLK 125
+#define GCC_PORT4_MAC_CLK 126
+#define GCC_PORT5_MAC_CLK 127
+#define GCC_UBI0_AHB_CLK 128
+#define GCC_UBI0_AXI_CLK 129
+#define GCC_UBI0_CORE_CLK 130
+#define GCC_PCIE0_AHB_CLK 131
+#define GCC_PCIE0_AUX_CLK 132
+#define GCC_PCIE0_AXI_M_CLK 133
+#define GCC_PCIE0_AXI_S_CLK 134
+#define GCC_PCIE0_PIPE_CLK 135
+#define GCC_PRNG_AHB_CLK 136
+#define GCC_QPIC_AHB_CLK 137
+#define GCC_QPIC_CLK 138
+#define GCC_SDCC1_AHB_CLK 139
+#define GCC_SDCC1_APPS_CLK 140
+#define GCC_UNIPHY0_AHB_CLK 141
+#define GCC_UNIPHY0_PORT1_RX_CLK 142
+#define GCC_UNIPHY0_PORT1_TX_CLK 143
+#define GCC_UNIPHY0_PORT2_RX_CLK 144
+#define GCC_UNIPHY0_PORT2_TX_CLK 145
+#define GCC_UNIPHY0_PORT3_RX_CLK 146
+#define GCC_UNIPHY0_PORT3_TX_CLK 147
+#define GCC_UNIPHY0_PORT4_RX_CLK 148
+#define GCC_UNIPHY0_PORT4_TX_CLK 149
+#define GCC_UNIPHY0_PORT5_RX_CLK 150
+#define GCC_UNIPHY0_PORT5_TX_CLK 151
+#define GCC_UNIPHY0_SYS_CLK 152
+#define GCC_UNIPHY1_AHB_CLK 153
+#define GCC_UNIPHY1_PORT5_RX_CLK 154
+#define GCC_UNIPHY1_PORT5_TX_CLK 155
+#define GCC_UNIPHY1_SYS_CLK 156
+#define GCC_USB0_AUX_CLK 157
+#define GCC_USB0_MASTER_CLK 158
+#define GCC_USB0_MOCK_UTMI_CLK 159
+#define GCC_USB0_PHY_CFG_AHB_CLK 160
+#define GCC_USB0_PIPE_CLK 161
+#define GCC_USB0_SLEEP_CLK 162
+#define GCC_USB1_MASTER_CLK 163
+#define GCC_USB1_MOCK_UTMI_CLK 164
+#define GCC_USB1_PHY_CFG_AHB_CLK 165
+#define GCC_USB1_SLEEP_CLK 166
+#define GP1_CLK_SRC 167
+#define GP2_CLK_SRC 168
+#define GP3_CLK_SRC 169
+#define GCC_GP1_CLK 170
+#define GCC_GP2_CLK 171
+#define GCC_GP3_CLK 172
+#define SYSTEM_NOC_BFDCD_CLK_SRC 173
+#define GCC_NSSNOC_SNOC_CLK 174
+#define GCC_UBI0_NC_AXI_CLK 175
+#define GCC_UBI1_NC_AXI_CLK 176
+#define GPLL0_MAIN 177
+#define UBI32_PLL_MAIN 178
+#define GPLL6_MAIN 179
+#define GPLL4_MAIN 180
+#define GPLL2_MAIN 181
+#define NSS_CRYPTO_PLL_MAIN 182
+#define GCC_CMN_12GPLL_AHB_CLK 183
+#define GCC_CMN_12GPLL_SYS_CLK 184
+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 185
+#define GCC_SYS_NOC_USB0_AXI_CLK 186
+#define GCC_SYS_NOC_PCIE0_AXI_CLK 187
+#define QDSS_TSCTR_CLK_SRC 188
+#define QDSS_AT_CLK_SRC 189
+#define GCC_QDSS_AT_CLK 190
+#define GCC_QDSS_DAP_CLK 191
+#define ADSS_PWM_CLK_SRC 192
+#define GCC_ADSS_PWM_CLK 193
+#define SDCC1_ICE_CORE_CLK_SRC 194
+#define GCC_SDCC1_ICE_CORE_CLK 195
+#define GCC_DCC_CLK 196
+#define PCIE0_RCHNG_CLK_SRC 197
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 198
+#define PCIE0_RCHNG_CLK 199
+#define UBI32_MEM_NOC_BFDCD_CLK_SRC 200
+#define WCSS_AHB_CLK_SRC 201
+#define Q6_AXI_CLK_SRC 202
+#define GCC_Q6SS_PCLKDBG_CLK 203
+#define GCC_Q6_TSCTR_1TO2_CLK 204
+#define GCC_WCSS_CORE_TBU_CLK 205
+#define GCC_WCSS_AXI_M_CLK 206
+#define GCC_SYS_NOC_WCSS_AHB_CLK 207
+#define GCC_Q6_AXIM_CLK 208
+#define GCC_Q6SS_ATBM_CLK 209
+#define GCC_WCSS_Q6_TBU_CLK 210
+#define GCC_Q6_AXIM2_CLK 211
+#define GCC_Q6_AHB_CLK 212
+#define GCC_Q6_AHB_S_CLK 213
+#define GCC_WCSS_DBG_IFC_APB_CLK 214
+#define GCC_WCSS_DBG_IFC_ATB_CLK 215
+#define GCC_WCSS_DBG_IFC_NTS_CLK 216
+#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 217
+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 218
+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 219
+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 220
+#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 221
+#define GCC_WCSS_ECAHB_CLK 222
+#define GCC_WCSS_ACMT_CLK 223
+#define GCC_WCSS_AHB_S_CLK 224
+#define GCC_RBCPR_WCSS_CLK 225
+#define RBCPR_WCSS_CLK_SRC 226
+#define GCC_RBCPR_WCSS_AHB_CLK 227
+#define GCC_LPASS_CORE_AXIM_CLK 228
+#define GCC_LPASS_SNOC_CFG_CLK 229
+#define GCC_LPASS_Q6_AXIM_CLK 230
+#define GCC_LPASS_Q6_ATBM_AT_CLK 231
+#define GCC_LPASS_Q6_PCLKDBG_CLK 232
+#define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK 233
+#define GCC_LPASS_Q6SS_TRIG_CLK 234
+#define GCC_LPASS_TBU_CLK 235
+#define LPASS_CORE_AXIM_CLK_SRC 236
+#define LPASS_SNOC_CFG_CLK_SRC 237
+#define LPASS_Q6_AXIM_CLK_SRC 238
+#define GCC_PCNOC_LPASS_CLK 239
+#define GCC_UBI0_UTCM_CLK 240
+#define SNOC_NSSNOC_BFDCD_CLK_SRC 241
+#define GCC_SNOC_NSSNOC_CLK 242
+#define GCC_MEM_NOC_Q6_AXI_CLK 243
+#define GCC_MEM_NOC_UBI32_CLK 244
+#define GCC_MEM_NOC_LPASS_CLK 245
+#define GCC_SNOC_LPASS_CFG_CLK 246
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 247
+#define GCC_QDSS_STM_CLK 248
+#define GCC_QDSS_TRACECLKIN_CLK 249
+#define QDSS_STM_CLK_SRC 250
+#define QDSS_TRACECLKIN_CLK_SRC 251
+#define GCC_NSSNOC_ATB_CLK 252
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
index 4de4811..8e2bec1 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -230,6 +230,9 @@
#define GCC_GP1_CLK 221
#define GCC_GP2_CLK 222
#define GCC_GP3_CLK 223
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
+#define GCC_PCIE0_RCHNG_CLK_SRC 225
+#define GCC_PCIE0_RCHNG_CLK 226
#define GCC_BLSP1_BCR 0
#define GCC_BLSP1_QUP1_BCR 1
@@ -362,5 +365,6 @@
#define GCC_PCIE1_AXI_SLAVE_ARES 128
#define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
+#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8939.h b/include/dt-bindings/clock/qcom,gcc-msm8939.h
new file mode 100644
index 0000000..0634467
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8939.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2020 Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8939_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8939_H
+
+#define GPLL0 0
+#define GPLL0_VOTE 1
+#define BIMC_PLL 2
+#define BIMC_PLL_VOTE 3
+#define GPLL1 4
+#define GPLL1_VOTE 5
+#define GPLL2 6
+#define GPLL2_VOTE 7
+#define PCNOC_BFDCD_CLK_SRC 8
+#define SYSTEM_NOC_BFDCD_CLK_SRC 9
+#define CAMSS_AHB_CLK_SRC 10
+#define APSS_AHB_CLK_SRC 11
+#define CSI0_CLK_SRC 12
+#define CSI1_CLK_SRC 13
+#define GFX3D_CLK_SRC 14
+#define VFE0_CLK_SRC 15
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27
+#define BLSP1_UART1_APPS_CLK_SRC 28
+#define BLSP1_UART2_APPS_CLK_SRC 29
+#define CCI_CLK_SRC 30
+#define CAMSS_GP0_CLK_SRC 31
+#define CAMSS_GP1_CLK_SRC 32
+#define JPEG0_CLK_SRC 33
+#define MCLK0_CLK_SRC 34
+#define MCLK1_CLK_SRC 35
+#define CSI0PHYTIMER_CLK_SRC 36
+#define CSI1PHYTIMER_CLK_SRC 37
+#define CPP_CLK_SRC 38
+#define CRYPTO_CLK_SRC 39
+#define GP1_CLK_SRC 40
+#define GP2_CLK_SRC 41
+#define GP3_CLK_SRC 42
+#define BYTE0_CLK_SRC 43
+#define ESC0_CLK_SRC 44
+#define MDP_CLK_SRC 45
+#define PCLK0_CLK_SRC 46
+#define VSYNC_CLK_SRC 47
+#define PDM2_CLK_SRC 48
+#define SDCC1_APPS_CLK_SRC 49
+#define SDCC2_APPS_CLK_SRC 50
+#define APSS_TCU_CLK_SRC 51
+#define USB_HS_SYSTEM_CLK_SRC 52
+#define VCODEC0_CLK_SRC 53
+#define GCC_BLSP1_AHB_CLK 54
+#define GCC_BLSP1_SLEEP_CLK 55
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67
+#define GCC_BLSP1_UART1_APPS_CLK 68
+#define GCC_BLSP1_UART2_APPS_CLK 69
+#define GCC_BOOT_ROM_AHB_CLK 70
+#define GCC_CAMSS_CCI_AHB_CLK 71
+#define GCC_CAMSS_CCI_CLK 72
+#define GCC_CAMSS_CSI0_AHB_CLK 73
+#define GCC_CAMSS_CSI0_CLK 74
+#define GCC_CAMSS_CSI0PHY_CLK 75
+#define GCC_CAMSS_CSI0PIX_CLK 76
+#define GCC_CAMSS_CSI0RDI_CLK 77
+#define GCC_CAMSS_CSI1_AHB_CLK 78
+#define GCC_CAMSS_CSI1_CLK 79
+#define GCC_CAMSS_CSI1PHY_CLK 80
+#define GCC_CAMSS_CSI1PIX_CLK 81
+#define GCC_CAMSS_CSI1RDI_CLK 82
+#define GCC_CAMSS_CSI_VFE0_CLK 83
+#define GCC_CAMSS_GP0_CLK 84
+#define GCC_CAMSS_GP1_CLK 85
+#define GCC_CAMSS_ISPIF_AHB_CLK 86
+#define GCC_CAMSS_JPEG0_CLK 87
+#define GCC_CAMSS_JPEG_AHB_CLK 88
+#define GCC_CAMSS_JPEG_AXI_CLK 89
+#define GCC_CAMSS_MCLK0_CLK 90
+#define GCC_CAMSS_MCLK1_CLK 91
+#define GCC_CAMSS_MICRO_AHB_CLK 92
+#define GCC_CAMSS_CSI0PHYTIMER_CLK 93
+#define GCC_CAMSS_CSI1PHYTIMER_CLK 94
+#define GCC_CAMSS_AHB_CLK 95
+#define GCC_CAMSS_TOP_AHB_CLK 96
+#define GCC_CAMSS_CPP_AHB_CLK 97
+#define GCC_CAMSS_CPP_CLK 98
+#define GCC_CAMSS_VFE0_CLK 99
+#define GCC_CAMSS_VFE_AHB_CLK 100
+#define GCC_CAMSS_VFE_AXI_CLK 101
+#define GCC_CRYPTO_AHB_CLK 102
+#define GCC_CRYPTO_AXI_CLK 103
+#define GCC_CRYPTO_CLK 104
+#define GCC_OXILI_GMEM_CLK 105
+#define GCC_GP1_CLK 106
+#define GCC_GP2_CLK 107
+#define GCC_GP3_CLK 108
+#define GCC_MDSS_AHB_CLK 109
+#define GCC_MDSS_AXI_CLK 110
+#define GCC_MDSS_BYTE0_CLK 111
+#define GCC_MDSS_ESC0_CLK 112
+#define GCC_MDSS_MDP_CLK 113
+#define GCC_MDSS_PCLK0_CLK 114
+#define GCC_MDSS_VSYNC_CLK 115
+#define GCC_MSS_CFG_AHB_CLK 116
+#define GCC_OXILI_AHB_CLK 117
+#define GCC_OXILI_GFX3D_CLK 118
+#define GCC_PDM2_CLK 119
+#define GCC_PDM_AHB_CLK 120
+#define GCC_PRNG_AHB_CLK 121
+#define GCC_SDCC1_AHB_CLK 122
+#define GCC_SDCC1_APPS_CLK 123
+#define GCC_SDCC2_AHB_CLK 124
+#define GCC_SDCC2_APPS_CLK 125
+#define GCC_GTCU_AHB_CLK 126
+#define GCC_JPEG_TBU_CLK 127
+#define GCC_MDP_TBU_CLK 128
+#define GCC_SMMU_CFG_CLK 129
+#define GCC_VENUS_TBU_CLK 130
+#define GCC_VFE_TBU_CLK 131
+#define GCC_USB2A_PHY_SLEEP_CLK 132
+#define GCC_USB_HS_AHB_CLK 133
+#define GCC_USB_HS_SYSTEM_CLK 134
+#define GCC_VENUS0_AHB_CLK 135
+#define GCC_VENUS0_AXI_CLK 136
+#define GCC_VENUS0_VCODEC0_CLK 137
+#define BIMC_DDR_CLK_SRC 138
+#define GCC_APSS_TCU_CLK 139
+#define GCC_GFX_TCU_CLK 140
+#define BIMC_GPU_CLK_SRC 141
+#define GCC_BIMC_GFX_CLK 142
+#define GCC_BIMC_GPU_CLK 143
+#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144
+#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145
+#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146
+#define ULTAUDIO_XO_CLK_SRC 147
+#define ULTAUDIO_AHBFABRIC_CLK_SRC 148
+#define CODEC_DIGCODEC_CLK_SRC 149
+#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150
+#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151
+#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152
+#define GCC_ULTAUDIO_STC_XO_CLK 153
+#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154
+#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155
+#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156
+#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157
+#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158
+#define GCC_CODEC_DIGCODEC_CLK 159
+#define GCC_MSS_Q6_BIMC_AXI_CLK 160
+#define GPLL3 161
+#define GPLL3_VOTE 162
+#define GPLL4 163
+#define GPLL4_VOTE 164
+#define GPLL5 165
+#define GPLL5_VOTE 166
+#define GPLL6 167
+#define GPLL6_VOTE 168
+#define BYTE1_CLK_SRC 169
+#define GCC_MDSS_BYTE1_CLK 170
+#define ESC1_CLK_SRC 171
+#define GCC_MDSS_ESC1_CLK 172
+#define PCLK1_CLK_SRC 173
+#define GCC_MDSS_PCLK1_CLK 174
+#define GCC_GFX_TBU_CLK 175
+#define GCC_CPP_TBU_CLK 176
+#define GCC_MDP_RT_TBU_CLK 177
+#define USB_FS_SYSTEM_CLK_SRC 178
+#define USB_FS_IC_CLK_SRC 179
+#define GCC_USB_FS_AHB_CLK 180
+#define GCC_USB_FS_IC_CLK 181
+#define GCC_USB_FS_SYSTEM_CLK 182
+#define GCC_VENUS0_CORE0_VCODEC0_CLK 183
+#define GCC_VENUS0_CORE1_VCODEC0_CLK 184
+#define GCC_OXILI_TIMER_CLK 185
+
+/* Indexes for GDSCs */
+#define BIMC_GDSC 0
+#define VENUS_GDSC 1
+#define MDSS_GDSC 2
+#define JPEG_GDSC 3
+#define VFE_GDSC 4
+#define OXILI_GDSC 5
+#define VENUS_CORE0_GDSC 6
+#define VENUS_CORE1_GDSC 7
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8994.h b/include/dt-bindings/clock/qcom,gcc-msm8994.h
index 9389693..507b8d6 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8994.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8994.h
@@ -126,5 +126,41 @@
#define GCC_USB3_PHY_AUX_CLK 116
#define GCC_USB_HS_SYSTEM_CLK 117
#define GCC_SDCC1_AHB_CLK 118
+#define GCC_LPASS_Q6_AXI_CLK 119
+#define GCC_MSS_Q6_BIMC_AXI_CLK 120
+#define GCC_PCIE_0_CFG_AHB_CLK 121
+#define GCC_PCIE_0_MSTR_AXI_CLK 122
+#define GCC_PCIE_0_SLV_AXI_CLK 123
+#define GCC_PCIE_1_CFG_AHB_CLK 124
+#define GCC_PCIE_1_MSTR_AXI_CLK 125
+#define GCC_PCIE_1_SLV_AXI_CLK 126
+#define GCC_PDM_AHB_CLK 127
+#define GCC_SDCC2_AHB_CLK 128
+#define GCC_SDCC3_AHB_CLK 129
+#define GCC_SDCC4_AHB_CLK 130
+#define GCC_TSIF_AHB_CLK 131
+#define GCC_UFS_AHB_CLK 132
+#define GCC_UFS_RX_SYMBOL_0_CLK 133
+#define GCC_UFS_RX_SYMBOL_1_CLK 134
+#define GCC_UFS_TX_SYMBOL_0_CLK 135
+#define GCC_UFS_TX_SYMBOL_1_CLK 136
+#define GCC_USB2_HS_PHY_SLEEP_CLK 137
+#define GCC_USB30_SLEEP_CLK 138
+#define GCC_USB_HS_AHB_CLK 139
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 140
+
+/* GDSCs */
+#define PCIE_GDSC 0
+#define PCIE_0_GDSC 1
+#define PCIE_1_GDSC 2
+#define USB30_GDSC 3
+#define UFS_GDSC 4
+
+/* Resets */
+#define USB3_PHY_RESET 0
+#define USB3PHY_PHY_RESET 1
+#define PCIE_PHY_0_RESET 2
+#define PCIE_PHY_1_RESET 3
+#define QUSB2_PHY_RESET 4
#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
index ab37626..6a73a17 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8998.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -177,6 +177,13 @@
#define GCC_UFS_CLKREF_CLK 168
#define GCC_PCIE_CLKREF_CLK 169
#define GCC_RX1_USB2_CLKREF_CLK 170
+#define GCC_MSS_CFG_AHB_CLK 171
+#define GCC_BOOT_ROM_AHB_CLK 172
+#define GCC_MSS_GPLL0_DIV_CLK_SRC 173
+#define GCC_MSS_SNOC_AXI_CLK 174
+#define GCC_MSS_MNOC_BIMC_AXI_CLK 175
+#define GCC_BIMC_GFX_CLK 176
+#define UFS_UNIPRO_CORE_CLK_SRC 177
#define PCIE_0_GDSC 0
#define UFS_GDSC 1
@@ -290,5 +297,6 @@
#define GCC_MSMPU_BCR 105
#define GCC_QUSB2PHY_PRIM_BCR 106
#define GCC_QUSB2PHY_SEC_BCR 107
+#define GCC_MSS_RESTART 108
#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h
new file mode 100644
index 0000000..bdf43ad
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
+
+/* GCC clocks */
+#define GCC_GPLL0_MAIN_DIV_CDIV 0
+#define GPLL0 1
+#define GPLL0_OUT_EVEN 2
+#define GPLL1 3
+#define GPLL4 4
+#define GPLL6 5
+#define GPLL7 6
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 7
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
+#define GCC_BOOT_ROM_AHB_CLK 9
+#define GCC_CAMERA_AHB_CLK 10
+#define GCC_CAMERA_HF_AXI_CLK 11
+#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12
+#define GCC_CAMERA_XO_CLK 13
+#define GCC_CE1_AHB_CLK 14
+#define GCC_CE1_AXI_CLK 15
+#define GCC_CE1_CLK 16
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
+#define GCC_CPUSS_AHB_CLK 18
+#define GCC_CPUSS_AHB_CLK_SRC 19
+#define GCC_CPUSS_GNOC_CLK 20
+#define GCC_CPUSS_RBCPR_CLK 21
+#define GCC_DDRSS_GPU_AXI_CLK 22
+#define GCC_DISP_AHB_CLK 23
+#define GCC_DISP_GPLL0_CLK_SRC 24
+#define GCC_DISP_GPLL0_DIV_CLK_SRC 25
+#define GCC_DISP_HF_AXI_CLK 26
+#define GCC_DISP_THROTTLE_HF_AXI_CLK 27
+#define GCC_DISP_XO_CLK 28
+#define GCC_GP1_CLK 29
+#define GCC_GP1_CLK_SRC 30
+#define GCC_GP2_CLK 31
+#define GCC_GP2_CLK_SRC 32
+#define GCC_GP3_CLK 33
+#define GCC_GP3_CLK_SRC 34
+#define GCC_GPU_CFG_AHB_CLK 35
+#define GCC_GPU_GPLL0_CLK_SRC 36
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 37
+#define GCC_GPU_MEMNOC_GFX_CLK 38
+#define GCC_GPU_SNOC_DVM_GFX_CLK 39
+#define GCC_NPU_AXI_CLK 40
+#define GCC_NPU_BWMON_AXI_CLK 41
+#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42
+#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43
+#define GCC_NPU_CFG_AHB_CLK 44
+#define GCC_NPU_DMA_CLK 45
+#define GCC_NPU_GPLL0_CLK_SRC 46
+#define GCC_NPU_GPLL0_DIV_CLK_SRC 47
+#define GCC_PDM2_CLK 48
+#define GCC_PDM2_CLK_SRC 49
+#define GCC_PDM_AHB_CLK 50
+#define GCC_PDM_XO4_CLK 51
+#define GCC_PRNG_AHB_CLK 52
+#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53
+#define GCC_QSPI_CORE_CLK 54
+#define GCC_QSPI_CORE_CLK_SRC 55
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56
+#define GCC_QUPV3_WRAP0_CORE_CLK 57
+#define GCC_QUPV3_WRAP0_S0_CLK 58
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59
+#define GCC_QUPV3_WRAP0_S1_CLK 60
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61
+#define GCC_QUPV3_WRAP0_S2_CLK 62
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63
+#define GCC_QUPV3_WRAP0_S3_CLK 64
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65
+#define GCC_QUPV3_WRAP0_S4_CLK 66
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67
+#define GCC_QUPV3_WRAP0_S5_CLK 68
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70
+#define GCC_QUPV3_WRAP1_CORE_CLK 71
+#define GCC_QUPV3_WRAP1_S0_CLK 72
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
+#define GCC_QUPV3_WRAP1_S1_CLK 74
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
+#define GCC_QUPV3_WRAP1_S2_CLK 76
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
+#define GCC_QUPV3_WRAP1_S3_CLK 78
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
+#define GCC_QUPV3_WRAP1_S4_CLK 80
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
+#define GCC_QUPV3_WRAP1_S5_CLK 82
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87
+#define GCC_SDCC1_AHB_CLK 88
+#define GCC_SDCC1_APPS_CLK 89
+#define GCC_SDCC1_APPS_CLK_SRC 90
+#define GCC_SDCC1_ICE_CORE_CLK 91
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 92
+#define GCC_SDCC2_AHB_CLK 93
+#define GCC_SDCC2_APPS_CLK 94
+#define GCC_SDCC2_APPS_CLK_SRC 95
+#define GCC_SYS_NOC_CPUSS_AHB_CLK 96
+#define GCC_UFS_MEM_CLKREF_CLK 97
+#define GCC_UFS_PHY_AHB_CLK 98
+#define GCC_UFS_PHY_AXI_CLK 99
+#define GCC_UFS_PHY_AXI_CLK_SRC 100
+#define GCC_UFS_PHY_ICE_CORE_CLK 101
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102
+#define GCC_UFS_PHY_PHY_AUX_CLK 103
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108
+#define GCC_USB30_PRIM_MASTER_CLK 109
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 110
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112
+#define GCC_USB30_PRIM_SLEEP_CLK 113
+#define GCC_USB3_PRIM_CLKREF_CLK 114
+#define GCC_USB3_PRIM_PHY_AUX_CLK 115
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 118
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119
+#define GCC_VIDEO_AHB_CLK 120
+#define GCC_VIDEO_AXI_CLK 121
+#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
+#define GCC_VIDEO_THROTTLE_AXI_CLK 123
+#define GCC_VIDEO_XO_CLK 124
+#define GCC_MSS_CFG_AHB_CLK 125
+#define GCC_MSS_MFAB_AXIS_CLK 126
+#define GCC_MSS_NAV_AXI_CLK 127
+#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128
+#define GCC_MSS_SNOC_AXI_CLK 129
+#define GCC_SEC_CTRL_CLK_SRC 130
+#define GCC_LPASS_CFG_NOC_SWAY_CLK 131
+
+/* GCC resets */
+#define GCC_QUSB2PHY_PRIM_BCR 0
+#define GCC_QUSB2PHY_SEC_BCR 1
+#define GCC_UFS_PHY_BCR 2
+#define GCC_USB30_PRIM_BCR 3
+#define GCC_USB3_DP_PHY_PRIM_BCR 4
+#define GCC_USB3_DP_PHY_SEC_BCR 5
+#define GCC_USB3_PHY_PRIM_BCR 6
+#define GCC_USB3_PHY_SEC_BCR 7
+#define GCC_USB3PHY_PHY_PRIM_BCR 8
+#define GCC_USB3PHY_PHY_SEC_BCR 9
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
+
+/* GCC GDSCRs */
+#define UFS_PHY_GDSC 0
+#define USB30_PRIM_GDSC 1
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
index 4683022..df8a6f3 100644
--- a/include/dt-bindings/clock/qcom,gcc-sdm660.h
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -152,5 +152,6 @@
#define GCC_USB_20_BCR 6
#define GCC_USB_30_BCR 7
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
+#define GCC_MSS_RESTART 9
#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
index 90d60ef..3e1a918 100644
--- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -240,4 +240,8 @@
#define GCC_USB30_SEC_BCR 27
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
+/* GCC GDSCRs */
+#define USB30_PRIM_GDSC 4
+#define USB30_SEC_GDSC 5
+
#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8250.h b/include/dt-bindings/clock/qcom,gcc-sm8250.h
new file mode 100644
index 0000000..7b7abe3
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sm8250.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
+
+/* GCC clocks */
+#define GPLL0 0
+#define GPLL0_OUT_EVEN 1
+#define GPLL4 2
+#define GPLL9 3
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 4
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 5
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 6
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 7
+#define GCC_AGGRE_USB3_SEC_AXI_CLK 8
+#define GCC_BOOT_ROM_AHB_CLK 9
+#define GCC_CAMERA_AHB_CLK 10
+#define GCC_CAMERA_HF_AXI_CLK 11
+#define GCC_CAMERA_SF_AXI_CLK 12
+#define GCC_CAMERA_XO_CLK 13
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 14
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 15
+#define GCC_CPUSS_AHB_CLK 16
+#define GCC_CPUSS_AHB_CLK_SRC 17
+#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 18
+#define GCC_CPUSS_DVM_BUS_CLK 19
+#define GCC_CPUSS_RBCPR_CLK 20
+#define GCC_DDRSS_GPU_AXI_CLK 21
+#define GCC_DDRSS_PCIE_SF_TBU_CLK 22
+#define GCC_DISP_AHB_CLK 23
+#define GCC_DISP_HF_AXI_CLK 24
+#define GCC_DISP_SF_AXI_CLK 25
+#define GCC_DISP_XO_CLK 26
+#define GCC_GP1_CLK 27
+#define GCC_GP1_CLK_SRC 28
+#define GCC_GP2_CLK 29
+#define GCC_GP2_CLK_SRC 30
+#define GCC_GP3_CLK 31
+#define GCC_GP3_CLK_SRC 32
+#define GCC_GPU_CFG_AHB_CLK 33
+#define GCC_GPU_GPLL0_CLK_SRC 34
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
+#define GCC_GPU_IREF_EN 36
+#define GCC_GPU_MEMNOC_GFX_CLK 37
+#define GCC_GPU_SNOC_DVM_GFX_CLK 38
+#define GCC_NPU_AXI_CLK 39
+#define GCC_NPU_BWMON_AXI_CLK 40
+#define GCC_NPU_BWMON_CFG_AHB_CLK 41
+#define GCC_NPU_CFG_AHB_CLK 42
+#define GCC_NPU_DMA_CLK 43
+#define GCC_NPU_GPLL0_CLK_SRC 44
+#define GCC_NPU_GPLL0_DIV_CLK_SRC 45
+#define GCC_PCIE0_PHY_REFGEN_CLK 46
+#define GCC_PCIE1_PHY_REFGEN_CLK 47
+#define GCC_PCIE2_PHY_REFGEN_CLK 48
+#define GCC_PCIE_0_AUX_CLK 49
+#define GCC_PCIE_0_AUX_CLK_SRC 50
+#define GCC_PCIE_0_CFG_AHB_CLK 51
+#define GCC_PCIE_0_MSTR_AXI_CLK 52
+#define GCC_PCIE_0_PIPE_CLK 53
+#define GCC_PCIE_0_SLV_AXI_CLK 54
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55
+#define GCC_PCIE_1_AUX_CLK 56
+#define GCC_PCIE_1_AUX_CLK_SRC 57
+#define GCC_PCIE_1_CFG_AHB_CLK 58
+#define GCC_PCIE_1_MSTR_AXI_CLK 59
+#define GCC_PCIE_1_PIPE_CLK 60
+#define GCC_PCIE_1_SLV_AXI_CLK 61
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62
+#define GCC_PCIE_2_AUX_CLK 63
+#define GCC_PCIE_2_AUX_CLK_SRC 64
+#define GCC_PCIE_2_CFG_AHB_CLK 65
+#define GCC_PCIE_2_MSTR_AXI_CLK 66
+#define GCC_PCIE_2_PIPE_CLK 67
+#define GCC_PCIE_2_SLV_AXI_CLK 68
+#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 69
+#define GCC_PCIE_MDM_CLKREF_EN 70
+#define GCC_PCIE_PHY_AUX_CLK 71
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72
+#define GCC_PCIE_WIFI_CLKREF_EN 73
+#define GCC_PCIE_WIGIG_CLKREF_EN 74
+#define GCC_PDM2_CLK 75
+#define GCC_PDM2_CLK_SRC 76
+#define GCC_PDM_AHB_CLK 77
+#define GCC_PDM_XO4_CLK 78
+#define GCC_PRNG_AHB_CLK 79
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK 80
+#define GCC_QMIP_CAMERA_RT_AHB_CLK 81
+#define GCC_QMIP_DISP_AHB_CLK 82
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK 83
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 84
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85
+#define GCC_QUPV3_WRAP0_CORE_CLK 86
+#define GCC_QUPV3_WRAP0_S0_CLK 87
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88
+#define GCC_QUPV3_WRAP0_S1_CLK 89
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90
+#define GCC_QUPV3_WRAP0_S2_CLK 91
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92
+#define GCC_QUPV3_WRAP0_S3_CLK 93
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94
+#define GCC_QUPV3_WRAP0_S4_CLK 95
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96
+#define GCC_QUPV3_WRAP0_S5_CLK 97
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98
+#define GCC_QUPV3_WRAP0_S6_CLK 99
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100
+#define GCC_QUPV3_WRAP0_S7_CLK 101
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103
+#define GCC_QUPV3_WRAP1_CORE_CLK 104
+#define GCC_QUPV3_WRAP1_S0_CLK 105
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 106
+#define GCC_QUPV3_WRAP1_S1_CLK 107
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 108
+#define GCC_QUPV3_WRAP1_S2_CLK 109
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 110
+#define GCC_QUPV3_WRAP1_S3_CLK 111
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 112
+#define GCC_QUPV3_WRAP1_S4_CLK 113
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 114
+#define GCC_QUPV3_WRAP1_S5_CLK 115
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 116
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK 117
+#define GCC_QUPV3_WRAP2_CORE_CLK 118
+#define GCC_QUPV3_WRAP2_S0_CLK 119
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC 120
+#define GCC_QUPV3_WRAP2_S1_CLK 121
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC 122
+#define GCC_QUPV3_WRAP2_S2_CLK 123
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC 124
+#define GCC_QUPV3_WRAP2_S3_CLK 125
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC 126
+#define GCC_QUPV3_WRAP2_S4_CLK 127
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC 128
+#define GCC_QUPV3_WRAP2_S5_CLK 129
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC 130
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 131
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 132
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 133
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 134
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK 135
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK 136
+#define GCC_SDCC2_AHB_CLK 137
+#define GCC_SDCC2_APPS_CLK 138
+#define GCC_SDCC2_APPS_CLK_SRC 139
+#define GCC_SDCC4_AHB_CLK 140
+#define GCC_SDCC4_APPS_CLK 141
+#define GCC_SDCC4_APPS_CLK_SRC 142
+#define GCC_SYS_NOC_CPUSS_AHB_CLK 143
+#define GCC_TSIF_AHB_CLK 144
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 145
+#define GCC_TSIF_REF_CLK 146
+#define GCC_TSIF_REF_CLK_SRC 147
+#define GCC_UFS_1X_CLKREF_EN 148
+#define GCC_UFS_CARD_AHB_CLK 149
+#define GCC_UFS_CARD_AXI_CLK 150
+#define GCC_UFS_CARD_AXI_CLK_SRC 151
+#define GCC_UFS_CARD_ICE_CORE_CLK 152
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153
+#define GCC_UFS_CARD_PHY_AUX_CLK 154
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 156
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 157
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK 159
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 160
+#define GCC_UFS_PHY_AHB_CLK 161
+#define GCC_UFS_PHY_AXI_CLK 162
+#define GCC_UFS_PHY_AXI_CLK_SRC 163
+#define GCC_UFS_PHY_ICE_CORE_CLK 164
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 165
+#define GCC_UFS_PHY_PHY_AUX_CLK 166
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 168
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 170
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 171
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 172
+#define GCC_USB30_PRIM_MASTER_CLK 173
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
+#define GCC_USB30_PRIM_SLEEP_CLK 178
+#define GCC_USB30_SEC_MASTER_CLK 179
+#define GCC_USB30_SEC_MASTER_CLK_SRC 180
+#define GCC_USB30_SEC_MOCK_UTMI_CLK 181
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 182
+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 183
+#define GCC_USB30_SEC_SLEEP_CLK 184
+#define GCC_USB3_PRIM_PHY_AUX_CLK 185
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 186
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 187
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 188
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 189
+#define GCC_USB3_SEC_CLKREF_EN 190
+#define GCC_USB3_SEC_PHY_AUX_CLK 191
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 192
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK 193
+#define GCC_USB3_SEC_PHY_PIPE_CLK 194
+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 195
+#define GCC_VIDEO_AHB_CLK 196
+#define GCC_VIDEO_AXI0_CLK 197
+#define GCC_VIDEO_AXI1_CLK 198
+#define GCC_VIDEO_XO_CLK 199
+
+/* GCC resets */
+#define GCC_GPU_BCR 0
+#define GCC_MMSS_BCR 1
+#define GCC_NPU_BWMON_BCR 2
+#define GCC_NPU_BCR 3
+#define GCC_PCIE_0_BCR 4
+#define GCC_PCIE_0_LINK_DOWN_BCR 5
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
+#define GCC_PCIE_0_PHY_BCR 7
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
+#define GCC_PCIE_1_BCR 9
+#define GCC_PCIE_1_LINK_DOWN_BCR 10
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
+#define GCC_PCIE_1_PHY_BCR 12
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
+#define GCC_PCIE_2_BCR 14
+#define GCC_PCIE_2_LINK_DOWN_BCR 15
+#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16
+#define GCC_PCIE_2_PHY_BCR 17
+#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18
+#define GCC_PCIE_PHY_BCR 19
+#define GCC_PCIE_PHY_CFG_AHB_BCR 20
+#define GCC_PCIE_PHY_COM_BCR 21
+#define GCC_PDM_BCR 22
+#define GCC_PRNG_BCR 23
+#define GCC_QUPV3_WRAPPER_0_BCR 24
+#define GCC_QUPV3_WRAPPER_1_BCR 25
+#define GCC_QUPV3_WRAPPER_2_BCR 26
+#define GCC_QUSB2PHY_PRIM_BCR 27
+#define GCC_QUSB2PHY_SEC_BCR 28
+#define GCC_SDCC2_BCR 29
+#define GCC_SDCC4_BCR 30
+#define GCC_TSIF_BCR 31
+#define GCC_UFS_CARD_BCR 32
+#define GCC_UFS_PHY_BCR 33
+#define GCC_USB30_PRIM_BCR 34
+#define GCC_USB30_SEC_BCR 35
+#define GCC_USB3_DP_PHY_PRIM_BCR 36
+#define GCC_USB3_DP_PHY_SEC_BCR 37
+#define GCC_USB3_PHY_PRIM_BCR 38
+#define GCC_USB3_PHY_SEC_BCR 39
+#define GCC_USB3PHY_PHY_PRIM_BCR 40
+#define GCC_USB3PHY_PHY_SEC_BCR 41
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42
+#define GCC_VIDEO_AXI0_CLK_ARES 43
+#define GCC_VIDEO_AXI1_CLK_ARES 44
+
+/* GCC power domains */
+#define PCIE_0_GDSC 0
+#define PCIE_1_GDSC 1
+#define PCIE_2_GDSC 2
+#define UFS_CARD_GDSC 3
+#define UFS_PHY_GDSC 4
+#define USB30_PRIM_GDSC 5
+#define USB30_SEC_GDSC 6
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 10
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7180.h b/include/dt-bindings/clock/qcom,gpucc-sc7180.h
new file mode 100644
index 0000000..65e706d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sc7180.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SC7180_H
+
+#define GPU_CC_PLL1 0
+#define GPU_CC_AHB_CLK 1
+#define GPU_CC_CRC_AHB_CLK 2
+#define GPU_CC_CX_GMU_CLK 3
+#define GPU_CC_CX_SNOC_DVM_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_GMU_CLK_SRC 7
+
+/* GPU_CC GDSCRs */
+#define CX_GDSC 0
+#define GX_GDSC 1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8150.h b/include/dt-bindings/clock/qcom,gpucc-sm8150.h
new file mode 100644
index 0000000..c5b70aa
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm8150.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
+
+/* GPU_CC clock registers */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CRC_AHB_CLK 1
+#define GPU_CC_CX_APB_CLK 2
+#define GPU_CC_CX_GMU_CLK 3
+#define GPU_CC_CX_SNOC_DVM_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_GMU_CLK_SRC 7
+#define GPU_CC_GX_GMU_CLK 8
+#define GPU_CC_PLL1 9
+
+/* GPU_CC Resets */
+#define GPUCC_GPU_CC_CX_BCR 0
+#define GPUCC_GPU_CC_GFX3D_AON_BCR 1
+#define GPUCC_GPU_CC_GMU_BCR 2
+#define GPUCC_GPU_CC_GX_BCR 3
+#define GPUCC_GPU_CC_SPDM_BCR 4
+#define GPUCC_GPU_CC_XO_BCR 5
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC 0
+#define GPU_GX_GDSC 1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8250.h b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
new file mode 100644
index 0000000..dc8e387
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
+
+/* GPU_CC clock registers */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CRC_AHB_CLK 1
+#define GPU_CC_CX_APB_CLK 2
+#define GPU_CC_CX_GMU_CLK 3
+#define GPU_CC_CX_SNOC_DVM_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_GMU_CLK_SRC 7
+#define GPU_CC_GX_GMU_CLK 8
+#define GPU_CC_PLL1 9
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 10
+
+/* GPU_CC Resets */
+#define GPUCC_GPU_CC_ACD_BCR 0
+#define GPUCC_GPU_CC_CX_BCR 1
+#define GPUCC_GPU_CC_GFX3D_AON_BCR 2
+#define GPUCC_GPU_CC_GMU_BCR 3
+#define GPUCC_GPU_CC_GX_BCR 4
+#define GPUCC_GPU_CC_XO_BCR 5
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC 0
+#define GPU_GX_GDSC 1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
new file mode 100644
index 0000000..a55d01d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H
+#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H
+
+/* LPASS_CORE_CC clocks */
+#define LPASS_LPAAUDIO_DIG_PLL 0
+#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1
+#define CORE_CLK_SRC 2
+#define EXT_MCLK0_CLK_SRC 3
+#define LPAIF_PRI_CLK_SRC 4
+#define LPAIF_SEC_CLK_SRC 5
+#define LPASS_AUDIO_CORE_CORE_CLK 6
+#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7
+#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8
+#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9
+#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10
+
+/* LPASS Core power domains */
+#define LPASS_CORE_HM_GDSCR 0
+
+/* LPASS Audio power domains */
+#define LPASS_AUDIO_HM_GDSCR 0
+#define LPASS_PDC_HM_GDSCR 1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8998.h b/include/dt-bindings/clock/qcom,mmcc-msm8998.h
new file mode 100644
index 0000000..ecbafdb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8998.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8998_H
+
+#define MMPLL0 0
+#define MMPLL0_OUT_EVEN 1
+#define MMPLL1 2
+#define MMPLL1_OUT_EVEN 3
+#define MMPLL3 4
+#define MMPLL3_OUT_EVEN 5
+#define MMPLL4 6
+#define MMPLL4_OUT_EVEN 7
+#define MMPLL5 8
+#define MMPLL5_OUT_EVEN 9
+#define MMPLL6 10
+#define MMPLL6_OUT_EVEN 11
+#define MMPLL7 12
+#define MMPLL7_OUT_EVEN 13
+#define MMPLL10 14
+#define MMPLL10_OUT_EVEN 15
+#define BYTE0_CLK_SRC 16
+#define BYTE1_CLK_SRC 17
+#define CCI_CLK_SRC 18
+#define CPP_CLK_SRC 19
+#define CSI0_CLK_SRC 20
+#define CSI1_CLK_SRC 21
+#define CSI2_CLK_SRC 22
+#define CSI3_CLK_SRC 23
+#define CSIPHY_CLK_SRC 24
+#define CSI0PHYTIMER_CLK_SRC 25
+#define CSI1PHYTIMER_CLK_SRC 26
+#define CSI2PHYTIMER_CLK_SRC 27
+#define DP_AUX_CLK_SRC 28
+#define DP_CRYPTO_CLK_SRC 29
+#define DP_LINK_CLK_SRC 30
+#define DP_PIXEL_CLK_SRC 31
+#define ESC0_CLK_SRC 32
+#define ESC1_CLK_SRC 33
+#define EXTPCLK_CLK_SRC 34
+#define FD_CORE_CLK_SRC 35
+#define HDMI_CLK_SRC 36
+#define JPEG0_CLK_SRC 37
+#define MAXI_CLK_SRC 38
+#define MCLK0_CLK_SRC 39
+#define MCLK1_CLK_SRC 40
+#define MCLK2_CLK_SRC 41
+#define MCLK3_CLK_SRC 42
+#define MDP_CLK_SRC 43
+#define VSYNC_CLK_SRC 44
+#define AHB_CLK_SRC 45
+#define AXI_CLK_SRC 46
+#define PCLK0_CLK_SRC 47
+#define PCLK1_CLK_SRC 48
+#define ROT_CLK_SRC 49
+#define VIDEO_CORE_CLK_SRC 50
+#define VIDEO_SUBCORE0_CLK_SRC 51
+#define VIDEO_SUBCORE1_CLK_SRC 52
+#define VFE0_CLK_SRC 53
+#define VFE1_CLK_SRC 54
+#define MISC_AHB_CLK 55
+#define VIDEO_CORE_CLK 56
+#define VIDEO_AHB_CLK 57
+#define VIDEO_AXI_CLK 58
+#define VIDEO_MAXI_CLK 59
+#define VIDEO_SUBCORE0_CLK 60
+#define VIDEO_SUBCORE1_CLK 61
+#define MDSS_AHB_CLK 62
+#define MDSS_HDMI_DP_AHB_CLK 63
+#define MDSS_AXI_CLK 64
+#define MDSS_PCLK0_CLK 65
+#define MDSS_PCLK1_CLK 66
+#define MDSS_MDP_CLK 67
+#define MDSS_MDP_LUT_CLK 68
+#define MDSS_EXTPCLK_CLK 69
+#define MDSS_VSYNC_CLK 70
+#define MDSS_HDMI_CLK 71
+#define MDSS_BYTE0_CLK 72
+#define MDSS_BYTE1_CLK 73
+#define MDSS_ESC0_CLK 74
+#define MDSS_ESC1_CLK 75
+#define MDSS_ROT_CLK 76
+#define MDSS_DP_LINK_CLK 77
+#define MDSS_DP_LINK_INTF_CLK 78
+#define MDSS_DP_CRYPTO_CLK 79
+#define MDSS_DP_PIXEL_CLK 80
+#define MDSS_DP_AUX_CLK 81
+#define MDSS_BYTE0_INTF_CLK 82
+#define MDSS_BYTE1_INTF_CLK 83
+#define CAMSS_CSI0PHYTIMER_CLK 84
+#define CAMSS_CSI1PHYTIMER_CLK 85
+#define CAMSS_CSI2PHYTIMER_CLK 86
+#define CAMSS_CSI0_CLK 87
+#define CAMSS_CSI0_AHB_CLK 88
+#define CAMSS_CSI0RDI_CLK 89
+#define CAMSS_CSI0PIX_CLK 90
+#define CAMSS_CSI1_CLK 91
+#define CAMSS_CSI1_AHB_CLK 92
+#define CAMSS_CSI1RDI_CLK 93
+#define CAMSS_CSI1PIX_CLK 94
+#define CAMSS_CSI2_CLK 95
+#define CAMSS_CSI2_AHB_CLK 96
+#define CAMSS_CSI2RDI_CLK 97
+#define CAMSS_CSI2PIX_CLK 98
+#define CAMSS_CSI3_CLK 99
+#define CAMSS_CSI3_AHB_CLK 100
+#define CAMSS_CSI3RDI_CLK 101
+#define CAMSS_CSI3PIX_CLK 102
+#define CAMSS_ISPIF_AHB_CLK 103
+#define CAMSS_CCI_CLK 104
+#define CAMSS_CCI_AHB_CLK 105
+#define CAMSS_MCLK0_CLK 106
+#define CAMSS_MCLK1_CLK 107
+#define CAMSS_MCLK2_CLK 108
+#define CAMSS_MCLK3_CLK 109
+#define CAMSS_TOP_AHB_CLK 110
+#define CAMSS_AHB_CLK 111
+#define CAMSS_MICRO_AHB_CLK 112
+#define CAMSS_JPEG0_CLK 113
+#define CAMSS_JPEG_AHB_CLK 114
+#define CAMSS_JPEG_AXI_CLK 115
+#define CAMSS_VFE0_AHB_CLK 116
+#define CAMSS_VFE1_AHB_CLK 117
+#define CAMSS_VFE0_CLK 118
+#define CAMSS_VFE1_CLK 119
+#define CAMSS_CPP_CLK 120
+#define CAMSS_CPP_AHB_CLK 121
+#define CAMSS_VFE_VBIF_AHB_CLK 122
+#define CAMSS_VFE_VBIF_AXI_CLK 123
+#define CAMSS_CPP_AXI_CLK 124
+#define CAMSS_CPP_VBIF_AHB_CLK 125
+#define CAMSS_CSI_VFE0_CLK 126
+#define CAMSS_CSI_VFE1_CLK 127
+#define CAMSS_VFE0_STREAM_CLK 128
+#define CAMSS_VFE1_STREAM_CLK 129
+#define CAMSS_CPHY_CSID0_CLK 130
+#define CAMSS_CPHY_CSID1_CLK 131
+#define CAMSS_CPHY_CSID2_CLK 132
+#define CAMSS_CPHY_CSID3_CLK 133
+#define CAMSS_CSIPHY0_CLK 134
+#define CAMSS_CSIPHY1_CLK 135
+#define CAMSS_CSIPHY2_CLK 136
+#define FD_CORE_CLK 137
+#define FD_CORE_UAR_CLK 138
+#define FD_AHB_CLK 139
+#define MNOC_AHB_CLK 140
+#define BIMC_SMMU_AHB_CLK 141
+#define BIMC_SMMU_AXI_CLK 142
+#define MNOC_MAXI_CLK 143
+#define VMEM_MAXI_CLK 144
+#define VMEM_AHB_CLK 145
+
+#define SPDM_BCR 0
+#define SPDM_RM_BCR 1
+#define MISC_BCR 2
+#define VIDEO_TOP_BCR 3
+#define THROTTLE_VIDEO_BCR 4
+#define MDSS_BCR 5
+#define THROTTLE_MDSS_BCR 6
+#define CAMSS_PHY0_BCR 7
+#define CAMSS_PHY1_BCR 8
+#define CAMSS_PHY2_BCR 9
+#define CAMSS_CSI0_BCR 10
+#define CAMSS_CSI0RDI_BCR 11
+#define CAMSS_CSI0PIX_BCR 12
+#define CAMSS_CSI1_BCR 13
+#define CAMSS_CSI1RDI_BCR 14
+#define CAMSS_CSI1PIX_BCR 15
+#define CAMSS_CSI2_BCR 16
+#define CAMSS_CSI2RDI_BCR 17
+#define CAMSS_CSI2PIX_BCR 18
+#define CAMSS_CSI3_BCR 19
+#define CAMSS_CSI3RDI_BCR 20
+#define CAMSS_CSI3PIX_BCR 21
+#define CAMSS_ISPIF_BCR 22
+#define CAMSS_CCI_BCR 23
+#define CAMSS_TOP_BCR 24
+#define CAMSS_AHB_BCR 25
+#define CAMSS_MICRO_BCR 26
+#define CAMSS_JPEG_BCR 27
+#define CAMSS_VFE0_BCR 28
+#define CAMSS_VFE1_BCR 29
+#define CAMSS_VFE_VBIF_BCR 30
+#define CAMSS_CPP_TOP_BCR 31
+#define CAMSS_CPP_BCR 32
+#define CAMSS_CSI_VFE0_BCR 33
+#define CAMSS_CSI_VFE1_BCR 34
+#define CAMSS_FD_BCR 35
+#define THROTTLE_CAMSS_BCR 36
+#define MNOCAHB_BCR 37
+#define MNOCAXI_BCR 38
+#define BMIC_SMMU_BCR 39
+#define MNOC_MAXI_BCR 40
+#define VMEM_BCR 41
+#define BTO_BCR 42
+
+#define VIDEO_TOP_GDSC 1
+#define VIDEO_SUBCORE0_GDSC 2
+#define VIDEO_SUBCORE1_GDSC 3
+#define MDSS_GDSC 4
+#define CAMSS_TOP_GDSC 5
+#define CAMSS_VFE0_GDSC 6
+#define CAMSS_VFE1_GDSC 7
+#define CAMSS_CPP_GDSC 8
+#define BIMC_SMMU_GDSC 9
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,mss-sc7180.h b/include/dt-bindings/clock/qcom,mss-sc7180.h
new file mode 100644
index 0000000..f15a9de
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mss-sc7180.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H
+#define _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H
+
+#define MSS_AXI_CRYPTO_CLK 0
+#define MSS_AXI_NAV_CLK 1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h b/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h
new file mode 100644
index 0000000..c6f5290
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H
+#define _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H
+
+#define LCC_AHBFABRIC_CBC_CLK 0
+#define LCC_Q6SS_AHBS_CBC_CLK 1
+#define LCC_Q6SS_TCM_SLAVE_CBC_CLK 2
+#define LCC_Q6SS_AHBM_CBC_CLK 3
+#define LCC_Q6SS_AXIM_CBC_CLK 4
+#define LCC_Q6SS_BCR_SLEEP_CLK 5
+#define TCSR_Q6SS_LCC_CBCR_CLK 6
+
+#define Q6SSTOP_BCR_RESET 1
+#endif
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 8e30957..8aaba7c 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -37,6 +37,10 @@
#define RPM_XO_A0 27
#define RPM_XO_A1 28
#define RPM_XO_A2 29
+#define RPM_NSS_FABRIC_0_CLK 30
+#define RPM_NSS_FABRIC_0_A_CLK 31
+#define RPM_NSS_FABRIC_1_CLK 32
+#define RPM_NSS_FABRIC_1_A_CLK 33
/* SMD RPM clocks */
#define RPM_SMD_XO_CLK_SRC 0
@@ -129,5 +133,21 @@
#define RPM_SMD_RF_CLK3_A 87
#define RPM_SMD_RF_CLK3_PIN 88
#define RPM_SMD_RF_CLK3_A_PIN 89
+#define RPM_SMD_MMSSNOC_AXI_CLK 90
+#define RPM_SMD_MMSSNOC_AXI_CLK_A 91
+#define RPM_SMD_CNOC_PERIPH_CLK 92
+#define RPM_SMD_CNOC_PERIPH_A_CLK 93
+#define RPM_SMD_LN_BB_CLK3 94
+#define RPM_SMD_LN_BB_CLK3_A 95
+#define RPM_SMD_LN_BB_CLK1_PIN 96
+#define RPM_SMD_LN_BB_CLK1_A_PIN 97
+#define RPM_SMD_LN_BB_CLK2_PIN 98
+#define RPM_SMD_LN_BB_CLK2_A_PIN 99
+#define RPM_SMD_SYSMMNOC_CLK 100
+#define RPM_SMD_SYSMMNOC_A_CLK 101
+#define RPM_SMD_CE2_CLK 102
+#define RPM_SMD_CE2_A_CLK 103
+#define RPM_SMD_CE3_CLK 104
+#define RPM_SMD_CE3_A_CLK 105
#endif
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
index edcab3f..2e6c54e 100644
--- a/include/dt-bindings/clock/qcom,rpmh.h
+++ b/include/dt-bindings/clock/qcom,rpmh.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */
#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
@@ -19,5 +19,7 @@
#define RPMH_RF_CLK3 10
#define RPMH_RF_CLK3_A 11
#define RPMH_IPA_CLK 12
+#define RPMH_LN_BB_CLK1 13
+#define RPMH_LN_BB_CLK1_A 14
#endif
diff --git a/include/dt-bindings/clock/qcom,videocc-sc7180.h b/include/dt-bindings/clock/qcom,videocc-sc7180.h
new file mode 100644
index 0000000..7acaf13
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sc7180.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SC7180_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_PLL0 0
+#define VIDEO_CC_VCODEC0_AXI_CLK 1
+#define VIDEO_CC_VCODEC0_CORE_CLK 2
+#define VIDEO_CC_VENUS_AHB_CLK 3
+#define VIDEO_CC_VENUS_CLK_SRC 4
+#define VIDEO_CC_VENUS_CTL_AXI_CLK 5
+#define VIDEO_CC_VENUS_CTL_CORE_CLK 6
+#define VIDEO_CC_XO_CLK 7
+
+/* VIDEO_CC GDSCRs */
+#define VENUS_GDSC 0
+#define VCODEC0_GDSC 1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,videocc-sm8150.h b/include/dt-bindings/clock/qcom,videocc-sm8150.h
new file mode 100644
index 0000000..e24ee84
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sm8150.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_IRIS_AHB_CLK 0
+#define VIDEO_CC_IRIS_CLK_SRC 1
+#define VIDEO_CC_MVS0_CORE_CLK 2
+#define VIDEO_CC_MVS1_CORE_CLK 3
+#define VIDEO_CC_MVSC_CORE_CLK 4
+#define VIDEO_CC_PLL0 5
+
+/* VIDEO_CC Resets */
+#define VIDEO_CC_MVSC_CORE_CLK_BCR 0
+
+/* VIDEO_CC GDSCRs */
+#define VENUS_GDSC 0
+#define VCODEC0_GDSC 1
+#define VCODEC1_GDSC 2
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,videocc-sm8250.h b/include/dt-bindings/clock/qcom,videocc-sm8250.h
new file mode 100644
index 0000000..2b2b386
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sm8250.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_MVS0_CLK_SRC 0
+#define VIDEO_CC_MVS0C_CLK 1
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 2
+#define VIDEO_CC_MVS1_CLK_SRC 3
+#define VIDEO_CC_MVS1_DIV2_CLK 4
+#define VIDEO_CC_MVS1C_CLK 5
+#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 6
+#define VIDEO_CC_PLL0 7
+#define VIDEO_CC_PLL1 8
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_CVP_INTERFACE_BCR 0
+#define VIDEO_CC_CVP_MVS0_BCR 1
+#define VIDEO_CC_MVS0C_CLK_ARES 2
+#define VIDEO_CC_CVP_MVS0C_BCR 3
+#define VIDEO_CC_CVP_MVS1_BCR 4
+#define VIDEO_CC_MVS1C_CLK_ARES 5
+#define VIDEO_CC_CVP_MVS1C_BCR 6
+
+#define MVS0C_GDSC 0
+#define MVS1C_GDSC 1
+#define MVS0_GDSC 2
+#define MVS1_GDSC 3
+
+#endif
diff --git a/include/dt-bindings/clock/r8a7742-cpg-mssr.h b/include/dt-bindings/clock/r8a7742-cpg-mssr.h
new file mode 100644
index 0000000..e68191c
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7742-cpg-mssr.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7742 CPG Core Clocks */
+#define R8A7742_CLK_Z 0
+#define R8A7742_CLK_Z2 1
+#define R8A7742_CLK_ZG 2
+#define R8A7742_CLK_ZTR 3
+#define R8A7742_CLK_ZTRD2 4
+#define R8A7742_CLK_ZT 5
+#define R8A7742_CLK_ZX 6
+#define R8A7742_CLK_ZS 7
+#define R8A7742_CLK_HP 8
+#define R8A7742_CLK_B 9
+#define R8A7742_CLK_LB 10
+#define R8A7742_CLK_P 11
+#define R8A7742_CLK_CL 12
+#define R8A7742_CLK_M2 13
+#define R8A7742_CLK_ZB3 14
+#define R8A7742_CLK_ZB3D2 15
+#define R8A7742_CLK_DDR 16
+#define R8A7742_CLK_SDH 17
+#define R8A7742_CLK_SD0 18
+#define R8A7742_CLK_SD1 19
+#define R8A7742_CLK_SD2 20
+#define R8A7742_CLK_SD3 21
+#define R8A7742_CLK_MMC0 22
+#define R8A7742_CLK_MMC1 23
+#define R8A7742_CLK_MP 24
+#define R8A7742_CLK_QSPI 25
+#define R8A7742_CLK_CP 26
+#define R8A7742_CLK_RCAN 27
+#define R8A7742_CLK_R 28
+#define R8A7742_CLK_OSC 29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h
new file mode 100644
index 0000000..1355451
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a774b1 CPG Core Clocks */
+#define R8A774B1_CLK_Z 0
+#define R8A774B1_CLK_ZG 1
+#define R8A774B1_CLK_ZTR 2
+#define R8A774B1_CLK_ZTRD2 3
+#define R8A774B1_CLK_ZT 4
+#define R8A774B1_CLK_ZX 5
+#define R8A774B1_CLK_S0D1 6
+#define R8A774B1_CLK_S0D2 7
+#define R8A774B1_CLK_S0D3 8
+#define R8A774B1_CLK_S0D4 9
+#define R8A774B1_CLK_S0D6 10
+#define R8A774B1_CLK_S0D8 11
+#define R8A774B1_CLK_S0D12 12
+#define R8A774B1_CLK_S1D2 13
+#define R8A774B1_CLK_S1D4 14
+#define R8A774B1_CLK_S2D1 15
+#define R8A774B1_CLK_S2D2 16
+#define R8A774B1_CLK_S2D4 17
+#define R8A774B1_CLK_S3D1 18
+#define R8A774B1_CLK_S3D2 19
+#define R8A774B1_CLK_S3D4 20
+#define R8A774B1_CLK_LB 21
+#define R8A774B1_CLK_CL 22
+#define R8A774B1_CLK_ZB3 23
+#define R8A774B1_CLK_ZB3D2 24
+#define R8A774B1_CLK_CR 25
+#define R8A774B1_CLK_DDR 26
+#define R8A774B1_CLK_SD0H 27
+#define R8A774B1_CLK_SD0 28
+#define R8A774B1_CLK_SD1H 29
+#define R8A774B1_CLK_SD1 30
+#define R8A774B1_CLK_SD2H 31
+#define R8A774B1_CLK_SD2 32
+#define R8A774B1_CLK_SD3H 33
+#define R8A774B1_CLK_SD3 34
+#define R8A774B1_CLK_RPC 35
+#define R8A774B1_CLK_RPCD2 36
+#define R8A774B1_CLK_MSO 37
+#define R8A774B1_CLK_HDMI 38
+#define R8A774B1_CLK_CSI0 39
+#define R8A774B1_CLK_CP 40
+#define R8A774B1_CLK_CPEX 41
+#define R8A774B1_CLK_R 42
+#define R8A774B1_CLK_OSC 43
+#define R8A774B1_CLK_CANFD 44
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h
new file mode 100644
index 0000000..b2fc1d1
--- /dev/null
+++ b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R8A774E1 CPG Core Clocks */
+#define R8A774E1_CLK_Z 0
+#define R8A774E1_CLK_Z2 1
+#define R8A774E1_CLK_ZG 2
+#define R8A774E1_CLK_ZTR 3
+#define R8A774E1_CLK_ZTRD2 4
+#define R8A774E1_CLK_ZT 5
+#define R8A774E1_CLK_ZX 6
+#define R8A774E1_CLK_S0D1 7
+#define R8A774E1_CLK_S0D2 8
+#define R8A774E1_CLK_S0D3 9
+#define R8A774E1_CLK_S0D4 10
+#define R8A774E1_CLK_S0D6 11
+#define R8A774E1_CLK_S0D8 12
+#define R8A774E1_CLK_S0D12 13
+#define R8A774E1_CLK_S1D2 14
+#define R8A774E1_CLK_S1D4 15
+#define R8A774E1_CLK_S2D1 16
+#define R8A774E1_CLK_S2D2 17
+#define R8A774E1_CLK_S2D4 18
+#define R8A774E1_CLK_S3D1 19
+#define R8A774E1_CLK_S3D2 20
+#define R8A774E1_CLK_S3D4 21
+#define R8A774E1_CLK_LB 22
+#define R8A774E1_CLK_CL 23
+#define R8A774E1_CLK_ZB3 24
+#define R8A774E1_CLK_ZB3D2 25
+#define R8A774E1_CLK_ZB3D4 26
+#define R8A774E1_CLK_CR 27
+#define R8A774E1_CLK_CRD2 28
+#define R8A774E1_CLK_SD0H 29
+#define R8A774E1_CLK_SD0 30
+#define R8A774E1_CLK_SD1H 31
+#define R8A774E1_CLK_SD1 32
+#define R8A774E1_CLK_SD2H 33
+#define R8A774E1_CLK_SD2 34
+#define R8A774E1_CLK_SD3H 35
+#define R8A774E1_CLK_SD3 36
+#define R8A774E1_CLK_RPC 37
+#define R8A774E1_CLK_RPCD2 38
+#define R8A774E1_CLK_MSO 39
+#define R8A774E1_CLK_HDMI 40
+#define R8A774E1_CLK_CSI0 41
+#define R8A774E1_CLK_CP 42
+#define R8A774E1_CLK_CPEX 43
+#define R8A774E1_CLK_R 44
+#define R8A774E1_CLK_OSC 45
+#define R8A774E1_CLK_CANFD 46
+
+#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77961-cpg-mssr.h b/include/dt-bindings/clock/r8a77961-cpg-mssr.h
new file mode 100644
index 0000000..7921d78
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77961-cpg-mssr.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77961 CPG Core Clocks */
+#define R8A77961_CLK_Z 0
+#define R8A77961_CLK_Z2 1
+#define R8A77961_CLK_ZR 2
+#define R8A77961_CLK_ZG 3
+#define R8A77961_CLK_ZTR 4
+#define R8A77961_CLK_ZTRD2 5
+#define R8A77961_CLK_ZT 6
+#define R8A77961_CLK_ZX 7
+#define R8A77961_CLK_S0D1 8
+#define R8A77961_CLK_S0D2 9
+#define R8A77961_CLK_S0D3 10
+#define R8A77961_CLK_S0D4 11
+#define R8A77961_CLK_S0D6 12
+#define R8A77961_CLK_S0D8 13
+#define R8A77961_CLK_S0D12 14
+#define R8A77961_CLK_S1D1 15
+#define R8A77961_CLK_S1D2 16
+#define R8A77961_CLK_S1D4 17
+#define R8A77961_CLK_S2D1 18
+#define R8A77961_CLK_S2D2 19
+#define R8A77961_CLK_S2D4 20
+#define R8A77961_CLK_S3D1 21
+#define R8A77961_CLK_S3D2 22
+#define R8A77961_CLK_S3D4 23
+#define R8A77961_CLK_LB 24
+#define R8A77961_CLK_CL 25
+#define R8A77961_CLK_ZB3 26
+#define R8A77961_CLK_ZB3D2 27
+#define R8A77961_CLK_ZB3D4 28
+#define R8A77961_CLK_CR 29
+#define R8A77961_CLK_CRD2 30
+#define R8A77961_CLK_SD0H 31
+#define R8A77961_CLK_SD0 32
+#define R8A77961_CLK_SD1H 33
+#define R8A77961_CLK_SD1 34
+#define R8A77961_CLK_SD2H 35
+#define R8A77961_CLK_SD2 36
+#define R8A77961_CLK_SD3H 37
+#define R8A77961_CLK_SD3 38
+#define R8A77961_CLK_SSP2 39
+#define R8A77961_CLK_SSP1 40
+#define R8A77961_CLK_SSPRS 41
+#define R8A77961_CLK_RPC 42
+#define R8A77961_CLK_RPCD2 43
+#define R8A77961_CLK_MSO 44
+#define R8A77961_CLK_CANFD 45
+#define R8A77961_CLK_HDMI 46
+#define R8A77961_CLK_CSI0 47
+/* CLK_CSIREF was removed */
+#define R8A77961_CLK_CP 49
+#define R8A77961_CLK_CPEX 50
+#define R8A77961_CLK_R 51
+#define R8A77961_CLK_OSC 52
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
new file mode 100644
index 0000000..f1d737c
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779A0 CPG Core Clocks */
+#define R8A779A0_CLK_Z0 0
+#define R8A779A0_CLK_ZX 1
+#define R8A779A0_CLK_Z1 2
+#define R8A779A0_CLK_ZR 3
+#define R8A779A0_CLK_ZS 4
+#define R8A779A0_CLK_ZT 5
+#define R8A779A0_CLK_ZTR 6
+#define R8A779A0_CLK_S1D1 7
+#define R8A779A0_CLK_S1D2 8
+#define R8A779A0_CLK_S1D4 9
+#define R8A779A0_CLK_S1D8 10
+#define R8A779A0_CLK_S1D12 11
+#define R8A779A0_CLK_S3D1 12
+#define R8A779A0_CLK_S3D2 13
+#define R8A779A0_CLK_S3D4 14
+#define R8A779A0_CLK_LB 15
+#define R8A779A0_CLK_CP 16
+#define R8A779A0_CLK_CL 17
+#define R8A779A0_CLK_CL16MCK 18
+#define R8A779A0_CLK_ZB30 19
+#define R8A779A0_CLK_ZB30D2 20
+#define R8A779A0_CLK_ZB30D4 21
+#define R8A779A0_CLK_ZB31 22
+#define R8A779A0_CLK_ZB31D2 23
+#define R8A779A0_CLK_ZB31D4 24
+#define R8A779A0_CLK_SD0H 25
+#define R8A779A0_CLK_SD0 26
+#define R8A779A0_CLK_RPC 27
+#define R8A779A0_CLK_RPCD2 28
+#define R8A779A0_CLK_MSO 29
+#define R8A779A0_CLK_CANFD 30
+#define R8A779A0_CLK_CSI0 31
+#define R8A779A0_CLK_FRAY 32
+#define R8A779A0_CLK_DSI 33
+#define R8A779A0_CLK_VIP 34
+#define R8A779A0_CLK_ADGH 35
+#define R8A779A0_CLK_CNNDSP 36
+#define R8A779A0_CLK_ICU 37
+#define R8A779A0_CLK_ICUD2 38
+#define R8A779A0_CLK_VCBUS 39
+#define R8A779A0_CLK_CBFUSA 40
+#define R8A779A0_CLK_R 41
+#define R8A779A0_CLK_OSC 42
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/sprd,sc9863a-clk.h b/include/dt-bindings/clock/sprd,sc9863a-clk.h
new file mode 100644
index 0000000..4e03042
--- /dev/null
+++ b/include/dt-bindings/clock/sprd,sc9863a-clk.h
@@ -0,0 +1,339 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Unisoc SC9863A platform clocks
+ *
+ * Copyright (C) 2019, Unisoc Communications Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SC9863A_H_
+#define _DT_BINDINGS_CLK_SC9863A_H_
+
+#define CLK_MPLL0_GATE 0
+#define CLK_DPLL0_GATE 1
+#define CLK_LPLL_GATE 2
+#define CLK_GPLL_GATE 3
+#define CLK_DPLL1_GATE 4
+#define CLK_MPLL1_GATE 5
+#define CLK_MPLL2_GATE 6
+#define CLK_ISPPLL_GATE 7
+#define CLK_PMU_APB_NUM (CLK_ISPPLL_GATE + 1)
+
+#define CLK_AUDIO_GATE 0
+#define CLK_RPLL 1
+#define CLK_RPLL_390M 2
+#define CLK_RPLL_260M 3
+#define CLK_RPLL_195M 4
+#define CLK_RPLL_26M 5
+#define CLK_ANLG_PHY_G5_NUM (CLK_RPLL_26M + 1)
+
+#define CLK_TWPLL 0
+#define CLK_TWPLL_768M 1
+#define CLK_TWPLL_384M 2
+#define CLK_TWPLL_192M 3
+#define CLK_TWPLL_96M 4
+#define CLK_TWPLL_48M 5
+#define CLK_TWPLL_24M 6
+#define CLK_TWPLL_12M 7
+#define CLK_TWPLL_512M 8
+#define CLK_TWPLL_256M 9
+#define CLK_TWPLL_128M 10
+#define CLK_TWPLL_64M 11
+#define CLK_TWPLL_307M2 12
+#define CLK_TWPLL_219M4 13
+#define CLK_TWPLL_170M6 14
+#define CLK_TWPLL_153M6 15
+#define CLK_TWPLL_76M8 16
+#define CLK_TWPLL_51M2 17
+#define CLK_TWPLL_38M4 18
+#define CLK_TWPLL_19M2 19
+#define CLK_LPLL 20
+#define CLK_LPLL_409M6 21
+#define CLK_LPLL_245M76 22
+#define CLK_GPLL 23
+#define CLK_ISPPLL 24
+#define CLK_ISPPLL_468M 25
+#define CLK_ANLG_PHY_G1_NUM (CLK_ISPPLL_468M + 1)
+
+#define CLK_DPLL0 0
+#define CLK_DPLL1 1
+#define CLK_DPLL0_933M 2
+#define CLK_DPLL0_622M3 3
+#define CLK_DPLL0_400M 4
+#define CLK_DPLL0_266M7 5
+#define CLK_DPLL0_123M1 6
+#define CLK_DPLL0_50M 7
+#define CLK_ANLG_PHY_G7_NUM (CLK_DPLL0_50M + 1)
+
+#define CLK_MPLL0 0
+#define CLK_MPLL1 1
+#define CLK_MPLL2 2
+#define CLK_MPLL2_675M 3
+#define CLK_ANLG_PHY_G4_NUM (CLK_MPLL2_675M + 1)
+
+#define CLK_AP_APB 0
+#define CLK_AP_CE 1
+#define CLK_NANDC_ECC 2
+#define CLK_NANDC_26M 3
+#define CLK_EMMC_32K 4
+#define CLK_SDIO0_32K 5
+#define CLK_SDIO1_32K 6
+#define CLK_SDIO2_32K 7
+#define CLK_OTG_UTMI 8
+#define CLK_AP_UART0 9
+#define CLK_AP_UART1 10
+#define CLK_AP_UART2 11
+#define CLK_AP_UART3 12
+#define CLK_AP_UART4 13
+#define CLK_AP_I2C0 14
+#define CLK_AP_I2C1 15
+#define CLK_AP_I2C2 16
+#define CLK_AP_I2C3 17
+#define CLK_AP_I2C4 18
+#define CLK_AP_I2C5 19
+#define CLK_AP_I2C6 20
+#define CLK_AP_SPI0 21
+#define CLK_AP_SPI1 22
+#define CLK_AP_SPI2 23
+#define CLK_AP_SPI3 24
+#define CLK_AP_IIS0 25
+#define CLK_AP_IIS1 26
+#define CLK_AP_IIS2 27
+#define CLK_SIM0 28
+#define CLK_SIM0_32K 29
+#define CLK_AP_CLK_NUM (CLK_SIM0_32K + 1)
+
+#define CLK_13M 0
+#define CLK_6M5 1
+#define CLK_4M3 2
+#define CLK_2M 3
+#define CLK_250K 4
+#define CLK_RCO_25M 5
+#define CLK_RCO_4M 6
+#define CLK_RCO_2M 7
+#define CLK_EMC 8
+#define CLK_AON_APB 9
+#define CLK_ADI 10
+#define CLK_AUX0 11
+#define CLK_AUX1 12
+#define CLK_AUX2 13
+#define CLK_PROBE 14
+#define CLK_PWM0 15
+#define CLK_PWM1 16
+#define CLK_PWM2 17
+#define CLK_AON_THM 18
+#define CLK_AUDIF 19
+#define CLK_CPU_DAP 20
+#define CLK_CPU_TS 21
+#define CLK_DJTAG_TCK 22
+#define CLK_EMC_REF 23
+#define CLK_CSSYS 24
+#define CLK_AON_PMU 25
+#define CLK_PMU_26M 26
+#define CLK_AON_TMR 27
+#define CLK_POWER_CPU 28
+#define CLK_AP_AXI 29
+#define CLK_SDIO0_2X 30
+#define CLK_SDIO1_2X 31
+#define CLK_SDIO2_2X 32
+#define CLK_EMMC_2X 33
+#define CLK_DPU 34
+#define CLK_DPU_DPI 35
+#define CLK_OTG_REF 36
+#define CLK_SDPHY_APB 37
+#define CLK_ALG_IO_APB 38
+#define CLK_GPU_CORE 39
+#define CLK_GPU_SOC 40
+#define CLK_MM_EMC 41
+#define CLK_MM_AHB 42
+#define CLK_BPC 43
+#define CLK_DCAM_IF 44
+#define CLK_ISP 45
+#define CLK_JPG 46
+#define CLK_CPP 47
+#define CLK_SENSOR0 48
+#define CLK_SENSOR1 49
+#define CLK_SENSOR2 50
+#define CLK_MM_VEMC 51
+#define CLK_MM_VAHB 52
+#define CLK_VSP 53
+#define CLK_CORE0 54
+#define CLK_CORE1 55
+#define CLK_CORE2 56
+#define CLK_CORE3 57
+#define CLK_CORE4 58
+#define CLK_CORE5 59
+#define CLK_CORE6 60
+#define CLK_CORE7 61
+#define CLK_SCU 62
+#define CLK_ACE 63
+#define CLK_AXI_PERIPH 64
+#define CLK_AXI_ACP 65
+#define CLK_ATB 66
+#define CLK_DEBUG_APB 67
+#define CLK_GIC 68
+#define CLK_PERIPH 69
+#define CLK_AON_CLK_NUM (CLK_VSP + 1)
+
+#define CLK_OTG_EB 0
+#define CLK_DMA_EB 1
+#define CLK_CE_EB 2
+#define CLK_NANDC_EB 3
+#define CLK_SDIO0_EB 4
+#define CLK_SDIO1_EB 5
+#define CLK_SDIO2_EB 6
+#define CLK_EMMC_EB 7
+#define CLK_EMMC_32K_EB 8
+#define CLK_SDIO0_32K_EB 9
+#define CLK_SDIO1_32K_EB 10
+#define CLK_SDIO2_32K_EB 11
+#define CLK_NANDC_26M_EB 12
+#define CLK_DMA_EB2 13
+#define CLK_CE_EB2 14
+#define CLK_AP_AHB_GATE_NUM (CLK_CE_EB2 + 1)
+
+#define CLK_GPIO_EB 0
+#define CLK_PWM0_EB 1
+#define CLK_PWM1_EB 2
+#define CLK_PWM2_EB 3
+#define CLK_PWM3_EB 4
+#define CLK_KPD_EB 5
+#define CLK_AON_SYST_EB 6
+#define CLK_AP_SYST_EB 7
+#define CLK_AON_TMR_EB 8
+#define CLK_EFUSE_EB 9
+#define CLK_EIC_EB 10
+#define CLK_INTC_EB 11
+#define CLK_ADI_EB 12
+#define CLK_AUDIF_EB 13
+#define CLK_AUD_EB 14
+#define CLK_VBC_EB 15
+#define CLK_PIN_EB 16
+#define CLK_AP_WDG_EB 17
+#define CLK_MM_EB 18
+#define CLK_AON_APB_CKG_EB 19
+#define CLK_CA53_TS0_EB 20
+#define CLK_CA53_TS1_EB 21
+#define CLK_CS53_DAP_EB 22
+#define CLK_PMU_EB 23
+#define CLK_THM_EB 24
+#define CLK_AUX0_EB 25
+#define CLK_AUX1_EB 26
+#define CLK_AUX2_EB 27
+#define CLK_PROBE_EB 28
+#define CLK_EMC_REF_EB 29
+#define CLK_CA53_WDG_EB 30
+#define CLK_AP_TMR1_EB 31
+#define CLK_AP_TMR2_EB 32
+#define CLK_DISP_EMC_EB 33
+#define CLK_ZIP_EMC_EB 34
+#define CLK_GSP_EMC_EB 35
+#define CLK_MM_VSP_EB 36
+#define CLK_MDAR_EB 37
+#define CLK_RTC4M0_CAL_EB 38
+#define CLK_RTC4M1_CAL_EB 39
+#define CLK_DJTAG_EB 40
+#define CLK_MBOX_EB 41
+#define CLK_AON_DMA_EB 42
+#define CLK_AON_APB_DEF_EB 43
+#define CLK_CA5_TS0_EB 44
+#define CLK_DBG_EB 45
+#define CLK_DBG_EMC_EB 46
+#define CLK_CROSS_TRIG_EB 47
+#define CLK_SERDES_DPHY_EB 48
+#define CLK_ARCH_RTC_EB 49
+#define CLK_KPD_RTC_EB 50
+#define CLK_AON_SYST_RTC_EB 51
+#define CLK_AP_SYST_RTC_EB 52
+#define CLK_AON_TMR_RTC_EB 53
+#define CLK_AP_TMR0_RTC_EB 54
+#define CLK_EIC_RTC_EB 55
+#define CLK_EIC_RTCDV5_EB 56
+#define CLK_AP_WDG_RTC_EB 57
+#define CLK_CA53_WDG_RTC_EB 58
+#define CLK_THM_RTC_EB 59
+#define CLK_ATHMA_RTC_EB 60
+#define CLK_GTHMA_RTC_EB 61
+#define CLK_ATHMA_RTC_A_EB 62
+#define CLK_GTHMA_RTC_A_EB 63
+#define CLK_AP_TMR1_RTC_EB 64
+#define CLK_AP_TMR2_RTC_EB 65
+#define CLK_DXCO_LC_RTC_EB 66
+#define CLK_BB_CAL_RTC_EB 67
+#define CLK_GNU_EB 68
+#define CLK_DISP_EB 69
+#define CLK_MM_EMC_EB 70
+#define CLK_POWER_CPU_EB 71
+#define CLK_HW_I2C_EB 72
+#define CLK_MM_VSP_EMC_EB 73
+#define CLK_VSP_EB 74
+#define CLK_CSSYS_EB 75
+#define CLK_DMC_EB 76
+#define CLK_ROSC_EB 77
+#define CLK_S_D_CFG_EB 78
+#define CLK_S_D_REF_EB 79
+#define CLK_B_DMA_EB 80
+#define CLK_ANLG_EB 81
+#define CLK_ANLG_APB_EB 82
+#define CLK_BSMTMR_EB 83
+#define CLK_AP_AXI_EB 84
+#define CLK_AP_INTC0_EB 85
+#define CLK_AP_INTC1_EB 86
+#define CLK_AP_INTC2_EB 87
+#define CLK_AP_INTC3_EB 88
+#define CLK_AP_INTC4_EB 89
+#define CLK_AP_INTC5_EB 90
+#define CLK_SCC_EB 91
+#define CLK_DPHY_CFG_EB 92
+#define CLK_DPHY_REF_EB 93
+#define CLK_CPHY_CFG_EB 94
+#define CLK_OTG_REF_EB 95
+#define CLK_SERDES_EB 96
+#define CLK_AON_AP_EMC_EB 97
+#define CLK_AON_APB_GATE_NUM (CLK_AON_AP_EMC_EB + 1)
+
+#define CLK_MAHB_CKG_EB 0
+#define CLK_MDCAM_EB 1
+#define CLK_MISP_EB 2
+#define CLK_MAHBCSI_EB 3
+#define CLK_MCSI_S_EB 4
+#define CLK_MCSI_T_EB 5
+#define CLK_DCAM_AXI_EB 6
+#define CLK_ISP_AXI_EB 7
+#define CLK_MCSI_EB 8
+#define CLK_MCSI_S_CKG_EB 9
+#define CLK_MCSI_T_CKG_EB 10
+#define CLK_SENSOR0_EB 11
+#define CLK_SENSOR1_EB 12
+#define CLK_SENSOR2_EB 13
+#define CLK_MCPHY_CFG_EB 14
+#define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1)
+
+#define CLK_MIPI_CSI 0
+#define CLK_MIPI_CSI_S 1
+#define CLK_MIPI_CSI_M 2
+#define CLK_MM_CLK_NUM (CLK_MIPI_CSI_M + 1)
+
+#define CLK_SIM0_EB 0
+#define CLK_IIS0_EB 1
+#define CLK_IIS1_EB 2
+#define CLK_IIS2_EB 3
+#define CLK_SPI0_EB 4
+#define CLK_SPI1_EB 5
+#define CLK_SPI2_EB 6
+#define CLK_I2C0_EB 7
+#define CLK_I2C1_EB 8
+#define CLK_I2C2_EB 9
+#define CLK_I2C3_EB 10
+#define CLK_I2C4_EB 11
+#define CLK_UART0_EB 12
+#define CLK_UART1_EB 13
+#define CLK_UART2_EB 14
+#define CLK_UART3_EB 15
+#define CLK_UART4_EB 16
+#define CLK_SIM0_32K_EB 17
+#define CLK_SPI3_EB 18
+#define CLK_I2C5_EB 19
+#define CLK_I2C6_EB 20
+#define CLK_AP_APB_GATE_NUM (CLK_I2C6_EB + 1)
+
+#endif /* _DT_BINDINGS_CLK_SC9863A_H_ */
diff --git a/include/dt-bindings/clock/sun50i-a100-ccu.h b/include/dt-bindings/clock/sun50i-a100-ccu.h
new file mode 100644
index 0000000..28dc36e
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-a100-ccu.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_A100_H_
+#define _DT_BINDINGS_CLK_SUN50I_A100_H_
+
+#define CLK_PLL_PERIPH0 3
+
+#define CLK_CPUX 24
+
+#define CLK_APB1 29
+
+#define CLK_MBUS 31
+#define CLK_DE 32
+#define CLK_BUS_DE 33
+#define CLK_G2D 34
+#define CLK_BUS_G2D 35
+#define CLK_GPU 36
+#define CLK_BUS_GPU 37
+#define CLK_CE 38
+#define CLK_BUS_CE 39
+#define CLK_VE 40
+#define CLK_BUS_VE 41
+#define CLK_BUS_DMA 42
+#define CLK_BUS_MSGBOX 43
+#define CLK_BUS_SPINLOCK 44
+#define CLK_BUS_HSTIMER 45
+#define CLK_AVS 46
+#define CLK_BUS_DBG 47
+#define CLK_BUS_PSI 48
+#define CLK_BUS_PWM 49
+#define CLK_BUS_IOMMU 50
+#define CLK_MBUS_DMA 51
+#define CLK_MBUS_VE 52
+#define CLK_MBUS_CE 53
+#define CLK_MBUS_NAND 54
+#define CLK_MBUS_CSI 55
+#define CLK_MBUS_ISP 56
+#define CLK_MBUS_G2D 57
+
+#define CLK_NAND0 59
+#define CLK_NAND1 60
+#define CLK_BUS_NAND 61
+#define CLK_MMC0 62
+#define CLK_MMC1 63
+#define CLK_MMC2 64
+#define CLK_MMC3 65
+#define CLK_BUS_MMC0 66
+#define CLK_BUS_MMC1 67
+#define CLK_BUS_MMC2 68
+#define CLK_BUS_UART0 69
+#define CLK_BUS_UART1 70
+#define CLK_BUS_UART2 71
+#define CLK_BUS_UART3 72
+#define CLK_BUS_UART4 73
+#define CLK_BUS_I2C0 74
+#define CLK_BUS_I2C1 75
+#define CLK_BUS_I2C2 76
+#define CLK_BUS_I2C3 77
+#define CLK_SPI0 78
+#define CLK_SPI1 79
+#define CLK_SPI2 80
+#define CLK_BUS_SPI0 81
+#define CLK_BUS_SPI1 82
+#define CLK_BUS_SPI2 83
+#define CLK_EMAC_25M 84
+#define CLK_BUS_EMAC 85
+#define CLK_IR_RX 86
+#define CLK_BUS_IR_RX 87
+#define CLK_IR_TX 88
+#define CLK_BUS_IR_TX 89
+#define CLK_BUS_GPADC 90
+#define CLK_BUS_THS 91
+#define CLK_I2S0 92
+#define CLK_I2S1 93
+#define CLK_I2S2 94
+#define CLK_I2S3 95
+#define CLK_BUS_I2S0 96
+#define CLK_BUS_I2S1 97
+#define CLK_BUS_I2S2 98
+#define CLK_BUS_I2S3 99
+#define CLK_SPDIF 100
+#define CLK_BUS_SPDIF 101
+#define CLK_DMIC 102
+#define CLK_BUS_DMIC 103
+#define CLK_AUDIO_DAC 104
+#define CLK_AUDIO_ADC 105
+#define CLK_AUDIO_4X 106
+#define CLK_BUS_AUDIO_CODEC 107
+#define CLK_USB_OHCI0 108
+#define CLK_USB_PHY0 109
+#define CLK_USB_OHCI1 110
+#define CLK_USB_PHY1 111
+#define CLK_BUS_OHCI0 112
+#define CLK_BUS_OHCI1 113
+#define CLK_BUS_EHCI0 114
+#define CLK_BUS_EHCI1 115
+#define CLK_BUS_OTG 116
+#define CLK_BUS_LRADC 117
+#define CLK_BUS_DPSS_TOP0 118
+#define CLK_BUS_DPSS_TOP1 119
+#define CLK_MIPI_DSI 120
+#define CLK_BUS_MIPI_DSI 121
+#define CLK_TCON_LCD 122
+#define CLK_BUS_TCON_LCD 123
+#define CLK_LEDC 124
+#define CLK_BUS_LEDC 125
+#define CLK_CSI_TOP 126
+#define CLK_CSI0_MCLK 127
+#define CLK_CSI1_MCLK 128
+#define CLK_BUS_CSI 129
+#define CLK_CSI_ISP 130
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_A100_H_ */
diff --git a/include/dt-bindings/clock/sun50i-a100-r-ccu.h b/include/dt-bindings/clock/sun50i-a100-r-ccu.h
new file mode 100644
index 0000000..07312e7
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-a100-r-ccu.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_
+
+#define CLK_R_APB1 2
+
+#define CLK_R_APB1_TIMER 4
+#define CLK_R_APB1_TWD 5
+#define CLK_R_APB1_PWM 6
+#define CLK_R_APB1_BUS_PWM 7
+#define CLK_R_APB1_PPU 8
+#define CLK_R_APB2_UART 9
+#define CLK_R_APB2_I2C0 10
+#define CLK_R_APB2_I2C1 11
+#define CLK_R_APB1_IR 12
+#define CLK_R_APB1_BUS_IR 13
+#define CLK_R_AHB_BUS_RTC 14
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
index a8ac4cf..318eb15 100644
--- a/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -46,6 +46,7 @@
#define CLK_PLL_VIDEO0 7
#define CLK_PLL_PERIPH0 11
+#define CLK_CPUX 21
#define CLK_BUS_MIPI_DSI 28
#define CLK_BUS_CE 29
#define CLK_BUS_DMA 30
@@ -130,7 +131,7 @@
#define CLK_AVS 109
#define CLK_HDMI 110
#define CLK_HDMI_DDC 111
-
+#define CLK_MBUS 112
#define CLK_DSI_DPHY 113
#define CLK_GPU 114
diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h
index c5d1334..39878d9 100644
--- a/include/dt-bindings/clock/sun6i-a31-ccu.h
+++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
@@ -49,6 +49,8 @@
#define CLK_PLL_VIDEO1_2X 13
+#define CLK_PLL_MIPI 15
+
#define CLK_CPU 18
#define CLK_AHB1_MIPIDSI 23
diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
index f8222b6..eb524d0 100644
--- a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
+++ b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
@@ -43,6 +43,8 @@
#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
+#define CLK_PLL_MIPI 13
+
#define CLK_CPUX 18
#define CLK_BUS_MIPI_DSI 23
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
index c5f7e9a..30d2d15 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -143,7 +143,7 @@
#define CLK_AVS 110
#define CLK_HDMI 111
#define CLK_HDMI_DDC 112
-
+#define CLK_MBUS 113
#define CLK_GPU 114
/* New clocks imported in H5 */
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h
index f9e15a2..d7337b5 100644
--- a/include/dt-bindings/clock/sun8i-r40-ccu.h
+++ b/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -176,7 +176,7 @@
#define CLK_AVS 152
#define CLK_HDMI 153
#define CLK_HDMI_SLOW 154
-
+#define CLK_MBUS 155
#define CLK_DSI_DPHY 156
#define CLK_TVE0 157
#define CLK_TVE1 158
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index bb5c2c9..a93426f 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -228,6 +228,8 @@
#define TEGRA114_CLK_CLK_M 201
#define TEGRA114_CLK_CLK_M_DIV2 202
#define TEGRA114_CLK_CLK_M_DIV4 203
+#define TEGRA114_CLK_OSC_DIV2 202
+#define TEGRA114_CLK_OSC_DIV4 203
#define TEGRA114_CLK_PLL_REF 204
#define TEGRA114_CLK_PLL_C 205
#define TEGRA114_CLK_PLL_C_OUT1 206
@@ -270,11 +272,11 @@
#define TEGRA114_CLK_AUDIO3 242
#define TEGRA114_CLK_AUDIO4 243
#define TEGRA114_CLK_SPDIF 244
-#define TEGRA114_CLK_CLK_OUT_1 245
-#define TEGRA114_CLK_CLK_OUT_2 246
-#define TEGRA114_CLK_CLK_OUT_3 247
-#define TEGRA114_CLK_BLINK 248
-/* 249 */
+/* 245 */
+/* 246 */
+/* 247 */
+/* 248 */
+#define TEGRA114_CLK_OSC 249
/* 250 */
/* 251 */
#define TEGRA114_CLK_XUSB_HOST_SRC 252
@@ -333,9 +335,9 @@
#define TEGRA114_CLK_AUDIO3_MUX 303
#define TEGRA114_CLK_AUDIO4_MUX 304
#define TEGRA114_CLK_SPDIF_MUX 305
-#define TEGRA114_CLK_CLK_OUT_1_MUX 306
-#define TEGRA114_CLK_CLK_OUT_2_MUX 307
-#define TEGRA114_CLK_CLK_OUT_3_MUX 308
+/* 306 */
+/* 307 */
+/* 308 */
#define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310
#define TEGRA114_CLK_XUSB_SS_DIV2 311
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
index 4331f1d..c59f9de 100644
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -227,6 +227,8 @@
#define TEGRA124_CLK_CLK_M 201
#define TEGRA124_CLK_CLK_M_DIV2 202
#define TEGRA124_CLK_CLK_M_DIV4 203
+#define TEGRA124_CLK_OSC_DIV2 202
+#define TEGRA124_CLK_OSC_DIV4 203
#define TEGRA124_CLK_PLL_REF 204
#define TEGRA124_CLK_PLL_C 205
#define TEGRA124_CLK_PLL_C_OUT1 206
@@ -269,11 +271,11 @@
#define TEGRA124_CLK_AUDIO3 242
#define TEGRA124_CLK_AUDIO4 243
#define TEGRA124_CLK_SPDIF 244
-#define TEGRA124_CLK_CLK_OUT_1 245
-#define TEGRA124_CLK_CLK_OUT_2 246
-#define TEGRA124_CLK_CLK_OUT_3 247
-#define TEGRA124_CLK_BLINK 248
-/* 249 */
+/* 245 */
+/* 246 */
+/* 247 */
+/* 248 */
+#define TEGRA124_CLK_OSC 249
/* 250 */
/* 251 */
#define TEGRA124_CLK_XUSB_HOST_SRC 252
@@ -332,12 +334,13 @@
#define TEGRA124_CLK_AUDIO3_MUX 303
#define TEGRA124_CLK_AUDIO4_MUX 304
#define TEGRA124_CLK_SPDIF_MUX 305
-#define TEGRA124_CLK_CLK_OUT_1_MUX 306
-#define TEGRA124_CLK_CLK_OUT_2_MUX 307
-#define TEGRA124_CLK_CLK_OUT_3_MUX 308
+/* 306 */
+/* 307 */
+/* 308 */
/* 309 */
/* 310 */
-#define TEGRA124_CLK_SOR0_LVDS 311
+#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */
+#define TEGRA124_CLK_SOR0_OUT 311
#define TEGRA124_CLK_XUSB_SS_DIV2 312
#define TEGRA124_CLK_PLL_M_UD 313
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index b21a0eb..fe541f6 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -131,7 +131,7 @@
#define TEGRA20_CLK_CCLK 108
#define TEGRA20_CLK_HCLK 109
#define TEGRA20_CLK_PCLK 110
-#define TEGRA20_CLK_BLINK 111
+/* 111 */
#define TEGRA20_CLK_PLL_A 112
#define TEGRA20_CLK_PLL_A_OUT0 113
#define TEGRA20_CLK_PLL_C 114
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 6b77e72..ab8b8a7 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -262,6 +262,8 @@
#define TEGRA210_CLK_CLK_M 233
#define TEGRA210_CLK_CLK_M_DIV2 234
#define TEGRA210_CLK_CLK_M_DIV4 235
+#define TEGRA210_CLK_OSC_DIV2 234
+#define TEGRA210_CLK_OSC_DIV4 235
#define TEGRA210_CLK_PLL_REF 236
#define TEGRA210_CLK_PLL_C 237
#define TEGRA210_CLK_PLL_C_OUT1 238
@@ -304,12 +306,12 @@
#define TEGRA210_CLK_AUDIO3 274
#define TEGRA210_CLK_AUDIO4 275
#define TEGRA210_CLK_SPDIF 276
-#define TEGRA210_CLK_CLK_OUT_1 277
-#define TEGRA210_CLK_CLK_OUT_2 278
-#define TEGRA210_CLK_CLK_OUT_3 279
-#define TEGRA210_CLK_BLINK 280
-/* 281 */
-#define TEGRA210_CLK_SOR1_SRC 282
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
+#define TEGRA210_CLK_SOR0_OUT 281
#define TEGRA210_CLK_SOR1_OUT 282
/* 283 */
#define TEGRA210_CLK_XUSB_HOST_SRC 284
@@ -349,14 +351,14 @@
#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
#define TEGRA210_CLK_XUSB_SSP_SRC 318
#define TEGRA210_CLK_PLL_RE_OUT1 319
-/* 320 */
-/* 321 */
+#define TEGRA210_CLK_PLL_MB_UD 320
+#define TEGRA210_CLK_PLL_P_UD 321
#define TEGRA210_CLK_ISP 322
#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
/* 325 */
-/* 326 */
-/* 327 */
+#define TEGRA210_CLK_OSC 326
+#define TEGRA210_CLK_CSI_TPG 327
/* 328 */
/* 329 */
/* 330 */
@@ -386,12 +388,12 @@
#define TEGRA210_CLK_AUDIO3_MUX 353
#define TEGRA210_CLK_AUDIO4_MUX 354
#define TEGRA210_CLK_SPDIF_MUX 355
-#define TEGRA210_CLK_CLK_OUT_1_MUX 356
-#define TEGRA210_CLK_CLK_OUT_2_MUX 357
-#define TEGRA210_CLK_CLK_OUT_3_MUX 358
+/* 356 */
+/* 357 */
+/* 358 */
#define TEGRA210_CLK_DSIA_MUX 359
#define TEGRA210_CLK_DSIB_MUX 360
-#define TEGRA210_CLK_SOR0_LVDS 361
+/* 361 */
#define TEGRA210_CLK_XUSB_SS_DIV2 362
#define TEGRA210_CLK_PLL_M_UD 363
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
new file mode 100644
index 0000000..2c82072
--- /dev/null
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
+#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
+
+/** @brief output of gate CLK_ENB_FUSE */
+#define TEGRA234_CLK_FUSE 40
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
+#define TEGRA234_CLK_SDMMC4 123
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
+#define TEGRA234_CLK_UARTA 155
+
+#endif
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 3c90f15..f193663 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -196,6 +196,8 @@
#define TEGRA30_CLK_CLK_M 171
#define TEGRA30_CLK_CLK_M_DIV2 172
#define TEGRA30_CLK_CLK_M_DIV4 173
+#define TEGRA30_CLK_OSC_DIV2 172
+#define TEGRA30_CLK_OSC_DIV4 173
#define TEGRA30_CLK_PLL_REF 174
#define TEGRA30_CLK_PLL_C 175
#define TEGRA30_CLK_PLL_C_OUT1 176
@@ -230,11 +232,11 @@
#define TEGRA30_CLK_AUDIO3 204
#define TEGRA30_CLK_AUDIO4 205
#define TEGRA30_CLK_SPDIF 206
-#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
-#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
-#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
+/* 207 */
+/* 208 */
+/* 209 */
#define TEGRA30_CLK_SCLK 210
-#define TEGRA30_CLK_BLINK 211
+/* 211 */
#define TEGRA30_CLK_CCLK_G 212
#define TEGRA30_CLK_CCLK_LP 213
#define TEGRA30_CLK_TWD 214
@@ -243,7 +245,7 @@
#define TEGRA30_CLK_HCLK 217
#define TEGRA30_CLK_PCLK 218
/* 219 */
-/* 220 */
+#define TEGRA30_CLK_OSC 220
/* 221 */
/* 222 */
/* 223 */
@@ -260,9 +262,9 @@
/* 297 */
/* 298 */
/* 299 */
-#define TEGRA30_CLK_CLK_OUT_1_MUX 300
-#define TEGRA30_CLK_CLK_OUT_2_MUX 301
-#define TEGRA30_CLK_CLK_OUT_3_MUX 302
+/* 300 */
+/* 301 */
+/* 302 */
#define TEGRA30_CLK_AUDIO0_MUX 303
#define TEGRA30_CLK_AUDIO1_MUX 304
#define TEGRA30_CLK_AUDIO2_MUX 305
diff --git a/include/dt-bindings/clock/ti-dra7-atl.h b/include/dt-bindings/clock/ti-dra7-atl.h
new file mode 100644
index 0000000..42dd416
--- /dev/null
+++ b/include/dt-bindings/clock/ti-dra7-atl.h
@@ -0,0 +1,40 @@
+/*
+ * This header provides constants for DRA7 ATL (Audio Tracking Logic)
+ *
+ * The constants defined in this header are used in dts files
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Peter Ujfalusi <peter.ujfalusi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
+#define _DT_BINDINGS_CLK_DRA7_ATL_H
+
+#define DRA7_ATL_WS_MCASP1_FSR 0
+#define DRA7_ATL_WS_MCASP1_FSX 1
+#define DRA7_ATL_WS_MCASP2_FSR 2
+#define DRA7_ATL_WS_MCASP2_FSX 3
+#define DRA7_ATL_WS_MCASP3_FSX 4
+#define DRA7_ATL_WS_MCASP4_FSX 5
+#define DRA7_ATL_WS_MCASP5_FSX 6
+#define DRA7_ATL_WS_MCASP6_FSX 7
+#define DRA7_ATL_WS_MCASP7_FSX 8
+#define DRA7_ATL_WS_MCASP8_FSX 9
+#define DRA7_ATL_WS_MCASP8_AHCLKX 10
+#define DRA7_ATL_WS_XREF_CLK3 11
+#define DRA7_ATL_WS_XREF_CLK0 12
+#define DRA7_ATL_WS_XREF_CLK1 13
+#define DRA7_ATL_WS_XREF_CLK2 14
+#define DRA7_ATL_WS_OSC1_X1 15
+
+#endif
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 95394f3..373644e 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -195,6 +195,8 @@
#define VF610_CLK_WKPU 186
#define VF610_CLK_TCON0 187
#define VF610_CLK_TCON1 188
-#define VF610_CLK_END 189
+#define VF610_CLK_CAAM 189
+#define VF610_CLK_CRC 190
+#define VF610_CLK_END 191
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h
new file mode 100644
index 0000000..f187e07
--- /dev/null
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,x1000-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ * - external clocks
+ * - PLLs
+ * - muxes/dividers in the order they appear in the x1000 programmers manual
+ * - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
+#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
+
+#define X1000_CLK_EXCLK 0
+#define X1000_CLK_RTCLK 1
+#define X1000_CLK_APLL 2
+#define X1000_CLK_MPLL 3
+#define X1000_CLK_OTGPHY 4
+#define X1000_CLK_SCLKA 5
+#define X1000_CLK_CPUMUX 6
+#define X1000_CLK_CPU 7
+#define X1000_CLK_L2CACHE 8
+#define X1000_CLK_AHB0 9
+#define X1000_CLK_AHB2PMUX 10
+#define X1000_CLK_AHB2 11
+#define X1000_CLK_PCLK 12
+#define X1000_CLK_DDR 13
+#define X1000_CLK_MAC 14
+#define X1000_CLK_LCD 15
+#define X1000_CLK_MSCMUX 16
+#define X1000_CLK_MSC0 17
+#define X1000_CLK_MSC1 18
+#define X1000_CLK_OTG 19
+#define X1000_CLK_SSIPLL 20
+#define X1000_CLK_SSIPLL_DIV2 21
+#define X1000_CLK_SSIMUX 22
+#define X1000_CLK_EMC 23
+#define X1000_CLK_EFUSE 24
+#define X1000_CLK_SFC 25
+#define X1000_CLK_I2C0 26
+#define X1000_CLK_I2C1 27
+#define X1000_CLK_I2C2 28
+#define X1000_CLK_UART0 29
+#define X1000_CLK_UART1 30
+#define X1000_CLK_UART2 31
+#define X1000_CLK_TCU 32
+#define X1000_CLK_SSI 33
+#define X1000_CLK_OST 34
+#define X1000_CLK_PDMA 35
+#define X1000_CLK_EXCLK_DIV512 36
+#define X1000_CLK_RTC 37
+
+#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h
new file mode 100644
index 0000000..8845537
--- /dev/null
+++ b/include/dt-bindings/clock/x1830-cgu.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,x1830-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ * - external clocks
+ * - PLLs
+ * - muxes/dividers in the order they appear in the x1830 programmers manual
+ * - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__
+#define __DT_BINDINGS_CLOCK_X1830_CGU_H__
+
+#define X1830_CLK_EXCLK 0
+#define X1830_CLK_RTCLK 1
+#define X1830_CLK_APLL 2
+#define X1830_CLK_MPLL 3
+#define X1830_CLK_EPLL 4
+#define X1830_CLK_VPLL 5
+#define X1830_CLK_OTGPHY 6
+#define X1830_CLK_SCLKA 7
+#define X1830_CLK_CPUMUX 8
+#define X1830_CLK_CPU 9
+#define X1830_CLK_L2CACHE 10
+#define X1830_CLK_AHB0 11
+#define X1830_CLK_AHB2PMUX 12
+#define X1830_CLK_AHB2 13
+#define X1830_CLK_PCLK 14
+#define X1830_CLK_DDR 15
+#define X1830_CLK_MAC 16
+#define X1830_CLK_LCD 17
+#define X1830_CLK_MSCMUX 18
+#define X1830_CLK_MSC0 19
+#define X1830_CLK_MSC1 20
+#define X1830_CLK_SSIPLL 21
+#define X1830_CLK_SSIPLL_DIV2 22
+#define X1830_CLK_SSIMUX 23
+#define X1830_CLK_EMC 24
+#define X1830_CLK_EFUSE 25
+#define X1830_CLK_OTG 26
+#define X1830_CLK_SSI0 27
+#define X1830_CLK_SMB0 28
+#define X1830_CLK_SMB1 29
+#define X1830_CLK_SMB2 30
+#define X1830_CLK_UART0 31
+#define X1830_CLK_UART1 32
+#define X1830_CLK_SSI1 33
+#define X1830_CLK_SFC 34
+#define X1830_CLK_PDMA 35
+#define X1830_CLK_TCU 36
+#define X1830_CLK_DTRNG 37
+#define X1830_CLK_OST 38
+#define X1830_CLK_EXCLK_DIV512 39
+#define X1830_CLK_RTC 40
+
+#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */
diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h
new file mode 100644
index 0000000..264d634
--- /dev/null
+++ b/include/dt-bindings/clock/xlnx-versal-clk.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Xilinx Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLK_VERSAL_H
+#define _DT_BINDINGS_CLK_VERSAL_H
+
+#define PMC_PLL 1
+#define APU_PLL 2
+#define RPU_PLL 3
+#define CPM_PLL 4
+#define NOC_PLL 5
+#define PLL_MAX 6
+#define PMC_PRESRC 7
+#define PMC_POSTCLK 8
+#define PMC_PLL_OUT 9
+#define PPLL 10
+#define NOC_PRESRC 11
+#define NOC_POSTCLK 12
+#define NOC_PLL_OUT 13
+#define NPLL 14
+#define APU_PRESRC 15
+#define APU_POSTCLK 16
+#define APU_PLL_OUT 17
+#define APLL 18
+#define RPU_PRESRC 19
+#define RPU_POSTCLK 20
+#define RPU_PLL_OUT 21
+#define RPLL 22
+#define CPM_PRESRC 23
+#define CPM_POSTCLK 24
+#define CPM_PLL_OUT 25
+#define CPLL 26
+#define PPLL_TO_XPD 27
+#define NPLL_TO_XPD 28
+#define APLL_TO_XPD 29
+#define RPLL_TO_XPD 30
+#define EFUSE_REF 31
+#define SYSMON_REF 32
+#define IRO_SUSPEND_REF 33
+#define USB_SUSPEND 34
+#define SWITCH_TIMEOUT 35
+#define RCLK_PMC 36
+#define RCLK_LPD 37
+#define WDT 38
+#define TTC0 39
+#define TTC1 40
+#define TTC2 41
+#define TTC3 42
+#define GEM_TSU 43
+#define GEM_TSU_LB 44
+#define MUXED_IRO_DIV2 45
+#define MUXED_IRO_DIV4 46
+#define PSM_REF 47
+#define GEM0_RX 48
+#define GEM0_TX 49
+#define GEM1_RX 50
+#define GEM1_TX 51
+#define CPM_CORE_REF 52
+#define CPM_LSBUS_REF 53
+#define CPM_DBG_REF 54
+#define CPM_AUX0_REF 55
+#define CPM_AUX1_REF 56
+#define QSPI_REF 57
+#define OSPI_REF 58
+#define SDIO0_REF 59
+#define SDIO1_REF 60
+#define PMC_LSBUS_REF 61
+#define I2C_REF 62
+#define TEST_PATTERN_REF 63
+#define DFT_OSC_REF 64
+#define PMC_PL0_REF 65
+#define PMC_PL1_REF 66
+#define PMC_PL2_REF 67
+#define PMC_PL3_REF 68
+#define CFU_REF 69
+#define SPARE_REF 70
+#define NPI_REF 71
+#define HSM0_REF 72
+#define HSM1_REF 73
+#define SD_DLL_REF 74
+#define FPD_TOP_SWITCH 75
+#define FPD_LSBUS 76
+#define ACPU 77
+#define DBG_TRACE 78
+#define DBG_FPD 79
+#define LPD_TOP_SWITCH 80
+#define ADMA 81
+#define LPD_LSBUS 82
+#define CPU_R5 83
+#define CPU_R5_CORE 84
+#define CPU_R5_OCM 85
+#define CPU_R5_OCM2 86
+#define IOU_SWITCH 87
+#define GEM0_REF 88
+#define GEM1_REF 89
+#define GEM_TSU_REF 90
+#define USB0_BUS_REF 91
+#define UART0_REF 92
+#define UART1_REF 93
+#define SPI0_REF 94
+#define SPI1_REF 95
+#define CAN0_REF 96
+#define CAN1_REF 97
+#define I2C0_REF 98
+#define I2C1_REF 99
+#define DBG_LPD 100
+#define TIMESTAMP_REF 101
+#define DBG_TSTMP 102
+#define CPM_TOPSW_REF 103
+#define USB3_DUAL_REF 104
+#define OUTCLK_MAX 105
+#define REF_CLK 106
+#define PL_ALT_REF_CLK 107
+#define MUXED_IRO 108
+#define PL_EXT 109
+#define PL_LB 110
+#define MIO_50_OR_51 111
+#define MIO_24_OR_25 112
+
+#endif