Update Linux to v5.10.109
Sourced from [1]
[1] https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.10.109.tar.xz
Change-Id: I19bca9fc6762d4e63bcf3e4cba88bbe560d9c76c
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
diff --git a/arch/arm/mach-omap2/.gitignore b/arch/arm/mach-omap2/.gitignore
index 79a8d6e..dc7be75 100644
--- a/arch/arm/mach-omap2/.gitignore
+++ b/arch/arm/mach-omap2/.gitignore
@@ -1 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
pm-asm-offsets.h
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index fdb6743..3f62a0c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -66,7 +66,6 @@
select ARCH_OMAP2PLUS
select ARM_GIC
select MACH_OMAP_GENERIC
- select MIGHT_HAVE_CACHE_L2X0
select HAVE_ARM_SCU
select GENERIC_CLOCKEVENTS_BROADCAST
select HAVE_ARM_TWD
@@ -95,6 +94,7 @@
bool
select ARCH_HAS_BANDGAP
select ARCH_HAS_HOLES_MEMORYMODEL
+ select ARCH_HAS_RESET_CONTROLLER
select ARCH_OMAP
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
@@ -105,6 +105,9 @@
select OMAP_DM_TIMER
select OMAP_GPMC
select PINCTRL
+ select PM_GENERIC_DOMAINS if PM
+ select PM_GENERIC_DOMAINS_OF if PM
+ select RESET_CONTROLLER
select SOC_BUS
select TI_SYSC
select OMAP_IRQCHIP
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8f20819..732e614 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -7,7 +7,7 @@
-I$(srctree)/arch/arm/plat-omap/include
# Common support
-obj-y := id.o io.o control.o devices.o fb.o timer.o pm.o \
+obj-y := id.o io.o control.o devices.o fb.o pm.o \
common.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
omap_device.o omap-headsmp.o sram.o
@@ -19,8 +19,8 @@
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
-obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common)
-obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
@@ -29,6 +29,11 @@
endif
obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
+
+ifneq ($(CONFIG_MFD_CPCAP),)
+obj-y += pmic-cpcap.o
+endif
+
obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
# SMP support ONLY available for OMAP4
@@ -41,6 +46,10 @@
obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o
+omap5-dra7-common-$(CONFIG_SOC_HAS_REALTIME_COUNTER) = timer.o
+obj-$(CONFIG_SOC_OMAP5) += $(omap5-dra7-common-y)
+obj-$(CONFIG_SOC_DRA7XX) += $(omap5-dra7-common-y)
+
# Functions loaded to SRAM
obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
@@ -216,9 +225,6 @@
# Platform specific device init code
-omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
-obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
-
obj-y += omap_phy_internal.o
obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index 5eef093..bf2b5f8 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -1,7 +1,7 @@
/*
* This file contains the address info for various AM33XX modules.
*
- * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments, Inc. - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index ad512f0..1610c56 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -3,7 +3,7 @@
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* Modified from the original mach-omap/omap2/board-generic.c did by Paul
* to support the OMAP2+ device tree boards with an unique board file.
@@ -12,6 +12,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/irqdomain.h>
+#include <linux/clocksource.h>
#include <asm/setup.h>
#include <asm/mach/arch.h>
@@ -31,6 +32,20 @@
omap_soc_device_init();
}
+/* Clocks are needed early, see drivers/clocksource for the rest */
+static void __init __maybe_unused omap_init_time_of(void)
+{
+ omap_clk_init();
+ timer_probe();
+}
+
+/* Used by am437x for ARM timer in non-SMP configurations */
+#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
+void tick_broadcast(const struct cpumask *mask)
+{
+}
+#endif
+
#ifdef CONFIG_SOC_OMAP2420
static const char *const omap242x_boards_compat[] __initconst = {
"ti,omap2420",
@@ -42,7 +57,7 @@
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_machine = omap_generic_init,
- .init_time = omap_init_time,
+ .init_time = omap_init_time_of,
.dt_compat = omap242x_boards_compat,
.restart = omap2xxx_restart,
MACHINE_END
@@ -59,7 +74,7 @@
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_machine = omap_generic_init,
- .init_time = omap_init_time,
+ .init_time = omap_init_time_of,
.dt_compat = omap243x_boards_compat,
.restart = omap2xxx_restart,
MACHINE_END
@@ -106,7 +121,7 @@
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
- .init_time = omap_init_time,
+ .init_time = omap_init_time_of,
.dt_compat = n900_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@@ -124,7 +139,7 @@
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
- .init_time = omap_init_time,
+ .init_time = omap_init_time_of,
.dt_compat = omap3_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@@ -141,7 +156,7 @@
.init_early = omap3630_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
- .init_time = omap_init_time,
+ .init_time = omap_init_time_of,
.dt_compat = omap36xx_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@@ -158,7 +173,7 @@
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
- .init_time = omap3_secure_sync32k_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = omap3_gp_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@@ -174,7 +189,7 @@
.init_early = am35xx_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = am3517_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
@@ -193,7 +208,7 @@
.init_early = ti814x_init_early,
.init_machine = omap_generic_init,
.init_late = ti81xx_init_late,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = ti814x_boards_compat,
.restart = ti81xx_restart,
MACHINE_END
@@ -210,7 +225,7 @@
.init_early = ti816x_init_early,
.init_machine = omap_generic_init,
.init_late = ti81xx_init_late,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = ti816x_boards_compat,
.restart = ti81xx_restart,
MACHINE_END
@@ -228,7 +243,7 @@
.init_early = am33xx_init_early,
.init_machine = omap_generic_init,
.init_late = am33xx_init_late,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = am33xx_boards_compat,
.restart = am33xx_restart,
MACHINE_END
@@ -253,7 +268,7 @@
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
.init_late = omap4430_init_late,
- .init_time = omap4_local_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = omap4_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
@@ -300,7 +315,7 @@
.init_late = am43xx_init_late,
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap_init_time_of,
.dt_compat = am43_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
@@ -327,7 +342,7 @@
.init_late = dra7xx_init_late,
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap5_realtime_timer_init,
.dt_compat = dra74x_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
@@ -350,7 +365,7 @@
.init_late = dra7xx_init_late,
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
- .init_time = omap3_gptimer_timer_init,
+ .init_time = omap5_realtime_timer_init,
.dt_compat = dra72x_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index f98c8ec..dedd47e 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -1147,7 +1147,21 @@
/* Clockdomain-to-clock/hwmod framework interface code */
-static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
+/**
+ * clkdm_clk_enable - add an enabled downstream clock to this clkdm
+ * @clkdm: struct clockdomain *
+ * @clk: struct clk * of the enabled downstream clock
+ *
+ * Increment the usecount of the clockdomain @clkdm and ensure that it
+ * is awake before @clk is enabled. Intended to be called by
+ * clk_enable() code. If the clockdomain is in software-supervised
+ * idle mode, force the clockdomain to wake. If the clockdomain is in
+ * hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
+ * ensure that devices in the clockdomain can be read from/written to
+ * by on-chip processors. Returns -EINVAL if passed null pointers;
+ * returns 0 upon success or if the clockdomain is in hwsup idle mode.
+ */
+int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *unused)
{
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
return -EINVAL;
@@ -1175,33 +1189,6 @@
}
/**
- * clkdm_clk_enable - add an enabled downstream clock to this clkdm
- * @clkdm: struct clockdomain *
- * @clk: struct clk * of the enabled downstream clock
- *
- * Increment the usecount of the clockdomain @clkdm and ensure that it
- * is awake before @clk is enabled. Intended to be called by
- * clk_enable() code. If the clockdomain is in software-supervised
- * idle mode, force the clockdomain to wake. If the clockdomain is in
- * hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
- * ensure that devices in the clockdomain can be read from/written to
- * by on-chip processors. Returns -EINVAL if passed null pointers;
- * returns 0 upon success or if the clockdomain is in hwsup idle mode.
- */
-int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
-{
- /*
- * XXX Rewrite this code to maintain a list of enabled
- * downstream clocks for debugging purposes?
- */
-
- if (!clk)
- return -EINVAL;
-
- return _clkdm_clk_hwmod_enable(clkdm);
-}
-
-/**
* clkdm_clk_disable - remove an enabled downstream clock from this clkdm
* @clkdm: struct clockdomain *
* @clk: struct clk * of the disabled downstream clock
@@ -1216,13 +1203,13 @@
*/
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
{
- if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+ if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
pwrdm_lock(clkdm->pwrdm.ptr);
/* corner case: disabling unused clocks */
- if ((__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0)
+ if (clk && (__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0)
goto ccd_exit;
if (clkdm->usecount == 0) {
@@ -1277,7 +1264,7 @@
if (!oh)
return -EINVAL;
- return _clkdm_clk_hwmod_enable(clkdm);
+ return clkdm_clk_enable(clkdm, NULL);
}
/**
@@ -1300,35 +1287,10 @@
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
- /*
- * XXX Rewrite this code to maintain a list of enabled
- * downstream hwmods for debugging purposes?
- */
-
- if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+ if (!oh)
return -EINVAL;
- pwrdm_lock(clkdm->pwrdm.ptr);
-
- if (clkdm->usecount == 0) {
- pwrdm_unlock(clkdm->pwrdm.ptr);
- WARN_ON(1); /* underflow */
- return -ERANGE;
- }
-
- clkdm->usecount--;
- if (clkdm->usecount > 0) {
- pwrdm_unlock(clkdm->pwrdm.ptr);
- return 0;
- }
-
- arch_clkdm->clkdm_clk_disable(clkdm);
- pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
- pwrdm_unlock(clkdm->pwrdm.ptr);
-
- pr_debug("clockdomain: %s: disabled\n", clkdm->name);
-
- return 0;
+ return clkdm_clk_disable(clkdm, NULL);
}
/**
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
index 32c90fd..b4d5144 100644
--- a/arch/arm/mach-omap2/clockdomains33xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
@@ -1,7 +1,7 @@
/*
* AM33XX Clock Domain data.
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* This program is free software; you can redistribute it and/or
diff --git a/arch/arm/mach-omap2/clockdomains43xx_data.c b/arch/arm/mach-omap2/clockdomains43xx_data.c
index 751708d..c96a2b1 100644
--- a/arch/arm/mach-omap2/clockdomains43xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains43xx_data.c
@@ -84,6 +84,15 @@
.flags = CLKDM_CAN_SWSUP,
};
+static struct clockdomain lcdc_43xx_clkdm = {
+ .name = "lcdc_clkdm",
+ .pwrdm = { .name = "per_pwrdm" },
+ .prcm_partition = AM43XX_CM_PARTITION,
+ .cm_inst = AM43XX_CM_PER_INST,
+ .clkdm_offs = AM43XX_CM_PER_LCDC_CDOFFS,
+ .flags = CLKDM_CAN_SWSUP,
+};
+
static struct clockdomain dss_43xx_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "per_pwrdm" },
@@ -173,6 +182,7 @@
&pruss_ocp_43xx_clkdm,
&ocpwp_l3_43xx_clkdm,
&l3s_tsc_43xx_clkdm,
+ &lcdc_43xx_clkdm,
&dss_43xx_clkdm,
&l3_aon_43xx_clkdm,
&emif_43xx_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 6005c4e..8285be7 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -214,7 +214,7 @@
.dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
.wkdep_srcs = l4_secure_wkup_sleep_deps,
.sleepdep_srcs = l4_secure_wkup_sleep_deps,
- .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4_per_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
index 3ab41fc..5611e08 100644
--- a/arch/arm/mach-omap2/clockdomains54xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -170,7 +170,7 @@
.dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT,
.wkdep_srcs = l4sec_wkup_sleep_deps,
.sleepdep_srcs = l4sec_wkup_sleep_deps,
- .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain iva_54xx_clkdm = {
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
index 3068802..27835c4 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -606,7 +606,7 @@
.dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
.wkdep_srcs = cam_wkup_sleep_deps,
.sleepdep_srcs = cam_wkup_sleep_deps,
- .flags = CLKDM_CAN_HWSUP_SWSUP,
+ .flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4per_7xx_clkdm = {
diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
index 65fbd13..127dc7a 100644
--- a/arch/arm/mach-omap2/clockdomains81xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -1,7 +1,7 @@
/*
* TI81XX Clock Domain data.
*
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
*
* This program is free software; you can redistribute it and/or
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index c0823fd..e7ae2bb 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -4,7 +4,7 @@
* This file is automatically generated from the AM33XX hardware databases.
* Vaibhav Hiremath <hvaibhav@ti.com>
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h
index 44663b5..fc88688 100644
--- a/arch/arm/mach-omap2/cm-regbits-54xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54xx Clock Management register bits
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
diff --git a/arch/arm/mach-omap2/cm-regbits-7xx.h b/arch/arm/mach-omap2/cm-regbits-7xx.h
index a78ccba..2725af4 100644
--- a/arch/arm/mach-omap2/cm-regbits-7xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-7xx.h
@@ -2,7 +2,7 @@
/*
* DRA7xx Clock Management register bits
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
index 7be363a..eb86bbd 100644
--- a/arch/arm/mach-omap2/cm1_54xx.h
+++ b/arch/arm/mach-omap2/cm1_54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54xx CM1 instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
index 28660ed..aae3831 100644
--- a/arch/arm/mach-omap2/cm1_7xx.h
+++ b/arch/arm/mach-omap2/cm1_7xx.h
@@ -2,7 +2,7 @@
/*
* DRA7xx CM1 instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
index c5da1f5..8e49765 100644
--- a/arch/arm/mach-omap2/cm2_54xx.h
+++ b/arch/arm/mach-omap2/cm2_54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54xx CM2 instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index e16fc58..f873460 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -2,7 +2,7 @@
/*
* DRA7xx CM2 instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 084d454..ac4882e 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -1,7 +1,7 @@
/*
* AM33XX CM functions
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* Reference taken from from OMAP4 cminst44xx.c
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index a91f7d2..63b362b 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -1,7 +1,7 @@
/*
* AM33XX CM offset macros
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* This program is free software; you can redistribute it and/or
diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h
index 5d73a10..bd91223 100644
--- a/arch/arm/mach-omap2/cm81xx.h
+++ b/arch/arm/mach-omap2/cm81xx.h
@@ -1,7 +1,7 @@
/*
* Clock domain register offsets for TI81XX.
*
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
*
* This program is free software; you can redistribute it and/or
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 6316da3..49926ec 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -111,7 +111,14 @@
#define OMAP_L2C_AUX_CTRL 0
#define omap4_l2c310_write_sec NULL
#endif
+
+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
extern void omap5_realtime_timer_init(void);
+#else
+static inline void omap5_realtime_timer_init(void)
+{
+}
+#endif
void omap2420_init_early(void);
void omap2430_init_early(void);
@@ -255,7 +262,7 @@
extern void gic_dist_enable(void);
extern bool gic_dist_disabled(void);
extern void gic_timer_retrigger(void);
-extern void omap_smc1(u32 fn, u32 arg);
+extern void _omap_smc1(u32 fn, u32 arg);
extern void omap4_sar_ram_init(void);
extern void __iomem *omap4_get_sar_ram_base(void);
extern void omap4_mpuss_early_init(void);
@@ -345,14 +352,16 @@
}
#endif
+struct omap_system_dma_plat_info;
+
void pdata_quirks_init(const struct of_device_id *);
void omap_auxdata_legacy_init(struct device *dev);
void omap_pcs_legacy_init(int irq, void (*rearm)(void));
+extern struct omap_system_dma_plat_info dma_plat_info;
struct omap_sdrc_params;
extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1);
-struct omap2_hsmmc_info;
extern void omap_reserve(void);
struct omap_hwmod;
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index c84b5e2..73338cf 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -684,7 +684,7 @@
*
* Save the wkup domain registers
*/
-void am43xx_control_save_context(void)
+static void am43xx_control_save_context(void)
{
int i;
@@ -698,7 +698,7 @@
*
* Restore the wkup domain registers
*/
-void am43xx_control_restore_context(void)
+static void am43xx_control_restore_context(void)
{
int i;
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 393b421..eceb4b0 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -195,6 +195,7 @@
#define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243
#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246
#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB 0x24C
#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 46012ca..6098666 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -1,7 +1,7 @@
/*
* OMAP2plus display device setup / initialization.
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Senthilvadivu Guruswamy
* Sumit Semwal
*
@@ -263,9 +263,9 @@
}
r = of_platform_populate(node, NULL, NULL, &pdev->dev);
+ put_device(&pdev->dev);
if (r) {
pr_err("Unable to populate DSS submodule devices\n");
- put_device(&pdev->dev);
return r;
}
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 0c105ba..dfc9b21 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -13,7 +13,7 @@
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Converted DMA library into platform driver
* - G, Manjunath Kondaiah <manjugk@ti.com>
*/
@@ -30,10 +30,6 @@
#include <linux/omap-dma.h>
#include "soc.h"
-#include "omap_hwmod.h"
-#include "omap_device.h"
-
-static enum omap_reg_offsets dma_common_ch_end;
static const struct omap_dma_reg reg_map[] = {
[REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
@@ -81,42 +77,6 @@
[CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
};
-static void __iomem *dma_base;
-static inline void dma_write(u32 val, int reg, int lch)
-{
- void __iomem *addr = dma_base;
-
- addr += reg_map[reg].offset;
- addr += reg_map[reg].stride * lch;
-
- writel_relaxed(val, addr);
-}
-
-static inline u32 dma_read(int reg, int lch)
-{
- void __iomem *addr = dma_base;
-
- addr += reg_map[reg].offset;
- addr += reg_map[reg].stride * lch;
-
- return readl_relaxed(addr);
-}
-
-static void omap2_clear_dma(int lch)
-{
- int i;
-
- for (i = CSDP; i <= dma_common_ch_end; i += 1)
- dma_write(0, i, lch);
-}
-
-static void omap2_show_dma_caps(void)
-{
- u8 revision = dma_read(REVISION, 0) & 0xff;
- printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
- revision >> 4, revision & 0xf);
-}
-
static unsigned configure_dma_errata(void)
{
unsigned errata = 0;
@@ -211,82 +171,35 @@
{ "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
};
-static struct omap_system_dma_plat_info dma_plat_info __initdata = {
- .reg_map = reg_map,
- .channel_stride = 0x60,
- .show_dma_caps = omap2_show_dma_caps,
- .clear_dma = omap2_clear_dma,
- .dma_write = dma_write,
- .dma_read = dma_read,
+static struct omap_dma_dev_attr dma_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+ IS_CSSA_32 | IS_CDSA_32,
+ .lch_count = 32,
};
-static struct platform_device_info omap_dma_dev_info __initdata = {
- .name = "omap-dma-engine",
- .id = -1,
- .dma_mask = DMA_BIT_MASK(32),
+struct omap_system_dma_plat_info dma_plat_info = {
+ .reg_map = reg_map,
+ .channel_stride = 0x60,
+ .dma_attr = &dma_attr,
};
/* One time initializations */
-static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
+static int __init omap2_system_dma_init(void)
{
- struct platform_device *pdev;
- struct omap_system_dma_plat_info p;
- struct omap_dma_dev_attr *d;
- struct resource *mem;
- char *name = "omap_dma_system";
-
- p = dma_plat_info;
- p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
- p.errata = configure_dma_errata();
+ dma_plat_info.errata = configure_dma_errata();
if (soc_is_omap24xx()) {
/* DMA slave map for drivers not yet converted to DT */
- p.slave_map = omap24xx_sdma_dt_map;
- p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
+ dma_plat_info.slave_map = omap24xx_sdma_dt_map;
+ dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
}
- pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
- if (IS_ERR(pdev)) {
- pr_err("%s: Can't build omap_device for %s:%s.\n",
- __func__, name, oh->name);
- return PTR_ERR(pdev);
- }
+ if (!soc_is_omap242x())
+ dma_attr.dev_caps |= IS_RW_PRIORITY;
- omap_dma_dev_info.res = pdev->resource;
- omap_dma_dev_info.num_res = pdev->num_resources;
-
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!mem) {
- dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
- return -EINVAL;
- }
-
- dma_base = ioremap(mem->start, resource_size(mem));
- if (!dma_base) {
- dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
- return -ENOMEM;
- }
-
- d = oh->dev_attr;
-
- if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
- d->dev_caps |= HS_CHANNELS_RESERVED;
-
- if (platform_get_irq_byname(pdev, "0") < 0)
- d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
-
- /* Check the capabilities register for descriptor loading feature */
- if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
- dma_common_ch_end = CCDN;
- else
- dma_common_ch_end = CCFN;
+ if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+ dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
return 0;
}
-
-static int __init omap2_system_dma_init(void)
-{
- return omap_hwmod_for_each_by_class("dma",
- omap2_system_dma_init_dev, NULL);
-}
omap_arch_initcall(omap2_system_dma_init);
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
deleted file mode 100644
index 63423ea..0000000
--- a/arch/arm/mach-omap2/hsmmc.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-omap2/hsmmc.c
- *
- * Copyright (C) 2007-2008 Texas Instruments
- * Copyright (C) 2008 Nokia Corporation
- * Author: Texas Instruments
- */
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_data/hsmmc-omap.h>
-
-#include "soc.h"
-#include "omap_device.h"
-
-#include "hsmmc.h"
-#include "control.h"
-
-#if IS_ENABLED(CONFIG_MMC_OMAP_HS)
-
-static u16 control_pbias_offset;
-static u16 control_devconf1_offset;
-
-#define HSMMC_NAME_LEN 9
-
-static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
- struct omap_hsmmc_platform_data *mmc)
-{
- char *hc_name;
-
- hc_name = kzalloc(HSMMC_NAME_LEN + 1, GFP_KERNEL);
- if (!hc_name)
- return -ENOMEM;
-
- snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", c->mmc, 1);
- mmc->name = hc_name;
- mmc->caps = c->caps;
- mmc->reg_offset = 0;
-
- return 0;
-}
-
-static int omap_hsmmc_done;
-
-void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
-{
- struct platform_device *pdev;
- int res;
-
- if (omap_hsmmc_done)
- return;
-
- omap_hsmmc_done = 1;
-
- for (; c->mmc; c++) {
- pdev = c->pdev;
- if (!pdev)
- continue;
- res = omap_device_register(pdev);
- if (res)
- pr_err("Could not late init MMC\n");
- }
-}
-
-#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
-
-static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
- int ctrl_nr)
-{
- struct omap_hwmod *oh;
- struct omap_hwmod *ohs[1];
- struct omap_device *od;
- struct platform_device *pdev;
- char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
- struct omap_hsmmc_platform_data *mmc_data;
- struct omap_hsmmc_dev_attr *mmc_dev_attr;
- char *name;
- int res;
-
- mmc_data = kzalloc(sizeof(*mmc_data), GFP_KERNEL);
- if (!mmc_data)
- return;
-
- res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
- if (res < 0)
- goto free_mmc;
-
- name = "omap_hsmmc";
- res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
- "mmc%d", ctrl_nr);
- WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
- "String buffer overflow in MMC%d device setup\n", ctrl_nr);
-
- oh = omap_hwmod_lookup(oh_name);
- if (!oh) {
- pr_err("Could not look up %s\n", oh_name);
- goto free_name;
- }
- ohs[0] = oh;
- if (oh->dev_attr != NULL) {
- mmc_dev_attr = oh->dev_attr;
- mmc_data->controller_flags = mmc_dev_attr->flags;
- }
-
- pdev = platform_device_alloc(name, ctrl_nr - 1);
- if (!pdev) {
- pr_err("Could not allocate pdev for %s\n", name);
- goto free_name;
- }
- dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
-
- od = omap_device_alloc(pdev, ohs, 1);
- if (IS_ERR(od)) {
- pr_err("Could not allocate od for %s\n", name);
- goto put_pdev;
- }
-
- res = platform_device_add_data(pdev, mmc_data,
- sizeof(struct omap_hsmmc_platform_data));
- if (res) {
- pr_err("Could not add pdata for %s\n", name);
- goto put_pdev;
- }
-
- hsmmcinfo->pdev = pdev;
-
- res = omap_device_register(pdev);
- if (res) {
- pr_err("Could not register od for %s\n", name);
- goto free_od;
- }
-
- goto free_mmc;
-
-free_od:
- omap_device_delete(od);
-
-put_pdev:
- platform_device_put(pdev);
-
-free_name:
- kfree(mmc_data->name);
-
-free_mmc:
- kfree(mmc_data);
-}
-
-void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
-{
- if (omap_hsmmc_done)
- return;
-
- omap_hsmmc_done = 1;
-
- if (cpu_is_omap2430()) {
- control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
- control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
- } else {
- control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
- control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
- }
-
- for (; controllers->mmc; controllers++)
- omap_hsmmc_init_one(controllers, controllers->mmc);
-
-}
-
-#endif
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
deleted file mode 100644
index 76c5ed2..0000000
--- a/arch/arm/mach-omap2/hsmmc.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * MMC definitions for OMAP2
- */
-
-struct mmc_card;
-
-struct omap2_hsmmc_info {
- u8 mmc; /* controller 1/2/3 */
- u32 caps; /* 4/8 wires and any additional host
- * capabilities OR'd (ref. linux/mmc/host.h) */
- struct platform_device *pdev; /* mmc controller instance */
- /* init some special card */
- void (*init_card)(struct mmc_card *card);
-};
-
-#if IS_ENABLED(CONFIG_MMC_OMAP_HS)
-
-void omap_hsmmc_init(struct omap2_hsmmc_info *);
-void omap_hsmmc_late_init(struct omap2_hsmmc_info *);
-
-#else
-
-static inline void omap_hsmmc_init(struct omap2_hsmmc_info *info)
-{
-}
-
-static inline void omap_hsmmc_late_init(struct omap2_hsmmc_info *info)
-{
-}
-
-#endif
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 188ea52..59755b5 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -396,7 +396,6 @@
cpu_rev = "3.1";
break;
case 7:
- /* FALLTHROUGH */
default:
/* Use the latest known revision as default */
omap_revision = OMAP3430_REV_ES3_1_2;
@@ -416,7 +415,6 @@
cpu_rev = "1.0";
break;
case 1:
- /* FALLTHROUGH */
default:
omap_revision = AM35XX_REV_ES1_1;
cpu_rev = "1.1";
@@ -435,7 +433,6 @@
cpu_rev = "1.1";
break;
case 2:
- /* FALLTHROUGH */
default:
omap_revision = OMAP3630_REV_ES1_2;
cpu_rev = "1.2";
@@ -456,7 +453,6 @@
cpu_rev = "2.0";
break;
case 3:
- /* FALLTHROUGH */
default:
omap_revision = TI8168_REV_ES2_1;
cpu_rev = "2.1";
@@ -473,7 +469,6 @@
cpu_rev = "2.0";
break;
case 2:
- /* FALLTHROUGH */
default:
omap_revision = AM335X_REV_ES2_1;
cpu_rev = "2.1";
@@ -491,7 +486,6 @@
cpu_rev = "1.1";
break;
case 2:
- /* FALLTHROUGH */
default:
omap_revision = AM437X_REV_ES1_2;
cpu_rev = "1.2";
@@ -502,7 +496,6 @@
case 0xb968:
switch (rev) {
case 0:
- /* FALLTHROUGH */
case 1:
omap_revision = TI8148_REV_ES1_0;
cpu_rev = "1.0";
@@ -512,7 +505,6 @@
cpu_rev = "2.0";
break;
case 3:
- /* FALLTHROUGH */
default:
omap_revision = TI8148_REV_ES2_1;
cpu_rev = "2.1";
@@ -775,19 +767,23 @@
return kasprintf(GFP_KERNEL, "Unknown");
}
-static ssize_t omap_get_type(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t
+type_show(struct device *dev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%s\n", omap_types[omap_type()]);
}
-static struct device_attribute omap_soc_attr =
- __ATTR(type, S_IRUGO, omap_get_type, NULL);
+static DEVICE_ATTR_RO(type);
+
+static struct attribute *omap_soc_attrs[] = {
+ &dev_attr_type.attr,
+ NULL
+};
+
+ATTRIBUTE_GROUPS(omap_soc);
void __init omap_soc_device_init(void)
{
- struct device *parent;
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
@@ -798,14 +794,12 @@
soc_dev_attr->machine = soc_name;
soc_dev_attr->family = omap_get_family();
soc_dev_attr->revision = soc_rev;
+ soc_dev_attr->custom_attr_group = omap_soc_groups[0];
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
kfree(soc_dev_attr);
return;
}
-
- parent = soc_device_to_device(soc_dev);
- device_create_file(parent, &omap_soc_attr);
}
#endif /* CONFIG_SOC_BUS */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 349e480..27608d1 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -51,6 +51,7 @@
#include "prm33xx.h"
#include "prm44xx.h"
#include "opp2xxx.h"
+#include "omap-secure.h"
/*
* omap_clk_soc_init: points to a function that does the SoC-specific
@@ -481,6 +482,7 @@
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
+ omap_secure_init();
}
void __init omap3430_init_early(void)
@@ -533,6 +535,7 @@
dm814x_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = dm814x_dt_clk_init;
+ omap_secure_init();
}
void __init ti816x_init_early(void)
@@ -549,6 +552,7 @@
dm816x_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = dm816x_dt_clk_init;
+ omap_secure_init();
}
#endif
@@ -566,6 +570,7 @@
am33xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = am33xx_dt_clk_init;
+ omap_secure_init();
}
void __init am33xx_init_late(void)
@@ -589,6 +594,7 @@
omap_hwmod_init_postsetup();
omap_l2_cache_init();
omap_clk_soc_init = am43xx_dt_clk_init;
+ omap_secure_init();
}
void __init am43xx_init_late(void)
@@ -617,6 +623,7 @@
omap_hwmod_init_postsetup();
omap_l2_cache_init();
omap_clk_soc_init = omap4xxx_dt_clk_init;
+ omap_secure_init();
}
void __init omap4430_init_late(void)
@@ -643,6 +650,7 @@
omap54xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap5xxx_dt_clk_init;
+ omap_secure_init();
}
void __init omap5_init_late(void)
@@ -666,6 +674,7 @@
dra7xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = dra7xx_dt_clk_init;
+ omap_secure_init();
}
void __init dra7xx_init_late(void)
diff --git a/arch/arm/mach-omap2/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h
index c2bd8d8..6297c62 100644
--- a/arch/arm/mach-omap2/l3_2xxx.h
+++ b/arch/arm/mach-omap2/l3_2xxx.h
@@ -2,7 +2,7 @@
/*
* arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Sumit Semwal
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
diff --git a/arch/arm/mach-omap2/l3_3xxx.h b/arch/arm/mach-omap2/l3_3xxx.h
index 995ebcc..60ea7b2 100644
--- a/arch/arm/mach-omap2/l3_3xxx.h
+++ b/arch/arm/mach-omap2/l3_3xxx.h
@@ -2,7 +2,7 @@
/*
* arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Sumit Semwal
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
diff --git a/arch/arm/mach-omap2/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h
index 556e69c..418e107 100644
--- a/arch/arm/mach-omap2/l4_2xxx.h
+++ b/arch/arm/mach-omap2/l4_2xxx.h
@@ -2,7 +2,7 @@
/*
* arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
* Sumit Semwal
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h
index 7f4e053..b5533e9 100644
--- a/arch/arm/mach-omap2/mmc.h
+++ b/arch/arm/mach-omap2/mmc.h
@@ -16,7 +16,3 @@
return 0;
}
#endif
-
-/* called from board-specific card detection service routine */
-extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
- int is_closed);
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 78247e6..93c20bb 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -2,25 +2,33 @@
/*
* OMAP IOMMU quirks for various TI SoCs
*
- * Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2019 Texas Instruments Incorporated - https://www.ti.com/
* Suman Anna <s-anna@ti.com>
*/
#include <linux/platform_device.h>
#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/list.h>
-#include "omap_hwmod.h"
-#include "omap_device.h"
#include "clockdomain.h"
#include "powerdomain.h"
+struct pwrdm_link {
+ struct device *dev;
+ struct powerdomain *pwrdm;
+ struct list_head node;
+};
+
+static DEFINE_SPINLOCK(iommu_lock);
+static struct clockdomain *emu_clkdm;
+static atomic_t emu_count;
+
static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev,
bool enable)
{
- static struct clockdomain *emu_clkdm;
- static DEFINE_SPINLOCK(emu_lock);
- static atomic_t count;
struct device_node *np = pdev->dev.of_node;
+ unsigned long flags;
if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
return;
@@ -31,34 +39,87 @@
return;
}
- spin_lock(&emu_lock);
+ spin_lock_irqsave(&iommu_lock, flags);
- if (enable && (atomic_inc_return(&count) == 1))
+ if (enable && (atomic_inc_return(&emu_count) == 1))
clkdm_deny_idle(emu_clkdm);
- else if (!enable && (atomic_dec_return(&count) == 0))
+ else if (!enable && (atomic_dec_return(&emu_count) == 0))
clkdm_allow_idle(emu_clkdm);
- spin_unlock(&emu_lock);
+ spin_unlock_irqrestore(&iommu_lock, flags);
+}
+
+static struct powerdomain *_get_pwrdm(struct device *dev)
+{
+ struct clk *clk;
+ struct clk_hw_omap *hwclk;
+ struct clockdomain *clkdm;
+ struct powerdomain *pwrdm = NULL;
+ struct pwrdm_link *entry;
+ unsigned long flags;
+ static LIST_HEAD(cache);
+
+ spin_lock_irqsave(&iommu_lock, flags);
+
+ list_for_each_entry(entry, &cache, node) {
+ if (entry->dev == dev) {
+ pwrdm = entry->pwrdm;
+ break;
+ }
+ }
+
+ spin_unlock_irqrestore(&iommu_lock, flags);
+
+ if (pwrdm)
+ return pwrdm;
+
+ clk = of_clk_get(dev->of_node->parent, 0);
+ if (IS_ERR(clk)) {
+ dev_err(dev, "no fck found\n");
+ return NULL;
+ }
+
+ hwclk = to_clk_hw_omap(__clk_get_hw(clk));
+ clk_put(clk);
+ if (!hwclk || !hwclk->clkdm_name) {
+ dev_err(dev, "no hwclk data\n");
+ return NULL;
+ }
+
+ clkdm = clkdm_lookup(hwclk->clkdm_name);
+ if (!clkdm) {
+ dev_err(dev, "clkdm not found: %s\n", hwclk->clkdm_name);
+ return NULL;
+ }
+
+ pwrdm = clkdm_get_pwrdm(clkdm);
+ if (!pwrdm) {
+ dev_err(dev, "pwrdm not found: %s\n", clkdm->name);
+ return NULL;
+ }
+
+ entry = kmalloc(sizeof(*entry), GFP_KERNEL);
+ if (entry) {
+ entry->dev = dev;
+ entry->pwrdm = pwrdm;
+ spin_lock_irqsave(&iommu_lock, flags);
+ list_add(&entry->node, &cache);
+ spin_unlock_irqrestore(&iommu_lock, flags);
+ }
+
+ return pwrdm;
}
int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
u8 *pwrst)
{
struct powerdomain *pwrdm;
- struct omap_device *od;
u8 next_pwrst;
int ret = 0;
- od = to_omap_device(pdev);
- if (!od)
- return -ENODEV;
-
- if (od->hwmods_cnt != 1)
- return -EINVAL;
-
- pwrdm = omap_hwmod_get_pwrdm(od->hwmods[0]);
+ pwrdm = _get_pwrdm(&pdev->dev);
if (!pwrdm)
- return -EINVAL;
+ return -ENODEV;
if (request) {
*pwrst = pwrdm_read_next_pwrst(pwrdm);
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 2d8f905..9fba98c 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -42,7 +42,6 @@
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/smp_scu.h>
-#include <asm/pgalloc.h>
#include <asm/suspend.h>
#include <asm/virt.h>
#include <asm/hardware/cache-l2x0.h>
@@ -227,7 +226,6 @@
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
- unsigned int wakeup_cpu;
if (omap_rev() == OMAP4430_REV_ES1_0)
return -ENXIO;
@@ -292,7 +290,6 @@
* secure devices, CPUx does WFI which can result in
* domain transition
*/
- wakeup_cpu = smp_processor_id();
pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
pwrdm_post_transition(NULL);
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index 24298e4..0659ab4 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -5,21 +5,47 @@
* Copyright (C) 2011 Texas Instruments, Inc.
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
- * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
+ * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
*/
+#include <linux/arm-smccc.h>
+#include <linux/cpu_pm.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/memblock.h>
+#include <linux/of.h>
#include <asm/cacheflush.h>
#include <asm/memblock.h>
+#include "common.h"
#include "omap-secure.h"
+#include "soc.h"
static phys_addr_t omap_secure_memblock_base;
+bool optee_available;
+
+#define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \
+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \
+ ARM_SMCCC_OWNER_SIP, (func_num))
+
+static void __init omap_optee_init_check(void)
+{
+ struct device_node *np;
+
+ /*
+ * We only check that the OP-TEE node is present and available. The
+ * OP-TEE kernel driver is not needed for the type of interaction made
+ * with OP-TEE here so the driver's status is not checked.
+ */
+ np = of_find_node_by_path("/firmware/optee");
+ if (np && of_device_is_available(np))
+ optee_available = true;
+ of_node_put(np);
+}
+
/**
* omap_sec_dispatcher: Routine to dispatch low power secure
* service routines
@@ -53,6 +79,27 @@
return ret;
}
+void omap_smccc_smc(u32 fn, u32 arg)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg,
+ 0, 0, 0, 0, 0, 0, &res);
+ WARN(res.a0, "Secure function call 0x%08x failed\n", fn);
+}
+
+void omap_smc1(u32 fn, u32 arg)
+{
+ /*
+ * If this platform has OP-TEE installed we use ARM SMC calls
+ * otherwise fall back to the OMAP ROM style calls.
+ */
+ if (optee_available)
+ omap_smccc_smc(fn, arg);
+ else
+ _omap_smc1(fn, arg);
+}
+
/* Allocate the memory to save secure ram */
int __init omap_secure_ram_reserve_memblock(void)
{
@@ -163,3 +210,45 @@
NO_FLAG,
3, ptr, count, flag, 0);
}
+
+void __init omap_secure_init(void)
+{
+ omap_optee_init_check();
+}
+
+/*
+ * Dummy dispatcher call after core OSWR and MPU off. Updates the ROM return
+ * address after MMU has been re-enabled after CPU1 has been woken up again.
+ * Otherwise the ROM code will attempt to use the earlier physical return
+ * address that got set with MMU off when waking up CPU1. Only used on secure
+ * devices.
+ */
+static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
+{
+ switch (cmd) {
+ case CPU_CLUSTER_PM_EXIT:
+ omap_secure_dispatcher(OMAP4_PPA_SERVICE_0,
+ FLAG_START_CRITICAL,
+ 0, 0, 0, 0, 0);
+ break;
+ default:
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block secure_notifier_block = {
+ .notifier_call = cpu_notifier,
+};
+
+static int __init secure_pm_init(void)
+{
+ if (omap_type() == OMAP2_DEVICE_TYPE_GP || !soc_is_omap44xx())
+ return 0;
+
+ cpu_pm_register_notifier(&secure_notifier_block);
+
+ return 0;
+}
+omap_arch_initcall(secure_pm_init);
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 20046e8..172069f 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -5,11 +5,13 @@
* Copyright (C) 2011 Texas Instruments, Inc.
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
- * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
+ * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
*/
#ifndef OMAP_ARCH_OMAP_SECURE_H
#define OMAP_ARCH_OMAP_SECURE_H
+#include <linux/types.h>
+
/* Monitor error code */
#define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
#define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
@@ -48,9 +50,13 @@
#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
/* Secure PPA(Primary Protected Application) APIs */
+#define OMAP4_PPA_SERVICE_0 0x21
#define OMAP4_PPA_L2_POR_INDEX 0x23
#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
+#define AM43xx_PPA_SVC_PM_SUSPEND 0x71
+#define AM43xx_PPA_SVC_PM_RESUME 0x72
+
/* Secure RX-51 PPA (Primary Protected Application) APIs */
#define RX51_PPA_HWRNG 29
#define RX51_PPA_L2_INVAL 40
@@ -60,6 +66,8 @@
extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
u32 arg1, u32 arg2, u32 arg3, u32 arg4);
+extern void omap_smccc_smc(u32 fn, u32 arg);
+extern void omap_smc1(u32 fn, u32 arg);
extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
extern phys_addr_t omap_secure_ram_mempool_base(void);
@@ -72,6 +80,9 @@
extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
+extern bool optee_available;
+void omap_secure_init(void);
+
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
void set_cntfreq(void);
#else
diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S
index fd2bcd9..7376f52 100644
--- a/arch/arm/mach-omap2/omap-smc.S
+++ b/arch/arm/mach-omap2/omap-smc.S
@@ -6,7 +6,7 @@
* Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
- * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
+ * Copyright (C) 2013 Pali Rohár <pali@kernel.org>
*/
#include <linux/linkage.h>
@@ -18,18 +18,18 @@
* the monitor API number. It uses few CPU registers
* internally and hence they need be backed up including
* link register "lr".
- * Function signature : void omap_smc1(u32 fn, u32 arg)
+ * Function signature : void _omap_smc1(u32 fn, u32 arg)
*/
.arch armv7-a
.arch_extension sec
-ENTRY(omap_smc1)
+ENTRY(_omap_smc1)
stmfd sp!, {r2-r12, lr}
mov r12, r0
mov r0, r1
dsb
smc #0
ldmfd sp!, {r2-r12, pc}
-ENDPROC(omap_smc1)
+ENDPROC(_omap_smc1)
/**
* u32 omap_smc2(u32 id, u32 falg, u32 pargs)
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 6a82fce..570a987 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -72,7 +72,7 @@
}
#ifdef CONFIG_OMAP5_ERRATA_801819
-void omap5_erratum_workaround_801819(void)
+static void omap5_erratum_workaround_801819(void)
{
u32 acr, revidr;
u32 acr_mask;
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index f85a0fd..64b23b0 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -119,11 +119,7 @@
/**
* omap_device_build_from_dt - build an omap_device with multiple hwmods
- * @pdev_name: name of the platform_device driver to use
- * @pdev_id: this platform_device's connection ID
- * @oh: ptr to the single omap_hwmod that backs this omap_device
- * @pdata: platform_data ptr to associate with the platform_device
- * @pdata_len: amount of memory pointed to by @pdata
+ * @pdev: The platform device to update.
*
* Function for building an omap_device already registered from device-tree
*
@@ -246,7 +242,7 @@
if (pdev->dev.of_node)
omap_device_build_from_dt(pdev);
omap_auxdata_legacy_init(dev);
- /* fall through */
+ fallthrough;
default:
od = to_omap_device(pdev);
if (od)
@@ -294,7 +290,7 @@
/**
* omap_device_get_context_loss_count - get lost context count
- * @od: struct omap_device *
+ * @pdev: The platform device to update.
*
* Using the primary hwmod, query the context loss count for this
* device.
@@ -323,9 +319,8 @@
/**
* omap_device_alloc - allocate an omap_device
* @pdev: platform_device that will be included in this omap_device
- * @oh: ptr to the single omap_hwmod that backs this omap_device
- * @pdata: platform_data ptr to associate with the platform_device
- * @pdata_len: amount of memory pointed to by @pdata
+ * @ohs: ptr to the omap_hwmod for this omap_device
+ * @oh_cnt: the size of the ohs list
*
* Convenience function for allocating an omap_device structure and filling
* hwmods, and resources.
@@ -380,176 +375,6 @@
kfree(od);
}
-/**
- * omap_device_copy_resources - Add legacy IO and IRQ resources
- * @oh: interconnect target module
- * @pdev: platform device to copy resources to
- *
- * We still have legacy DMA and smartreflex needing resources.
- * Let's populate what they need until we can eventually just
- * remove this function. Note that there should be no need to
- * call this from omap_device_build_from_dt(), nor should there
- * be any need to call it for other devices.
- */
-static int
-omap_device_copy_resources(struct omap_hwmod *oh,
- struct platform_device *pdev)
-{
- struct device_node *np, *child;
- struct property *prop;
- struct resource *res;
- const char *name;
- int error, irq = 0;
-
- if (!oh || !oh->od || !oh->od->pdev)
- return -EINVAL;
-
- np = oh->od->pdev->dev.of_node;
- if (!np) {
- error = -ENODEV;
- goto error;
- }
-
- res = kcalloc(2, sizeof(*res), GFP_KERNEL);
- if (!res)
- return -ENOMEM;
-
- /* Do we have a dts range for the interconnect target module? */
- error = omap_hwmod_parse_module_range(oh, np, res);
-
- /* No ranges, rely on device reg entry */
- if (error)
- error = of_address_to_resource(np, 0, res);
- if (error)
- goto free;
-
- /* SmartReflex needs first IO resource name to be "mpu" */
- res[0].name = "mpu";
-
- /*
- * We may have a configured "ti,sysc" interconnect target with a
- * dts child with the interrupt. If so use the first child's
- * first interrupt for "ti-hwmods" legacy support.
- */
- of_property_for_each_string(np, "compatible", prop, name)
- if (!strncmp("ti,sysc-", name, 8))
- break;
-
- child = of_get_next_available_child(np, NULL);
-
- if (name)
- irq = irq_of_parse_and_map(child, 0);
- if (!irq)
- irq = irq_of_parse_and_map(np, 0);
- if (!irq) {
- error = -EINVAL;
- goto free;
- }
-
- /* Legacy DMA code needs interrupt name to be "0" */
- res[1].start = irq;
- res[1].end = irq;
- res[1].flags = IORESOURCE_IRQ;
- res[1].name = "0";
-
- error = platform_device_add_resources(pdev, res, 2);
-
-free:
- kfree(res);
-
-error:
- WARN(error, "%s: %s device %s failed: %i\n",
- __func__, oh->name, dev_name(&pdev->dev),
- error);
-
- return error;
-}
-
-/**
- * omap_device_build - build and register an omap_device with one omap_hwmod
- * @pdev_name: name of the platform_device driver to use
- * @pdev_id: this platform_device's connection ID
- * @oh: ptr to the single omap_hwmod that backs this omap_device
- * @pdata: platform_data ptr to associate with the platform_device
- * @pdata_len: amount of memory pointed to by @pdata
- *
- * Convenience function for building and registering a single
- * omap_device record, which in turn builds and registers a
- * platform_device record. See omap_device_build_ss() for more
- * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
- * passes along the return value of omap_device_build_ss().
- */
-struct platform_device __init *omap_device_build(const char *pdev_name,
- int pdev_id,
- struct omap_hwmod *oh,
- void *pdata, int pdata_len)
-{
- int ret = -ENOMEM;
- struct platform_device *pdev;
- struct omap_device *od;
-
- if (!oh || !pdev_name)
- return ERR_PTR(-EINVAL);
-
- if (!pdata && pdata_len > 0)
- return ERR_PTR(-EINVAL);
-
- if (strncmp(oh->name, "smartreflex", 11) &&
- strncmp(oh->name, "dma", 3)) {
- pr_warn("%s need to update %s to probe with dt\na",
- __func__, pdev_name);
- ret = -ENODEV;
- goto odbs_exit;
- }
-
- pdev = platform_device_alloc(pdev_name, pdev_id);
- if (!pdev) {
- ret = -ENOMEM;
- goto odbs_exit;
- }
-
- /* Set the dev_name early to allow dev_xxx in omap_device_alloc */
- if (pdev->id != -1)
- dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
- else
- dev_set_name(&pdev->dev, "%s", pdev->name);
-
- /*
- * Must be called before omap_device_alloc() as oh->od
- * only contains the currently registered omap_device
- * and will get overwritten by omap_device_alloc().
- */
- ret = omap_device_copy_resources(oh, pdev);
- if (ret)
- goto odbs_exit1;
-
- od = omap_device_alloc(pdev, &oh, 1);
- if (IS_ERR(od)) {
- ret = PTR_ERR(od);
- goto odbs_exit1;
- }
-
- ret = platform_device_add_data(pdev, pdata, pdata_len);
- if (ret)
- goto odbs_exit2;
-
- ret = omap_device_register(pdev);
- if (ret)
- goto odbs_exit2;
-
- return pdev;
-
-odbs_exit2:
- omap_device_delete(od);
-odbs_exit1:
- platform_device_put(pdev);
-odbs_exit:
-
- pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
-
- return ERR_PTR(ret);
-}
-
#ifdef CONFIG_PM
static int _od_runtime_suspend(struct device *dev)
{
@@ -651,7 +476,7 @@
/**
* omap_device_register - register an omap_device with one omap_hwmod
- * @od: struct omap_device * to register
+ * @pdev: the platform device (omap_device) to register.
*
* Register the omap_device structure. This currently just calls
* platform_device_register() on the underlying platform_device.
@@ -670,7 +495,7 @@
/**
* omap_device_enable - fully activate an omap_device
- * @od: struct omap_device * to activate
+ * @pdev: the platform device to activate
*
* Do whatever is necessary for the hwmods underlying omap_device @od
* to be accessible and ready to operate. This generally involves
@@ -704,7 +529,7 @@
/**
* omap_device_idle - idle an omap_device
- * @od: struct omap_device * to idle
+ * @pdev: The platform_device (omap_device) to idle
*
* Idle omap_device @od. Device drivers call this function indirectly
* via pm_runtime_put*(). Returns -EINVAL if the omap_device is not
diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h
index ced775e..f77e76a 100644
--- a/arch/arm/mach-omap2/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -68,10 +68,6 @@
/* Core code interface */
-struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
- struct omap_hwmod *oh, void *pdata,
- int pdata_len);
-
struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_hwmod **ohs, int oh_cnt);
void omap_device_delete(struct omap_device *od);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index eb74aa1..1fd67ab 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -623,39 +623,6 @@
return 0;
}
-/**
- * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
- * @oh: struct omap_hwmod *
- *
- * Prevent the hardware module @oh to send wakeups. Returns -EINVAL
- * upon error or 0 upon success.
- */
-static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
-{
- if (!oh->class->sysc ||
- !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
- (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
- (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
- return -EINVAL;
-
- if (!oh->class->sysc->sysc_fields) {
- WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
- return -EINVAL;
- }
-
- if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
- *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
-
- if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
- _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
- if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
- _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v);
-
- /* XXX test pwrdm_get_wken for this hwmod's subsystem */
-
- return 0;
-}
-
static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
{
struct clk_hw_omap *clk;
@@ -782,8 +749,10 @@
for_each_matching_node(np, ti_clkctrl_match_table) {
ret = _setup_clkctrl_provider(np);
- if (ret)
+ if (ret) {
+ of_node_put(np);
break;
+ }
}
return ret;
@@ -1886,23 +1855,6 @@
}
/**
- * _enable_preprogram - Pre-program an IP block during the _enable() process
- * @oh: struct omap_hwmod *
- *
- * Some IP blocks (such as AESS) require some additional programming
- * after enable before they can enter idle. If a function pointer to
- * do so is present in the hwmod data, then call it and pass along the
- * return value; otherwise, return 0.
- */
-static int _enable_preprogram(struct omap_hwmod *oh)
-{
- if (!oh->class->enable_preprogram)
- return 0;
-
- return oh->class->enable_preprogram(oh);
-}
-
-/**
* _enable - enable an omap_hwmod
* @oh: struct omap_hwmod *
*
@@ -1985,7 +1937,6 @@
_update_sysc_cache(oh);
_enable_sysc(oh);
}
- r = _enable_preprogram(oh);
} else {
if (soc_ops.disable_module)
soc_ops.disable_module(oh);
@@ -3199,15 +3150,14 @@
/**
* omap_hwmod_init_regbits - init sysconfig specific register bits
* @dev: struct device
+ * @oh: module
* @data: module data
* @sysc_fields: new sysc configuration
*/
-static int omap_hwmod_init_regbits(struct device *dev,
+static int omap_hwmod_init_regbits(struct device *dev, struct omap_hwmod *oh,
const struct ti_sysc_module_data *data,
struct sysc_regbits **sysc_fields)
{
- *sysc_fields = NULL;
-
switch (data->cap->type) {
case TI_SYSC_OMAP2:
case TI_SYSC_OMAP2_TIMER:
@@ -3242,6 +3192,12 @@
*sysc_fields = &omap_hwmod_sysc_type_usb_host_fs;
break;
default:
+ *sysc_fields = NULL;
+ if (!oh->class->sysc->sysc_fields)
+ return 0;
+
+ dev_err(dev, "sysc_fields not found\n");
+
return -EINVAL;
}
@@ -3407,9 +3363,9 @@
if (!oh->class->sysc)
return -ENODEV;
- if (sysc_fields != oh->class->sysc->sysc_fields)
- dev_warn(dev, "sysc_fields %p != %p\n", sysc_fields,
- oh->class->sysc->sysc_fields);
+ if (oh->class->sysc->sysc_fields &&
+ sysc_fields != oh->class->sysc->sysc_fields)
+ dev_warn(dev, "sysc_fields mismatch\n");
if (rev_offs != oh->class->sysc->rev_offs)
dev_warn(dev, "rev_offs %08x != %08x\n", rev_offs,
@@ -3481,7 +3437,7 @@
regs = ioremap(data->module_pa,
data->module_size);
if (!regs)
- return -ENOMEM;
+ goto out_free_sysc;
}
/*
@@ -3491,13 +3447,13 @@
if (oh->class->name && strcmp(oh->class->name, data->name)) {
class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL);
if (!class)
- return -ENOMEM;
+ goto out_unmap;
}
if (list_empty(&oh->slave_ports)) {
oi = kcalloc(1, sizeof(*oi), GFP_KERNEL);
if (!oi)
- return -ENOMEM;
+ goto out_free_class;
/*
* Note that we assume interconnect interface clocks will be
@@ -3524,6 +3480,14 @@
spin_unlock_irqrestore(&oh->_lock, flags);
return 0;
+
+out_free_class:
+ kfree(class);
+out_unmap:
+ iounmap(regs);
+out_free_sysc:
+ kfree(sysc);
+ return -ENOMEM;
}
static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
@@ -3625,7 +3589,7 @@
cookie->data = oh;
- error = omap_hwmod_init_regbits(dev, data, &sysc_fields);
+ error = omap_hwmod_init_regbits(dev, oh, data, &sysc_fields);
if (error)
return error;
@@ -3656,6 +3620,8 @@
oh->flags |= HWMOD_SWSUP_SIDLE_ACT;
if (data->cfg->quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
oh->flags |= HWMOD_SWSUP_MSTANDBY;
+ if (data->cfg->quirks & SYSC_QUIRK_CLKDM_NOAUTO)
+ oh->flags |= HWMOD_CLKDM_NOAUTO;
error = omap_hwmod_check_module(dev, oh, data, sysc_fields,
rev_offs, sysc_offs, syss_offs,
@@ -3815,6 +3781,7 @@
struct omap_hwmod_ocp_if *oi;
struct clockdomain *clkdm;
struct clk_hw_omap *clk;
+ struct clk_hw *hw;
if (!oh)
return NULL;
@@ -3831,7 +3798,14 @@
c = oi->_clk;
}
- clk = to_clk_hw_omap(__clk_get_hw(c));
+ hw = __clk_get_hw(c);
+ if (!hw)
+ return NULL;
+
+ clk = to_clk_hw_omap(hw);
+ if (!clk)
+ return NULL;
+
clkdm = clk->clkdm;
if (!clkdm)
return NULL;
@@ -3868,70 +3842,6 @@
*/
/**
- * omap_hwmod_enable_wakeup - allow device to wake up the system
- * @oh: struct omap_hwmod *
- *
- * Sets the module OCP socket ENAWAKEUP bit to allow the module to
- * send wakeups to the PRCM, and enable I/O ring wakeup events for
- * this IP block if it has dynamic mux entries. Eventually this
- * should set PRCM wakeup registers to cause the PRCM to receive
- * wakeup events from the module. Does not set any wakeup routing
- * registers beyond this point - if the module is to wake up any other
- * module or subsystem, that must be set separately. Called by
- * omap_device code. Returns -EINVAL on error or 0 upon success.
- */
-int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
-{
- unsigned long flags;
- u32 v;
-
- spin_lock_irqsave(&oh->_lock, flags);
-
- if (oh->class->sysc &&
- (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
- v = oh->_sysc_cache;
- _enable_wakeup(oh, &v);
- _write_sysconfig(v, oh);
- }
-
- spin_unlock_irqrestore(&oh->_lock, flags);
-
- return 0;
-}
-
-/**
- * omap_hwmod_disable_wakeup - prevent device from waking the system
- * @oh: struct omap_hwmod *
- *
- * Clears the module OCP socket ENAWAKEUP bit to prevent the module
- * from sending wakeups to the PRCM, and disable I/O ring wakeup
- * events for this IP block if it has dynamic mux entries. Eventually
- * this should clear PRCM wakeup registers to cause the PRCM to ignore
- * wakeup events from the module. Does not set any wakeup routing
- * registers beyond this point - if the module is to wake up any other
- * module or subsystem, that must be set separately. Called by
- * omap_device code. Returns -EINVAL on error or 0 upon success.
- */
-int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
-{
- unsigned long flags;
- u32 v;
-
- spin_lock_irqsave(&oh->_lock, flags);
-
- if (oh->class->sysc &&
- (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
- v = oh->_sysc_cache;
- _disable_wakeup(oh, &v);
- _write_sysconfig(v, oh);
- }
-
- spin_unlock_irqrestore(&oh->_lock, flags);
-
- return 0;
-}
-
-/**
* omap_hwmod_assert_hardreset - assert the HW reset line of submodules
* contained in the hwmod module.
* @oh: struct omap_hwmod *
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index ef1bb08..eebf2fd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -501,7 +501,6 @@
* @sysc: device SYSCONFIG/SYSSTATUS register data
* @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
* @reset: ptr to fn to be executed in place of the standard hwmod reset fn
- * @enable_preprogram: ptr to fn to be executed during device enable
* @lock: ptr to fn to be executed to lock IP registers
* @unlock: ptr to fn to be executed to unlock IP registers
*
@@ -526,7 +525,6 @@
struct omap_hwmod_class_sysconfig *sysc;
int (*pre_shutdown)(struct omap_hwmod *oh);
int (*reset)(struct omap_hwmod *oh);
- int (*enable_preprogram)(struct omap_hwmod *oh);
void (*lock)(struct omap_hwmod *oh);
void (*unlock)(struct omap_hwmod *oh);
};
@@ -646,9 +644,6 @@
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
-int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
-int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
-
int omap_hwmod_for_each_by_class(const char *classname,
int (*fn)(struct omap_hwmod *oh,
void *user),
@@ -665,7 +660,6 @@
*
*/
-extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh);
void omap_hwmod_rtc_unlock(struct omap_hwmod *oh);
void omap_hwmod_rtc_lock(struct omap_hwmod *oh);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index d49df96..558fae4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -11,7 +11,6 @@
*/
#include <linux/platform_data/i2c-omap.h>
-#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
@@ -126,21 +125,6 @@
.flags = HWMOD_16BIT_REG,
};
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32,
- .lch_count = 32,
-};
-
-static struct omap_hwmod omap2420_dma_system_hwmod = {
- .name = "dma",
- .class = &omap2xxx_dma_hwmod_class,
- .main_clk = "core_l3_ck",
- .dev_attr = &dma_dev_attr,
- .flags = HWMOD_NO_IDLEST,
-};
-
/* mailbox */
static struct omap_hwmod omap2420_mailbox_hwmod = {
.name = "mailbox",
@@ -280,14 +264,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_timer1_hwmod,
- .clk = "gpt1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
.master = &omap2xxx_l4_wkup_hwmod,
@@ -328,22 +304,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
- .master = &omap2420_dma_system_hwmod,
- .slave = &omap2xxx_l3_main_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dma_system */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2420_dma_system_hwmod,
- .clk = "sdma_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
.master = &omap2xxx_l4_core_hwmod,
@@ -384,15 +344,6 @@
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
-
-/* l4_wkup -> 32ksync_counter */
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_counter_32k_hwmod,
- .clk = "sync_32k_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
.master = &omap2xxx_l3_main_hwmod,
.slave = &omap2xxx_gpmc_hwmod,
@@ -414,8 +365,6 @@
&omap2420_l4_core__i2c2,
&omap2420_l3__iva,
&omap2420_l3__dsp,
- &omap2420_l4_wkup__timer1,
- &omap2xxx_l4_core__timer2,
&omap2xxx_l4_core__timer3,
&omap2xxx_l4_core__timer4,
&omap2xxx_l4_core__timer5,
@@ -435,8 +384,6 @@
&omap2420_l4_wkup__gpio2,
&omap2420_l4_wkup__gpio3,
&omap2420_l4_wkup__gpio4,
- &omap2420_dma_system__l3,
- &omap2420_l4_core__dma_system,
&omap2420_l4_core__mailbox,
&omap2420_l4_core__mcbsp1,
&omap2420_l4_core__mcbsp2,
@@ -445,7 +392,6 @@
&omap2xxx_l4_core__sham,
&omap2xxx_l4_core__aes,
&omap2420_l4_core__hdq1w,
- &omap2420_l4_wkup__counter_32k,
&omap2420_l3__gpmc,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c51ef84..c932008 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -12,7 +12,6 @@
#include <linux/platform_data/i2c-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
-#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
@@ -121,21 +120,6 @@
.class = &omap2xxx_gpio_hwmod_class,
};
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-static struct omap_hwmod omap2430_dma_system_hwmod = {
- .name = "dma",
- .class = &omap2xxx_dma_hwmod_class,
- .main_clk = "core_l3_ck",
- .dev_attr = &dma_dev_attr,
- .flags = HWMOD_NO_IDLEST,
-};
-
/* mailbox */
static struct omap_hwmod omap2430_mailbox_hwmod = {
.name = "mailbox",
@@ -452,14 +436,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_timer1_hwmod,
- .clk = "gpt1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
.master = &omap2xxx_l4_wkup_hwmod,
@@ -508,22 +484,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
- .master = &omap2430_dma_system_hwmod,
- .slave = &omap2xxx_l3_main_hwmod,
- .clk = "core_l3_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_core -> dma_system */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2430_dma_system_hwmod,
- .clk = "sdma_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
.master = &omap2xxx_l4_core_hwmod,
@@ -580,14 +540,6 @@
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
-/* l4_wkup -> 32ksync_counter */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
- .master = &omap2xxx_l4_wkup_hwmod,
- .slave = &omap2xxx_counter_32k_hwmod,
- .clk = "sync_32k_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
.master = &omap2xxx_l3_main_hwmod,
.slave = &omap2xxx_gpmc_hwmod,
@@ -613,8 +565,6 @@
&omap2xxx_l4_core__mcspi2,
&omap2430_l4_core__mcspi3,
&omap2430_l3__iva,
- &omap2430_l4_wkup__timer1,
- &omap2xxx_l4_core__timer2,
&omap2xxx_l4_core__timer3,
&omap2xxx_l4_core__timer4,
&omap2xxx_l4_core__timer5,
@@ -635,8 +585,6 @@
&omap2430_l4_wkup__gpio3,
&omap2430_l4_wkup__gpio4,
&omap2430_l4_core__gpio5,
- &omap2430_dma_system__l3,
- &omap2430_l4_core__dma_system,
&omap2430_l4_core__mailbox,
&omap2430_l4_core__mcbsp1,
&omap2430_l4_core__mcbsp2,
@@ -647,7 +595,6 @@
&omap2xxx_l4_core__rng,
&omap2xxx_l4_core__sham,
&omap2xxx_l4_core__aes,
- &omap2430_l4_wkup__counter_32k,
&omap2430_l3__gpmc,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index eef96ad..518e877 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -95,14 +95,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_core -> timer2 */
-struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
- .master = &omap2xxx_l4_core_hwmod,
- .slave = &omap2xxx_timer2_hwmod,
- .clk = "gpt2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_core -> timer3 */
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
.master = &omap2xxx_l4_core_hwmod,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index f767524..9156f2b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -7,7 +7,6 @@
*/
#include <linux/types.h>
-#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
@@ -95,23 +94,6 @@
.sysc = &omap2xxx_gpio_sysc,
};
-/* system dma */
-static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap2xxx_dma_sysc,
-};
-
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors
@@ -213,36 +195,6 @@
.class = &iva_hwmod_class,
};
-/* timer1 */
-struct omap_hwmod omap2xxx_timer1_hwmod = {
- .name = "timer1",
- .main_clk = "gpt1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer2 */
-struct omap_hwmod omap2xxx_timer2_hwmod = {
- .name = "timer2",
- .main_clk = "gpt2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
- },
- },
- .class = &omap2xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
/* timer3 */
struct omap_hwmod omap2xxx_timer3_hwmod = {
.name = "timer3",
@@ -613,23 +565,6 @@
.class = &omap2xxx_mcspi_class,
};
-static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
- .name = "counter",
-};
-
-struct omap_hwmod omap2xxx_counter_32k_hwmod = {
- .name = "counter_32k",
- .main_clk = "func_32k_ck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
- },
- },
- .class = &omap2xxx_counter_hwmod_class,
-};
-
/* gpmc */
struct omap_hwmod omap2xxx_gpmc_hwmod = {
.name = "gpmc",
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
index 3de3d7a..e298410 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
@@ -24,37 +24,11 @@
extern struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr;
extern struct omap_hwmod_ocp_if am33xx_mpu__prcm;
extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main;
-extern struct omap_hwmod_ocp_if am33xx_pruss__l3_main;
extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main;
extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
-extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2;
extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__mailbox;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer3;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer4;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer5;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer6;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer7;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__tpcc;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc0;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc1;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2;
extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0;
-extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__rng;
extern struct omap_hwmod am33xx_l3_main_hwmod;
extern struct omap_hwmod am33xx_l3_s_hwmod;
@@ -62,48 +36,18 @@
extern struct omap_hwmod am33xx_l4_ls_hwmod;
extern struct omap_hwmod am33xx_l4_wkup_hwmod;
extern struct omap_hwmod am33xx_mpu_hwmod;
-extern struct omap_hwmod am33xx_pruss_hwmod;
extern struct omap_hwmod am33xx_gfx_hwmod;
extern struct omap_hwmod am33xx_prcm_hwmod;
-extern struct omap_hwmod am33xx_aes0_hwmod;
-extern struct omap_hwmod am33xx_sha0_hwmod;
-extern struct omap_hwmod am33xx_rng_hwmod;
extern struct omap_hwmod am33xx_ocmcram_hwmod;
extern struct omap_hwmod am33xx_smartreflex0_hwmod;
extern struct omap_hwmod am33xx_smartreflex1_hwmod;
-extern struct omap_hwmod am33xx_dcan0_hwmod;
-extern struct omap_hwmod am33xx_dcan1_hwmod;
-extern struct omap_hwmod am33xx_elm_hwmod;
-extern struct omap_hwmod am33xx_epwmss0_hwmod;
-extern struct omap_hwmod am33xx_epwmss1_hwmod;
-extern struct omap_hwmod am33xx_epwmss2_hwmod;
extern struct omap_hwmod am33xx_gpmc_hwmod;
-extern struct omap_hwmod am33xx_mailbox_hwmod;
-extern struct omap_hwmod am33xx_mcasp0_hwmod;
-extern struct omap_hwmod am33xx_mcasp1_hwmod;
-extern struct omap_hwmod am33xx_rtc_hwmod;
-extern struct omap_hwmod am33xx_spi0_hwmod;
-extern struct omap_hwmod am33xx_spi1_hwmod;
-extern struct omap_hwmod am33xx_spinlock_hwmod;
-extern struct omap_hwmod am33xx_timer1_hwmod;
-extern struct omap_hwmod am33xx_timer2_hwmod;
-extern struct omap_hwmod am33xx_timer3_hwmod;
-extern struct omap_hwmod am33xx_timer4_hwmod;
-extern struct omap_hwmod am33xx_timer5_hwmod;
-extern struct omap_hwmod am33xx_timer6_hwmod;
-extern struct omap_hwmod am33xx_timer7_hwmod;
-extern struct omap_hwmod am33xx_tpcc_hwmod;
-extern struct omap_hwmod am33xx_tptc0_hwmod;
-extern struct omap_hwmod am33xx_tptc1_hwmod;
-extern struct omap_hwmod am33xx_tptc2_hwmod;
-extern struct omap_hwmod am33xx_wd_timer1_hwmod;
extern struct omap_hwmod_class am33xx_emif_hwmod_class;
extern struct omap_hwmod_class am33xx_l4_hwmod_class;
extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class;
extern struct omap_hwmod_class am33xx_control_hwmod_class;
extern struct omap_hwmod_class am33xx_timer_hwmod_class;
-extern struct omap_hwmod_class am33xx_epwmss_hwmod_class;
extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class;
extern struct omap_hwmod_class am33xx_spi_hwmod_class;
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
index 63698ff..ab5146b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
@@ -74,82 +74,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* pru-icss -> l3 main */
-struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
- .master = &am33xx_pruss_hwmod,
- .slave = &am33xx_l3_main_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* gfx -> l3 main */
-struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
- .master = &am33xx_gfx_hwmod,
- .slave = &am33xx_l3_main_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3 main -> gfx */
-struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_gfx_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 wkup -> rtc */
-struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_rtc_hwmod,
- .clk = "clkdiv32k_ick",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per/ls -> DCAN0 */
-struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_dcan0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 per/ls -> DCAN1 */
-struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_dcan1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_elm_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_epwmss0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_epwmss1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_epwmss2_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
/* l3s cfg -> gpmc */
struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.master = &am33xx_l3_s_hwmod,
@@ -158,161 +82,9 @@
.user = OCP_USER_MPU,
};
-/* l4 ls -> mailbox */
-struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_mailbox_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 ls -> spinlock */
-struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_spinlock_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcasp0 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_mcasp0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcasp1 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_mcasp1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcspi0 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_spi0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 ls -> mcspi1 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_spi1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer2 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer2_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer3 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer3_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer4 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer4_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer5 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer5_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer6 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer6_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4 per -> timer7 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_timer7_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc */
-struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_tpcc_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc0 */
-struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_tptc0_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc1 */
-struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_tptc1_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU,
-};
-
-/* l3 main -> tpcc2 */
-struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_tptc2_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU,
-};
-
/* l3 main -> ocmc */
struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_ocmcram_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-
-/* l3 main -> sha0 HIB2 */
-struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_sha0_hwmod,
- .clk = "sha0_fck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3 main -> AES0 HIB2 */
-struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_aes0_hwmod,
- .clk = "aes0_fck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 per -> rng */
-struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am33xx_rng_hwmod,
- .clk = "rng_fck",
- .user = OCP_USER_MPU,
-};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index 29fd136..bcc120e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -17,7 +17,6 @@
#include <linux/types.h>
#include "omap_hwmod.h"
-#include "wd_timer.h"
#include "cm33xx.h"
#include "prm33xx.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
@@ -27,7 +26,6 @@
#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
-#define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
/*
* 'l3' class
@@ -135,58 +133,6 @@
};
/*
- * 'pru-icss' class
- * Programmable Real-Time Unit and Industrial Communication Subsystem
- */
-static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
- .name = "pruss",
-};
-
-static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
- { .name = "pruss", .rst_shift = 1 },
-};
-
-/* pru-icss */
-/* Pseudo hwmod for reset control purpose only */
-struct omap_hwmod am33xx_pruss_hwmod = {
- .name = "pruss",
- .class = &am33xx_pruss_hwmod_class,
- .clkdm_name = "pruss_ocp_clkdm",
- .main_clk = "pruss_ocp_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .rst_lines = am33xx_pruss_resets,
- .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
-};
-
-/* gfx */
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
- .name = "gfx",
-};
-
-static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
- { .name = "gfx", .rst_shift = 0, .st_shift = 0},
-};
-
-struct omap_hwmod am33xx_gfx_hwmod = {
- .name = "gfx",
- .class = &am33xx_gfx_hwmod_class,
- .clkdm_name = "gfx_l3_clkdm",
- .main_clk = "gfx_fck_div_ck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .rst_lines = am33xx_gfx_resets,
- .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
-};
-
-/*
* 'prcm' class
* power and reset manager (whole prcm infrastructure)
*/
@@ -214,84 +160,7 @@
.sysc = &am33xx_emif_sysc,
};
-/*
- * 'aes0' class
- */
-static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
- .rev_offs = 0x80,
- .sysc_offs = 0x84,
- .syss_offs = 0x88,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
- .name = "aes0",
- .sysc = &am33xx_aes0_sysc,
-};
-
-struct omap_hwmod am33xx_aes0_hwmod = {
- .name = "aes",
- .class = &am33xx_aes0_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .main_clk = "aes0_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* sha0 HIB2 (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
- .rev_offs = 0x100,
- .sysc_offs = 0x110,
- .syss_offs = 0x114,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
- .name = "sha0",
- .sysc = &am33xx_sha0_sysc,
-};
-
-struct omap_hwmod am33xx_sha0_hwmod = {
- .name = "sham",
- .class = &am33xx_sha0_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* rng */
-static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
- .rev_offs = 0x1fe0,
- .sysc_offs = 0x1fe4,
- .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
- .idlemodes = SIDLE_FORCE | SIDLE_NO,
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_rng_hwmod_class = {
- .name = "rng",
- .sysc = &am33xx_rng_sysc,
-};
-
-struct omap_hwmod am33xx_rng_hwmod = {
- .name = "rng",
- .class = &am33xx_rng_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "rng_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
@@ -349,202 +218,6 @@
.name = "control",
};
-/*
- * dcan class
- */
-static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
- .name = "d_can",
-};
-
-/* dcan0 */
-struct omap_hwmod am33xx_dcan0_hwmod = {
- .name = "d_can0",
- .class = &am33xx_dcan_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dcan0_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* dcan1 */
-struct omap_hwmod am33xx_dcan1_hwmod = {
- .name = "d_can1",
- .class = &am33xx_dcan_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dcan1_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* elm */
-static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_elm_hwmod_class = {
- .name = "elm",
- .sysc = &am33xx_elm_sysc,
-};
-
-struct omap_hwmod am33xx_elm_hwmod = {
- .name = "elm",
- .class = &am33xx_elm_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* pwmss */
-static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x4,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
- .name = "epwmss",
- .sysc = &am33xx_epwmss_sysc,
-};
-
-/* epwmss0 */
-struct omap_hwmod am33xx_epwmss0_hwmod = {
- .name = "epwmss0",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* epwmss1 */
-struct omap_hwmod am33xx_epwmss1_hwmod = {
- .name = "epwmss1",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* epwmss2 */
-struct omap_hwmod am33xx_epwmss2_hwmod = {
- .name = "epwmss2",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'gpio' class: for gpio 0,1,2,3
- */
-static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0114,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
- .name = "gpio",
- .sysc = &am33xx_gpio_sysc,
-};
-
-/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio1_dbclk" },
-};
-
-static struct omap_hwmod am33xx_gpio1_hwmod = {
- .name = "gpio2",
- .class = &am33xx_gpio_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = gpio1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
-};
-
-/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio2_dbclk" },
-};
-
-static struct omap_hwmod am33xx_gpio2_hwmod = {
- .name = "gpio3",
- .class = &am33xx_gpio_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = gpio2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
-};
-
-/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
- { .role = "dbclk", .clk = "gpio3_dbclk" },
-};
-
-static struct omap_hwmod am33xx_gpio3_hwmod = {
- .name = "gpio4",
- .class = &am33xx_gpio_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = gpio3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
-};
/* gpmc */
static struct omap_hwmod_class_sysconfig gpmc_sysc = {
@@ -576,535 +249,42 @@
},
};
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors using a
- * queued mailbox-interrupt mechanism.
- */
-static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &am33xx_mailbox_sysc,
-};
-
-struct omap_hwmod am33xx_mailbox_hwmod = {
- .name = "mailbox",
- .class = &am33xx_mailbox_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mcasp' class
- */
-static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x4,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
- .name = "mcasp",
- .sysc = &am33xx_mcasp_sysc,
-};
-
-/* mcasp0 */
-struct omap_hwmod am33xx_mcasp0_hwmod = {
- .name = "mcasp0",
- .class = &am33xx_mcasp_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .main_clk = "mcasp0_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* mcasp1 */
-struct omap_hwmod am33xx_mcasp1_hwmod = {
- .name = "mcasp1",
- .class = &am33xx_mcasp_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .main_clk = "mcasp1_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'rtc' class
- * rtc subsystem
- */
-static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
- .rev_offs = 0x0074,
- .sysc_offs = 0x0078,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO |
- SIDLE_SMART | SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
- .name = "rtc",
- .sysc = &am33xx_rtc_sysc,
- .unlock = &omap_hwmod_rtc_unlock,
- .lock = &omap_hwmod_rtc_lock,
-};
-
-struct omap_hwmod am33xx_rtc_hwmod = {
- .name = "rtc",
- .class = &am33xx_rtc_hwmod_class,
- .clkdm_name = "l4_rtc_clkdm",
- .main_clk = "clk_32768_ck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* 'spi' class */
-static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0110,
- .syss_offs = 0x0114,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class am33xx_spi_hwmod_class = {
- .name = "mcspi",
- .sysc = &am33xx_mcspi_sysc,
-};
-
-/* spi0 */
-struct omap_hwmod am33xx_spi0_hwmod = {
- .name = "spi0",
- .class = &am33xx_spi_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* spi1 */
-struct omap_hwmod am33xx_spi1_hwmod = {
- .name = "spi1",
- .class = &am33xx_spi_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'spinlock' class
- * spinlock provides hardware assistance for synchronizing the
- * processes running on multiple processors
- */
-
-static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
- .name = "spinlock",
- .sysc = &am33xx_spinlock_sysc,
-};
-
-struct omap_hwmod am33xx_spinlock_hwmod = {
- .name = "spinlock",
- .class = &am33xx_spinlock_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* 'timer 2-7' class */
-static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_RESET_STATUS,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-struct omap_hwmod_class am33xx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &am33xx_timer_sysc,
-};
-
-/* timer1 1ms */
-static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
- .name = "timer",
- .sysc = &am33xx_timer1ms_sysc,
-};
-
-struct omap_hwmod am33xx_timer1_hwmod = {
- .name = "timer1",
- .class = &am33xx_timer1ms_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .main_clk = "timer1_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer2_hwmod = {
- .name = "timer2",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer2_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer3_hwmod = {
- .name = "timer3",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer3_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer4_hwmod = {
- .name = "timer4",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer4_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer5_hwmod = {
- .name = "timer5",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer5_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer6_hwmod = {
- .name = "timer6",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer6_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod am33xx_timer7_hwmod = {
- .name = "timer7",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer7_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* tpcc */
-static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
- .name = "tpcc",
-};
-
-struct omap_hwmod am33xx_tpcc_hwmod = {
- .name = "tpcc",
- .class = &am33xx_tpcc_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_MIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-/* 'tptc' class */
-static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
- .name = "tptc",
- .sysc = &am33xx_tptc_sysc,
-};
-
-/* tptc0 */
-struct omap_hwmod am33xx_tptc0_hwmod = {
- .name = "tptc0",
- .class = &am33xx_tptc_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* tptc1 */
-struct omap_hwmod am33xx_tptc1_hwmod = {
- .name = "tptc1",
- .class = &am33xx_tptc_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* tptc2 */
-struct omap_hwmod am33xx_tptc2_hwmod = {
- .name = "tptc2",
- .class = &am33xx_tptc_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* 'wd_timer' class */
-static struct omap_hwmod_class_sysconfig wdt_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x10,
- .syss_offs = 0x14,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &wdt_sysc,
- .pre_shutdown = &omap2_wd_timer_disable,
-};
-
-/*
- * XXX: device.c file uses hardcoded name for watchdog timer
- * driver "wd_timer2, so we are also using same name as of now...
- */
-struct omap_hwmod am33xx_wd_timer1_hwmod = {
- .name = "wd_timer2",
- .class = &am33xx_wd_timer_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wdt1_fck",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
static void omap_hwmod_am33xx_clkctrl(void)
{
- CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex0_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex1_hwmod,
AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
- PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET);
-}
-
-static void omap_hwmod_am33xx_rst(void)
-{
- RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
- RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
- RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
}
void omap_hwmod_am33xx_reg(void)
{
omap_hwmod_am33xx_clkctrl();
- omap_hwmod_am33xx_rst();
}
static void omap_hwmod_am43xx_clkctrl(void)
{
- CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex0_hwmod,
AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_smartreflex1_hwmod,
AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
- CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET);
-}
-
-static void omap_hwmod_am43xx_rst(void)
-{
- RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
- RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
- RSTST(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTST_OFFSET);
- RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
}
void omap_hwmod_am43xx_reg(void)
{
omap_hwmod_am43xx_clkctrl();
- omap_hwmod_am43xx_rst();
}
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 5452477..b232f6c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -1,7 +1,7 @@
/*
* omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
*
- * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) {2012} Texas Instruments Incorporated - https://www.ti.com/
*
* This file is automatically generated from the AM33XX hardware databases.
* This program is free software; you can redistribute it and/or
@@ -21,7 +21,6 @@
#include "cm33xx.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
-#include "wd_timer.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
/*
@@ -82,36 +81,6 @@
.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
};
-/*
- * 'adc/tsc' class
- * TouchScreen Controller (Anolog-To-Digital Converter)
- */
-static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x10,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
- .name = "adc_tsc",
- .sysc = &am33xx_adc_tsc_sysc,
-};
-
-static struct omap_hwmod am33xx_adc_tsc_hwmod = {
- .name = "adc_tsc",
- .class = &am33xx_adc_tsc_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .main_clk = "adc_tsc_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
/*
* Modules omap_hwmod structures
@@ -227,67 +196,6 @@
},
};
-/* lcdc */
-static struct omap_hwmod_class_sysconfig lcdc_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x54,
- .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE,
- .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART,
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
- .name = "lcdc",
- .sysc = &lcdc_sysc,
-};
-
-static struct omap_hwmod am33xx_lcdc_hwmod = {
- .name = "lcdc",
- .class = &am33xx_lcdc_hwmod_class,
- .clkdm_name = "lcdc_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "lcd_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'usb_otg' class
- * high-speed on-the-go universal serial bus (usb_otg) controller
- */
-static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am33xx_usbotg_class = {
- .name = "usbotg",
- .sysc = &am33xx_usbhsotg_sysc,
-};
-
-static struct omap_hwmod am33xx_usbss_hwmod = {
- .name = "usb_otg_hs",
- .class = &am33xx_usbotg_class,
- .clkdm_name = "l3s_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "usbotg_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
/*
* Interfaces
@@ -325,14 +233,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4 hs -> pru-icss */
-static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
- .master = &am33xx_l4_hs_hwmod,
- .slave = &am33xx_pruss_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main -> debugss */
static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
.master = &am33xx_l3_main_hwmod,
@@ -365,47 +265,6 @@
.user = OCP_USER_MPU,
};
-/* L4 WKUP -> ADC_TSC */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_adc_tsc_hwmod,
- .clk = "dpll_core_m4_div2_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_lcdc_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l4 wkup -> timer1 */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_timer1_hwmod,
- .clk = "dpll_core_m4_div2_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l4 wkup -> wd_timer1 */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_wd_timer1_hwmod,
- .clk = "dpll_core_m4_div2_ck",
- .user = OCP_USER_MPU,
-};
-
-/* usbss */
-/* l3 s -> USBSS interface */
-static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am33xx_usbss_hwmod,
- .clk = "l3s_gclk",
- .user = OCP_USER_MPU,
- .flags = OCPIF_SWSUP_IDLE,
-};
-
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__emif,
&am33xx_mpu__l3_main,
@@ -415,50 +274,15 @@
&am33xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
- &am33xx_l3_main__gfx,
&am33xx_l3_s__l3_main,
- &am33xx_pruss__l3_main,
&am33xx_wkup_m3__l4_wkup,
- &am33xx_gfx__l3_main,
&am33xx_l3_main__debugss,
&am33xx_l4_wkup__wkup_m3,
&am33xx_l4_wkup__control,
&am33xx_l4_wkup__smartreflex0,
&am33xx_l4_wkup__smartreflex1,
- &am33xx_l4_wkup__timer1,
- &am33xx_l4_wkup__rtc,
- &am33xx_l4_wkup__adc_tsc,
- &am33xx_l4_wkup__wd_timer1,
- &am33xx_l4_hs__pruss,
- &am33xx_l4_per__dcan0,
- &am33xx_l4_per__dcan1,
- &am33xx_l4_per__mailbox,
- &am33xx_l4_ls__mcasp0,
- &am33xx_l4_ls__mcasp1,
- &am33xx_l4_ls__timer2,
- &am33xx_l4_ls__timer3,
- &am33xx_l4_ls__timer4,
- &am33xx_l4_ls__timer5,
- &am33xx_l4_ls__timer6,
- &am33xx_l4_ls__timer7,
- &am33xx_l3_main__tpcc,
- &am33xx_l4_ls__spinlock,
- &am33xx_l4_ls__elm,
- &am33xx_l4_ls__epwmss0,
- &am33xx_l4_ls__epwmss1,
- &am33xx_l4_ls__epwmss2,
&am33xx_l3_s__gpmc,
- &am33xx_l3_main__lcdc,
- &am33xx_l4_ls__mcspi0,
- &am33xx_l4_ls__mcspi1,
- &am33xx_l3_main__tptc0,
- &am33xx_l3_main__tptc1,
- &am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
- &am33xx_l3_s__usbss,
- &am33xx_l3_main__sha0,
- &am33xx_l3_main__aes0,
- &am33xx_l4_per__rng,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index f52438b..b6c7d98 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -16,7 +16,6 @@
#include <linux/power/smartreflex.h>
#include <linux/platform_data/hsmmc-omap.h>
-#include <linux/omap-dma.h>
#include "l3_3xxx.h"
#include "l4_3xxx.h"
@@ -148,36 +147,6 @@
.sysc = &omap3xxx_timer_sysc,
};
-/* timer1 */
-static struct omap_hwmod omap3xxx_timer1_hwmod = {
- .name = "timer1",
- .main_clk = "gpt1_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
- },
- },
- .class = &omap3xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
-/* timer2 */
-static struct omap_hwmod omap3xxx_timer2_hwmod = {
- .name = "timer2",
- .main_clk = "gpt2_fck",
- .prcm = {
- .omap2 = {
- .module_offs = OMAP3430_PER_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
- },
- },
- .class = &omap3xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
/* timer3 */
static struct omap_hwmod omap3xxx_timer3_hwmod = {
.name = "timer3",
@@ -313,21 +282,6 @@
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
-/* timer12 */
-static struct omap_hwmod omap3xxx_timer12_hwmod = {
- .name = "timer12",
- .main_clk = "gpt12_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
- },
- },
- .class = &omap3xxx_timer_hwmod_class,
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
-};
-
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
@@ -833,47 +787,6 @@
.class = &omap3xxx_gpio_hwmod_class,
};
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap3xxx_dma_sysc,
-};
-
-/* dma_system */
-static struct omap_hwmod omap3xxx_dma_system_hwmod = {
- .name = "dma",
- .class = &omap3xxx_dma_hwmod_class,
- .main_clk = "core_l3_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
- },
- },
- .dev_attr = &dma_dev_attr,
- .flags = HWMOD_NO_IDLEST,
-};
-
/*
* 'mcbsp' class
* multi channel buffered serial port controller
@@ -1567,38 +1480,6 @@
};
/*
- * '32K sync counter' class
- * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
- */
-static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0004,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
- .name = "counter",
- .sysc = &omap3xxx_counter_sysc,
-};
-
-static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
- .name = "counter_32k",
- .class = &omap3xxx_counter_hwmod_class,
- .clkdm_name = "wkup_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wkup_32k_fck",
- .prcm = {
- .omap2 = {
- .module_offs = WKUP_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
- },
- },
-};
-
-/*
* 'gpmc' class
* general purpose memory controller
*/
@@ -1910,25 +1791,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
- .master = &omap3xxx_l4_wkup_hwmod,
- .slave = &omap3xxx_timer1_hwmod,
- .clk = "gpt1_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
- .master = &omap3xxx_l4_per_hwmod,
- .slave = &omap3xxx_timer2_hwmod,
- .clk = "gpt2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-
/* l4_per -> timer3 */
static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
.master = &omap3xxx_l4_per_hwmod,
@@ -2007,15 +1869,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
- .master = &omap3xxx_l4_sec_hwmod,
- .slave = &omap3xxx_timer12_hwmod,
- .clk = "gpt12_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
@@ -2233,23 +2086,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
- .master = &omap3xxx_dma_system_hwmod,
- .slave = &omap3xxx_l3_main_hwmod,
- .clk = "core_l3_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_dma_system_hwmod,
- .clk = "core_l4_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-
/* l4_core -> mcbsp1 */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
.master = &omap3xxx_l4_core_hwmod,
@@ -2384,16 +2220,6 @@
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};
-/* l4_wkup -> 32ksync_counter */
-
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
- .master = &omap3xxx_l4_wkup_hwmod,
- .slave = &omap3xxx_counter_32k_hwmod,
- .clk = "omap_32ksync_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* am35xx has Davinci MDIO & EMAC */
static struct omap_hwmod_class am35xx_mdio_class = {
.name = "davinci_mdio",
@@ -2516,44 +2342,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_core -> AES */
-static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
- .rev_offs = 0x44,
- .sysc_offs = 0x48,
- .syss_offs = 0x4c,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap3xxx_aes_sysc_fields,
-};
-
-static struct omap_hwmod_class omap3xxx_aes_class = {
- .name = "aes",
- .sysc = &omap3_aes_sysc,
-};
-
-
-static struct omap_hwmod omap3xxx_aes_hwmod = {
- .name = "aes",
- .main_clk = "aes2_ick",
- .prcm = {
- .omap2 = {
- .module_offs = CORE_MOD,
- .idlest_reg_id = 1,
- .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
- },
- },
- .class = &omap3xxx_aes_class,
-};
-
-
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
- .master = &omap3xxx_l4_core_hwmod,
- .slave = &omap3xxx_aes_hwmod,
- .clk = "aes2_ick",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/*
* 'ssi' class
* synchronous serial interface (multichannel and full-duplex serial if)
@@ -2610,8 +2398,6 @@
&omap3_l4_core__i2c2,
&omap3_l4_core__i2c3,
&omap3xxx_l4_wkup__l4_sec,
- &omap3xxx_l4_wkup__timer1,
- &omap3xxx_l4_per__timer2,
&omap3xxx_l4_per__timer3,
&omap3xxx_l4_per__timer4,
&omap3xxx_l4_per__timer5,
@@ -2628,8 +2414,6 @@
&omap3xxx_l4_per__gpio4,
&omap3xxx_l4_per__gpio5,
&omap3xxx_l4_per__gpio6,
- &omap3xxx_dma_system__l3,
- &omap3xxx_l4_core__dma_system,
&omap3xxx_l4_core__mcbsp1,
&omap3xxx_l4_per__mcbsp2,
&omap3xxx_l4_per__mcbsp3,
@@ -2641,47 +2425,21 @@
&omap34xx_l4_core__mcspi2,
&omap34xx_l4_core__mcspi3,
&omap34xx_l4_core__mcspi4,
- &omap3xxx_l4_wkup__counter_32k,
&omap3xxx_l3_main__gpmc,
NULL,
};
-/* GP-only hwmod links */
-static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_sec__timer12,
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_sec__timer12,
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_sec__timer12,
- NULL,
-};
-
/* crypto hwmod links */
static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__sham,
NULL,
};
-static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_core__aes,
- NULL,
-};
-
static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__sham,
NULL
};
-static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
- &omap3xxx_l4_core__aes,
- NULL
-};
/*
* Apparently the SHA/MD5 and AES accelerator IP blocks are
@@ -2696,11 +2454,6 @@
NULL
};
-static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
- /* &omap3xxx_l4_core__aes, */
- NULL,
-};
-
/* 3430ES1-only hwmod links */
static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
&omap3430es1_dss__l3,
@@ -2835,8 +2588,7 @@
int __init omap3xxx_hwmod_init(void)
{
int r;
- struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
- struct omap_hwmod_ocp_if **h_aes = NULL;
+ struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL;
struct device_node *bus;
unsigned int rev;
@@ -2858,20 +2610,14 @@
rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
h = omap34xx_hwmod_ocp_ifs;
- h_gp = omap34xx_gp_hwmod_ocp_ifs;
h_sham = omap34xx_sham_hwmod_ocp_ifs;
- h_aes = omap34xx_aes_hwmod_ocp_ifs;
} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
h = am35xx_hwmod_ocp_ifs;
- h_gp = am35xx_gp_hwmod_ocp_ifs;
h_sham = am35xx_sham_hwmod_ocp_ifs;
- h_aes = am35xx_aes_hwmod_ocp_ifs;
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
rev == OMAP3630_REV_ES1_2) {
h = omap36xx_hwmod_ocp_ifs;
- h_gp = omap36xx_gp_hwmod_ocp_ifs;
h_sham = omap36xx_sham_hwmod_ocp_ifs;
- h_aes = omap36xx_aes_hwmod_ocp_ifs;
} else {
WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
return -EINVAL;
@@ -2881,13 +2627,6 @@
if (r < 0)
return r;
- /* Register GP-only hwmod links. */
- if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
- r = omap_hwmod_register_links(h_gp);
- if (r < 0)
- return r;
- }
-
/*
* Register crypto hwmod links only if they are not disabled in DT.
* If DT information is missing, enable them only for GP devices.
@@ -2901,11 +2640,6 @@
goto put_node;
}
- if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
- r = omap_hwmod_register_links(h_aes);
- if (r < 0)
- goto put_node;
- }
of_node_put(bus);
/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 5c3db6b..b97cb74 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -18,8 +18,6 @@
#include "omap_hwmod_33xx_43xx_common_data.h"
#include "prcm43xx.h"
#include "omap_hwmod_common_data.h"
-#include "hdq1w.h"
-
/* IP blocks */
static struct omap_hwmod am43xx_emif_hwmod = {
@@ -87,452 +85,6 @@
},
};
-static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x4,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
- .name = "synctimer",
- .sysc = &am43xx_synctimer_sysc,
-};
-
-static struct omap_hwmod am43xx_synctimer_hwmod = {
- .name = "counter_32k",
- .class = &am43xx_synctimer_hwmod_class,
- .clkdm_name = "l4_wkup_aon_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "synctimer_32kclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_timer8_hwmod = {
- .name = "timer8",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer8_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_timer9_hwmod = {
- .name = "timer9",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer9_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_timer10_hwmod = {
- .name = "timer10",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer10_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_timer11_hwmod = {
- .name = "timer11",
- .class = &am33xx_timer_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "timer11_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_epwmss3_hwmod = {
- .name = "epwmss3",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_epwmss4_hwmod = {
- .name = "epwmss4",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_epwmss5_hwmod = {
- .name = "epwmss5",
- .class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_spi2_hwmod = {
- .name = "spi2",
- .class = &am33xx_spi_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_spi3_hwmod = {
- .name = "spi3",
- .class = &am33xx_spi_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_spi4_hwmod = {
- .name = "spi4",
- .class = &am33xx_spi_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "dpll_per_m2_div4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
- .name = "ocp2scp",
-};
-
-static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
- .name = "ocp2scp0",
- .class = &am43xx_ocp2scp_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
- .name = "ocp2scp1",
- .class = &am43xx_ocp2scp_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE |
- MSTANDBY_NO | MSTANDBY_SMART |
- MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
- .name = "usb_otg_ss",
- .sysc = &am43xx_usb_otg_ss_sysc,
-};
-
-static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
- .name = "usb_otg_ss0",
- .class = &am43xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .main_clk = "l3s_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
- .name = "usb_otg_ss1",
- .class = &am43xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .main_clk = "l3s_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
- .rev_offs = 0,
- .sysc_offs = 0x0010,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
- .name = "qspi",
- .sysc = &am43xx_qspi_sysc,
-};
-
-static struct omap_hwmod am43xx_qspi_hwmod = {
- .name = "qspi",
- .class = &am43xx_qspi_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .main_clk = "l3s_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'adc/tsc' class
- * TouchScreen Controller (Analog-To-Digital Converter)
- */
-static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
- .rev_offs = 0x00,
- .sysc_offs = 0x10,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
- .name = "adc_tsc",
- .sysc = &am43xx_adc_tsc_sysc,
-};
-
-static struct omap_hwmod am43xx_adc_tsc_hwmod = {
- .name = "adc_tsc",
- .class = &am43xx_adc_tsc_hwmod_class,
- .clkdm_name = "l3s_tsc_clkdm",
- .main_clk = "adc_tsc_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class_sysconfig am43xx_des_sysc = {
- .rev_offs = 0x30,
- .sysc_offs = 0x34,
- .syss_offs = 0x38,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class am43xx_des_hwmod_class = {
- .name = "des",
- .sysc = &am43xx_des_sysc,
-};
-
-static struct omap_hwmod am43xx_des_hwmod = {
- .name = "des",
- .class = &am43xx_des_hwmod_class,
- .clkdm_name = "l3_clkdm",
- .main_clk = "l3_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_DES_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* dss */
-
-static struct omap_hwmod am43xx_dss_core_hwmod = {
- .name = "dss_core",
- .class = &omap2_dss_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "disp_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* dispc */
-
-static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
- .manager_count = 1,
- .has_framedonetv_irq = 0
-};
-
-static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &am43xx_dispc_sysc,
-};
-
-static struct omap_hwmod am43xx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &am43xx_dispc_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "disp_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
- },
- },
- .dev_attr = &am43xx_dss_dispc_dev_attr,
- .parent_hwmod = &am43xx_dss_core_hwmod,
-};
-
-/* rfbi */
-
-static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap2_rfbi_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "disp_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
- },
- },
- .parent_hwmod = &am43xx_dss_core_hwmod,
-};
-
-/* HDQ1W */
-static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0014,
- .syss_offs = 0x0018,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
- .name = "hdq1w",
- .sysc = &am43xx_hdq1w_sysc,
- .reset = &omap_hdq1w_reset,
-};
-
-static struct omap_hwmod am43xx_hdq1w_hwmod = {
- .name = "hdq1w",
- .class = &am43xx_hdq1w_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x104,
- .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
- .name = "vpfe",
- .sysc = &am43xx_vpfe_sysc,
-};
-
-static struct omap_hwmod am43xx_vpfe0_hwmod = {
- .name = "vpfe0",
- .class = &am43xx_vpfe_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
- },
- },
-};
-
-static struct omap_hwmod am43xx_vpfe1_hwmod = {
- .name = "vpfe1",
- .class = &am43xx_vpfe_hwmod_class,
- .clkdm_name = "l3s_clkdm",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
- },
- },
-};
-
/* Interfaces */
static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
.master = &am33xx_l3_main_hwmod,
@@ -562,13 +114,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am33xx_pruss_hwmod,
- .clk = "dpll_core_m4_ck",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_smartreflex0_hwmod,
@@ -590,222 +135,7 @@
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am43xx_adc_tsc_hwmod,
- .clk = "dpll_core_m4_div2_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_timer1_hwmod,
- .clk = "sys_clkin_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am33xx_wd_timer1_hwmod,
- .clk = "sys_clkin_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
- .master = &am33xx_l4_wkup_hwmod,
- .slave = &am43xx_synctimer_hwmod,
- .clk = "sys_clkin_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_timer8_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_timer9_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_timer10_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_timer11_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_epwmss3_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_epwmss4_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_epwmss5_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_spi2_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_spi3_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_spi4_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_ocp2scp0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_ocp2scp1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am43xx_usb_otg_ss0_hwmod,
- .clk = "l3s_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am43xx_usb_otg_ss1_hwmod,
- .clk = "l3s_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
- .master = &am33xx_l3_s_hwmod,
- .slave = &am43xx_qspi_hwmod,
- .clk = "l3s_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
- .master = &am43xx_dss_core_hwmod,
- .slave = &am33xx_l3_main_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_dss_core_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_dss_dispc_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_dss_rfbi_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_hdq1w_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
- .master = &am43xx_vpfe0_hwmod,
- .slave = &am33xx_l3_main_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
- .master = &am43xx_vpfe1_hwmod,
- .slave = &am33xx_l3_main_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_vpfe0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
- .master = &am33xx_l4_ls_hwmod,
- .slave = &am43xx_vpfe1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l3_main__des = {
- .master = &am33xx_l3_main_hwmod,
- .slave = &am43xx_des_hwmod,
- .clk = "l3_gclk",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
- &am33xx_l4_wkup__synctimer,
- &am43xx_l4_ls__timer8,
- &am43xx_l4_ls__timer9,
- &am43xx_l4_ls__timer10,
- &am43xx_l4_ls__timer11,
- &am43xx_l4_ls__epwmss3,
- &am43xx_l4_ls__epwmss4,
- &am43xx_l4_ls__epwmss5,
- &am43xx_l4_ls__mcspi2,
- &am43xx_l4_ls__mcspi3,
- &am43xx_l4_ls__mcspi4,
- &am43xx_l3_main__pruss,
&am33xx_mpu__l3_main,
&am33xx_mpu__prcm,
&am33xx_l3_s__l4_ls,
@@ -813,66 +143,15 @@
&am43xx_l3_main__l4_hs,
&am33xx_l3_main__l3_s,
&am33xx_l3_main__l3_instr,
- &am33xx_l3_main__gfx,
&am33xx_l3_s__l3_main,
&am43xx_l3_main__emif,
- &am33xx_pruss__l3_main,
&am43xx_wkup_m3__l4_wkup,
- &am33xx_gfx__l3_main,
&am43xx_l4_wkup__wkup_m3,
&am43xx_l4_wkup__control,
&am43xx_l4_wkup__smartreflex0,
&am43xx_l4_wkup__smartreflex1,
- &am43xx_l4_wkup__timer1,
- &am43xx_l4_wkup__wd_timer1,
- &am43xx_l4_wkup__adc_tsc,
- &am43xx_l3_s__qspi,
- &am33xx_l4_per__dcan0,
- &am33xx_l4_per__dcan1,
- &am33xx_l4_per__mailbox,
- &am33xx_l4_per__rng,
- &am33xx_l4_ls__mcasp0,
- &am33xx_l4_ls__mcasp1,
- &am33xx_l4_ls__timer2,
- &am33xx_l4_ls__timer3,
- &am33xx_l4_ls__timer4,
- &am33xx_l4_ls__timer5,
- &am33xx_l4_ls__timer6,
- &am33xx_l4_ls__timer7,
- &am33xx_l3_main__tpcc,
- &am33xx_l4_ls__spinlock,
- &am33xx_l4_ls__elm,
- &am33xx_l4_ls__epwmss0,
- &am33xx_l4_ls__epwmss1,
- &am33xx_l4_ls__epwmss2,
&am33xx_l3_s__gpmc,
- &am33xx_l4_ls__mcspi0,
- &am33xx_l4_ls__mcspi1,
- &am33xx_l3_main__tptc0,
- &am33xx_l3_main__tptc1,
- &am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
- &am33xx_l3_main__sha0,
- &am33xx_l3_main__aes0,
- &am43xx_l3_main__des,
- &am43xx_l4_ls__ocp2scp0,
- &am43xx_l4_ls__ocp2scp1,
- &am43xx_l3_s__usbotgss0,
- &am43xx_l3_s__usbotgss1,
- &am43xx_dss__l3_main,
- &am43xx_l4_ls__dss,
- &am43xx_l4_ls__dss_dispc,
- &am43xx_l4_ls__dss_rfbi,
- &am43xx_l4_ls__hdq1w,
- &am43xx_l3__vpfe0,
- &am43xx_l3__vpfe1,
- &am43xx_l4_ls__vpfe0,
- &am43xx_l4_ls__vpfe1,
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
- &am33xx_l4_wkup__rtc,
NULL,
};
@@ -884,8 +163,5 @@
omap_hwmod_init();
ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
- if (!ret && of_machine_is_compatible("ti,am4372"))
- ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
-
return ret;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 28ea296..37c5911 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -18,9 +18,6 @@
*/
#include <linux/io.h>
-#include <linux/power/smartreflex.h>
-
-#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
@@ -32,9 +29,6 @@
/* Base offset for all OMAP4 interrupts external to MPUSS */
#define OMAP44XX_IRQ_GIC_START 32
-/* Base offset for all OMAP4 dma requests */
-#define OMAP44XX_DMA_REQ_START 1
-
/*
* IP blocks
*/
@@ -130,21 +124,6 @@
.name = "l4",
};
-/* l4_abe */
-static struct omap_hwmod omap44xx_l4_abe_hwmod = {
- .name = "l4_abe",
- .class = &omap44xx_l4_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
- .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
/* l4_cfg */
static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
.name = "l4_cfg",
@@ -238,76 +217,6 @@
*/
/*
- * 'aess' class
- * audio engine sub system
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
- MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
- .name = "aess",
- .sysc = &omap44xx_aess_sysc,
- .enable_preprogram = omap_hwmod_aess_preprogram,
-};
-
-/* aess */
-static struct omap_hwmod omap44xx_aess_hwmod = {
- .name = "aess",
- .class = &omap44xx_aess_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "aess_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
- .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'counter' class
- * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0004,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
- .name = "counter",
- .sysc = &omap44xx_counter_sysc,
-};
-
-/* counter_32k */
-static struct omap_hwmod omap44xx_counter_32k_hwmod = {
- .name = "counter_32k",
- .class = &omap44xx_counter_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
* 'ctrl_module' class
* attila core control module + core pad control module + wkup pad control
* module + attila wkup control module
@@ -399,446 +308,6 @@
};
/*
- * 'dma' class
- * dma controller for data exchange between memory to memory (i.e. internal or
- * external memory) and gp peripherals to memory or memory to gp peripherals
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap44xx_dma_sysc,
-};
-
-/* dma dev_attr */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-/* dma_system */
-static struct omap_hwmod omap44xx_dma_system_hwmod = {
- .name = "dma_system",
- .class = &omap44xx_dma_hwmod_class,
- .clkdm_name = "l3_dma_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
- },
- },
- .dev_attr = &dma_dev_attr,
-};
-
-/*
- * 'dmic' class
- * digital microphone controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
- .name = "dmic",
- .sysc = &omap44xx_dmic_sysc,
-};
-
-/* dmic */
-static struct omap_hwmod omap44xx_dmic_hwmod = {
- .name = "dmic",
- .class = &omap44xx_dmic_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "func_dmic_abe_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'dsp' class
- * dsp sub-system
- */
-
-static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
- .name = "dsp",
-};
-
-/* dsp */
-static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
- { .name = "dsp", .rst_shift = 0 },
-};
-
-static struct omap_hwmod omap44xx_dsp_hwmod = {
- .name = "dsp",
- .class = &omap44xx_dsp_hwmod_class,
- .clkdm_name = "tesla_clkdm",
- .rst_lines = omap44xx_dsp_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
- .main_clk = "dpll_iva_m4x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
- .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'dss' class
- * display sub-system
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
- .rev_offs = 0x0000,
- .syss_offs = 0x0014,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
- .name = "dss",
- .sysc = &omap44xx_dss_sysc,
- .reset = omap_dss_reset,
-};
-
-/* dss */
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
- { .role = "tv_clk", .clk = "dss_tv_clk" },
- { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_hwmod = {
- .name = "dss_core",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .class = &omap44xx_dss_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-};
-
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap44xx_dispc_sysc,
-};
-
-/* dss_dispc */
-static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
- .manager_count = 3,
- .has_framedonetv_irq = 1
-};
-
-static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &omap44xx_dispc_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .dev_attr = &omap44xx_dss_dispc_dev_attr,
- .parent_hwmod = &omap44xx_dss_hwmod,
-};
-
-/*
- * 'dsi' class
- * display serial interface controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
- .name = "dsi",
- .sysc = &omap44xx_dsi_sysc,
-};
-
-/* dss_dsi1 */
-static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
- .name = "dss_dsi1",
- .class = &omap44xx_dsi_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .opt_clks = dss_dsi1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
- .parent_hwmod = &omap44xx_dss_hwmod,
-};
-
-/* dss_dsi2 */
-static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
- .name = "dss_dsi2",
- .class = &omap44xx_dsi_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .opt_clks = dss_dsi2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
- .parent_hwmod = &omap44xx_dss_hwmod,
-};
-
-/*
- * 'hdmi' class
- * hdmi controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
- .name = "hdmi",
- .sysc = &omap44xx_hdmi_sysc,
-};
-
-/* dss_hdmi */
-static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
- { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
- .name = "dss_hdmi",
- .class = &omap44xx_hdmi_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- /*
- * HDMI audio requires to use no-idle mode. Hence,
- * set idle mode by software.
- */
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
- .main_clk = "dss_48mhz_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .opt_clks = dss_hdmi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
- .parent_hwmod = &omap44xx_dss_hwmod,
-};
-
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
- .name = "rfbi",
- .sysc = &omap44xx_rfbi_sysc,
-};
-
-/* dss_rfbi */
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
- { .role = "ick", .clk = "l3_div_ck" },
-};
-
-static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap44xx_rfbi_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .opt_clks = dss_rfbi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
- .parent_hwmod = &omap44xx_dss_hwmod,
-};
-
-/*
- * 'venc' class
- * video encoder
- */
-
-static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
- .name = "venc",
-};
-
-/* dss_venc */
-static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
- { .role = "tv_clk", .clk = "dss_tv_clk" },
-};
-
-static struct omap_hwmod omap44xx_dss_venc_hwmod = {
- .name = "dss_venc",
- .class = &omap44xx_venc_hwmod_class,
- .clkdm_name = "l3_dss_clkdm",
- .main_clk = "dss_tv_clk",
- .flags = HWMOD_OPT_CLKS_NEEDED,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
- },
- },
- .parent_hwmod = &omap44xx_dss_hwmod,
- .opt_clks = dss_venc_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
-};
-
-/* sha0 HIB2 (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
- .rev_offs = 0x100,
- .sysc_offs = 0x110,
- .syss_offs = 0x114,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
- .name = "sham",
- .sysc = &omap44xx_sha0_sysc,
-};
-
-struct omap_hwmod omap44xx_sha0_hwmod = {
- .name = "sham",
- .class = &omap44xx_sha0_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'elm' class
- * bch error location module
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
- .name = "elm",
- .sysc = &omap44xx_elm_sysc,
-};
-
-/* elm */
-static struct omap_hwmod omap44xx_elm_hwmod = {
- .name = "elm",
- .class = &omap44xx_elm_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
* 'emif' class
* external memory interface no1
*/
@@ -885,147 +354,6 @@
};
/*
- Crypto modules AES0/1 belong to:
- PD_L4_PER power domain
- CD_L4_SEC clock domain
- On the L3, the AES modules are mapped to
- L3_CLK2: Peripherals and multimedia sub clock domain
-*/
-static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
- .rev_offs = 0x80,
- .sysc_offs = 0x84,
- .syss_offs = 0x88,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
- .name = "aes",
- .sysc = &omap44xx_aes_sysc,
-};
-
-static struct omap_hwmod omap44xx_aes1_hwmod = {
- .name = "aes1",
- .class = &omap44xx_aes_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .context_offs = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
- .clkctrl_offs = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_aes1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod omap44xx_aes2_hwmod = {
- .name = "aes2",
- .class = &omap44xx_aes_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .context_offs = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
- .clkctrl_offs = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_aes2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/*
- * 'des' class for DES3DES module
- */
-static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
- .rev_offs = 0x30,
- .sysc_offs = 0x34,
- .syss_offs = 0x38,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap44xx_des_hwmod_class = {
- .name = "des",
- .sysc = &omap44xx_des_sysc,
-};
-
-static struct omap_hwmod omap44xx_des_hwmod = {
- .name = "des",
- .class = &omap44xx_des_hwmod_class,
- .clkdm_name = "l4_secure_clkdm",
- .main_clk = "l3_div_ck",
- .prcm = {
- .omap4 = {
- .context_offs = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
- .clkctrl_offs = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_des_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/*
- * 'fdif' class
- * face detection hw accelerator module
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- /*
- * FDIF needs 100 OCP clk cycles delay after a softreset before
- * accessing sysconfig again.
- * The lowest frequency at the moment for L3 bus is 100 MHz, so
- * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
- *
- * TODO: Indicate errata when available.
- */
- .srst_udelay = 2,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
- .name = "fdif",
- .sysc = &omap44xx_fdif_sysc,
-};
-
-/* fdif */
-static struct omap_hwmod omap44xx_fdif_hwmod = {
- .name = "fdif",
- .class = &omap44xx_fdif_hwmod_class,
- .clkdm_name = "iss_clkdm",
- .main_clk = "fdif_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
* 'gpmc' class
* general purpose memory controller
*/
@@ -1062,112 +390,6 @@
};
/*
- * 'hdq1w' class
- * hdq / 1-wire serial interface controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0014,
- .syss_offs = 0x0018,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
- .name = "hdq1w",
- .sysc = &omap44xx_hdq1w_sysc,
-};
-
-/* hdq1w */
-static struct omap_hwmod omap44xx_hdq1w_hwmod = {
- .name = "hdq1w",
- .class = &omap44xx_hdq1w_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
- .main_clk = "func_12m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'hsi' class
- * mipi high-speed synchronous serial interface (multichannel and full-duplex
- * serial if)
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
- SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
- .name = "hsi",
- .sysc = &omap44xx_hsi_sysc,
-};
-
-/* hsi */
-static struct omap_hwmod omap44xx_hsi_hwmod = {
- .name = "hsi",
- .class = &omap44xx_hsi_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .main_clk = "hsi_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'ipu' class
- * imaging processor unit
- */
-
-static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
- .name = "ipu",
-};
-
-/* ipu */
-static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
- { .name = "cpu0", .rst_shift = 0 },
- { .name = "cpu1", .rst_shift = 1 },
-};
-
-static struct omap_hwmod omap44xx_ipu_hwmod = {
- .name = "ipu",
- .class = &omap44xx_ipu_hwmod_class,
- .clkdm_name = "ducati_clkdm",
- .rst_lines = omap44xx_ipu_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
- .main_clk = "ducati_clk_mux_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
- .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
* 'iss' class
* external images sensor pixel data processor
*/
@@ -1252,351 +474,6 @@
};
/*
- * 'kbd' class
- * keyboard controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
- .name = "kbd",
- .sysc = &omap44xx_kbd_sysc,
-};
-
-/* kbd */
-static struct omap_hwmod omap44xx_kbd_hwmod = {
- .name = "kbd",
- .class = &omap44xx_kbd_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors using a
- * queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &omap44xx_mailbox_sysc,
-};
-
-/* mailbox */
-static struct omap_hwmod omap44xx_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap44xx_mailbox_hwmod_class,
- .clkdm_name = "l4_cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'mcasp' class
- * multi-channel audio serial port controller
- */
-
-/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
- .rev_offs = 0,
- .sysc_offs = 0x0004,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type_mcasp,
-};
-
-static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
- .name = "mcasp",
- .sysc = &omap44xx_mcasp_sysc,
-};
-
-/* mcasp */
-static struct omap_hwmod omap44xx_mcasp_hwmod = {
- .name = "mcasp",
- .class = &omap44xx_mcasp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "func_mcasp_abe_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
- .rev_offs = -ENODEV,
- .sysc_offs = 0x008c,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
- .name = "mcbsp",
- .sysc = &omap44xx_mcbsp_sysc,
-};
-
-/* mcbsp1 */
-static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap44xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "func_mcbsp1_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
-};
-
-/* mcbsp2 */
-static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap44xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "func_mcbsp2_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
-};
-
-/* mcbsp3 */
-static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
- .name = "mcbsp3",
- .class = &omap44xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "func_mcbsp3_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
-};
-
-/* mcbsp4 */
-static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
- .name = "mcbsp4",
- .class = &omap44xx_mcbsp_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .main_clk = "per_mcbsp4_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp4_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
-};
-
-/*
- * 'mcpdm' class
- * multi channel pdm controller (proprietary interface with phoenix power
- * ic)
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
- .name = "mcpdm",
- .sysc = &omap44xx_mcpdm_sysc,
-};
-
-/* mcpdm */
-static struct omap_hwmod omap44xx_mcpdm_hwmod = {
- .name = "mcpdm",
- .class = &omap44xx_mcpdm_hwmod_class,
- .clkdm_name = "abe_clkdm",
- /*
- * It's suspected that the McPDM requires an off-chip main
- * functional clock, controlled via I2C. This IP block is
- * currently reset very early during boot, before I2C is
- * available, so it doesn't seem that we have any choice in
- * the kernel other than to avoid resetting it.
- *
- * Also, McPDM needs to be configured to NO_IDLE mode when it
- * is in used otherwise vital clocks will be gated which
- * results 'slow motion' audio playback.
- */
- .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
- .main_clk = "pad_clks_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mmu' class
- * The memory management unit performs virtual to physical address translation
- * for its requestors.
- */
-
-static struct omap_hwmod_class_sysconfig mmu_sysc = {
- .rev_offs = 0x000,
- .sysc_offs = 0x010,
- .syss_offs = 0x014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
- .name = "mmu",
- .sysc = &mmu_sysc,
-};
-
-/* mmu ipu */
-
-static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
-static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
- { .name = "mmu_cache", .rst_shift = 2 },
-};
-
-/* l3_main_2 -> mmu_ipu */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_mmu_ipu_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
- .name = "mmu_ipu",
- .class = &omap44xx_mmu_hwmod_class,
- .clkdm_name = "ducati_clkdm",
- .rst_lines = omap44xx_mmu_ipu_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
- .main_clk = "ducati_clk_mux_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
- .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* mmu dsp */
-
-static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
-static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
- { .name = "mmu_cache", .rst_shift = 1 },
-};
-
-/* l4_cfg -> dsp */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_mmu_dsp_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
- .name = "mmu_dsp",
- .class = &omap44xx_mmu_hwmod_class,
- .clkdm_name = "tesla_clkdm",
- .rst_lines = omap44xx_mmu_dsp_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
- .main_clk = "dpll_iva_m4x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
- .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
* 'mpu' class
* mpu sub-system
*/
@@ -1642,51 +519,6 @@
},
};
-/*
- * 'ocp2scp' class
- * bridge to transform ocp interface protocol to scp (serial control port)
- * protocol
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
- .name = "ocp2scp",
- .sysc = &omap44xx_ocp2scp_sysc,
-};
-
-/* ocp2scp_usb_phy */
-static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
- .name = "ocp2scp_usb_phy",
- .class = &omap44xx_ocp2scp_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- /*
- * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
- * block as an "optional clock," and normally should never be
- * specified as the main_clk for an OMAP IP block. However it
- * turns out that this clock is actually the main clock for
- * the ocp2scp_usb_phy IP block:
- * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
- * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
- * to be the best workaround.
- */
- .main_clk = "ocp2scp_usb_phy_phy_48m",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
/*
* 'prcm' class
@@ -1793,588 +625,6 @@
};
/*
- * 'slimbus' class
- * bidirectional, multi-drop, multi-channel two-line serial interface between
- * the device and external components
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
- .name = "slimbus",
- .sysc = &omap44xx_slimbus_sysc,
-};
-
-/* slimbus1 */
-static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
- { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
- { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
- { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
- { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
-};
-
-static struct omap_hwmod omap44xx_slimbus1_hwmod = {
- .name = "slimbus1",
- .class = &omap44xx_slimbus_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = slimbus1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
-};
-
-/* slimbus2 */
-static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
- { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
- { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
- { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
-};
-
-static struct omap_hwmod omap44xx_slimbus2_hwmod = {
- .name = "slimbus2",
- .class = &omap44xx_slimbus_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = slimbus2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
-};
-
-/*
- * 'smartreflex' class
- * smartreflex module (monitor silicon performance and outputs a measure of
- * performance error)
- */
-
-/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
- .rev_offs = -ENODEV,
- .sysc_offs = 0x0038,
- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap36xx_sr_sysc_fields,
-};
-
-static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
- .name = "smartreflex",
- .sysc = &omap44xx_smartreflex_sysc,
-};
-
-/* smartreflex_core */
-static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
- .sensor_voltdm_name = "core",
-};
-
-static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
- .name = "smartreflex_core",
- .class = &omap44xx_smartreflex_hwmod_class,
- .clkdm_name = "l4_ao_clkdm",
-
- .main_clk = "smartreflex_core_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .dev_attr = &smartreflex_core_dev_attr,
-};
-
-/* smartreflex_iva */
-static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
- .sensor_voltdm_name = "iva",
-};
-
-static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
- .name = "smartreflex_iva",
- .class = &omap44xx_smartreflex_hwmod_class,
- .clkdm_name = "l4_ao_clkdm",
- .main_clk = "smartreflex_iva_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .dev_attr = &smartreflex_iva_dev_attr,
-};
-
-/* smartreflex_mpu */
-static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
- .sensor_voltdm_name = "mpu",
-};
-
-static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
- .name = "smartreflex_mpu",
- .class = &omap44xx_smartreflex_hwmod_class,
- .clkdm_name = "l4_ao_clkdm",
- .main_clk = "smartreflex_mpu_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .dev_attr = &smartreflex_mpu_dev_attr,
-};
-
-/*
- * 'spinlock' class
- * spinlock provides hardware assistance for synchronizing the processes
- * running on multiple processors
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
- .name = "spinlock",
- .sysc = &omap44xx_spinlock_sysc,
-};
-
-/* spinlock */
-static struct omap_hwmod omap44xx_spinlock_hwmod = {
- .name = "spinlock",
- .class = &omap44xx_spinlock_hwmod_class,
- .clkdm_name = "l4_cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'timer' class
- * general purpose timer module with accurate 1ms tick
- * This class contains several variants: ['timer_1ms', 'timer']
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
- .name = "timer",
- .sysc = &omap44xx_timer_1ms_sysc,
-};
-
-static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &omap44xx_timer_sysc,
-};
-
-/* timer1 */
-static struct omap_hwmod omap44xx_timer1_hwmod = {
- .name = "timer1",
- .class = &omap44xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "dmt1_clk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer2 */
-static struct omap_hwmod omap44xx_timer2_hwmod = {
- .name = "timer2",
- .class = &omap44xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "cm2_dm2_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer3 */
-static struct omap_hwmod omap44xx_timer3_hwmod = {
- .name = "timer3",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm3_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer4 */
-static struct omap_hwmod omap44xx_timer4_hwmod = {
- .name = "timer4",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm4_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer5 */
-static struct omap_hwmod omap44xx_timer5_hwmod = {
- .name = "timer5",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer5_sync_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer6 */
-static struct omap_hwmod omap44xx_timer6_hwmod = {
- .name = "timer6",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer6_sync_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer7 */
-static struct omap_hwmod omap44xx_timer7_hwmod = {
- .name = "timer7",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer7_sync_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer8 */
-static struct omap_hwmod omap44xx_timer8_hwmod = {
- .name = "timer8",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer8_sync_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer9 */
-static struct omap_hwmod omap44xx_timer9_hwmod = {
- .name = "timer9",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm9_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer10 */
-static struct omap_hwmod omap44xx_timer10_hwmod = {
- .name = "timer10",
- .class = &omap44xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .main_clk = "cm2_dm10_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer11 */
-static struct omap_hwmod omap44xx_timer11_hwmod = {
- .name = "timer11",
- .class = &omap44xx_timer_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .main_clk = "cm2_dm11_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'usb_host_fs' class
- * full-speed usb host controller
- */
-
-/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0210,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
-};
-
-static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
- .name = "usb_host_fs",
- .sysc = &omap44xx_usb_host_fs_sysc,
-};
-
-/* usb_host_fs */
-static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
- .name = "usb_host_fs",
- .class = &omap44xx_usb_host_fs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .main_clk = "usb_host_fs_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'usb_host_hs' class
- * high-speed multi-port usb host controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
- .name = "usb_host_hs",
- .sysc = &omap44xx_usb_host_hs_sysc,
-};
-
-/* usb_host_hs */
-static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
- .name = "usb_host_hs",
- .class = &omap44xx_usb_host_hs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .main_clk = "usb_host_hs_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-
- /*
- * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
- * id: i660
- *
- * Description:
- * In the following configuration :
- * - USBHOST module is set to smart-idle mode
- * - PRCM asserts idle_req to the USBHOST module ( This typically
- * happens when the system is going to a low power mode : all ports
- * have been suspended, the master part of the USBHOST module has
- * entered the standby state, and SW has cut the functional clocks)
- * - an USBHOST interrupt occurs before the module is able to answer
- * idle_ack, typically a remote wakeup IRQ.
- * Then the USB HOST module will enter a deadlock situation where it
- * is no more accessible nor functional.
- *
- * Workaround:
- * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
- */
-
- /*
- * Errata: USB host EHCI may stall when entering smart-standby mode
- * Id: i571
- *
- * Description:
- * When the USBHOST module is set to smart-standby mode, and when it is
- * ready to enter the standby state (i.e. all ports are suspended and
- * all attached devices are in suspend mode), then it can wrongly assert
- * the Mstandby signal too early while there are still some residual OCP
- * transactions ongoing. If this condition occurs, the internal state
- * machine may go to an undefined state and the USB link may be stuck
- * upon the next resume.
- *
- * Workaround:
- * Don't use smart standby; use only force standby,
- * hence HWMOD_SWSUP_MSTANDBY
- */
-
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
-};
-
-/*
- * 'usb_otg_hs' class
- * high-speed on-the-go universal serial bus (usb_otg_hs) controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
- .rev_offs = 0x0400,
- .sysc_offs = 0x0404,
- .syss_offs = 0x0408,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
- .name = "usb_otg_hs",
- .sysc = &omap44xx_usb_otg_hs_sysc,
-};
-
-/* usb_otg_hs */
-static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
- { .role = "xclk", .clk = "usb_otg_hs_xclk" },
-};
-
-static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
- .name = "usb_otg_hs",
- .class = &omap44xx_usb_otg_hs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "usb_otg_hs_ick",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
- .opt_clks = usb_otg_hs_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
-};
-
-/*
- * 'usb_tll_hs' class
- * usb_tll_hs module is the adapter on the usb_host_hs ports
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
- .name = "usb_tll_hs",
- .sysc = &omap44xx_usb_tll_hs_sysc,
-};
-
-static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
- .name = "usb_tll_hs",
- .class = &omap44xx_usb_tll_hs_hwmod_class,
- .clkdm_name = "l3_init_clkdm",
- .main_clk = "usb_tll_hs_ick",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
* interfaces
*/
@@ -2418,22 +668,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dsp -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dss -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
- .master = &omap44xx_dss_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_2 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -2466,38 +700,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* dma_system -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
- .master = &omap44xx_dma_system_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* fdif -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
- .master = &omap44xx_fdif_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* hsi -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
- .master = &omap44xx_hsi_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* ipu -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
- .master = &omap44xx_ipu_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* iss -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
.master = &omap44xx_iss_hwmod,
@@ -2530,30 +732,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* usb_host_fs -> l3_main_2 */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
- .master = &omap44xx_usb_host_fs_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* usb_host_hs -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
- .master = &omap44xx_usb_host_hs_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* usb_otg_hs -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
- .master = &omap44xx_usb_otg_hs_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
.master = &omap44xx_l3_main_1_hwmod,
@@ -2578,38 +756,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* aess -> l4_abe */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
- .master = &omap44xx_aess_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dsp -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_l4_abe_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
.master = &omap44xx_l3_main_1_hwmod,
@@ -2650,30 +796,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_abe -> aess */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_aess_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> aess (dma) */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_aess_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_wkup -> counter_32k */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_counter_32k_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_cfg -> ctrl_module_core */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
.master = &omap44xx_l4_cfg_hwmod,
@@ -2714,182 +836,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_dma_system_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> dmic */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_dmic_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dsp -> iva */
-static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_iva_hwmod,
- .clk = "dpll_iva_m5x2_ck",
- .user = OCP_USER_DSP,
-};
-
-/* dsp -> sl2if */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
- .master = &omap44xx_dsp_hwmod,
- .slave = &omap44xx_sl2if_hwmod,
- .clk = "dpll_iva_m5x2_ck",
- .user = OCP_USER_DSP,
-};
-
-/* l4_cfg -> dsp */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_dsp_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_dispc */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_dispc_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_dispc */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_dispc_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_dsi1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_dsi1_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_dsi2 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_dsi2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_dsi2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_dsi2_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_hdmi_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_hdmi_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_rfbi_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_rfbi_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss_venc */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_dss_venc_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> dss_venc */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_dss_venc_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> sham */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_sha0_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> elm */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_elm_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> fdif */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_fdif_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_2 -> gpmc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -2898,30 +844,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_per -> hdq1w */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_hdq1w_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> hsi */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_hsi_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> ipu */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_ipu_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_2 -> iss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -2946,78 +868,6 @@
.user = OCP_USER_MPU,
};
-/* l4_wkup -> kbd */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_kbd_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> mailbox */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_mailbox_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcasp */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcasp_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> mcasp (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcasp_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp1_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp2_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcbsp3_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_mcbsp4_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcpdm */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_mcpdm_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_2 -> ocmc_ram */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -3026,14 +876,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> ocp2scp_usb_phy */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* mpu_private -> prcm_mpu */
static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
.master = &omap44xx_mpu_private_hwmod,
@@ -3082,182 +924,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_abe -> slimbus1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_slimbus1_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> slimbus1 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_slimbus1_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_SDMA,
-};
-
-/* l4_per -> slimbus2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_slimbus2_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> smartreflex_core */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_smartreflex_core_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> smartreflex_iva */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_smartreflex_iva_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> smartreflex_mpu */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_smartreflex_mpu_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> spinlock */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_spinlock_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_timer1_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer2_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer3_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer4_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> timer5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer5_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> timer6 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer6_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> timer7 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer7_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> timer8 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
- .master = &omap44xx_l4_abe_hwmod,
- .slave = &omap44xx_timer8_hwmod,
- .clk = "ocp_abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer9 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer9_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer10 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer10_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer11 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
- .master = &omap44xx_l4_per_hwmod,
- .slave = &omap44xx_timer11_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_host_fs */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_host_fs_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_host_hs */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_host_hs_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_otg_hs */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_otg_hs_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_tll_hs */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_usb_tll_hs_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* mpu -> emif1 */
static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
.master = &omap44xx_mpu_hwmod,
@@ -3280,118 +946,40 @@
&omap44xx_iva__l3_instr,
&omap44xx_l3_main_3__l3_instr,
&omap44xx_ocp_wp_noc__l3_instr,
- &omap44xx_dsp__l3_main_1,
- &omap44xx_dss__l3_main_1,
&omap44xx_l3_main_2__l3_main_1,
&omap44xx_l4_cfg__l3_main_1,
&omap44xx_mpu__l3_main_1,
&omap44xx_debugss__l3_main_2,
- &omap44xx_dma_system__l3_main_2,
- &omap44xx_fdif__l3_main_2,
- &omap44xx_hsi__l3_main_2,
- &omap44xx_ipu__l3_main_2,
&omap44xx_iss__l3_main_2,
&omap44xx_iva__l3_main_2,
&omap44xx_l3_main_1__l3_main_2,
&omap44xx_l4_cfg__l3_main_2,
- /* &omap44xx_usb_host_fs__l3_main_2, */
- &omap44xx_usb_host_hs__l3_main_2,
- &omap44xx_usb_otg_hs__l3_main_2,
&omap44xx_l3_main_1__l3_main_3,
&omap44xx_l3_main_2__l3_main_3,
&omap44xx_l4_cfg__l3_main_3,
- &omap44xx_aess__l4_abe,
- &omap44xx_dsp__l4_abe,
- &omap44xx_l3_main_1__l4_abe,
- &omap44xx_mpu__l4_abe,
&omap44xx_l3_main_1__l4_cfg,
&omap44xx_l3_main_2__l4_per,
&omap44xx_l4_cfg__l4_wkup,
&omap44xx_mpu__mpu_private,
&omap44xx_l4_cfg__ocp_wp_noc,
- &omap44xx_l4_abe__aess,
- &omap44xx_l4_abe__aess_dma,
- &omap44xx_l4_wkup__counter_32k,
&omap44xx_l4_cfg__ctrl_module_core,
&omap44xx_l4_cfg__ctrl_module_pad_core,
&omap44xx_l4_wkup__ctrl_module_wkup,
&omap44xx_l4_wkup__ctrl_module_pad_wkup,
&omap44xx_l3_instr__debugss,
- &omap44xx_l4_cfg__dma_system,
- &omap44xx_l4_abe__dmic,
- &omap44xx_dsp__iva,
- /* &omap44xx_dsp__sl2if, */
- &omap44xx_l4_cfg__dsp,
- &omap44xx_l3_main_2__dss,
- &omap44xx_l4_per__dss,
- &omap44xx_l3_main_2__dss_dispc,
- &omap44xx_l4_per__dss_dispc,
- &omap44xx_l3_main_2__dss_dsi1,
- &omap44xx_l4_per__dss_dsi1,
- &omap44xx_l3_main_2__dss_dsi2,
- &omap44xx_l4_per__dss_dsi2,
- &omap44xx_l3_main_2__dss_hdmi,
- &omap44xx_l4_per__dss_hdmi,
- &omap44xx_l3_main_2__dss_rfbi,
- &omap44xx_l4_per__dss_rfbi,
- &omap44xx_l3_main_2__dss_venc,
- &omap44xx_l4_per__dss_venc,
- &omap44xx_l4_per__elm,
- &omap44xx_l4_cfg__fdif,
&omap44xx_l3_main_2__gpmc,
- &omap44xx_l4_per__hdq1w,
- &omap44xx_l4_cfg__hsi,
- &omap44xx_l3_main_2__ipu,
&omap44xx_l3_main_2__iss,
/* &omap44xx_iva__sl2if, */
&omap44xx_l3_main_2__iva,
- &omap44xx_l4_wkup__kbd,
- &omap44xx_l4_cfg__mailbox,
- &omap44xx_l4_abe__mcasp,
- &omap44xx_l4_abe__mcasp_dma,
- &omap44xx_l4_abe__mcbsp1,
- &omap44xx_l4_abe__mcbsp2,
- &omap44xx_l4_abe__mcbsp3,
- &omap44xx_l4_per__mcbsp4,
- &omap44xx_l4_abe__mcpdm,
- &omap44xx_l3_main_2__mmu_ipu,
- &omap44xx_l4_cfg__mmu_dsp,
&omap44xx_l3_main_2__ocmc_ram,
- &omap44xx_l4_cfg__ocp2scp_usb_phy,
&omap44xx_mpu_private__prcm_mpu,
&omap44xx_l4_wkup__cm_core_aon,
&omap44xx_l4_cfg__cm_core,
&omap44xx_l4_wkup__prm,
&omap44xx_l4_wkup__scrm,
/* &omap44xx_l3_main_2__sl2if, */
- &omap44xx_l4_abe__slimbus1,
- &omap44xx_l4_abe__slimbus1_dma,
- &omap44xx_l4_per__slimbus2,
- &omap44xx_l4_cfg__smartreflex_core,
- &omap44xx_l4_cfg__smartreflex_iva,
- &omap44xx_l4_cfg__smartreflex_mpu,
- &omap44xx_l4_cfg__spinlock,
- &omap44xx_l4_wkup__timer1,
- &omap44xx_l4_per__timer2,
- &omap44xx_l4_per__timer3,
- &omap44xx_l4_per__timer4,
- &omap44xx_l4_abe__timer5,
- &omap44xx_l4_abe__timer6,
- &omap44xx_l4_abe__timer7,
- &omap44xx_l4_abe__timer8,
- &omap44xx_l4_per__timer9,
- &omap44xx_l4_per__timer10,
- &omap44xx_l4_per__timer11,
- /* &omap44xx_l4_cfg__usb_host_fs, */
- &omap44xx_l4_cfg__usb_host_hs,
- &omap44xx_l4_cfg__usb_otg_hs,
- &omap44xx_l4_cfg__usb_tll_hs,
&omap44xx_mpu__emif1,
&omap44xx_mpu__emif2,
- &omap44xx_l3_main_2__aes1,
- &omap44xx_l3_main_2__aes2,
- &omap44xx_l3_main_2__des,
- &omap44xx_l3_main_2__sha0,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 8006b43..85b9ab4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -2,7 +2,7 @@
/*
* Hardware modules present on the OMAP54xx chips
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley
* Benoit Cousson
@@ -17,22 +17,15 @@
#include <linux/io.h>
#include <linux/power/smartreflex.h>
-#include <linux/omap-dma.h>
-
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include "cm1_54xx.h"
#include "cm2_54xx.h"
#include "prm54xx.h"
-#include "wd_timer.h"
/* Base offset for all OMAP5 interrupts external to MPUSS */
#define OMAP54XX_IRQ_GIC_START 32
-/* Base offset for all OMAP5 dma requests */
-#define OMAP54XX_DMA_REQ_START 1
-
-
/*
* IP blocks
*/
@@ -128,19 +121,6 @@
.name = "l4",
};
-/* l4_abe */
-static struct omap_hwmod omap54xx_l4_abe_hwmod = {
- .name = "l4_abe",
- .class = &omap54xx_l4_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
/* l4_cfg */
static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
.name = "l4_cfg",
@@ -201,354 +181,6 @@
};
/*
- * 'counter' class
- * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
- .name = "counter",
- .sysc = &omap54xx_counter_sysc,
-};
-
-/* counter_32k */
-static struct omap_hwmod omap54xx_counter_32k_hwmod = {
- .name = "counter_32k",
- .class = &omap54xx_counter_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wkupaon_iclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'dma' class
- * dma controller for data exchange between memory to memory (i.e. internal or
- * external memory) and gp peripherals to memory or memory to gp peripherals
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap54xx_dma_sysc,
-};
-
-/* dma dev_attr */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-/* dma_system */
-static struct omap_hwmod omap54xx_dma_system_hwmod = {
- .name = "dma_system",
- .class = &omap54xx_dma_hwmod_class,
- .clkdm_name = "dma_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
- },
- },
- .dev_attr = &dma_dev_attr,
-};
-
-/*
- * 'dmic' class
- * digital microphone controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
- .name = "dmic",
- .sysc = &omap54xx_dmic_sysc,
-};
-
-/* dmic */
-static struct omap_hwmod omap54xx_dmic_hwmod = {
- .name = "dmic",
- .class = &omap54xx_dmic_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "dmic_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'dss' class
- * display sub-system
- */
-static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
- .rev_offs = 0x0000,
- .syss_offs = 0x0014,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
- .name = "dss",
- .sysc = &omap54xx_dss_sysc,
- .reset = omap_dss_reset,
-};
-
-/* dss */
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- { .role = "32khz_clk", .clk = "dss_32khz_clk" },
- { .role = "sys_clk", .clk = "dss_sys_clk" },
- { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
-};
-
-static struct omap_hwmod omap54xx_dss_hwmod = {
- .name = "dss_core",
- .class = &omap54xx_dss_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-};
-
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap54xx_dispc_sysc,
-};
-
-/* dss_dispc */
-static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-/* dss_dispc dev_attr */
-static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
- .has_framedonetv_irq = 1,
- .manager_count = 4,
-};
-
-static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &omap54xx_dispc_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_dispc_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
- .dev_attr = &dss_dispc_dev_attr,
- .parent_hwmod = &omap54xx_dss_hwmod,
-};
-
-/*
- * 'dsi1' class
- * display serial interface controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
- .name = "dsi1",
- .sysc = &omap54xx_dsi1_sysc,
-};
-
-/* dss_dsi1_a */
-static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
- .name = "dss_dsi1",
- .class = &omap54xx_dsi1_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_dsi1_a_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
- .parent_hwmod = &omap54xx_dss_hwmod,
-};
-
-/* dss_dsi1_c */
-static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
- .name = "dss_dsi2",
- .class = &omap54xx_dsi1_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_dsi1_c_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
- .parent_hwmod = &omap54xx_dss_hwmod,
-};
-
-/*
- * 'hdmi' class
- * hdmi controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
- .name = "hdmi",
- .sysc = &omap54xx_hdmi_sysc,
-};
-
-static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_sys_clk" },
-};
-
-static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
- .name = "dss_hdmi",
- .class = &omap54xx_hdmi_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_48mhz_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_hdmi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
- .parent_hwmod = &omap54xx_dss_hwmod,
-};
-
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
- .name = "rfbi",
- .sysc = &omap54xx_rfbi_sysc,
-};
-
-/* dss_rfbi */
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
- { .role = "ick", .clk = "l3_iclk_div" },
-};
-
-static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
- .name = "dss_rfbi",
- .class = &omap54xx_rfbi_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_rfbi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
- .parent_hwmod = &omap54xx_dss_hwmod,
-};
-
-/*
* 'emif' class
* external memory interface no1 (wrapper)
*/
@@ -594,352 +226,8 @@
},
};
-/*
- * 'kbd' class
- * keyboard controller
- */
-static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
- .name = "kbd",
- .sysc = &omap54xx_kbd_sysc,
-};
-
-/* kbd */
-static struct omap_hwmod omap54xx_kbd_hwmod = {
- .name = "kbd",
- .class = &omap54xx_kbd_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors using a
- * queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &omap54xx_mailbox_sysc,
-};
-
-/* mailbox */
-static struct omap_hwmod omap54xx_mailbox_hwmod = {
- .name = "mailbox",
- .class = &omap54xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
- .rev_offs = -ENODEV,
- .sysc_offs = 0x008c,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
- .name = "mcbsp",
- .sysc = &omap54xx_mcbsp_sysc,
-};
-
-/* mcbsp1 */
-static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
- .name = "mcbsp1",
- .class = &omap54xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "mcbsp1_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
-};
-
-/* mcbsp2 */
-static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
- .name = "mcbsp2",
- .class = &omap54xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "mcbsp2_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
-};
-
-/* mcbsp3 */
-static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
- { .role = "pad_fck", .clk = "pad_clks_ck" },
- { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
-};
-
-static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
- .name = "mcbsp3",
- .class = &omap54xx_mcbsp_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "mcbsp3_gfclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = mcbsp3_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
-};
-
-/*
- * 'mcpdm' class
- * multi channel pdm controller (proprietary interface with phoenix power
- * ic)
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
- .name = "mcpdm",
- .sysc = &omap54xx_mcpdm_sysc,
-};
-
-/* mcpdm */
-static struct omap_hwmod omap54xx_mcpdm_hwmod = {
- .name = "mcpdm",
- .class = &omap54xx_mcpdm_hwmod_class,
- .clkdm_name = "abe_clkdm",
- /*
- * It's suspected that the McPDM requires an off-chip main
- * functional clock, controlled via I2C. This IP block is
- * currently reset very early during boot, before I2C is
- * available, so it doesn't seem that we have any choice in
- * the kernel other than to avoid resetting it. XXX This is
- * really a hardware issue workaround: every IP block should
- * be able to source its main functional clock from either
- * on-chip or off-chip sources. McPDM seems to be the only
- * current exception.
- */
-
- .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
- .main_clk = "pad_clks_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mcspi' class
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
- * bus
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
- .name = "mcspi",
- .sysc = &omap54xx_mcspi_sysc,
-};
-
-/* mcspi1 */
-static struct omap_hwmod omap54xx_mcspi1_hwmod = {
- .name = "mcspi1",
- .class = &omap54xx_mcspi_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* mcspi2 */
-static struct omap_hwmod omap54xx_mcspi2_hwmod = {
- .name = "mcspi2",
- .class = &omap54xx_mcspi_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* mcspi3 */
-static struct omap_hwmod omap54xx_mcspi3_hwmod = {
- .name = "mcspi3",
- .class = &omap54xx_mcspi_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* mcspi4 */
-static struct omap_hwmod omap54xx_mcspi4_hwmod = {
- .name = "mcspi4",
- .class = &omap54xx_mcspi_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "func_48m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mmu' class
- * The memory management unit performs virtual to physical address translation
- * for its requestors.
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
- .name = "mmu",
- .sysc = &omap54xx_mmu_sysc,
-};
-
-static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
- { .name = "mmu_cache", .rst_shift = 1 },
-};
-
-static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
- .name = "mmu_dsp",
- .class = &omap54xx_mmu_hwmod_class,
- .clkdm_name = "dsp_clkdm",
- .rst_lines = omap54xx_mmu_dsp_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
- .main_clk = "dpll_iva_h11x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* mmu ipu */
-static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
- { .name = "mmu_cache", .rst_shift = 2 },
-};
-
-static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
- .name = "mmu_ipu",
- .class = &omap54xx_mmu_hwmod_class,
- .clkdm_name = "ipu_clkdm",
- .rst_lines = omap54xx_mmu_ipu_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
- .main_clk = "dpll_core_h22x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
- .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
/*
* 'mpu' class
@@ -966,499 +254,6 @@
};
/*
- * 'spinlock' class
- * spinlock provides hardware assistance for synchronizing the processes
- * running on multiple processors
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
- .name = "spinlock",
- .sysc = &omap54xx_spinlock_sysc,
-};
-
-/* spinlock */
-static struct omap_hwmod omap54xx_spinlock_hwmod = {
- .name = "spinlock",
- .class = &omap54xx_spinlock_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'ocp2scp' class
- * bridge to transform ocp interface protocol to scp (serial control port)
- * protocol
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
- .name = "ocp2scp",
- .sysc = &omap54xx_ocp2scp_sysc,
-};
-
-/* ocp2scp1 */
-static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
- .name = "ocp2scp1",
- .class = &omap54xx_ocp2scp_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'timer' class
- * general purpose timer module with accurate 1ms tick
- * This class contains several variants: ['timer_1ms', 'timer']
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
- .name = "timer",
- .sysc = &omap54xx_timer_1ms_sysc,
-};
-
-static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &omap54xx_timer_sysc,
-};
-
-/* timer1 */
-static struct omap_hwmod omap54xx_timer1_hwmod = {
- .name = "timer1",
- .class = &omap54xx_timer_1ms_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "timer1_gfclk_mux",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer2 */
-static struct omap_hwmod omap54xx_timer2_hwmod = {
- .name = "timer2",
- .class = &omap54xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer2_gfclk_mux",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer3 */
-static struct omap_hwmod omap54xx_timer3_hwmod = {
- .name = "timer3",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer3_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer4 */
-static struct omap_hwmod omap54xx_timer4_hwmod = {
- .name = "timer4",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer4_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer5 */
-static struct omap_hwmod omap54xx_timer5_hwmod = {
- .name = "timer5",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer5_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer6 */
-static struct omap_hwmod omap54xx_timer6_hwmod = {
- .name = "timer6",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer6_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer7 */
-static struct omap_hwmod omap54xx_timer7_hwmod = {
- .name = "timer7",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer7_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer8 */
-static struct omap_hwmod omap54xx_timer8_hwmod = {
- .name = "timer8",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "abe_clkdm",
- .main_clk = "timer8_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer9 */
-static struct omap_hwmod omap54xx_timer9_hwmod = {
- .name = "timer9",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer9_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer10 */
-static struct omap_hwmod omap54xx_timer10_hwmod = {
- .name = "timer10",
- .class = &omap54xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer10_gfclk_mux",
- .flags = HWMOD_SET_DEFAULT_CLOCKACT,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer11 */
-static struct omap_hwmod omap54xx_timer11_hwmod = {
- .name = "timer11",
- .class = &omap54xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer11_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'usb_host_hs' class
- * high-speed multi-port usb host controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
- .name = "usb_host_hs",
- .sysc = &omap54xx_usb_host_hs_sysc,
-};
-
-static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
- .name = "usb_host_hs",
- .class = &omap54xx_usb_host_hs_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- /*
- * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
- * id: i660
- *
- * Description:
- * In the following configuration :
- * - USBHOST module is set to smart-idle mode
- * - PRCM asserts idle_req to the USBHOST module ( This typically
- * happens when the system is going to a low power mode : all ports
- * have been suspended, the master part of the USBHOST module has
- * entered the standby state, and SW has cut the functional clocks)
- * - an USBHOST interrupt occurs before the module is able to answer
- * idle_ack, typically a remote wakeup IRQ.
- * Then the USB HOST module will enter a deadlock situation where it
- * is no more accessible nor functional.
- *
- * Workaround:
- * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
- */
-
- /*
- * Errata: USB host EHCI may stall when entering smart-standby mode
- * Id: i571
- *
- * Description:
- * When the USBHOST module is set to smart-standby mode, and when it is
- * ready to enter the standby state (i.e. all ports are suspended and
- * all attached devices are in suspend mode), then it can wrongly assert
- * the Mstandby signal too early while there are still some residual OCP
- * transactions ongoing. If this condition occurs, the internal state
- * machine may go to an undefined state and the USB link may be stuck
- * upon the next resume.
- *
- * Workaround:
- * Don't use smart standby; use only force standby,
- * hence HWMOD_SWSUP_MSTANDBY
- */
-
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "l3init_60m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'usb_tll_hs' class
- * usb_tll_hs module is the adapter on the usb_host_hs ports
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
- .name = "usb_tll_hs",
- .sysc = &omap54xx_usb_tll_hs_sysc,
-};
-
-static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
- .name = "usb_tll_hs",
- .class = &omap54xx_usb_tll_hs_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'usb_otg_ss' class
- * 2.0 super speed (usb_otg_ss) controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
- .name = "usb_otg_ss",
- .sysc = &omap54xx_usb_otg_ss_sysc,
-};
-
-/* usb_otg_ss */
-static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
- { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
-};
-
-static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
- .name = "usb_otg_ss",
- .class = &omap54xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "dpll_core_h13x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
- .opt_clks = usb_otg_ss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
-};
-
-/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &omap54xx_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable,
-};
-
-/* wd_timer2 */
-static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
- .name = "wd_timer2",
- .class = &omap54xx_wd_timer_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'ocp2scp' class
- * bridge to transform ocp interface protocol to scp (serial control port)
- * protocol
- */
-/* ocp2scp3 */
-static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
-/* l4_cfg -> ocp2scp3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_ocp2scp3_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
- .name = "ocp2scp3",
- .class = &omap54xx_ocp2scp_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
* 'sata' class
* sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
*/
@@ -1539,14 +334,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> mmu_dsp */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_mmu_dsp_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* mpu -> l3_main_1 */
static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
.master = &omap54xx_mpu_hwmod,
@@ -1571,14 +358,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l3_main_2 -> mmu_ipu */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_mmu_ipu_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
.master = &omap54xx_l3_main_1_hwmod,
@@ -1603,22 +382,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l3_main_1 -> l4_abe */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
- .master = &omap54xx_l3_main_1_hwmod,
- .slave = &omap54xx_l4_abe_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> l4_abe */
-static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
- .master = &omap54xx_mpu_hwmod,
- .slave = &omap54xx_l4_abe_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
.master = &omap54xx_l3_main_1_hwmod,
@@ -1651,78 +414,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> counter_32k */
-static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
- .master = &omap54xx_l4_wkup_hwmod,
- .slave = &omap54xx_counter_32k_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_dma_system_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> dmic */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_dmic_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> dss */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss_dispc */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_dispc_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss_dsi1_a */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_dsi1_a_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss_dsi1_c */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_dsi1_c_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_hdmi_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_dss_rfbi_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* mpu -> emif1 */
static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
.master = &omap54xx_mpu_hwmod,
@@ -1739,86 +430,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> kbd */
-static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
- .master = &omap54xx_l4_wkup_hwmod,
- .slave = &omap54xx_kbd_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> mailbox */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_mailbox_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_mcbsp1_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_mcbsp2_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_mcbsp3_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> mcpdm */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_mcpdm_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_per -> mcspi1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_mcspi1_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcspi2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_mcspi2_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcspi3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_mcspi3_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcspi4 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_mcspi4_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_cfg -> mpu */
static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
.master = &omap54xx_l4_cfg_hwmod,
@@ -1827,142 +438,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> spinlock */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_spinlock_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> ocp2scp1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_ocp2scp1_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
- .master = &omap54xx_l4_wkup_hwmod,
- .slave = &omap54xx_timer1_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer2_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer3_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer4 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer4_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_abe -> timer5 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_timer5_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> timer6 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_timer6_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> timer7 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_timer7_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_abe -> timer8 */
-static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
- .master = &omap54xx_l4_abe_hwmod,
- .slave = &omap54xx_timer8_hwmod,
- .clk = "abe_iclk",
- .user = OCP_USER_MPU,
-};
-
-/* l4_per -> timer9 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer9_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer10 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer10_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> timer11 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
- .master = &omap54xx_l4_per_hwmod,
- .slave = &omap54xx_timer11_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_host_hs */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_usb_host_hs_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_tll_hs */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_usb_tll_hs_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> usb_otg_ss */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_usb_otg_ss_hwmod,
- .clk = "dpll_core_h13x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
- .master = &omap54xx_l4_wkup_hwmod,
- .slave = &omap54xx_wd_timer2_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
&omap54xx_l3_main_1__dmm,
&omap54xx_l3_main_3__l3_instr,
@@ -1974,54 +449,13 @@
&omap54xx_l3_main_1__l3_main_3,
&omap54xx_l3_main_2__l3_main_3,
&omap54xx_l4_cfg__l3_main_3,
- &omap54xx_l3_main_1__l4_abe,
- &omap54xx_mpu__l4_abe,
&omap54xx_l3_main_1__l4_cfg,
&omap54xx_l3_main_2__l4_per,
&omap54xx_l3_main_1__l4_wkup,
&omap54xx_mpu__mpu_private,
- &omap54xx_l4_wkup__counter_32k,
- &omap54xx_l4_cfg__dma_system,
- &omap54xx_l4_abe__dmic,
- &omap54xx_l4_cfg__mmu_dsp,
- &omap54xx_l3_main_2__dss,
- &omap54xx_l3_main_2__dss_dispc,
- &omap54xx_l3_main_2__dss_dsi1_a,
- &omap54xx_l3_main_2__dss_dsi1_c,
- &omap54xx_l3_main_2__dss_hdmi,
- &omap54xx_l3_main_2__dss_rfbi,
&omap54xx_mpu__emif1,
&omap54xx_mpu__emif2,
- &omap54xx_l3_main_2__mmu_ipu,
- &omap54xx_l4_wkup__kbd,
- &omap54xx_l4_cfg__mailbox,
- &omap54xx_l4_abe__mcbsp1,
- &omap54xx_l4_abe__mcbsp2,
- &omap54xx_l4_abe__mcbsp3,
- &omap54xx_l4_abe__mcpdm,
- &omap54xx_l4_per__mcspi1,
- &omap54xx_l4_per__mcspi2,
- &omap54xx_l4_per__mcspi3,
- &omap54xx_l4_per__mcspi4,
&omap54xx_l4_cfg__mpu,
- &omap54xx_l4_cfg__spinlock,
- &omap54xx_l4_cfg__ocp2scp1,
- &omap54xx_l4_wkup__timer1,
- &omap54xx_l4_per__timer2,
- &omap54xx_l4_per__timer3,
- &omap54xx_l4_per__timer4,
- &omap54xx_l4_abe__timer5,
- &omap54xx_l4_abe__timer6,
- &omap54xx_l4_abe__timer7,
- &omap54xx_l4_abe__timer8,
- &omap54xx_l4_per__timer9,
- &omap54xx_l4_per__timer10,
- &omap54xx_l4_per__timer11,
- &omap54xx_l4_cfg__usb_host_hs,
- &omap54xx_l4_cfg__usb_tll_hs,
- &omap54xx_l4_cfg__usb_otg_ss,
- &omap54xx_l4_wkup__wd_timer2,
- &omap54xx_l4_cfg__ocp2scp3,
&omap54xx_l4_cfg__sata,
NULL,
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index e5bd549..05e163c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -2,7 +2,7 @@
/*
* Hardware modules present on the DRA7xx chips
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley
* Benoit Cousson
@@ -15,25 +15,17 @@
*/
#include <linux/io.h>
-#include <linux/power/smartreflex.h>
-
-#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include "cm1_7xx.h"
#include "cm2_7xx.h"
#include "prm7xx.h"
-#include "wd_timer.h"
#include "soc.h"
/* Base offset for all DRA7XX interrupts external to MPUSS */
#define DRA7XX_IRQ_GIC_START 32
-/* Base offset for all DRA7XX dma requests */
-#define DRA7XX_DMA_REQ_START 1
-
-
/*
* IP blocks
*/
@@ -230,40 +222,6 @@
};
/*
- * 'counter' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
- .name = "counter",
- .sysc = &dra7xx_counter_sysc,
-};
-
-/* counter_32k */
-static struct omap_hwmod dra7xx_counter_32k_hwmod = {
- .name = "counter_32k",
- .class = &dra7xx_counter_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .flags = HWMOD_SWSUP_SIDLE,
- .main_clk = "wkupaon_iclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
* 'ctrl_module' class
*
*/
@@ -285,456 +243,6 @@
};
/*
- * 'dcan' class
- *
- */
-
-static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
- .name = "dcan",
-};
-
-/* dcan1 */
-static struct omap_hwmod dra7xx_dcan1_hwmod = {
- .name = "dcan1",
- .class = &dra7xx_dcan_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "dcan1_sys_clk_mux",
- .flags = HWMOD_CLKDM_NOAUTO,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* dcan2 */
-static struct omap_hwmod dra7xx_dcan2_hwmod = {
- .name = "dcan2",
- .class = &dra7xx_dcan_hwmod_class,
- .clkdm_name = "l4per2_clkdm",
- .main_clk = "sys_clkin1",
- .flags = HWMOD_CLKDM_NOAUTO,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* pwmss */
-static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x4,
- .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_RESET_STATUS,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-/*
- * epwmss class
- */
-static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
- .name = "epwmss",
- .sysc = &dra7xx_epwmss_sysc,
-};
-
-/* epwmss0 */
-static struct omap_hwmod dra7xx_epwmss0_hwmod = {
- .name = "epwmss0",
- .class = &dra7xx_epwmss_hwmod_class,
- .clkdm_name = "l4per2_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
- },
- },
-};
-
-/* epwmss1 */
-static struct omap_hwmod dra7xx_epwmss1_hwmod = {
- .name = "epwmss1",
- .class = &dra7xx_epwmss_hwmod_class,
- .clkdm_name = "l4per2_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
- },
- },
-};
-
-/* epwmss2 */
-static struct omap_hwmod dra7xx_epwmss2_hwmod = {
- .name = "epwmss2",
- .class = &dra7xx_epwmss_hwmod_class,
- .clkdm_name = "l4per2_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .modulemode = MODULEMODE_SWCTRL,
- .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'dma' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
- .name = "dma",
- .sysc = &dra7xx_dma_sysc,
-};
-
-/* dma dev_attr */
-static struct omap_dma_dev_attr dma_dev_attr = {
- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
- .lch_count = 32,
-};
-
-/* dma_system */
-static struct omap_hwmod dra7xx_dma_system_hwmod = {
- .name = "dma_system",
- .class = &dra7xx_dma_hwmod_class,
- .clkdm_name = "dma_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
- },
- },
- .dev_attr = &dma_dev_attr,
-};
-
-/*
- * 'tpcc' class
- *
- */
-static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
- .name = "tpcc",
-};
-
-static struct omap_hwmod dra7xx_tpcc_hwmod = {
- .name = "tpcc",
- .class = &dra7xx_tpcc_hwmod_class,
- .clkdm_name = "l3main1_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'tptc' class
- *
- */
-static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
- .name = "tptc",
-};
-
-/* tptc0 */
-static struct omap_hwmod dra7xx_tptc0_hwmod = {
- .name = "tptc0",
- .class = &dra7xx_tptc_hwmod_class,
- .clkdm_name = "l3main1_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* tptc1 */
-static struct omap_hwmod dra7xx_tptc1_hwmod = {
- .name = "tptc1",
- .class = &dra7xx_tptc_hwmod_class,
- .clkdm_name = "l3main1_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'dss' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
- .rev_offs = 0x0000,
- .syss_offs = 0x0014,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
- .name = "dss",
- .sysc = &dra7xx_dss_sysc,
- .reset = omap_dss_reset,
-};
-
-/* dss */
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
- { .role = "dss_clk", .clk = "dss_dss_clk" },
- { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
- { .role = "32khz_clk", .clk = "dss_32khz_clk" },
- { .role = "video2_clk", .clk = "dss_video2_clk" },
- { .role = "video1_clk", .clk = "dss_video1_clk" },
- { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
- { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
-};
-
-static struct omap_hwmod dra7xx_dss_hwmod = {
- .name = "dss_core",
- .class = &dra7xx_dss_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = dss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-};
-
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &dra7xx_dispc_sysc,
-};
-
-/* dss_dispc */
-/* dss_dispc dev_attr */
-static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
- .has_framedonetv_irq = 1,
- .manager_count = 4,
-};
-
-static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
- .name = "dss_dispc",
- .class = &dra7xx_dispc_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_dss_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .dev_attr = &dss_dispc_dev_attr,
- .parent_hwmod = &dra7xx_dss_hwmod,
-};
-
-/*
- * 'hdmi' class
- * hdmi controller
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
- .name = "hdmi",
- .sysc = &dra7xx_hdmi_sysc,
-};
-
-/* dss_hdmi */
-
-static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
- { .role = "sys_clk", .clk = "dss_hdmi_clk" },
-};
-
-static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
- .name = "dss_hdmi",
- .class = &dra7xx_hdmi_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dss_48mhz_clk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
- .opt_clks = dss_hdmi_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
- .parent_hwmod = &dra7xx_dss_hwmod,
-};
-
-/* AES (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
- .rev_offs = 0x0080,
- .sysc_offs = 0x0084,
- .syss_offs = 0x0088,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
- .name = "aes",
- .sysc = &dra7xx_aes_sysc,
-};
-
-/* AES1 */
-static struct omap_hwmod dra7xx_aes1_hwmod = {
- .name = "aes1",
- .class = &dra7xx_aes_hwmod_class,
- .clkdm_name = "l4sec_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* AES2 */
-static struct omap_hwmod dra7xx_aes2_hwmod = {
- .name = "aes2",
- .class = &dra7xx_aes_hwmod_class,
- .clkdm_name = "l4sec_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* sha0 HIB2 (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
- .rev_offs = 0x100,
- .sysc_offs = 0x110,
- .syss_offs = 0x114,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
- .name = "sham",
- .sysc = &dra7xx_sha0_sysc,
-};
-
-struct omap_hwmod dra7xx_sha0_hwmod = {
- .name = "sham",
- .class = &dra7xx_sha0_hwmod_class,
- .clkdm_name = "l4sec_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'elm' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
- .name = "elm",
- .sysc = &dra7xx_elm_sysc,
-};
-
-/* elm */
-
-static struct omap_hwmod dra7xx_elm_hwmod = {
- .name = "elm",
- .class = &dra7xx_elm_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
* 'gpmc' class
*
*/
@@ -772,229 +280,7 @@
},
};
-/*
- * 'hdq1w' class
- *
- */
-static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0014,
- .syss_offs = 0x0018,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
- .name = "hdq1w",
- .sysc = &dra7xx_hdq1w_sysc,
-};
-
-/* hdq1w */
-
-static struct omap_hwmod dra7xx_hdq1w_hwmod = {
- .name = "hdq1w",
- .class = &dra7xx_hdq1w_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .flags = HWMOD_INIT_NO_RESET,
- .main_clk = "func_12m_fclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'mailbox' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &dra7xx_mailbox_sysc,
-};
-
-/* mailbox1 */
-static struct omap_hwmod dra7xx_mailbox1_hwmod = {
- .name = "mailbox1",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox2 */
-static struct omap_hwmod dra7xx_mailbox2_hwmod = {
- .name = "mailbox2",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox3 */
-static struct omap_hwmod dra7xx_mailbox3_hwmod = {
- .name = "mailbox3",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox4 */
-static struct omap_hwmod dra7xx_mailbox4_hwmod = {
- .name = "mailbox4",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox5 */
-static struct omap_hwmod dra7xx_mailbox5_hwmod = {
- .name = "mailbox5",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox6 */
-static struct omap_hwmod dra7xx_mailbox6_hwmod = {
- .name = "mailbox6",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox7 */
-static struct omap_hwmod dra7xx_mailbox7_hwmod = {
- .name = "mailbox7",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox8 */
-static struct omap_hwmod dra7xx_mailbox8_hwmod = {
- .name = "mailbox8",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox9 */
-static struct omap_hwmod dra7xx_mailbox9_hwmod = {
- .name = "mailbox9",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox10 */
-static struct omap_hwmod dra7xx_mailbox10_hwmod = {
- .name = "mailbox10",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox11 */
-static struct omap_hwmod dra7xx_mailbox11_hwmod = {
- .name = "mailbox11",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox12 */
-static struct omap_hwmod dra7xx_mailbox12_hwmod = {
- .name = "mailbox12",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
- },
- },
-};
-
-/* mailbox13 */
-static struct omap_hwmod dra7xx_mailbox13_hwmod = {
- .name = "mailbox13",
- .class = &dra7xx_mailbox_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
- },
- },
-};
/*
* 'mpu' class
@@ -1020,55 +306,6 @@
},
};
-/*
- * 'ocp2scp' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
- .name = "ocp2scp",
- .sysc = &dra7xx_ocp2scp_sysc,
-};
-
-/* ocp2scp1 */
-static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
- .name = "ocp2scp1",
- .class = &dra7xx_ocp2scp_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* ocp2scp3 */
-static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
- .name = "ocp2scp3",
- .class = &dra7xx_ocp2scp_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
/*
* 'PCIE' class
@@ -1182,41 +419,6 @@
};
/*
- * 'rtcss' class
- *
- */
-static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
- .rev_offs = 0x0074,
- .sysc_offs = 0x0078,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
- .name = "rtcss",
- .sysc = &dra7xx_rtcss_sysc,
- .unlock = &omap_hwmod_rtc_unlock,
- .lock = &omap_hwmod_rtc_lock,
-};
-
-/* rtcss */
-static struct omap_hwmod dra7xx_rtcss_hwmod = {
- .name = "rtcss",
- .class = &dra7xx_rtcss_hwmod_class,
- .clkdm_name = "rtc_clkdm",
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
* 'sata' class
*
*/
@@ -1255,530 +457,6 @@
};
/*
- * 'smartreflex' class
- *
- */
-
-/* The IP is not compliant to type1 / type2 scheme */
-static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
- .rev_offs = -ENODEV,
- .sysc_offs = 0x0038,
- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap36xx_sr_sysc_fields,
-};
-
-static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
- .name = "smartreflex",
- .sysc = &dra7xx_smartreflex_sysc,
-};
-
-/* smartreflex_core */
-/* smartreflex_core dev_attr */
-static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
- .sensor_voltdm_name = "core",
-};
-
-static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
- .name = "smartreflex_core",
- .class = &dra7xx_smartreflex_hwmod_class,
- .clkdm_name = "coreaon_clkdm",
- .main_clk = "wkupaon_iclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .dev_attr = &smartreflex_core_dev_attr,
-};
-
-/* smartreflex_mpu */
-/* smartreflex_mpu dev_attr */
-static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
- .sensor_voltdm_name = "mpu",
-};
-
-static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
- .name = "smartreflex_mpu",
- .class = &dra7xx_smartreflex_hwmod_class,
- .clkdm_name = "coreaon_clkdm",
- .main_clk = "wkupaon_iclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .dev_attr = &smartreflex_mpu_dev_attr,
-};
-
-/*
- * 'spinlock' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
- .name = "spinlock",
- .sysc = &dra7xx_spinlock_sysc,
-};
-
-/* spinlock */
-static struct omap_hwmod dra7xx_spinlock_hwmod = {
- .name = "spinlock",
- .class = &dra7xx_spinlock_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'timer' class
- *
- * This class contains several variants: ['timer_1ms', 'timer_secure',
- * 'timer']
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
- .name = "timer",
- .sysc = &dra7xx_timer_1ms_sysc,
-};
-
-static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
- .name = "timer",
- .sysc = &dra7xx_timer_sysc,
-};
-
-/* timer1 */
-static struct omap_hwmod dra7xx_timer1_hwmod = {
- .name = "timer1",
- .class = &dra7xx_timer_1ms_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "timer1_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer2 */
-static struct omap_hwmod dra7xx_timer2_hwmod = {
- .name = "timer2",
- .class = &dra7xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer2_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer3 */
-static struct omap_hwmod dra7xx_timer3_hwmod = {
- .name = "timer3",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer3_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer4 */
-static struct omap_hwmod dra7xx_timer4_hwmod = {
- .name = "timer4",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer4_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer5 */
-static struct omap_hwmod dra7xx_timer5_hwmod = {
- .name = "timer5",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "ipu_clkdm",
- .main_clk = "timer5_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer6 */
-static struct omap_hwmod dra7xx_timer6_hwmod = {
- .name = "timer6",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "ipu_clkdm",
- .main_clk = "timer6_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer7 */
-static struct omap_hwmod dra7xx_timer7_hwmod = {
- .name = "timer7",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "ipu_clkdm",
- .main_clk = "timer7_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer8 */
-static struct omap_hwmod dra7xx_timer8_hwmod = {
- .name = "timer8",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "ipu_clkdm",
- .main_clk = "timer8_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer9 */
-static struct omap_hwmod dra7xx_timer9_hwmod = {
- .name = "timer9",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer9_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer10 */
-static struct omap_hwmod dra7xx_timer10_hwmod = {
- .name = "timer10",
- .class = &dra7xx_timer_1ms_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer10_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer11 */
-static struct omap_hwmod dra7xx_timer11_hwmod = {
- .name = "timer11",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .main_clk = "timer11_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer12 */
-static struct omap_hwmod dra7xx_timer12_hwmod = {
- .name = "timer12",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "secure_32k_clk_src_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
- },
- },
-};
-
-/* timer13 */
-static struct omap_hwmod dra7xx_timer13_hwmod = {
- .name = "timer13",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per3_clkdm",
- .main_clk = "timer13_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer14 */
-static struct omap_hwmod dra7xx_timer14_hwmod = {
- .name = "timer14",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per3_clkdm",
- .main_clk = "timer14_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer15 */
-static struct omap_hwmod dra7xx_timer15_hwmod = {
- .name = "timer15",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per3_clkdm",
- .main_clk = "timer15_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* timer16 */
-static struct omap_hwmod dra7xx_timer16_hwmod = {
- .name = "timer16",
- .class = &dra7xx_timer_hwmod_class,
- .clkdm_name = "l4per3_clkdm",
- .main_clk = "timer16_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* DES (the 'P' (public) device) */
-static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
- .rev_offs = 0x0030,
- .sysc_offs = 0x0034,
- .syss_offs = 0x0038,
- .sysc_flags = SYSS_HAS_RESET_STATUS,
-};
-
-static struct omap_hwmod_class dra7xx_des_hwmod_class = {
- .name = "des",
- .sysc = &dra7xx_des_sysc,
-};
-
-/* DES */
-static struct omap_hwmod dra7xx_des_hwmod = {
- .name = "des",
- .class = &dra7xx_des_hwmod_class,
- .clkdm_name = "l4sec_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* rng */
-static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
- .rev_offs = 0x1fe0,
- .sysc_offs = 0x1fe4,
- .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
- .idlemodes = SIDLE_FORCE | SIDLE_NO,
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
- .name = "rng",
- .sysc = &dra7xx_rng_sysc,
-};
-
-static struct omap_hwmod dra7xx_rng_hwmod = {
- .name = "rng",
- .class = &dra7xx_rng_hwmod_class,
- .flags = HWMOD_SWSUP_SIDLE,
- .clkdm_name = "l4sec_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'usb_otg_ss' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
- .name = "usb_otg_ss",
- .sysc = &dra7xx_usb_otg_ss_sysc,
-};
-
-/* usb_otg_ss1 */
-static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
- { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
-};
-
-static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
- .name = "usb_otg_ss1",
- .class = &dra7xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "dpll_core_h13x2_ck",
- .flags = HWMOD_CLKDM_NOAUTO,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
- .opt_clks = usb_otg_ss1_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
-};
-
-/* usb_otg_ss2 */
-static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
- { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
-};
-
-static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
- .name = "usb_otg_ss2",
- .class = &dra7xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "dpll_core_h13x2_ck",
- .flags = HWMOD_CLKDM_NOAUTO,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
- .opt_clks = usb_otg_ss2_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
-};
-
-/* usb_otg_ss3 */
-static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
- .name = "usb_otg_ss3",
- .class = &dra7xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "dpll_core_h13x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* usb_otg_ss4 */
-static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
- .name = "usb_otg_ss4",
- .class = &dra7xx_usb_otg_ss_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .main_clk = "dpll_core_h13x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
* 'vcp' class
*
*/
@@ -1815,43 +493,6 @@
},
};
-/*
- * 'wd_timer' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &dra7xx_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable,
- .reset = &omap2_wd_timer_reset,
-};
-
-/* wd_timer2 */
-static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
- .name = "wd_timer2",
- .class = &dra7xx_wd_timer_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .main_clk = "sys_32k_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
/*
@@ -1962,14 +603,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> counter_32k */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_counter_32k_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_wkup -> ctrl_module_wkup */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
.master = &dra7xx_l4_wkup_hwmod,
@@ -1978,110 +611,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> dcan1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_dcan1_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> dcan2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_dcan2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_dma_system_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> tpcc */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_tpcc_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_1 -> tptc0 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_tptc0_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_1 -> tptc1 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_tptc1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_1 -> dss */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_dss_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> dispc */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_dss_dispc_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> dispc */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_dss_hdmi_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> aes1 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_aes1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> aes2 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_aes2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> sha0 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_sha0_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> elm */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_elm_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> gpmc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
.master = &dra7xx_l3_main_1_hwmod,
@@ -2090,118 +619,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_per1 -> hdq1w */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_hdq1w_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> mailbox1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_mailbox1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox3_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox4_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox5 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox5_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox6 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox6_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox7 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox7_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox8 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox8_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox9 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox9_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox10 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox10_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox11 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox11_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox12 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox12_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> mailbox13 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_mailbox13_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_cfg -> mpu */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2210,22 +627,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> ocp2scp1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_ocp2scp1_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> ocp2scp3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_ocp2scp3_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> pciess1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
.master = &dra7xx_l3_main_1_hwmod,
@@ -2266,14 +667,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_per3 -> rtcss */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_rtcss_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l4_cfg -> sata */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2282,205 +675,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg -> smartreflex_core */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_smartreflex_core_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> smartreflex_mpu */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_smartreflex_mpu_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> spinlock */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_spinlock_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_timer1_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer3_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer4_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer5 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer5_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer6 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer6_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer7 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer7_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer8 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer8_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer9 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer9_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer10 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer10_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> timer11 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_timer11_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> timer12 */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_timer12_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer13 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer13_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer14 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer14_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer15 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer15_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> timer16 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_timer16_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> des */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_des_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> rng */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
- .master = &dra7xx_l4_per1_hwmod,
- .slave = &dra7xx_rng_hwmod,
- .user = OCP_USER_MPU,
-};
-
-/* l4_per3 -> usb_otg_ss1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_usb_otg_ss1_hwmod,
- .clk = "dpll_core_h13x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> usb_otg_ss2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_usb_otg_ss2_hwmod,
- .clk = "dpll_core_h13x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> usb_otg_ss3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_usb_otg_ss3_hwmod,
- .clk = "dpll_core_h13x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per3 -> usb_otg_ss4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
- .master = &dra7xx_l4_per3_hwmod,
- .slave = &dra7xx_usb_otg_ss4_hwmod,
- .clk = "dpll_core_h13x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
/* l3_main_1 -> vcp1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
.master = &dra7xx_l3_main_1_hwmod,
@@ -2513,38 +707,6 @@
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_wd_timer2_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> epwmss0 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_epwmss0_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l4_per2 -> epwmss1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_epwmss1_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l4_per2 -> epwmss2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_epwmss2_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__dmm,
&dra7xx_l3_main_2__l3_instr,
@@ -2559,106 +721,28 @@
&dra7xx_l3_main_1__l4_wkup,
&dra7xx_l4_per2__atl,
&dra7xx_l3_main_1__bb2d,
- &dra7xx_l4_wkup__counter_32k,
&dra7xx_l4_wkup__ctrl_module_wkup,
- &dra7xx_l4_wkup__dcan1,
- &dra7xx_l4_per2__dcan2,
- &dra7xx_l4_cfg__dma_system,
- &dra7xx_l3_main_1__tpcc,
- &dra7xx_l3_main_1__tptc0,
- &dra7xx_l3_main_1__tptc1,
- &dra7xx_l3_main_1__dss,
- &dra7xx_l3_main_1__dispc,
- &dra7xx_l3_main_1__hdmi,
- &dra7xx_l3_main_1__aes1,
- &dra7xx_l3_main_1__aes2,
- &dra7xx_l3_main_1__sha0,
- &dra7xx_l4_per1__elm,
&dra7xx_l3_main_1__gpmc,
- &dra7xx_l4_per1__hdq1w,
- &dra7xx_l4_cfg__mailbox1,
- &dra7xx_l4_per3__mailbox2,
- &dra7xx_l4_per3__mailbox3,
- &dra7xx_l4_per3__mailbox4,
- &dra7xx_l4_per3__mailbox5,
- &dra7xx_l4_per3__mailbox6,
- &dra7xx_l4_per3__mailbox7,
- &dra7xx_l4_per3__mailbox8,
- &dra7xx_l4_per3__mailbox9,
- &dra7xx_l4_per3__mailbox10,
- &dra7xx_l4_per3__mailbox11,
- &dra7xx_l4_per3__mailbox12,
- &dra7xx_l4_per3__mailbox13,
&dra7xx_l4_cfg__mpu,
- &dra7xx_l4_cfg__ocp2scp1,
- &dra7xx_l4_cfg__ocp2scp3,
&dra7xx_l3_main_1__pciess1,
&dra7xx_l4_cfg__pciess1,
&dra7xx_l3_main_1__pciess2,
&dra7xx_l4_cfg__pciess2,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
- &dra7xx_l4_cfg__smartreflex_core,
- &dra7xx_l4_cfg__smartreflex_mpu,
- &dra7xx_l4_cfg__spinlock,
- &dra7xx_l4_wkup__timer1,
- &dra7xx_l4_per1__timer2,
- &dra7xx_l4_per1__timer3,
- &dra7xx_l4_per1__timer4,
- &dra7xx_l4_per3__timer5,
- &dra7xx_l4_per3__timer6,
- &dra7xx_l4_per3__timer7,
- &dra7xx_l4_per3__timer8,
- &dra7xx_l4_per1__timer9,
- &dra7xx_l4_per1__timer10,
- &dra7xx_l4_per1__timer11,
- &dra7xx_l4_per3__timer13,
- &dra7xx_l4_per3__timer14,
- &dra7xx_l4_per3__timer15,
- &dra7xx_l4_per3__timer16,
- &dra7xx_l4_per1__des,
- &dra7xx_l4_per3__usb_otg_ss1,
- &dra7xx_l4_per3__usb_otg_ss2,
- &dra7xx_l4_per3__usb_otg_ss3,
&dra7xx_l3_main_1__vcp1,
&dra7xx_l4_per2__vcp1,
&dra7xx_l3_main_1__vcp2,
&dra7xx_l4_per2__vcp2,
- &dra7xx_l4_wkup__wd_timer2,
- &dra7xx_l4_per2__epwmss0,
- &dra7xx_l4_per2__epwmss1,
- &dra7xx_l4_per2__epwmss2,
- NULL,
-};
-
-/* GP-only hwmod links */
-static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
- &dra7xx_l4_wkup__timer12,
- &dra7xx_l4_per1__rng,
NULL,
};
/* SoC variant specific hwmod links */
-static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
- &dra7xx_l4_per3__usb_otg_ss4,
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
- &dra7xx_l4_per3__usb_otg_ss4,
- NULL,
-};
-
static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
NULL,
};
static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
- &dra7xx_l4_per3__rtcss,
NULL,
};
@@ -2670,25 +754,15 @@
ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
if (!ret && soc_is_dra74x()) {
- ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
- if (!ret)
- ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
+ ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
} else if (!ret && soc_is_dra72x()) {
ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
if (!ret && !of_machine_is_compatible("ti,dra718"))
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
} else if (!ret && soc_is_dra76x()) {
- ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
-
- if (!ret && soc_is_dra76x_acd()) {
- ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
- } else if (!ret && soc_is_dra76x_abz()) {
+ if (!ret && soc_is_dra76x_abz())
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
- }
}
- if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
- ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
-
return ret;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index 83230d9..450ab99 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -1,7 +1,7 @@
/*
* DM81xx hwmod data.
*
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
* Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
*
* This program is free software; you can redistribute it and/or
@@ -129,13 +129,6 @@
.flags = HWMOD_NO_IDLEST,
};
-static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
- .name = "l3_fast",
- .clkdm_name = "alwon_l3_fast_clkdm",
- .class = &l3_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
/*
* L4 standard peripherals, see TRM table 1-12 for devices using this.
* See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
@@ -697,76 +690,6 @@
.sysc = &dm816x_timer_sysc,
};
-static struct omap_hwmod dm814x_timer1_hwmod = {
- .name = "timer1",
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "timer1_fck",
- .class = &dm816x_timer_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
-static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
- .master = &dm81xx_l4_ls_hwmod,
- .slave = &dm814x_timer1_hwmod,
- .clk = "sysclk6_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod dm816x_timer1_hwmod = {
- .name = "timer1",
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "timer1_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .class = &dm816x_timer_hwmod_class,
-};
-
-static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
- .master = &dm81xx_l4_ls_hwmod,
- .slave = &dm816x_timer1_hwmod,
- .clk = "sysclk6_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod dm814x_timer2_hwmod = {
- .name = "timer2",
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "timer2_fck",
- .class = &dm816x_timer_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
-};
-
-static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
- .master = &dm81xx_l4_ls_hwmod,
- .slave = &dm814x_timer2_hwmod,
- .clk = "sysclk6_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod dm816x_timer2_hwmod = {
- .name = "timer2",
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "timer2_fck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .class = &dm816x_timer_hwmod_class,
-};
-
-static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
- .master = &dm81xx_l4_ls_hwmod,
- .slave = &dm816x_timer2_hwmod,
- .clk = "sysclk6_ck",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod dm816x_timer3_hwmod = {
.name = "timer3",
.clkdm_name = "alwon_l3s_clkdm",
@@ -867,62 +790,6 @@
.user = OCP_USER_MPU,
};
-/* CPSW on dm814x */
-static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x8,
- .syss_offs = 0x4,
- .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSS_HAS_RESET_STATUS,
- .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
- MSTANDBY_NO,
- .sysc_fields = &omap_hwmod_sysc_type3,
-};
-
-static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
- .name = "cpgmac0",
- .sysc = &dm814x_cpgmac_sysc,
-};
-
-static struct omap_hwmod dm814x_cpgmac0_hwmod = {
- .name = "cpgmac0",
- .class = &dm814x_cpgmac0_hwmod_class,
- .clkdm_name = "alwon_ethernet_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "cpsw_125mhz_gclk",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
- .name = "davinci_mdio",
-};
-
-static struct omap_hwmod dm814x_mdio_hwmod = {
- .name = "davinci_mdio",
- .class = &dm814x_mdio_hwmod_class,
- .clkdm_name = "alwon_ethernet_clkdm",
- .main_clk = "cpsw_125mhz_gclk",
-};
-
-static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
- .master = &dm81xx_l4_hs_hwmod,
- .slave = &dm814x_cpgmac0_hwmod,
- .clk = "cpsw_125mhz_gclk",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
- .master = &dm814x_cpgmac0_hwmod,
- .slave = &dm814x_mdio_hwmod,
- .user = OCP_USER_MPU,
- .flags = HWMOD_NO_IDLEST,
-};
-
/* EMAC Ethernet */
static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
.rev_offs = 0x0,
@@ -1321,154 +1188,6 @@
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
- .name = "tpcc",
-};
-
-static struct omap_hwmod dm81xx_tpcc_hwmod = {
- .name = "tpcc",
- .class = &dm81xx_tpcc_hwmod_class,
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "sysclk4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
- .master = &dm81xx_alwon_l3_fast_hwmod,
- .slave = &dm81xx_tpcc_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
- .name = "tptc0",
-};
-
-static struct omap_hwmod dm81xx_tptc0_hwmod = {
- .name = "tptc0",
- .class = &dm81xx_tptc0_hwmod_class,
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "sysclk4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
- .master = &dm81xx_alwon_l3_fast_hwmod,
- .slave = &dm81xx_tptc0_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
- .master = &dm81xx_tptc0_hwmod,
- .slave = &dm81xx_alwon_l3_fast_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
- .name = "tptc1",
-};
-
-static struct omap_hwmod dm81xx_tptc1_hwmod = {
- .name = "tptc1",
- .class = &dm81xx_tptc1_hwmod_class,
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "sysclk4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
- .master = &dm81xx_alwon_l3_fast_hwmod,
- .slave = &dm81xx_tptc1_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
- .master = &dm81xx_tptc1_hwmod,
- .slave = &dm81xx_alwon_l3_fast_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
- .name = "tptc2",
-};
-
-static struct omap_hwmod dm81xx_tptc2_hwmod = {
- .name = "tptc2",
- .class = &dm81xx_tptc2_hwmod_class,
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "sysclk4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
- .master = &dm81xx_alwon_l3_fast_hwmod,
- .slave = &dm81xx_tptc2_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
- .master = &dm81xx_tptc2_hwmod,
- .slave = &dm81xx_alwon_l3_fast_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
- .name = "tptc3",
-};
-
-static struct omap_hwmod dm81xx_tptc3_hwmod = {
- .name = "tptc3",
- .class = &dm81xx_tptc3_hwmod_class,
- .clkdm_name = "alwon_l3s_clkdm",
- .main_clk = "sysclk4_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
- .master = &dm81xx_alwon_l3_fast_hwmod,
- .slave = &dm81xx_tptc3_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
- .master = &dm81xx_tptc3_hwmod,
- .slave = &dm81xx_alwon_l3_fast_hwmod,
- .clk = "sysclk4_ck",
- .user = OCP_USER_MPU,
-};
-
/*
* REVISIT: Test and enable the following once clocks work:
* dm81xx_l4_ls__mailbox
@@ -1499,19 +1218,6 @@
&dm814x_l4_ls__mmc1,
&dm814x_l4_ls__mmc2,
&ti81xx_l4_ls__rtc,
- &dm81xx_alwon_l3_fast__tpcc,
- &dm81xx_alwon_l3_fast__tptc0,
- &dm81xx_alwon_l3_fast__tptc1,
- &dm81xx_alwon_l3_fast__tptc2,
- &dm81xx_alwon_l3_fast__tptc3,
- &dm81xx_tptc0__alwon_l3_fast,
- &dm81xx_tptc1__alwon_l3_fast,
- &dm81xx_tptc2__alwon_l3_fast,
- &dm81xx_tptc3__alwon_l3_fast,
- &dm814x_l4_ls__timer1,
- &dm814x_l4_ls__timer2,
- &dm814x_l4_hs__cpgmac0,
- &dm814x_cpgmac0__mdio,
&dm81xx_alwon_l3_slow__gpmc,
&dm814x_default_l3_slow__usbss,
&dm814x_alwon_l3_med__mmc3,
@@ -1540,8 +1246,6 @@
&dm81xx_l4_ls__elm,
&ti81xx_l4_ls__rtc,
&dm816x_l4_ls__mmc1,
- &dm816x_l4_ls__timer1,
- &dm816x_l4_ls__timer2,
&dm816x_l4_ls__timer3,
&dm816x_l4_ls__timer4,
&dm816x_l4_ls__timer5,
@@ -1554,15 +1258,6 @@
&dm81xx_emac0__mdio,
&dm816x_l4_hs__emac1,
&dm81xx_l4_hs__sata,
- &dm81xx_alwon_l3_fast__tpcc,
- &dm81xx_alwon_l3_fast__tptc0,
- &dm81xx_alwon_l3_fast__tptc1,
- &dm81xx_alwon_l3_fast__tptc2,
- &dm81xx_alwon_l3_fast__tptc3,
- &dm81xx_tptc0__alwon_l3_fast,
- &dm81xx_tptc1__alwon_l3_fast,
- &dm81xx_tptc2__alwon_l3_fast,
- &dm81xx_tptc3__alwon_l3_fast,
&dm81xx_alwon_l3_slow__gpmc,
&dm816x_default_l3_slow__usbss,
NULL,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index ca56563..0045e66 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -21,8 +21,6 @@
extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
extern struct omap_hwmod omap2xxx_mpu_hwmod;
extern struct omap_hwmod omap2xxx_iva_hwmod;
-extern struct omap_hwmod omap2xxx_timer1_hwmod;
-extern struct omap_hwmod omap2xxx_timer2_hwmod;
extern struct omap_hwmod omap2xxx_timer3_hwmod;
extern struct omap_hwmod omap2xxx_timer4_hwmod;
extern struct omap_hwmod omap2xxx_timer5_hwmod;
@@ -47,7 +45,6 @@
extern struct omap_hwmod omap2xxx_gpio4_hwmod;
extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
-extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
extern struct omap_hwmod omap2xxx_gpmc_hwmod;
extern struct omap_hwmod omap2xxx_rng_hwmod;
extern struct omap_hwmod omap2xxx_sham_hwmod;
@@ -98,7 +95,6 @@
extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
-extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mcspi_class;
diff --git a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c
index d5ddba0..143623b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_reset.c
+++ b/arch/arm/mach-omap2/omap_hwmod_reset.c
@@ -26,8 +26,6 @@
#include <linux/kernel.h>
#include <linux/errno.h>
-#include <sound/aess.h>
-
#include "omap_hwmod.h"
#include "common.h"
@@ -41,28 +39,6 @@
#define OMAP_RTC_MAX_READY_TIME 50
/**
- * omap_hwmod_aess_preprogram - enable AESS internal autogating
- * @oh: struct omap_hwmod *
- *
- * The AESS will not IdleAck to the PRCM until its internal autogating
- * is enabled. Since internal autogating is disabled by default after
- * AESS reset, we must enable autogating after the hwmod code resets
- * the AESS. Returns 0.
- */
-int omap_hwmod_aess_preprogram(struct omap_hwmod *oh)
-{
- void __iomem *va;
-
- va = omap_hwmod_get_mpu_rt_va(oh);
- if (!va)
- return -EINVAL;
-
- aess_enable_autogating(va);
-
- return 0;
-}
-
-/**
* omap_rtc_wait_not_busy - Wait for the RTC BUSY flag
* @oh: struct omap_hwmod *
*
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
index 336fdfc..533dd64 100644
--- a/arch/arm/mach-omap2/omap_opp_data.h
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -1,7 +1,7 @@
/*
* OMAP SoC specific OPP Data helpers
*
- * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Copyright (C) 2010 Nokia Corporation.
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index d2925e8..6f6a6a6 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -3,7 +3,7 @@
* This file configures the internal USB PHY in OMAP4430. Used
* with TWL6030 transceiver and MUSB on OMAP4430.
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com
* Author: Hema HK <hemahk@ti.com>
*/
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 6787f1e..a642d3b 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -36,11 +36,6 @@
#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
#define OMAP4_VDD_CORE_SR_CMD_REG 0x62
-#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
-#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
-#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
-#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
-
static bool is_offset_valid;
static u8 smps_offset;
@@ -219,7 +214,8 @@
{
struct voltagedomain *voltdm;
- if (!cpu_is_omap44xx())
+ if (!cpu_is_omap44xx() ||
+ of_find_compatible_node(NULL, NULL, "motorola,cpcap"))
return -ENODEV;
voltdm = voltdm_lookup("mpu");
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
index c2d459f..b610c5f 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -1,7 +1,7 @@
/*
* OMAP3 OPP table definitions.
*
- * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Copyright (C) 2010-2011 Nokia Corporation.
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index adea43e..d937c5e 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -1,7 +1,7 @@
/*
* OMAP4 OPP table definitions.
*
- * Copyright (C) 2010-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010-2012 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Thara Gopinath
@@ -32,20 +32,22 @@
#define OMAP4430_VDD_MPU_OPP50_UV 1025000
#define OMAP4430_VDD_MPU_OPP100_UV 1200000
-#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000
-#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
+#define OMAP4430_VDD_MPU_OPPTURBO_UV 1325000
+#define OMAP4430_VDD_MPU_OPPNITRO_UV 1388000
+#define OMAP4430_VDD_MPU_OPPNITROSB_UV 1398000
struct omap_volt_data omap443x_vdd_mpu_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
+ VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITROSB_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB, 0xfa, 0x27),
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
-#define OMAP4430_VDD_IVA_OPP50_UV 1013000
-#define OMAP4430_VDD_IVA_OPP100_UV 1188000
-#define OMAP4430_VDD_IVA_OPPTURBO_UV 1300000
+#define OMAP4430_VDD_IVA_OPP50_UV 950000
+#define OMAP4430_VDD_IVA_OPP100_UV 1114000
+#define OMAP4430_VDD_IVA_OPPTURBO_UV 1291000
struct omap_volt_data omap443x_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
@@ -54,8 +56,8 @@
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
-#define OMAP4430_VDD_CORE_OPP50_UV 1025000
-#define OMAP4430_VDD_CORE_OPP100_UV 1200000
+#define OMAP4430_VDD_CORE_OPP50_UV 962000
+#define OMAP4430_VDD_CORE_OPP100_UV 1127000
struct omap_volt_data omap443x_vdd_core_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index ca07e31..2a4fe3e 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -10,7 +10,6 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
-#include <linux/ti_wilink_st.h>
#include <linux/wl12xx.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
@@ -24,6 +23,7 @@
#include <linux/platform_data/ti-sysc.h>
#include <linux/platform_data/wkup_m3.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <linux/platform_data/ti-prm.h>
#include "clockdomain.h"
#include "common.h"
@@ -32,7 +32,6 @@
#include "omap_device.h"
#include "omap-secure.h"
#include "soc.h"
-#include "hsmmc.h"
static struct omap_hsmmc_platform_data __maybe_unused mmc_pdata[2];
@@ -156,53 +155,6 @@
omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
}
-static struct ti_st_plat_data wilink_pdata = {
- .nshutdown_gpio = 137,
- .dev_name = "/dev/ttyO1",
- .flow_cntrl = 1,
- .baud_rate = 300000,
-};
-
-static struct platform_device wl18xx_device = {
- .name = "kim",
- .id = -1,
- .dev = {
- .platform_data = &wilink_pdata,
- }
-};
-
-static struct ti_st_plat_data wilink7_pdata = {
- .nshutdown_gpio = 162,
- .dev_name = "/dev/ttyO1",
- .flow_cntrl = 1,
- .baud_rate = 3000000,
-};
-
-static struct platform_device wl128x_device = {
- .name = "kim",
- .id = -1,
- .dev = {
- .platform_data = &wilink7_pdata,
- }
-};
-
-static struct platform_device btwilink_device = {
- .name = "btwilink",
- .id = -1,
-};
-
-static void __init omap3_igep0020_rev_f_legacy_init(void)
-{
- platform_device_register(&wl18xx_device);
- platform_device_register(&btwilink_device);
-}
-
-static void __init omap3_igep0030_rev_g_legacy_init(void)
-{
- platform_device_register(&wl18xx_device);
- platform_device_register(&btwilink_device);
-}
-
static void __init omap3_evm_legacy_init(void)
{
hsmmc2_internal_input_clk();
@@ -285,7 +237,7 @@
mmc_pdata[0].name = "external";
mmc_pdata[1].name = "internal";
- if (omap_type() == OMAP2_DEVICE_TYPE_SEC) {
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
if (IS_ENABLED(CONFIG_ARM_ERRATA_430973)) {
pr_info("RX-51: Enabling ARM errata 430973 workaround\n");
/* set IBE to 1 */
@@ -305,8 +257,6 @@
static void __init omap3_logicpd_torpedo_init(void)
{
omap3_gpio126_127_129();
- platform_device_register(&wl128x_device);
- platform_device_register(&btwilink_device);
}
/* omap3pandora legacy devices */
@@ -447,10 +397,16 @@
return omap_hwmod_shutdown(cookie->data);
}
+static bool ti_sysc_soc_type_gp(void)
+{
+ return omap_type() == OMAP2_DEVICE_TYPE_GP;
+}
+
static struct of_dev_auxdata omap_auxdata_lookup[];
static struct ti_sysc_platform_data ti_sysc_pdata = {
.auxdata = omap_auxdata_lookup,
+ .soc_type_gp = ti_sysc_soc_type_gp,
.init_clockdomain = ti_sysc_clkdm_init,
.clkdm_deny_idle = ti_sysc_clkdm_deny_idle,
.clkdm_allow_idle = ti_sysc_clkdm_allow_idle,
@@ -468,6 +424,12 @@
pcs_pdata.rearm = rearm;
}
+static struct ti_prm_platform_data ti_prm_pdata = {
+ .clkdm_deny_idle = clkdm_deny_idle,
+ .clkdm_allow_idle = clkdm_allow_idle,
+ .clkdm_lookup = clkdm_lookup,
+};
+
/*
* GPIOs for TWL are initialized by the I2C bus and need custom
* handing until DSS has device tree bindings.
@@ -572,6 +534,8 @@
/* Common auxdata */
OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata),
OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),
+ OF_DEV_AUXDATA("ti,omap-prm-inst", 0, NULL, &ti_prm_pdata),
+ OF_DEV_AUXDATA("ti,omap-sdma", 0, NULL, &dma_plat_info),
{ /* sentinel */ },
};
@@ -587,8 +551,6 @@
{ "nokia,omap3-n900", nokia_n900_legacy_init, },
{ "nokia,omap3-n9", hsmmc2_internal_input_clk, },
{ "nokia,omap3-n950", hsmmc2_internal_input_clk, },
- { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, },
- { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, },
{ "logicpd,dm3730-torpedo-devkit", omap3_logicpd_torpedo_init, },
{ "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
{ "ti,am3517-evm", am3517_evm_legacy_init, },
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index fceb1e5..919d35d 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -34,8 +34,6 @@
#include "prm2xxx_3xxx.h"
#include "pm.h"
-u32 enable_off_mode;
-
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 7ac9af5..da829a9 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -28,6 +28,8 @@
#include "clockdomain.h"
#include "pm.h"
+u32 enable_off_mode;
+
#ifdef CONFIG_SUSPEND
/*
* omap_pm_suspend: points to a function that does the SoC-specific
@@ -148,6 +150,7 @@
/* Init the voltage layer */
omap3_twl_init();
omap4_twl_init();
+ omap4_cpcap_init();
omap_voltage_late_init();
/* Smartreflex device init */
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 8a55b69..80e84ae 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -49,11 +49,7 @@
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
-#ifdef CONFIG_PM_DEBUG
extern u32 enable_off_mode;
-#else
-#define enable_off_mode 0
-#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
@@ -107,6 +103,11 @@
#define IS_PM44XX_ERRATUM(id) 0
#endif
+#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
+#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
+#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
+#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
+
#ifdef CONFIG_POWER_AVS_OMAP
extern int omap_devinit_smartreflex(void);
extern void omap_enable_smartreflex_on_init(void);
@@ -134,6 +135,15 @@
}
#endif
+#if IS_ENABLED(CONFIG_MFD_CPCAP)
+extern int omap4_cpcap_init(void);
+#else
+static inline int omap4_cpcap_init(void)
+{
+ return -EINVAL;
+}
+#endif
+
#ifdef CONFIG_PM
extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 1581b6a..6953c47 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -83,8 +83,6 @@
l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
- cpu_cluster_pm_enter();
-
/* One last check for pending IRQs to avoid extra latency due
* to sleeping unnecessarily. */
if (omap_irq_pending())
@@ -96,8 +94,6 @@
OMAP_SDRC_REGADDR(SDRC_POWER));
no_sleep:
- cpu_cluster_pm_exit();
-
clk_enable(osc_ck);
/* clear CORE wake-up events */
@@ -162,25 +158,27 @@
return 0;
if (__clk_is_enabled(osc_ck))
return 0;
- if (omap_dma_running())
- return 0;
return 1;
}
static void omap2_pm_idle(void)
{
- if (!omap2_can_sleep()) {
- if (omap_irq_pending())
- return;
- omap2_enter_mpu_retention();
- return;
- }
+ int error;
if (omap_irq_pending())
return;
+ error = cpu_cluster_pm_enter();
+ if (error || !omap2_can_sleep()) {
+ omap2_enter_mpu_retention();
+ goto out_cpu_cluster_pm;
+ }
+
omap2_enter_full_retention();
+
+out_cpu_cluster_pm:
+ cpu_cluster_pm_exit();
}
static void __init prcm_setup_regs(void)
diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c
index f11442e..bf0d25f 100644
--- a/arch/arm/mach-omap2/pm33xx-core.c
+++ b/arch/arm/mach-omap2/pm33xx-core.c
@@ -2,15 +2,19 @@
/*
* AM33XX Arch Power Management Routines
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach
*/
+#include <linux/cpuidle.h>
+#include <linux/platform_data/pm33xx.h>
+#include <linux/suspend.h>
+#include <asm/cpuidle.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>
#include <linux/errno.h>
-#include <linux/platform_data/pm33xx.h>
#include <linux/clk.h>
+#include <linux/cpu.h>
#include <linux/platform_data/gpio-omap.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/wkup_m3_ipc.h>
@@ -22,17 +26,24 @@
#include "control.h"
#include "clockdomain.h"
#include "iomap.h"
-#include "omap_hwmod.h"
#include "pm.h"
#include "powerdomain.h"
#include "prm33xx.h"
#include "soc.h"
#include "sram.h"
+#include "omap-secure.h"
static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
static struct clockdomain *gfx_l4ls_clkdm;
static void __iomem *scu_base;
-static struct omap_hwmod *rtc_oh;
+
+static int (*idle_fn)(u32 wfi_flags);
+
+struct amx3_idle_state {
+ int wfi_flags;
+};
+
+static struct amx3_idle_state *idle_states;
static int am43xx_map_scu(void)
{
@@ -67,7 +78,7 @@
return 0;
}
-static int amx3_common_init(void)
+static int amx3_common_init(int (*idle)(u32 wfi_flags))
{
gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
per_pwrdm = pwrdm_lookup("per_pwrdm");
@@ -87,10 +98,12 @@
else
omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
+ idle_fn = idle;
+
return 0;
}
-static int am33xx_suspend_init(void)
+static int am33xx_suspend_init(int (*idle)(u32 wfi_flags))
{
int ret;
@@ -101,12 +114,12 @@
return -ENODEV;
}
- ret = amx3_common_init();
+ ret = amx3_common_init(idle);
return ret;
}
-static int am43xx_suspend_init(void)
+static int am43xx_suspend_init(int (*idle)(u32 wfi_flags))
{
int ret = 0;
@@ -116,11 +129,17 @@
return ret;
}
- ret = amx3_common_init();
+ ret = amx3_common_init(idle);
return ret;
}
+static int amx3_suspend_deinit(void)
+{
+ idle_fn = NULL;
+ return 0;
+}
+
static void amx3_pre_suspend_common(void)
{
omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF);
@@ -166,6 +185,16 @@
{
int ret = 0;
+ /* Suspend secure side on HS devices */
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
+ if (optee_available)
+ omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0);
+ else
+ omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND,
+ FLAG_START_CRITICAL,
+ 0, 0, 0, 0, 0);
+ }
+
amx3_pre_suspend_common();
scu_power_mode(scu_base, SCU_PM_POWEROFF);
ret = cpu_suspend(args, fn);
@@ -174,9 +203,59 @@
if (!am43xx_check_off_mode_enable())
amx3_post_suspend_common();
+ /*
+ * Resume secure side on HS devices.
+ *
+ * Note that even on systems with OP-TEE available this resume call is
+ * issued to the ROM. This is because upon waking from suspend the ROM
+ * is restored as the secure monitor. On systems with OP-TEE ROM will
+ * restore OP-TEE during this call.
+ */
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+ omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME,
+ FLAG_START_CRITICAL,
+ 0, 0, 0, 0, 0);
+
return ret;
}
+static int am33xx_cpu_suspend(int (*fn)(unsigned long), unsigned long args)
+{
+ int ret = 0;
+
+ if (omap_irq_pending() || need_resched())
+ return ret;
+
+ ret = cpu_suspend(args, fn);
+
+ return ret;
+}
+
+static int am43xx_cpu_suspend(int (*fn)(unsigned long), unsigned long args)
+{
+ int ret = 0;
+
+ if (!scu_base)
+ return 0;
+
+ scu_power_mode(scu_base, SCU_PM_DORMANT);
+ ret = cpu_suspend(args, fn);
+ scu_power_mode(scu_base, SCU_PM_NORMAL);
+
+ return ret;
+}
+
+static void amx3_begin_suspend(void)
+{
+ cpu_idle_poll_ctrl(true);
+}
+
+static void amx3_finish_suspend(void)
+{
+ cpu_idle_poll_ctrl(false);
+}
+
+
static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void)
{
if (soc_is_am33xx())
@@ -187,13 +266,6 @@
return NULL;
}
-void __iomem *am43xx_get_rtc_base_addr(void)
-{
- rtc_oh = omap_hwmod_lookup("rtc");
-
- return omap_hwmod_get_mpu_rt_va(rtc_oh);
-}
-
static void am43xx_save_context(void)
{
}
@@ -217,38 +289,30 @@
writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14));
}
-static void am43xx_prepare_rtc_suspend(void)
-{
- omap_hwmod_enable(rtc_oh);
-}
-
-static void am43xx_prepare_rtc_resume(void)
-{
- omap_hwmod_idle(rtc_oh);
-}
-
static struct am33xx_pm_platform_data am33xx_ops = {
.init = am33xx_suspend_init,
+ .deinit = amx3_suspend_deinit,
.soc_suspend = am33xx_suspend,
+ .cpu_suspend = am33xx_cpu_suspend,
+ .begin_suspend = amx3_begin_suspend,
+ .finish_suspend = amx3_finish_suspend,
.get_sram_addrs = amx3_get_sram_addrs,
.save_context = am33xx_save_context,
.restore_context = am33xx_restore_context,
- .prepare_rtc_suspend = am43xx_prepare_rtc_suspend,
- .prepare_rtc_resume = am43xx_prepare_rtc_resume,
.check_off_mode_enable = am33xx_check_off_mode_enable,
- .get_rtc_base_addr = am43xx_get_rtc_base_addr,
};
static struct am33xx_pm_platform_data am43xx_ops = {
.init = am43xx_suspend_init,
+ .deinit = amx3_suspend_deinit,
.soc_suspend = am43xx_suspend,
+ .cpu_suspend = am43xx_cpu_suspend,
+ .begin_suspend = amx3_begin_suspend,
+ .finish_suspend = amx3_finish_suspend,
.get_sram_addrs = amx3_get_sram_addrs,
.save_context = am43xx_save_context,
.restore_context = am43xx_restore_context,
- .prepare_rtc_suspend = am43xx_prepare_rtc_suspend,
- .prepare_rtc_resume = am43xx_prepare_rtc_resume,
.check_off_mode_enable = am43xx_check_off_mode_enable,
- .get_rtc_base_addr = am43xx_get_rtc_base_addr,
};
static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void)
@@ -261,6 +325,44 @@
return NULL;
}
+#ifdef CONFIG_SUSPEND
+/*
+ * Block system suspend initially. Later on pm33xx sets up it's own
+ * platform_suspend_ops after probe. That depends also on loaded
+ * wkup_m3_ipc and booted am335x-pm-firmware.elf.
+ */
+static int amx3_suspend_block(suspend_state_t state)
+{
+ pr_warn("PM not initialized for pm33xx, wkup_m3_ipc, or am335x-pm-firmware.elf\n");
+
+ return -EINVAL;
+}
+
+static int amx3_pm_valid(suspend_state_t state)
+{
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+static const struct platform_suspend_ops amx3_blocked_pm_ops = {
+ .begin = amx3_suspend_block,
+ .valid = amx3_pm_valid,
+};
+
+static void __init amx3_block_suspend(void)
+{
+ suspend_set_ops(&amx3_blocked_pm_ops);
+}
+#else
+static inline void amx3_block_suspend(void)
+{
+}
+#endif /* CONFIG_SUSPEND */
+
int __init amx3_common_pm_init(void)
{
struct am33xx_pm_platform_data *pdata;
@@ -274,6 +376,68 @@
devinfo.size_data = sizeof(*pdata);
devinfo.id = -1;
platform_device_register_full(&devinfo);
+ amx3_block_suspend();
return 0;
}
+
+static int __init amx3_idle_init(struct device_node *cpu_node, int cpu)
+{
+ struct device_node *state_node;
+ struct amx3_idle_state states[CPUIDLE_STATE_MAX];
+ int i;
+ int state_count = 1;
+
+ for (i = 0; ; i++) {
+ state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+ if (!state_node)
+ break;
+
+ if (!of_device_is_available(state_node))
+ continue;
+
+ if (i == CPUIDLE_STATE_MAX) {
+ pr_warn("%s: cpuidle states reached max possible\n",
+ __func__);
+ break;
+ }
+
+ states[state_count].wfi_flags = 0;
+
+ if (of_property_read_bool(state_node, "ti,idle-wkup-m3"))
+ states[state_count].wfi_flags |= WFI_FLAG_WAKE_M3 |
+ WFI_FLAG_FLUSH_CACHE;
+
+ state_count++;
+ }
+
+ idle_states = kcalloc(state_count, sizeof(*idle_states), GFP_KERNEL);
+ if (!idle_states)
+ return -ENOMEM;
+
+ for (i = 1; i < state_count; i++)
+ idle_states[i].wfi_flags = states[i].wfi_flags;
+
+ return 0;
+}
+
+static int amx3_idle_enter(unsigned long index)
+{
+ struct amx3_idle_state *idle_state = &idle_states[index];
+
+ if (!idle_state)
+ return -EINVAL;
+
+ if (idle_fn)
+ idle_fn(idle_state->wfi_flags);
+
+ return 0;
+}
+
+static struct cpuidle_ops amx3_cpuidle_ops __initdata = {
+ .init = amx3_idle_init,
+ .suspend = amx3_idle_enter,
+};
+
+CPUIDLE_METHOD_OF_DECLARE(pm33xx_idle, "ti,am3352", &amx3_cpuidle_ops);
+CPUIDLE_METHOD_OF_DECLARE(pm43xx_idle, "ti,am4372", &amx3_cpuidle_ops);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fa66534..71c1d18 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -25,7 +25,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/slab.h>
-#include <linux/omap-dma.h>
+#include <linux/of.h>
#include <linux/omap-gpmc.h>
#include <trace/events/power.h>
@@ -85,7 +85,6 @@
omap3_gpmc_save_context();
/* Save the system control module context, padconf already save above*/
omap3_control_save_context();
- omap_dma_global_context_save();
}
static void omap3_core_restore_context(void)
@@ -96,7 +95,6 @@
omap3_gpmc_restore_context();
/* Restore the interrupt controller context */
omap_intc_restore_context();
- omap_dma_global_context_restore();
}
/*
@@ -301,11 +299,7 @@
if (omap_irq_pending())
return;
- trace_cpu_idle_rcuidle(1, smp_processor_id());
-
omap_sram_idle();
-
- trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
}
#ifdef CONFIG_SUSPEND
@@ -417,7 +411,12 @@
if (!pwrst)
return -ENOMEM;
pwrst->pwrdm = pwrdm;
- pwrst->next_state = PWRDM_POWER_RET;
+
+ if (enable_off_mode)
+ pwrst->next_state = PWRDM_POWER_OFF;
+ else
+ pwrst->next_state = PWRDM_POWER_RET;
+
list_add(&pwrst->node, &pwrst_list);
if (pwrdm_has_hdwr_sar(pwrdm))
@@ -451,6 +450,22 @@
}
}
+static void __init omap3_pm_check_pmic(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle");
+ if (!np)
+ np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off");
+
+ if (np) {
+ of_node_put(np);
+ enable_off_mode = 1;
+ } else {
+ enable_off_mode = 0;
+ }
+}
+
int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
@@ -484,6 +499,8 @@
goto err2;
}
+ omap3_pm_check_pmic();
+
ret = pwrdm_for_each(pwrdms_setup, NULL);
if (ret) {
pr_err("Failed to setup powerdomains\n");
@@ -551,9 +568,7 @@
local_irq_disable();
- omap_dma_global_context_save();
omap3_save_secure_ram_context();
- omap_dma_global_context_restore();
local_irq_enable();
}
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 485550a..5a7a949 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -128,18 +128,9 @@
return 0;
}
- /*
- * Bootloader or kexec boot may have LOGICRETSTATE cleared
- * for some domains. This is the case when kexec booting from
- * Android kernels that support off mode for example.
- * Make sure it's set at least for core and per, otherwise
- * we currently will see lost GPIO interrupts for wlcore and
- * smsc911x at least if per hits retention during idle.
- */
if (!strncmp(pwrdm->name, "core", 4) ||
- !strncmp(pwrdm->name, "l4per", 5) ||
- !strncmp(pwrdm->name, "wkup", 4))
- pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_RET);
+ !strncmp(pwrdm->name, "l4per", 5))
+ pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_OFF);
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
if (!pwrst)
diff --git a/arch/arm/mach-omap2/pmic-cpcap.c b/arch/arm/mach-omap2/pmic-cpcap.c
new file mode 100644
index 0000000..668dc84
--- /dev/null
+++ b/arch/arm/mach-omap2/pmic-cpcap.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * pmic-cpcap.c - CPCAP-specific functions for the OPP code
+ *
+ * Adapted from Motorola Mapphone Android Linux kernel
+ * Copyright (C) 2011 Motorola, Inc.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "soc.h"
+#include "pm.h"
+#include "voltage.h"
+
+#include <linux/init.h>
+#include "vc.h"
+
+/**
+ * omap_cpcap_vsel_to_vdc - convert CPCAP VSEL value to microvolts DC
+ * @vsel: CPCAP VSEL value to convert
+ *
+ * Returns the microvolts DC that the CPCAP PMIC should generate when
+ * programmed with @vsel.
+ */
+static unsigned long omap_cpcap_vsel_to_uv(unsigned char vsel)
+{
+ if (vsel > 0x44)
+ vsel = 0x44;
+ return (((vsel * 125) + 6000)) * 100;
+}
+
+/**
+ * omap_cpcap_uv_to_vsel - convert microvolts DC to CPCAP VSEL value
+ * @uv: microvolts DC to convert
+ *
+ * Returns the VSEL value necessary for the CPCAP PMIC to
+ * generate an output voltage equal to or greater than @uv microvolts DC.
+ */
+static unsigned char omap_cpcap_uv_to_vsel(unsigned long uv)
+{
+ if (uv < 600000)
+ uv = 600000;
+ else if (uv > 1450000)
+ uv = 1450000;
+ return DIV_ROUND_UP(uv - 600000, 12500);
+}
+
+static struct omap_voltdm_pmic omap_cpcap_core = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ .vddmin = 900000,
+ .vddmax = 1350000,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = 0x02,
+ .volt_reg_addr = 0x00,
+ .cmd_reg_addr = 0x01,
+ .i2c_high_speed = false,
+ .vsel_to_uv = omap_cpcap_vsel_to_uv,
+ .uv_to_vsel = omap_cpcap_uv_to_vsel,
+};
+
+static struct omap_voltdm_pmic omap_cpcap_iva = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ .vddmin = 900000,
+ .vddmax = 1375000,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = 0x44,
+ .volt_reg_addr = 0x0,
+ .cmd_reg_addr = 0x01,
+ .i2c_high_speed = false,
+ .vsel_to_uv = omap_cpcap_vsel_to_uv,
+ .uv_to_vsel = omap_cpcap_uv_to_vsel,
+};
+
+/**
+ * omap_max8952_vsel_to_vdc - convert MAX8952 VSEL value to microvolts DC
+ * @vsel: MAX8952 VSEL value to convert
+ *
+ * Returns the microvolts DC that the MAX8952 Regulator should generate when
+ * programmed with @vsel.
+ */
+static unsigned long omap_max8952_vsel_to_uv(unsigned char vsel)
+{
+ if (vsel > 0x3F)
+ vsel = 0x3F;
+ return (((vsel * 100) + 7700)) * 100;
+}
+
+/**
+ * omap_max8952_uv_to_vsel - convert microvolts DC to MAX8952 VSEL value
+ * @uv: microvolts DC to convert
+ *
+ * Returns the VSEL value necessary for the MAX8952 Regulator to
+ * generate an output voltage equal to or greater than @uv microvolts DC.
+ */
+static unsigned char omap_max8952_uv_to_vsel(unsigned long uv)
+{
+ if (uv < 770000)
+ uv = 770000;
+ else if (uv > 1400000)
+ uv = 1400000;
+ return DIV_ROUND_UP(uv - 770000, 10000);
+}
+
+static struct omap_voltdm_pmic omap443x_max8952_mpu = {
+ .slew_rate = 16000,
+ .step_size = 10000,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ .vddmin = 900000,
+ .vddmax = 1400000,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = 0x60,
+ .volt_reg_addr = 0x03,
+ .cmd_reg_addr = 0x03,
+ .i2c_high_speed = false,
+ .vsel_to_uv = omap_max8952_vsel_to_uv,
+ .uv_to_vsel = omap_max8952_uv_to_vsel,
+};
+
+/**
+ * omap_fan5355_vsel_to_vdc - convert FAN535503 VSEL value to microvolts DC
+ * @vsel: FAN535503 VSEL value to convert
+ *
+ * Returns the microvolts DC that the FAN535503 Regulator should generate when
+ * programmed with @vsel.
+ */
+static unsigned long omap_fan535503_vsel_to_uv(unsigned char vsel)
+{
+ /* Extract bits[5:0] */
+ vsel &= 0x3F;
+
+ return (((vsel * 125) + 7500)) * 100;
+}
+
+/**
+ * omap_fan535508_vsel_to_vdc - convert FAN535508 VSEL value to microvolts DC
+ * @vsel: FAN535508 VSEL value to convert
+ *
+ * Returns the microvolts DC that the FAN535508 Regulator should generate when
+ * programmed with @vsel.
+ */
+static unsigned long omap_fan535508_vsel_to_uv(unsigned char vsel)
+{
+ /* Extract bits[5:0] */
+ vsel &= 0x3F;
+
+ if (vsel > 0x37)
+ vsel = 0x37;
+ return (((vsel * 125) + 7500)) * 100;
+}
+
+
+/**
+ * omap_fan535503_uv_to_vsel - convert microvolts DC to FAN535503 VSEL value
+ * @uv: microvolts DC to convert
+ *
+ * Returns the VSEL value necessary for the MAX8952 Regulator to
+ * generate an output voltage equal to or greater than @uv microvolts DC.
+ */
+static unsigned char omap_fan535503_uv_to_vsel(unsigned long uv)
+{
+ unsigned char vsel;
+ if (uv < 750000)
+ uv = 750000;
+ else if (uv > 1537500)
+ uv = 1537500;
+
+ vsel = DIV_ROUND_UP(uv - 750000, 12500);
+ return vsel | 0xC0;
+}
+
+/**
+ * omap_fan535508_uv_to_vsel - convert microvolts DC to FAN535508 VSEL value
+ * @uv: microvolts DC to convert
+ *
+ * Returns the VSEL value necessary for the MAX8952 Regulator to
+ * generate an output voltage equal to or greater than @uv microvolts DC.
+ */
+static unsigned char omap_fan535508_uv_to_vsel(unsigned long uv)
+{
+ unsigned char vsel;
+ if (uv < 750000)
+ uv = 750000;
+ else if (uv > 1437500)
+ uv = 1437500;
+
+ vsel = DIV_ROUND_UP(uv - 750000, 12500);
+ return vsel | 0xC0;
+}
+
+/* fan5335-core */
+static struct omap_voltdm_pmic omap4_fan_core = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ .vddmin = 850000,
+ .vddmax = 1375000,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = 0x4A,
+ .i2c_high_speed = false,
+ .volt_reg_addr = 0x01,
+ .cmd_reg_addr = 0x01,
+ .vsel_to_uv = omap_fan535508_vsel_to_uv,
+ .uv_to_vsel = omap_fan535508_uv_to_vsel,
+};
+
+/* fan5335 iva */
+static struct omap_voltdm_pmic omap4_fan_iva = {
+ .slew_rate = 4000,
+ .step_size = 12500,
+ .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
+ .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+ .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+ .vddmin = 850000,
+ .vddmax = 1375000,
+ .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+ .i2c_slave_addr = 0x48,
+ .volt_reg_addr = 0x01,
+ .cmd_reg_addr = 0x01,
+ .i2c_high_speed = false,
+ .vsel_to_uv = omap_fan535503_vsel_to_uv,
+ .uv_to_vsel = omap_fan535503_uv_to_vsel,
+};
+
+int __init omap4_cpcap_init(void)
+{
+ struct voltagedomain *voltdm;
+
+ if (!of_find_compatible_node(NULL, NULL, "motorola,cpcap"))
+ return -ENODEV;
+
+ voltdm = voltdm_lookup("mpu");
+ omap_voltage_register_pmic(voltdm, &omap443x_max8952_mpu);
+
+ if (of_machine_is_compatible("motorola,droid-bionic")) {
+ voltdm = voltdm_lookup("core");
+ omap_voltage_register_pmic(voltdm, &omap_cpcap_core);
+
+ voltdm = voltdm_lookup("iva");
+ omap_voltage_register_pmic(voltdm, &omap_cpcap_iva);
+ } else {
+ voltdm = voltdm_lookup("core");
+ omap_voltage_register_pmic(voltdm, &omap4_fan_core);
+
+ voltdm = voltdm_lookup("iva");
+ omap_voltage_register_pmic(voltdm, &omap4_fan_iva);
+ }
+
+ return 0;
+}
+
+static int __init cpcap_late_init(void)
+{
+ omap4_vc_set_pmic_signaling(PWRDM_POWER_RET);
+
+ return 0;
+}
+omap_late_initcall(cpcap_late_init);
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
index 869adb8..626055e 100644
--- a/arch/arm/mach-omap2/powerdomains33xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -1,7 +1,7 @@
/*
* AM33XX Power domain data
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h
index e2ad14e..899da0a 100644
--- a/arch/arm/mach-omap2/prcm43xx.h
+++ b/arch/arm/mach-omap2/prcm43xx.h
@@ -1,7 +1,7 @@
/*
* AM43x PRCM defines
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -68,6 +68,7 @@
#define AM43XX_CM_PER_ICSS_CDOFFS 0x0300
#define AM43XX_CM_PER_L4LS_CDOFFS 0x0400
#define AM43XX_CM_PER_EMIF_CDOFFS 0x0700
+#define AM43XX_CM_PER_LCDC_CDOFFS 0x0800
#define AM43XX_CM_PER_DSS_CDOFFS 0x0a00
#define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00
#define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00
diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h
index 6ef3882..bdbfa07 100644
--- a/arch/arm/mach-omap2/prcm_mpu54xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54xx PRCM MPU instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
diff --git a/arch/arm/mach-omap2/prcm_mpu7xx.h b/arch/arm/mach-omap2/prcm_mpu7xx.h
index 33d0013..2e30324 100644
--- a/arch/arm/mach-omap2/prcm_mpu7xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu7xx.h
@@ -2,7 +2,7 @@
/*
* DRA7xx PRCM MPU instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
index 84feece..7dfdff0 100644
--- a/arch/arm/mach-omap2/prm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -1,7 +1,7 @@
/*
* AM33XX PRM_XXX register bits
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index d514166..9144cc0 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -1,7 +1,7 @@
/*
* AM33XX PRM functions
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 66302c6..d0b7404 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -1,7 +1,7 @@
/*
* AM33XX PRM instance offset macros
*
- * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 1d9346f..25093c1 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -745,7 +745,7 @@
static int omap44xx_prm_late_init(void);
-void prm_save_context(void)
+static void prm_save_context(void)
{
omap_prm_context.irq_enable =
omap4_prm_read_inst_reg(AM43XX_PRM_OCP_SOCKET_INST,
@@ -756,7 +756,7 @@
omap4_prcm_irq_setup.pm_ctrl);
}
-void prm_restore_context(void)
+static void prm_restore_context(void)
{
omap4_prm_write_inst_reg(omap_prm_context.irq_enable,
OMAP4430_PRM_OCP_SOCKET_INST,
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index ee0f1cc..7329d6f 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54xx PRM instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index cf99307..e5aee04 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -2,7 +2,7 @@
/*
* DRA7xx PRM instance offset macros
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h
index 810d2b1..cb6f3e6 100644
--- a/arch/arm/mach-omap2/scrm54xx.h
+++ b/arch/arm/mach-omap2/scrm54xx.h
@@ -2,7 +2,7 @@
/*
* OMAP54XX SCRM registers and bitfields
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*
* Benoit Cousson (b-cousson@ti.com)
*
diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
index dc22124..ac3d0b3 100644
--- a/arch/arm/mach-omap2/sleep33xx.S
+++ b/arch/arm/mach-omap2/sleep33xx.S
@@ -2,7 +2,7 @@
/*
* Low level suspend code for AM33XX SoCs
*
- * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012-2018 Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach, Vaibhav Bedia
*/
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index ac1324c..c4e97d3 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -72,7 +72,7 @@
stmfd sp!, {lr} @ save registers on stack
/* Setup so that we will disable and enable l2 */
mov r1, #0x1
- adrl r3, l2dis_3630_offset @ may be too distant for plain adr
+ adr r3, l2dis_3630_offset
ldr r2, [r3] @ value for offset
str r1, [r2, r3] @ write to l2dis_3630
ldmfd sp!, {pc} @ restore regs and return
diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S
index 90d2907..832c913 100644
--- a/arch/arm/mach-omap2/sleep43xx.S
+++ b/arch/arm/mach-omap2/sleep43xx.S
@@ -2,7 +2,7 @@
/*
* Low level suspend code for AM43XX SoCs
*
- * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2018 Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach, Vaibhav Bedia
*/
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 62df666..6059256 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -88,34 +88,26 @@
extern struct omap_sr_data omap_sr_pdata[];
-static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
+static int __init sr_init_by_name(const char *name, const char *voltdm)
{
struct omap_sr_data *sr_data = NULL;
struct omap_volt_data *volt_data;
- struct omap_smartreflex_dev_attr *sr_dev_attr;
static int i;
- if (!strncmp(oh->name, "smartreflex_mpu_iva", 20) ||
- !strncmp(oh->name, "smartreflex_mpu", 16))
+ if (!strncmp(name, "smartreflex_mpu_iva", 20) ||
+ !strncmp(name, "smartreflex_mpu", 16))
sr_data = &omap_sr_pdata[OMAP_SR_MPU];
- else if (!strncmp(oh->name, "smartreflex_core", 17))
+ else if (!strncmp(name, "smartreflex_core", 17))
sr_data = &omap_sr_pdata[OMAP_SR_CORE];
- else if (!strncmp(oh->name, "smartreflex_iva", 16))
+ else if (!strncmp(name, "smartreflex_iva", 16))
sr_data = &omap_sr_pdata[OMAP_SR_IVA];
if (!sr_data) {
- pr_err("%s: Unknown instance %s\n", __func__, oh->name);
+ pr_err("%s: Unknown instance %s\n", __func__, name);
return -EINVAL;
}
- sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
- if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
- pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
- __func__, oh->name);
- goto exit;
- }
-
- sr_data->name = oh->name;
+ sr_data->name = name;
if (cpu_is_omap343x())
sr_data->ip_type = 1;
else
@@ -136,10 +128,10 @@
}
}
- sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
+ sr_data->voltdm = voltdm_lookup(voltdm);
if (!sr_data->voltdm) {
pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
- __func__, sr_dev_attr->sensor_voltdm_name);
+ __func__, voltdm);
goto exit;
}
@@ -160,6 +152,20 @@
return 0;
}
+static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
+{
+ struct omap_smartreflex_dev_attr *sr_dev_attr;
+
+ sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
+ if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
+ pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
+ __func__, oh->name);
+ return 0;
+ }
+
+ return sr_init_by_name(oh->name, sr_dev_attr->sensor_voltdm_name);
+}
+
/*
* API to be called from board files to enable smartreflex
* autocompensation at init.
@@ -169,7 +175,42 @@
sr_enable_on_init = true;
}
+static const char * const omap4_sr_instances[] = {
+ "mpu",
+ "iva",
+ "core",
+};
+
+static const char * const dra7_sr_instances[] = {
+ "mpu",
+ "core",
+};
+
int __init omap_devinit_smartreflex(void)
{
+ const char * const *sr_inst = NULL;
+ int i, nr_sr = 0;
+
+ if (soc_is_omap44xx()) {
+ sr_inst = omap4_sr_instances;
+ nr_sr = ARRAY_SIZE(omap4_sr_instances);
+
+ } else if (soc_is_dra7xx()) {
+ sr_inst = dra7_sr_instances;
+ nr_sr = ARRAY_SIZE(dra7_sr_instances);
+ }
+
+ if (nr_sr) {
+ const char *name, *voltdm;
+
+ for (i = 0; i < nr_sr; i++) {
+ name = kasprintf(GFP_KERNEL, "smartreflex_%s", sr_inst[i]);
+ voltdm = sr_inst[i];
+ sr_init_by_name(name, voltdm);
+ }
+
+ return 0;
+ }
+
return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL);
}
diff --git a/arch/arm/mach-omap2/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h
index a1e6caf..192b0e7 100644
--- a/arch/arm/mach-omap2/ti81xx.h
+++ b/arch/arm/mach-omap2/ti81xx.h
@@ -1,7 +1,7 @@
/*
* This file contains the address data for various TI81XX modules.
*
- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 1defb83..620ba69 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -26,35 +26,12 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/slab.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/dmtimer-omap.h>
-#include <linux/sched_clock.h>
-#include <linux/cpu.h>
-
-#include <asm/mach/time.h>
-
-#include "omap_hwmod.h"
-#include "omap_device.h"
-#include <plat/counter-32k.h>
-#include <clocksource/timer-ti-dm.h>
#include "soc.h"
#include "common.h"
#include "control.h"
-#include "powerdomain.h"
#include "omap-secure.h"
#define REALTIME_COUNTER_BASE 0x48243200
@@ -62,612 +39,12 @@
#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
-/* Clockevent code */
-
-/* Clockevent hwmod for am335x and am437x suspend */
-static struct omap_hwmod *clockevent_gpt_hwmod;
-
-/* Clockesource hwmod for am437x suspend */
-static struct omap_hwmod *clocksource_gpt_hwmod;
-
-struct dmtimer_clockevent {
- struct clock_event_device dev;
- struct omap_dm_timer timer;
-};
-
-static struct dmtimer_clockevent clockevent;
-
-static struct omap_dm_timer *to_dmtimer(struct clock_event_device *clockevent)
-{
- struct dmtimer_clockevent *clkevt =
- container_of(clockevent, struct dmtimer_clockevent, dev);
- struct omap_dm_timer *timer = &clkevt->timer;
-
- return timer;
-}
-
-#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
static unsigned long arch_timer_freq;
void set_cntfreq(void)
{
omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
}
-#endif
-
-static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
-{
- struct dmtimer_clockevent *clkevt = dev_id;
- struct clock_event_device *evt = &clkevt->dev;
- struct omap_dm_timer *timer = &clkevt->timer;
-
- __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW);
- evt->event_handler(evt);
- return IRQ_HANDLED;
-}
-
-static int omap2_gp_timer_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- struct omap_dm_timer *timer = to_dmtimer(evt);
-
- __omap_dm_timer_load_start(timer, OMAP_TIMER_CTRL_ST,
- 0xffffffff - cycles, OMAP_TIMER_POSTED);
-
- return 0;
-}
-
-static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
-{
- struct omap_dm_timer *timer = to_dmtimer(evt);
-
- __omap_dm_timer_stop(timer, OMAP_TIMER_POSTED, timer->rate);
-
- return 0;
-}
-
-static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
-{
- struct omap_dm_timer *timer = to_dmtimer(evt);
- u32 period;
-
- __omap_dm_timer_stop(timer, OMAP_TIMER_POSTED, timer->rate);
-
- period = timer->rate / HZ;
- period -= 1;
- /* Looks like we need to first set the load value separately */
- __omap_dm_timer_write(timer, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
- OMAP_TIMER_POSTED);
- __omap_dm_timer_load_start(timer,
- OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
- 0xffffffff - period, OMAP_TIMER_POSTED);
- return 0;
-}
-
-static void omap_clkevt_idle(struct clock_event_device *unused)
-{
- if (!clockevent_gpt_hwmod)
- return;
-
- omap_hwmod_idle(clockevent_gpt_hwmod);
-}
-
-static void omap_clkevt_unidle(struct clock_event_device *evt)
-{
- struct omap_dm_timer *timer = to_dmtimer(evt);
-
- if (!clockevent_gpt_hwmod)
- return;
-
- omap_hwmod_enable(clockevent_gpt_hwmod);
- __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
-}
-
-static const struct of_device_id omap_timer_match[] __initconst = {
- { .compatible = "ti,omap2420-timer", },
- { .compatible = "ti,omap3430-timer", },
- { .compatible = "ti,omap4430-timer", },
- { .compatible = "ti,omap5430-timer", },
- { .compatible = "ti,dm814-timer", },
- { .compatible = "ti,dm816-timer", },
- { .compatible = "ti,am335x-timer", },
- { .compatible = "ti,am335x-timer-1ms", },
- { }
-};
-
-static int omap_timer_add_disabled_property(struct device_node *np)
-{
- struct property *prop;
-
- prop = kzalloc(sizeof(*prop), GFP_KERNEL);
- if (!prop)
- return -ENOMEM;
-
- prop->name = "status";
- prop->value = "disabled";
- prop->length = strlen(prop->value);
-
- return of_add_property(np, prop);
-}
-
-static int omap_timer_update_dt(struct device_node *np)
-{
- int error = 0;
-
- if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
- error = omap_timer_add_disabled_property(np);
- if (error)
- return error;
- }
-
- /* No parent interconnect target module configured? */
- if (of_get_property(np, "ti,hwmods", NULL))
- return error;
-
- /* Tag parent interconnect target module disabled */
- error = omap_timer_add_disabled_property(np->parent);
- if (error)
- return error;
-
- return 0;
-}
-
-/**
- * omap_get_timer_dt - get a timer using device-tree
- * @match - device-tree match structure for matching a device type
- * @property - optional timer property to match
- *
- * Helper function to get a timer during early boot using device-tree for use
- * as kernel system timer. Optionally, the property argument can be used to
- * select a timer with a specific property. Once a timer is found then mark
- * the timer node in device-tree as disabled, to prevent the kernel from
- * registering this timer as a platform device and so no one else can use it.
- */
-static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
- const char *property)
-{
- struct device_node *np;
- int error;
-
- for_each_matching_node(np, match) {
- if (!of_device_is_available(np))
- continue;
-
- if (property && !of_get_property(np, property, NULL))
- continue;
-
- if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
- of_get_property(np, "ti,timer-dsp", NULL) ||
- of_get_property(np, "ti,timer-pwm", NULL) ||
- of_get_property(np, "ti,timer-secure", NULL)))
- continue;
-
- error = omap_timer_update_dt(np);
- WARN(error, "%s: Could not update dt: %i\n", __func__, error);
-
- return np;
- }
-
- return NULL;
-}
-
-/**
- * omap_dmtimer_init - initialisation function when device tree is used
- *
- * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
- * cannot be used by the kernel as they are reserved. Therefore, to prevent the
- * kernel registering these devices remove them dynamically from the device
- * tree on boot.
- */
-static void __init omap_dmtimer_init(void)
-{
- struct device_node *np;
-
- if (!cpu_is_omap34xx() && !soc_is_dra7xx())
- return;
-
- /* If we are a secure device, remove any secure timer nodes */
- if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
- np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
- of_node_put(np);
- }
-}
-
-/**
- * omap_dm_timer_get_errata - get errata flags for a timer
- *
- * Get the timer errata flags that are specific to the OMAP device being used.
- */
-static u32 __init omap_dm_timer_get_errata(void)
-{
- if (cpu_is_omap24xx())
- return 0;
-
- return OMAP_TIMER_ERRATA_I103_I767;
-}
-
-static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
- const char *fck_source,
- const char *property,
- const char **timer_name,
- int posted)
-{
- const char *oh_name = NULL;
- struct device_node *np;
- struct omap_hwmod *oh;
- struct clk *src;
- int r = 0;
-
- np = omap_get_timer_dt(omap_timer_match, property);
- if (!np)
- return -ENODEV;
-
- of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
- if (!oh_name) {
- of_property_read_string_index(np->parent, "ti,hwmods", 0,
- &oh_name);
- if (!oh_name)
- return -ENODEV;
- }
-
- timer->irq = irq_of_parse_and_map(np, 0);
- if (!timer->irq)
- return -ENXIO;
-
- timer->io_base = of_iomap(np, 0);
-
- timer->fclk = of_clk_get_by_name(np, "fck");
-
- of_node_put(np);
-
- oh = omap_hwmod_lookup(oh_name);
- if (!oh)
- return -ENODEV;
-
- *timer_name = oh->name;
-
- if (!timer->io_base)
- return -ENXIO;
-
- omap_hwmod_setup_one(oh_name);
-
- /* After the dmtimer is using hwmod these clocks won't be needed */
- if (IS_ERR_OR_NULL(timer->fclk))
- timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
- if (IS_ERR(timer->fclk))
- return PTR_ERR(timer->fclk);
-
- src = clk_get(NULL, fck_source);
- if (IS_ERR(src))
- return PTR_ERR(src);
-
- WARN(clk_set_parent(timer->fclk, src) < 0,
- "Cannot set timer parent clock, no PLL clock driver?");
-
- clk_put(src);
-
- omap_hwmod_enable(oh);
- __omap_dm_timer_init_regs(timer);
-
- if (posted)
- __omap_dm_timer_enable_posted(timer);
-
- /* Check that the intended posted configuration matches the actual */
- if (posted != timer->posted)
- return -EINVAL;
-
- timer->rate = clk_get_rate(timer->fclk);
- timer->reserved = 1;
-
- return r;
-}
-
-#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
-void tick_broadcast(const struct cpumask *mask)
-{
-}
-#endif
-
-static void __init dmtimer_clkevt_init_common(struct dmtimer_clockevent *clkevt,
- int gptimer_id,
- const char *fck_source,
- unsigned int features,
- const struct cpumask *cpumask,
- const char *property,
- int rating, const char *name)
-{
- struct omap_dm_timer *timer = &clkevt->timer;
- int res;
-
- timer->id = gptimer_id;
- timer->errata = omap_dm_timer_get_errata();
- clkevt->dev.features = features;
- clkevt->dev.rating = rating;
- clkevt->dev.set_next_event = omap2_gp_timer_set_next_event;
- clkevt->dev.set_state_shutdown = omap2_gp_timer_shutdown;
- clkevt->dev.set_state_periodic = omap2_gp_timer_set_periodic;
- clkevt->dev.set_state_oneshot = omap2_gp_timer_shutdown;
- clkevt->dev.tick_resume = omap2_gp_timer_shutdown;
-
- /*
- * For clock-event timers we never read the timer counter and
- * so we are not impacted by errata i103 and i767. Therefore,
- * we can safely ignore this errata for clock-event timers.
- */
- __omap_dm_timer_override_errata(timer, OMAP_TIMER_ERRATA_I103_I767);
-
- res = omap_dm_timer_init_one(timer, fck_source, property,
- &clkevt->dev.name, OMAP_TIMER_POSTED);
- BUG_ON(res);
-
- clkevt->dev.cpumask = cpumask;
- clkevt->dev.irq = omap_dm_timer_get_irq(timer);
-
- if (request_irq(clkevt->dev.irq, omap2_gp_timer_interrupt,
- IRQF_TIMER | IRQF_IRQPOLL, name, clkevt))
- pr_err("Failed to request irq %d (gp_timer)\n", clkevt->dev.irq);
-
- __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW);
-
- if (soc_is_am33xx() || soc_is_am43xx()) {
- clkevt->dev.suspend = omap_clkevt_idle;
- clkevt->dev.resume = omap_clkevt_unidle;
-
- clockevent_gpt_hwmod =
- omap_hwmod_lookup(clkevt->dev.name);
- }
-
- pr_info("OMAP clockevent source: %s at %lu Hz\n", clkevt->dev.name,
- timer->rate);
-}
-
-static DEFINE_PER_CPU(struct dmtimer_clockevent, dmtimer_percpu_timer);
-
-static int omap_gptimer_starting_cpu(unsigned int cpu)
-{
- struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
- struct clock_event_device *dev = &clkevt->dev;
- struct omap_dm_timer *timer = &clkevt->timer;
-
- clockevents_config_and_register(dev, timer->rate, 3, ULONG_MAX);
- irq_force_affinity(dev->irq, cpumask_of(cpu));
-
- return 0;
-}
-
-static int __init dmtimer_percpu_quirk_init(void)
-{
- struct dmtimer_clockevent *clkevt;
- struct clock_event_device *dev;
- struct device_node *arm_timer;
- struct omap_dm_timer *timer;
- int cpu = 0;
-
- arm_timer = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
- if (of_device_is_available(arm_timer)) {
- pr_warn_once("ARM architected timer wrap issue i940 detected\n");
- return 0;
- }
-
- for_each_possible_cpu(cpu) {
- clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
- dev = &clkevt->dev;
- timer = &clkevt->timer;
-
- dmtimer_clkevt_init_common(clkevt, 0, "timer_sys_ck",
- CLOCK_EVT_FEAT_ONESHOT,
- cpumask_of(cpu),
- "assigned-clock-parents",
- 500, "percpu timer");
- }
-
- cpuhp_setup_state(CPUHP_AP_OMAP_DM_TIMER_STARTING,
- "clockevents/omap/gptimer:starting",
- omap_gptimer_starting_cpu, NULL);
-
- return 0;
-}
-
-/* Clocksource code */
-static struct omap_dm_timer clksrc;
-static bool use_gptimer_clksrc __initdata;
-
-/*
- * clocksource
- */
-static u64 clocksource_read_cycles(struct clocksource *cs)
-{
- return (u64)__omap_dm_timer_read_counter(&clksrc,
- OMAP_TIMER_NONPOSTED);
-}
-
-static struct clocksource clocksource_gpt = {
- .rating = 300,
- .read = clocksource_read_cycles,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static u64 notrace dmtimer_read_sched_clock(void)
-{
- if (clksrc.reserved)
- return __omap_dm_timer_read_counter(&clksrc,
- OMAP_TIMER_NONPOSTED);
-
- return 0;
-}
-
-static const struct of_device_id omap_counter_match[] __initconst = {
- { .compatible = "ti,omap-counter32k", },
- { }
-};
-
-/* Setup free-running counter for clocksource */
-static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
-{
- int ret;
- struct device_node *np = NULL;
- struct omap_hwmod *oh;
- const char *oh_name = "counter_32k";
-
- /*
- * See if the 32kHz counter is supported.
- */
- np = omap_get_timer_dt(omap_counter_match, NULL);
- if (!np)
- return -ENODEV;
-
- of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name);
- if (!oh_name) {
- of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
- if (!oh_name)
- return -ENODEV;
- }
-
- /*
- * First check hwmod data is available for sync32k counter
- */
- oh = omap_hwmod_lookup(oh_name);
- if (!oh || oh->slaves_cnt == 0)
- return -ENODEV;
-
- omap_hwmod_setup_one(oh_name);
-
- ret = omap_hwmod_enable(oh);
- if (ret) {
- pr_warn("%s: failed to enable counter_32k module (%d)\n",
- __func__, ret);
- return ret;
- }
-
- return ret;
-}
-
-static unsigned int omap2_gptimer_clksrc_load;
-
-static void omap2_gptimer_clksrc_suspend(struct clocksource *unused)
-{
- omap2_gptimer_clksrc_load =
- __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED);
-
- omap_hwmod_idle(clocksource_gpt_hwmod);
-}
-
-static void omap2_gptimer_clksrc_resume(struct clocksource *unused)
-{
- omap_hwmod_enable(clocksource_gpt_hwmod);
-
- __omap_dm_timer_load_start(&clksrc,
- OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
- omap2_gptimer_clksrc_load,
- OMAP_TIMER_NONPOSTED);
-}
-
-static void __init omap2_gptimer_clocksource_init(int gptimer_id,
- const char *fck_source,
- const char *property)
-{
- int res;
-
- clksrc.id = gptimer_id;
- clksrc.errata = omap_dm_timer_get_errata();
-
- res = omap_dm_timer_init_one(&clksrc, fck_source, property,
- &clocksource_gpt.name,
- OMAP_TIMER_NONPOSTED);
-
- if (soc_is_am43xx()) {
- clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend;
- clocksource_gpt.resume = omap2_gptimer_clksrc_resume;
-
- clocksource_gpt_hwmod =
- omap_hwmod_lookup(clocksource_gpt.name);
- }
-
- BUG_ON(res);
-
- __omap_dm_timer_load_start(&clksrc,
- OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
- OMAP_TIMER_NONPOSTED);
- sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
-
- if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
- pr_err("Could not register clocksource %s\n",
- clocksource_gpt.name);
- else
- pr_info("OMAP clocksource: %s at %lu Hz\n",
- clocksource_gpt.name, clksrc.rate);
-}
-
-static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
- const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
- const char *clksrc_prop, bool gptimer)
-{
- omap_clk_init();
- omap_dmtimer_init();
- dmtimer_clkevt_init_common(&clockevent, clkev_nr, clkev_src,
- CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- cpu_possible_mask, clkev_prop, 300, "clockevent");
- clockevents_config_and_register(&clockevent.dev, clockevent.timer.rate,
- 3, /* Timer internal resynch latency */
- 0xffffffff);
-
- if (soc_is_dra7xx())
- dmtimer_percpu_quirk_init();
-
- /* Enable the use of clocksource="gp_timer" kernel parameter */
- if (use_gptimer_clksrc || gptimer)
- omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
- clksrc_prop);
- else
- omap2_sync32k_clocksource_init();
-}
-
-void __init omap_init_time(void)
-{
- __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
- 2, "timer_sys_ck", NULL, false);
-
- timer_probe();
-}
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
-void __init omap3_secure_sync32k_timer_init(void)
-{
- __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
- 2, "timer_sys_ck", NULL, false);
-
- timer_probe();
-}
-#endif /* CONFIG_ARCH_OMAP3 */
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
- defined(CONFIG_SOC_AM43XX) || defined(CONFIG_SOC_DRA7XX)
-void __init omap3_gptimer_timer_init(void)
-{
- __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
- 1, "timer_sys_ck", "ti,timer-alwon", true);
- if (of_have_populated_dt())
- timer_probe();
-}
-#endif
-
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
- defined(CONFIG_SOC_DRA7XX)
-static void __init omap4_sync32k_timer_init(void)
-{
- __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
- 2, "sys_clkin_ck", NULL, false);
-}
-
-void __init omap4_local_timer_init(void)
-{
- omap4_sync32k_timer_init();
- timer_probe();
-}
-#endif
-
-#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
/*
* The realtime counter also called master counter, is a free-running
@@ -680,7 +57,6 @@
*/
static void __init realtime_counter_init(void)
{
-#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
void __iomem *base;
static struct clk *sys_clk;
unsigned long rate;
@@ -779,39 +155,12 @@
set_cntfreq();
iounmap(base);
-#endif
}
void __init omap5_realtime_timer_init(void)
{
- omap4_sync32k_timer_init();
+ omap_clk_init();
realtime_counter_init();
timer_probe();
}
-#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
-
-/**
- * omap2_override_clocksource - clocksource override with user configuration
- *
- * Allows user to override default clocksource, using kernel parameter
- * clocksource="gp_timer" (For all OMAP2PLUS architectures)
- *
- * Note that, here we are using same standard kernel parameter "clocksource=",
- * and not introducing any OMAP specific interface.
- */
-static int __init omap2_override_clocksource(char *str)
-{
- if (!str)
- return 0;
- /*
- * For OMAP architecture, we only have two options
- * - sync_32k (default)
- * - gp_timer (sys_clk based)
- */
- if (!strcmp(str, "gp_timer"))
- use_gptimer_clksrc = true;
-
- return 0;
-}
-early_param("clocksource", omap2_override_clocksource);
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index d76b1e5..86f1ac4 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -26,6 +26,31 @@
#include "scrm44xx.h"
#include "control.h"
+#define OMAP4430_VDD_IVA_I2C_DISABLE BIT(14)
+#define OMAP4430_VDD_MPU_I2C_DISABLE BIT(13)
+#define OMAP4430_VDD_CORE_I2C_DISABLE BIT(12)
+#define OMAP4430_VDD_IVA_PRESENCE BIT(9)
+#define OMAP4430_VDD_MPU_PRESENCE BIT(8)
+#define OMAP4430_AUTO_CTRL_VDD_IVA(x) ((x) << 4)
+#define OMAP4430_AUTO_CTRL_VDD_MPU(x) ((x) << 2)
+#define OMAP4430_AUTO_CTRL_VDD_CORE(x) ((x) << 0)
+#define OMAP4430_AUTO_CTRL_VDD_RET 2
+
+#define OMAP4430_VDD_I2C_DISABLE_MASK \
+ (OMAP4430_VDD_IVA_I2C_DISABLE | \
+ OMAP4430_VDD_MPU_I2C_DISABLE | \
+ OMAP4430_VDD_CORE_I2C_DISABLE)
+
+#define OMAP4_VDD_DEFAULT_VAL \
+ (OMAP4430_VDD_I2C_DISABLE_MASK | \
+ OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \
+ OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \
+ OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \
+ OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET))
+
+#define OMAP4_VDD_RET_VAL \
+ (OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK)
+
/**
* struct omap_vc_channel_cfg - describe the cfg_channel bitfield
* @sa: bit for slave address
@@ -280,6 +305,26 @@
}
}
+void omap4_vc_set_pmic_signaling(int core_next_state)
+{
+ struct voltagedomain *vd = vc.vd;
+ u32 val;
+
+ if (!vd)
+ return;
+
+ switch (core_next_state) {
+ case PWRDM_POWER_RET:
+ val = OMAP4_VDD_RET_VAL;
+ break;
+ default:
+ val = OMAP4_VDD_DEFAULT_VAL;
+ break;
+ }
+
+ vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET);
+}
+
/*
* Configure signal polarity for sys_clkreq and sys_off_mode pins
* as the default values are wrong and can cause the system to hang
@@ -542,9 +587,19 @@
writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
}
+static void __init omap4_vc_init_pmic_signaling(struct voltagedomain *voltdm)
+{
+ if (vc.vd)
+ return;
+
+ vc.vd = voltdm;
+ voltdm->write(OMAP4_VDD_DEFAULT_VAL, OMAP4_PRM_VOLTCTRL_OFFSET);
+}
+
/* OMAP4 specific voltage init functions */
static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
{
+ omap4_vc_init_pmic_signaling(voltdm);
omap4_set_timings(voltdm, true);
omap4_set_timings(voltdm, false);
}
@@ -615,7 +670,7 @@
const struct i2c_init_data *i2c_data;
if (!voltdm->pmic->i2c_high_speed) {
- pr_warn("%s: only high speed supported!\n", __func__);
+ pr_info("%s: using bootloader low-speed timings\n", __func__);
return;
}
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
index 5bf0886..9e861db 100644
--- a/arch/arm/mach-omap2/vc.h
+++ b/arch/arm/mach-omap2/vc.h
@@ -117,7 +117,7 @@
extern struct omap_vc_param omap4_core_vc_data;
void omap3_vc_set_pmic_signaling(int core_next_state);
-
+void omap4_vc_set_pmic_signaling(int core_next_state);
void omap_vc_init_channel(struct voltagedomain *voltdm);
int omap_vc_pre_scale(struct voltagedomain *voltdm,
diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c
index aac274d..e60d76d 100644
--- a/arch/arm/mach-omap2/voltagedomains54xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c
@@ -4,7 +4,7 @@
*
* Based on voltagedomains44xx_data.c
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
*/
#include <linux/kernel.h>
#include <linux/err.h>