Update Linux to v5.4.2
Change-Id: Idf6911045d9d382da2cfe01b1edff026404ac8fd
diff --git a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
index 6c4d4b6..580aa26 100644
--- a/drivers/gpu/drm/ati_pcigart.c
+++ b/drivers/gpu/drm/ati_pcigart.c
@@ -32,9 +32,11 @@
*/
#include <linux/export.h>
-#include <drm/drmP.h>
#include <drm/ati_pcigart.h>
+#include <drm/drm_device.h>
+#include <drm/drm_pci.h>
+#include <drm/drm_print.h>
# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
@@ -103,7 +105,7 @@
unsigned long pages;
u32 *pci_gart = NULL, page_base, gart_idx;
dma_addr_t bus_address = 0;
- int i, j, ret = 0;
+ int i, j, ret = -ENOMEM;
int max_ati_pages, max_real_pages;
if (!entry) {
@@ -117,7 +119,7 @@
if (pci_set_dma_mask(dev->pdev, gart_info->table_mask)) {
DRM_ERROR("fail to set dma mask to 0x%Lx\n",
(unsigned long long)gart_info->table_mask);
- ret = 1;
+ ret = -EFAULT;
goto done;
}
@@ -160,11 +162,13 @@
drm_ati_pcigart_cleanup(dev, gart_info);
address = NULL;
bus_address = 0;
+ ret = -ENOMEM;
goto done;
}
page_base = (u32) entry->busaddr[i];
for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
+ u32 offset;
u32 val;
switch(gart_info->gart_reg_if) {
@@ -180,15 +184,17 @@
break;
}
if (gart_info->gart_table_location ==
- DRM_ATI_GART_MAIN)
+ DRM_ATI_GART_MAIN) {
pci_gart[gart_idx] = cpu_to_le32(val);
- else
- DRM_WRITE32(map, gart_idx * sizeof(u32), val);
+ } else {
+ offset = gart_idx * sizeof(u32);
+ writel(val, (void __iomem *)map->handle + offset);
+ }
gart_idx++;
page_base += ATI_PCIGART_PAGE_SIZE;
}
}
- ret = 1;
+ ret = 0;
#if defined(__i386__) || defined(__x86_64__)
wbinvd();