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review.trustedfirmware.org / hafnium / prebuilts / cdfccccb1ea3e050b07dc59f87e214ee979da2ae / . / linux-x64 / clang / include / llvm / Support / X86DisassemblerDecoderCommon.h
blob: 185b357efef5f7a74909f64c5199ecf546650f24 [file] [log] [blame]
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]1//===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler.
11// It contains common definitions used by both the disassembler and the table
12// generator.
13// Documentation for the disassembler can be found in X86Disassembler.h.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODERCOMMON_H
18#define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODERCOMMON_H
19
20#include "llvm/Support/DataTypes.h"
21
22namespace llvm {
23namespace X86Disassembler {
24
25#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
26#define CONTEXTS_SYM x86DisassemblerContexts
27#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
28#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
29#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
30#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
31#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
32#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
33#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
34#define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes
35
36#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
37#define CONTEXTS_STR "x86DisassemblerContexts"
38#define ONEBYTE_STR "x86DisassemblerOneByteOpcodes"
39#define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes"
40#define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes"
41#define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes"
42#define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes"
43#define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes"
44#define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes"
45#define THREEDNOW_MAP_STR "x86Disassembler3DNowOpcodes"
46
47// Attributes of an instruction that must be known before the opcode can be
48// processed correctly. Most of these indicate the presence of particular
49// prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
50#define ATTRIBUTE_BITS \
51 ENUM_ENTRY(ATTR_NONE, 0x00) \
52 ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \
53 ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \
54 ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \
55 ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \
56 ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \
57 ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \
58 ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \
59 ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \
60 ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \
61 ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \
62 ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \
63 ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \
64 ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \
65 ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13))
66
67#define ENUM_ENTRY(n, v) n = v,
68enum attributeBits {
69 ATTRIBUTE_BITS
70 ATTR_max
71};
72#undef ENUM_ENTRY
73
74// Combinations of the above attributes that are relevant to instruction
75// decode. Although other combinations are possible, they can be reduced to
76// these without affecting the ultimately decoded instruction.
77
78// Class name Rank Rationale for rank assignment
79#define INSTRUCTION_CONTEXTS \
80 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
81 ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \
82 "64-bit mode but no more") \
83 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
84 "operands change width") \
85 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
86 "operands change width") \
87 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \
88 ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \
89 "but not the operands") \
90 ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \
91 "but not the operands") \
92 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
93 "operands change width") \
94 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
95 "operands change width") \
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame^]96 ENUM_ENTRY(IC_XD_ADSIZE, 3, "requires an ADSIZE prefix, so " \
97 "operands change width") \
98 ENUM_ENTRY(IC_XS_ADSIZE, 3, "requires an ADSIZE prefix, so " \
99 "operands change width") \
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]100 ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\
101 "change width; overrides IC_OPSIZE") \
102 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \
103 "prefix") \
104 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \
105 ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \
106 ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \
107 "IC_ADSIZE") \
108 ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \
109 "secondary") \
110 ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \
111 ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \
112 ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame^]113 ENUM_ENTRY(IC_64BIT_XD_ADSIZE, 3, "Just as meaningful as IC_XD_ADSIZE") \
114 ENUM_ENTRY(IC_64BIT_XS_ADSIZE, 3, "Just as meaningful as IC_XS_ADSIZE") \
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]115 ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \
116 "opcode") \
117 ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \
118 "IC_64BIT_REXW_XS") \
119 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \
120 "else because this changes most " \
121 "operands' meaning") \
122 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
123 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
124 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
125 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
126 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
127 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
128 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
129 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
130 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
131 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
132 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
133 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
134 ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \
135 ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \
136 ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \
137 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \
138 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
139 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
140 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
141 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
142 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
143 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
144 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \
145 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
146 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \
147 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\
148 ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\
149 ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \
150 ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \
151 ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \
152 ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \
153 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \
154 ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \
155 ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\
156 ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\
157 ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \
158 ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \
159 ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \
160 ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \
161 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \
162 ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \
163 ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \
164 ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \
165 ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \
166 ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \
167 ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \
168 ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \
169 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \
170 ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \
171 ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\
172 ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\
173 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \
174 ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \
175 ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \
176 ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \
177 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \
178 ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \
179 ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\
180 ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\
181 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \
182 ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \
183 ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \
184 ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \
185 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \
186 ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \
187 ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \
188 ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \
189 ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \
190 ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \
191 ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \
192 ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \
193 ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \
194 ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \
195 ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\
196 ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\
197 ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \
198 ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \
199 ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \
200 ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \
201 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \
202 ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \
203 ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\
204 ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\
205 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \
206 ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \
207 ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \
208 ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \
209 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \
210 ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
211 ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
212 ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
213 ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \
214 ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
215 ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
216 ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
217 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \
218 ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
219 ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\
220 ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\
221 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \
222 ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
223 ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \
224 ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \
225 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \
226 ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
227 ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
228 ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
229 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \
230 ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
231 ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
232 ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
233 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \
234 ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \
235 ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \
236 ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \
237 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \
238 ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \
239 ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \
240 ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \
241 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \
242 ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \
243 ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\
244 ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\
245 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \
246 ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \
247 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \
248 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \
249 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \
250 ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \
251 ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\
252 ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\
253 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \
254 ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \
255 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \
256 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \
257 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \
258 ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \
259 ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \
260 ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \
261 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \
262 ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \
263 ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \
264 ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \
265 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \
266 ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \
267 ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\
268 ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\
269 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \
270 ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \
271 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \
272 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \
273 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \
274 ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \
275 ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\
276 ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\
277 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \
278 ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \
279 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \
280 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \
281 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize")
282
283#define ENUM_ENTRY(n, r, d) n,
284enum InstructionContext {
285 INSTRUCTION_CONTEXTS
286 IC_max
287};
288#undef ENUM_ENTRY
289
290// Opcode types, which determine which decode table to use, both in the Intel
291// manual and also for the decoder.
292enum OpcodeType {
293 ONEBYTE = 0,
294 TWOBYTE = 1,
295 THREEBYTE_38 = 2,
296 THREEBYTE_3A = 3,
297 XOP8_MAP = 4,
298 XOP9_MAP = 5,
299 XOPA_MAP = 6,
300 THREEDNOW_MAP = 7
301};
302
303// The following structs are used for the hierarchical decode table. After
304// determining the instruction's class (i.e., which IC_* constant applies to
305// it), the decoder reads the opcode. Some instructions require specific
306// values of the ModR/M byte, so the ModR/M byte indexes into the final table.
307//
308// If a ModR/M byte is not required, "required" is left unset, and the values
309// for each instructionID are identical.
310typedef uint16_t InstrUID;
311
312// ModRMDecisionType - describes the type of ModR/M decision, allowing the
313// consumer to determine the number of entries in it.
314//
315// MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
316// instruction is the same.
317// MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
318// corresponds to one instruction; otherwise, it corresponds to
319// a different instruction.
320// MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
321// divided by 8 is used to select instruction; otherwise, each
322// value of the ModR/M byte could correspond to a different
323// instruction.
324// MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
325// corresponds to instructions that use reg field as opcode
326// MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
327// to a different instruction.
328#define MODRMTYPES \
329 ENUM_ENTRY(MODRM_ONEENTRY) \
330 ENUM_ENTRY(MODRM_SPLITRM) \
331 ENUM_ENTRY(MODRM_SPLITMISC) \
332 ENUM_ENTRY(MODRM_SPLITREG) \
333 ENUM_ENTRY(MODRM_FULL)
334
335#define ENUM_ENTRY(n) n,
336enum ModRMDecisionType {
337 MODRMTYPES
338 MODRM_max
339};
340#undef ENUM_ENTRY
341
342#define CASE_ENCODING_RM \
343 case ENCODING_RM: \
344 case ENCODING_RM_CD2: \
345 case ENCODING_RM_CD4: \
346 case ENCODING_RM_CD8: \
347 case ENCODING_RM_CD16: \
348 case ENCODING_RM_CD32: \
349 case ENCODING_RM_CD64
350
351#define CASE_ENCODING_VSIB \
352 case ENCODING_VSIB: \
353 case ENCODING_VSIB_CD2: \
354 case ENCODING_VSIB_CD4: \
355 case ENCODING_VSIB_CD8: \
356 case ENCODING_VSIB_CD16: \
357 case ENCODING_VSIB_CD32: \
358 case ENCODING_VSIB_CD64
359
360// Physical encodings of instruction operands.
361#define ENCODINGS \
362 ENUM_ENTRY(ENCODING_NONE, "") \
363 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
364 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
365 ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \
366 ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \
367 ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \
368 ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \
369 ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \
370 ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \
371 ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \
372 ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \
373 ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \
374 ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \
375 ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \
376 ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \
377 ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \
378 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
379 ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \
380 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \
381 ENUM_ENTRY(ENCODING_IW, "2-byte") \
382 ENUM_ENTRY(ENCODING_ID, "4-byte") \
383 ENUM_ENTRY(ENCODING_IO, "8-byte") \
384 ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \
385 "the opcode byte") \
386 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
387 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
388 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
389 ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \
390 "byte.") \
391 \
392 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
393 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
394 ENUM_ENTRY(ENCODING_IRC, "Immediate for static rounding control") \
395 ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
396 "opcode byte") \
397 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
398 "in type") \
399 ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \
400 ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes")
401
402#define ENUM_ENTRY(n, d) n,
403enum OperandEncoding {
404 ENCODINGS
405 ENCODING_max
406};
407#undef ENUM_ENTRY
408
409// Semantic interpretations of instruction operands.
410#define TYPES \
411 ENUM_ENTRY(TYPE_NONE, "") \
412 ENUM_ENTRY(TYPE_REL, "immediate address") \
413 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
414 ENUM_ENTRY(TYPE_R16, "2-byte") \
415 ENUM_ENTRY(TYPE_R32, "4-byte") \
416 ENUM_ENTRY(TYPE_R64, "8-byte") \
417 ENUM_ENTRY(TYPE_IMM, "immediate operand") \
418 ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \
419 ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \
420 ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \
421 ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \
422 ENUM_ENTRY(TYPE_M, "Memory operand") \
423 ENUM_ENTRY(TYPE_MVSIBX, "Memory operand using XMM index") \
424 ENUM_ENTRY(TYPE_MVSIBY, "Memory operand using YMM index") \
425 ENUM_ENTRY(TYPE_MVSIBZ, "Memory operand using ZMM index") \
426 ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \
427 ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \
428 ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \
429 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
430 ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \
431 ENUM_ENTRY(TYPE_XMM, "16-byte") \
432 ENUM_ENTRY(TYPE_YMM, "32-byte") \
433 ENUM_ENTRY(TYPE_ZMM, "64-byte") \
434 ENUM_ENTRY(TYPE_VK, "mask register") \
435 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
436 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
437 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
438 ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \
439 \
440 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
441 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
442 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
443 ENUM_ENTRY(TYPE_DUP1, "operand 1") \
444 ENUM_ENTRY(TYPE_DUP2, "operand 2") \
445 ENUM_ENTRY(TYPE_DUP3, "operand 3") \
446 ENUM_ENTRY(TYPE_DUP4, "operand 4") \
447
448#define ENUM_ENTRY(n, d) n,
449enum OperandType {
450 TYPES
451 TYPE_max
452};
453#undef ENUM_ENTRY
454
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100[diff] [blame^]455/// The specification for how to extract and interpret one operand.
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100[diff] [blame]456struct OperandSpecifier {
457 uint8_t encoding;
458 uint8_t type;
459};
460
461static const unsigned X86_MAX_OPERANDS = 6;
462
463/// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
464/// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
465/// respectively.
466enum DisassemblerMode {
467 MODE_16BIT,
468 MODE_32BIT,
469 MODE_64BIT
470};
471
472} // namespace X86Disassembler
473} // namespace llvm
474
475#endif