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Andrew Scull5e1ddfa2018-08-14 10:06:54 +01001//===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
2//
Andrew Walbran16937d02019-10-22 13:54:20 +01003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Andrew Scull5e1ddfa2018-08-14 10:06:54 +01006//
7//===----------------------------------------------------------------------===//
8//
9/// Target-Independent Code Generator Pass Configuration Options pass.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
14#define LLVM_CODEGEN_TARGETPASSCONFIG_H
15
16#include "llvm/Pass.h"
17#include "llvm/Support/CodeGen.h"
Andrew Scullcdfcccc2018-10-05 20:58:37 +010018#include <cassert>
Andrew Scull5e1ddfa2018-08-14 10:06:54 +010019#include <string>
20
21namespace llvm {
22
23class LLVMTargetMachine;
24struct MachineSchedContext;
25class PassConfigImpl;
26class ScheduleDAGInstrs;
Andrew Walbran3d2c1972020-04-07 12:24:26 +010027class CSEConfigBase;
Olivier Deprezf4ef2d02021-04-20 13:36:24 +020028class PassInstrumentationCallbacks;
Andrew Scull5e1ddfa2018-08-14 10:06:54 +010029
30// The old pass manager infrastructure is hidden in a legacy namespace now.
31namespace legacy {
32
33class PassManagerBase;
34
35} // end namespace legacy
36
37using legacy::PassManagerBase;
38
39/// Discriminated union of Pass ID types.
40///
41/// The PassConfig API prefers dealing with IDs because they are safer and more
42/// efficient. IDs decouple configuration from instantiation. This way, when a
43/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
44/// refer to a Pass pointer after adding it to a pass manager, which deletes
45/// redundant pass instances.
46///
47/// However, it is convient to directly instantiate target passes with
48/// non-default ctors. These often don't have a registered PassInfo. Rather than
49/// force all target passes to implement the pass registry boilerplate, allow
50/// the PassConfig API to handle either type.
51///
52/// AnalysisID is sadly char*, so PointerIntPair won't work.
53class IdentifyingPassPtr {
54 union {
55 AnalysisID ID;
56 Pass *P;
57 };
58 bool IsInstance = false;
59
60public:
61 IdentifyingPassPtr() : P(nullptr) {}
62 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
63 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
64
65 bool isValid() const { return P; }
66 bool isInstance() const { return IsInstance; }
67
68 AnalysisID getID() const {
69 assert(!IsInstance && "Not a Pass ID");
70 return ID;
71 }
72
73 Pass *getInstance() const {
74 assert(IsInstance && "Not a Pass Instance");
75 return P;
76 }
77};
78
Andrew Scull5e1ddfa2018-08-14 10:06:54 +010079
80/// Target-Independent Code Generator Pass Configuration Options.
81///
82/// This is an ImmutablePass solely for the purpose of exposing CodeGen options
83/// to the internals of other CodeGen passes.
84class TargetPassConfig : public ImmutablePass {
85private:
86 PassManagerBase *PM = nullptr;
87 AnalysisID StartBefore = nullptr;
88 AnalysisID StartAfter = nullptr;
89 AnalysisID StopBefore = nullptr;
90 AnalysisID StopAfter = nullptr;
Andrew Walbran16937d02019-10-22 13:54:20 +010091
92 unsigned StartBeforeInstanceNum = 0;
93 unsigned StartBeforeCount = 0;
94
95 unsigned StartAfterInstanceNum = 0;
96 unsigned StartAfterCount = 0;
97
98 unsigned StopBeforeInstanceNum = 0;
99 unsigned StopBeforeCount = 0;
100
101 unsigned StopAfterInstanceNum = 0;
102 unsigned StopAfterCount = 0;
103
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100104 bool Started = true;
105 bool Stopped = false;
106 bool AddingMachinePasses = false;
Olivier Deprezf4ef2d02021-04-20 13:36:24 +0200107 bool DebugifyIsSafe = true;
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100108
109 /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
110 /// a portion of the normal code-gen pass sequence.
111 ///
112 /// If the StartAfter and StartBefore pass ID is zero, then compilation will
113 /// begin at the normal point; otherwise, clear the Started flag to indicate
114 /// that passes should not be added until the starting pass is seen. If the
115 /// Stop pass ID is zero, then compilation will continue to the end.
116 ///
117 /// This function expects that at least one of the StartAfter or the
118 /// StartBefore pass IDs is null.
119 void setStartStopPasses();
120
121protected:
122 LLVMTargetMachine *TM;
123 PassConfigImpl *Impl = nullptr; // Internal data structures
124 bool Initialized = false; // Flagged after all passes are configured.
125
126 // Target Pass Options
127 // Targets provide a default setting, user flags override.
128 bool DisableVerify = false;
129
130 /// Default setting for -enable-tail-merge on this target.
131 bool EnableTailMerge = true;
132
133 /// Require processing of functions such that callees are generated before
134 /// callers.
135 bool RequireCodeGenSCCOrder = false;
136
137 /// Add the actual instruction selection passes. This does not include
138 /// preparation passes on IR.
139 bool addCoreISelPasses();
140
141public:
142 TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm);
143 // Dummy constructor.
144 TargetPassConfig();
145
146 ~TargetPassConfig() override;
147
148 static char ID;
149
150 /// Get the right type of TargetMachine for this target.
151 template<typename TMC> TMC &getTM() const {
152 return *static_cast<TMC*>(TM);
153 }
154
155 //
156 void setInitialized() { Initialized = true; }
157
158 CodeGenOpt::Level getOptLevel() const;
159
Andrew Walbran16937d02019-10-22 13:54:20 +0100160 /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after`
161 /// or `-stop-before` options is set.
162 static bool hasLimitedCodeGenPipeline();
163
164 /// Returns true if none of the `-stop-before` and `-stop-after` options is
165 /// set.
166 static bool willCompleteCodeGenPipeline();
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100167
168 /// If hasLimitedCodeGenPipeline is true, this method
169 /// returns a string with the name of the options, separated
170 /// by \p Separator that caused this pipeline to be limited.
Olivier Deprezf4ef2d02021-04-20 13:36:24 +0200171 static std::string
172 getLimitedCodeGenPipelineReason(const char *Separator = "/");
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100173
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100174 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
175
176 bool getEnableTailMerge() const { return EnableTailMerge; }
177 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
178
179 bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
180 void setRequiresCodeGenSCCOrder(bool Enable = true) {
181 setOpt(RequireCodeGenSCCOrder, Enable);
182 }
183
184 /// Allow the target to override a specific pass without overriding the pass
185 /// pipeline. When passes are added to the standard pipeline at the
186 /// point where StandardID is expected, add TargetID in its place.
187 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
188
189 /// Insert InsertedPassID pass after TargetPassID pass.
190 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
Olivier Deprezf4ef2d02021-04-20 13:36:24 +0200191 bool VerifyAfter = true);
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100192
193 /// Allow the target to enable a specific standard pass by default.
194 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
195
196 /// Allow the target to disable a specific standard pass by default.
197 void disablePass(AnalysisID PassID) {
198 substitutePass(PassID, IdentifyingPassPtr());
199 }
200
201 /// Return the pass substituted for StandardID by the target.
202 /// If no substitution exists, return StandardID.
203 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
204
205 /// Return true if the pass has been substituted by the target or
206 /// overridden on the command line.
207 bool isPassSubstitutedOrOverridden(AnalysisID ID) const;
208
209 /// Return true if the optimized regalloc pipeline is enabled.
210 bool getOptimizeRegAlloc() const;
211
212 /// Return true if the default global register allocator is in use and
213 /// has not be overriden on the command line with '-regalloc=...'
214 bool usingDefaultRegAlloc() const;
215
216 /// High level function that adds all passes necessary to go from llvm IR
217 /// representation to the MI representation.
218 /// Adds IR based lowering and target specific optimization passes and finally
219 /// the core instruction selection passes.
220 /// \returns true if an error occurred, false otherwise.
221 bool addISelPasses();
222
223 /// Add common target configurable passes that perform LLVM IR to IR
224 /// transforms following machine independent optimization.
225 virtual void addIRPasses();
226
227 /// Add passes to lower exception handling for the code generator.
228 void addPassesToHandleExceptions();
229
230 /// Add pass to prepare the LLVM IR for code generation. This should be done
231 /// before exception handling preparation passes.
232 virtual void addCodeGenPrepare();
233
234 /// Add common passes that perform LLVM IR to IR transforms in preparation for
235 /// instruction selection.
236 virtual void addISelPrepare();
237
238 /// addInstSelector - This method should install an instruction selector pass,
239 /// which converts from LLVM code to machine instructions.
240 virtual bool addInstSelector() {
241 return true;
242 }
243
244 /// This method should install an IR translator pass, which converts from
245 /// LLVM code to machine instructions with possibly generic opcodes.
246 virtual bool addIRTranslator() { return true; }
247
248 /// This method may be implemented by targets that want to run passes
249 /// immediately before legalization.
250 virtual void addPreLegalizeMachineIR() {}
251
252 /// This method should install a legalize pass, which converts the instruction
253 /// sequence into one that can be selected by the target.
254 virtual bool addLegalizeMachineIR() { return true; }
255
256 /// This method may be implemented by targets that want to run passes
257 /// immediately before the register bank selection.
258 virtual void addPreRegBankSelect() {}
259
260 /// This method should install a register bank selector pass, which
261 /// assigns register banks to virtual registers without a register
262 /// class or register banks.
263 virtual bool addRegBankSelect() { return true; }
264
265 /// This method may be implemented by targets that want to run passes
266 /// immediately before the (global) instruction selection.
267 virtual void addPreGlobalInstructionSelect() {}
268
269 /// This method should install a (global) instruction selector pass, which
270 /// converts possibly generic instructions to fully target-specific
271 /// instructions, thereby constraining all generic virtual registers to
272 /// register classes.
273 virtual bool addGlobalInstructionSelect() { return true; }
274
275 /// Add the complete, standard set of LLVM CodeGen passes.
276 /// Fully developed targets will not generally override this.
277 virtual void addMachinePasses();
278
279 /// Create an instance of ScheduleDAGInstrs to be run within the standard
280 /// MachineScheduler pass for this function and target at the current
281 /// optimization level.
282 ///
283 /// This can also be used to plug a new MachineSchedStrategy into an instance
284 /// of the standard ScheduleDAGMI:
Olivier Deprezf4ef2d02021-04-20 13:36:24 +0200285 /// return new ScheduleDAGMI(C, std::make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100286 ///
287 /// Return NULL to select the default (generic) machine scheduler.
288 virtual ScheduleDAGInstrs *
289 createMachineScheduler(MachineSchedContext *C) const {
290 return nullptr;
291 }
292
293 /// Similar to createMachineScheduler but used when postRA machine scheduling
294 /// is enabled.
295 virtual ScheduleDAGInstrs *
296 createPostMachineScheduler(MachineSchedContext *C) const {
297 return nullptr;
298 }
299
300 /// printAndVerify - Add a pass to dump then verify the machine function, if
301 /// those steps are enabled.
302 void printAndVerify(const std::string &Banner);
303
304 /// Add a pass to print the machine function if printing is enabled.
305 void addPrintPass(const std::string &Banner);
306
307 /// Add a pass to perform basic verification of the machine function if
308 /// verification is enabled.
309 void addVerifyPass(const std::string &Banner);
310
Olivier Deprezf4ef2d02021-04-20 13:36:24 +0200311 /// Add a pass to add synthesized debug info to the MIR.
312 void addDebugifyPass();
313
314 /// Add a pass to remove debug info from the MIR.
315 void addStripDebugPass();
316
317 /// Add a pass to check synthesized debug info for MIR.
318 void addCheckDebugPass();
319
320 /// Add standard passes before a pass that's about to be added. For example,
321 /// the DebugifyMachineModulePass if it is enabled.
322 void addMachinePrePasses(bool AllowDebugify = true);
323
324 /// Add standard passes after a pass that has just been added. For example,
325 /// the MachineVerifier if it is enabled.
326 void addMachinePostPasses(const std::string &Banner, bool AllowVerify = true,
327 bool AllowStrip = true);
328
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100329 /// Check whether or not GlobalISel should abort on error.
330 /// When this is disabled, GlobalISel will fall back on SDISel instead of
331 /// erroring out.
332 bool isGlobalISelAbortEnabled() const;
333
334 /// Check whether or not a diagnostic should be emitted when GlobalISel
335 /// uses the fallback path. In other words, it will emit a diagnostic
336 /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
337 virtual bool reportDiagnosticWhenGlobalISelFallback() const;
338
Andrew Walbran16937d02019-10-22 13:54:20 +0100339 /// Check whether continuous CSE should be enabled in GISel passes.
340 /// By default, it's enabled for non O0 levels.
341 virtual bool isGISelCSEEnabled() const;
342
Andrew Walbran3d2c1972020-04-07 12:24:26 +0100343 /// Returns the CSEConfig object to use for the current optimization level.
344 virtual std::unique_ptr<CSEConfigBase> getCSEConfig() const;
345
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100346protected:
347 // Helper to verify the analysis is really immutable.
348 void setOpt(bool &Opt, bool Val);
349
350 /// Methods with trivial inline returns are convenient points in the common
351 /// codegen pass pipeline where targets may insert passes. Methods with
352 /// out-of-line standard implementations are major CodeGen stages called by
353 /// addMachinePasses. Some targets may override major stages when inserting
354 /// passes is insufficient, but maintaining overriden stages is more work.
355 ///
356
357 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
358 /// passes (which are run just before instruction selector).
359 virtual bool addPreISel() {
360 return true;
361 }
362
363 /// addMachineSSAOptimization - Add standard passes that optimize machine
364 /// instructions in SSA form.
365 virtual void addMachineSSAOptimization();
366
367 /// Add passes that optimize instruction level parallelism for out-of-order
368 /// targets. These passes are run while the machine code is still in SSA
369 /// form, so they can use MachineTraceMetrics to control their heuristics.
370 ///
371 /// All passes added here should preserve the MachineDominatorTree,
372 /// MachineLoopInfo, and MachineTraceMetrics analyses.
373 virtual bool addILPOpts() {
374 return false;
375 }
376
377 /// This method may be implemented by targets that want to run passes
378 /// immediately before register allocation.
379 virtual void addPreRegAlloc() { }
380
381 /// createTargetRegisterAllocator - Create the register allocator pass for
382 /// this target at the current optimization level.
383 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
384
385 /// addFastRegAlloc - Add the minimum set of target-independent passes that
386 /// are required for fast register allocation.
Andrew Walbran3d2c1972020-04-07 12:24:26 +0100387 virtual void addFastRegAlloc();
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100388
389 /// addOptimizedRegAlloc - Add passes related to register allocation.
390 /// LLVMTargetMachine provides standard regalloc passes for most targets.
Andrew Walbran3d2c1972020-04-07 12:24:26 +0100391 virtual void addOptimizedRegAlloc();
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100392
393 /// addPreRewrite - Add passes to the optimized register allocation pipeline
394 /// after register allocation is complete, but before virtual registers are
395 /// rewritten to physical registers.
396 ///
397 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
398 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
399 /// When these passes run, VirtRegMap contains legal physreg assignments for
400 /// all virtual registers.
Andrew Walbran3d2c1972020-04-07 12:24:26 +0100401 ///
402 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
403 /// be honored. This is also not generally used for the the fast variant,
404 /// where the allocation and rewriting are done in one pass.
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100405 virtual bool addPreRewrite() {
406 return false;
407 }
408
Andrew Walbran3d2c1972020-04-07 12:24:26 +0100409 /// Add passes to be run immediately after virtual registers are rewritten
410 /// to physical registers.
411 virtual void addPostRewrite() { }
412
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100413 /// This method may be implemented by targets that want to run passes after
414 /// register allocation pass pipeline but before prolog-epilog insertion.
415 virtual void addPostRegAlloc() { }
416
417 /// Add passes that optimize machine instructions after register allocation.
418 virtual void addMachineLateOptimization();
419
420 /// This method may be implemented by targets that want to run passes after
421 /// prolog-epilog insertion and before the second instruction scheduling pass.
422 virtual void addPreSched2() { }
423
424 /// addGCPasses - Add late codegen passes that analyze code for garbage
425 /// collection. This should return true if GC info should be printed after
426 /// these passes.
427 virtual bool addGCPasses();
428
429 /// Add standard basic block placement passes.
430 virtual void addBlockPlacement();
431
432 /// This pass may be implemented by targets that want to run passes
433 /// immediately before machine code is emitted.
434 virtual void addPreEmitPass() { }
435
436 /// Targets may add passes immediately before machine code is emitted in this
437 /// callback. This is called even later than `addPreEmitPass`.
438 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
439 // position and remove the `2` suffix here as this callback is what
440 // `addPreEmitPass` *should* be but in reality isn't.
441 virtual void addPreEmitPass2() {}
442
443 /// Utilities for targets to add passes to the pass manager.
444 ///
445
446 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
447 /// Return the pass that was added, or zero if no pass was added.
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100448 /// @p verifyAfter if true and adding a machine function pass add an extra
449 /// machine verification pass afterwards.
Olivier Deprezf4ef2d02021-04-20 13:36:24 +0200450 AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true);
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100451
452 /// Add a pass to the PassManager if that pass is supposed to be run, as
453 /// determined by the StartAfter and StopAfter options. Takes ownership of the
454 /// pass.
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100455 /// @p verifyAfter if true and adding a machine function pass add an extra
456 /// machine verification pass afterwards.
Olivier Deprezf4ef2d02021-04-20 13:36:24 +0200457 void addPass(Pass *P, bool verifyAfter = true);
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100458
459 /// addMachinePasses helper to create the target-selected or overriden
460 /// regalloc pass.
Andrew Walbran3d2c1972020-04-07 12:24:26 +0100461 virtual FunctionPass *createRegAllocPass(bool Optimized);
462
Olivier Deprezf4ef2d02021-04-20 13:36:24 +0200463 /// Add core register allocator passes which do the actual register assignment
Andrew Walbran3d2c1972020-04-07 12:24:26 +0100464 /// and rewriting. \returns true if any passes were added.
Olivier Deprezf4ef2d02021-04-20 13:36:24 +0200465 virtual bool addRegAssignAndRewriteFast();
466 virtual bool addRegAssignAndRewriteOptimized();
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100467};
468
Olivier Deprezf4ef2d02021-04-20 13:36:24 +0200469void registerCodeGenCallback(PassInstrumentationCallbacks &PIC,
470 LLVMTargetMachine &);
471
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100472} // end namespace llvm
473
474#endif // LLVM_CODEGEN_TARGETPASSCONFIG_H