Update prebuilt Clang to r416183b from Android.
https://android.googlesource.com/platform/prebuilts/clang/host/
linux-x86/+/06a71ddac05c22edb2d10b590e1769b3f8619bef
clang 12.0.5 (based on r416183b) from build 7284624.
Change-Id: I277a316abcf47307562d8b748b84870f31a72866
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
diff --git a/linux-x64/clang/include/llvm/MC/MCSubtargetInfo.h b/linux-x64/clang/include/llvm/MC/MCSubtargetInfo.h
index 9490a6e..2c1072d 100644
--- a/linux-x64/clang/include/llvm/MC/MCSubtargetInfo.h
+++ b/linux-x64/clang/include/llvm/MC/MCSubtargetInfo.h
@@ -54,6 +54,7 @@
struct SubtargetSubTypeKV {
const char *Key; ///< K-V key string
FeatureBitArray Implies; ///< K-V bit mask
+ FeatureBitArray TuneImplies; ///< K-V bit mask
const MCSchedModel *SchedModel;
/// Compare routine for std::lower_bound
@@ -74,6 +75,7 @@
class MCSubtargetInfo {
Triple TargetTriple;
std::string CPU; // CPU being targeted.
+ std::string TuneCPU; // CPU being tuned for.
ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
ArrayRef<SubtargetSubTypeKV> ProcDesc; // Processor descriptions
@@ -90,8 +92,8 @@
public:
MCSubtargetInfo(const MCSubtargetInfo &) = default;
- MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
- ArrayRef<SubtargetFeatureKV> PF,
+ MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
+ StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetSubTypeKV> PD,
const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
@@ -103,6 +105,7 @@
const Triple &getTargetTriple() const { return TargetTriple; }
StringRef getCPU() const { return CPU; }
+ StringRef getTuneCPU() const { return TuneCPU; }
const FeatureBitset& getFeatureBits() const { return FeatureBits; }
void setFeatureBits(const FeatureBitset &FeatureBits_) {
@@ -118,12 +121,12 @@
///
/// FIXME: Find a way to stick this in the constructor, since it should only
/// be called during initialization.
- void InitMCProcessorInfo(StringRef CPU, StringRef FS);
+ void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS);
public:
- /// Set the features to the default for the given CPU with an appended feature
- /// string.
- void setDefaultFeatures(StringRef CPU, StringRef FS);
+ /// Set the features to the default for the given CPU and TuneCPU, with ano
+ /// appended feature string.
+ void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
/// Toggle a feature and return the re-computed feature bits.
/// This version does not change the implied bits.
@@ -210,17 +213,71 @@
void initInstrItins(InstrItineraryData &InstrItins) const;
/// Resolve a variant scheduling class for the given MCInst and CPU.
- virtual unsigned
- resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
- unsigned CPUID) const {
+ virtual unsigned resolveVariantSchedClass(unsigned SchedClass,
+ const MCInst *MI,
+ const MCInstrInfo *MCII,
+ unsigned CPUID) const {
return 0;
}
/// Check whether the CPU string is valid.
bool isCPUStringValid(StringRef CPU) const {
- auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
+ auto Found = llvm::lower_bound(ProcDesc, CPU);
return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
}
+
+ virtual unsigned getHwMode() const { return 0; }
+
+ /// Return the cache size in bytes for the given level of cache.
+ /// Level is zero-based, so a value of zero means the first level of
+ /// cache.
+ ///
+ virtual Optional<unsigned> getCacheSize(unsigned Level) const;
+
+ /// Return the cache associatvity for the given level of cache.
+ /// Level is zero-based, so a value of zero means the first level of
+ /// cache.
+ ///
+ virtual Optional<unsigned> getCacheAssociativity(unsigned Level) const;
+
+ /// Return the target cache line size in bytes at a given level.
+ ///
+ virtual Optional<unsigned> getCacheLineSize(unsigned Level) const;
+
+ /// Return the target cache line size in bytes. By default, return
+ /// the line size for the bottom-most level of cache. This provides
+ /// a more convenient interface for the common case where all cache
+ /// levels have the same line size. Return zero if there is no
+ /// cache model.
+ ///
+ virtual unsigned getCacheLineSize() const {
+ Optional<unsigned> Size = getCacheLineSize(0);
+ if (Size)
+ return *Size;
+
+ return 0;
+ }
+
+ /// Return the preferred prefetch distance in terms of instructions.
+ ///
+ virtual unsigned getPrefetchDistance() const;
+
+ /// Return the maximum prefetch distance in terms of loop
+ /// iterations.
+ ///
+ virtual unsigned getMaxPrefetchIterationsAhead() const;
+
+ /// \return True if prefetching should also be done for writes.
+ ///
+ virtual bool enableWritePrefetching() const;
+
+ /// Return the minimum stride necessary to trigger software
+ /// prefetching.
+ ///
+ virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses,
+ unsigned NumStridedMemAccesses,
+ unsigned NumPrefetches,
+ bool HasCall) const;
};
} // end namespace llvm