Update prebuilt Clang to r416183b from Android.
https://android.googlesource.com/platform/prebuilts/clang/host/
linux-x86/+/06a71ddac05c22edb2d10b590e1769b3f8619bef
clang 12.0.5 (based on r416183b) from build 7284624.
Change-Id: I277a316abcf47307562d8b748b84870f31a72866
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
diff --git a/linux-x64/clang/include/llvm/CodeGen/CallingConvLower.h b/linux-x64/clang/include/llvm/CodeGen/CallingConvLower.h
index aa339e1..2fe4e37 100644
--- a/linux-x64/clang/include/llvm/CodeGen/CallingConvLower.h
+++ b/linux-x64/clang/include/llvm/CodeGen/CallingConvLower.h
@@ -16,16 +16,17 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/Register.h"
#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Support/Alignment.h"
namespace llvm {
class CCState;
+class MachineFunction;
class MVT;
-class TargetMachine;
class TargetRegisterInfo;
/// CCValAssign - Represent assignment of one arg/retval to a location.
@@ -43,6 +44,7 @@
AExtUpper, // The value is in the upper bits of the location and should be
// extended with undefined upper bits when retrieved.
BCvt, // The value is bit-converted in the location.
+ Trunc, // The value is truncated in the location.
VExt, // The value is vector-widened in the location.
// FIXME: Not implemented yet. Code that uses AExt to mean
// vector-widen should be fixed to use VExt instead.
@@ -163,9 +165,9 @@
/// Describes a register that needs to be forwarded from the prologue to a
/// musttail call.
struct ForwardedRegister {
- ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
+ ForwardedRegister(Register VReg, MCPhysReg PReg, MVT VT)
: VReg(VReg), PReg(PReg), VT(VT) {}
- unsigned VReg;
+ Register VReg;
MCPhysReg PReg;
MVT VT;
};
@@ -197,7 +199,7 @@
LLVMContext &Context;
unsigned StackOffset;
- unsigned MaxStackArgAlign;
+ Align MaxStackArgAlign;
SmallVector<uint32_t, 16> UsedRegs;
SmallVector<CCValAssign, 4> PendingLocs;
SmallVector<ISD::ArgFlagsTy, 4> PendingArgFlags;
@@ -220,9 +222,7 @@
// ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
//
// In case of 8 bytes stack alignment,
- // ByValRegs may also contain information about wasted registers.
// In function shown above, r3 would be wasted according to AAPCS rules.
- // And in that case ByValRegs[1].Waste would be "true".
// ByValRegs vector size still would be 2,
// while "%t" goes to the stack: it wouldn't be described in ByValRegs.
//
@@ -232,19 +232,13 @@
// 3. Argument analysis (LowerFormatArguments, for example). After
// some byval argument was analyzed, InRegsParamsProcessed is increased.
struct ByValInfo {
- ByValInfo(unsigned B, unsigned E, bool IsWaste = false) :
- Begin(B), End(E), Waste(IsWaste) {}
+ ByValInfo(unsigned B, unsigned E) : Begin(B), End(E) {}
+
// First register allocated for current parameter.
unsigned Begin;
// First after last register allocated for current parameter.
unsigned End;
-
- // Means that current range of registers doesn't belong to any
- // parameters. It was wasted due to stack alignment rules.
- // For more information see:
- // AAPCS, 5.5 Parameter Passing, Stage C, C.3.
- bool Waste;
};
SmallVector<ByValInfo, 4 > ByValRegs;
@@ -280,8 +274,8 @@
/// isAllocated - Return true if the specified register (or an alias) is
/// allocated.
- bool isAllocated(unsigned Reg) const {
- return UsedRegs[Reg/32] & (1 << (Reg&31));
+ bool isAllocated(MCRegister Reg) const {
+ return UsedRegs[Reg / 32] & (1 << (Reg & 31));
}
/// AnalyzeFormalArguments - Analyze an array of argument values,
@@ -331,7 +325,7 @@
/// A shadow allocated register is a register that was allocated
/// but wasn't added to the location list (Locs).
/// \returns true if the register was allocated as shadow or false otherwise.
- bool IsShadowAllocatedReg(unsigned Reg) const;
+ bool IsShadowAllocatedReg(MCRegister Reg) const;
/// AnalyzeCallResult - Same as above except it's specialized for calls which
/// produce a single value.
@@ -346,18 +340,25 @@
return Regs.size();
}
+ void DeallocateReg(MCPhysReg Reg) {
+ assert(isAllocated(Reg) && "Trying to deallocate an unallocated register");
+ MarkUnallocated(Reg);
+ }
+
/// AllocateReg - Attempt to allocate one register. If it is not available,
/// return zero. Otherwise, return the register, marking it and any aliases
/// as allocated.
- unsigned AllocateReg(unsigned Reg) {
- if (isAllocated(Reg)) return 0;
+ MCRegister AllocateReg(MCPhysReg Reg) {
+ if (isAllocated(Reg))
+ return MCRegister();
MarkAllocated(Reg);
return Reg;
}
/// Version of AllocateReg with extra register to be shadowed.
- unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
- if (isAllocated(Reg)) return 0;
+ MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) {
+ if (isAllocated(Reg))
+ return MCRegister();
MarkAllocated(Reg);
MarkAllocated(ShadowReg);
return Reg;
@@ -366,13 +367,13 @@
/// AllocateReg - Attempt to allocate one of the specified registers. If none
/// are available, return zero. Otherwise, return the first one available,
/// marking it and any aliases as allocated.
- unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
+ MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) {
unsigned FirstUnalloc = getFirstUnallocated(Regs);
if (FirstUnalloc == Regs.size())
- return 0; // Didn't find the reg.
+ return MCRegister(); // Didn't find the reg.
// Mark the register and any aliases as allocated.
- unsigned Reg = Regs[FirstUnalloc];
+ MCPhysReg Reg = Regs[FirstUnalloc];
MarkAllocated(Reg);
return Reg;
}
@@ -380,7 +381,7 @@
/// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
/// registers. If this is not possible, return zero. Otherwise, return the first
/// register of the block that were allocated, marking the entire block as allocated.
- unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
+ MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
if (RegsRequired > Regs.size())
return 0;
@@ -407,13 +408,13 @@
}
/// Version of AllocateReg with list of registers to be shadowed.
- unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
+ MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
unsigned FirstUnalloc = getFirstUnallocated(Regs);
if (FirstUnalloc == Regs.size())
- return 0; // Didn't find the reg.
+ return MCRegister(); // Didn't find the reg.
// Mark the register and any aliases as allocated.
- unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
+ MCRegister Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
MarkAllocated(Reg);
MarkAllocated(ShadowReg);
return Reg;
@@ -421,42 +422,48 @@
/// AllocateStack - Allocate a chunk of stack space with the specified size
/// and alignment.
- unsigned AllocateStack(unsigned Size, unsigned Align) {
- assert(Align && ((Align - 1) & Align) == 0); // Align is power of 2.
- StackOffset = alignTo(StackOffset, Align);
+ unsigned AllocateStack(unsigned Size, Align Alignment) {
+ StackOffset = alignTo(StackOffset, Alignment);
unsigned Result = StackOffset;
StackOffset += Size;
- MaxStackArgAlign = std::max(Align, MaxStackArgAlign);
- ensureMaxAlignment(Align);
+ MaxStackArgAlign = std::max(Alignment, MaxStackArgAlign);
+ ensureMaxAlignment(Alignment);
return Result;
}
- void ensureMaxAlignment(unsigned Align) {
- if (!AnalyzingMustTailForwardedRegs)
- MF.getFrameInfo().ensureMaxAlignment(Align);
+ // FIXME: Deprecate this function when transition to Align is over.
+ LLVM_ATTRIBUTE_DEPRECATED(unsigned AllocateStack(unsigned Size,
+ unsigned Alignment),
+ "Use the version that takes Align instead.") {
+ return AllocateStack(Size, Align(Alignment));
}
+ void ensureMaxAlignment(Align Alignment);
+
/// Version of AllocateStack with extra register to be shadowed.
- unsigned AllocateStack(unsigned Size, unsigned Align, unsigned ShadowReg) {
+ LLVM_ATTRIBUTE_DEPRECATED(unsigned AllocateStack(unsigned Size,
+ unsigned Alignment,
+ unsigned ShadowReg),
+ "Use the version that takes Align instead.") {
MarkAllocated(ShadowReg);
- return AllocateStack(Size, Align);
+ return AllocateStack(Size, Align(Alignment));
}
/// Version of AllocateStack with list of extra registers to be shadowed.
/// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
- unsigned AllocateStack(unsigned Size, unsigned Align,
+ unsigned AllocateStack(unsigned Size, Align Alignment,
ArrayRef<MCPhysReg> ShadowRegs) {
for (unsigned i = 0; i < ShadowRegs.size(); ++i)
MarkAllocated(ShadowRegs[i]);
- return AllocateStack(Size, Align);
+ return AllocateStack(Size, Alignment);
}
// HandleByVal - Allocate a stack slot large enough to pass an argument by
// value. The size and alignment information of the argument is encoded in its
// parameter attribute.
- void HandleByVal(unsigned ValNo, MVT ValVT,
- MVT LocVT, CCValAssign::LocInfo LocInfo,
- int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
+ void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
+ CCValAssign::LocInfo LocInfo, int MinSize, Align MinAlign,
+ ISD::ArgFlagsTy ArgFlags);
// Returns count of byval arguments that are to be stored (even partly)
// in registers.
@@ -567,7 +574,9 @@
private:
/// MarkAllocated - Mark a register and all of its aliases as allocated.
- void MarkAllocated(unsigned Reg);
+ void MarkAllocated(MCPhysReg Reg);
+
+ void MarkUnallocated(MCPhysReg Reg);
};
} // end namespace llvm