Update prebuilt Clang to r365631c1 from Android.
The version we had was segfaulting.
Bug: 132420445
Change-Id: Icb45a6fe0b4e2166f7895e669df1157cec9fb4e0
diff --git a/linux-x64/clang/include/llvm/Target/GenericOpcodes.td b/linux-x64/clang/include/llvm/Target/GenericOpcodes.td
index e4b452e..11fbf62 100644
--- a/linux-x64/clang/include/llvm/Target/GenericOpcodes.td
+++ b/linux-x64/clang/include/llvm/Target/GenericOpcodes.td
@@ -169,6 +169,12 @@
let hasSideEffects = 0;
}
+def G_JUMP_TABLE : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins unknown:$jti);
+ let hasSideEffects = 0;
+}
+
//------------------------------------------------------------------------------
// Binary ops.
//------------------------------------------------------------------------------
@@ -308,6 +314,38 @@
let hasSideEffects = 0;
}
+// Generic signed integer minimum.
+def G_SMIN : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 1;
+}
+
+// Generic signed integer maximum.
+def G_SMAX : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 1;
+}
+
+// Generic unsigned integer minimum.
+def G_UMIN : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 1;
+}
+
+// Generic unsigned integer maximum.
+def G_UMAX : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 1;
+}
+
//------------------------------------------------------------------------------
// Overflow ops
//------------------------------------------------------------------------------
@@ -455,6 +493,12 @@
let hasSideEffects = 0;
}
+def G_FCOPYSIGN : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src0, type1:$src1);
+ let hasSideEffects = 0;
+}
+
def G_FCANONICALIZE : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
@@ -592,6 +636,20 @@
let hasSideEffects = 0;
}
+// Floating point round to next integer.
+def G_FRINT : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
+// Floating point round to the nearest integer.
+def G_FNEARBYINT : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
//------------------------------------------------------------------------------
// Opcodes for LLVM Intrinsics
//------------------------------------------------------------------------------
@@ -685,6 +743,12 @@
def G_ATOMICRMW_UMAX : G_ATOMICRMW_OP;
def G_ATOMICRMW_UMIN : G_ATOMICRMW_OP;
+def G_FENCE : GenericInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins i32imm:$ordering, i32imm:$scope);
+ let hasSideEffects = 1;
+}
+
//------------------------------------------------------------------------------
// Variadic ops
//------------------------------------------------------------------------------
@@ -799,6 +863,15 @@
let isTerminator = 1;
}
+// Generic branch to jump table entry
+def G_BRJT : GenericInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins ptype0:$tbl, unknown:$jti, type1:$idx);
+ let hasSideEffects = 0;
+ let isBranch = 1;
+ let isTerminator = 1;
+}
+
//------------------------------------------------------------------------------
// Vector ops
//------------------------------------------------------------------------------
diff --git a/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 6b0434a..6cc58d6 100644
--- a/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -49,6 +49,8 @@
def : GINodeEquiv<G_ADD, add>;
def : GINodeEquiv<G_SUB, sub>;
def : GINodeEquiv<G_MUL, mul>;
+def : GINodeEquiv<G_UMULH, mulhu>;
+def : GINodeEquiv<G_SMULH, mulhs>;
def : GINodeEquiv<G_SDIV, sdiv>;
def : GINodeEquiv<G_UDIV, udiv>;
def : GINodeEquiv<G_SREM, srem>;
@@ -76,6 +78,7 @@
def : GINodeEquiv<G_FPOW, fpow>;
def : GINodeEquiv<G_FEXP2, fexp2>;
def : GINodeEquiv<G_FLOG2, flog2>;
+def : GINodeEquiv<G_FCANONICALIZE, fcanonicalize>;
def : GINodeEquiv<G_INTRINSIC, intrinsic_wo_chain>;
// ISD::INTRINSIC_VOID can also be handled with G_INTRINSIC_W_SIDE_EFFECTS.
def : GINodeEquiv<G_INTRINSIC_W_SIDE_EFFECTS, intrinsic_void>;
@@ -88,12 +91,19 @@
def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>;
def : GINodeEquiv<G_CTPOP, ctpop>;
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
+def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
def : GINodeEquiv<G_FCEIL, fceil>;
def : GINodeEquiv<G_FCOS, fcos>;
def : GINodeEquiv<G_FSIN, fsin>;
def : GINodeEquiv<G_FABS, fabs>;
def : GINodeEquiv<G_FSQRT, fsqrt>;
def : GINodeEquiv<G_FFLOOR, ffloor>;
+def : GINodeEquiv<G_FRINT, frint>;
+def : GINodeEquiv<G_FNEARBYINT, fnearbyint>;
+def : GINodeEquiv<G_SMIN, smin>;
+def : GINodeEquiv<G_SMAX, smax>;
+def : GINodeEquiv<G_UMIN, umin>;
+def : GINodeEquiv<G_UMAX, umax>;
// Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some
// complications that tablegen must take care of. For example, Predicates such
@@ -128,6 +138,7 @@
def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max>;
def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin>;
def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax>;
+def : GINodeEquiv<G_FENCE, atomic_fence>;
// Specifies the GlobalISel equivalents for SelectionDAG's ComplexPattern.
// Should be used on defs that subclass GIComplexOperandMatcher<>.
diff --git a/linux-x64/clang/include/llvm/Target/Target.td b/linux-x64/clang/include/llvm/Target/Target.td
index 380e848..d58662e 100644
--- a/linux-x64/clang/include/llvm/Target/Target.td
+++ b/linux-x64/clang/include/llvm/Target/Target.td
@@ -121,6 +121,10 @@
// this register class when printing.
class RegAltNameIndex {
string Namespace = "";
+
+ // A set to be used if the name for a register is not defined in this set.
+ // This allows creating name sets with only a few alternative names.
+ RegAltNameIndex FallbackRegAltNameIndex = ?;
}
def NoRegAltName : RegAltNameIndex;
@@ -394,11 +398,49 @@
class Predicate; // Forward def
+class InstructionEncoding {
+ // Size of encoded instruction.
+ int Size;
+
+ // The "namespace" in which this instruction exists, on targets like ARM
+ // which multiple ISA namespaces exist.
+ string DecoderNamespace = "";
+
+ // List of predicates which will be turned into isel matching code.
+ list<Predicate> Predicates = [];
+
+ string DecoderMethod = "";
+
+ // Is the instruction decoder method able to completely determine if the
+ // given instruction is valid or not. If the TableGen definition of the
+ // instruction specifies bitpattern A??B where A and B are static bits, the
+ // hasCompleteDecoder flag says whether the decoder method fully handles the
+ // ?? space, i.e. if it is a final arbiter for the instruction validity.
+ // If not then the decoder attempts to continue decoding when the decoder
+ // method fails.
+ //
+ // This allows to handle situations where the encoding is not fully
+ // orthogonal. Example:
+ // * InstA with bitpattern 0b0000????,
+ // * InstB with bitpattern 0b000000?? but the associated decoder method
+ // DecodeInstB() returns Fail when ?? is 0b00 or 0b11.
+ //
+ // The decoder tries to decode a bitpattern that matches both InstA and
+ // InstB bitpatterns first as InstB (because it is the most specific
+ // encoding). In the default case (hasCompleteDecoder = 1), when
+ // DecodeInstB() returns Fail the bitpattern gets rejected. By setting
+ // hasCompleteDecoder = 0 in InstB, the decoder is informed that
+ // DecodeInstB() is not able to determine if all possible values of ?? are
+ // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
+ // decode the bitpattern as InstA too.
+ bit hasCompleteDecoder = 1;
+}
+
//===----------------------------------------------------------------------===//
// Instruction set description - These classes correspond to the C++ classes in
// the Target/TargetInstrInfo.h file.
//
-class Instruction {
+class Instruction : InstructionEncoding {
string Namespace = "";
dag OutOperandList; // An dag containing the MI def operand list.
@@ -423,10 +465,6 @@
// from the opcode.
int Size = 0;
- // DecoderNamespace - The "namespace" in which this instruction exists, on
- // targets like ARM which multiple ISA namespaces exist.
- string DecoderNamespace = "";
-
// Code size, for instruction selection.
// FIXME: What does this actually mean?
int CodeSize = 0;
@@ -452,11 +490,16 @@
bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
bit mayLoad = ?; // Is it possible for this inst to read memory?
bit mayStore = ?; // Is it possible for this inst to write memory?
+ bit mayRaiseFPException = 0; // Can this raise a floating-point exception?
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
bit isReMaterializable = 0; // Is this instruction re-materializable?
- bit isPredicable = 0; // Is this instruction predicable?
+ bit isPredicable = 0; // 1 means this instruction is predicable
+ // even if it does not have any operand
+ // tablegen can identify as a predicate
+ bit isUnpredicable = 0; // 1 means this instruction is not predicable
+ // even if it _does_ have a predicate operand
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomInserter = 0; // Pseudo instr needing special help.
bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
@@ -523,31 +566,6 @@
string DisableEncoding = "";
string PostEncoderMethod = "";
- string DecoderMethod = "";
-
- // Is the instruction decoder method able to completely determine if the
- // given instruction is valid or not. If the TableGen definition of the
- // instruction specifies bitpattern A??B where A and B are static bits, the
- // hasCompleteDecoder flag says whether the decoder method fully handles the
- // ?? space, i.e. if it is a final arbiter for the instruction validity.
- // If not then the decoder attempts to continue decoding when the decoder
- // method fails.
- //
- // This allows to handle situations where the encoding is not fully
- // orthogonal. Example:
- // * InstA with bitpattern 0b0000????,
- // * InstB with bitpattern 0b000000?? but the associated decoder method
- // DecodeInstB() returns Fail when ?? is 0b00 or 0b11.
- //
- // The decoder tries to decode a bitpattern that matches both InstA and
- // InstB bitpatterns first as InstB (because it is the most specific
- // encoding). In the default case (hasCompleteDecoder = 1), when
- // DecodeInstB() returns Fail the bitpattern gets rejected. By setting
- // hasCompleteDecoder = 0 in InstB, the decoder is informed that
- // DecodeInstB() is not able to determine if all possible values of ?? are
- // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
- // decode the bitpattern as InstA too.
- bit hasCompleteDecoder = 1;
/// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
bits<64> TSFlags = 0;
@@ -584,6 +602,13 @@
bit FastISelShouldIgnore = 0;
}
+/// Defines an additional encoding that disassembles to the given instruction
+/// Like Instruction, the Inst and SoftFail fields are omitted to allow targets
+// to specify their size.
+class AdditionalEncoding<Instruction I> : InstructionEncoding {
+ Instruction AliasOf = I;
+}
+
/// PseudoInstExpansion - Expansion information for a pseudo-instruction.
/// Which instruction it expands to and how the operands map from the
/// pseudo.
@@ -908,7 +933,7 @@
}
// Standard Pseudo Instructions.
-// This list must match TargetOpcodes.h and CodeGenTarget.cpp.
+// This list must match TargetOpcodes.def.
// Only these instructions are allowed in the TargetOpcode namespace.
// Ensure mayLoad and mayStore have a default value, so as not to break
// targets that set guessInstructionProperties=0. Any local definition of
@@ -1045,7 +1070,7 @@
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "BUNDLE";
- let hasSideEffects = 1;
+ let hasSideEffects = 0;
}
def LIFETIME_START : StandardPseudoInstruction {
let OutOperandList = (outs);
@@ -1182,7 +1207,7 @@
let hasSideEffects = 1;
}
def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction {
- let OutOperandList = (outs unknown:$dst);
+ let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "";
let hasSideEffects = 1;
diff --git a/linux-x64/clang/include/llvm/Target/TargetCallingConv.td b/linux-x64/clang/include/llvm/Target/TargetCallingConv.td
index 11ed4f5..1bc03cf 100644
--- a/linux-x64/clang/include/llvm/Target/TargetCallingConv.td
+++ b/linux-x64/clang/include/llvm/Target/TargetCallingConv.td
@@ -82,6 +82,15 @@
/// CCIfNotVarArg - If the current function is not vararg - apply the action
class CCIfNotVarArg<CCAction A> : CCIf<"!State.isVarArg()", A> {}
+/// CCIfPtrAddrSpace - If the top-level parent of the current argument has
+/// pointer type in the specified address-space.
+class CCIfPtrAddrSpace<int AS, CCAction A>
+ : CCIf<"(ArgFlags.isPointer() && ArgFlags.getPointerAddrSpace() == " # AS # ")", A> {}
+
+/// CCIfPtr - If the top-level parent of the current argument had
+/// pointer type in some address-space.
+class CCIfPtr<CCAction A> : CCIf<"ArgFlags.isPointer()", A> {}
+
/// CCAssignToReg - This action matches if there is a register in the specified
/// list that is still available. If so, it assigns the value to the first
/// available register and succeeds.
diff --git a/linux-x64/clang/include/llvm/Target/TargetLoweringObjectFile.h b/linux-x64/clang/include/llvm/Target/TargetLoweringObjectFile.h
index f96e353..7e094a1 100644
--- a/linux-x64/clang/include/llvm/Target/TargetLoweringObjectFile.h
+++ b/linux-x64/clang/include/llvm/Target/TargetLoweringObjectFile.h
@@ -79,6 +79,9 @@
/// Emit the module-level metadata that the platform cares about.
virtual void emitModuleMetadata(MCStreamer &Streamer, Module &M) const {}
+ /// Get the module-level metadata that the platform cares about.
+ virtual void getModuleMetadata(Module &M) {}
+
/// Given a constant with the SectionKind, return a section that it should be
/// placed in.
virtual MCSection *getSectionForConstant(const DataLayout &DL,
diff --git a/linux-x64/clang/include/llvm/Target/TargetMachine.h b/linux-x64/clang/include/llvm/Target/TargetMachine.h
index 7dd9b99..cdf9f8b 100644
--- a/linux-x64/clang/include/llvm/Target/TargetMachine.h
+++ b/linux-x64/clang/include/llvm/Target/TargetMachine.h
@@ -35,6 +35,9 @@
class MCSymbol;
class raw_pwrite_stream;
class PassManagerBuilder;
+struct PerFunctionMIParsingState;
+class SMDiagnostic;
+class SMRange;
class Target;
class TargetIntrinsicInfo;
class TargetIRAnalysis;
@@ -49,6 +52,10 @@
}
using legacy::PassManagerBase;
+namespace yaml {
+struct MachineFunctionInfo;
+}
+
//===----------------------------------------------------------------------===//
///
/// Primary interface to the complete machine description for the target
@@ -114,6 +121,27 @@
return nullptr;
}
+ /// Allocate and return a default initialized instance of the YAML
+ /// representation for the MachineFunctionInfo.
+ virtual yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const {
+ return nullptr;
+ }
+
+ /// Allocate and initialize an instance of the YAML representation of the
+ /// MachineFunctionInfo.
+ virtual yaml::MachineFunctionInfo *
+ convertFuncInfoToYAML(const MachineFunction &MF) const {
+ return nullptr;
+ }
+
+ /// Parse out the target's MachineFunctionInfo from the YAML reprsentation.
+ virtual bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
+ PerFunctionMIParsingState &PFS,
+ SMDiagnostic &Error,
+ SMRange &SourceRange) const {
+ return false;
+ }
+
/// This method returns a pointer to the specified type of
/// TargetSubtargetInfo. In debug builds, it verifies that the object being
/// returned is of the correct type.
@@ -362,9 +390,9 @@
if (CM) {
// By default, targets do not support the tiny and kernel models.
if (*CM == CodeModel::Tiny)
- report_fatal_error("Target does not support the tiny CodeModel");
+ report_fatal_error("Target does not support the tiny CodeModel", false);
if (*CM == CodeModel::Kernel)
- report_fatal_error("Target does not support the kernel CodeModel");
+ report_fatal_error("Target does not support the kernel CodeModel", false);
return *CM;
}
return Default;
diff --git a/linux-x64/clang/include/llvm/Target/TargetOptions.h b/linux-x64/clang/include/llvm/Target/TargetOptions.h
index 6b76a11..8cc2a60 100644
--- a/linux-x64/clang/include/llvm/Target/TargetOptions.h
+++ b/linux-x64/clang/include/llvm/Target/TargetOptions.h
@@ -118,7 +118,8 @@
NoTrapAfterNoreturn(false), EmulatedTLS(false),
ExplicitEmulatedTLS(false), EnableIPRA(false),
EmitStackSizeSection(false), EnableMachineOutliner(false),
- SupportsDefaultOutlining(false), EmitAddrsig(false) {}
+ SupportsDefaultOutlining(false), EmitAddrsig(false),
+ EnableDebugEntryValues(false) {}
/// PrintMachineCode - This flag is enabled when the -print-machineinstrs
/// option is specified on the command line, and should enable debugging
@@ -252,6 +253,9 @@
/// Emit address-significance table.
unsigned EmitAddrsig : 1;
+ /// Emit debug info about parameter's entry values.
+ unsigned EnableDebugEntryValues : 1;
+
/// FloatABIType - This setting is set by -float-abi=xxx option is specfied
/// on the command line. This setting may either be Default, Soft, or Hard.
/// Default selects the target's default behavior. Soft selects the ABI for
diff --git a/linux-x64/clang/include/llvm/Target/TargetSchedule.td b/linux-x64/clang/include/llvm/Target/TargetSchedule.td
index cbfad5f..a36d259 100644
--- a/linux-x64/clang/include/llvm/Target/TargetSchedule.td
+++ b/linux-x64/clang/include/llvm/Target/TargetSchedule.td
@@ -135,7 +135,7 @@
//
// An optional Super resource may be given to model these resources as
// a subset of the more general super resources. Using one of these
-// resources implies using one of the super resoruces.
+// resources implies using one of the super resources.
//
// ProcResourceUnits normally model a few buffered resources within an
// out-of-order engine. Buffered resources may be held for multiple
diff --git a/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td b/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td
index 174d97a..3b5c767 100644
--- a/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td
+++ b/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td
@@ -391,6 +391,7 @@
def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>;
def smulfix : SDNode<"ISD::SMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>;
+def smulfixsat : SDNode<"ISD::SMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>;
def umulfix : SDNode<"ISD::UMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>;
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
@@ -450,6 +451,11 @@
def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
+def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>;
+def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>;
+def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>;
+def llrint : SDNode<"ISD::LLRINT" , SDTFPToIntOp>;
+
def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
@@ -461,6 +467,53 @@
def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
+def strict_fadd : SDNode<"ISD::STRICT_FADD",
+ SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>;
+def strict_fsub : SDNode<"ISD::STRICT_FSUB",
+ SDTFPBinOp, [SDNPHasChain]>;
+def strict_fmul : SDNode<"ISD::STRICT_FMUL",
+ SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>;
+def strict_fdiv : SDNode<"ISD::STRICT_FDIV",
+ SDTFPBinOp, [SDNPHasChain]>;
+def strict_frem : SDNode<"ISD::STRICT_FREM",
+ SDTFPBinOp, [SDNPHasChain]>;
+def strict_fma : SDNode<"ISD::STRICT_FMA",
+ SDTFPTernaryOp, [SDNPHasChain]>;
+def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_fsin : SDNode<"ISD::STRICT_FSIN",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_fcos : SDNode<"ISD::STRICT_FCOS",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_fpow : SDNode<"ISD::STRICT_FPOW",
+ SDTFPBinOp, [SDNPHasChain]>;
+def strict_flog2 : SDNode<"ISD::STRICT_FLOG2",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_frint : SDNode<"ISD::STRICT_FRINT",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_fnearbyint : SDNode<"ISD::STRICT_FNEARBYINT",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_fceil : SDNode<"ISD::STRICT_FCEIL",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_ffloor : SDNode<"ISD::STRICT_FFLOOR",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_fround : SDNode<"ISD::STRICT_FROUND",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_ftrunc : SDNode<"ISD::STRICT_FTRUNC",
+ SDTFPUnaryOp, [SDNPHasChain]>;
+def strict_fminnum : SDNode<"ISD::STRICT_FMINNUM",
+ SDTFPBinOp, [SDNPHasChain,
+ SDNPCommutative, SDNPAssociative]>;
+def strict_fmaxnum : SDNode<"ISD::STRICT_FMAXNUM",
+ SDTFPBinOp, [SDNPHasChain,
+ SDNPCommutative, SDNPAssociative]>;
+def strict_fpround : SDNode<"ISD::STRICT_FP_ROUND",
+ SDTFPRoundOp, [SDNPHasChain]>;
+def strict_fpextend : SDNode<"ISD::STRICT_FP_EXTEND",
+ SDTFPExtendOp, [SDNPHasChain]>;
+
def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
def select : SDNode<"ISD::SELECT" , SDTSelect>;
def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
@@ -527,9 +580,9 @@
def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
-def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore,
+def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
-def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad,
+def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
@@ -782,14 +835,11 @@
def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
-def immAllOnesV: PatLeaf<(build_vector), [{
- return ISD::isBuildVectorAllOnes(N);
-}]>;
-def immAllZerosV: PatLeaf<(build_vector), [{
- return ISD::isBuildVectorAllZeros(N);
-}]>;
-
-
+// Use ISD::isBuildVectorAllOnes or ISD::isBuildVectorAllZeros to look for
+// the corresponding build_vector. Will look through bitcasts except when used
+// as a pattern root.
+def immAllOnesV; // ISD::isBuildVectorAllOnes
+def immAllZerosV; // ISD::isBuildVectorAllZeros
// Other helper fragments.
def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
@@ -1174,6 +1224,87 @@
def setne : PatFrag<(ops node:$lhs, node:$rhs),
(setcc node:$lhs, node:$rhs, SETNE)>;
+// We don't have strict FP extended loads as single DAG nodes, but we can
+// still provide convenience fragments to match those operations.
+def strict_extloadf32 : PatFrag<(ops node:$ptr),
+ (strict_fpextend (f32 (load node:$ptr)))>;
+def strict_extloadf64 : PatFrag<(ops node:$ptr),
+ (strict_fpextend (f64 (load node:$ptr)))>;
+
+// Convenience fragments to match both strict and non-strict fp operations
+def any_fadd : PatFrags<(ops node:$lhs, node:$rhs),
+ [(strict_fadd node:$lhs, node:$rhs),
+ (fadd node:$lhs, node:$rhs)]>;
+def any_fsub : PatFrags<(ops node:$lhs, node:$rhs),
+ [(strict_fsub node:$lhs, node:$rhs),
+ (fsub node:$lhs, node:$rhs)]>;
+def any_fmul : PatFrags<(ops node:$lhs, node:$rhs),
+ [(strict_fmul node:$lhs, node:$rhs),
+ (fmul node:$lhs, node:$rhs)]>;
+def any_fdiv : PatFrags<(ops node:$lhs, node:$rhs),
+ [(strict_fdiv node:$lhs, node:$rhs),
+ (fdiv node:$lhs, node:$rhs)]>;
+def any_frem : PatFrags<(ops node:$lhs, node:$rhs),
+ [(strict_frem node:$lhs, node:$rhs),
+ (frem node:$lhs, node:$rhs)]>;
+def any_fma : PatFrags<(ops node:$src1, node:$src2, node:$src3),
+ [(strict_fma node:$src1, node:$src2, node:$src3),
+ (fma node:$src1, node:$src2, node:$src3)]>;
+def any_fsqrt : PatFrags<(ops node:$src),
+ [(strict_fsqrt node:$src),
+ (fsqrt node:$src)]>;
+def any_fsin : PatFrags<(ops node:$src),
+ [(strict_fsin node:$src),
+ (fsin node:$src)]>;
+def any_fcos : PatFrags<(ops node:$src),
+ [(strict_fcos node:$src),
+ (fcos node:$src)]>;
+def any_fexp2 : PatFrags<(ops node:$src),
+ [(strict_fexp2 node:$src),
+ (fexp2 node:$src)]>;
+def any_fpow : PatFrags<(ops node:$lhs, node:$rhs),
+ [(strict_fpow node:$lhs, node:$rhs),
+ (fpow node:$lhs, node:$rhs)]>;
+def any_flog2 : PatFrags<(ops node:$src),
+ [(strict_flog2 node:$src),
+ (flog2 node:$src)]>;
+def any_frint : PatFrags<(ops node:$src),
+ [(strict_frint node:$src),
+ (frint node:$src)]>;
+def any_fnearbyint : PatFrags<(ops node:$src),
+ [(strict_fnearbyint node:$src),
+ (fnearbyint node:$src)]>;
+def any_fceil : PatFrags<(ops node:$src),
+ [(strict_fceil node:$src),
+ (fceil node:$src)]>;
+def any_ffloor : PatFrags<(ops node:$src),
+ [(strict_ffloor node:$src),
+ (ffloor node:$src)]>;
+def any_fround : PatFrags<(ops node:$src),
+ [(strict_fround node:$src),
+ (fround node:$src)]>;
+def any_ftrunc : PatFrags<(ops node:$src),
+ [(strict_ftrunc node:$src),
+ (ftrunc node:$src)]>;
+def any_fmaxnum : PatFrags<(ops node:$lhs, node:$rhs),
+ [(strict_fmaxnum node:$lhs, node:$rhs),
+ (fmaxnum node:$lhs, node:$rhs)]>;
+def any_fminnum : PatFrags<(ops node:$lhs, node:$rhs),
+ [(strict_fminnum node:$lhs, node:$rhs),
+ (fminnum node:$lhs, node:$rhs)]>;
+def any_fpround : PatFrags<(ops node:$src),
+ [(strict_fpround node:$src),
+ (fpround node:$src)]>;
+def any_fpextend : PatFrags<(ops node:$src),
+ [(strict_fpextend node:$src),
+ (fpextend node:$src)]>;
+def any_extloadf32 : PatFrags<(ops node:$ptr),
+ [(strict_extloadf32 node:$ptr),
+ (extloadf32 node:$ptr)]>;
+def any_extloadf64 : PatFrags<(ops node:$ptr),
+ [(strict_extloadf64 node:$ptr),
+ (extloadf64 node:$ptr)]>;
+
multiclass binary_atomic_op_ord<SDNode atomic_op> {
def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val),
(!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {